/* * Copyright © 2017 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. */ /* THIS FILE HAS BEEN GENERATED, DO NOT HAND EDIT. * * Sizes of bitfields in genxml instructions, structures, and registers. */ #ifndef GENX_BITS_H #define GENX_BITS_H #include #include "dev/intel_device_info.h" #include "util/macros.h" #ifdef __cplusplus extern "C" { #endif /* 3DPRIMITIVE */ #define GFX125_3DPRIMITIVE_length 7 #define GFX12_3DPRIMITIVE_length 7 #define GFX11_3DPRIMITIVE_length 7 #define GFX9_3DPRIMITIVE_length 7 #define GFX8_3DPRIMITIVE_length 7 #define GFX75_3DPRIMITIVE_length 7 #define GFX7_3DPRIMITIVE_length 7 #define GFX6_3DPRIMITIVE_length 6 #define GFX5_3DPRIMITIVE_length 6 #define GFX45_3DPRIMITIVE_length 6 #define GFX4_3DPRIMITIVE_length 6 static inline uint32_t ATTRIBUTE_PURE _3DPRIMITIVE_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 7; case 120: return 7; case 110: return 7; case 90: return 7; case 80: return 7; case 75: return 7; case 70: return 7; case 60: return 6; case 50: return 6; case 45: return 6; case 40: return 6; default: unreachable("Invalid hardware generation"); } } /* 3DPRIMITIVE::3D Command Opcode */ #define GFX125_3DPRIMITIVE_3DCommandOpcode_bits 3 #define GFX12_3DPRIMITIVE_3DCommandOpcode_bits 3 #define GFX11_3DPRIMITIVE_3DCommandOpcode_bits 3 #define GFX9_3DPRIMITIVE_3DCommandOpcode_bits 3 #define GFX8_3DPRIMITIVE_3DCommandOpcode_bits 3 #define GFX75_3DPRIMITIVE_3DCommandOpcode_bits 3 #define GFX7_3DPRIMITIVE_3DCommandOpcode_bits 3 #define GFX6_3DPRIMITIVE_3DCommandOpcode_bits 3 #define GFX5_3DPRIMITIVE_3DCommandOpcode_bits 3 #define GFX45_3DPRIMITIVE_3DCommandOpcode_bits 3 #define GFX4_3DPRIMITIVE_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DPRIMITIVE_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DPRIMITIVE_3DCommandOpcode_start 24 #define GFX12_3DPRIMITIVE_3DCommandOpcode_start 24 #define GFX11_3DPRIMITIVE_3DCommandOpcode_start 24 #define GFX9_3DPRIMITIVE_3DCommandOpcode_start 24 #define GFX8_3DPRIMITIVE_3DCommandOpcode_start 24 #define GFX75_3DPRIMITIVE_3DCommandOpcode_start 24 #define GFX7_3DPRIMITIVE_3DCommandOpcode_start 24 #define GFX6_3DPRIMITIVE_3DCommandOpcode_start 24 #define GFX5_3DPRIMITIVE_3DCommandOpcode_start 24 #define GFX45_3DPRIMITIVE_3DCommandOpcode_start 24 #define GFX4_3DPRIMITIVE_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DPRIMITIVE_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 24; case 50: return 24; case 45: return 24; case 40: return 24; default: unreachable("Invalid hardware generation"); } } /* 3DPRIMITIVE::3D Command Sub Opcode */ #define GFX125_3DPRIMITIVE_3DCommandSubOpcode_bits 8 #define GFX12_3DPRIMITIVE_3DCommandSubOpcode_bits 8 #define GFX11_3DPRIMITIVE_3DCommandSubOpcode_bits 8 #define GFX9_3DPRIMITIVE_3DCommandSubOpcode_bits 8 #define GFX8_3DPRIMITIVE_3DCommandSubOpcode_bits 8 #define GFX75_3DPRIMITIVE_3DCommandSubOpcode_bits 8 #define GFX7_3DPRIMITIVE_3DCommandSubOpcode_bits 8 #define GFX6_3DPRIMITIVE_3DCommandSubOpcode_bits 8 #define GFX5_3DPRIMITIVE_3DCommandSubOpcode_bits 8 #define GFX45_3DPRIMITIVE_3DCommandSubOpcode_bits 8 #define GFX4_3DPRIMITIVE_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DPRIMITIVE_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 8; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DPRIMITIVE_3DCommandSubOpcode_start 16 #define GFX12_3DPRIMITIVE_3DCommandSubOpcode_start 16 #define GFX11_3DPRIMITIVE_3DCommandSubOpcode_start 16 #define GFX9_3DPRIMITIVE_3DCommandSubOpcode_start 16 #define GFX8_3DPRIMITIVE_3DCommandSubOpcode_start 16 #define GFX75_3DPRIMITIVE_3DCommandSubOpcode_start 16 #define GFX7_3DPRIMITIVE_3DCommandSubOpcode_start 16 #define GFX6_3DPRIMITIVE_3DCommandSubOpcode_start 16 #define GFX5_3DPRIMITIVE_3DCommandSubOpcode_start 16 #define GFX45_3DPRIMITIVE_3DCommandSubOpcode_start 16 #define GFX4_3DPRIMITIVE_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DPRIMITIVE_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 16; case 50: return 16; case 45: return 16; case 40: return 16; default: unreachable("Invalid hardware generation"); } } /* 3DPRIMITIVE::Base Vertex Location */ #define GFX125_3DPRIMITIVE_BaseVertexLocation_bits 32 #define GFX12_3DPRIMITIVE_BaseVertexLocation_bits 32 #define GFX11_3DPRIMITIVE_BaseVertexLocation_bits 32 #define GFX9_3DPRIMITIVE_BaseVertexLocation_bits 32 #define GFX8_3DPRIMITIVE_BaseVertexLocation_bits 32 #define GFX75_3DPRIMITIVE_BaseVertexLocation_bits 32 #define GFX7_3DPRIMITIVE_BaseVertexLocation_bits 32 #define GFX6_3DPRIMITIVE_BaseVertexLocation_bits 32 #define GFX5_3DPRIMITIVE_BaseVertexLocation_bits 32 #define GFX45_3DPRIMITIVE_BaseVertexLocation_bits 32 #define GFX4_3DPRIMITIVE_BaseVertexLocation_bits 32 static inline uint32_t ATTRIBUTE_PURE _3DPRIMITIVE_BaseVertexLocation_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 32; case 50: return 32; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DPRIMITIVE_BaseVertexLocation_start 192 #define GFX12_3DPRIMITIVE_BaseVertexLocation_start 192 #define GFX11_3DPRIMITIVE_BaseVertexLocation_start 192 #define GFX9_3DPRIMITIVE_BaseVertexLocation_start 192 #define GFX8_3DPRIMITIVE_BaseVertexLocation_start 192 #define GFX75_3DPRIMITIVE_BaseVertexLocation_start 192 #define GFX7_3DPRIMITIVE_BaseVertexLocation_start 192 #define GFX6_3DPRIMITIVE_BaseVertexLocation_start 160 #define GFX5_3DPRIMITIVE_BaseVertexLocation_start 160 #define GFX45_3DPRIMITIVE_BaseVertexLocation_start 160 #define GFX4_3DPRIMITIVE_BaseVertexLocation_start 160 static inline uint32_t ATTRIBUTE_PURE _3DPRIMITIVE_BaseVertexLocation_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 192; case 120: return 192; case 110: return 192; case 90: return 192; case 80: return 192; case 75: return 192; case 70: return 192; case 60: return 160; case 50: return 160; case 45: return 160; case 40: return 160; default: unreachable("Invalid hardware generation"); } } /* 3DPRIMITIVE::Command SubType */ #define GFX125_3DPRIMITIVE_CommandSubType_bits 2 #define GFX12_3DPRIMITIVE_CommandSubType_bits 2 #define GFX11_3DPRIMITIVE_CommandSubType_bits 2 #define GFX9_3DPRIMITIVE_CommandSubType_bits 2 #define GFX8_3DPRIMITIVE_CommandSubType_bits 2 #define GFX75_3DPRIMITIVE_CommandSubType_bits 2 #define GFX7_3DPRIMITIVE_CommandSubType_bits 2 #define GFX6_3DPRIMITIVE_CommandSubType_bits 2 #define GFX5_3DPRIMITIVE_CommandSubType_bits 2 #define GFX45_3DPRIMITIVE_CommandSubType_bits 2 #define GFX4_3DPRIMITIVE_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DPRIMITIVE_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 2; case 45: return 2; case 40: return 2; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DPRIMITIVE_CommandSubType_start 27 #define GFX12_3DPRIMITIVE_CommandSubType_start 27 #define GFX11_3DPRIMITIVE_CommandSubType_start 27 #define GFX9_3DPRIMITIVE_CommandSubType_start 27 #define GFX8_3DPRIMITIVE_CommandSubType_start 27 #define GFX75_3DPRIMITIVE_CommandSubType_start 27 #define GFX7_3DPRIMITIVE_CommandSubType_start 27 #define GFX6_3DPRIMITIVE_CommandSubType_start 27 #define GFX5_3DPRIMITIVE_CommandSubType_start 27 #define GFX45_3DPRIMITIVE_CommandSubType_start 27 #define GFX4_3DPRIMITIVE_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DPRIMITIVE_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 27; case 50: return 27; case 45: return 27; case 40: return 27; default: unreachable("Invalid hardware generation"); } } /* 3DPRIMITIVE::Command Type */ #define GFX125_3DPRIMITIVE_CommandType_bits 3 #define GFX12_3DPRIMITIVE_CommandType_bits 3 #define GFX11_3DPRIMITIVE_CommandType_bits 3 #define GFX9_3DPRIMITIVE_CommandType_bits 3 #define GFX8_3DPRIMITIVE_CommandType_bits 3 #define GFX75_3DPRIMITIVE_CommandType_bits 3 #define GFX7_3DPRIMITIVE_CommandType_bits 3 #define GFX6_3DPRIMITIVE_CommandType_bits 3 #define GFX5_3DPRIMITIVE_CommandType_bits 3 #define GFX45_3DPRIMITIVE_CommandType_bits 3 #define GFX4_3DPRIMITIVE_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DPRIMITIVE_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DPRIMITIVE_CommandType_start 29 #define GFX12_3DPRIMITIVE_CommandType_start 29 #define GFX11_3DPRIMITIVE_CommandType_start 29 #define GFX9_3DPRIMITIVE_CommandType_start 29 #define GFX8_3DPRIMITIVE_CommandType_start 29 #define GFX75_3DPRIMITIVE_CommandType_start 29 #define GFX7_3DPRIMITIVE_CommandType_start 29 #define GFX6_3DPRIMITIVE_CommandType_start 29 #define GFX5_3DPRIMITIVE_CommandType_start 29 #define GFX45_3DPRIMITIVE_CommandType_start 29 #define GFX4_3DPRIMITIVE_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DPRIMITIVE_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 29; case 50: return 29; case 45: return 29; case 40: return 29; default: unreachable("Invalid hardware generation"); } } /* 3DPRIMITIVE::DWord Length */ #define GFX125_3DPRIMITIVE_DWordLength_bits 8 #define GFX12_3DPRIMITIVE_DWordLength_bits 8 #define GFX11_3DPRIMITIVE_DWordLength_bits 8 #define GFX9_3DPRIMITIVE_DWordLength_bits 8 #define GFX8_3DPRIMITIVE_DWordLength_bits 8 #define GFX75_3DPRIMITIVE_DWordLength_bits 8 #define GFX7_3DPRIMITIVE_DWordLength_bits 8 #define GFX6_3DPRIMITIVE_DWordLength_bits 8 #define GFX5_3DPRIMITIVE_DWordLength_bits 8 #define GFX45_3DPRIMITIVE_DWordLength_bits 8 #define GFX4_3DPRIMITIVE_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DPRIMITIVE_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 8; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DPRIMITIVE_DWordLength_start 0 #define GFX12_3DPRIMITIVE_DWordLength_start 0 #define GFX11_3DPRIMITIVE_DWordLength_start 0 #define GFX9_3DPRIMITIVE_DWordLength_start 0 #define GFX8_3DPRIMITIVE_DWordLength_start 0 #define GFX75_3DPRIMITIVE_DWordLength_start 0 #define GFX7_3DPRIMITIVE_DWordLength_start 0 #define GFX6_3DPRIMITIVE_DWordLength_start 0 #define GFX5_3DPRIMITIVE_DWordLength_start 0 #define GFX45_3DPRIMITIVE_DWordLength_start 0 #define GFX4_3DPRIMITIVE_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DPRIMITIVE_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DPRIMITIVE::End Offset Enable */ #define GFX125_3DPRIMITIVE_EndOffsetEnable_bits 1 #define GFX12_3DPRIMITIVE_EndOffsetEnable_bits 1 #define GFX11_3DPRIMITIVE_EndOffsetEnable_bits 1 #define GFX9_3DPRIMITIVE_EndOffsetEnable_bits 1 #define GFX8_3DPRIMITIVE_EndOffsetEnable_bits 1 #define GFX75_3DPRIMITIVE_EndOffsetEnable_bits 1 #define GFX7_3DPRIMITIVE_EndOffsetEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DPRIMITIVE_EndOffsetEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DPRIMITIVE_EndOffsetEnable_start 41 #define GFX12_3DPRIMITIVE_EndOffsetEnable_start 41 #define GFX11_3DPRIMITIVE_EndOffsetEnable_start 41 #define GFX9_3DPRIMITIVE_EndOffsetEnable_start 41 #define GFX8_3DPRIMITIVE_EndOffsetEnable_start 41 #define GFX75_3DPRIMITIVE_EndOffsetEnable_start 41 #define GFX7_3DPRIMITIVE_EndOffsetEnable_start 41 static inline uint32_t ATTRIBUTE_PURE _3DPRIMITIVE_EndOffsetEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 41; case 120: return 41; case 110: return 41; case 90: return 41; case 80: return 41; case 75: return 41; case 70: return 41; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DPRIMITIVE::Extended Parameter 0 */ #define GFX125_3DPRIMITIVE_ExtendedParameter0_bits 32 #define GFX12_3DPRIMITIVE_ExtendedParameter0_bits 32 #define GFX11_3DPRIMITIVE_ExtendedParameter0_bits 32 static inline uint32_t ATTRIBUTE_PURE _3DPRIMITIVE_ExtendedParameter0_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DPRIMITIVE_ExtendedParameter0_start 224 #define GFX12_3DPRIMITIVE_ExtendedParameter0_start 224 #define GFX11_3DPRIMITIVE_ExtendedParameter0_start 224 static inline uint32_t ATTRIBUTE_PURE _3DPRIMITIVE_ExtendedParameter0_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 224; case 120: return 224; case 110: return 224; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DPRIMITIVE::Extended Parameter 1 */ #define GFX125_3DPRIMITIVE_ExtendedParameter1_bits 32 #define GFX12_3DPRIMITIVE_ExtendedParameter1_bits 32 #define GFX11_3DPRIMITIVE_ExtendedParameter1_bits 32 static inline uint32_t ATTRIBUTE_PURE _3DPRIMITIVE_ExtendedParameter1_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DPRIMITIVE_ExtendedParameter1_start 256 #define GFX12_3DPRIMITIVE_ExtendedParameter1_start 256 #define GFX11_3DPRIMITIVE_ExtendedParameter1_start 256 static inline uint32_t ATTRIBUTE_PURE _3DPRIMITIVE_ExtendedParameter1_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 256; case 120: return 256; case 110: return 256; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DPRIMITIVE::Extended Parameter 2 */ #define GFX125_3DPRIMITIVE_ExtendedParameter2_bits 32 #define GFX12_3DPRIMITIVE_ExtendedParameter2_bits 32 #define GFX11_3DPRIMITIVE_ExtendedParameter2_bits 32 static inline uint32_t ATTRIBUTE_PURE _3DPRIMITIVE_ExtendedParameter2_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DPRIMITIVE_ExtendedParameter2_start 288 #define GFX12_3DPRIMITIVE_ExtendedParameter2_start 288 #define GFX11_3DPRIMITIVE_ExtendedParameter2_start 288 static inline uint32_t ATTRIBUTE_PURE _3DPRIMITIVE_ExtendedParameter2_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 288; case 120: return 288; case 110: return 288; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DPRIMITIVE::Extended Parameters Present */ #define GFX125_3DPRIMITIVE_ExtendedParametersPresent_bits 1 #define GFX12_3DPRIMITIVE_ExtendedParametersPresent_bits 1 #define GFX11_3DPRIMITIVE_ExtendedParametersPresent_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DPRIMITIVE_ExtendedParametersPresent_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DPRIMITIVE_ExtendedParametersPresent_start 11 #define GFX12_3DPRIMITIVE_ExtendedParametersPresent_start 11 #define GFX11_3DPRIMITIVE_ExtendedParametersPresent_start 11 static inline uint32_t ATTRIBUTE_PURE _3DPRIMITIVE_ExtendedParametersPresent_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 11; case 120: return 11; case 110: return 11; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DPRIMITIVE::Indirect Parameter Enable */ #define GFX125_3DPRIMITIVE_IndirectParameterEnable_bits 1 #define GFX12_3DPRIMITIVE_IndirectParameterEnable_bits 1 #define GFX11_3DPRIMITIVE_IndirectParameterEnable_bits 1 #define GFX9_3DPRIMITIVE_IndirectParameterEnable_bits 1 #define GFX8_3DPRIMITIVE_IndirectParameterEnable_bits 1 #define GFX75_3DPRIMITIVE_IndirectParameterEnable_bits 1 #define GFX7_3DPRIMITIVE_IndirectParameterEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DPRIMITIVE_IndirectParameterEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DPRIMITIVE_IndirectParameterEnable_start 10 #define GFX12_3DPRIMITIVE_IndirectParameterEnable_start 10 #define GFX11_3DPRIMITIVE_IndirectParameterEnable_start 10 #define GFX9_3DPRIMITIVE_IndirectParameterEnable_start 10 #define GFX8_3DPRIMITIVE_IndirectParameterEnable_start 10 #define GFX75_3DPRIMITIVE_IndirectParameterEnable_start 10 #define GFX7_3DPRIMITIVE_IndirectParameterEnable_start 10 static inline uint32_t ATTRIBUTE_PURE _3DPRIMITIVE_IndirectParameterEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 10; case 120: return 10; case 110: return 10; case 90: return 10; case 80: return 10; case 75: return 10; case 70: return 10; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DPRIMITIVE::Indirect Vertex Count */ #define GFX5_3DPRIMITIVE_IndirectVertexCount_bits 1 #define GFX45_3DPRIMITIVE_IndirectVertexCount_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DPRIMITIVE_IndirectVertexCount_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX5_3DPRIMITIVE_IndirectVertexCount_start 9 #define GFX45_3DPRIMITIVE_IndirectVertexCount_start 9 static inline uint32_t ATTRIBUTE_PURE _3DPRIMITIVE_IndirectVertexCount_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 9; case 45: return 9; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DPRIMITIVE::Instance Count */ #define GFX125_3DPRIMITIVE_InstanceCount_bits 32 #define GFX12_3DPRIMITIVE_InstanceCount_bits 32 #define GFX11_3DPRIMITIVE_InstanceCount_bits 32 #define GFX9_3DPRIMITIVE_InstanceCount_bits 32 #define GFX8_3DPRIMITIVE_InstanceCount_bits 32 #define GFX75_3DPRIMITIVE_InstanceCount_bits 32 #define GFX7_3DPRIMITIVE_InstanceCount_bits 32 #define GFX6_3DPRIMITIVE_InstanceCount_bits 32 #define GFX5_3DPRIMITIVE_InstanceCount_bits 32 #define GFX45_3DPRIMITIVE_InstanceCount_bits 32 #define GFX4_3DPRIMITIVE_InstanceCount_bits 32 static inline uint32_t ATTRIBUTE_PURE _3DPRIMITIVE_InstanceCount_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 32; case 50: return 32; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DPRIMITIVE_InstanceCount_start 128 #define GFX12_3DPRIMITIVE_InstanceCount_start 128 #define GFX11_3DPRIMITIVE_InstanceCount_start 128 #define GFX9_3DPRIMITIVE_InstanceCount_start 128 #define GFX8_3DPRIMITIVE_InstanceCount_start 128 #define GFX75_3DPRIMITIVE_InstanceCount_start 128 #define GFX7_3DPRIMITIVE_InstanceCount_start 128 #define GFX6_3DPRIMITIVE_InstanceCount_start 96 #define GFX5_3DPRIMITIVE_InstanceCount_start 96 #define GFX45_3DPRIMITIVE_InstanceCount_start 96 #define GFX4_3DPRIMITIVE_InstanceCount_start 96 static inline uint32_t ATTRIBUTE_PURE _3DPRIMITIVE_InstanceCount_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 128; case 120: return 128; case 110: return 128; case 90: return 128; case 80: return 128; case 75: return 128; case 70: return 128; case 60: return 96; case 50: return 96; case 45: return 96; case 40: return 96; default: unreachable("Invalid hardware generation"); } } /* 3DPRIMITIVE::Internal Vertex Count */ #define GFX6_3DPRIMITIVE_InternalVertexCount_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DPRIMITIVE_InternalVertexCount_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DPRIMITIVE_InternalVertexCount_start 9 static inline uint32_t ATTRIBUTE_PURE _3DPRIMITIVE_InternalVertexCount_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 9; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DPRIMITIVE::Predicate Enable */ #define GFX125_3DPRIMITIVE_PredicateEnable_bits 1 #define GFX12_3DPRIMITIVE_PredicateEnable_bits 1 #define GFX11_3DPRIMITIVE_PredicateEnable_bits 1 #define GFX9_3DPRIMITIVE_PredicateEnable_bits 1 #define GFX8_3DPRIMITIVE_PredicateEnable_bits 1 #define GFX75_3DPRIMITIVE_PredicateEnable_bits 1 #define GFX7_3DPRIMITIVE_PredicateEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DPRIMITIVE_PredicateEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DPRIMITIVE_PredicateEnable_start 8 #define GFX12_3DPRIMITIVE_PredicateEnable_start 8 #define GFX11_3DPRIMITIVE_PredicateEnable_start 8 #define GFX9_3DPRIMITIVE_PredicateEnable_start 8 #define GFX8_3DPRIMITIVE_PredicateEnable_start 8 #define GFX75_3DPRIMITIVE_PredicateEnable_start 8 #define GFX7_3DPRIMITIVE_PredicateEnable_start 8 static inline uint32_t ATTRIBUTE_PURE _3DPRIMITIVE_PredicateEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DPRIMITIVE::Primitive Topology Type */ #define GFX125_3DPRIMITIVE_PrimitiveTopologyType_bits 6 #define GFX12_3DPRIMITIVE_PrimitiveTopologyType_bits 6 #define GFX11_3DPRIMITIVE_PrimitiveTopologyType_bits 6 #define GFX9_3DPRIMITIVE_PrimitiveTopologyType_bits 6 #define GFX8_3DPRIMITIVE_PrimitiveTopologyType_bits 6 #define GFX75_3DPRIMITIVE_PrimitiveTopologyType_bits 6 #define GFX7_3DPRIMITIVE_PrimitiveTopologyType_bits 6 #define GFX6_3DPRIMITIVE_PrimitiveTopologyType_bits 5 #define GFX5_3DPRIMITIVE_PrimitiveTopologyType_bits 5 #define GFX45_3DPRIMITIVE_PrimitiveTopologyType_bits 5 #define GFX4_3DPRIMITIVE_PrimitiveTopologyType_bits 5 static inline uint32_t ATTRIBUTE_PURE _3DPRIMITIVE_PrimitiveTopologyType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 6; case 60: return 5; case 50: return 5; case 45: return 5; case 40: return 5; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DPRIMITIVE_PrimitiveTopologyType_start 32 #define GFX12_3DPRIMITIVE_PrimitiveTopologyType_start 32 #define GFX11_3DPRIMITIVE_PrimitiveTopologyType_start 32 #define GFX9_3DPRIMITIVE_PrimitiveTopologyType_start 32 #define GFX8_3DPRIMITIVE_PrimitiveTopologyType_start 32 #define GFX75_3DPRIMITIVE_PrimitiveTopologyType_start 32 #define GFX7_3DPRIMITIVE_PrimitiveTopologyType_start 32 #define GFX6_3DPRIMITIVE_PrimitiveTopologyType_start 10 #define GFX5_3DPRIMITIVE_PrimitiveTopologyType_start 10 #define GFX45_3DPRIMITIVE_PrimitiveTopologyType_start 10 #define GFX4_3DPRIMITIVE_PrimitiveTopologyType_start 10 static inline uint32_t ATTRIBUTE_PURE _3DPRIMITIVE_PrimitiveTopologyType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 10; case 50: return 10; case 45: return 10; case 40: return 10; default: unreachable("Invalid hardware generation"); } } /* 3DPRIMITIVE::Start Instance Location */ #define GFX125_3DPRIMITIVE_StartInstanceLocation_bits 32 #define GFX12_3DPRIMITIVE_StartInstanceLocation_bits 32 #define GFX11_3DPRIMITIVE_StartInstanceLocation_bits 32 #define GFX9_3DPRIMITIVE_StartInstanceLocation_bits 32 #define GFX8_3DPRIMITIVE_StartInstanceLocation_bits 32 #define GFX75_3DPRIMITIVE_StartInstanceLocation_bits 32 #define GFX7_3DPRIMITIVE_StartInstanceLocation_bits 32 #define GFX6_3DPRIMITIVE_StartInstanceLocation_bits 32 #define GFX5_3DPRIMITIVE_StartInstanceLocation_bits 32 #define GFX45_3DPRIMITIVE_StartInstanceLocation_bits 32 static inline uint32_t ATTRIBUTE_PURE _3DPRIMITIVE_StartInstanceLocation_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 32; case 50: return 32; case 45: return 32; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DPRIMITIVE_StartInstanceLocation_start 160 #define GFX12_3DPRIMITIVE_StartInstanceLocation_start 160 #define GFX11_3DPRIMITIVE_StartInstanceLocation_start 160 #define GFX9_3DPRIMITIVE_StartInstanceLocation_start 160 #define GFX8_3DPRIMITIVE_StartInstanceLocation_start 160 #define GFX75_3DPRIMITIVE_StartInstanceLocation_start 160 #define GFX7_3DPRIMITIVE_StartInstanceLocation_start 160 #define GFX6_3DPRIMITIVE_StartInstanceLocation_start 128 #define GFX5_3DPRIMITIVE_StartInstanceLocation_start 128 #define GFX45_3DPRIMITIVE_StartInstanceLocation_start 128 static inline uint32_t ATTRIBUTE_PURE _3DPRIMITIVE_StartInstanceLocation_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 160; case 120: return 160; case 110: return 160; case 90: return 160; case 80: return 160; case 75: return 160; case 70: return 160; case 60: return 128; case 50: return 128; case 45: return 128; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DPRIMITIVE::Start Vertex Location */ #define GFX125_3DPRIMITIVE_StartVertexLocation_bits 32 #define GFX12_3DPRIMITIVE_StartVertexLocation_bits 32 #define GFX11_3DPRIMITIVE_StartVertexLocation_bits 32 #define GFX9_3DPRIMITIVE_StartVertexLocation_bits 32 #define GFX8_3DPRIMITIVE_StartVertexLocation_bits 32 #define GFX75_3DPRIMITIVE_StartVertexLocation_bits 32 #define GFX7_3DPRIMITIVE_StartVertexLocation_bits 32 #define GFX6_3DPRIMITIVE_StartVertexLocation_bits 32 #define GFX5_3DPRIMITIVE_StartVertexLocation_bits 32 #define GFX45_3DPRIMITIVE_StartVertexLocation_bits 32 #define GFX4_3DPRIMITIVE_StartVertexLocation_bits 32 static inline uint32_t ATTRIBUTE_PURE _3DPRIMITIVE_StartVertexLocation_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 32; case 50: return 32; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DPRIMITIVE_StartVertexLocation_start 96 #define GFX12_3DPRIMITIVE_StartVertexLocation_start 96 #define GFX11_3DPRIMITIVE_StartVertexLocation_start 96 #define GFX9_3DPRIMITIVE_StartVertexLocation_start 96 #define GFX8_3DPRIMITIVE_StartVertexLocation_start 96 #define GFX75_3DPRIMITIVE_StartVertexLocation_start 96 #define GFX7_3DPRIMITIVE_StartVertexLocation_start 96 #define GFX6_3DPRIMITIVE_StartVertexLocation_start 64 #define GFX5_3DPRIMITIVE_StartVertexLocation_start 64 #define GFX45_3DPRIMITIVE_StartVertexLocation_start 64 #define GFX4_3DPRIMITIVE_StartVertexLocation_start 64 static inline uint32_t ATTRIBUTE_PURE _3DPRIMITIVE_StartVertexLocation_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 96; case 120: return 96; case 110: return 96; case 90: return 96; case 80: return 96; case 75: return 96; case 70: return 96; case 60: return 64; case 50: return 64; case 45: return 64; case 40: return 64; default: unreachable("Invalid hardware generation"); } } /* 3DPRIMITIVE::UAV Coherency Required */ #define GFX125_3DPRIMITIVE_UAVCoherencyRequired_bits 1 #define GFX12_3DPRIMITIVE_UAVCoherencyRequired_bits 1 #define GFX11_3DPRIMITIVE_UAVCoherencyRequired_bits 1 #define GFX9_3DPRIMITIVE_UAVCoherencyRequired_bits 1 #define GFX8_3DPRIMITIVE_UAVCoherencyRequired_bits 1 #define GFX75_3DPRIMITIVE_UAVCoherencyRequired_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DPRIMITIVE_UAVCoherencyRequired_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DPRIMITIVE_UAVCoherencyRequired_start 9 #define GFX12_3DPRIMITIVE_UAVCoherencyRequired_start 9 #define GFX11_3DPRIMITIVE_UAVCoherencyRequired_start 9 #define GFX9_3DPRIMITIVE_UAVCoherencyRequired_start 9 #define GFX8_3DPRIMITIVE_UAVCoherencyRequired_start 9 #define GFX75_3DPRIMITIVE_UAVCoherencyRequired_start 9 static inline uint32_t ATTRIBUTE_PURE _3DPRIMITIVE_UAVCoherencyRequired_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 9; case 120: return 9; case 110: return 9; case 90: return 9; case 80: return 9; case 75: return 9; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DPRIMITIVE::Vertex Access Type */ #define GFX125_3DPRIMITIVE_VertexAccessType_bits 1 #define GFX12_3DPRIMITIVE_VertexAccessType_bits 1 #define GFX11_3DPRIMITIVE_VertexAccessType_bits 1 #define GFX9_3DPRIMITIVE_VertexAccessType_bits 1 #define GFX8_3DPRIMITIVE_VertexAccessType_bits 1 #define GFX75_3DPRIMITIVE_VertexAccessType_bits 1 #define GFX7_3DPRIMITIVE_VertexAccessType_bits 1 #define GFX6_3DPRIMITIVE_VertexAccessType_bits 1 #define GFX5_3DPRIMITIVE_VertexAccessType_bits 1 #define GFX45_3DPRIMITIVE_VertexAccessType_bits 1 #define GFX4_3DPRIMITIVE_VertexAccessType_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DPRIMITIVE_VertexAccessType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DPRIMITIVE_VertexAccessType_start 40 #define GFX12_3DPRIMITIVE_VertexAccessType_start 40 #define GFX11_3DPRIMITIVE_VertexAccessType_start 40 #define GFX9_3DPRIMITIVE_VertexAccessType_start 40 #define GFX8_3DPRIMITIVE_VertexAccessType_start 40 #define GFX75_3DPRIMITIVE_VertexAccessType_start 40 #define GFX7_3DPRIMITIVE_VertexAccessType_start 40 #define GFX6_3DPRIMITIVE_VertexAccessType_start 15 #define GFX5_3DPRIMITIVE_VertexAccessType_start 15 #define GFX45_3DPRIMITIVE_VertexAccessType_start 15 #define GFX4_3DPRIMITIVE_VertexAccessType_start 15 static inline uint32_t ATTRIBUTE_PURE _3DPRIMITIVE_VertexAccessType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 40; case 120: return 40; case 110: return 40; case 90: return 40; case 80: return 40; case 75: return 40; case 70: return 40; case 60: return 15; case 50: return 15; case 45: return 15; case 40: return 15; default: unreachable("Invalid hardware generation"); } } /* 3DPRIMITIVE::Vertex Count Per Instance */ #define GFX125_3DPRIMITIVE_VertexCountPerInstance_bits 32 #define GFX12_3DPRIMITIVE_VertexCountPerInstance_bits 32 #define GFX11_3DPRIMITIVE_VertexCountPerInstance_bits 32 #define GFX9_3DPRIMITIVE_VertexCountPerInstance_bits 32 #define GFX8_3DPRIMITIVE_VertexCountPerInstance_bits 32 #define GFX75_3DPRIMITIVE_VertexCountPerInstance_bits 32 #define GFX7_3DPRIMITIVE_VertexCountPerInstance_bits 32 #define GFX6_3DPRIMITIVE_VertexCountPerInstance_bits 32 #define GFX5_3DPRIMITIVE_VertexCountPerInstance_bits 32 #define GFX45_3DPRIMITIVE_VertexCountPerInstance_bits 32 #define GFX4_3DPRIMITIVE_VertexCountPerInstance_bits 32 static inline uint32_t ATTRIBUTE_PURE _3DPRIMITIVE_VertexCountPerInstance_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 32; case 50: return 32; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DPRIMITIVE_VertexCountPerInstance_start 64 #define GFX12_3DPRIMITIVE_VertexCountPerInstance_start 64 #define GFX11_3DPRIMITIVE_VertexCountPerInstance_start 64 #define GFX9_3DPRIMITIVE_VertexCountPerInstance_start 64 #define GFX8_3DPRIMITIVE_VertexCountPerInstance_start 64 #define GFX75_3DPRIMITIVE_VertexCountPerInstance_start 64 #define GFX7_3DPRIMITIVE_VertexCountPerInstance_start 64 #define GFX6_3DPRIMITIVE_VertexCountPerInstance_start 32 #define GFX5_3DPRIMITIVE_VertexCountPerInstance_start 32 #define GFX45_3DPRIMITIVE_VertexCountPerInstance_start 32 #define GFX4_3DPRIMITIVE_VertexCountPerInstance_start 32 static inline uint32_t ATTRIBUTE_PURE _3DPRIMITIVE_VertexCountPerInstance_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 64; case 80: return 64; case 75: return 64; case 70: return 64; case 60: return 32; case 50: return 32; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_3D_MODE */ #define GFX125_3DSTATE_3D_MODE_length 2 #define GFX12_3DSTATE_3D_MODE_length 2 #define GFX11_3DSTATE_3D_MODE_length 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_3D_MODE_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_3D_MODE::3D Command Opcode */ #define GFX125_3DSTATE_3D_MODE_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_3D_MODE_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_3D_MODE_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_3D_MODE_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_3D_MODE_3DCommandOpcode_start 24 #define GFX12_3DSTATE_3D_MODE_3DCommandOpcode_start 24 #define GFX11_3DSTATE_3D_MODE_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_3D_MODE_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_3D_MODE::3D Command Sub Opcode */ #define GFX125_3DSTATE_3D_MODE_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_3D_MODE_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_3D_MODE_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_3D_MODE_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_3D_MODE_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_3D_MODE_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_3D_MODE_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_3D_MODE_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_3D_MODE::3D Scoreboard Hashing Mode */ #define GFX125_3DSTATE_3D_MODE_3DScoreboardHashingMode_bits 1 #define GFX12_3DSTATE_3D_MODE_3DScoreboardHashingMode_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_3D_MODE_3DScoreboardHashingMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_3D_MODE_3DScoreboardHashingMode_start 36 #define GFX12_3DSTATE_3D_MODE_3DScoreboardHashingMode_start 36 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_3D_MODE_3DScoreboardHashingMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 36; case 120: return 36; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_3D_MODE::3D Scoreboard Hashing Mode Mask */ #define GFX125_3DSTATE_3D_MODE_3DScoreboardHashingModeMask_bits 1 #define GFX12_3DSTATE_3D_MODE_3DScoreboardHashingModeMask_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_3D_MODE_3DScoreboardHashingModeMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_3D_MODE_3DScoreboardHashingModeMask_start 52 #define GFX12_3DSTATE_3D_MODE_3DScoreboardHashingModeMask_start 52 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_3D_MODE_3DScoreboardHashingModeMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 52; case 120: return 52; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_3D_MODE::Command SubType */ #define GFX125_3DSTATE_3D_MODE_CommandSubType_bits 2 #define GFX12_3DSTATE_3D_MODE_CommandSubType_bits 2 #define GFX11_3DSTATE_3D_MODE_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_3D_MODE_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_3D_MODE_CommandSubType_start 27 #define GFX12_3DSTATE_3D_MODE_CommandSubType_start 27 #define GFX11_3DSTATE_3D_MODE_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_3D_MODE_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_3D_MODE::Command Type */ #define GFX125_3DSTATE_3D_MODE_CommandType_bits 3 #define GFX12_3DSTATE_3D_MODE_CommandType_bits 3 #define GFX11_3DSTATE_3D_MODE_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_3D_MODE_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_3D_MODE_CommandType_start 29 #define GFX12_3DSTATE_3D_MODE_CommandType_start 29 #define GFX11_3DSTATE_3D_MODE_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_3D_MODE_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_3D_MODE::Cross Slice Hashing Mode */ #define GFX125_3DSTATE_3D_MODE_CrossSliceHashingMode_bits 2 #define GFX12_3DSTATE_3D_MODE_CrossSliceHashingMode_bits 2 #define GFX11_3DSTATE_3D_MODE_CrossSliceHashingMode_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_3D_MODE_CrossSliceHashingMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_3D_MODE_CrossSliceHashingMode_start 32 #define GFX12_3DSTATE_3D_MODE_CrossSliceHashingMode_start 32 #define GFX11_3DSTATE_3D_MODE_CrossSliceHashingMode_start 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_3D_MODE_CrossSliceHashingMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_3D_MODE::Cross Slice Hashing Mode Mask */ #define GFX125_3DSTATE_3D_MODE_CrossSliceHashingModeMask_bits 2 #define GFX12_3DSTATE_3D_MODE_CrossSliceHashingModeMask_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_3D_MODE_CrossSliceHashingModeMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_3D_MODE_CrossSliceHashingModeMask_start 48 #define GFX12_3DSTATE_3D_MODE_CrossSliceHashingModeMask_start 48 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_3D_MODE_CrossSliceHashingModeMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 48; case 120: return 48; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_3D_MODE::DWord Length */ #define GFX125_3DSTATE_3D_MODE_DWordLength_bits 8 #define GFX12_3DSTATE_3D_MODE_DWordLength_bits 8 #define GFX11_3DSTATE_3D_MODE_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_3D_MODE_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_3D_MODE_DWordLength_start 0 #define GFX12_3DSTATE_3D_MODE_DWordLength_start 0 #define GFX11_3DSTATE_3D_MODE_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_3D_MODE_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_3D_MODE::Mask */ #define GFX11_3DSTATE_3D_MODE_Mask_bits 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_3D_MODE_Mask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 16; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX11_3DSTATE_3D_MODE_Mask_start 48 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_3D_MODE_Mask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 48; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_3D_MODE::Slice Hashing Table Enable */ #define GFX125_3DSTATE_3D_MODE_SliceHashingTableEnable_bits 1 #define GFX12_3DSTATE_3D_MODE_SliceHashingTableEnable_bits 1 #define GFX11_3DSTATE_3D_MODE_SliceHashingTableEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_3D_MODE_SliceHashingTableEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_3D_MODE_SliceHashingTableEnable_start 38 #define GFX12_3DSTATE_3D_MODE_SliceHashingTableEnable_start 38 #define GFX11_3DSTATE_3D_MODE_SliceHashingTableEnable_start 38 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_3D_MODE_SliceHashingTableEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 38; case 120: return 38; case 110: return 38; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_3D_MODE::Slice Hashing Table Enable Mask */ #define GFX125_3DSTATE_3D_MODE_SliceHashingTableEnableMask_bits 1 #define GFX12_3DSTATE_3D_MODE_SliceHashingTableEnableMask_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_3D_MODE_SliceHashingTableEnableMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_3D_MODE_SliceHashingTableEnableMask_start 54 #define GFX12_3DSTATE_3D_MODE_SliceHashingTableEnableMask_start 54 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_3D_MODE_SliceHashingTableEnableMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 54; case 120: return 54; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_3D_MODE::Subslice Hashing Mode */ #define GFX11_3DSTATE_3D_MODE_SubsliceHashingMode_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_3D_MODE_SubsliceHashingMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 2; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX11_3DSTATE_3D_MODE_SubsliceHashingMode_start 34 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_3D_MODE_SubsliceHashingMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 34; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_3D_MODE::Subslice Hashing Table Enable */ #define GFX125_3DSTATE_3D_MODE_SubsliceHashingTableEnable_bits 1 #define GFX12_3DSTATE_3D_MODE_SubsliceHashingTableEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_3D_MODE_SubsliceHashingTableEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_3D_MODE_SubsliceHashingTableEnable_start 37 #define GFX12_3DSTATE_3D_MODE_SubsliceHashingTableEnable_start 37 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_3D_MODE_SubsliceHashingTableEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 37; case 120: return 37; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_3D_MODE::Subslice Hashing Table Enable Mask */ #define GFX125_3DSTATE_3D_MODE_SubsliceHashingTableEnableMask_bits 1 #define GFX12_3DSTATE_3D_MODE_SubsliceHashingTableEnableMask_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_3D_MODE_SubsliceHashingTableEnableMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_3D_MODE_SubsliceHashingTableEnableMask_start 53 #define GFX12_3DSTATE_3D_MODE_SubsliceHashingTableEnableMask_start 53 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_3D_MODE_SubsliceHashingTableEnableMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 53; case 120: return 53; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_AA_LINE_PARAMETERS */ #define GFX125_3DSTATE_AA_LINE_PARAMETERS_length 3 #define GFX12_3DSTATE_AA_LINE_PARAMETERS_length 3 #define GFX11_3DSTATE_AA_LINE_PARAMETERS_length 3 #define GFX9_3DSTATE_AA_LINE_PARAMETERS_length 3 #define GFX8_3DSTATE_AA_LINE_PARAMETERS_length 3 #define GFX75_3DSTATE_AA_LINE_PARAMETERS_length 3 #define GFX7_3DSTATE_AA_LINE_PARAMETERS_length 3 #define GFX6_3DSTATE_AA_LINE_PARAMETERS_length 3 #define GFX5_3DSTATE_AA_LINE_PARAMETERS_length 3 #define GFX45_3DSTATE_AA_LINE_PARAMETERS_length 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_AA_LINE_PARAMETERS_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 3; case 45: return 3; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_AA_LINE_PARAMETERS::3D Command Opcode */ #define GFX125_3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_bits 3 #define GFX75_3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_bits 3 #define GFX7_3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_bits 3 #define GFX6_3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_bits 3 #define GFX5_3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_bits 3 #define GFX45_3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 3; case 45: return 3; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_start 24 #define GFX12_3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_start 24 #define GFX11_3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_start 24 #define GFX9_3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_start 24 #define GFX8_3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_start 24 #define GFX75_3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_start 24 #define GFX7_3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_start 24 #define GFX6_3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_start 24 #define GFX5_3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_start 24 #define GFX45_3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 24; case 50: return 24; case 45: return 24; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_AA_LINE_PARAMETERS::3D Command Sub Opcode */ #define GFX125_3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_bits 8 #define GFX75_3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_bits 8 #define GFX7_3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_bits 8 #define GFX6_3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_bits 8 #define GFX5_3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_bits 8 #define GFX45_3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 8; case 45: return 8; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_start 16 #define GFX75_3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_start 16 #define GFX7_3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_start 16 #define GFX6_3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_start 16 #define GFX5_3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_start 16 #define GFX45_3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 16; case 50: return 16; case 45: return 16; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_AA_LINE_PARAMETERS::AA Coverage Bias */ #define GFX125_3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_bits 8 #define GFX12_3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_bits 8 #define GFX11_3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_bits 8 #define GFX9_3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_bits 8 #define GFX8_3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_bits 8 #define GFX75_3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_bits 8 #define GFX7_3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_bits 8 #define GFX6_3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_bits 8 #define GFX5_3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_bits 8 #define GFX45_3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 8; case 45: return 8; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_start 48 #define GFX12_3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_start 48 #define GFX11_3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_start 48 #define GFX9_3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_start 48 #define GFX8_3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_start 48 #define GFX75_3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_start 48 #define GFX7_3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_start 48 #define GFX6_3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_start 48 #define GFX5_3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_start 48 #define GFX45_3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_start 48 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 48; case 120: return 48; case 110: return 48; case 90: return 48; case 80: return 48; case 75: return 48; case 70: return 48; case 60: return 48; case 50: return 48; case 45: return 48; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_AA_LINE_PARAMETERS::AA Coverage EndCap Bias */ #define GFX125_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_bits 8 #define GFX12_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_bits 8 #define GFX11_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_bits 8 #define GFX9_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_bits 8 #define GFX8_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_bits 8 #define GFX75_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_bits 8 #define GFX7_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_bits 8 #define GFX6_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_bits 8 #define GFX5_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_bits 8 #define GFX45_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 8; case 45: return 8; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_start 80 #define GFX12_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_start 80 #define GFX11_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_start 80 #define GFX9_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_start 80 #define GFX8_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_start 80 #define GFX75_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_start 80 #define GFX7_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_start 80 #define GFX6_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_start 80 #define GFX5_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_start 80 #define GFX45_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_start 80 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 80; case 120: return 80; case 110: return 80; case 90: return 80; case 80: return 80; case 75: return 80; case 70: return 80; case 60: return 80; case 50: return 80; case 45: return 80; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_AA_LINE_PARAMETERS::AA Coverage EndCap Slope */ #define GFX125_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_bits 8 #define GFX12_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_bits 8 #define GFX11_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_bits 8 #define GFX9_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_bits 8 #define GFX8_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_bits 8 #define GFX75_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_bits 8 #define GFX7_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_bits 8 #define GFX6_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_bits 8 #define GFX5_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_bits 8 #define GFX45_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 8; case 45: return 8; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_start 64 #define GFX12_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_start 64 #define GFX11_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_start 64 #define GFX9_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_start 64 #define GFX8_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_start 64 #define GFX75_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_start 64 #define GFX7_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_start 64 #define GFX6_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_start 64 #define GFX5_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_start 64 #define GFX45_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_start 64 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 64; case 80: return 64; case 75: return 64; case 70: return 64; case 60: return 64; case 50: return 64; case 45: return 64; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_AA_LINE_PARAMETERS::AA Coverage Slope */ #define GFX125_3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_bits 8 #define GFX12_3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_bits 8 #define GFX11_3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_bits 8 #define GFX9_3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_bits 8 #define GFX8_3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_bits 8 #define GFX75_3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_bits 8 #define GFX7_3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_bits 8 #define GFX6_3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_bits 8 #define GFX5_3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_bits 8 #define GFX45_3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 8; case 45: return 8; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_start 32 #define GFX12_3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_start 32 #define GFX11_3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_start 32 #define GFX9_3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_start 32 #define GFX8_3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_start 32 #define GFX75_3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_start 32 #define GFX7_3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_start 32 #define GFX6_3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_start 32 #define GFX5_3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_start 32 #define GFX45_3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_start 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 32; case 50: return 32; case 45: return 32; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_AA_LINE_PARAMETERS::AA Point Coverage Bias */ #define GFX125_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageBias_bits 8 #define GFX12_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageBias_bits 8 #define GFX11_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageBias_bits 8 #define GFX9_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageBias_bits 8 #define GFX8_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageBias_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageBias_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageBias_start 56 #define GFX12_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageBias_start 56 #define GFX11_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageBias_start 56 #define GFX9_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageBias_start 56 #define GFX8_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageBias_start 56 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageBias_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 56; case 120: return 56; case 110: return 56; case 90: return 56; case 80: return 56; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_AA_LINE_PARAMETERS::AA Point Coverage EndCap Bias */ #define GFX125_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapBias_bits 8 #define GFX12_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapBias_bits 8 #define GFX11_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapBias_bits 8 #define GFX9_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapBias_bits 8 #define GFX8_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapBias_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapBias_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapBias_start 88 #define GFX12_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapBias_start 88 #define GFX11_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapBias_start 88 #define GFX9_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapBias_start 88 #define GFX8_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapBias_start 88 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapBias_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 88; case 120: return 88; case 110: return 88; case 90: return 88; case 80: return 88; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_AA_LINE_PARAMETERS::AA Point Coverage EndCap Slope */ #define GFX125_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapSlope_bits 8 #define GFX12_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapSlope_bits 8 #define GFX11_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapSlope_bits 8 #define GFX9_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapSlope_bits 8 #define GFX8_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapSlope_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapSlope_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapSlope_start 72 #define GFX12_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapSlope_start 72 #define GFX11_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapSlope_start 72 #define GFX9_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapSlope_start 72 #define GFX8_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapSlope_start 72 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapSlope_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 72; case 120: return 72; case 110: return 72; case 90: return 72; case 80: return 72; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_AA_LINE_PARAMETERS::AA Point Coverage Slope */ #define GFX125_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageSlope_bits 8 #define GFX12_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageSlope_bits 8 #define GFX11_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageSlope_bits 8 #define GFX9_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageSlope_bits 8 #define GFX8_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageSlope_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageSlope_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageSlope_start 40 #define GFX12_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageSlope_start 40 #define GFX11_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageSlope_start 40 #define GFX9_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageSlope_start 40 #define GFX8_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageSlope_start 40 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageSlope_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 40; case 120: return 40; case 110: return 40; case 90: return 40; case 80: return 40; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_AA_LINE_PARAMETERS::Command SubType */ #define GFX125_3DSTATE_AA_LINE_PARAMETERS_CommandSubType_bits 2 #define GFX12_3DSTATE_AA_LINE_PARAMETERS_CommandSubType_bits 2 #define GFX11_3DSTATE_AA_LINE_PARAMETERS_CommandSubType_bits 2 #define GFX9_3DSTATE_AA_LINE_PARAMETERS_CommandSubType_bits 2 #define GFX8_3DSTATE_AA_LINE_PARAMETERS_CommandSubType_bits 2 #define GFX75_3DSTATE_AA_LINE_PARAMETERS_CommandSubType_bits 2 #define GFX7_3DSTATE_AA_LINE_PARAMETERS_CommandSubType_bits 2 #define GFX6_3DSTATE_AA_LINE_PARAMETERS_CommandSubType_bits 2 #define GFX5_3DSTATE_AA_LINE_PARAMETERS_CommandSubType_bits 2 #define GFX45_3DSTATE_AA_LINE_PARAMETERS_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_AA_LINE_PARAMETERS_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 2; case 45: return 2; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_AA_LINE_PARAMETERS_CommandSubType_start 27 #define GFX12_3DSTATE_AA_LINE_PARAMETERS_CommandSubType_start 27 #define GFX11_3DSTATE_AA_LINE_PARAMETERS_CommandSubType_start 27 #define GFX9_3DSTATE_AA_LINE_PARAMETERS_CommandSubType_start 27 #define GFX8_3DSTATE_AA_LINE_PARAMETERS_CommandSubType_start 27 #define GFX75_3DSTATE_AA_LINE_PARAMETERS_CommandSubType_start 27 #define GFX7_3DSTATE_AA_LINE_PARAMETERS_CommandSubType_start 27 #define GFX6_3DSTATE_AA_LINE_PARAMETERS_CommandSubType_start 27 #define GFX5_3DSTATE_AA_LINE_PARAMETERS_CommandSubType_start 27 #define GFX45_3DSTATE_AA_LINE_PARAMETERS_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_AA_LINE_PARAMETERS_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 27; case 50: return 27; case 45: return 27; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_AA_LINE_PARAMETERS::Command Type */ #define GFX125_3DSTATE_AA_LINE_PARAMETERS_CommandType_bits 3 #define GFX12_3DSTATE_AA_LINE_PARAMETERS_CommandType_bits 3 #define GFX11_3DSTATE_AA_LINE_PARAMETERS_CommandType_bits 3 #define GFX9_3DSTATE_AA_LINE_PARAMETERS_CommandType_bits 3 #define GFX8_3DSTATE_AA_LINE_PARAMETERS_CommandType_bits 3 #define GFX75_3DSTATE_AA_LINE_PARAMETERS_CommandType_bits 3 #define GFX7_3DSTATE_AA_LINE_PARAMETERS_CommandType_bits 3 #define GFX6_3DSTATE_AA_LINE_PARAMETERS_CommandType_bits 3 #define GFX5_3DSTATE_AA_LINE_PARAMETERS_CommandType_bits 3 #define GFX45_3DSTATE_AA_LINE_PARAMETERS_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_AA_LINE_PARAMETERS_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 3; case 45: return 3; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_AA_LINE_PARAMETERS_CommandType_start 29 #define GFX12_3DSTATE_AA_LINE_PARAMETERS_CommandType_start 29 #define GFX11_3DSTATE_AA_LINE_PARAMETERS_CommandType_start 29 #define GFX9_3DSTATE_AA_LINE_PARAMETERS_CommandType_start 29 #define GFX8_3DSTATE_AA_LINE_PARAMETERS_CommandType_start 29 #define GFX75_3DSTATE_AA_LINE_PARAMETERS_CommandType_start 29 #define GFX7_3DSTATE_AA_LINE_PARAMETERS_CommandType_start 29 #define GFX6_3DSTATE_AA_LINE_PARAMETERS_CommandType_start 29 #define GFX5_3DSTATE_AA_LINE_PARAMETERS_CommandType_start 29 #define GFX45_3DSTATE_AA_LINE_PARAMETERS_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_AA_LINE_PARAMETERS_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 29; case 50: return 29; case 45: return 29; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_AA_LINE_PARAMETERS::DWord Length */ #define GFX125_3DSTATE_AA_LINE_PARAMETERS_DWordLength_bits 8 #define GFX12_3DSTATE_AA_LINE_PARAMETERS_DWordLength_bits 8 #define GFX11_3DSTATE_AA_LINE_PARAMETERS_DWordLength_bits 8 #define GFX9_3DSTATE_AA_LINE_PARAMETERS_DWordLength_bits 8 #define GFX8_3DSTATE_AA_LINE_PARAMETERS_DWordLength_bits 8 #define GFX75_3DSTATE_AA_LINE_PARAMETERS_DWordLength_bits 8 #define GFX7_3DSTATE_AA_LINE_PARAMETERS_DWordLength_bits 8 #define GFX6_3DSTATE_AA_LINE_PARAMETERS_DWordLength_bits 8 #define GFX5_3DSTATE_AA_LINE_PARAMETERS_DWordLength_bits 8 #define GFX45_3DSTATE_AA_LINE_PARAMETERS_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_AA_LINE_PARAMETERS_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 8; case 45: return 8; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_AA_LINE_PARAMETERS_DWordLength_start 0 #define GFX12_3DSTATE_AA_LINE_PARAMETERS_DWordLength_start 0 #define GFX11_3DSTATE_AA_LINE_PARAMETERS_DWordLength_start 0 #define GFX9_3DSTATE_AA_LINE_PARAMETERS_DWordLength_start 0 #define GFX8_3DSTATE_AA_LINE_PARAMETERS_DWordLength_start 0 #define GFX75_3DSTATE_AA_LINE_PARAMETERS_DWordLength_start 0 #define GFX7_3DSTATE_AA_LINE_PARAMETERS_DWordLength_start 0 #define GFX6_3DSTATE_AA_LINE_PARAMETERS_DWordLength_start 0 #define GFX5_3DSTATE_AA_LINE_PARAMETERS_DWordLength_start 0 #define GFX45_3DSTATE_AA_LINE_PARAMETERS_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_AA_LINE_PARAMETERS_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_EDIT_DS */ /* 3DSTATE_BINDING_TABLE_EDIT_DS::3D Command Opcode */ #define GFX125_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandOpcode_bits 3 #define GFX75_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandOpcode_start 24 #define GFX12_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandOpcode_start 24 #define GFX11_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandOpcode_start 24 #define GFX9_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandOpcode_start 24 #define GFX8_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandOpcode_start 24 #define GFX75_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_EDIT_DS::3D Command Sub Opcode */ #define GFX125_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandSubOpcode_bits 8 #define GFX75_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandSubOpcode_start 16 #define GFX75_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_EDIT_DS::Binding Table Block Clear */ #define GFX125_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableBlockClear_bits 16 #define GFX12_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableBlockClear_bits 16 #define GFX11_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableBlockClear_bits 16 #define GFX9_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableBlockClear_bits 16 #define GFX8_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableBlockClear_bits 16 #define GFX75_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableBlockClear_bits 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableBlockClear_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableBlockClear_start 48 #define GFX12_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableBlockClear_start 48 #define GFX11_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableBlockClear_start 48 #define GFX9_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableBlockClear_start 48 #define GFX8_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableBlockClear_start 48 #define GFX75_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableBlockClear_start 48 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableBlockClear_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 48; case 120: return 48; case 110: return 48; case 90: return 48; case 80: return 48; case 75: return 48; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_EDIT_DS::Binding Table Edit Target */ #define GFX125_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableEditTarget_bits 2 #define GFX12_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableEditTarget_bits 2 #define GFX11_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableEditTarget_bits 2 #define GFX9_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableEditTarget_bits 2 #define GFX8_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableEditTarget_bits 2 #define GFX75_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableEditTarget_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableEditTarget_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableEditTarget_start 32 #define GFX12_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableEditTarget_start 32 #define GFX11_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableEditTarget_start 32 #define GFX9_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableEditTarget_start 32 #define GFX8_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableEditTarget_start 32 #define GFX75_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableEditTarget_start 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableEditTarget_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_EDIT_DS::Command SubType */ #define GFX125_3DSTATE_BINDING_TABLE_EDIT_DS_CommandSubType_bits 2 #define GFX12_3DSTATE_BINDING_TABLE_EDIT_DS_CommandSubType_bits 2 #define GFX11_3DSTATE_BINDING_TABLE_EDIT_DS_CommandSubType_bits 2 #define GFX9_3DSTATE_BINDING_TABLE_EDIT_DS_CommandSubType_bits 2 #define GFX8_3DSTATE_BINDING_TABLE_EDIT_DS_CommandSubType_bits 2 #define GFX75_3DSTATE_BINDING_TABLE_EDIT_DS_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_EDIT_DS_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BINDING_TABLE_EDIT_DS_CommandSubType_start 27 #define GFX12_3DSTATE_BINDING_TABLE_EDIT_DS_CommandSubType_start 27 #define GFX11_3DSTATE_BINDING_TABLE_EDIT_DS_CommandSubType_start 27 #define GFX9_3DSTATE_BINDING_TABLE_EDIT_DS_CommandSubType_start 27 #define GFX8_3DSTATE_BINDING_TABLE_EDIT_DS_CommandSubType_start 27 #define GFX75_3DSTATE_BINDING_TABLE_EDIT_DS_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_EDIT_DS_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_EDIT_DS::Command Type */ #define GFX125_3DSTATE_BINDING_TABLE_EDIT_DS_CommandType_bits 3 #define GFX12_3DSTATE_BINDING_TABLE_EDIT_DS_CommandType_bits 3 #define GFX11_3DSTATE_BINDING_TABLE_EDIT_DS_CommandType_bits 3 #define GFX9_3DSTATE_BINDING_TABLE_EDIT_DS_CommandType_bits 3 #define GFX8_3DSTATE_BINDING_TABLE_EDIT_DS_CommandType_bits 3 #define GFX75_3DSTATE_BINDING_TABLE_EDIT_DS_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_EDIT_DS_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BINDING_TABLE_EDIT_DS_CommandType_start 29 #define GFX12_3DSTATE_BINDING_TABLE_EDIT_DS_CommandType_start 29 #define GFX11_3DSTATE_BINDING_TABLE_EDIT_DS_CommandType_start 29 #define GFX9_3DSTATE_BINDING_TABLE_EDIT_DS_CommandType_start 29 #define GFX8_3DSTATE_BINDING_TABLE_EDIT_DS_CommandType_start 29 #define GFX75_3DSTATE_BINDING_TABLE_EDIT_DS_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_EDIT_DS_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_EDIT_DS::DWord Length */ #define GFX125_3DSTATE_BINDING_TABLE_EDIT_DS_DWordLength_bits 9 #define GFX12_3DSTATE_BINDING_TABLE_EDIT_DS_DWordLength_bits 9 #define GFX11_3DSTATE_BINDING_TABLE_EDIT_DS_DWordLength_bits 9 #define GFX9_3DSTATE_BINDING_TABLE_EDIT_DS_DWordLength_bits 9 #define GFX8_3DSTATE_BINDING_TABLE_EDIT_DS_DWordLength_bits 9 #define GFX75_3DSTATE_BINDING_TABLE_EDIT_DS_DWordLength_bits 9 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_EDIT_DS_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 9; case 120: return 9; case 110: return 9; case 90: return 9; case 80: return 9; case 75: return 9; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BINDING_TABLE_EDIT_DS_DWordLength_start 0 #define GFX12_3DSTATE_BINDING_TABLE_EDIT_DS_DWordLength_start 0 #define GFX11_3DSTATE_BINDING_TABLE_EDIT_DS_DWordLength_start 0 #define GFX9_3DSTATE_BINDING_TABLE_EDIT_DS_DWordLength_start 0 #define GFX8_3DSTATE_BINDING_TABLE_EDIT_DS_DWordLength_start 0 #define GFX75_3DSTATE_BINDING_TABLE_EDIT_DS_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_EDIT_DS_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_EDIT_GS */ /* 3DSTATE_BINDING_TABLE_EDIT_GS::3D Command Opcode */ #define GFX125_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandOpcode_bits 3 #define GFX75_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandOpcode_start 24 #define GFX12_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandOpcode_start 24 #define GFX11_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandOpcode_start 24 #define GFX9_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandOpcode_start 24 #define GFX8_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandOpcode_start 24 #define GFX75_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_EDIT_GS::3D Command Sub Opcode */ #define GFX125_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandSubOpcode_bits 8 #define GFX75_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandSubOpcode_start 16 #define GFX75_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_EDIT_GS::Binding Table Block Clear */ #define GFX125_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableBlockClear_bits 16 #define GFX12_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableBlockClear_bits 16 #define GFX11_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableBlockClear_bits 16 #define GFX9_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableBlockClear_bits 16 #define GFX8_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableBlockClear_bits 16 #define GFX75_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableBlockClear_bits 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableBlockClear_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableBlockClear_start 48 #define GFX12_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableBlockClear_start 48 #define GFX11_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableBlockClear_start 48 #define GFX9_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableBlockClear_start 48 #define GFX8_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableBlockClear_start 48 #define GFX75_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableBlockClear_start 48 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableBlockClear_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 48; case 120: return 48; case 110: return 48; case 90: return 48; case 80: return 48; case 75: return 48; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_EDIT_GS::Binding Table Edit Target */ #define GFX125_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableEditTarget_bits 2 #define GFX12_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableEditTarget_bits 2 #define GFX11_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableEditTarget_bits 2 #define GFX9_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableEditTarget_bits 2 #define GFX8_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableEditTarget_bits 2 #define GFX75_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableEditTarget_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableEditTarget_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableEditTarget_start 32 #define GFX12_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableEditTarget_start 32 #define GFX11_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableEditTarget_start 32 #define GFX9_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableEditTarget_start 32 #define GFX8_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableEditTarget_start 32 #define GFX75_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableEditTarget_start 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableEditTarget_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_EDIT_GS::Command SubType */ #define GFX125_3DSTATE_BINDING_TABLE_EDIT_GS_CommandSubType_bits 2 #define GFX12_3DSTATE_BINDING_TABLE_EDIT_GS_CommandSubType_bits 2 #define GFX11_3DSTATE_BINDING_TABLE_EDIT_GS_CommandSubType_bits 2 #define GFX9_3DSTATE_BINDING_TABLE_EDIT_GS_CommandSubType_bits 2 #define GFX8_3DSTATE_BINDING_TABLE_EDIT_GS_CommandSubType_bits 2 #define GFX75_3DSTATE_BINDING_TABLE_EDIT_GS_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_EDIT_GS_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BINDING_TABLE_EDIT_GS_CommandSubType_start 27 #define GFX12_3DSTATE_BINDING_TABLE_EDIT_GS_CommandSubType_start 27 #define GFX11_3DSTATE_BINDING_TABLE_EDIT_GS_CommandSubType_start 27 #define GFX9_3DSTATE_BINDING_TABLE_EDIT_GS_CommandSubType_start 27 #define GFX8_3DSTATE_BINDING_TABLE_EDIT_GS_CommandSubType_start 27 #define GFX75_3DSTATE_BINDING_TABLE_EDIT_GS_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_EDIT_GS_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_EDIT_GS::Command Type */ #define GFX125_3DSTATE_BINDING_TABLE_EDIT_GS_CommandType_bits 3 #define GFX12_3DSTATE_BINDING_TABLE_EDIT_GS_CommandType_bits 3 #define GFX11_3DSTATE_BINDING_TABLE_EDIT_GS_CommandType_bits 3 #define GFX9_3DSTATE_BINDING_TABLE_EDIT_GS_CommandType_bits 3 #define GFX8_3DSTATE_BINDING_TABLE_EDIT_GS_CommandType_bits 3 #define GFX75_3DSTATE_BINDING_TABLE_EDIT_GS_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_EDIT_GS_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BINDING_TABLE_EDIT_GS_CommandType_start 29 #define GFX12_3DSTATE_BINDING_TABLE_EDIT_GS_CommandType_start 29 #define GFX11_3DSTATE_BINDING_TABLE_EDIT_GS_CommandType_start 29 #define GFX9_3DSTATE_BINDING_TABLE_EDIT_GS_CommandType_start 29 #define GFX8_3DSTATE_BINDING_TABLE_EDIT_GS_CommandType_start 29 #define GFX75_3DSTATE_BINDING_TABLE_EDIT_GS_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_EDIT_GS_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_EDIT_GS::DWord Length */ #define GFX125_3DSTATE_BINDING_TABLE_EDIT_GS_DWordLength_bits 9 #define GFX12_3DSTATE_BINDING_TABLE_EDIT_GS_DWordLength_bits 9 #define GFX11_3DSTATE_BINDING_TABLE_EDIT_GS_DWordLength_bits 9 #define GFX9_3DSTATE_BINDING_TABLE_EDIT_GS_DWordLength_bits 9 #define GFX8_3DSTATE_BINDING_TABLE_EDIT_GS_DWordLength_bits 9 #define GFX75_3DSTATE_BINDING_TABLE_EDIT_GS_DWordLength_bits 9 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_EDIT_GS_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 9; case 120: return 9; case 110: return 9; case 90: return 9; case 80: return 9; case 75: return 9; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BINDING_TABLE_EDIT_GS_DWordLength_start 0 #define GFX12_3DSTATE_BINDING_TABLE_EDIT_GS_DWordLength_start 0 #define GFX11_3DSTATE_BINDING_TABLE_EDIT_GS_DWordLength_start 0 #define GFX9_3DSTATE_BINDING_TABLE_EDIT_GS_DWordLength_start 0 #define GFX8_3DSTATE_BINDING_TABLE_EDIT_GS_DWordLength_start 0 #define GFX75_3DSTATE_BINDING_TABLE_EDIT_GS_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_EDIT_GS_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_EDIT_HS */ /* 3DSTATE_BINDING_TABLE_EDIT_HS::3D Command Opcode */ #define GFX125_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandOpcode_bits 3 #define GFX75_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandOpcode_start 24 #define GFX12_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandOpcode_start 24 #define GFX11_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandOpcode_start 24 #define GFX9_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandOpcode_start 24 #define GFX8_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandOpcode_start 24 #define GFX75_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_EDIT_HS::3D Command Sub Opcode */ #define GFX125_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandSubOpcode_bits 8 #define GFX75_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandSubOpcode_start 16 #define GFX75_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_EDIT_HS::Binding Table Block Clear */ #define GFX125_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableBlockClear_bits 16 #define GFX12_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableBlockClear_bits 16 #define GFX11_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableBlockClear_bits 16 #define GFX9_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableBlockClear_bits 16 #define GFX8_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableBlockClear_bits 16 #define GFX75_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableBlockClear_bits 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableBlockClear_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableBlockClear_start 48 #define GFX12_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableBlockClear_start 48 #define GFX11_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableBlockClear_start 48 #define GFX9_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableBlockClear_start 48 #define GFX8_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableBlockClear_start 48 #define GFX75_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableBlockClear_start 48 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableBlockClear_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 48; case 120: return 48; case 110: return 48; case 90: return 48; case 80: return 48; case 75: return 48; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_EDIT_HS::Binding Table Edit Target */ #define GFX125_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableEditTarget_bits 2 #define GFX12_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableEditTarget_bits 2 #define GFX11_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableEditTarget_bits 2 #define GFX9_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableEditTarget_bits 2 #define GFX8_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableEditTarget_bits 2 #define GFX75_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableEditTarget_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableEditTarget_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableEditTarget_start 32 #define GFX12_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableEditTarget_start 32 #define GFX11_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableEditTarget_start 32 #define GFX9_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableEditTarget_start 32 #define GFX8_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableEditTarget_start 32 #define GFX75_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableEditTarget_start 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableEditTarget_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_EDIT_HS::Command SubType */ #define GFX125_3DSTATE_BINDING_TABLE_EDIT_HS_CommandSubType_bits 2 #define GFX12_3DSTATE_BINDING_TABLE_EDIT_HS_CommandSubType_bits 2 #define GFX11_3DSTATE_BINDING_TABLE_EDIT_HS_CommandSubType_bits 2 #define GFX9_3DSTATE_BINDING_TABLE_EDIT_HS_CommandSubType_bits 2 #define GFX8_3DSTATE_BINDING_TABLE_EDIT_HS_CommandSubType_bits 2 #define GFX75_3DSTATE_BINDING_TABLE_EDIT_HS_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_EDIT_HS_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BINDING_TABLE_EDIT_HS_CommandSubType_start 27 #define GFX12_3DSTATE_BINDING_TABLE_EDIT_HS_CommandSubType_start 27 #define GFX11_3DSTATE_BINDING_TABLE_EDIT_HS_CommandSubType_start 27 #define GFX9_3DSTATE_BINDING_TABLE_EDIT_HS_CommandSubType_start 27 #define GFX8_3DSTATE_BINDING_TABLE_EDIT_HS_CommandSubType_start 27 #define GFX75_3DSTATE_BINDING_TABLE_EDIT_HS_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_EDIT_HS_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_EDIT_HS::Command Type */ #define GFX125_3DSTATE_BINDING_TABLE_EDIT_HS_CommandType_bits 3 #define GFX12_3DSTATE_BINDING_TABLE_EDIT_HS_CommandType_bits 3 #define GFX11_3DSTATE_BINDING_TABLE_EDIT_HS_CommandType_bits 3 #define GFX9_3DSTATE_BINDING_TABLE_EDIT_HS_CommandType_bits 3 #define GFX8_3DSTATE_BINDING_TABLE_EDIT_HS_CommandType_bits 3 #define GFX75_3DSTATE_BINDING_TABLE_EDIT_HS_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_EDIT_HS_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BINDING_TABLE_EDIT_HS_CommandType_start 29 #define GFX12_3DSTATE_BINDING_TABLE_EDIT_HS_CommandType_start 29 #define GFX11_3DSTATE_BINDING_TABLE_EDIT_HS_CommandType_start 29 #define GFX9_3DSTATE_BINDING_TABLE_EDIT_HS_CommandType_start 29 #define GFX8_3DSTATE_BINDING_TABLE_EDIT_HS_CommandType_start 29 #define GFX75_3DSTATE_BINDING_TABLE_EDIT_HS_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_EDIT_HS_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_EDIT_HS::DWord Length */ #define GFX125_3DSTATE_BINDING_TABLE_EDIT_HS_DWordLength_bits 9 #define GFX12_3DSTATE_BINDING_TABLE_EDIT_HS_DWordLength_bits 9 #define GFX11_3DSTATE_BINDING_TABLE_EDIT_HS_DWordLength_bits 9 #define GFX9_3DSTATE_BINDING_TABLE_EDIT_HS_DWordLength_bits 9 #define GFX8_3DSTATE_BINDING_TABLE_EDIT_HS_DWordLength_bits 9 #define GFX75_3DSTATE_BINDING_TABLE_EDIT_HS_DWordLength_bits 9 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_EDIT_HS_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 9; case 120: return 9; case 110: return 9; case 90: return 9; case 80: return 9; case 75: return 9; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BINDING_TABLE_EDIT_HS_DWordLength_start 0 #define GFX12_3DSTATE_BINDING_TABLE_EDIT_HS_DWordLength_start 0 #define GFX11_3DSTATE_BINDING_TABLE_EDIT_HS_DWordLength_start 0 #define GFX9_3DSTATE_BINDING_TABLE_EDIT_HS_DWordLength_start 0 #define GFX8_3DSTATE_BINDING_TABLE_EDIT_HS_DWordLength_start 0 #define GFX75_3DSTATE_BINDING_TABLE_EDIT_HS_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_EDIT_HS_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_EDIT_PS */ /* 3DSTATE_BINDING_TABLE_EDIT_PS::3D Command Opcode */ #define GFX125_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandOpcode_bits 3 #define GFX75_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandOpcode_start 24 #define GFX12_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandOpcode_start 24 #define GFX11_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandOpcode_start 24 #define GFX9_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandOpcode_start 24 #define GFX8_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandOpcode_start 24 #define GFX75_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_EDIT_PS::3D Command Sub Opcode */ #define GFX125_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandSubOpcode_bits 8 #define GFX75_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandSubOpcode_start 16 #define GFX75_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_EDIT_PS::Binding Table Block Clear */ #define GFX125_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableBlockClear_bits 16 #define GFX12_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableBlockClear_bits 16 #define GFX11_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableBlockClear_bits 16 #define GFX9_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableBlockClear_bits 16 #define GFX8_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableBlockClear_bits 16 #define GFX75_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableBlockClear_bits 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableBlockClear_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableBlockClear_start 48 #define GFX12_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableBlockClear_start 48 #define GFX11_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableBlockClear_start 48 #define GFX9_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableBlockClear_start 48 #define GFX8_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableBlockClear_start 48 #define GFX75_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableBlockClear_start 48 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableBlockClear_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 48; case 120: return 48; case 110: return 48; case 90: return 48; case 80: return 48; case 75: return 48; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_EDIT_PS::Binding Table Edit Target */ #define GFX125_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableEditTarget_bits 2 #define GFX12_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableEditTarget_bits 2 #define GFX11_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableEditTarget_bits 2 #define GFX9_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableEditTarget_bits 2 #define GFX8_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableEditTarget_bits 2 #define GFX75_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableEditTarget_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableEditTarget_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableEditTarget_start 32 #define GFX12_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableEditTarget_start 32 #define GFX11_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableEditTarget_start 32 #define GFX9_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableEditTarget_start 32 #define GFX8_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableEditTarget_start 32 #define GFX75_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableEditTarget_start 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableEditTarget_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_EDIT_PS::Command SubType */ #define GFX125_3DSTATE_BINDING_TABLE_EDIT_PS_CommandSubType_bits 2 #define GFX12_3DSTATE_BINDING_TABLE_EDIT_PS_CommandSubType_bits 2 #define GFX11_3DSTATE_BINDING_TABLE_EDIT_PS_CommandSubType_bits 2 #define GFX9_3DSTATE_BINDING_TABLE_EDIT_PS_CommandSubType_bits 2 #define GFX8_3DSTATE_BINDING_TABLE_EDIT_PS_CommandSubType_bits 2 #define GFX75_3DSTATE_BINDING_TABLE_EDIT_PS_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_EDIT_PS_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BINDING_TABLE_EDIT_PS_CommandSubType_start 27 #define GFX12_3DSTATE_BINDING_TABLE_EDIT_PS_CommandSubType_start 27 #define GFX11_3DSTATE_BINDING_TABLE_EDIT_PS_CommandSubType_start 27 #define GFX9_3DSTATE_BINDING_TABLE_EDIT_PS_CommandSubType_start 27 #define GFX8_3DSTATE_BINDING_TABLE_EDIT_PS_CommandSubType_start 27 #define GFX75_3DSTATE_BINDING_TABLE_EDIT_PS_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_EDIT_PS_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_EDIT_PS::Command Type */ #define GFX125_3DSTATE_BINDING_TABLE_EDIT_PS_CommandType_bits 3 #define GFX12_3DSTATE_BINDING_TABLE_EDIT_PS_CommandType_bits 3 #define GFX11_3DSTATE_BINDING_TABLE_EDIT_PS_CommandType_bits 3 #define GFX9_3DSTATE_BINDING_TABLE_EDIT_PS_CommandType_bits 3 #define GFX8_3DSTATE_BINDING_TABLE_EDIT_PS_CommandType_bits 3 #define GFX75_3DSTATE_BINDING_TABLE_EDIT_PS_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_EDIT_PS_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BINDING_TABLE_EDIT_PS_CommandType_start 29 #define GFX12_3DSTATE_BINDING_TABLE_EDIT_PS_CommandType_start 29 #define GFX11_3DSTATE_BINDING_TABLE_EDIT_PS_CommandType_start 29 #define GFX9_3DSTATE_BINDING_TABLE_EDIT_PS_CommandType_start 29 #define GFX8_3DSTATE_BINDING_TABLE_EDIT_PS_CommandType_start 29 #define GFX75_3DSTATE_BINDING_TABLE_EDIT_PS_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_EDIT_PS_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_EDIT_PS::DWord Length */ #define GFX125_3DSTATE_BINDING_TABLE_EDIT_PS_DWordLength_bits 9 #define GFX12_3DSTATE_BINDING_TABLE_EDIT_PS_DWordLength_bits 9 #define GFX11_3DSTATE_BINDING_TABLE_EDIT_PS_DWordLength_bits 9 #define GFX9_3DSTATE_BINDING_TABLE_EDIT_PS_DWordLength_bits 9 #define GFX8_3DSTATE_BINDING_TABLE_EDIT_PS_DWordLength_bits 9 #define GFX75_3DSTATE_BINDING_TABLE_EDIT_PS_DWordLength_bits 9 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_EDIT_PS_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 9; case 120: return 9; case 110: return 9; case 90: return 9; case 80: return 9; case 75: return 9; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BINDING_TABLE_EDIT_PS_DWordLength_start 0 #define GFX12_3DSTATE_BINDING_TABLE_EDIT_PS_DWordLength_start 0 #define GFX11_3DSTATE_BINDING_TABLE_EDIT_PS_DWordLength_start 0 #define GFX9_3DSTATE_BINDING_TABLE_EDIT_PS_DWordLength_start 0 #define GFX8_3DSTATE_BINDING_TABLE_EDIT_PS_DWordLength_start 0 #define GFX75_3DSTATE_BINDING_TABLE_EDIT_PS_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_EDIT_PS_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_EDIT_VS */ /* 3DSTATE_BINDING_TABLE_EDIT_VS::3D Command Opcode */ #define GFX125_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandOpcode_bits 3 #define GFX75_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandOpcode_start 24 #define GFX12_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandOpcode_start 24 #define GFX11_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandOpcode_start 24 #define GFX9_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandOpcode_start 24 #define GFX8_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandOpcode_start 24 #define GFX75_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_EDIT_VS::3D Command Sub Opcode */ #define GFX125_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandSubOpcode_bits 8 #define GFX75_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandSubOpcode_start 16 #define GFX75_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_EDIT_VS::Binding Table Block Clear */ #define GFX125_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableBlockClear_bits 16 #define GFX12_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableBlockClear_bits 16 #define GFX11_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableBlockClear_bits 16 #define GFX9_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableBlockClear_bits 16 #define GFX8_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableBlockClear_bits 16 #define GFX75_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableBlockClear_bits 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableBlockClear_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableBlockClear_start 48 #define GFX12_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableBlockClear_start 48 #define GFX11_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableBlockClear_start 48 #define GFX9_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableBlockClear_start 48 #define GFX8_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableBlockClear_start 48 #define GFX75_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableBlockClear_start 48 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableBlockClear_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 48; case 120: return 48; case 110: return 48; case 90: return 48; case 80: return 48; case 75: return 48; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_EDIT_VS::Binding Table Edit Target */ #define GFX125_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableEditTarget_bits 2 #define GFX12_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableEditTarget_bits 2 #define GFX11_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableEditTarget_bits 2 #define GFX9_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableEditTarget_bits 2 #define GFX8_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableEditTarget_bits 2 #define GFX75_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableEditTarget_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableEditTarget_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableEditTarget_start 32 #define GFX12_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableEditTarget_start 32 #define GFX11_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableEditTarget_start 32 #define GFX9_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableEditTarget_start 32 #define GFX8_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableEditTarget_start 32 #define GFX75_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableEditTarget_start 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableEditTarget_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_EDIT_VS::Command SubType */ #define GFX125_3DSTATE_BINDING_TABLE_EDIT_VS_CommandSubType_bits 2 #define GFX12_3DSTATE_BINDING_TABLE_EDIT_VS_CommandSubType_bits 2 #define GFX11_3DSTATE_BINDING_TABLE_EDIT_VS_CommandSubType_bits 2 #define GFX9_3DSTATE_BINDING_TABLE_EDIT_VS_CommandSubType_bits 2 #define GFX8_3DSTATE_BINDING_TABLE_EDIT_VS_CommandSubType_bits 2 #define GFX75_3DSTATE_BINDING_TABLE_EDIT_VS_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_EDIT_VS_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BINDING_TABLE_EDIT_VS_CommandSubType_start 27 #define GFX12_3DSTATE_BINDING_TABLE_EDIT_VS_CommandSubType_start 27 #define GFX11_3DSTATE_BINDING_TABLE_EDIT_VS_CommandSubType_start 27 #define GFX9_3DSTATE_BINDING_TABLE_EDIT_VS_CommandSubType_start 27 #define GFX8_3DSTATE_BINDING_TABLE_EDIT_VS_CommandSubType_start 27 #define GFX75_3DSTATE_BINDING_TABLE_EDIT_VS_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_EDIT_VS_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_EDIT_VS::Command Type */ #define GFX125_3DSTATE_BINDING_TABLE_EDIT_VS_CommandType_bits 3 #define GFX12_3DSTATE_BINDING_TABLE_EDIT_VS_CommandType_bits 3 #define GFX11_3DSTATE_BINDING_TABLE_EDIT_VS_CommandType_bits 3 #define GFX9_3DSTATE_BINDING_TABLE_EDIT_VS_CommandType_bits 3 #define GFX8_3DSTATE_BINDING_TABLE_EDIT_VS_CommandType_bits 3 #define GFX75_3DSTATE_BINDING_TABLE_EDIT_VS_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_EDIT_VS_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BINDING_TABLE_EDIT_VS_CommandType_start 29 #define GFX12_3DSTATE_BINDING_TABLE_EDIT_VS_CommandType_start 29 #define GFX11_3DSTATE_BINDING_TABLE_EDIT_VS_CommandType_start 29 #define GFX9_3DSTATE_BINDING_TABLE_EDIT_VS_CommandType_start 29 #define GFX8_3DSTATE_BINDING_TABLE_EDIT_VS_CommandType_start 29 #define GFX75_3DSTATE_BINDING_TABLE_EDIT_VS_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_EDIT_VS_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_EDIT_VS::DWord Length */ #define GFX125_3DSTATE_BINDING_TABLE_EDIT_VS_DWordLength_bits 9 #define GFX12_3DSTATE_BINDING_TABLE_EDIT_VS_DWordLength_bits 9 #define GFX11_3DSTATE_BINDING_TABLE_EDIT_VS_DWordLength_bits 9 #define GFX9_3DSTATE_BINDING_TABLE_EDIT_VS_DWordLength_bits 9 #define GFX8_3DSTATE_BINDING_TABLE_EDIT_VS_DWordLength_bits 9 #define GFX75_3DSTATE_BINDING_TABLE_EDIT_VS_DWordLength_bits 9 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_EDIT_VS_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 9; case 120: return 9; case 110: return 9; case 90: return 9; case 80: return 9; case 75: return 9; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BINDING_TABLE_EDIT_VS_DWordLength_start 0 #define GFX12_3DSTATE_BINDING_TABLE_EDIT_VS_DWordLength_start 0 #define GFX11_3DSTATE_BINDING_TABLE_EDIT_VS_DWordLength_start 0 #define GFX9_3DSTATE_BINDING_TABLE_EDIT_VS_DWordLength_start 0 #define GFX8_3DSTATE_BINDING_TABLE_EDIT_VS_DWordLength_start 0 #define GFX75_3DSTATE_BINDING_TABLE_EDIT_VS_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_EDIT_VS_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_POINTERS */ #define GFX6_3DSTATE_BINDING_TABLE_POINTERS_length 4 #define GFX5_3DSTATE_BINDING_TABLE_POINTERS_length 6 #define GFX45_3DSTATE_BINDING_TABLE_POINTERS_length 6 #define GFX4_3DSTATE_BINDING_TABLE_POINTERS_length 6 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 4; case 50: return 6; case 45: return 6; case 40: return 6; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_POINTERS::3D Command Opcode */ #define GFX6_3DSTATE_BINDING_TABLE_POINTERS_3DCommandOpcode_bits 3 #define GFX5_3DSTATE_BINDING_TABLE_POINTERS_3DCommandOpcode_bits 3 #define GFX45_3DSTATE_BINDING_TABLE_POINTERS_3DCommandOpcode_bits 3 #define GFX4_3DSTATE_BINDING_TABLE_POINTERS_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 3; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_BINDING_TABLE_POINTERS_3DCommandOpcode_start 24 #define GFX5_3DSTATE_BINDING_TABLE_POINTERS_3DCommandOpcode_start 24 #define GFX45_3DSTATE_BINDING_TABLE_POINTERS_3DCommandOpcode_start 24 #define GFX4_3DSTATE_BINDING_TABLE_POINTERS_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 24; case 50: return 24; case 45: return 24; case 40: return 24; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_POINTERS::3D Command Sub Opcode */ #define GFX6_3DSTATE_BINDING_TABLE_POINTERS_3DCommandSubOpcode_bits 8 #define GFX5_3DSTATE_BINDING_TABLE_POINTERS_3DCommandSubOpcode_bits 8 #define GFX45_3DSTATE_BINDING_TABLE_POINTERS_3DCommandSubOpcode_bits 8 #define GFX4_3DSTATE_BINDING_TABLE_POINTERS_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 8; case 50: return 8; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_BINDING_TABLE_POINTERS_3DCommandSubOpcode_start 16 #define GFX5_3DSTATE_BINDING_TABLE_POINTERS_3DCommandSubOpcode_start 16 #define GFX45_3DSTATE_BINDING_TABLE_POINTERS_3DCommandSubOpcode_start 16 #define GFX4_3DSTATE_BINDING_TABLE_POINTERS_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 16; case 50: return 16; case 45: return 16; case 40: return 16; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_POINTERS::Command SubType */ #define GFX6_3DSTATE_BINDING_TABLE_POINTERS_CommandSubType_bits 2 #define GFX5_3DSTATE_BINDING_TABLE_POINTERS_CommandSubType_bits 2 #define GFX45_3DSTATE_BINDING_TABLE_POINTERS_CommandSubType_bits 2 #define GFX4_3DSTATE_BINDING_TABLE_POINTERS_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 2; case 50: return 2; case 45: return 2; case 40: return 2; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_BINDING_TABLE_POINTERS_CommandSubType_start 27 #define GFX5_3DSTATE_BINDING_TABLE_POINTERS_CommandSubType_start 27 #define GFX45_3DSTATE_BINDING_TABLE_POINTERS_CommandSubType_start 27 #define GFX4_3DSTATE_BINDING_TABLE_POINTERS_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 27; case 50: return 27; case 45: return 27; case 40: return 27; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_POINTERS::Command Type */ #define GFX6_3DSTATE_BINDING_TABLE_POINTERS_CommandType_bits 3 #define GFX5_3DSTATE_BINDING_TABLE_POINTERS_CommandType_bits 3 #define GFX45_3DSTATE_BINDING_TABLE_POINTERS_CommandType_bits 3 #define GFX4_3DSTATE_BINDING_TABLE_POINTERS_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 3; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_BINDING_TABLE_POINTERS_CommandType_start 29 #define GFX5_3DSTATE_BINDING_TABLE_POINTERS_CommandType_start 29 #define GFX45_3DSTATE_BINDING_TABLE_POINTERS_CommandType_start 29 #define GFX4_3DSTATE_BINDING_TABLE_POINTERS_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 29; case 50: return 29; case 45: return 29; case 40: return 29; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_POINTERS::DWord Length */ #define GFX6_3DSTATE_BINDING_TABLE_POINTERS_DWordLength_bits 8 #define GFX5_3DSTATE_BINDING_TABLE_POINTERS_DWordLength_bits 8 #define GFX45_3DSTATE_BINDING_TABLE_POINTERS_DWordLength_bits 8 #define GFX4_3DSTATE_BINDING_TABLE_POINTERS_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 8; case 50: return 8; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_BINDING_TABLE_POINTERS_DWordLength_start 0 #define GFX5_3DSTATE_BINDING_TABLE_POINTERS_DWordLength_start 0 #define GFX45_3DSTATE_BINDING_TABLE_POINTERS_DWordLength_start 0 #define GFX4_3DSTATE_BINDING_TABLE_POINTERS_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_POINTERS::GS Binding Table Change */ #define GFX6_3DSTATE_BINDING_TABLE_POINTERS_GSBindingTableChange_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_GSBindingTableChange_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_BINDING_TABLE_POINTERS_GSBindingTableChange_start 9 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_GSBindingTableChange_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 9; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_POINTERS::PS Binding Table Change */ #define GFX6_3DSTATE_BINDING_TABLE_POINTERS_PSBindingTableChange_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_PSBindingTableChange_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_BINDING_TABLE_POINTERS_PSBindingTableChange_start 12 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_PSBindingTableChange_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 12; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_POINTERS::Pointer to CLIP Binding Table */ #define GFX5_3DSTATE_BINDING_TABLE_POINTERS_PointertoCLIPBindingTable_bits 27 #define GFX45_3DSTATE_BINDING_TABLE_POINTERS_PointertoCLIPBindingTable_bits 27 #define GFX4_3DSTATE_BINDING_TABLE_POINTERS_PointertoCLIPBindingTable_bits 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_PointertoCLIPBindingTable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 27; case 45: return 27; case 40: return 27; default: unreachable("Invalid hardware generation"); } } #define GFX5_3DSTATE_BINDING_TABLE_POINTERS_PointertoCLIPBindingTable_start 101 #define GFX45_3DSTATE_BINDING_TABLE_POINTERS_PointertoCLIPBindingTable_start 101 #define GFX4_3DSTATE_BINDING_TABLE_POINTERS_PointertoCLIPBindingTable_start 101 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_PointertoCLIPBindingTable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 101; case 45: return 101; case 40: return 101; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_POINTERS::Pointer to GS Binding Table */ #define GFX6_3DSTATE_BINDING_TABLE_POINTERS_PointertoGSBindingTable_bits 27 #define GFX5_3DSTATE_BINDING_TABLE_POINTERS_PointertoGSBindingTable_bits 27 #define GFX45_3DSTATE_BINDING_TABLE_POINTERS_PointertoGSBindingTable_bits 27 #define GFX4_3DSTATE_BINDING_TABLE_POINTERS_PointertoGSBindingTable_bits 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_PointertoGSBindingTable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 27; case 50: return 27; case 45: return 27; case 40: return 27; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_BINDING_TABLE_POINTERS_PointertoGSBindingTable_start 69 #define GFX5_3DSTATE_BINDING_TABLE_POINTERS_PointertoGSBindingTable_start 69 #define GFX45_3DSTATE_BINDING_TABLE_POINTERS_PointertoGSBindingTable_start 69 #define GFX4_3DSTATE_BINDING_TABLE_POINTERS_PointertoGSBindingTable_start 69 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_PointertoGSBindingTable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 69; case 50: return 69; case 45: return 69; case 40: return 69; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_POINTERS::Pointer to PS Binding Table */ #define GFX6_3DSTATE_BINDING_TABLE_POINTERS_PointertoPSBindingTable_bits 27 #define GFX5_3DSTATE_BINDING_TABLE_POINTERS_PointertoPSBindingTable_bits 27 #define GFX45_3DSTATE_BINDING_TABLE_POINTERS_PointertoPSBindingTable_bits 27 #define GFX4_3DSTATE_BINDING_TABLE_POINTERS_PointertoPSBindingTable_bits 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_PointertoPSBindingTable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 27; case 50: return 27; case 45: return 27; case 40: return 27; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_BINDING_TABLE_POINTERS_PointertoPSBindingTable_start 101 #define GFX5_3DSTATE_BINDING_TABLE_POINTERS_PointertoPSBindingTable_start 165 #define GFX45_3DSTATE_BINDING_TABLE_POINTERS_PointertoPSBindingTable_start 165 #define GFX4_3DSTATE_BINDING_TABLE_POINTERS_PointertoPSBindingTable_start 165 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_PointertoPSBindingTable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 101; case 50: return 165; case 45: return 165; case 40: return 165; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_POINTERS::Pointer to SF Binding Table */ #define GFX5_3DSTATE_BINDING_TABLE_POINTERS_PointertoSFBindingTable_bits 27 #define GFX45_3DSTATE_BINDING_TABLE_POINTERS_PointertoSFBindingTable_bits 27 #define GFX4_3DSTATE_BINDING_TABLE_POINTERS_PointertoSFBindingTable_bits 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_PointertoSFBindingTable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 27; case 45: return 27; case 40: return 27; default: unreachable("Invalid hardware generation"); } } #define GFX5_3DSTATE_BINDING_TABLE_POINTERS_PointertoSFBindingTable_start 133 #define GFX45_3DSTATE_BINDING_TABLE_POINTERS_PointertoSFBindingTable_start 133 #define GFX4_3DSTATE_BINDING_TABLE_POINTERS_PointertoSFBindingTable_start 133 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_PointertoSFBindingTable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 133; case 45: return 133; case 40: return 133; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_POINTERS::Pointer to VS Binding Table */ #define GFX6_3DSTATE_BINDING_TABLE_POINTERS_PointertoVSBindingTable_bits 27 #define GFX5_3DSTATE_BINDING_TABLE_POINTERS_PointertoVSBindingTable_bits 27 #define GFX45_3DSTATE_BINDING_TABLE_POINTERS_PointertoVSBindingTable_bits 27 #define GFX4_3DSTATE_BINDING_TABLE_POINTERS_PointertoVSBindingTable_bits 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_PointertoVSBindingTable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 27; case 50: return 27; case 45: return 27; case 40: return 27; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_BINDING_TABLE_POINTERS_PointertoVSBindingTable_start 37 #define GFX5_3DSTATE_BINDING_TABLE_POINTERS_PointertoVSBindingTable_start 37 #define GFX45_3DSTATE_BINDING_TABLE_POINTERS_PointertoVSBindingTable_start 37 #define GFX4_3DSTATE_BINDING_TABLE_POINTERS_PointertoVSBindingTable_start 37 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_PointertoVSBindingTable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 37; case 50: return 37; case 45: return 37; case 40: return 37; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_POINTERS::VS Binding Table Change */ #define GFX6_3DSTATE_BINDING_TABLE_POINTERS_VSBindingTableChange_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_VSBindingTableChange_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_BINDING_TABLE_POINTERS_VSBindingTableChange_start 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_VSBindingTableChange_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_POINTERS_DS */ #define GFX125_3DSTATE_BINDING_TABLE_POINTERS_DS_length 2 #define GFX12_3DSTATE_BINDING_TABLE_POINTERS_DS_length 2 #define GFX11_3DSTATE_BINDING_TABLE_POINTERS_DS_length 2 #define GFX9_3DSTATE_BINDING_TABLE_POINTERS_DS_length 2 #define GFX8_3DSTATE_BINDING_TABLE_POINTERS_DS_length 2 #define GFX75_3DSTATE_BINDING_TABLE_POINTERS_DS_length 2 #define GFX7_3DSTATE_BINDING_TABLE_POINTERS_DS_length 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_DS_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_POINTERS_DS::3D Command Opcode */ #define GFX125_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandOpcode_bits 3 #define GFX75_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandOpcode_bits 3 #define GFX7_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandOpcode_start 24 #define GFX12_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandOpcode_start 24 #define GFX11_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandOpcode_start 24 #define GFX9_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandOpcode_start 24 #define GFX8_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandOpcode_start 24 #define GFX75_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandOpcode_start 24 #define GFX7_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_POINTERS_DS::3D Command Sub Opcode */ #define GFX125_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandSubOpcode_bits 8 #define GFX75_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandSubOpcode_bits 8 #define GFX7_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandSubOpcode_start 16 #define GFX75_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandSubOpcode_start 16 #define GFX7_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_POINTERS_DS::Command SubType */ #define GFX125_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandSubType_bits 2 #define GFX12_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandSubType_bits 2 #define GFX11_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandSubType_bits 2 #define GFX9_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandSubType_bits 2 #define GFX8_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandSubType_bits 2 #define GFX75_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandSubType_bits 2 #define GFX7_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_DS_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandSubType_start 27 #define GFX12_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandSubType_start 27 #define GFX11_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandSubType_start 27 #define GFX9_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandSubType_start 27 #define GFX8_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandSubType_start 27 #define GFX75_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandSubType_start 27 #define GFX7_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_DS_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_POINTERS_DS::Command Type */ #define GFX125_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandType_bits 3 #define GFX12_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandType_bits 3 #define GFX11_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandType_bits 3 #define GFX9_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandType_bits 3 #define GFX8_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandType_bits 3 #define GFX75_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandType_bits 3 #define GFX7_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_DS_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandType_start 29 #define GFX12_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandType_start 29 #define GFX11_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandType_start 29 #define GFX9_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandType_start 29 #define GFX8_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandType_start 29 #define GFX75_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandType_start 29 #define GFX7_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_DS_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_POINTERS_DS::DWord Length */ #define GFX125_3DSTATE_BINDING_TABLE_POINTERS_DS_DWordLength_bits 8 #define GFX12_3DSTATE_BINDING_TABLE_POINTERS_DS_DWordLength_bits 8 #define GFX11_3DSTATE_BINDING_TABLE_POINTERS_DS_DWordLength_bits 8 #define GFX9_3DSTATE_BINDING_TABLE_POINTERS_DS_DWordLength_bits 8 #define GFX8_3DSTATE_BINDING_TABLE_POINTERS_DS_DWordLength_bits 8 #define GFX75_3DSTATE_BINDING_TABLE_POINTERS_DS_DWordLength_bits 8 #define GFX7_3DSTATE_BINDING_TABLE_POINTERS_DS_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_DS_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BINDING_TABLE_POINTERS_DS_DWordLength_start 0 #define GFX12_3DSTATE_BINDING_TABLE_POINTERS_DS_DWordLength_start 0 #define GFX11_3DSTATE_BINDING_TABLE_POINTERS_DS_DWordLength_start 0 #define GFX9_3DSTATE_BINDING_TABLE_POINTERS_DS_DWordLength_start 0 #define GFX8_3DSTATE_BINDING_TABLE_POINTERS_DS_DWordLength_start 0 #define GFX75_3DSTATE_BINDING_TABLE_POINTERS_DS_DWordLength_start 0 #define GFX7_3DSTATE_BINDING_TABLE_POINTERS_DS_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_DS_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_POINTERS_DS::Pointer to DS Binding Table */ #define GFX125_3DSTATE_BINDING_TABLE_POINTERS_DS_PointertoDSBindingTable_bits 16 #define GFX12_3DSTATE_BINDING_TABLE_POINTERS_DS_PointertoDSBindingTable_bits 11 #define GFX11_3DSTATE_BINDING_TABLE_POINTERS_DS_PointertoDSBindingTable_bits 11 #define GFX9_3DSTATE_BINDING_TABLE_POINTERS_DS_PointertoDSBindingTable_bits 11 #define GFX8_3DSTATE_BINDING_TABLE_POINTERS_DS_PointertoDSBindingTable_bits 11 #define GFX75_3DSTATE_BINDING_TABLE_POINTERS_DS_PointertoDSBindingTable_bits 11 #define GFX7_3DSTATE_BINDING_TABLE_POINTERS_DS_PointertoDSBindingTable_bits 11 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_DS_PointertoDSBindingTable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 11; case 110: return 11; case 90: return 11; case 80: return 11; case 75: return 11; case 70: return 11; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BINDING_TABLE_POINTERS_DS_PointertoDSBindingTable_start 37 #define GFX12_3DSTATE_BINDING_TABLE_POINTERS_DS_PointertoDSBindingTable_start 37 #define GFX11_3DSTATE_BINDING_TABLE_POINTERS_DS_PointertoDSBindingTable_start 37 #define GFX9_3DSTATE_BINDING_TABLE_POINTERS_DS_PointertoDSBindingTable_start 37 #define GFX8_3DSTATE_BINDING_TABLE_POINTERS_DS_PointertoDSBindingTable_start 37 #define GFX75_3DSTATE_BINDING_TABLE_POINTERS_DS_PointertoDSBindingTable_start 37 #define GFX7_3DSTATE_BINDING_TABLE_POINTERS_DS_PointertoDSBindingTable_start 37 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_DS_PointertoDSBindingTable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 37; case 120: return 37; case 110: return 37; case 90: return 37; case 80: return 37; case 75: return 37; case 70: return 37; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_POINTERS_GS */ #define GFX125_3DSTATE_BINDING_TABLE_POINTERS_GS_length 2 #define GFX12_3DSTATE_BINDING_TABLE_POINTERS_GS_length 2 #define GFX11_3DSTATE_BINDING_TABLE_POINTERS_GS_length 2 #define GFX9_3DSTATE_BINDING_TABLE_POINTERS_GS_length 2 #define GFX8_3DSTATE_BINDING_TABLE_POINTERS_GS_length 2 #define GFX75_3DSTATE_BINDING_TABLE_POINTERS_GS_length 2 #define GFX7_3DSTATE_BINDING_TABLE_POINTERS_GS_length 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_GS_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_POINTERS_GS::3D Command Opcode */ #define GFX125_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandOpcode_bits 3 #define GFX75_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandOpcode_bits 3 #define GFX7_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandOpcode_start 24 #define GFX12_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandOpcode_start 24 #define GFX11_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandOpcode_start 24 #define GFX9_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandOpcode_start 24 #define GFX8_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandOpcode_start 24 #define GFX75_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandOpcode_start 24 #define GFX7_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_POINTERS_GS::3D Command Sub Opcode */ #define GFX125_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandSubOpcode_bits 8 #define GFX75_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandSubOpcode_bits 8 #define GFX7_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandSubOpcode_start 16 #define GFX75_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandSubOpcode_start 16 #define GFX7_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_POINTERS_GS::Command SubType */ #define GFX125_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandSubType_bits 2 #define GFX12_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandSubType_bits 2 #define GFX11_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandSubType_bits 2 #define GFX9_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandSubType_bits 2 #define GFX8_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandSubType_bits 2 #define GFX75_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandSubType_bits 2 #define GFX7_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_GS_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandSubType_start 27 #define GFX12_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandSubType_start 27 #define GFX11_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandSubType_start 27 #define GFX9_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandSubType_start 27 #define GFX8_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandSubType_start 27 #define GFX75_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandSubType_start 27 #define GFX7_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_GS_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_POINTERS_GS::Command Type */ #define GFX125_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandType_bits 3 #define GFX12_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandType_bits 3 #define GFX11_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandType_bits 3 #define GFX9_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandType_bits 3 #define GFX8_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandType_bits 3 #define GFX75_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandType_bits 3 #define GFX7_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_GS_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandType_start 29 #define GFX12_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandType_start 29 #define GFX11_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandType_start 29 #define GFX9_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandType_start 29 #define GFX8_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandType_start 29 #define GFX75_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandType_start 29 #define GFX7_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_GS_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_POINTERS_GS::DWord Length */ #define GFX125_3DSTATE_BINDING_TABLE_POINTERS_GS_DWordLength_bits 8 #define GFX12_3DSTATE_BINDING_TABLE_POINTERS_GS_DWordLength_bits 8 #define GFX11_3DSTATE_BINDING_TABLE_POINTERS_GS_DWordLength_bits 8 #define GFX9_3DSTATE_BINDING_TABLE_POINTERS_GS_DWordLength_bits 8 #define GFX8_3DSTATE_BINDING_TABLE_POINTERS_GS_DWordLength_bits 8 #define GFX75_3DSTATE_BINDING_TABLE_POINTERS_GS_DWordLength_bits 8 #define GFX7_3DSTATE_BINDING_TABLE_POINTERS_GS_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_GS_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BINDING_TABLE_POINTERS_GS_DWordLength_start 0 #define GFX12_3DSTATE_BINDING_TABLE_POINTERS_GS_DWordLength_start 0 #define GFX11_3DSTATE_BINDING_TABLE_POINTERS_GS_DWordLength_start 0 #define GFX9_3DSTATE_BINDING_TABLE_POINTERS_GS_DWordLength_start 0 #define GFX8_3DSTATE_BINDING_TABLE_POINTERS_GS_DWordLength_start 0 #define GFX75_3DSTATE_BINDING_TABLE_POINTERS_GS_DWordLength_start 0 #define GFX7_3DSTATE_BINDING_TABLE_POINTERS_GS_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_GS_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_POINTERS_GS::Pointer to GS Binding Table */ #define GFX125_3DSTATE_BINDING_TABLE_POINTERS_GS_PointertoGSBindingTable_bits 16 #define GFX12_3DSTATE_BINDING_TABLE_POINTERS_GS_PointertoGSBindingTable_bits 11 #define GFX11_3DSTATE_BINDING_TABLE_POINTERS_GS_PointertoGSBindingTable_bits 11 #define GFX9_3DSTATE_BINDING_TABLE_POINTERS_GS_PointertoGSBindingTable_bits 11 #define GFX8_3DSTATE_BINDING_TABLE_POINTERS_GS_PointertoGSBindingTable_bits 11 #define GFX75_3DSTATE_BINDING_TABLE_POINTERS_GS_PointertoGSBindingTable_bits 11 #define GFX7_3DSTATE_BINDING_TABLE_POINTERS_GS_PointertoGSBindingTable_bits 11 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_GS_PointertoGSBindingTable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 11; case 110: return 11; case 90: return 11; case 80: return 11; case 75: return 11; case 70: return 11; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BINDING_TABLE_POINTERS_GS_PointertoGSBindingTable_start 37 #define GFX12_3DSTATE_BINDING_TABLE_POINTERS_GS_PointertoGSBindingTable_start 37 #define GFX11_3DSTATE_BINDING_TABLE_POINTERS_GS_PointertoGSBindingTable_start 37 #define GFX9_3DSTATE_BINDING_TABLE_POINTERS_GS_PointertoGSBindingTable_start 37 #define GFX8_3DSTATE_BINDING_TABLE_POINTERS_GS_PointertoGSBindingTable_start 37 #define GFX75_3DSTATE_BINDING_TABLE_POINTERS_GS_PointertoGSBindingTable_start 37 #define GFX7_3DSTATE_BINDING_TABLE_POINTERS_GS_PointertoGSBindingTable_start 37 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_GS_PointertoGSBindingTable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 37; case 120: return 37; case 110: return 37; case 90: return 37; case 80: return 37; case 75: return 37; case 70: return 37; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_POINTERS_HS */ #define GFX125_3DSTATE_BINDING_TABLE_POINTERS_HS_length 2 #define GFX12_3DSTATE_BINDING_TABLE_POINTERS_HS_length 2 #define GFX11_3DSTATE_BINDING_TABLE_POINTERS_HS_length 2 #define GFX9_3DSTATE_BINDING_TABLE_POINTERS_HS_length 2 #define GFX8_3DSTATE_BINDING_TABLE_POINTERS_HS_length 2 #define GFX75_3DSTATE_BINDING_TABLE_POINTERS_HS_length 2 #define GFX7_3DSTATE_BINDING_TABLE_POINTERS_HS_length 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_HS_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_POINTERS_HS::3D Command Opcode */ #define GFX125_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandOpcode_bits 3 #define GFX75_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandOpcode_bits 3 #define GFX7_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandOpcode_start 24 #define GFX12_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandOpcode_start 24 #define GFX11_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandOpcode_start 24 #define GFX9_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandOpcode_start 24 #define GFX8_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandOpcode_start 24 #define GFX75_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandOpcode_start 24 #define GFX7_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_POINTERS_HS::3D Command Sub Opcode */ #define GFX125_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandSubOpcode_bits 8 #define GFX75_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandSubOpcode_bits 8 #define GFX7_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandSubOpcode_start 16 #define GFX75_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandSubOpcode_start 16 #define GFX7_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_POINTERS_HS::Command SubType */ #define GFX125_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandSubType_bits 2 #define GFX12_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandSubType_bits 2 #define GFX11_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandSubType_bits 2 #define GFX9_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandSubType_bits 2 #define GFX8_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandSubType_bits 2 #define GFX75_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandSubType_bits 2 #define GFX7_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_HS_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandSubType_start 27 #define GFX12_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandSubType_start 27 #define GFX11_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandSubType_start 27 #define GFX9_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandSubType_start 27 #define GFX8_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandSubType_start 27 #define GFX75_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandSubType_start 27 #define GFX7_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_HS_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_POINTERS_HS::Command Type */ #define GFX125_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandType_bits 3 #define GFX12_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandType_bits 3 #define GFX11_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandType_bits 3 #define GFX9_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandType_bits 3 #define GFX8_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandType_bits 3 #define GFX75_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandType_bits 3 #define GFX7_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_HS_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandType_start 29 #define GFX12_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandType_start 29 #define GFX11_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandType_start 29 #define GFX9_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandType_start 29 #define GFX8_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandType_start 29 #define GFX75_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandType_start 29 #define GFX7_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_HS_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_POINTERS_HS::DWord Length */ #define GFX125_3DSTATE_BINDING_TABLE_POINTERS_HS_DWordLength_bits 8 #define GFX12_3DSTATE_BINDING_TABLE_POINTERS_HS_DWordLength_bits 8 #define GFX11_3DSTATE_BINDING_TABLE_POINTERS_HS_DWordLength_bits 8 #define GFX9_3DSTATE_BINDING_TABLE_POINTERS_HS_DWordLength_bits 8 #define GFX8_3DSTATE_BINDING_TABLE_POINTERS_HS_DWordLength_bits 8 #define GFX75_3DSTATE_BINDING_TABLE_POINTERS_HS_DWordLength_bits 8 #define GFX7_3DSTATE_BINDING_TABLE_POINTERS_HS_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_HS_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BINDING_TABLE_POINTERS_HS_DWordLength_start 0 #define GFX12_3DSTATE_BINDING_TABLE_POINTERS_HS_DWordLength_start 0 #define GFX11_3DSTATE_BINDING_TABLE_POINTERS_HS_DWordLength_start 0 #define GFX9_3DSTATE_BINDING_TABLE_POINTERS_HS_DWordLength_start 0 #define GFX8_3DSTATE_BINDING_TABLE_POINTERS_HS_DWordLength_start 0 #define GFX75_3DSTATE_BINDING_TABLE_POINTERS_HS_DWordLength_start 0 #define GFX7_3DSTATE_BINDING_TABLE_POINTERS_HS_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_HS_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_POINTERS_HS::Pointer to HS Binding Table */ #define GFX125_3DSTATE_BINDING_TABLE_POINTERS_HS_PointertoHSBindingTable_bits 16 #define GFX12_3DSTATE_BINDING_TABLE_POINTERS_HS_PointertoHSBindingTable_bits 11 #define GFX11_3DSTATE_BINDING_TABLE_POINTERS_HS_PointertoHSBindingTable_bits 11 #define GFX9_3DSTATE_BINDING_TABLE_POINTERS_HS_PointertoHSBindingTable_bits 11 #define GFX8_3DSTATE_BINDING_TABLE_POINTERS_HS_PointertoHSBindingTable_bits 11 #define GFX75_3DSTATE_BINDING_TABLE_POINTERS_HS_PointertoHSBindingTable_bits 11 #define GFX7_3DSTATE_BINDING_TABLE_POINTERS_HS_PointertoHSBindingTable_bits 11 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_HS_PointertoHSBindingTable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 11; case 110: return 11; case 90: return 11; case 80: return 11; case 75: return 11; case 70: return 11; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BINDING_TABLE_POINTERS_HS_PointertoHSBindingTable_start 37 #define GFX12_3DSTATE_BINDING_TABLE_POINTERS_HS_PointertoHSBindingTable_start 37 #define GFX11_3DSTATE_BINDING_TABLE_POINTERS_HS_PointertoHSBindingTable_start 37 #define GFX9_3DSTATE_BINDING_TABLE_POINTERS_HS_PointertoHSBindingTable_start 37 #define GFX8_3DSTATE_BINDING_TABLE_POINTERS_HS_PointertoHSBindingTable_start 37 #define GFX75_3DSTATE_BINDING_TABLE_POINTERS_HS_PointertoHSBindingTable_start 37 #define GFX7_3DSTATE_BINDING_TABLE_POINTERS_HS_PointertoHSBindingTable_start 37 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_HS_PointertoHSBindingTable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 37; case 120: return 37; case 110: return 37; case 90: return 37; case 80: return 37; case 75: return 37; case 70: return 37; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_POINTERS_PS */ #define GFX125_3DSTATE_BINDING_TABLE_POINTERS_PS_length 2 #define GFX12_3DSTATE_BINDING_TABLE_POINTERS_PS_length 2 #define GFX11_3DSTATE_BINDING_TABLE_POINTERS_PS_length 2 #define GFX9_3DSTATE_BINDING_TABLE_POINTERS_PS_length 2 #define GFX8_3DSTATE_BINDING_TABLE_POINTERS_PS_length 2 #define GFX75_3DSTATE_BINDING_TABLE_POINTERS_PS_length 2 #define GFX7_3DSTATE_BINDING_TABLE_POINTERS_PS_length 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_PS_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_POINTERS_PS::3D Command Opcode */ #define GFX125_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandOpcode_bits 3 #define GFX75_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandOpcode_bits 3 #define GFX7_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandOpcode_start 24 #define GFX12_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandOpcode_start 24 #define GFX11_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandOpcode_start 24 #define GFX9_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandOpcode_start 24 #define GFX8_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandOpcode_start 24 #define GFX75_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandOpcode_start 24 #define GFX7_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_POINTERS_PS::3D Command Sub Opcode */ #define GFX125_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandSubOpcode_bits 8 #define GFX75_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandSubOpcode_bits 8 #define GFX7_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandSubOpcode_start 16 #define GFX75_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandSubOpcode_start 16 #define GFX7_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_POINTERS_PS::Command SubType */ #define GFX125_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandSubType_bits 2 #define GFX12_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandSubType_bits 2 #define GFX11_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandSubType_bits 2 #define GFX9_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandSubType_bits 2 #define GFX8_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandSubType_bits 2 #define GFX75_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandSubType_bits 2 #define GFX7_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_PS_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandSubType_start 27 #define GFX12_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandSubType_start 27 #define GFX11_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandSubType_start 27 #define GFX9_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandSubType_start 27 #define GFX8_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandSubType_start 27 #define GFX75_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandSubType_start 27 #define GFX7_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_PS_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_POINTERS_PS::Command Type */ #define GFX125_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandType_bits 3 #define GFX12_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandType_bits 3 #define GFX11_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandType_bits 3 #define GFX9_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandType_bits 3 #define GFX8_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandType_bits 3 #define GFX75_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandType_bits 3 #define GFX7_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_PS_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandType_start 29 #define GFX12_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandType_start 29 #define GFX11_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandType_start 29 #define GFX9_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandType_start 29 #define GFX8_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandType_start 29 #define GFX75_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandType_start 29 #define GFX7_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_PS_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_POINTERS_PS::DWord Length */ #define GFX125_3DSTATE_BINDING_TABLE_POINTERS_PS_DWordLength_bits 8 #define GFX12_3DSTATE_BINDING_TABLE_POINTERS_PS_DWordLength_bits 8 #define GFX11_3DSTATE_BINDING_TABLE_POINTERS_PS_DWordLength_bits 8 #define GFX9_3DSTATE_BINDING_TABLE_POINTERS_PS_DWordLength_bits 8 #define GFX8_3DSTATE_BINDING_TABLE_POINTERS_PS_DWordLength_bits 8 #define GFX75_3DSTATE_BINDING_TABLE_POINTERS_PS_DWordLength_bits 8 #define GFX7_3DSTATE_BINDING_TABLE_POINTERS_PS_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_PS_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BINDING_TABLE_POINTERS_PS_DWordLength_start 0 #define GFX12_3DSTATE_BINDING_TABLE_POINTERS_PS_DWordLength_start 0 #define GFX11_3DSTATE_BINDING_TABLE_POINTERS_PS_DWordLength_start 0 #define GFX9_3DSTATE_BINDING_TABLE_POINTERS_PS_DWordLength_start 0 #define GFX8_3DSTATE_BINDING_TABLE_POINTERS_PS_DWordLength_start 0 #define GFX75_3DSTATE_BINDING_TABLE_POINTERS_PS_DWordLength_start 0 #define GFX7_3DSTATE_BINDING_TABLE_POINTERS_PS_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_PS_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_POINTERS_PS::Pointer to PS Binding Table */ #define GFX125_3DSTATE_BINDING_TABLE_POINTERS_PS_PointertoPSBindingTable_bits 16 #define GFX12_3DSTATE_BINDING_TABLE_POINTERS_PS_PointertoPSBindingTable_bits 11 #define GFX11_3DSTATE_BINDING_TABLE_POINTERS_PS_PointertoPSBindingTable_bits 11 #define GFX9_3DSTATE_BINDING_TABLE_POINTERS_PS_PointertoPSBindingTable_bits 11 #define GFX8_3DSTATE_BINDING_TABLE_POINTERS_PS_PointertoPSBindingTable_bits 11 #define GFX75_3DSTATE_BINDING_TABLE_POINTERS_PS_PointertoPSBindingTable_bits 11 #define GFX7_3DSTATE_BINDING_TABLE_POINTERS_PS_PointertoPSBindingTable_bits 11 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_PS_PointertoPSBindingTable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 11; case 110: return 11; case 90: return 11; case 80: return 11; case 75: return 11; case 70: return 11; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BINDING_TABLE_POINTERS_PS_PointertoPSBindingTable_start 37 #define GFX12_3DSTATE_BINDING_TABLE_POINTERS_PS_PointertoPSBindingTable_start 37 #define GFX11_3DSTATE_BINDING_TABLE_POINTERS_PS_PointertoPSBindingTable_start 37 #define GFX9_3DSTATE_BINDING_TABLE_POINTERS_PS_PointertoPSBindingTable_start 37 #define GFX8_3DSTATE_BINDING_TABLE_POINTERS_PS_PointertoPSBindingTable_start 37 #define GFX75_3DSTATE_BINDING_TABLE_POINTERS_PS_PointertoPSBindingTable_start 37 #define GFX7_3DSTATE_BINDING_TABLE_POINTERS_PS_PointertoPSBindingTable_start 37 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_PS_PointertoPSBindingTable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 37; case 120: return 37; case 110: return 37; case 90: return 37; case 80: return 37; case 75: return 37; case 70: return 37; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_POINTERS_VS */ #define GFX125_3DSTATE_BINDING_TABLE_POINTERS_VS_length 2 #define GFX12_3DSTATE_BINDING_TABLE_POINTERS_VS_length 2 #define GFX11_3DSTATE_BINDING_TABLE_POINTERS_VS_length 2 #define GFX9_3DSTATE_BINDING_TABLE_POINTERS_VS_length 2 #define GFX8_3DSTATE_BINDING_TABLE_POINTERS_VS_length 2 #define GFX75_3DSTATE_BINDING_TABLE_POINTERS_VS_length 2 #define GFX7_3DSTATE_BINDING_TABLE_POINTERS_VS_length 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_VS_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_POINTERS_VS::3D Command Opcode */ #define GFX125_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandOpcode_bits 3 #define GFX75_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandOpcode_bits 3 #define GFX7_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandOpcode_start 24 #define GFX12_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandOpcode_start 24 #define GFX11_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandOpcode_start 24 #define GFX9_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandOpcode_start 24 #define GFX8_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandOpcode_start 24 #define GFX75_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandOpcode_start 24 #define GFX7_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_POINTERS_VS::3D Command Sub Opcode */ #define GFX125_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandSubOpcode_bits 8 #define GFX75_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandSubOpcode_bits 8 #define GFX7_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandSubOpcode_start 16 #define GFX75_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandSubOpcode_start 16 #define GFX7_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_POINTERS_VS::Command SubType */ #define GFX125_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandSubType_bits 2 #define GFX12_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandSubType_bits 2 #define GFX11_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandSubType_bits 2 #define GFX9_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandSubType_bits 2 #define GFX8_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandSubType_bits 2 #define GFX75_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandSubType_bits 2 #define GFX7_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_VS_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandSubType_start 27 #define GFX12_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandSubType_start 27 #define GFX11_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandSubType_start 27 #define GFX9_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandSubType_start 27 #define GFX8_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandSubType_start 27 #define GFX75_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandSubType_start 27 #define GFX7_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_VS_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_POINTERS_VS::Command Type */ #define GFX125_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandType_bits 3 #define GFX12_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandType_bits 3 #define GFX11_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandType_bits 3 #define GFX9_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandType_bits 3 #define GFX8_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandType_bits 3 #define GFX75_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandType_bits 3 #define GFX7_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_VS_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandType_start 29 #define GFX12_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandType_start 29 #define GFX11_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandType_start 29 #define GFX9_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandType_start 29 #define GFX8_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandType_start 29 #define GFX75_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandType_start 29 #define GFX7_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_VS_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_POINTERS_VS::DWord Length */ #define GFX125_3DSTATE_BINDING_TABLE_POINTERS_VS_DWordLength_bits 8 #define GFX12_3DSTATE_BINDING_TABLE_POINTERS_VS_DWordLength_bits 8 #define GFX11_3DSTATE_BINDING_TABLE_POINTERS_VS_DWordLength_bits 8 #define GFX9_3DSTATE_BINDING_TABLE_POINTERS_VS_DWordLength_bits 8 #define GFX8_3DSTATE_BINDING_TABLE_POINTERS_VS_DWordLength_bits 8 #define GFX75_3DSTATE_BINDING_TABLE_POINTERS_VS_DWordLength_bits 8 #define GFX7_3DSTATE_BINDING_TABLE_POINTERS_VS_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_VS_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BINDING_TABLE_POINTERS_VS_DWordLength_start 0 #define GFX12_3DSTATE_BINDING_TABLE_POINTERS_VS_DWordLength_start 0 #define GFX11_3DSTATE_BINDING_TABLE_POINTERS_VS_DWordLength_start 0 #define GFX9_3DSTATE_BINDING_TABLE_POINTERS_VS_DWordLength_start 0 #define GFX8_3DSTATE_BINDING_TABLE_POINTERS_VS_DWordLength_start 0 #define GFX75_3DSTATE_BINDING_TABLE_POINTERS_VS_DWordLength_start 0 #define GFX7_3DSTATE_BINDING_TABLE_POINTERS_VS_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_VS_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_POINTERS_VS::Pointer to VS Binding Table */ #define GFX125_3DSTATE_BINDING_TABLE_POINTERS_VS_PointertoVSBindingTable_bits 16 #define GFX12_3DSTATE_BINDING_TABLE_POINTERS_VS_PointertoVSBindingTable_bits 11 #define GFX11_3DSTATE_BINDING_TABLE_POINTERS_VS_PointertoVSBindingTable_bits 11 #define GFX9_3DSTATE_BINDING_TABLE_POINTERS_VS_PointertoVSBindingTable_bits 11 #define GFX8_3DSTATE_BINDING_TABLE_POINTERS_VS_PointertoVSBindingTable_bits 11 #define GFX75_3DSTATE_BINDING_TABLE_POINTERS_VS_PointertoVSBindingTable_bits 11 #define GFX7_3DSTATE_BINDING_TABLE_POINTERS_VS_PointertoVSBindingTable_bits 11 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_VS_PointertoVSBindingTable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 11; case 110: return 11; case 90: return 11; case 80: return 11; case 75: return 11; case 70: return 11; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BINDING_TABLE_POINTERS_VS_PointertoVSBindingTable_start 37 #define GFX12_3DSTATE_BINDING_TABLE_POINTERS_VS_PointertoVSBindingTable_start 37 #define GFX11_3DSTATE_BINDING_TABLE_POINTERS_VS_PointertoVSBindingTable_start 37 #define GFX9_3DSTATE_BINDING_TABLE_POINTERS_VS_PointertoVSBindingTable_start 37 #define GFX8_3DSTATE_BINDING_TABLE_POINTERS_VS_PointertoVSBindingTable_start 37 #define GFX75_3DSTATE_BINDING_TABLE_POINTERS_VS_PointertoVSBindingTable_start 37 #define GFX7_3DSTATE_BINDING_TABLE_POINTERS_VS_PointertoVSBindingTable_start 37 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POINTERS_VS_PointertoVSBindingTable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 37; case 120: return 37; case 110: return 37; case 90: return 37; case 80: return 37; case 75: return 37; case 70: return 37; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_POOL_ALLOC */ #define GFX125_3DSTATE_BINDING_TABLE_POOL_ALLOC_length 4 #define GFX12_3DSTATE_BINDING_TABLE_POOL_ALLOC_length 4 #define GFX11_3DSTATE_BINDING_TABLE_POOL_ALLOC_length 4 #define GFX9_3DSTATE_BINDING_TABLE_POOL_ALLOC_length 4 #define GFX8_3DSTATE_BINDING_TABLE_POOL_ALLOC_length 4 #define GFX75_3DSTATE_BINDING_TABLE_POOL_ALLOC_length 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POOL_ALLOC_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 3; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_POOL_ALLOC::3D Command Opcode */ #define GFX125_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandOpcode_bits 3 #define GFX75_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandOpcode_start 24 #define GFX12_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandOpcode_start 24 #define GFX11_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandOpcode_start 24 #define GFX9_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandOpcode_start 24 #define GFX8_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandOpcode_start 24 #define GFX75_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_POOL_ALLOC::3D Command Sub Opcode */ #define GFX125_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandSubOpcode_bits 8 #define GFX75_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandSubOpcode_start 16 #define GFX75_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_POOL_ALLOC::Binding Table Pool Base Address */ #define GFX125_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBaseAddress_bits 52 #define GFX12_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBaseAddress_bits 52 #define GFX11_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBaseAddress_bits 52 #define GFX9_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBaseAddress_bits 52 #define GFX8_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBaseAddress_bits 52 #define GFX75_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBaseAddress_bits 20 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBaseAddress_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 52; case 120: return 52; case 110: return 52; case 90: return 52; case 80: return 52; case 75: return 20; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBaseAddress_start 44 #define GFX12_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBaseAddress_start 44 #define GFX11_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBaseAddress_start 44 #define GFX9_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBaseAddress_start 44 #define GFX8_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBaseAddress_start 44 #define GFX75_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBaseAddress_start 44 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBaseAddress_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 44; case 120: return 44; case 110: return 44; case 90: return 44; case 80: return 44; case 75: return 44; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_POOL_ALLOC::Binding Table Pool Buffer Size */ #define GFX125_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBufferSize_bits 20 #define GFX12_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBufferSize_bits 20 #define GFX11_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBufferSize_bits 20 #define GFX9_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBufferSize_bits 20 #define GFX8_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBufferSize_bits 20 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBufferSize_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 20; case 120: return 20; case 110: return 20; case 90: return 20; case 80: return 20; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBufferSize_start 108 #define GFX12_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBufferSize_start 108 #define GFX11_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBufferSize_start 108 #define GFX9_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBufferSize_start 108 #define GFX8_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBufferSize_start 108 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBufferSize_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 108; case 120: return 108; case 110: return 108; case 90: return 108; case 80: return 108; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_POOL_ALLOC::Binding Table Pool Enable */ #define GFX125_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolEnable_bits 1 #define GFX12_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolEnable_bits 1 #define GFX11_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolEnable_bits 1 #define GFX9_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolEnable_bits 1 #define GFX8_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolEnable_bits 1 #define GFX75_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolEnable_start 43 #define GFX12_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolEnable_start 43 #define GFX11_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolEnable_start 43 #define GFX9_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolEnable_start 43 #define GFX8_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolEnable_start 43 #define GFX75_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolEnable_start 43 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 43; case 120: return 43; case 110: return 43; case 90: return 43; case 80: return 43; case 75: return 43; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_POOL_ALLOC::Binding Table Pool Upper Bound */ #define GFX75_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolUpperBound_bits 20 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolUpperBound_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 20; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolUpperBound_start 76 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolUpperBound_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 76; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_POOL_ALLOC::Command SubType */ #define GFX125_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandSubType_bits 2 #define GFX12_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandSubType_bits 2 #define GFX11_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandSubType_bits 2 #define GFX9_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandSubType_bits 2 #define GFX8_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandSubType_bits 2 #define GFX75_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandSubType_start 27 #define GFX12_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandSubType_start 27 #define GFX11_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandSubType_start 27 #define GFX9_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandSubType_start 27 #define GFX8_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandSubType_start 27 #define GFX75_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_POOL_ALLOC::Command Type */ #define GFX125_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandType_bits 3 #define GFX12_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandType_bits 3 #define GFX11_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandType_bits 3 #define GFX9_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandType_bits 3 #define GFX8_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandType_bits 3 #define GFX75_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandType_start 29 #define GFX12_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandType_start 29 #define GFX11_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandType_start 29 #define GFX9_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandType_start 29 #define GFX8_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandType_start 29 #define GFX75_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_POOL_ALLOC::DWord Length */ #define GFX125_3DSTATE_BINDING_TABLE_POOL_ALLOC_DWordLength_bits 8 #define GFX12_3DSTATE_BINDING_TABLE_POOL_ALLOC_DWordLength_bits 8 #define GFX11_3DSTATE_BINDING_TABLE_POOL_ALLOC_DWordLength_bits 8 #define GFX9_3DSTATE_BINDING_TABLE_POOL_ALLOC_DWordLength_bits 8 #define GFX8_3DSTATE_BINDING_TABLE_POOL_ALLOC_DWordLength_bits 8 #define GFX75_3DSTATE_BINDING_TABLE_POOL_ALLOC_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POOL_ALLOC_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BINDING_TABLE_POOL_ALLOC_DWordLength_start 0 #define GFX12_3DSTATE_BINDING_TABLE_POOL_ALLOC_DWordLength_start 0 #define GFX11_3DSTATE_BINDING_TABLE_POOL_ALLOC_DWordLength_start 0 #define GFX9_3DSTATE_BINDING_TABLE_POOL_ALLOC_DWordLength_start 0 #define GFX8_3DSTATE_BINDING_TABLE_POOL_ALLOC_DWordLength_start 0 #define GFX75_3DSTATE_BINDING_TABLE_POOL_ALLOC_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POOL_ALLOC_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BINDING_TABLE_POOL_ALLOC::MOCS */ #define GFX125_3DSTATE_BINDING_TABLE_POOL_ALLOC_MOCS_bits 7 #define GFX12_3DSTATE_BINDING_TABLE_POOL_ALLOC_MOCS_bits 7 #define GFX11_3DSTATE_BINDING_TABLE_POOL_ALLOC_MOCS_bits 7 #define GFX9_3DSTATE_BINDING_TABLE_POOL_ALLOC_MOCS_bits 7 #define GFX8_3DSTATE_BINDING_TABLE_POOL_ALLOC_MOCS_bits 7 #define GFX75_3DSTATE_BINDING_TABLE_POOL_ALLOC_MOCS_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POOL_ALLOC_MOCS_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 7; case 120: return 7; case 110: return 7; case 90: return 7; case 80: return 7; case 75: return 4; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BINDING_TABLE_POOL_ALLOC_MOCS_start 32 #define GFX12_3DSTATE_BINDING_TABLE_POOL_ALLOC_MOCS_start 32 #define GFX11_3DSTATE_BINDING_TABLE_POOL_ALLOC_MOCS_start 32 #define GFX9_3DSTATE_BINDING_TABLE_POOL_ALLOC_MOCS_start 32 #define GFX8_3DSTATE_BINDING_TABLE_POOL_ALLOC_MOCS_start 32 #define GFX75_3DSTATE_BINDING_TABLE_POOL_ALLOC_MOCS_start 39 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BINDING_TABLE_POOL_ALLOC_MOCS_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 39; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BLEND_STATE_POINTERS */ #define GFX125_3DSTATE_BLEND_STATE_POINTERS_length 2 #define GFX12_3DSTATE_BLEND_STATE_POINTERS_length 2 #define GFX11_3DSTATE_BLEND_STATE_POINTERS_length 2 #define GFX9_3DSTATE_BLEND_STATE_POINTERS_length 2 #define GFX8_3DSTATE_BLEND_STATE_POINTERS_length 2 #define GFX75_3DSTATE_BLEND_STATE_POINTERS_length 2 #define GFX7_3DSTATE_BLEND_STATE_POINTERS_length 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BLEND_STATE_POINTERS_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BLEND_STATE_POINTERS::3D Command Opcode */ #define GFX125_3DSTATE_BLEND_STATE_POINTERS_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_BLEND_STATE_POINTERS_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_BLEND_STATE_POINTERS_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_BLEND_STATE_POINTERS_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_BLEND_STATE_POINTERS_3DCommandOpcode_bits 3 #define GFX75_3DSTATE_BLEND_STATE_POINTERS_3DCommandOpcode_bits 3 #define GFX7_3DSTATE_BLEND_STATE_POINTERS_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BLEND_STATE_POINTERS_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BLEND_STATE_POINTERS_3DCommandOpcode_start 24 #define GFX12_3DSTATE_BLEND_STATE_POINTERS_3DCommandOpcode_start 24 #define GFX11_3DSTATE_BLEND_STATE_POINTERS_3DCommandOpcode_start 24 #define GFX9_3DSTATE_BLEND_STATE_POINTERS_3DCommandOpcode_start 24 #define GFX8_3DSTATE_BLEND_STATE_POINTERS_3DCommandOpcode_start 24 #define GFX75_3DSTATE_BLEND_STATE_POINTERS_3DCommandOpcode_start 24 #define GFX7_3DSTATE_BLEND_STATE_POINTERS_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BLEND_STATE_POINTERS_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BLEND_STATE_POINTERS::3D Command Sub Opcode */ #define GFX125_3DSTATE_BLEND_STATE_POINTERS_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_BLEND_STATE_POINTERS_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_BLEND_STATE_POINTERS_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_BLEND_STATE_POINTERS_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_BLEND_STATE_POINTERS_3DCommandSubOpcode_bits 8 #define GFX75_3DSTATE_BLEND_STATE_POINTERS_3DCommandSubOpcode_bits 8 #define GFX7_3DSTATE_BLEND_STATE_POINTERS_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BLEND_STATE_POINTERS_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BLEND_STATE_POINTERS_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_BLEND_STATE_POINTERS_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_BLEND_STATE_POINTERS_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_BLEND_STATE_POINTERS_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_BLEND_STATE_POINTERS_3DCommandSubOpcode_start 16 #define GFX75_3DSTATE_BLEND_STATE_POINTERS_3DCommandSubOpcode_start 16 #define GFX7_3DSTATE_BLEND_STATE_POINTERS_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BLEND_STATE_POINTERS_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BLEND_STATE_POINTERS::Blend State Pointer */ #define GFX125_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointer_bits 26 #define GFX12_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointer_bits 26 #define GFX11_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointer_bits 26 #define GFX9_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointer_bits 26 #define GFX8_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointer_bits 26 #define GFX75_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointer_bits 26 #define GFX7_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointer_bits 26 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BLEND_STATE_POINTERS_BlendStatePointer_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 26; case 120: return 26; case 110: return 26; case 90: return 26; case 80: return 26; case 75: return 26; case 70: return 26; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointer_start 38 #define GFX12_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointer_start 38 #define GFX11_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointer_start 38 #define GFX9_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointer_start 38 #define GFX8_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointer_start 38 #define GFX75_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointer_start 38 #define GFX7_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointer_start 38 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BLEND_STATE_POINTERS_BlendStatePointer_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 38; case 120: return 38; case 110: return 38; case 90: return 38; case 80: return 38; case 75: return 38; case 70: return 38; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BLEND_STATE_POINTERS::Blend State Pointer Valid */ #define GFX125_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointerValid_bits 1 #define GFX12_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointerValid_bits 1 #define GFX11_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointerValid_bits 1 #define GFX9_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointerValid_bits 1 #define GFX8_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointerValid_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BLEND_STATE_POINTERS_BlendStatePointerValid_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointerValid_start 32 #define GFX12_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointerValid_start 32 #define GFX11_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointerValid_start 32 #define GFX9_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointerValid_start 32 #define GFX8_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointerValid_start 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BLEND_STATE_POINTERS_BlendStatePointerValid_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BLEND_STATE_POINTERS::Command SubType */ #define GFX125_3DSTATE_BLEND_STATE_POINTERS_CommandSubType_bits 2 #define GFX12_3DSTATE_BLEND_STATE_POINTERS_CommandSubType_bits 2 #define GFX11_3DSTATE_BLEND_STATE_POINTERS_CommandSubType_bits 2 #define GFX9_3DSTATE_BLEND_STATE_POINTERS_CommandSubType_bits 2 #define GFX8_3DSTATE_BLEND_STATE_POINTERS_CommandSubType_bits 2 #define GFX75_3DSTATE_BLEND_STATE_POINTERS_CommandSubType_bits 2 #define GFX7_3DSTATE_BLEND_STATE_POINTERS_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BLEND_STATE_POINTERS_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BLEND_STATE_POINTERS_CommandSubType_start 27 #define GFX12_3DSTATE_BLEND_STATE_POINTERS_CommandSubType_start 27 #define GFX11_3DSTATE_BLEND_STATE_POINTERS_CommandSubType_start 27 #define GFX9_3DSTATE_BLEND_STATE_POINTERS_CommandSubType_start 27 #define GFX8_3DSTATE_BLEND_STATE_POINTERS_CommandSubType_start 27 #define GFX75_3DSTATE_BLEND_STATE_POINTERS_CommandSubType_start 27 #define GFX7_3DSTATE_BLEND_STATE_POINTERS_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BLEND_STATE_POINTERS_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BLEND_STATE_POINTERS::Command Type */ #define GFX125_3DSTATE_BLEND_STATE_POINTERS_CommandType_bits 3 #define GFX12_3DSTATE_BLEND_STATE_POINTERS_CommandType_bits 3 #define GFX11_3DSTATE_BLEND_STATE_POINTERS_CommandType_bits 3 #define GFX9_3DSTATE_BLEND_STATE_POINTERS_CommandType_bits 3 #define GFX8_3DSTATE_BLEND_STATE_POINTERS_CommandType_bits 3 #define GFX75_3DSTATE_BLEND_STATE_POINTERS_CommandType_bits 3 #define GFX7_3DSTATE_BLEND_STATE_POINTERS_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BLEND_STATE_POINTERS_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BLEND_STATE_POINTERS_CommandType_start 29 #define GFX12_3DSTATE_BLEND_STATE_POINTERS_CommandType_start 29 #define GFX11_3DSTATE_BLEND_STATE_POINTERS_CommandType_start 29 #define GFX9_3DSTATE_BLEND_STATE_POINTERS_CommandType_start 29 #define GFX8_3DSTATE_BLEND_STATE_POINTERS_CommandType_start 29 #define GFX75_3DSTATE_BLEND_STATE_POINTERS_CommandType_start 29 #define GFX7_3DSTATE_BLEND_STATE_POINTERS_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BLEND_STATE_POINTERS_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_BLEND_STATE_POINTERS::DWord Length */ #define GFX125_3DSTATE_BLEND_STATE_POINTERS_DWordLength_bits 8 #define GFX12_3DSTATE_BLEND_STATE_POINTERS_DWordLength_bits 8 #define GFX11_3DSTATE_BLEND_STATE_POINTERS_DWordLength_bits 8 #define GFX9_3DSTATE_BLEND_STATE_POINTERS_DWordLength_bits 8 #define GFX8_3DSTATE_BLEND_STATE_POINTERS_DWordLength_bits 8 #define GFX75_3DSTATE_BLEND_STATE_POINTERS_DWordLength_bits 8 #define GFX7_3DSTATE_BLEND_STATE_POINTERS_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BLEND_STATE_POINTERS_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_BLEND_STATE_POINTERS_DWordLength_start 0 #define GFX12_3DSTATE_BLEND_STATE_POINTERS_DWordLength_start 0 #define GFX11_3DSTATE_BLEND_STATE_POINTERS_DWordLength_start 0 #define GFX9_3DSTATE_BLEND_STATE_POINTERS_DWordLength_start 0 #define GFX8_3DSTATE_BLEND_STATE_POINTERS_DWordLength_start 0 #define GFX75_3DSTATE_BLEND_STATE_POINTERS_DWordLength_start 0 #define GFX7_3DSTATE_BLEND_STATE_POINTERS_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_BLEND_STATE_POINTERS_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CC_STATE_POINTERS */ #define GFX125_3DSTATE_CC_STATE_POINTERS_length 2 #define GFX12_3DSTATE_CC_STATE_POINTERS_length 2 #define GFX11_3DSTATE_CC_STATE_POINTERS_length 2 #define GFX9_3DSTATE_CC_STATE_POINTERS_length 2 #define GFX8_3DSTATE_CC_STATE_POINTERS_length 2 #define GFX75_3DSTATE_CC_STATE_POINTERS_length 2 #define GFX7_3DSTATE_CC_STATE_POINTERS_length 2 #define GFX6_3DSTATE_CC_STATE_POINTERS_length 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CC_STATE_POINTERS_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CC_STATE_POINTERS::3D Command Opcode */ #define GFX125_3DSTATE_CC_STATE_POINTERS_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_CC_STATE_POINTERS_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_CC_STATE_POINTERS_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_CC_STATE_POINTERS_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_CC_STATE_POINTERS_3DCommandOpcode_bits 3 #define GFX75_3DSTATE_CC_STATE_POINTERS_3DCommandOpcode_bits 3 #define GFX7_3DSTATE_CC_STATE_POINTERS_3DCommandOpcode_bits 3 #define GFX6_3DSTATE_CC_STATE_POINTERS_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CC_STATE_POINTERS_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CC_STATE_POINTERS_3DCommandOpcode_start 24 #define GFX12_3DSTATE_CC_STATE_POINTERS_3DCommandOpcode_start 24 #define GFX11_3DSTATE_CC_STATE_POINTERS_3DCommandOpcode_start 24 #define GFX9_3DSTATE_CC_STATE_POINTERS_3DCommandOpcode_start 24 #define GFX8_3DSTATE_CC_STATE_POINTERS_3DCommandOpcode_start 24 #define GFX75_3DSTATE_CC_STATE_POINTERS_3DCommandOpcode_start 24 #define GFX7_3DSTATE_CC_STATE_POINTERS_3DCommandOpcode_start 24 #define GFX6_3DSTATE_CC_STATE_POINTERS_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CC_STATE_POINTERS_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 24; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CC_STATE_POINTERS::3D Command Sub Opcode */ #define GFX125_3DSTATE_CC_STATE_POINTERS_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_CC_STATE_POINTERS_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_CC_STATE_POINTERS_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_CC_STATE_POINTERS_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_CC_STATE_POINTERS_3DCommandSubOpcode_bits 8 #define GFX75_3DSTATE_CC_STATE_POINTERS_3DCommandSubOpcode_bits 8 #define GFX7_3DSTATE_CC_STATE_POINTERS_3DCommandSubOpcode_bits 8 #define GFX6_3DSTATE_CC_STATE_POINTERS_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CC_STATE_POINTERS_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CC_STATE_POINTERS_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_CC_STATE_POINTERS_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_CC_STATE_POINTERS_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_CC_STATE_POINTERS_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_CC_STATE_POINTERS_3DCommandSubOpcode_start 16 #define GFX75_3DSTATE_CC_STATE_POINTERS_3DCommandSubOpcode_start 16 #define GFX7_3DSTATE_CC_STATE_POINTERS_3DCommandSubOpcode_start 16 #define GFX6_3DSTATE_CC_STATE_POINTERS_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CC_STATE_POINTERS_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 16; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CC_STATE_POINTERS::BLEND_STATE Change */ #define GFX6_3DSTATE_CC_STATE_POINTERS_BLEND_STATEChange_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CC_STATE_POINTERS_BLEND_STATEChange_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_CC_STATE_POINTERS_BLEND_STATEChange_start 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CC_STATE_POINTERS_BLEND_STATEChange_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 32; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CC_STATE_POINTERS::Color Calc State Pointer */ #define GFX125_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointer_bits 26 #define GFX12_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointer_bits 26 #define GFX11_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointer_bits 26 #define GFX9_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointer_bits 26 #define GFX8_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointer_bits 26 #define GFX75_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointer_bits 26 #define GFX7_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointer_bits 26 #define GFX6_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointer_bits 26 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointer_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 26; case 120: return 26; case 110: return 26; case 90: return 26; case 80: return 26; case 75: return 26; case 70: return 26; case 60: return 26; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointer_start 38 #define GFX12_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointer_start 38 #define GFX11_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointer_start 38 #define GFX9_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointer_start 38 #define GFX8_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointer_start 38 #define GFX75_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointer_start 38 #define GFX7_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointer_start 38 #define GFX6_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointer_start 102 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointer_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 38; case 120: return 38; case 110: return 38; case 90: return 38; case 80: return 38; case 75: return 38; case 70: return 38; case 60: return 102; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CC_STATE_POINTERS::Color Calc State Pointer Valid */ #define GFX125_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointerValid_bits 1 #define GFX12_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointerValid_bits 1 #define GFX11_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointerValid_bits 1 #define GFX9_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointerValid_bits 1 #define GFX8_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointerValid_bits 1 #define GFX6_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointerValid_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointerValid_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointerValid_start 32 #define GFX12_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointerValid_start 32 #define GFX11_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointerValid_start 32 #define GFX9_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointerValid_start 32 #define GFX8_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointerValid_start 32 #define GFX6_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointerValid_start 96 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointerValid_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 0; case 70: return 0; case 60: return 96; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CC_STATE_POINTERS::Command SubType */ #define GFX125_3DSTATE_CC_STATE_POINTERS_CommandSubType_bits 2 #define GFX12_3DSTATE_CC_STATE_POINTERS_CommandSubType_bits 2 #define GFX11_3DSTATE_CC_STATE_POINTERS_CommandSubType_bits 2 #define GFX9_3DSTATE_CC_STATE_POINTERS_CommandSubType_bits 2 #define GFX8_3DSTATE_CC_STATE_POINTERS_CommandSubType_bits 2 #define GFX75_3DSTATE_CC_STATE_POINTERS_CommandSubType_bits 2 #define GFX7_3DSTATE_CC_STATE_POINTERS_CommandSubType_bits 2 #define GFX6_3DSTATE_CC_STATE_POINTERS_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CC_STATE_POINTERS_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CC_STATE_POINTERS_CommandSubType_start 27 #define GFX12_3DSTATE_CC_STATE_POINTERS_CommandSubType_start 27 #define GFX11_3DSTATE_CC_STATE_POINTERS_CommandSubType_start 27 #define GFX9_3DSTATE_CC_STATE_POINTERS_CommandSubType_start 27 #define GFX8_3DSTATE_CC_STATE_POINTERS_CommandSubType_start 27 #define GFX75_3DSTATE_CC_STATE_POINTERS_CommandSubType_start 27 #define GFX7_3DSTATE_CC_STATE_POINTERS_CommandSubType_start 27 #define GFX6_3DSTATE_CC_STATE_POINTERS_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CC_STATE_POINTERS_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 27; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CC_STATE_POINTERS::Command Type */ #define GFX125_3DSTATE_CC_STATE_POINTERS_CommandType_bits 3 #define GFX12_3DSTATE_CC_STATE_POINTERS_CommandType_bits 3 #define GFX11_3DSTATE_CC_STATE_POINTERS_CommandType_bits 3 #define GFX9_3DSTATE_CC_STATE_POINTERS_CommandType_bits 3 #define GFX8_3DSTATE_CC_STATE_POINTERS_CommandType_bits 3 #define GFX75_3DSTATE_CC_STATE_POINTERS_CommandType_bits 3 #define GFX7_3DSTATE_CC_STATE_POINTERS_CommandType_bits 3 #define GFX6_3DSTATE_CC_STATE_POINTERS_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CC_STATE_POINTERS_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CC_STATE_POINTERS_CommandType_start 29 #define GFX12_3DSTATE_CC_STATE_POINTERS_CommandType_start 29 #define GFX11_3DSTATE_CC_STATE_POINTERS_CommandType_start 29 #define GFX9_3DSTATE_CC_STATE_POINTERS_CommandType_start 29 #define GFX8_3DSTATE_CC_STATE_POINTERS_CommandType_start 29 #define GFX75_3DSTATE_CC_STATE_POINTERS_CommandType_start 29 #define GFX7_3DSTATE_CC_STATE_POINTERS_CommandType_start 29 #define GFX6_3DSTATE_CC_STATE_POINTERS_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CC_STATE_POINTERS_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 29; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CC_STATE_POINTERS::DEPTH_STENCIL_STATE Change */ #define GFX6_3DSTATE_CC_STATE_POINTERS_DEPTH_STENCIL_STATEChange_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CC_STATE_POINTERS_DEPTH_STENCIL_STATEChange_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_CC_STATE_POINTERS_DEPTH_STENCIL_STATEChange_start 64 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CC_STATE_POINTERS_DEPTH_STENCIL_STATEChange_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 64; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CC_STATE_POINTERS::DWord Length */ #define GFX125_3DSTATE_CC_STATE_POINTERS_DWordLength_bits 8 #define GFX12_3DSTATE_CC_STATE_POINTERS_DWordLength_bits 8 #define GFX11_3DSTATE_CC_STATE_POINTERS_DWordLength_bits 8 #define GFX9_3DSTATE_CC_STATE_POINTERS_DWordLength_bits 8 #define GFX8_3DSTATE_CC_STATE_POINTERS_DWordLength_bits 8 #define GFX75_3DSTATE_CC_STATE_POINTERS_DWordLength_bits 8 #define GFX7_3DSTATE_CC_STATE_POINTERS_DWordLength_bits 8 #define GFX6_3DSTATE_CC_STATE_POINTERS_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CC_STATE_POINTERS_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CC_STATE_POINTERS_DWordLength_start 0 #define GFX12_3DSTATE_CC_STATE_POINTERS_DWordLength_start 0 #define GFX11_3DSTATE_CC_STATE_POINTERS_DWordLength_start 0 #define GFX9_3DSTATE_CC_STATE_POINTERS_DWordLength_start 0 #define GFX8_3DSTATE_CC_STATE_POINTERS_DWordLength_start 0 #define GFX75_3DSTATE_CC_STATE_POINTERS_DWordLength_start 0 #define GFX7_3DSTATE_CC_STATE_POINTERS_DWordLength_start 0 #define GFX6_3DSTATE_CC_STATE_POINTERS_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CC_STATE_POINTERS_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CC_STATE_POINTERS::Pointer to BLEND_STATE */ #define GFX6_3DSTATE_CC_STATE_POINTERS_PointertoBLEND_STATE_bits 26 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CC_STATE_POINTERS_PointertoBLEND_STATE_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 26; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_CC_STATE_POINTERS_PointertoBLEND_STATE_start 38 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CC_STATE_POINTERS_PointertoBLEND_STATE_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 38; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CC_STATE_POINTERS::Pointer to DEPTH_STENCIL_STATE */ #define GFX6_3DSTATE_CC_STATE_POINTERS_PointertoDEPTH_STENCIL_STATE_bits 26 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CC_STATE_POINTERS_PointertoDEPTH_STENCIL_STATE_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 26; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_CC_STATE_POINTERS_PointertoDEPTH_STENCIL_STATE_start 70 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CC_STATE_POINTERS_PointertoDEPTH_STENCIL_STATE_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 70; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CHROMA_KEY */ #define GFX125_3DSTATE_CHROMA_KEY_length 4 #define GFX12_3DSTATE_CHROMA_KEY_length 4 #define GFX11_3DSTATE_CHROMA_KEY_length 4 #define GFX9_3DSTATE_CHROMA_KEY_length 4 #define GFX8_3DSTATE_CHROMA_KEY_length 4 #define GFX75_3DSTATE_CHROMA_KEY_length 4 #define GFX7_3DSTATE_CHROMA_KEY_length 4 #define GFX6_3DSTATE_CHROMA_KEY_length 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CHROMA_KEY_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 4; case 70: return 4; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CHROMA_KEY::3D Command Opcode */ #define GFX125_3DSTATE_CHROMA_KEY_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_CHROMA_KEY_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_CHROMA_KEY_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_CHROMA_KEY_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_CHROMA_KEY_3DCommandOpcode_bits 3 #define GFX75_3DSTATE_CHROMA_KEY_3DCommandOpcode_bits 3 #define GFX7_3DSTATE_CHROMA_KEY_3DCommandOpcode_bits 3 #define GFX6_3DSTATE_CHROMA_KEY_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CHROMA_KEY_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CHROMA_KEY_3DCommandOpcode_start 24 #define GFX12_3DSTATE_CHROMA_KEY_3DCommandOpcode_start 24 #define GFX11_3DSTATE_CHROMA_KEY_3DCommandOpcode_start 24 #define GFX9_3DSTATE_CHROMA_KEY_3DCommandOpcode_start 24 #define GFX8_3DSTATE_CHROMA_KEY_3DCommandOpcode_start 24 #define GFX75_3DSTATE_CHROMA_KEY_3DCommandOpcode_start 24 #define GFX7_3DSTATE_CHROMA_KEY_3DCommandOpcode_start 24 #define GFX6_3DSTATE_CHROMA_KEY_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CHROMA_KEY_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 24; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CHROMA_KEY::3D Command Sub Opcode */ #define GFX125_3DSTATE_CHROMA_KEY_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_CHROMA_KEY_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_CHROMA_KEY_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_CHROMA_KEY_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_CHROMA_KEY_3DCommandSubOpcode_bits 8 #define GFX75_3DSTATE_CHROMA_KEY_3DCommandSubOpcode_bits 8 #define GFX7_3DSTATE_CHROMA_KEY_3DCommandSubOpcode_bits 8 #define GFX6_3DSTATE_CHROMA_KEY_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CHROMA_KEY_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CHROMA_KEY_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_CHROMA_KEY_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_CHROMA_KEY_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_CHROMA_KEY_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_CHROMA_KEY_3DCommandSubOpcode_start 16 #define GFX75_3DSTATE_CHROMA_KEY_3DCommandSubOpcode_start 16 #define GFX7_3DSTATE_CHROMA_KEY_3DCommandSubOpcode_start 16 #define GFX6_3DSTATE_CHROMA_KEY_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CHROMA_KEY_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 16; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CHROMA_KEY::ChromaKey High Value */ #define GFX125_3DSTATE_CHROMA_KEY_ChromaKeyHighValue_bits 32 #define GFX12_3DSTATE_CHROMA_KEY_ChromaKeyHighValue_bits 32 #define GFX11_3DSTATE_CHROMA_KEY_ChromaKeyHighValue_bits 32 #define GFX9_3DSTATE_CHROMA_KEY_ChromaKeyHighValue_bits 32 #define GFX8_3DSTATE_CHROMA_KEY_ChromaKeyHighValue_bits 32 #define GFX75_3DSTATE_CHROMA_KEY_ChromaKeyHighValue_bits 32 #define GFX7_3DSTATE_CHROMA_KEY_ChromaKeyHighValue_bits 32 #define GFX6_3DSTATE_CHROMA_KEY_ChromaKeyHighValue_bits 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CHROMA_KEY_ChromaKeyHighValue_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 32; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CHROMA_KEY_ChromaKeyHighValue_start 96 #define GFX12_3DSTATE_CHROMA_KEY_ChromaKeyHighValue_start 96 #define GFX11_3DSTATE_CHROMA_KEY_ChromaKeyHighValue_start 96 #define GFX9_3DSTATE_CHROMA_KEY_ChromaKeyHighValue_start 96 #define GFX8_3DSTATE_CHROMA_KEY_ChromaKeyHighValue_start 96 #define GFX75_3DSTATE_CHROMA_KEY_ChromaKeyHighValue_start 96 #define GFX7_3DSTATE_CHROMA_KEY_ChromaKeyHighValue_start 96 #define GFX6_3DSTATE_CHROMA_KEY_ChromaKeyHighValue_start 96 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CHROMA_KEY_ChromaKeyHighValue_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 96; case 120: return 96; case 110: return 96; case 90: return 96; case 80: return 96; case 75: return 96; case 70: return 96; case 60: return 96; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CHROMA_KEY::ChromaKey Low Value */ #define GFX125_3DSTATE_CHROMA_KEY_ChromaKeyLowValue_bits 32 #define GFX12_3DSTATE_CHROMA_KEY_ChromaKeyLowValue_bits 32 #define GFX11_3DSTATE_CHROMA_KEY_ChromaKeyLowValue_bits 32 #define GFX9_3DSTATE_CHROMA_KEY_ChromaKeyLowValue_bits 32 #define GFX8_3DSTATE_CHROMA_KEY_ChromaKeyLowValue_bits 32 #define GFX75_3DSTATE_CHROMA_KEY_ChromaKeyLowValue_bits 32 #define GFX7_3DSTATE_CHROMA_KEY_ChromaKeyLowValue_bits 32 #define GFX6_3DSTATE_CHROMA_KEY_ChromaKeyLowValue_bits 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CHROMA_KEY_ChromaKeyLowValue_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 32; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CHROMA_KEY_ChromaKeyLowValue_start 64 #define GFX12_3DSTATE_CHROMA_KEY_ChromaKeyLowValue_start 64 #define GFX11_3DSTATE_CHROMA_KEY_ChromaKeyLowValue_start 64 #define GFX9_3DSTATE_CHROMA_KEY_ChromaKeyLowValue_start 64 #define GFX8_3DSTATE_CHROMA_KEY_ChromaKeyLowValue_start 64 #define GFX75_3DSTATE_CHROMA_KEY_ChromaKeyLowValue_start 64 #define GFX7_3DSTATE_CHROMA_KEY_ChromaKeyLowValue_start 64 #define GFX6_3DSTATE_CHROMA_KEY_ChromaKeyLowValue_start 64 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CHROMA_KEY_ChromaKeyLowValue_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 64; case 80: return 64; case 75: return 64; case 70: return 64; case 60: return 64; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CHROMA_KEY::ChromaKey Table Index */ #define GFX125_3DSTATE_CHROMA_KEY_ChromaKeyTableIndex_bits 2 #define GFX12_3DSTATE_CHROMA_KEY_ChromaKeyTableIndex_bits 2 #define GFX11_3DSTATE_CHROMA_KEY_ChromaKeyTableIndex_bits 2 #define GFX9_3DSTATE_CHROMA_KEY_ChromaKeyTableIndex_bits 2 #define GFX8_3DSTATE_CHROMA_KEY_ChromaKeyTableIndex_bits 2 #define GFX75_3DSTATE_CHROMA_KEY_ChromaKeyTableIndex_bits 2 #define GFX7_3DSTATE_CHROMA_KEY_ChromaKeyTableIndex_bits 2 #define GFX6_3DSTATE_CHROMA_KEY_ChromaKeyTableIndex_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CHROMA_KEY_ChromaKeyTableIndex_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CHROMA_KEY_ChromaKeyTableIndex_start 62 #define GFX12_3DSTATE_CHROMA_KEY_ChromaKeyTableIndex_start 62 #define GFX11_3DSTATE_CHROMA_KEY_ChromaKeyTableIndex_start 62 #define GFX9_3DSTATE_CHROMA_KEY_ChromaKeyTableIndex_start 62 #define GFX8_3DSTATE_CHROMA_KEY_ChromaKeyTableIndex_start 62 #define GFX75_3DSTATE_CHROMA_KEY_ChromaKeyTableIndex_start 62 #define GFX7_3DSTATE_CHROMA_KEY_ChromaKeyTableIndex_start 62 #define GFX6_3DSTATE_CHROMA_KEY_ChromaKeyTableIndex_start 62 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CHROMA_KEY_ChromaKeyTableIndex_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 62; case 120: return 62; case 110: return 62; case 90: return 62; case 80: return 62; case 75: return 62; case 70: return 62; case 60: return 62; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CHROMA_KEY::Command SubType */ #define GFX125_3DSTATE_CHROMA_KEY_CommandSubType_bits 2 #define GFX12_3DSTATE_CHROMA_KEY_CommandSubType_bits 2 #define GFX11_3DSTATE_CHROMA_KEY_CommandSubType_bits 2 #define GFX9_3DSTATE_CHROMA_KEY_CommandSubType_bits 2 #define GFX8_3DSTATE_CHROMA_KEY_CommandSubType_bits 2 #define GFX75_3DSTATE_CHROMA_KEY_CommandSubType_bits 2 #define GFX7_3DSTATE_CHROMA_KEY_CommandSubType_bits 2 #define GFX6_3DSTATE_CHROMA_KEY_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CHROMA_KEY_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CHROMA_KEY_CommandSubType_start 27 #define GFX12_3DSTATE_CHROMA_KEY_CommandSubType_start 27 #define GFX11_3DSTATE_CHROMA_KEY_CommandSubType_start 27 #define GFX9_3DSTATE_CHROMA_KEY_CommandSubType_start 27 #define GFX8_3DSTATE_CHROMA_KEY_CommandSubType_start 27 #define GFX75_3DSTATE_CHROMA_KEY_CommandSubType_start 27 #define GFX7_3DSTATE_CHROMA_KEY_CommandSubType_start 27 #define GFX6_3DSTATE_CHROMA_KEY_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CHROMA_KEY_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 27; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CHROMA_KEY::Command Type */ #define GFX125_3DSTATE_CHROMA_KEY_CommandType_bits 3 #define GFX12_3DSTATE_CHROMA_KEY_CommandType_bits 3 #define GFX11_3DSTATE_CHROMA_KEY_CommandType_bits 3 #define GFX9_3DSTATE_CHROMA_KEY_CommandType_bits 3 #define GFX8_3DSTATE_CHROMA_KEY_CommandType_bits 3 #define GFX75_3DSTATE_CHROMA_KEY_CommandType_bits 3 #define GFX7_3DSTATE_CHROMA_KEY_CommandType_bits 3 #define GFX6_3DSTATE_CHROMA_KEY_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CHROMA_KEY_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CHROMA_KEY_CommandType_start 29 #define GFX12_3DSTATE_CHROMA_KEY_CommandType_start 29 #define GFX11_3DSTATE_CHROMA_KEY_CommandType_start 29 #define GFX9_3DSTATE_CHROMA_KEY_CommandType_start 29 #define GFX8_3DSTATE_CHROMA_KEY_CommandType_start 29 #define GFX75_3DSTATE_CHROMA_KEY_CommandType_start 29 #define GFX7_3DSTATE_CHROMA_KEY_CommandType_start 29 #define GFX6_3DSTATE_CHROMA_KEY_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CHROMA_KEY_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 29; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CHROMA_KEY::DWord Length */ #define GFX125_3DSTATE_CHROMA_KEY_DWordLength_bits 8 #define GFX12_3DSTATE_CHROMA_KEY_DWordLength_bits 8 #define GFX11_3DSTATE_CHROMA_KEY_DWordLength_bits 8 #define GFX9_3DSTATE_CHROMA_KEY_DWordLength_bits 8 #define GFX8_3DSTATE_CHROMA_KEY_DWordLength_bits 8 #define GFX75_3DSTATE_CHROMA_KEY_DWordLength_bits 8 #define GFX7_3DSTATE_CHROMA_KEY_DWordLength_bits 8 #define GFX6_3DSTATE_CHROMA_KEY_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CHROMA_KEY_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CHROMA_KEY_DWordLength_start 0 #define GFX12_3DSTATE_CHROMA_KEY_DWordLength_start 0 #define GFX11_3DSTATE_CHROMA_KEY_DWordLength_start 0 #define GFX9_3DSTATE_CHROMA_KEY_DWordLength_start 0 #define GFX8_3DSTATE_CHROMA_KEY_DWordLength_start 0 #define GFX75_3DSTATE_CHROMA_KEY_DWordLength_start 0 #define GFX7_3DSTATE_CHROMA_KEY_DWordLength_start 0 #define GFX6_3DSTATE_CHROMA_KEY_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CHROMA_KEY_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CLEAR_PARAMS */ #define GFX125_3DSTATE_CLEAR_PARAMS_length 3 #define GFX12_3DSTATE_CLEAR_PARAMS_length 3 #define GFX11_3DSTATE_CLEAR_PARAMS_length 3 #define GFX9_3DSTATE_CLEAR_PARAMS_length 3 #define GFX8_3DSTATE_CLEAR_PARAMS_length 3 #define GFX75_3DSTATE_CLEAR_PARAMS_length 3 #define GFX7_3DSTATE_CLEAR_PARAMS_length 3 #define GFX6_3DSTATE_CLEAR_PARAMS_length 2 #define GFX5_3DSTATE_CLEAR_PARAMS_length 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLEAR_PARAMS_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 2; case 50: return 2; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CLEAR_PARAMS::3D Command Opcode */ #define GFX125_3DSTATE_CLEAR_PARAMS_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_CLEAR_PARAMS_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_CLEAR_PARAMS_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_CLEAR_PARAMS_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_CLEAR_PARAMS_3DCommandOpcode_bits 3 #define GFX75_3DSTATE_CLEAR_PARAMS_3DCommandOpcode_bits 3 #define GFX7_3DSTATE_CLEAR_PARAMS_3DCommandOpcode_bits 3 #define GFX6_3DSTATE_CLEAR_PARAMS_3DCommandOpcode_bits 3 #define GFX5_3DSTATE_CLEAR_PARAMS_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLEAR_PARAMS_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 3; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CLEAR_PARAMS_3DCommandOpcode_start 24 #define GFX12_3DSTATE_CLEAR_PARAMS_3DCommandOpcode_start 24 #define GFX11_3DSTATE_CLEAR_PARAMS_3DCommandOpcode_start 24 #define GFX9_3DSTATE_CLEAR_PARAMS_3DCommandOpcode_start 24 #define GFX8_3DSTATE_CLEAR_PARAMS_3DCommandOpcode_start 24 #define GFX75_3DSTATE_CLEAR_PARAMS_3DCommandOpcode_start 24 #define GFX7_3DSTATE_CLEAR_PARAMS_3DCommandOpcode_start 24 #define GFX6_3DSTATE_CLEAR_PARAMS_3DCommandOpcode_start 24 #define GFX5_3DSTATE_CLEAR_PARAMS_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLEAR_PARAMS_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 24; case 50: return 24; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CLEAR_PARAMS::3D Command Sub Opcode */ #define GFX125_3DSTATE_CLEAR_PARAMS_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_CLEAR_PARAMS_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_CLEAR_PARAMS_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_CLEAR_PARAMS_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_CLEAR_PARAMS_3DCommandSubOpcode_bits 8 #define GFX75_3DSTATE_CLEAR_PARAMS_3DCommandSubOpcode_bits 8 #define GFX7_3DSTATE_CLEAR_PARAMS_3DCommandSubOpcode_bits 8 #define GFX6_3DSTATE_CLEAR_PARAMS_3DCommandSubOpcode_bits 8 #define GFX5_3DSTATE_CLEAR_PARAMS_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLEAR_PARAMS_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 8; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CLEAR_PARAMS_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_CLEAR_PARAMS_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_CLEAR_PARAMS_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_CLEAR_PARAMS_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_CLEAR_PARAMS_3DCommandSubOpcode_start 16 #define GFX75_3DSTATE_CLEAR_PARAMS_3DCommandSubOpcode_start 16 #define GFX7_3DSTATE_CLEAR_PARAMS_3DCommandSubOpcode_start 16 #define GFX6_3DSTATE_CLEAR_PARAMS_3DCommandSubOpcode_start 16 #define GFX5_3DSTATE_CLEAR_PARAMS_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLEAR_PARAMS_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 16; case 50: return 16; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CLEAR_PARAMS::Command SubType */ #define GFX125_3DSTATE_CLEAR_PARAMS_CommandSubType_bits 2 #define GFX12_3DSTATE_CLEAR_PARAMS_CommandSubType_bits 2 #define GFX11_3DSTATE_CLEAR_PARAMS_CommandSubType_bits 2 #define GFX9_3DSTATE_CLEAR_PARAMS_CommandSubType_bits 2 #define GFX8_3DSTATE_CLEAR_PARAMS_CommandSubType_bits 2 #define GFX75_3DSTATE_CLEAR_PARAMS_CommandSubType_bits 2 #define GFX7_3DSTATE_CLEAR_PARAMS_CommandSubType_bits 2 #define GFX6_3DSTATE_CLEAR_PARAMS_CommandSubType_bits 2 #define GFX5_3DSTATE_CLEAR_PARAMS_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLEAR_PARAMS_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 2; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CLEAR_PARAMS_CommandSubType_start 27 #define GFX12_3DSTATE_CLEAR_PARAMS_CommandSubType_start 27 #define GFX11_3DSTATE_CLEAR_PARAMS_CommandSubType_start 27 #define GFX9_3DSTATE_CLEAR_PARAMS_CommandSubType_start 27 #define GFX8_3DSTATE_CLEAR_PARAMS_CommandSubType_start 27 #define GFX75_3DSTATE_CLEAR_PARAMS_CommandSubType_start 27 #define GFX7_3DSTATE_CLEAR_PARAMS_CommandSubType_start 27 #define GFX6_3DSTATE_CLEAR_PARAMS_CommandSubType_start 27 #define GFX5_3DSTATE_CLEAR_PARAMS_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLEAR_PARAMS_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 27; case 50: return 27; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CLEAR_PARAMS::Command Type */ #define GFX125_3DSTATE_CLEAR_PARAMS_CommandType_bits 3 #define GFX12_3DSTATE_CLEAR_PARAMS_CommandType_bits 3 #define GFX11_3DSTATE_CLEAR_PARAMS_CommandType_bits 3 #define GFX9_3DSTATE_CLEAR_PARAMS_CommandType_bits 3 #define GFX8_3DSTATE_CLEAR_PARAMS_CommandType_bits 3 #define GFX75_3DSTATE_CLEAR_PARAMS_CommandType_bits 3 #define GFX7_3DSTATE_CLEAR_PARAMS_CommandType_bits 3 #define GFX6_3DSTATE_CLEAR_PARAMS_CommandType_bits 3 #define GFX5_3DSTATE_CLEAR_PARAMS_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLEAR_PARAMS_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 3; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CLEAR_PARAMS_CommandType_start 29 #define GFX12_3DSTATE_CLEAR_PARAMS_CommandType_start 29 #define GFX11_3DSTATE_CLEAR_PARAMS_CommandType_start 29 #define GFX9_3DSTATE_CLEAR_PARAMS_CommandType_start 29 #define GFX8_3DSTATE_CLEAR_PARAMS_CommandType_start 29 #define GFX75_3DSTATE_CLEAR_PARAMS_CommandType_start 29 #define GFX7_3DSTATE_CLEAR_PARAMS_CommandType_start 29 #define GFX6_3DSTATE_CLEAR_PARAMS_CommandType_start 29 #define GFX5_3DSTATE_CLEAR_PARAMS_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLEAR_PARAMS_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 29; case 50: return 29; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CLEAR_PARAMS::DWord Length */ #define GFX125_3DSTATE_CLEAR_PARAMS_DWordLength_bits 8 #define GFX12_3DSTATE_CLEAR_PARAMS_DWordLength_bits 8 #define GFX11_3DSTATE_CLEAR_PARAMS_DWordLength_bits 8 #define GFX9_3DSTATE_CLEAR_PARAMS_DWordLength_bits 8 #define GFX8_3DSTATE_CLEAR_PARAMS_DWordLength_bits 8 #define GFX75_3DSTATE_CLEAR_PARAMS_DWordLength_bits 8 #define GFX7_3DSTATE_CLEAR_PARAMS_DWordLength_bits 8 #define GFX6_3DSTATE_CLEAR_PARAMS_DWordLength_bits 8 #define GFX5_3DSTATE_CLEAR_PARAMS_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLEAR_PARAMS_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 8; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CLEAR_PARAMS_DWordLength_start 0 #define GFX12_3DSTATE_CLEAR_PARAMS_DWordLength_start 0 #define GFX11_3DSTATE_CLEAR_PARAMS_DWordLength_start 0 #define GFX9_3DSTATE_CLEAR_PARAMS_DWordLength_start 0 #define GFX8_3DSTATE_CLEAR_PARAMS_DWordLength_start 0 #define GFX75_3DSTATE_CLEAR_PARAMS_DWordLength_start 0 #define GFX7_3DSTATE_CLEAR_PARAMS_DWordLength_start 0 #define GFX6_3DSTATE_CLEAR_PARAMS_DWordLength_start 0 #define GFX5_3DSTATE_CLEAR_PARAMS_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLEAR_PARAMS_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CLEAR_PARAMS::Depth Clear Value */ #define GFX125_3DSTATE_CLEAR_PARAMS_DepthClearValue_bits 32 #define GFX12_3DSTATE_CLEAR_PARAMS_DepthClearValue_bits 32 #define GFX11_3DSTATE_CLEAR_PARAMS_DepthClearValue_bits 32 #define GFX9_3DSTATE_CLEAR_PARAMS_DepthClearValue_bits 32 #define GFX8_3DSTATE_CLEAR_PARAMS_DepthClearValue_bits 32 #define GFX75_3DSTATE_CLEAR_PARAMS_DepthClearValue_bits 32 #define GFX7_3DSTATE_CLEAR_PARAMS_DepthClearValue_bits 32 #define GFX6_3DSTATE_CLEAR_PARAMS_DepthClearValue_bits 32 #define GFX5_3DSTATE_CLEAR_PARAMS_DepthClearValue_bits 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLEAR_PARAMS_DepthClearValue_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 32; case 50: return 32; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CLEAR_PARAMS_DepthClearValue_start 32 #define GFX12_3DSTATE_CLEAR_PARAMS_DepthClearValue_start 32 #define GFX11_3DSTATE_CLEAR_PARAMS_DepthClearValue_start 32 #define GFX9_3DSTATE_CLEAR_PARAMS_DepthClearValue_start 32 #define GFX8_3DSTATE_CLEAR_PARAMS_DepthClearValue_start 32 #define GFX75_3DSTATE_CLEAR_PARAMS_DepthClearValue_start 32 #define GFX7_3DSTATE_CLEAR_PARAMS_DepthClearValue_start 32 #define GFX6_3DSTATE_CLEAR_PARAMS_DepthClearValue_start 32 #define GFX5_3DSTATE_CLEAR_PARAMS_DepthClearValue_start 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLEAR_PARAMS_DepthClearValue_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 32; case 50: return 32; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CLEAR_PARAMS::Depth Clear Value Valid */ #define GFX125_3DSTATE_CLEAR_PARAMS_DepthClearValueValid_bits 1 #define GFX12_3DSTATE_CLEAR_PARAMS_DepthClearValueValid_bits 1 #define GFX11_3DSTATE_CLEAR_PARAMS_DepthClearValueValid_bits 1 #define GFX9_3DSTATE_CLEAR_PARAMS_DepthClearValueValid_bits 1 #define GFX8_3DSTATE_CLEAR_PARAMS_DepthClearValueValid_bits 1 #define GFX75_3DSTATE_CLEAR_PARAMS_DepthClearValueValid_bits 1 #define GFX7_3DSTATE_CLEAR_PARAMS_DepthClearValueValid_bits 1 #define GFX6_3DSTATE_CLEAR_PARAMS_DepthClearValueValid_bits 1 #define GFX5_3DSTATE_CLEAR_PARAMS_DepthClearValueValid_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLEAR_PARAMS_DepthClearValueValid_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 1; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CLEAR_PARAMS_DepthClearValueValid_start 64 #define GFX12_3DSTATE_CLEAR_PARAMS_DepthClearValueValid_start 64 #define GFX11_3DSTATE_CLEAR_PARAMS_DepthClearValueValid_start 64 #define GFX9_3DSTATE_CLEAR_PARAMS_DepthClearValueValid_start 64 #define GFX8_3DSTATE_CLEAR_PARAMS_DepthClearValueValid_start 64 #define GFX75_3DSTATE_CLEAR_PARAMS_DepthClearValueValid_start 64 #define GFX7_3DSTATE_CLEAR_PARAMS_DepthClearValueValid_start 64 #define GFX6_3DSTATE_CLEAR_PARAMS_DepthClearValueValid_start 15 #define GFX5_3DSTATE_CLEAR_PARAMS_DepthClearValueValid_start 15 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLEAR_PARAMS_DepthClearValueValid_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 64; case 80: return 64; case 75: return 64; case 70: return 64; case 60: return 15; case 50: return 15; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CLIP */ #define GFX125_3DSTATE_CLIP_length 4 #define GFX12_3DSTATE_CLIP_length 4 #define GFX11_3DSTATE_CLIP_length 4 #define GFX9_3DSTATE_CLIP_length 4 #define GFX8_3DSTATE_CLIP_length 4 #define GFX75_3DSTATE_CLIP_length 4 #define GFX7_3DSTATE_CLIP_length 4 #define GFX6_3DSTATE_CLIP_length 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLIP_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 4; case 70: return 4; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CLIP::3D Command Opcode */ #define GFX125_3DSTATE_CLIP_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_CLIP_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_CLIP_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_CLIP_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_CLIP_3DCommandOpcode_bits 3 #define GFX75_3DSTATE_CLIP_3DCommandOpcode_bits 3 #define GFX7_3DSTATE_CLIP_3DCommandOpcode_bits 3 #define GFX6_3DSTATE_CLIP_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLIP_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CLIP_3DCommandOpcode_start 24 #define GFX12_3DSTATE_CLIP_3DCommandOpcode_start 24 #define GFX11_3DSTATE_CLIP_3DCommandOpcode_start 24 #define GFX9_3DSTATE_CLIP_3DCommandOpcode_start 24 #define GFX8_3DSTATE_CLIP_3DCommandOpcode_start 24 #define GFX75_3DSTATE_CLIP_3DCommandOpcode_start 24 #define GFX7_3DSTATE_CLIP_3DCommandOpcode_start 24 #define GFX6_3DSTATE_CLIP_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLIP_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 24; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CLIP::3D Command Sub Opcode */ #define GFX125_3DSTATE_CLIP_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_CLIP_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_CLIP_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_CLIP_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_CLIP_3DCommandSubOpcode_bits 8 #define GFX75_3DSTATE_CLIP_3DCommandSubOpcode_bits 8 #define GFX7_3DSTATE_CLIP_3DCommandSubOpcode_bits 8 #define GFX6_3DSTATE_CLIP_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLIP_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CLIP_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_CLIP_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_CLIP_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_CLIP_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_CLIP_3DCommandSubOpcode_start 16 #define GFX75_3DSTATE_CLIP_3DCommandSubOpcode_start 16 #define GFX7_3DSTATE_CLIP_3DCommandSubOpcode_start 16 #define GFX6_3DSTATE_CLIP_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLIP_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 16; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CLIP::API Mode */ #define GFX125_3DSTATE_CLIP_APIMode_bits 1 #define GFX12_3DSTATE_CLIP_APIMode_bits 1 #define GFX11_3DSTATE_CLIP_APIMode_bits 1 #define GFX9_3DSTATE_CLIP_APIMode_bits 1 #define GFX8_3DSTATE_CLIP_APIMode_bits 1 #define GFX75_3DSTATE_CLIP_APIMode_bits 1 #define GFX7_3DSTATE_CLIP_APIMode_bits 1 #define GFX6_3DSTATE_CLIP_APIMode_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLIP_APIMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CLIP_APIMode_start 94 #define GFX12_3DSTATE_CLIP_APIMode_start 94 #define GFX11_3DSTATE_CLIP_APIMode_start 94 #define GFX9_3DSTATE_CLIP_APIMode_start 94 #define GFX8_3DSTATE_CLIP_APIMode_start 94 #define GFX75_3DSTATE_CLIP_APIMode_start 94 #define GFX7_3DSTATE_CLIP_APIMode_start 94 #define GFX6_3DSTATE_CLIP_APIMode_start 94 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLIP_APIMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 94; case 120: return 94; case 110: return 94; case 90: return 94; case 80: return 94; case 75: return 94; case 70: return 94; case 60: return 94; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CLIP::Clip Enable */ #define GFX125_3DSTATE_CLIP_ClipEnable_bits 1 #define GFX12_3DSTATE_CLIP_ClipEnable_bits 1 #define GFX11_3DSTATE_CLIP_ClipEnable_bits 1 #define GFX9_3DSTATE_CLIP_ClipEnable_bits 1 #define GFX8_3DSTATE_CLIP_ClipEnable_bits 1 #define GFX75_3DSTATE_CLIP_ClipEnable_bits 1 #define GFX7_3DSTATE_CLIP_ClipEnable_bits 1 #define GFX6_3DSTATE_CLIP_ClipEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLIP_ClipEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CLIP_ClipEnable_start 95 #define GFX12_3DSTATE_CLIP_ClipEnable_start 95 #define GFX11_3DSTATE_CLIP_ClipEnable_start 95 #define GFX9_3DSTATE_CLIP_ClipEnable_start 95 #define GFX8_3DSTATE_CLIP_ClipEnable_start 95 #define GFX75_3DSTATE_CLIP_ClipEnable_start 95 #define GFX7_3DSTATE_CLIP_ClipEnable_start 95 #define GFX6_3DSTATE_CLIP_ClipEnable_start 95 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLIP_ClipEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 95; case 120: return 95; case 110: return 95; case 90: return 95; case 80: return 95; case 75: return 95; case 70: return 95; case 60: return 95; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CLIP::Clip Mode */ #define GFX125_3DSTATE_CLIP_ClipMode_bits 3 #define GFX12_3DSTATE_CLIP_ClipMode_bits 3 #define GFX11_3DSTATE_CLIP_ClipMode_bits 3 #define GFX9_3DSTATE_CLIP_ClipMode_bits 3 #define GFX8_3DSTATE_CLIP_ClipMode_bits 3 #define GFX75_3DSTATE_CLIP_ClipMode_bits 3 #define GFX7_3DSTATE_CLIP_ClipMode_bits 3 #define GFX6_3DSTATE_CLIP_ClipMode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLIP_ClipMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CLIP_ClipMode_start 77 #define GFX12_3DSTATE_CLIP_ClipMode_start 77 #define GFX11_3DSTATE_CLIP_ClipMode_start 77 #define GFX9_3DSTATE_CLIP_ClipMode_start 77 #define GFX8_3DSTATE_CLIP_ClipMode_start 77 #define GFX75_3DSTATE_CLIP_ClipMode_start 77 #define GFX7_3DSTATE_CLIP_ClipMode_start 77 #define GFX6_3DSTATE_CLIP_ClipMode_start 77 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLIP_ClipMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 77; case 120: return 77; case 110: return 77; case 90: return 77; case 80: return 77; case 75: return 77; case 70: return 77; case 60: return 77; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CLIP::Command SubType */ #define GFX125_3DSTATE_CLIP_CommandSubType_bits 2 #define GFX12_3DSTATE_CLIP_CommandSubType_bits 2 #define GFX11_3DSTATE_CLIP_CommandSubType_bits 2 #define GFX9_3DSTATE_CLIP_CommandSubType_bits 2 #define GFX8_3DSTATE_CLIP_CommandSubType_bits 2 #define GFX75_3DSTATE_CLIP_CommandSubType_bits 2 #define GFX7_3DSTATE_CLIP_CommandSubType_bits 2 #define GFX6_3DSTATE_CLIP_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLIP_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CLIP_CommandSubType_start 27 #define GFX12_3DSTATE_CLIP_CommandSubType_start 27 #define GFX11_3DSTATE_CLIP_CommandSubType_start 27 #define GFX9_3DSTATE_CLIP_CommandSubType_start 27 #define GFX8_3DSTATE_CLIP_CommandSubType_start 27 #define GFX75_3DSTATE_CLIP_CommandSubType_start 27 #define GFX7_3DSTATE_CLIP_CommandSubType_start 27 #define GFX6_3DSTATE_CLIP_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLIP_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 27; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CLIP::Command Type */ #define GFX125_3DSTATE_CLIP_CommandType_bits 3 #define GFX12_3DSTATE_CLIP_CommandType_bits 3 #define GFX11_3DSTATE_CLIP_CommandType_bits 3 #define GFX9_3DSTATE_CLIP_CommandType_bits 3 #define GFX8_3DSTATE_CLIP_CommandType_bits 3 #define GFX75_3DSTATE_CLIP_CommandType_bits 3 #define GFX7_3DSTATE_CLIP_CommandType_bits 3 #define GFX6_3DSTATE_CLIP_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLIP_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CLIP_CommandType_start 29 #define GFX12_3DSTATE_CLIP_CommandType_start 29 #define GFX11_3DSTATE_CLIP_CommandType_start 29 #define GFX9_3DSTATE_CLIP_CommandType_start 29 #define GFX8_3DSTATE_CLIP_CommandType_start 29 #define GFX75_3DSTATE_CLIP_CommandType_start 29 #define GFX7_3DSTATE_CLIP_CommandType_start 29 #define GFX6_3DSTATE_CLIP_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLIP_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 29; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CLIP::Cull Mode */ #define GFX75_3DSTATE_CLIP_CullMode_bits 2 #define GFX7_3DSTATE_CLIP_CullMode_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLIP_CullMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_CLIP_CullMode_start 48 #define GFX7_3DSTATE_CLIP_CullMode_start 48 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLIP_CullMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 48; case 70: return 48; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CLIP::DWord Length */ #define GFX125_3DSTATE_CLIP_DWordLength_bits 8 #define GFX12_3DSTATE_CLIP_DWordLength_bits 8 #define GFX11_3DSTATE_CLIP_DWordLength_bits 8 #define GFX9_3DSTATE_CLIP_DWordLength_bits 8 #define GFX8_3DSTATE_CLIP_DWordLength_bits 8 #define GFX75_3DSTATE_CLIP_DWordLength_bits 8 #define GFX7_3DSTATE_CLIP_DWordLength_bits 8 #define GFX6_3DSTATE_CLIP_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLIP_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CLIP_DWordLength_start 0 #define GFX12_3DSTATE_CLIP_DWordLength_start 0 #define GFX11_3DSTATE_CLIP_DWordLength_start 0 #define GFX9_3DSTATE_CLIP_DWordLength_start 0 #define GFX8_3DSTATE_CLIP_DWordLength_start 0 #define GFX75_3DSTATE_CLIP_DWordLength_start 0 #define GFX7_3DSTATE_CLIP_DWordLength_start 0 #define GFX6_3DSTATE_CLIP_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLIP_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CLIP::Early Cull Enable */ #define GFX125_3DSTATE_CLIP_EarlyCullEnable_bits 1 #define GFX12_3DSTATE_CLIP_EarlyCullEnable_bits 1 #define GFX11_3DSTATE_CLIP_EarlyCullEnable_bits 1 #define GFX9_3DSTATE_CLIP_EarlyCullEnable_bits 1 #define GFX8_3DSTATE_CLIP_EarlyCullEnable_bits 1 #define GFX75_3DSTATE_CLIP_EarlyCullEnable_bits 1 #define GFX7_3DSTATE_CLIP_EarlyCullEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLIP_EarlyCullEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CLIP_EarlyCullEnable_start 50 #define GFX12_3DSTATE_CLIP_EarlyCullEnable_start 50 #define GFX11_3DSTATE_CLIP_EarlyCullEnable_start 50 #define GFX9_3DSTATE_CLIP_EarlyCullEnable_start 50 #define GFX8_3DSTATE_CLIP_EarlyCullEnable_start 50 #define GFX75_3DSTATE_CLIP_EarlyCullEnable_start 50 #define GFX7_3DSTATE_CLIP_EarlyCullEnable_start 50 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLIP_EarlyCullEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 50; case 120: return 50; case 110: return 50; case 90: return 50; case 80: return 50; case 75: return 50; case 70: return 50; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CLIP::Force Clip Mode */ #define GFX125_3DSTATE_CLIP_ForceClipMode_bits 1 #define GFX12_3DSTATE_CLIP_ForceClipMode_bits 1 #define GFX11_3DSTATE_CLIP_ForceClipMode_bits 1 #define GFX9_3DSTATE_CLIP_ForceClipMode_bits 1 #define GFX8_3DSTATE_CLIP_ForceClipMode_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLIP_ForceClipMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CLIP_ForceClipMode_start 48 #define GFX12_3DSTATE_CLIP_ForceClipMode_start 48 #define GFX11_3DSTATE_CLIP_ForceClipMode_start 48 #define GFX9_3DSTATE_CLIP_ForceClipMode_start 48 #define GFX8_3DSTATE_CLIP_ForceClipMode_start 48 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLIP_ForceClipMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 48; case 120: return 48; case 110: return 48; case 90: return 48; case 80: return 48; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CLIP::Force User Clip Distance Clip Test Enable Bitmask */ #define GFX125_3DSTATE_CLIP_ForceUserClipDistanceClipTestEnableBitmask_bits 1 #define GFX12_3DSTATE_CLIP_ForceUserClipDistanceClipTestEnableBitmask_bits 1 #define GFX11_3DSTATE_CLIP_ForceUserClipDistanceClipTestEnableBitmask_bits 1 #define GFX9_3DSTATE_CLIP_ForceUserClipDistanceClipTestEnableBitmask_bits 1 #define GFX8_3DSTATE_CLIP_ForceUserClipDistanceClipTestEnableBitmask_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLIP_ForceUserClipDistanceClipTestEnableBitmask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CLIP_ForceUserClipDistanceClipTestEnableBitmask_start 49 #define GFX12_3DSTATE_CLIP_ForceUserClipDistanceClipTestEnableBitmask_start 49 #define GFX11_3DSTATE_CLIP_ForceUserClipDistanceClipTestEnableBitmask_start 49 #define GFX9_3DSTATE_CLIP_ForceUserClipDistanceClipTestEnableBitmask_start 49 #define GFX8_3DSTATE_CLIP_ForceUserClipDistanceClipTestEnableBitmask_start 49 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLIP_ForceUserClipDistanceClipTestEnableBitmask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 49; case 120: return 49; case 110: return 49; case 90: return 49; case 80: return 49; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CLIP::Force User Clip Distance Cull Test Enable Bitmask */ #define GFX125_3DSTATE_CLIP_ForceUserClipDistanceCullTestEnableBitmask_bits 1 #define GFX12_3DSTATE_CLIP_ForceUserClipDistanceCullTestEnableBitmask_bits 1 #define GFX11_3DSTATE_CLIP_ForceUserClipDistanceCullTestEnableBitmask_bits 1 #define GFX9_3DSTATE_CLIP_ForceUserClipDistanceCullTestEnableBitmask_bits 1 #define GFX8_3DSTATE_CLIP_ForceUserClipDistanceCullTestEnableBitmask_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLIP_ForceUserClipDistanceCullTestEnableBitmask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CLIP_ForceUserClipDistanceCullTestEnableBitmask_start 52 #define GFX12_3DSTATE_CLIP_ForceUserClipDistanceCullTestEnableBitmask_start 52 #define GFX11_3DSTATE_CLIP_ForceUserClipDistanceCullTestEnableBitmask_start 52 #define GFX9_3DSTATE_CLIP_ForceUserClipDistanceCullTestEnableBitmask_start 52 #define GFX8_3DSTATE_CLIP_ForceUserClipDistanceCullTestEnableBitmask_start 52 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLIP_ForceUserClipDistanceCullTestEnableBitmask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 52; case 120: return 52; case 110: return 52; case 90: return 52; case 80: return 52; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CLIP::Force Zero RTA Index Enable */ #define GFX125_3DSTATE_CLIP_ForceZeroRTAIndexEnable_bits 1 #define GFX12_3DSTATE_CLIP_ForceZeroRTAIndexEnable_bits 1 #define GFX11_3DSTATE_CLIP_ForceZeroRTAIndexEnable_bits 1 #define GFX9_3DSTATE_CLIP_ForceZeroRTAIndexEnable_bits 1 #define GFX8_3DSTATE_CLIP_ForceZeroRTAIndexEnable_bits 1 #define GFX75_3DSTATE_CLIP_ForceZeroRTAIndexEnable_bits 1 #define GFX7_3DSTATE_CLIP_ForceZeroRTAIndexEnable_bits 1 #define GFX6_3DSTATE_CLIP_ForceZeroRTAIndexEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLIP_ForceZeroRTAIndexEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CLIP_ForceZeroRTAIndexEnable_start 101 #define GFX12_3DSTATE_CLIP_ForceZeroRTAIndexEnable_start 101 #define GFX11_3DSTATE_CLIP_ForceZeroRTAIndexEnable_start 101 #define GFX9_3DSTATE_CLIP_ForceZeroRTAIndexEnable_start 101 #define GFX8_3DSTATE_CLIP_ForceZeroRTAIndexEnable_start 101 #define GFX75_3DSTATE_CLIP_ForceZeroRTAIndexEnable_start 101 #define GFX7_3DSTATE_CLIP_ForceZeroRTAIndexEnable_start 101 #define GFX6_3DSTATE_CLIP_ForceZeroRTAIndexEnable_start 101 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLIP_ForceZeroRTAIndexEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 101; case 120: return 101; case 110: return 101; case 90: return 101; case 80: return 101; case 75: return 101; case 70: return 101; case 60: return 101; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CLIP::Front Winding */ #define GFX75_3DSTATE_CLIP_FrontWinding_bits 1 #define GFX7_3DSTATE_CLIP_FrontWinding_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLIP_FrontWinding_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_CLIP_FrontWinding_start 52 #define GFX7_3DSTATE_CLIP_FrontWinding_start 52 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLIP_FrontWinding_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 52; case 70: return 52; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CLIP::Guardband Clip Test Enable */ #define GFX125_3DSTATE_CLIP_GuardbandClipTestEnable_bits 1 #define GFX12_3DSTATE_CLIP_GuardbandClipTestEnable_bits 1 #define GFX11_3DSTATE_CLIP_GuardbandClipTestEnable_bits 1 #define GFX9_3DSTATE_CLIP_GuardbandClipTestEnable_bits 1 #define GFX8_3DSTATE_CLIP_GuardbandClipTestEnable_bits 1 #define GFX75_3DSTATE_CLIP_GuardbandClipTestEnable_bits 1 #define GFX7_3DSTATE_CLIP_GuardbandClipTestEnable_bits 1 #define GFX6_3DSTATE_CLIP_GuardbandClipTestEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLIP_GuardbandClipTestEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CLIP_GuardbandClipTestEnable_start 90 #define GFX12_3DSTATE_CLIP_GuardbandClipTestEnable_start 90 #define GFX11_3DSTATE_CLIP_GuardbandClipTestEnable_start 90 #define GFX9_3DSTATE_CLIP_GuardbandClipTestEnable_start 90 #define GFX8_3DSTATE_CLIP_GuardbandClipTestEnable_start 90 #define GFX75_3DSTATE_CLIP_GuardbandClipTestEnable_start 90 #define GFX7_3DSTATE_CLIP_GuardbandClipTestEnable_start 90 #define GFX6_3DSTATE_CLIP_GuardbandClipTestEnable_start 90 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLIP_GuardbandClipTestEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 90; case 120: return 90; case 110: return 90; case 90: return 90; case 80: return 90; case 75: return 90; case 70: return 90; case 60: return 90; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CLIP::Line Strip/List Provoking Vertex Select */ #define GFX125_3DSTATE_CLIP_LineStripListProvokingVertexSelect_bits 2 #define GFX12_3DSTATE_CLIP_LineStripListProvokingVertexSelect_bits 2 #define GFX11_3DSTATE_CLIP_LineStripListProvokingVertexSelect_bits 2 #define GFX9_3DSTATE_CLIP_LineStripListProvokingVertexSelect_bits 2 #define GFX8_3DSTATE_CLIP_LineStripListProvokingVertexSelect_bits 2 #define GFX75_3DSTATE_CLIP_LineStripListProvokingVertexSelect_bits 2 #define GFX7_3DSTATE_CLIP_LineStripListProvokingVertexSelect_bits 2 #define GFX6_3DSTATE_CLIP_LineStripListProvokingVertexSelect_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLIP_LineStripListProvokingVertexSelect_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CLIP_LineStripListProvokingVertexSelect_start 66 #define GFX12_3DSTATE_CLIP_LineStripListProvokingVertexSelect_start 66 #define GFX11_3DSTATE_CLIP_LineStripListProvokingVertexSelect_start 66 #define GFX9_3DSTATE_CLIP_LineStripListProvokingVertexSelect_start 66 #define GFX8_3DSTATE_CLIP_LineStripListProvokingVertexSelect_start 66 #define GFX75_3DSTATE_CLIP_LineStripListProvokingVertexSelect_start 66 #define GFX7_3DSTATE_CLIP_LineStripListProvokingVertexSelect_start 66 #define GFX6_3DSTATE_CLIP_LineStripListProvokingVertexSelect_start 66 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLIP_LineStripListProvokingVertexSelect_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 66; case 120: return 66; case 110: return 66; case 90: return 66; case 80: return 66; case 75: return 66; case 70: return 66; case 60: return 66; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CLIP::Maximum Point Width */ #define GFX125_3DSTATE_CLIP_MaximumPointWidth_bits 11 #define GFX12_3DSTATE_CLIP_MaximumPointWidth_bits 11 #define GFX11_3DSTATE_CLIP_MaximumPointWidth_bits 11 #define GFX9_3DSTATE_CLIP_MaximumPointWidth_bits 11 #define GFX8_3DSTATE_CLIP_MaximumPointWidth_bits 11 #define GFX75_3DSTATE_CLIP_MaximumPointWidth_bits 11 #define GFX7_3DSTATE_CLIP_MaximumPointWidth_bits 11 #define GFX6_3DSTATE_CLIP_MaximumPointWidth_bits 11 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLIP_MaximumPointWidth_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 11; case 120: return 11; case 110: return 11; case 90: return 11; case 80: return 11; case 75: return 11; case 70: return 11; case 60: return 11; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CLIP_MaximumPointWidth_start 102 #define GFX12_3DSTATE_CLIP_MaximumPointWidth_start 102 #define GFX11_3DSTATE_CLIP_MaximumPointWidth_start 102 #define GFX9_3DSTATE_CLIP_MaximumPointWidth_start 102 #define GFX8_3DSTATE_CLIP_MaximumPointWidth_start 102 #define GFX75_3DSTATE_CLIP_MaximumPointWidth_start 102 #define GFX7_3DSTATE_CLIP_MaximumPointWidth_start 102 #define GFX6_3DSTATE_CLIP_MaximumPointWidth_start 102 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLIP_MaximumPointWidth_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 102; case 120: return 102; case 110: return 102; case 90: return 102; case 80: return 102; case 75: return 102; case 70: return 102; case 60: return 102; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CLIP::Maximum VP Index */ #define GFX125_3DSTATE_CLIP_MaximumVPIndex_bits 4 #define GFX12_3DSTATE_CLIP_MaximumVPIndex_bits 4 #define GFX11_3DSTATE_CLIP_MaximumVPIndex_bits 4 #define GFX9_3DSTATE_CLIP_MaximumVPIndex_bits 4 #define GFX8_3DSTATE_CLIP_MaximumVPIndex_bits 4 #define GFX75_3DSTATE_CLIP_MaximumVPIndex_bits 4 #define GFX7_3DSTATE_CLIP_MaximumVPIndex_bits 4 #define GFX6_3DSTATE_CLIP_MaximumVPIndex_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLIP_MaximumVPIndex_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 4; case 70: return 4; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CLIP_MaximumVPIndex_start 96 #define GFX12_3DSTATE_CLIP_MaximumVPIndex_start 96 #define GFX11_3DSTATE_CLIP_MaximumVPIndex_start 96 #define GFX9_3DSTATE_CLIP_MaximumVPIndex_start 96 #define GFX8_3DSTATE_CLIP_MaximumVPIndex_start 96 #define GFX75_3DSTATE_CLIP_MaximumVPIndex_start 96 #define GFX7_3DSTATE_CLIP_MaximumVPIndex_start 96 #define GFX6_3DSTATE_CLIP_MaximumVPIndex_start 96 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLIP_MaximumVPIndex_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 96; case 120: return 96; case 110: return 96; case 90: return 96; case 80: return 96; case 75: return 96; case 70: return 96; case 60: return 96; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CLIP::Minimum Point Width */ #define GFX125_3DSTATE_CLIP_MinimumPointWidth_bits 11 #define GFX12_3DSTATE_CLIP_MinimumPointWidth_bits 11 #define GFX11_3DSTATE_CLIP_MinimumPointWidth_bits 11 #define GFX9_3DSTATE_CLIP_MinimumPointWidth_bits 11 #define GFX8_3DSTATE_CLIP_MinimumPointWidth_bits 11 #define GFX75_3DSTATE_CLIP_MinimumPointWidth_bits 11 #define GFX7_3DSTATE_CLIP_MinimumPointWidth_bits 11 #define GFX6_3DSTATE_CLIP_MinimumPointWidth_bits 11 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLIP_MinimumPointWidth_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 11; case 120: return 11; case 110: return 11; case 90: return 11; case 80: return 11; case 75: return 11; case 70: return 11; case 60: return 11; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CLIP_MinimumPointWidth_start 113 #define GFX12_3DSTATE_CLIP_MinimumPointWidth_start 113 #define GFX11_3DSTATE_CLIP_MinimumPointWidth_start 113 #define GFX9_3DSTATE_CLIP_MinimumPointWidth_start 113 #define GFX8_3DSTATE_CLIP_MinimumPointWidth_start 113 #define GFX75_3DSTATE_CLIP_MinimumPointWidth_start 113 #define GFX7_3DSTATE_CLIP_MinimumPointWidth_start 113 #define GFX6_3DSTATE_CLIP_MinimumPointWidth_start 113 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLIP_MinimumPointWidth_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 113; case 120: return 113; case 110: return 113; case 90: return 113; case 80: return 113; case 75: return 113; case 70: return 113; case 60: return 113; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CLIP::Non-Perspective Barycentric Enable */ #define GFX125_3DSTATE_CLIP_NonPerspectiveBarycentricEnable_bits 1 #define GFX12_3DSTATE_CLIP_NonPerspectiveBarycentricEnable_bits 1 #define GFX11_3DSTATE_CLIP_NonPerspectiveBarycentricEnable_bits 1 #define GFX9_3DSTATE_CLIP_NonPerspectiveBarycentricEnable_bits 1 #define GFX8_3DSTATE_CLIP_NonPerspectiveBarycentricEnable_bits 1 #define GFX75_3DSTATE_CLIP_NonPerspectiveBarycentricEnable_bits 1 #define GFX7_3DSTATE_CLIP_NonPerspectiveBarycentricEnable_bits 1 #define GFX6_3DSTATE_CLIP_NonPerspectiveBarycentricEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLIP_NonPerspectiveBarycentricEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CLIP_NonPerspectiveBarycentricEnable_start 72 #define GFX12_3DSTATE_CLIP_NonPerspectiveBarycentricEnable_start 72 #define GFX11_3DSTATE_CLIP_NonPerspectiveBarycentricEnable_start 72 #define GFX9_3DSTATE_CLIP_NonPerspectiveBarycentricEnable_start 72 #define GFX8_3DSTATE_CLIP_NonPerspectiveBarycentricEnable_start 72 #define GFX75_3DSTATE_CLIP_NonPerspectiveBarycentricEnable_start 72 #define GFX7_3DSTATE_CLIP_NonPerspectiveBarycentricEnable_start 72 #define GFX6_3DSTATE_CLIP_NonPerspectiveBarycentricEnable_start 72 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLIP_NonPerspectiveBarycentricEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 72; case 120: return 72; case 110: return 72; case 90: return 72; case 80: return 72; case 75: return 72; case 70: return 72; case 60: return 72; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CLIP::Perspective Divide Disable */ #define GFX125_3DSTATE_CLIP_PerspectiveDivideDisable_bits 1 #define GFX12_3DSTATE_CLIP_PerspectiveDivideDisable_bits 1 #define GFX11_3DSTATE_CLIP_PerspectiveDivideDisable_bits 1 #define GFX9_3DSTATE_CLIP_PerspectiveDivideDisable_bits 1 #define GFX8_3DSTATE_CLIP_PerspectiveDivideDisable_bits 1 #define GFX75_3DSTATE_CLIP_PerspectiveDivideDisable_bits 1 #define GFX7_3DSTATE_CLIP_PerspectiveDivideDisable_bits 1 #define GFX6_3DSTATE_CLIP_PerspectiveDivideDisable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLIP_PerspectiveDivideDisable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CLIP_PerspectiveDivideDisable_start 73 #define GFX12_3DSTATE_CLIP_PerspectiveDivideDisable_start 73 #define GFX11_3DSTATE_CLIP_PerspectiveDivideDisable_start 73 #define GFX9_3DSTATE_CLIP_PerspectiveDivideDisable_start 73 #define GFX8_3DSTATE_CLIP_PerspectiveDivideDisable_start 73 #define GFX75_3DSTATE_CLIP_PerspectiveDivideDisable_start 73 #define GFX7_3DSTATE_CLIP_PerspectiveDivideDisable_start 73 #define GFX6_3DSTATE_CLIP_PerspectiveDivideDisable_start 73 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLIP_PerspectiveDivideDisable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 73; case 120: return 73; case 110: return 73; case 90: return 73; case 80: return 73; case 75: return 73; case 70: return 73; case 60: return 73; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CLIP::Statistics Enable */ #define GFX125_3DSTATE_CLIP_StatisticsEnable_bits 1 #define GFX12_3DSTATE_CLIP_StatisticsEnable_bits 1 #define GFX11_3DSTATE_CLIP_StatisticsEnable_bits 1 #define GFX9_3DSTATE_CLIP_StatisticsEnable_bits 1 #define GFX8_3DSTATE_CLIP_StatisticsEnable_bits 1 #define GFX75_3DSTATE_CLIP_StatisticsEnable_bits 1 #define GFX7_3DSTATE_CLIP_StatisticsEnable_bits 1 #define GFX6_3DSTATE_CLIP_StatisticsEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLIP_StatisticsEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CLIP_StatisticsEnable_start 42 #define GFX12_3DSTATE_CLIP_StatisticsEnable_start 42 #define GFX11_3DSTATE_CLIP_StatisticsEnable_start 42 #define GFX9_3DSTATE_CLIP_StatisticsEnable_start 42 #define GFX8_3DSTATE_CLIP_StatisticsEnable_start 42 #define GFX75_3DSTATE_CLIP_StatisticsEnable_start 42 #define GFX7_3DSTATE_CLIP_StatisticsEnable_start 42 #define GFX6_3DSTATE_CLIP_StatisticsEnable_start 42 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLIP_StatisticsEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 42; case 120: return 42; case 110: return 42; case 90: return 42; case 80: return 42; case 75: return 42; case 70: return 42; case 60: return 42; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CLIP::Triangle Fan Provoking Vertex Select */ #define GFX125_3DSTATE_CLIP_TriangleFanProvokingVertexSelect_bits 2 #define GFX12_3DSTATE_CLIP_TriangleFanProvokingVertexSelect_bits 2 #define GFX11_3DSTATE_CLIP_TriangleFanProvokingVertexSelect_bits 2 #define GFX9_3DSTATE_CLIP_TriangleFanProvokingVertexSelect_bits 2 #define GFX8_3DSTATE_CLIP_TriangleFanProvokingVertexSelect_bits 2 #define GFX75_3DSTATE_CLIP_TriangleFanProvokingVertexSelect_bits 2 #define GFX7_3DSTATE_CLIP_TriangleFanProvokingVertexSelect_bits 2 #define GFX6_3DSTATE_CLIP_TriangleFanProvokingVertexSelect_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLIP_TriangleFanProvokingVertexSelect_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CLIP_TriangleFanProvokingVertexSelect_start 64 #define GFX12_3DSTATE_CLIP_TriangleFanProvokingVertexSelect_start 64 #define GFX11_3DSTATE_CLIP_TriangleFanProvokingVertexSelect_start 64 #define GFX9_3DSTATE_CLIP_TriangleFanProvokingVertexSelect_start 64 #define GFX8_3DSTATE_CLIP_TriangleFanProvokingVertexSelect_start 64 #define GFX75_3DSTATE_CLIP_TriangleFanProvokingVertexSelect_start 64 #define GFX7_3DSTATE_CLIP_TriangleFanProvokingVertexSelect_start 64 #define GFX6_3DSTATE_CLIP_TriangleFanProvokingVertexSelect_start 64 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLIP_TriangleFanProvokingVertexSelect_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 64; case 80: return 64; case 75: return 64; case 70: return 64; case 60: return 64; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CLIP::Triangle Strip/List Provoking Vertex Select */ #define GFX125_3DSTATE_CLIP_TriangleStripListProvokingVertexSelect_bits 2 #define GFX12_3DSTATE_CLIP_TriangleStripListProvokingVertexSelect_bits 2 #define GFX11_3DSTATE_CLIP_TriangleStripListProvokingVertexSelect_bits 2 #define GFX9_3DSTATE_CLIP_TriangleStripListProvokingVertexSelect_bits 2 #define GFX8_3DSTATE_CLIP_TriangleStripListProvokingVertexSelect_bits 2 #define GFX75_3DSTATE_CLIP_TriangleStripListProvokingVertexSelect_bits 2 #define GFX7_3DSTATE_CLIP_TriangleStripListProvokingVertexSelect_bits 2 #define GFX6_3DSTATE_CLIP_TriangleStripListProvokingVertexSelect_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLIP_TriangleStripListProvokingVertexSelect_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CLIP_TriangleStripListProvokingVertexSelect_start 68 #define GFX12_3DSTATE_CLIP_TriangleStripListProvokingVertexSelect_start 68 #define GFX11_3DSTATE_CLIP_TriangleStripListProvokingVertexSelect_start 68 #define GFX9_3DSTATE_CLIP_TriangleStripListProvokingVertexSelect_start 68 #define GFX8_3DSTATE_CLIP_TriangleStripListProvokingVertexSelect_start 68 #define GFX75_3DSTATE_CLIP_TriangleStripListProvokingVertexSelect_start 68 #define GFX7_3DSTATE_CLIP_TriangleStripListProvokingVertexSelect_start 68 #define GFX6_3DSTATE_CLIP_TriangleStripListProvokingVertexSelect_start 68 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLIP_TriangleStripListProvokingVertexSelect_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 68; case 120: return 68; case 110: return 68; case 90: return 68; case 80: return 68; case 75: return 68; case 70: return 68; case 60: return 68; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CLIP::User Clip Distance Clip Test Enable Bitmask */ #define GFX125_3DSTATE_CLIP_UserClipDistanceClipTestEnableBitmask_bits 8 #define GFX12_3DSTATE_CLIP_UserClipDistanceClipTestEnableBitmask_bits 8 #define GFX11_3DSTATE_CLIP_UserClipDistanceClipTestEnableBitmask_bits 8 #define GFX9_3DSTATE_CLIP_UserClipDistanceClipTestEnableBitmask_bits 8 #define GFX8_3DSTATE_CLIP_UserClipDistanceClipTestEnableBitmask_bits 8 #define GFX75_3DSTATE_CLIP_UserClipDistanceClipTestEnableBitmask_bits 8 #define GFX7_3DSTATE_CLIP_UserClipDistanceClipTestEnableBitmask_bits 8 #define GFX6_3DSTATE_CLIP_UserClipDistanceClipTestEnableBitmask_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLIP_UserClipDistanceClipTestEnableBitmask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CLIP_UserClipDistanceClipTestEnableBitmask_start 80 #define GFX12_3DSTATE_CLIP_UserClipDistanceClipTestEnableBitmask_start 80 #define GFX11_3DSTATE_CLIP_UserClipDistanceClipTestEnableBitmask_start 80 #define GFX9_3DSTATE_CLIP_UserClipDistanceClipTestEnableBitmask_start 80 #define GFX8_3DSTATE_CLIP_UserClipDistanceClipTestEnableBitmask_start 80 #define GFX75_3DSTATE_CLIP_UserClipDistanceClipTestEnableBitmask_start 80 #define GFX7_3DSTATE_CLIP_UserClipDistanceClipTestEnableBitmask_start 80 #define GFX6_3DSTATE_CLIP_UserClipDistanceClipTestEnableBitmask_start 80 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLIP_UserClipDistanceClipTestEnableBitmask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 80; case 120: return 80; case 110: return 80; case 90: return 80; case 80: return 80; case 75: return 80; case 70: return 80; case 60: return 80; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CLIP::User Clip Distance Cull Test Enable Bitmask */ #define GFX125_3DSTATE_CLIP_UserClipDistanceCullTestEnableBitmask_bits 8 #define GFX12_3DSTATE_CLIP_UserClipDistanceCullTestEnableBitmask_bits 8 #define GFX11_3DSTATE_CLIP_UserClipDistanceCullTestEnableBitmask_bits 8 #define GFX9_3DSTATE_CLIP_UserClipDistanceCullTestEnableBitmask_bits 8 #define GFX8_3DSTATE_CLIP_UserClipDistanceCullTestEnableBitmask_bits 8 #define GFX75_3DSTATE_CLIP_UserClipDistanceCullTestEnableBitmask_bits 8 #define GFX7_3DSTATE_CLIP_UserClipDistanceCullTestEnableBitmask_bits 8 #define GFX6_3DSTATE_CLIP_UserClipDistanceCullTestEnableBitmask_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLIP_UserClipDistanceCullTestEnableBitmask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CLIP_UserClipDistanceCullTestEnableBitmask_start 32 #define GFX12_3DSTATE_CLIP_UserClipDistanceCullTestEnableBitmask_start 32 #define GFX11_3DSTATE_CLIP_UserClipDistanceCullTestEnableBitmask_start 32 #define GFX9_3DSTATE_CLIP_UserClipDistanceCullTestEnableBitmask_start 32 #define GFX8_3DSTATE_CLIP_UserClipDistanceCullTestEnableBitmask_start 32 #define GFX75_3DSTATE_CLIP_UserClipDistanceCullTestEnableBitmask_start 32 #define GFX7_3DSTATE_CLIP_UserClipDistanceCullTestEnableBitmask_start 32 #define GFX6_3DSTATE_CLIP_UserClipDistanceCullTestEnableBitmask_start 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLIP_UserClipDistanceCullTestEnableBitmask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 32; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CLIP::Vertex Sub Pixel Precision Select */ #define GFX125_3DSTATE_CLIP_VertexSubPixelPrecisionSelect_bits 1 #define GFX12_3DSTATE_CLIP_VertexSubPixelPrecisionSelect_bits 1 #define GFX11_3DSTATE_CLIP_VertexSubPixelPrecisionSelect_bits 1 #define GFX9_3DSTATE_CLIP_VertexSubPixelPrecisionSelect_bits 1 #define GFX8_3DSTATE_CLIP_VertexSubPixelPrecisionSelect_bits 1 #define GFX75_3DSTATE_CLIP_VertexSubPixelPrecisionSelect_bits 1 #define GFX7_3DSTATE_CLIP_VertexSubPixelPrecisionSelect_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLIP_VertexSubPixelPrecisionSelect_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CLIP_VertexSubPixelPrecisionSelect_start 51 #define GFX12_3DSTATE_CLIP_VertexSubPixelPrecisionSelect_start 51 #define GFX11_3DSTATE_CLIP_VertexSubPixelPrecisionSelect_start 51 #define GFX9_3DSTATE_CLIP_VertexSubPixelPrecisionSelect_start 51 #define GFX8_3DSTATE_CLIP_VertexSubPixelPrecisionSelect_start 51 #define GFX75_3DSTATE_CLIP_VertexSubPixelPrecisionSelect_start 51 #define GFX7_3DSTATE_CLIP_VertexSubPixelPrecisionSelect_start 51 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLIP_VertexSubPixelPrecisionSelect_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 51; case 120: return 51; case 110: return 51; case 90: return 51; case 80: return 51; case 75: return 51; case 70: return 51; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CLIP::Viewport XY Clip Test Enable */ #define GFX125_3DSTATE_CLIP_ViewportXYClipTestEnable_bits 1 #define GFX12_3DSTATE_CLIP_ViewportXYClipTestEnable_bits 1 #define GFX11_3DSTATE_CLIP_ViewportXYClipTestEnable_bits 1 #define GFX9_3DSTATE_CLIP_ViewportXYClipTestEnable_bits 1 #define GFX8_3DSTATE_CLIP_ViewportXYClipTestEnable_bits 1 #define GFX75_3DSTATE_CLIP_ViewportXYClipTestEnable_bits 1 #define GFX7_3DSTATE_CLIP_ViewportXYClipTestEnable_bits 1 #define GFX6_3DSTATE_CLIP_ViewportXYClipTestEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLIP_ViewportXYClipTestEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CLIP_ViewportXYClipTestEnable_start 92 #define GFX12_3DSTATE_CLIP_ViewportXYClipTestEnable_start 92 #define GFX11_3DSTATE_CLIP_ViewportXYClipTestEnable_start 92 #define GFX9_3DSTATE_CLIP_ViewportXYClipTestEnable_start 92 #define GFX8_3DSTATE_CLIP_ViewportXYClipTestEnable_start 92 #define GFX75_3DSTATE_CLIP_ViewportXYClipTestEnable_start 92 #define GFX7_3DSTATE_CLIP_ViewportXYClipTestEnable_start 92 #define GFX6_3DSTATE_CLIP_ViewportXYClipTestEnable_start 92 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLIP_ViewportXYClipTestEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 92; case 120: return 92; case 110: return 92; case 90: return 92; case 80: return 92; case 75: return 92; case 70: return 92; case 60: return 92; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CLIP::Viewport Z Clip Test Enable */ #define GFX75_3DSTATE_CLIP_ViewportZClipTestEnable_bits 1 #define GFX7_3DSTATE_CLIP_ViewportZClipTestEnable_bits 1 #define GFX6_3DSTATE_CLIP_ViewportZClipTestEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLIP_ViewportZClipTestEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_CLIP_ViewportZClipTestEnable_start 91 #define GFX7_3DSTATE_CLIP_ViewportZClipTestEnable_start 91 #define GFX6_3DSTATE_CLIP_ViewportZClipTestEnable_start 91 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CLIP_ViewportZClipTestEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 91; case 70: return 91; case 60: return 91; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_ALL */ #define GFX125_3DSTATE_CONSTANT_ALL_length 2 #define GFX12_3DSTATE_CONSTANT_ALL_length 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_ALL_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_ALL::3D Command Opcode */ #define GFX125_3DSTATE_CONSTANT_ALL_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_CONSTANT_ALL_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_ALL_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CONSTANT_ALL_3DCommandOpcode_start 24 #define GFX12_3DSTATE_CONSTANT_ALL_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_ALL_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_ALL::3D Command Sub Opcode */ #define GFX125_3DSTATE_CONSTANT_ALL_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_CONSTANT_ALL_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_ALL_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CONSTANT_ALL_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_CONSTANT_ALL_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_ALL_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_ALL::Command SubType */ #define GFX125_3DSTATE_CONSTANT_ALL_CommandSubType_bits 2 #define GFX12_3DSTATE_CONSTANT_ALL_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_ALL_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CONSTANT_ALL_CommandSubType_start 27 #define GFX12_3DSTATE_CONSTANT_ALL_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_ALL_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_ALL::Command Type */ #define GFX125_3DSTATE_CONSTANT_ALL_CommandType_bits 3 #define GFX12_3DSTATE_CONSTANT_ALL_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_ALL_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CONSTANT_ALL_CommandType_start 29 #define GFX12_3DSTATE_CONSTANT_ALL_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_ALL_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_ALL::DWord Length */ #define GFX125_3DSTATE_CONSTANT_ALL_DWordLength_bits 8 #define GFX12_3DSTATE_CONSTANT_ALL_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_ALL_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CONSTANT_ALL_DWordLength_start 0 #define GFX12_3DSTATE_CONSTANT_ALL_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_ALL_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_ALL::Domain Shader Update Enable */ #define GFX125_3DSTATE_CONSTANT_ALL_DomainShaderUpdateEnable_bits 1 #define GFX12_3DSTATE_CONSTANT_ALL_DomainShaderUpdateEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_ALL_DomainShaderUpdateEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CONSTANT_ALL_DomainShaderUpdateEnable_start 10 #define GFX12_3DSTATE_CONSTANT_ALL_DomainShaderUpdateEnable_start 10 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_ALL_DomainShaderUpdateEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 10; case 120: return 10; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_ALL::Geometry Shader Update Enable */ #define GFX125_3DSTATE_CONSTANT_ALL_GeometryShaderUpdateEnable_bits 1 #define GFX12_3DSTATE_CONSTANT_ALL_GeometryShaderUpdateEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_ALL_GeometryShaderUpdateEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CONSTANT_ALL_GeometryShaderUpdateEnable_start 11 #define GFX12_3DSTATE_CONSTANT_ALL_GeometryShaderUpdateEnable_start 11 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_ALL_GeometryShaderUpdateEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 11; case 120: return 11; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_ALL::Hull Shader Update Enable */ #define GFX125_3DSTATE_CONSTANT_ALL_HullShaderUpdateEnable_bits 1 #define GFX12_3DSTATE_CONSTANT_ALL_HullShaderUpdateEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_ALL_HullShaderUpdateEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CONSTANT_ALL_HullShaderUpdateEnable_start 9 #define GFX12_3DSTATE_CONSTANT_ALL_HullShaderUpdateEnable_start 9 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_ALL_HullShaderUpdateEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 9; case 120: return 9; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_ALL::MOCS */ #define GFX125_3DSTATE_CONSTANT_ALL_MOCS_bits 7 #define GFX12_3DSTATE_CONSTANT_ALL_MOCS_bits 7 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_ALL_MOCS_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 7; case 120: return 7; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CONSTANT_ALL_MOCS_start 32 #define GFX12_3DSTATE_CONSTANT_ALL_MOCS_start 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_ALL_MOCS_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_ALL::Pixel Shader Update Enable */ #define GFX125_3DSTATE_CONSTANT_ALL_PixelShaderUpdateEnable_bits 1 #define GFX12_3DSTATE_CONSTANT_ALL_PixelShaderUpdateEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_ALL_PixelShaderUpdateEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CONSTANT_ALL_PixelShaderUpdateEnable_start 12 #define GFX12_3DSTATE_CONSTANT_ALL_PixelShaderUpdateEnable_start 12 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_ALL_PixelShaderUpdateEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 12; case 120: return 12; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_ALL::Pointer Buffer Mask */ #define GFX125_3DSTATE_CONSTANT_ALL_PointerBufferMask_bits 4 #define GFX12_3DSTATE_CONSTANT_ALL_PointerBufferMask_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_ALL_PointerBufferMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CONSTANT_ALL_PointerBufferMask_start 48 #define GFX12_3DSTATE_CONSTANT_ALL_PointerBufferMask_start 48 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_ALL_PointerBufferMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 48; case 120: return 48; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_ALL::Shader Update Enable */ #define GFX125_3DSTATE_CONSTANT_ALL_ShaderUpdateEnable_bits 5 #define GFX12_3DSTATE_CONSTANT_ALL_ShaderUpdateEnable_bits 5 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_ALL_ShaderUpdateEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 5; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CONSTANT_ALL_ShaderUpdateEnable_start 8 #define GFX12_3DSTATE_CONSTANT_ALL_ShaderUpdateEnable_start 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_ALL_ShaderUpdateEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_ALL::Update Mode */ #define GFX125_3DSTATE_CONSTANT_ALL_UpdateMode_bits 1 #define GFX12_3DSTATE_CONSTANT_ALL_UpdateMode_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_ALL_UpdateMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CONSTANT_ALL_UpdateMode_start 63 #define GFX12_3DSTATE_CONSTANT_ALL_UpdateMode_start 63 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_ALL_UpdateMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 63; case 120: return 63; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_ALL::Vertex Shader Update Enable */ #define GFX125_3DSTATE_CONSTANT_ALL_VertexShaderUpdateEnable_bits 1 #define GFX12_3DSTATE_CONSTANT_ALL_VertexShaderUpdateEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_ALL_VertexShaderUpdateEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CONSTANT_ALL_VertexShaderUpdateEnable_start 8 #define GFX12_3DSTATE_CONSTANT_ALL_VertexShaderUpdateEnable_start 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_ALL_VertexShaderUpdateEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_ALL_DATA */ #define GFX125_3DSTATE_CONSTANT_ALL_DATA_length 2 #define GFX12_3DSTATE_CONSTANT_ALL_DATA_length 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_ALL_DATA_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_ALL_DATA::Constant Buffer Read Length */ #define GFX125_3DSTATE_CONSTANT_ALL_DATA_ConstantBufferReadLength_bits 5 #define GFX12_3DSTATE_CONSTANT_ALL_DATA_ConstantBufferReadLength_bits 5 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_ALL_DATA_ConstantBufferReadLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 5; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CONSTANT_ALL_DATA_ConstantBufferReadLength_start 0 #define GFX12_3DSTATE_CONSTANT_ALL_DATA_ConstantBufferReadLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_ALL_DATA_ConstantBufferReadLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_ALL_DATA::Pointer To Constant Buffer */ #define GFX125_3DSTATE_CONSTANT_ALL_DATA_PointerToConstantBuffer_bits 59 #define GFX12_3DSTATE_CONSTANT_ALL_DATA_PointerToConstantBuffer_bits 59 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_ALL_DATA_PointerToConstantBuffer_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 59; case 120: return 59; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CONSTANT_ALL_DATA_PointerToConstantBuffer_start 5 #define GFX12_3DSTATE_CONSTANT_ALL_DATA_PointerToConstantBuffer_start 5 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_ALL_DATA_PointerToConstantBuffer_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 5; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_BODY */ #define GFX125_3DSTATE_CONSTANT_BODY_length 10 #define GFX12_3DSTATE_CONSTANT_BODY_length 10 #define GFX11_3DSTATE_CONSTANT_BODY_length 10 #define GFX9_3DSTATE_CONSTANT_BODY_length 10 #define GFX8_3DSTATE_CONSTANT_BODY_length 10 #define GFX75_3DSTATE_CONSTANT_BODY_length 6 #define GFX7_3DSTATE_CONSTANT_BODY_length 6 #define GFX6_3DSTATE_CONSTANT_BODY_length 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_BODY_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 10; case 120: return 10; case 110: return 10; case 90: return 10; case 80: return 10; case 75: return 6; case 70: return 6; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_BODY::Constant Buffer 0 Read Length */ #define GFX6_3DSTATE_CONSTANT_BODY_ConstantBuffer0ReadLength_bits 5 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_BODY_ConstantBuffer0ReadLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 5; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_CONSTANT_BODY_ConstantBuffer0ReadLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_BODY_ConstantBuffer0ReadLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_BODY::Constant Buffer 1 Read Length */ #define GFX6_3DSTATE_CONSTANT_BODY_ConstantBuffer1ReadLength_bits 5 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_BODY_ConstantBuffer1ReadLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 5; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_CONSTANT_BODY_ConstantBuffer1ReadLength_start 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_BODY_ConstantBuffer1ReadLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 32; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_BODY::Constant Buffer 2 Read Length */ #define GFX6_3DSTATE_CONSTANT_BODY_ConstantBuffer2ReadLength_bits 5 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_BODY_ConstantBuffer2ReadLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 5; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_CONSTANT_BODY_ConstantBuffer2ReadLength_start 64 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_BODY_ConstantBuffer2ReadLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 64; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_BODY::Constant Buffer 3 Read Length */ #define GFX6_3DSTATE_CONSTANT_BODY_ConstantBuffer3ReadLength_bits 5 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_BODY_ConstantBuffer3ReadLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 5; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_CONSTANT_BODY_ConstantBuffer3ReadLength_start 96 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_BODY_ConstantBuffer3ReadLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 96; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_BODY::MOCS */ #define GFX75_3DSTATE_CONSTANT_BODY_MOCS_bits 5 #define GFX7_3DSTATE_CONSTANT_BODY_MOCS_bits 5 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_BODY_MOCS_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 5; case 70: return 5; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_CONSTANT_BODY_MOCS_start 64 #define GFX7_3DSTATE_CONSTANT_BODY_MOCS_start 64 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_BODY_MOCS_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 64; case 70: return 64; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_BODY::Pointer to Constant Buffer 0 */ #define GFX6_3DSTATE_CONSTANT_BODY_PointertoConstantBuffer0_bits 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_BODY_PointertoConstantBuffer0_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 27; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_CONSTANT_BODY_PointertoConstantBuffer0_start 5 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_BODY_PointertoConstantBuffer0_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 5; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_BODY::Pointer to Constant Buffer 1 */ #define GFX6_3DSTATE_CONSTANT_BODY_PointertoConstantBuffer1_bits 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_BODY_PointertoConstantBuffer1_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 27; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_CONSTANT_BODY_PointertoConstantBuffer1_start 37 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_BODY_PointertoConstantBuffer1_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 37; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_BODY::Pointer to Constant Buffer 2 */ #define GFX6_3DSTATE_CONSTANT_BODY_PointertoConstantBuffer2_bits 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_BODY_PointertoConstantBuffer2_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 27; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_CONSTANT_BODY_PointertoConstantBuffer2_start 69 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_BODY_PointertoConstantBuffer2_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 69; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_BODY::Pointer to Constant Buffer 3 */ #define GFX6_3DSTATE_CONSTANT_BODY_PointertoConstantBuffer3_bits 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_BODY_PointertoConstantBuffer3_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 27; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_CONSTANT_BODY_PointertoConstantBuffer3_start 101 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_BODY_PointertoConstantBuffer3_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 101; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_COLOR */ #define GFX5_3DSTATE_CONSTANT_COLOR_length 5 #define GFX45_3DSTATE_CONSTANT_COLOR_length 5 #define GFX4_3DSTATE_CONSTANT_COLOR_length 5 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_COLOR_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 5; case 45: return 5; case 40: return 5; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_COLOR::3D Command Opcode */ #define GFX5_3DSTATE_CONSTANT_COLOR_3DCommandOpcode_bits 3 #define GFX45_3DSTATE_CONSTANT_COLOR_3DCommandOpcode_bits 3 #define GFX4_3DSTATE_CONSTANT_COLOR_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_COLOR_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX5_3DSTATE_CONSTANT_COLOR_3DCommandOpcode_start 24 #define GFX45_3DSTATE_CONSTANT_COLOR_3DCommandOpcode_start 24 #define GFX4_3DSTATE_CONSTANT_COLOR_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_COLOR_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 24; case 45: return 24; case 40: return 24; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_COLOR::3D Command Sub Opcode */ #define GFX5_3DSTATE_CONSTANT_COLOR_3DCommandSubOpcode_bits 8 #define GFX45_3DSTATE_CONSTANT_COLOR_3DCommandSubOpcode_bits 8 #define GFX4_3DSTATE_CONSTANT_COLOR_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_COLOR_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 8; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } #define GFX5_3DSTATE_CONSTANT_COLOR_3DCommandSubOpcode_start 16 #define GFX45_3DSTATE_CONSTANT_COLOR_3DCommandSubOpcode_start 16 #define GFX4_3DSTATE_CONSTANT_COLOR_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_COLOR_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 16; case 45: return 16; case 40: return 16; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_COLOR::Blend Constant Color Alpha */ #define GFX5_3DSTATE_CONSTANT_COLOR_BlendConstantColorAlpha_bits 32 #define GFX45_3DSTATE_CONSTANT_COLOR_BlendConstantColorAlpha_bits 32 #define GFX4_3DSTATE_CONSTANT_COLOR_BlendConstantColorAlpha_bits 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_COLOR_BlendConstantColorAlpha_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 32; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } #define GFX5_3DSTATE_CONSTANT_COLOR_BlendConstantColorAlpha_start 128 #define GFX45_3DSTATE_CONSTANT_COLOR_BlendConstantColorAlpha_start 128 #define GFX4_3DSTATE_CONSTANT_COLOR_BlendConstantColorAlpha_start 128 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_COLOR_BlendConstantColorAlpha_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 128; case 45: return 128; case 40: return 128; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_COLOR::Blend Constant Color Blue */ #define GFX5_3DSTATE_CONSTANT_COLOR_BlendConstantColorBlue_bits 32 #define GFX45_3DSTATE_CONSTANT_COLOR_BlendConstantColorBlue_bits 32 #define GFX4_3DSTATE_CONSTANT_COLOR_BlendConstantColorBlue_bits 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_COLOR_BlendConstantColorBlue_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 32; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } #define GFX5_3DSTATE_CONSTANT_COLOR_BlendConstantColorBlue_start 96 #define GFX45_3DSTATE_CONSTANT_COLOR_BlendConstantColorBlue_start 96 #define GFX4_3DSTATE_CONSTANT_COLOR_BlendConstantColorBlue_start 96 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_COLOR_BlendConstantColorBlue_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 96; case 45: return 96; case 40: return 96; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_COLOR::Blend Constant Color Green */ #define GFX5_3DSTATE_CONSTANT_COLOR_BlendConstantColorGreen_bits 32 #define GFX45_3DSTATE_CONSTANT_COLOR_BlendConstantColorGreen_bits 32 #define GFX4_3DSTATE_CONSTANT_COLOR_BlendConstantColorGreen_bits 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_COLOR_BlendConstantColorGreen_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 32; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } #define GFX5_3DSTATE_CONSTANT_COLOR_BlendConstantColorGreen_start 64 #define GFX45_3DSTATE_CONSTANT_COLOR_BlendConstantColorGreen_start 64 #define GFX4_3DSTATE_CONSTANT_COLOR_BlendConstantColorGreen_start 64 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_COLOR_BlendConstantColorGreen_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 64; case 45: return 64; case 40: return 64; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_COLOR::Blend Constant Color Red */ #define GFX5_3DSTATE_CONSTANT_COLOR_BlendConstantColorRed_bits 32 #define GFX45_3DSTATE_CONSTANT_COLOR_BlendConstantColorRed_bits 32 #define GFX4_3DSTATE_CONSTANT_COLOR_BlendConstantColorRed_bits 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_COLOR_BlendConstantColorRed_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 32; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } #define GFX5_3DSTATE_CONSTANT_COLOR_BlendConstantColorRed_start 32 #define GFX45_3DSTATE_CONSTANT_COLOR_BlendConstantColorRed_start 32 #define GFX4_3DSTATE_CONSTANT_COLOR_BlendConstantColorRed_start 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_COLOR_BlendConstantColorRed_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 32; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_COLOR::Command SubType */ #define GFX5_3DSTATE_CONSTANT_COLOR_CommandSubType_bits 2 #define GFX45_3DSTATE_CONSTANT_COLOR_CommandSubType_bits 2 #define GFX4_3DSTATE_CONSTANT_COLOR_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_COLOR_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 2; case 45: return 2; case 40: return 2; default: unreachable("Invalid hardware generation"); } } #define GFX5_3DSTATE_CONSTANT_COLOR_CommandSubType_start 27 #define GFX45_3DSTATE_CONSTANT_COLOR_CommandSubType_start 27 #define GFX4_3DSTATE_CONSTANT_COLOR_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_COLOR_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 27; case 45: return 27; case 40: return 27; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_COLOR::Command Type */ #define GFX5_3DSTATE_CONSTANT_COLOR_CommandType_bits 3 #define GFX45_3DSTATE_CONSTANT_COLOR_CommandType_bits 3 #define GFX4_3DSTATE_CONSTANT_COLOR_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_COLOR_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX5_3DSTATE_CONSTANT_COLOR_CommandType_start 29 #define GFX45_3DSTATE_CONSTANT_COLOR_CommandType_start 29 #define GFX4_3DSTATE_CONSTANT_COLOR_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_COLOR_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 29; case 45: return 29; case 40: return 29; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_COLOR::DWord Length */ #define GFX5_3DSTATE_CONSTANT_COLOR_DWordLength_bits 8 #define GFX45_3DSTATE_CONSTANT_COLOR_DWordLength_bits 8 #define GFX4_3DSTATE_CONSTANT_COLOR_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_COLOR_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 8; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } #define GFX5_3DSTATE_CONSTANT_COLOR_DWordLength_start 0 #define GFX45_3DSTATE_CONSTANT_COLOR_DWordLength_start 0 #define GFX4_3DSTATE_CONSTANT_COLOR_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_COLOR_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_DS */ #define GFX125_3DSTATE_CONSTANT_DS_length 11 #define GFX12_3DSTATE_CONSTANT_DS_length 11 #define GFX11_3DSTATE_CONSTANT_DS_length 11 #define GFX9_3DSTATE_CONSTANT_DS_length 11 #define GFX8_3DSTATE_CONSTANT_DS_length 11 #define GFX75_3DSTATE_CONSTANT_DS_length 7 #define GFX7_3DSTATE_CONSTANT_DS_length 7 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_DS_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 11; case 120: return 11; case 110: return 11; case 90: return 11; case 80: return 11; case 75: return 7; case 70: return 7; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_DS::3D Command Opcode */ #define GFX125_3DSTATE_CONSTANT_DS_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_CONSTANT_DS_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_CONSTANT_DS_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_CONSTANT_DS_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_CONSTANT_DS_3DCommandOpcode_bits 3 #define GFX75_3DSTATE_CONSTANT_DS_3DCommandOpcode_bits 3 #define GFX7_3DSTATE_CONSTANT_DS_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_DS_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CONSTANT_DS_3DCommandOpcode_start 24 #define GFX12_3DSTATE_CONSTANT_DS_3DCommandOpcode_start 24 #define GFX11_3DSTATE_CONSTANT_DS_3DCommandOpcode_start 24 #define GFX9_3DSTATE_CONSTANT_DS_3DCommandOpcode_start 24 #define GFX8_3DSTATE_CONSTANT_DS_3DCommandOpcode_start 24 #define GFX75_3DSTATE_CONSTANT_DS_3DCommandOpcode_start 24 #define GFX7_3DSTATE_CONSTANT_DS_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_DS_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_DS::3D Command Sub Opcode */ #define GFX125_3DSTATE_CONSTANT_DS_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_CONSTANT_DS_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_CONSTANT_DS_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_CONSTANT_DS_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_CONSTANT_DS_3DCommandSubOpcode_bits 8 #define GFX75_3DSTATE_CONSTANT_DS_3DCommandSubOpcode_bits 8 #define GFX7_3DSTATE_CONSTANT_DS_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_DS_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CONSTANT_DS_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_CONSTANT_DS_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_CONSTANT_DS_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_CONSTANT_DS_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_CONSTANT_DS_3DCommandSubOpcode_start 16 #define GFX75_3DSTATE_CONSTANT_DS_3DCommandSubOpcode_start 16 #define GFX7_3DSTATE_CONSTANT_DS_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_DS_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_DS::Command SubType */ #define GFX125_3DSTATE_CONSTANT_DS_CommandSubType_bits 2 #define GFX12_3DSTATE_CONSTANT_DS_CommandSubType_bits 2 #define GFX11_3DSTATE_CONSTANT_DS_CommandSubType_bits 2 #define GFX9_3DSTATE_CONSTANT_DS_CommandSubType_bits 2 #define GFX8_3DSTATE_CONSTANT_DS_CommandSubType_bits 2 #define GFX75_3DSTATE_CONSTANT_DS_CommandSubType_bits 2 #define GFX7_3DSTATE_CONSTANT_DS_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_DS_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CONSTANT_DS_CommandSubType_start 27 #define GFX12_3DSTATE_CONSTANT_DS_CommandSubType_start 27 #define GFX11_3DSTATE_CONSTANT_DS_CommandSubType_start 27 #define GFX9_3DSTATE_CONSTANT_DS_CommandSubType_start 27 #define GFX8_3DSTATE_CONSTANT_DS_CommandSubType_start 27 #define GFX75_3DSTATE_CONSTANT_DS_CommandSubType_start 27 #define GFX7_3DSTATE_CONSTANT_DS_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_DS_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_DS::Command Type */ #define GFX125_3DSTATE_CONSTANT_DS_CommandType_bits 3 #define GFX12_3DSTATE_CONSTANT_DS_CommandType_bits 3 #define GFX11_3DSTATE_CONSTANT_DS_CommandType_bits 3 #define GFX9_3DSTATE_CONSTANT_DS_CommandType_bits 3 #define GFX8_3DSTATE_CONSTANT_DS_CommandType_bits 3 #define GFX75_3DSTATE_CONSTANT_DS_CommandType_bits 3 #define GFX7_3DSTATE_CONSTANT_DS_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_DS_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CONSTANT_DS_CommandType_start 29 #define GFX12_3DSTATE_CONSTANT_DS_CommandType_start 29 #define GFX11_3DSTATE_CONSTANT_DS_CommandType_start 29 #define GFX9_3DSTATE_CONSTANT_DS_CommandType_start 29 #define GFX8_3DSTATE_CONSTANT_DS_CommandType_start 29 #define GFX75_3DSTATE_CONSTANT_DS_CommandType_start 29 #define GFX7_3DSTATE_CONSTANT_DS_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_DS_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_DS::Constant Body */ #define GFX125_3DSTATE_CONSTANT_DS_ConstantBody_bits 320 #define GFX12_3DSTATE_CONSTANT_DS_ConstantBody_bits 320 #define GFX11_3DSTATE_CONSTANT_DS_ConstantBody_bits 320 #define GFX9_3DSTATE_CONSTANT_DS_ConstantBody_bits 320 #define GFX8_3DSTATE_CONSTANT_DS_ConstantBody_bits 320 #define GFX75_3DSTATE_CONSTANT_DS_ConstantBody_bits 192 #define GFX7_3DSTATE_CONSTANT_DS_ConstantBody_bits 192 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_DS_ConstantBody_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 320; case 120: return 320; case 110: return 320; case 90: return 320; case 80: return 320; case 75: return 192; case 70: return 192; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CONSTANT_DS_ConstantBody_start 32 #define GFX12_3DSTATE_CONSTANT_DS_ConstantBody_start 32 #define GFX11_3DSTATE_CONSTANT_DS_ConstantBody_start 32 #define GFX9_3DSTATE_CONSTANT_DS_ConstantBody_start 32 #define GFX8_3DSTATE_CONSTANT_DS_ConstantBody_start 32 #define GFX75_3DSTATE_CONSTANT_DS_ConstantBody_start 32 #define GFX7_3DSTATE_CONSTANT_DS_ConstantBody_start 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_DS_ConstantBody_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_DS::DWord Length */ #define GFX125_3DSTATE_CONSTANT_DS_DWordLength_bits 8 #define GFX12_3DSTATE_CONSTANT_DS_DWordLength_bits 8 #define GFX11_3DSTATE_CONSTANT_DS_DWordLength_bits 8 #define GFX9_3DSTATE_CONSTANT_DS_DWordLength_bits 8 #define GFX8_3DSTATE_CONSTANT_DS_DWordLength_bits 8 #define GFX75_3DSTATE_CONSTANT_DS_DWordLength_bits 8 #define GFX7_3DSTATE_CONSTANT_DS_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_DS_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CONSTANT_DS_DWordLength_start 0 #define GFX12_3DSTATE_CONSTANT_DS_DWordLength_start 0 #define GFX11_3DSTATE_CONSTANT_DS_DWordLength_start 0 #define GFX9_3DSTATE_CONSTANT_DS_DWordLength_start 0 #define GFX8_3DSTATE_CONSTANT_DS_DWordLength_start 0 #define GFX75_3DSTATE_CONSTANT_DS_DWordLength_start 0 #define GFX7_3DSTATE_CONSTANT_DS_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_DS_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_DS::MOCS */ #define GFX125_3DSTATE_CONSTANT_DS_MOCS_bits 7 #define GFX12_3DSTATE_CONSTANT_DS_MOCS_bits 7 #define GFX11_3DSTATE_CONSTANT_DS_MOCS_bits 7 #define GFX9_3DSTATE_CONSTANT_DS_MOCS_bits 7 #define GFX8_3DSTATE_CONSTANT_DS_MOCS_bits 7 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_DS_MOCS_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 7; case 120: return 7; case 110: return 7; case 90: return 7; case 80: return 7; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CONSTANT_DS_MOCS_start 8 #define GFX12_3DSTATE_CONSTANT_DS_MOCS_start 8 #define GFX11_3DSTATE_CONSTANT_DS_MOCS_start 8 #define GFX9_3DSTATE_CONSTANT_DS_MOCS_start 8 #define GFX8_3DSTATE_CONSTANT_DS_MOCS_start 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_DS_MOCS_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_GS */ #define GFX125_3DSTATE_CONSTANT_GS_length 11 #define GFX12_3DSTATE_CONSTANT_GS_length 11 #define GFX11_3DSTATE_CONSTANT_GS_length 11 #define GFX9_3DSTATE_CONSTANT_GS_length 11 #define GFX8_3DSTATE_CONSTANT_GS_length 11 #define GFX75_3DSTATE_CONSTANT_GS_length 7 #define GFX7_3DSTATE_CONSTANT_GS_length 7 #define GFX6_3DSTATE_CONSTANT_GS_length 5 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_GS_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 11; case 120: return 11; case 110: return 11; case 90: return 11; case 80: return 11; case 75: return 7; case 70: return 7; case 60: return 5; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_GS::3D Command Opcode */ #define GFX125_3DSTATE_CONSTANT_GS_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_CONSTANT_GS_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_CONSTANT_GS_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_CONSTANT_GS_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_CONSTANT_GS_3DCommandOpcode_bits 3 #define GFX75_3DSTATE_CONSTANT_GS_3DCommandOpcode_bits 3 #define GFX7_3DSTATE_CONSTANT_GS_3DCommandOpcode_bits 3 #define GFX6_3DSTATE_CONSTANT_GS_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_GS_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CONSTANT_GS_3DCommandOpcode_start 24 #define GFX12_3DSTATE_CONSTANT_GS_3DCommandOpcode_start 24 #define GFX11_3DSTATE_CONSTANT_GS_3DCommandOpcode_start 24 #define GFX9_3DSTATE_CONSTANT_GS_3DCommandOpcode_start 24 #define GFX8_3DSTATE_CONSTANT_GS_3DCommandOpcode_start 24 #define GFX75_3DSTATE_CONSTANT_GS_3DCommandOpcode_start 24 #define GFX7_3DSTATE_CONSTANT_GS_3DCommandOpcode_start 24 #define GFX6_3DSTATE_CONSTANT_GS_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_GS_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 24; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_GS::3D Command Sub Opcode */ #define GFX125_3DSTATE_CONSTANT_GS_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_CONSTANT_GS_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_CONSTANT_GS_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_CONSTANT_GS_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_CONSTANT_GS_3DCommandSubOpcode_bits 8 #define GFX75_3DSTATE_CONSTANT_GS_3DCommandSubOpcode_bits 8 #define GFX7_3DSTATE_CONSTANT_GS_3DCommandSubOpcode_bits 8 #define GFX6_3DSTATE_CONSTANT_GS_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_GS_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CONSTANT_GS_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_CONSTANT_GS_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_CONSTANT_GS_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_CONSTANT_GS_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_CONSTANT_GS_3DCommandSubOpcode_start 16 #define GFX75_3DSTATE_CONSTANT_GS_3DCommandSubOpcode_start 16 #define GFX7_3DSTATE_CONSTANT_GS_3DCommandSubOpcode_start 16 #define GFX6_3DSTATE_CONSTANT_GS_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_GS_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 16; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_GS::Buffer 0 Valid */ #define GFX6_3DSTATE_CONSTANT_GS_Buffer0Valid_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_GS_Buffer0Valid_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_CONSTANT_GS_Buffer0Valid_start 12 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_GS_Buffer0Valid_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 12; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_GS::Buffer 1 Valid */ #define GFX6_3DSTATE_CONSTANT_GS_Buffer1Valid_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_GS_Buffer1Valid_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_CONSTANT_GS_Buffer1Valid_start 13 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_GS_Buffer1Valid_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 13; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_GS::Buffer 2 Valid */ #define GFX6_3DSTATE_CONSTANT_GS_Buffer2Valid_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_GS_Buffer2Valid_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_CONSTANT_GS_Buffer2Valid_start 14 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_GS_Buffer2Valid_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 14; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_GS::Buffer 3 Valid */ #define GFX6_3DSTATE_CONSTANT_GS_Buffer3Valid_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_GS_Buffer3Valid_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_CONSTANT_GS_Buffer3Valid_start 15 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_GS_Buffer3Valid_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 15; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_GS::Command SubType */ #define GFX125_3DSTATE_CONSTANT_GS_CommandSubType_bits 2 #define GFX12_3DSTATE_CONSTANT_GS_CommandSubType_bits 2 #define GFX11_3DSTATE_CONSTANT_GS_CommandSubType_bits 2 #define GFX9_3DSTATE_CONSTANT_GS_CommandSubType_bits 2 #define GFX8_3DSTATE_CONSTANT_GS_CommandSubType_bits 2 #define GFX75_3DSTATE_CONSTANT_GS_CommandSubType_bits 2 #define GFX7_3DSTATE_CONSTANT_GS_CommandSubType_bits 2 #define GFX6_3DSTATE_CONSTANT_GS_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_GS_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CONSTANT_GS_CommandSubType_start 27 #define GFX12_3DSTATE_CONSTANT_GS_CommandSubType_start 27 #define GFX11_3DSTATE_CONSTANT_GS_CommandSubType_start 27 #define GFX9_3DSTATE_CONSTANT_GS_CommandSubType_start 27 #define GFX8_3DSTATE_CONSTANT_GS_CommandSubType_start 27 #define GFX75_3DSTATE_CONSTANT_GS_CommandSubType_start 27 #define GFX7_3DSTATE_CONSTANT_GS_CommandSubType_start 27 #define GFX6_3DSTATE_CONSTANT_GS_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_GS_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 27; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_GS::Command Type */ #define GFX125_3DSTATE_CONSTANT_GS_CommandType_bits 3 #define GFX12_3DSTATE_CONSTANT_GS_CommandType_bits 3 #define GFX11_3DSTATE_CONSTANT_GS_CommandType_bits 3 #define GFX9_3DSTATE_CONSTANT_GS_CommandType_bits 3 #define GFX8_3DSTATE_CONSTANT_GS_CommandType_bits 3 #define GFX75_3DSTATE_CONSTANT_GS_CommandType_bits 3 #define GFX7_3DSTATE_CONSTANT_GS_CommandType_bits 3 #define GFX6_3DSTATE_CONSTANT_GS_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_GS_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CONSTANT_GS_CommandType_start 29 #define GFX12_3DSTATE_CONSTANT_GS_CommandType_start 29 #define GFX11_3DSTATE_CONSTANT_GS_CommandType_start 29 #define GFX9_3DSTATE_CONSTANT_GS_CommandType_start 29 #define GFX8_3DSTATE_CONSTANT_GS_CommandType_start 29 #define GFX75_3DSTATE_CONSTANT_GS_CommandType_start 29 #define GFX7_3DSTATE_CONSTANT_GS_CommandType_start 29 #define GFX6_3DSTATE_CONSTANT_GS_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_GS_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 29; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_GS::Constant Body */ #define GFX125_3DSTATE_CONSTANT_GS_ConstantBody_bits 320 #define GFX12_3DSTATE_CONSTANT_GS_ConstantBody_bits 320 #define GFX11_3DSTATE_CONSTANT_GS_ConstantBody_bits 320 #define GFX9_3DSTATE_CONSTANT_GS_ConstantBody_bits 320 #define GFX8_3DSTATE_CONSTANT_GS_ConstantBody_bits 320 #define GFX75_3DSTATE_CONSTANT_GS_ConstantBody_bits 192 #define GFX7_3DSTATE_CONSTANT_GS_ConstantBody_bits 192 #define GFX6_3DSTATE_CONSTANT_GS_ConstantBody_bits 128 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_GS_ConstantBody_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 320; case 120: return 320; case 110: return 320; case 90: return 320; case 80: return 320; case 75: return 192; case 70: return 192; case 60: return 128; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CONSTANT_GS_ConstantBody_start 32 #define GFX12_3DSTATE_CONSTANT_GS_ConstantBody_start 32 #define GFX11_3DSTATE_CONSTANT_GS_ConstantBody_start 32 #define GFX9_3DSTATE_CONSTANT_GS_ConstantBody_start 32 #define GFX8_3DSTATE_CONSTANT_GS_ConstantBody_start 32 #define GFX75_3DSTATE_CONSTANT_GS_ConstantBody_start 32 #define GFX7_3DSTATE_CONSTANT_GS_ConstantBody_start 32 #define GFX6_3DSTATE_CONSTANT_GS_ConstantBody_start 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_GS_ConstantBody_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 32; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_GS::DWord Length */ #define GFX125_3DSTATE_CONSTANT_GS_DWordLength_bits 8 #define GFX12_3DSTATE_CONSTANT_GS_DWordLength_bits 8 #define GFX11_3DSTATE_CONSTANT_GS_DWordLength_bits 8 #define GFX9_3DSTATE_CONSTANT_GS_DWordLength_bits 8 #define GFX8_3DSTATE_CONSTANT_GS_DWordLength_bits 8 #define GFX75_3DSTATE_CONSTANT_GS_DWordLength_bits 8 #define GFX7_3DSTATE_CONSTANT_GS_DWordLength_bits 8 #define GFX6_3DSTATE_CONSTANT_GS_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_GS_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CONSTANT_GS_DWordLength_start 0 #define GFX12_3DSTATE_CONSTANT_GS_DWordLength_start 0 #define GFX11_3DSTATE_CONSTANT_GS_DWordLength_start 0 #define GFX9_3DSTATE_CONSTANT_GS_DWordLength_start 0 #define GFX8_3DSTATE_CONSTANT_GS_DWordLength_start 0 #define GFX75_3DSTATE_CONSTANT_GS_DWordLength_start 0 #define GFX7_3DSTATE_CONSTANT_GS_DWordLength_start 0 #define GFX6_3DSTATE_CONSTANT_GS_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_GS_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_GS::MOCS */ #define GFX125_3DSTATE_CONSTANT_GS_MOCS_bits 7 #define GFX12_3DSTATE_CONSTANT_GS_MOCS_bits 7 #define GFX11_3DSTATE_CONSTANT_GS_MOCS_bits 7 #define GFX9_3DSTATE_CONSTANT_GS_MOCS_bits 7 #define GFX8_3DSTATE_CONSTANT_GS_MOCS_bits 7 #define GFX6_3DSTATE_CONSTANT_GS_MOCS_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_GS_MOCS_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 7; case 120: return 7; case 110: return 7; case 90: return 7; case 80: return 7; case 75: return 0; case 70: return 0; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CONSTANT_GS_MOCS_start 8 #define GFX12_3DSTATE_CONSTANT_GS_MOCS_start 8 #define GFX11_3DSTATE_CONSTANT_GS_MOCS_start 8 #define GFX9_3DSTATE_CONSTANT_GS_MOCS_start 8 #define GFX8_3DSTATE_CONSTANT_GS_MOCS_start 8 #define GFX6_3DSTATE_CONSTANT_GS_MOCS_start 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_GS_MOCS_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_HS */ #define GFX125_3DSTATE_CONSTANT_HS_length 11 #define GFX12_3DSTATE_CONSTANT_HS_length 11 #define GFX11_3DSTATE_CONSTANT_HS_length 11 #define GFX9_3DSTATE_CONSTANT_HS_length 11 #define GFX8_3DSTATE_CONSTANT_HS_length 11 #define GFX75_3DSTATE_CONSTANT_HS_length 7 #define GFX7_3DSTATE_CONSTANT_HS_length 7 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_HS_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 11; case 120: return 11; case 110: return 11; case 90: return 11; case 80: return 11; case 75: return 7; case 70: return 7; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_HS::3D Command Opcode */ #define GFX125_3DSTATE_CONSTANT_HS_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_CONSTANT_HS_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_CONSTANT_HS_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_CONSTANT_HS_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_CONSTANT_HS_3DCommandOpcode_bits 3 #define GFX75_3DSTATE_CONSTANT_HS_3DCommandOpcode_bits 3 #define GFX7_3DSTATE_CONSTANT_HS_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_HS_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CONSTANT_HS_3DCommandOpcode_start 24 #define GFX12_3DSTATE_CONSTANT_HS_3DCommandOpcode_start 24 #define GFX11_3DSTATE_CONSTANT_HS_3DCommandOpcode_start 24 #define GFX9_3DSTATE_CONSTANT_HS_3DCommandOpcode_start 24 #define GFX8_3DSTATE_CONSTANT_HS_3DCommandOpcode_start 24 #define GFX75_3DSTATE_CONSTANT_HS_3DCommandOpcode_start 24 #define GFX7_3DSTATE_CONSTANT_HS_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_HS_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_HS::3D Command Sub Opcode */ #define GFX125_3DSTATE_CONSTANT_HS_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_CONSTANT_HS_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_CONSTANT_HS_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_CONSTANT_HS_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_CONSTANT_HS_3DCommandSubOpcode_bits 8 #define GFX75_3DSTATE_CONSTANT_HS_3DCommandSubOpcode_bits 8 #define GFX7_3DSTATE_CONSTANT_HS_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_HS_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CONSTANT_HS_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_CONSTANT_HS_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_CONSTANT_HS_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_CONSTANT_HS_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_CONSTANT_HS_3DCommandSubOpcode_start 16 #define GFX75_3DSTATE_CONSTANT_HS_3DCommandSubOpcode_start 16 #define GFX7_3DSTATE_CONSTANT_HS_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_HS_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_HS::Command SubType */ #define GFX125_3DSTATE_CONSTANT_HS_CommandSubType_bits 2 #define GFX12_3DSTATE_CONSTANT_HS_CommandSubType_bits 2 #define GFX11_3DSTATE_CONSTANT_HS_CommandSubType_bits 2 #define GFX9_3DSTATE_CONSTANT_HS_CommandSubType_bits 2 #define GFX8_3DSTATE_CONSTANT_HS_CommandSubType_bits 2 #define GFX75_3DSTATE_CONSTANT_HS_CommandSubType_bits 2 #define GFX7_3DSTATE_CONSTANT_HS_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_HS_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CONSTANT_HS_CommandSubType_start 27 #define GFX12_3DSTATE_CONSTANT_HS_CommandSubType_start 27 #define GFX11_3DSTATE_CONSTANT_HS_CommandSubType_start 27 #define GFX9_3DSTATE_CONSTANT_HS_CommandSubType_start 27 #define GFX8_3DSTATE_CONSTANT_HS_CommandSubType_start 27 #define GFX75_3DSTATE_CONSTANT_HS_CommandSubType_start 27 #define GFX7_3DSTATE_CONSTANT_HS_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_HS_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_HS::Command Type */ #define GFX125_3DSTATE_CONSTANT_HS_CommandType_bits 3 #define GFX12_3DSTATE_CONSTANT_HS_CommandType_bits 3 #define GFX11_3DSTATE_CONSTANT_HS_CommandType_bits 3 #define GFX9_3DSTATE_CONSTANT_HS_CommandType_bits 3 #define GFX8_3DSTATE_CONSTANT_HS_CommandType_bits 3 #define GFX75_3DSTATE_CONSTANT_HS_CommandType_bits 3 #define GFX7_3DSTATE_CONSTANT_HS_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_HS_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CONSTANT_HS_CommandType_start 29 #define GFX12_3DSTATE_CONSTANT_HS_CommandType_start 29 #define GFX11_3DSTATE_CONSTANT_HS_CommandType_start 29 #define GFX9_3DSTATE_CONSTANT_HS_CommandType_start 29 #define GFX8_3DSTATE_CONSTANT_HS_CommandType_start 29 #define GFX75_3DSTATE_CONSTANT_HS_CommandType_start 29 #define GFX7_3DSTATE_CONSTANT_HS_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_HS_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_HS::Constant Body */ #define GFX125_3DSTATE_CONSTANT_HS_ConstantBody_bits 320 #define GFX12_3DSTATE_CONSTANT_HS_ConstantBody_bits 320 #define GFX11_3DSTATE_CONSTANT_HS_ConstantBody_bits 320 #define GFX9_3DSTATE_CONSTANT_HS_ConstantBody_bits 320 #define GFX8_3DSTATE_CONSTANT_HS_ConstantBody_bits 320 #define GFX75_3DSTATE_CONSTANT_HS_ConstantBody_bits 192 #define GFX7_3DSTATE_CONSTANT_HS_ConstantBody_bits 192 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_HS_ConstantBody_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 320; case 120: return 320; case 110: return 320; case 90: return 320; case 80: return 320; case 75: return 192; case 70: return 192; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CONSTANT_HS_ConstantBody_start 32 #define GFX12_3DSTATE_CONSTANT_HS_ConstantBody_start 32 #define GFX11_3DSTATE_CONSTANT_HS_ConstantBody_start 32 #define GFX9_3DSTATE_CONSTANT_HS_ConstantBody_start 32 #define GFX8_3DSTATE_CONSTANT_HS_ConstantBody_start 32 #define GFX75_3DSTATE_CONSTANT_HS_ConstantBody_start 32 #define GFX7_3DSTATE_CONSTANT_HS_ConstantBody_start 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_HS_ConstantBody_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_HS::DWord Length */ #define GFX125_3DSTATE_CONSTANT_HS_DWordLength_bits 8 #define GFX12_3DSTATE_CONSTANT_HS_DWordLength_bits 8 #define GFX11_3DSTATE_CONSTANT_HS_DWordLength_bits 8 #define GFX9_3DSTATE_CONSTANT_HS_DWordLength_bits 8 #define GFX8_3DSTATE_CONSTANT_HS_DWordLength_bits 8 #define GFX75_3DSTATE_CONSTANT_HS_DWordLength_bits 8 #define GFX7_3DSTATE_CONSTANT_HS_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_HS_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CONSTANT_HS_DWordLength_start 0 #define GFX12_3DSTATE_CONSTANT_HS_DWordLength_start 0 #define GFX11_3DSTATE_CONSTANT_HS_DWordLength_start 0 #define GFX9_3DSTATE_CONSTANT_HS_DWordLength_start 0 #define GFX8_3DSTATE_CONSTANT_HS_DWordLength_start 0 #define GFX75_3DSTATE_CONSTANT_HS_DWordLength_start 0 #define GFX7_3DSTATE_CONSTANT_HS_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_HS_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_HS::MOCS */ #define GFX125_3DSTATE_CONSTANT_HS_MOCS_bits 7 #define GFX12_3DSTATE_CONSTANT_HS_MOCS_bits 7 #define GFX11_3DSTATE_CONSTANT_HS_MOCS_bits 7 #define GFX9_3DSTATE_CONSTANT_HS_MOCS_bits 7 #define GFX8_3DSTATE_CONSTANT_HS_MOCS_bits 7 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_HS_MOCS_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 7; case 120: return 7; case 110: return 7; case 90: return 7; case 80: return 7; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CONSTANT_HS_MOCS_start 8 #define GFX12_3DSTATE_CONSTANT_HS_MOCS_start 8 #define GFX11_3DSTATE_CONSTANT_HS_MOCS_start 8 #define GFX9_3DSTATE_CONSTANT_HS_MOCS_start 8 #define GFX8_3DSTATE_CONSTANT_HS_MOCS_start 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_HS_MOCS_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_PS */ #define GFX125_3DSTATE_CONSTANT_PS_length 11 #define GFX12_3DSTATE_CONSTANT_PS_length 11 #define GFX11_3DSTATE_CONSTANT_PS_length 11 #define GFX9_3DSTATE_CONSTANT_PS_length 11 #define GFX8_3DSTATE_CONSTANT_PS_length 11 #define GFX75_3DSTATE_CONSTANT_PS_length 7 #define GFX7_3DSTATE_CONSTANT_PS_length 7 #define GFX6_3DSTATE_CONSTANT_PS_length 5 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_PS_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 11; case 120: return 11; case 110: return 11; case 90: return 11; case 80: return 11; case 75: return 7; case 70: return 7; case 60: return 5; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_PS::3D Command Opcode */ #define GFX125_3DSTATE_CONSTANT_PS_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_CONSTANT_PS_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_CONSTANT_PS_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_CONSTANT_PS_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_CONSTANT_PS_3DCommandOpcode_bits 3 #define GFX75_3DSTATE_CONSTANT_PS_3DCommandOpcode_bits 3 #define GFX7_3DSTATE_CONSTANT_PS_3DCommandOpcode_bits 3 #define GFX6_3DSTATE_CONSTANT_PS_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_PS_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CONSTANT_PS_3DCommandOpcode_start 24 #define GFX12_3DSTATE_CONSTANT_PS_3DCommandOpcode_start 24 #define GFX11_3DSTATE_CONSTANT_PS_3DCommandOpcode_start 24 #define GFX9_3DSTATE_CONSTANT_PS_3DCommandOpcode_start 24 #define GFX8_3DSTATE_CONSTANT_PS_3DCommandOpcode_start 24 #define GFX75_3DSTATE_CONSTANT_PS_3DCommandOpcode_start 24 #define GFX7_3DSTATE_CONSTANT_PS_3DCommandOpcode_start 24 #define GFX6_3DSTATE_CONSTANT_PS_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_PS_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 24; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_PS::3D Command Sub Opcode */ #define GFX125_3DSTATE_CONSTANT_PS_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_CONSTANT_PS_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_CONSTANT_PS_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_CONSTANT_PS_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_CONSTANT_PS_3DCommandSubOpcode_bits 8 #define GFX75_3DSTATE_CONSTANT_PS_3DCommandSubOpcode_bits 8 #define GFX7_3DSTATE_CONSTANT_PS_3DCommandSubOpcode_bits 8 #define GFX6_3DSTATE_CONSTANT_PS_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_PS_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CONSTANT_PS_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_CONSTANT_PS_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_CONSTANT_PS_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_CONSTANT_PS_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_CONSTANT_PS_3DCommandSubOpcode_start 16 #define GFX75_3DSTATE_CONSTANT_PS_3DCommandSubOpcode_start 16 #define GFX7_3DSTATE_CONSTANT_PS_3DCommandSubOpcode_start 16 #define GFX6_3DSTATE_CONSTANT_PS_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_PS_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 16; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_PS::Buffer 0 Valid */ #define GFX6_3DSTATE_CONSTANT_PS_Buffer0Valid_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_PS_Buffer0Valid_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_CONSTANT_PS_Buffer0Valid_start 12 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_PS_Buffer0Valid_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 12; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_PS::Buffer 1 Valid */ #define GFX6_3DSTATE_CONSTANT_PS_Buffer1Valid_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_PS_Buffer1Valid_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_CONSTANT_PS_Buffer1Valid_start 13 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_PS_Buffer1Valid_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 13; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_PS::Buffer 2 Valid */ #define GFX6_3DSTATE_CONSTANT_PS_Buffer2Valid_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_PS_Buffer2Valid_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_CONSTANT_PS_Buffer2Valid_start 14 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_PS_Buffer2Valid_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 14; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_PS::Buffer 3 Valid */ #define GFX6_3DSTATE_CONSTANT_PS_Buffer3Valid_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_PS_Buffer3Valid_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_CONSTANT_PS_Buffer3Valid_start 15 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_PS_Buffer3Valid_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 15; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_PS::Command SubType */ #define GFX125_3DSTATE_CONSTANT_PS_CommandSubType_bits 2 #define GFX12_3DSTATE_CONSTANT_PS_CommandSubType_bits 2 #define GFX11_3DSTATE_CONSTANT_PS_CommandSubType_bits 2 #define GFX9_3DSTATE_CONSTANT_PS_CommandSubType_bits 2 #define GFX8_3DSTATE_CONSTANT_PS_CommandSubType_bits 2 #define GFX75_3DSTATE_CONSTANT_PS_CommandSubType_bits 2 #define GFX7_3DSTATE_CONSTANT_PS_CommandSubType_bits 2 #define GFX6_3DSTATE_CONSTANT_PS_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_PS_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CONSTANT_PS_CommandSubType_start 27 #define GFX12_3DSTATE_CONSTANT_PS_CommandSubType_start 27 #define GFX11_3DSTATE_CONSTANT_PS_CommandSubType_start 27 #define GFX9_3DSTATE_CONSTANT_PS_CommandSubType_start 27 #define GFX8_3DSTATE_CONSTANT_PS_CommandSubType_start 27 #define GFX75_3DSTATE_CONSTANT_PS_CommandSubType_start 27 #define GFX7_3DSTATE_CONSTANT_PS_CommandSubType_start 27 #define GFX6_3DSTATE_CONSTANT_PS_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_PS_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 27; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_PS::Command Type */ #define GFX125_3DSTATE_CONSTANT_PS_CommandType_bits 3 #define GFX12_3DSTATE_CONSTANT_PS_CommandType_bits 3 #define GFX11_3DSTATE_CONSTANT_PS_CommandType_bits 3 #define GFX9_3DSTATE_CONSTANT_PS_CommandType_bits 3 #define GFX8_3DSTATE_CONSTANT_PS_CommandType_bits 3 #define GFX75_3DSTATE_CONSTANT_PS_CommandType_bits 3 #define GFX7_3DSTATE_CONSTANT_PS_CommandType_bits 3 #define GFX6_3DSTATE_CONSTANT_PS_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_PS_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CONSTANT_PS_CommandType_start 29 #define GFX12_3DSTATE_CONSTANT_PS_CommandType_start 29 #define GFX11_3DSTATE_CONSTANT_PS_CommandType_start 29 #define GFX9_3DSTATE_CONSTANT_PS_CommandType_start 29 #define GFX8_3DSTATE_CONSTANT_PS_CommandType_start 29 #define GFX75_3DSTATE_CONSTANT_PS_CommandType_start 29 #define GFX7_3DSTATE_CONSTANT_PS_CommandType_start 29 #define GFX6_3DSTATE_CONSTANT_PS_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_PS_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 29; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_PS::Constant Body */ #define GFX125_3DSTATE_CONSTANT_PS_ConstantBody_bits 320 #define GFX12_3DSTATE_CONSTANT_PS_ConstantBody_bits 320 #define GFX11_3DSTATE_CONSTANT_PS_ConstantBody_bits 320 #define GFX9_3DSTATE_CONSTANT_PS_ConstantBody_bits 320 #define GFX8_3DSTATE_CONSTANT_PS_ConstantBody_bits 320 #define GFX75_3DSTATE_CONSTANT_PS_ConstantBody_bits 192 #define GFX7_3DSTATE_CONSTANT_PS_ConstantBody_bits 192 #define GFX6_3DSTATE_CONSTANT_PS_ConstantBody_bits 128 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_PS_ConstantBody_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 320; case 120: return 320; case 110: return 320; case 90: return 320; case 80: return 320; case 75: return 192; case 70: return 192; case 60: return 128; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CONSTANT_PS_ConstantBody_start 32 #define GFX12_3DSTATE_CONSTANT_PS_ConstantBody_start 32 #define GFX11_3DSTATE_CONSTANT_PS_ConstantBody_start 32 #define GFX9_3DSTATE_CONSTANT_PS_ConstantBody_start 32 #define GFX8_3DSTATE_CONSTANT_PS_ConstantBody_start 32 #define GFX75_3DSTATE_CONSTANT_PS_ConstantBody_start 32 #define GFX7_3DSTATE_CONSTANT_PS_ConstantBody_start 32 #define GFX6_3DSTATE_CONSTANT_PS_ConstantBody_start 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_PS_ConstantBody_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 32; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_PS::DWord Length */ #define GFX125_3DSTATE_CONSTANT_PS_DWordLength_bits 8 #define GFX12_3DSTATE_CONSTANT_PS_DWordLength_bits 8 #define GFX11_3DSTATE_CONSTANT_PS_DWordLength_bits 8 #define GFX9_3DSTATE_CONSTANT_PS_DWordLength_bits 8 #define GFX8_3DSTATE_CONSTANT_PS_DWordLength_bits 8 #define GFX75_3DSTATE_CONSTANT_PS_DWordLength_bits 8 #define GFX7_3DSTATE_CONSTANT_PS_DWordLength_bits 8 #define GFX6_3DSTATE_CONSTANT_PS_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_PS_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CONSTANT_PS_DWordLength_start 0 #define GFX12_3DSTATE_CONSTANT_PS_DWordLength_start 0 #define GFX11_3DSTATE_CONSTANT_PS_DWordLength_start 0 #define GFX9_3DSTATE_CONSTANT_PS_DWordLength_start 0 #define GFX8_3DSTATE_CONSTANT_PS_DWordLength_start 0 #define GFX75_3DSTATE_CONSTANT_PS_DWordLength_start 0 #define GFX7_3DSTATE_CONSTANT_PS_DWordLength_start 0 #define GFX6_3DSTATE_CONSTANT_PS_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_PS_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_PS::Disable Gather at Set Shader Hint */ #define GFX125_3DSTATE_CONSTANT_PS_DisableGatheratSetShaderHint_bits 1 #define GFX12_3DSTATE_CONSTANT_PS_DisableGatheratSetShaderHint_bits 1 #define GFX11_3DSTATE_CONSTANT_PS_DisableGatheratSetShaderHint_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_PS_DisableGatheratSetShaderHint_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CONSTANT_PS_DisableGatheratSetShaderHint_start 15 #define GFX12_3DSTATE_CONSTANT_PS_DisableGatheratSetShaderHint_start 15 #define GFX11_3DSTATE_CONSTANT_PS_DisableGatheratSetShaderHint_start 15 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_PS_DisableGatheratSetShaderHint_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 15; case 120: return 15; case 110: return 15; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_PS::MOCS */ #define GFX125_3DSTATE_CONSTANT_PS_MOCS_bits 7 #define GFX12_3DSTATE_CONSTANT_PS_MOCS_bits 7 #define GFX11_3DSTATE_CONSTANT_PS_MOCS_bits 7 #define GFX9_3DSTATE_CONSTANT_PS_MOCS_bits 7 #define GFX8_3DSTATE_CONSTANT_PS_MOCS_bits 7 #define GFX6_3DSTATE_CONSTANT_PS_MOCS_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_PS_MOCS_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 7; case 120: return 7; case 110: return 7; case 90: return 7; case 80: return 7; case 75: return 0; case 70: return 0; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CONSTANT_PS_MOCS_start 8 #define GFX12_3DSTATE_CONSTANT_PS_MOCS_start 8 #define GFX11_3DSTATE_CONSTANT_PS_MOCS_start 8 #define GFX9_3DSTATE_CONSTANT_PS_MOCS_start 8 #define GFX8_3DSTATE_CONSTANT_PS_MOCS_start 8 #define GFX6_3DSTATE_CONSTANT_PS_MOCS_start 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_PS_MOCS_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_VS */ #define GFX125_3DSTATE_CONSTANT_VS_length 11 #define GFX12_3DSTATE_CONSTANT_VS_length 11 #define GFX11_3DSTATE_CONSTANT_VS_length 11 #define GFX9_3DSTATE_CONSTANT_VS_length 11 #define GFX8_3DSTATE_CONSTANT_VS_length 11 #define GFX75_3DSTATE_CONSTANT_VS_length 7 #define GFX7_3DSTATE_CONSTANT_VS_length 7 #define GFX6_3DSTATE_CONSTANT_VS_length 5 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_VS_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 11; case 120: return 11; case 110: return 11; case 90: return 11; case 80: return 11; case 75: return 7; case 70: return 7; case 60: return 5; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_VS::3D Command Opcode */ #define GFX125_3DSTATE_CONSTANT_VS_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_CONSTANT_VS_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_CONSTANT_VS_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_CONSTANT_VS_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_CONSTANT_VS_3DCommandOpcode_bits 3 #define GFX75_3DSTATE_CONSTANT_VS_3DCommandOpcode_bits 3 #define GFX7_3DSTATE_CONSTANT_VS_3DCommandOpcode_bits 3 #define GFX6_3DSTATE_CONSTANT_VS_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_VS_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CONSTANT_VS_3DCommandOpcode_start 24 #define GFX12_3DSTATE_CONSTANT_VS_3DCommandOpcode_start 24 #define GFX11_3DSTATE_CONSTANT_VS_3DCommandOpcode_start 24 #define GFX9_3DSTATE_CONSTANT_VS_3DCommandOpcode_start 24 #define GFX8_3DSTATE_CONSTANT_VS_3DCommandOpcode_start 24 #define GFX75_3DSTATE_CONSTANT_VS_3DCommandOpcode_start 24 #define GFX7_3DSTATE_CONSTANT_VS_3DCommandOpcode_start 24 #define GFX6_3DSTATE_CONSTANT_VS_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_VS_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 24; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_VS::3D Command Sub Opcode */ #define GFX125_3DSTATE_CONSTANT_VS_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_CONSTANT_VS_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_CONSTANT_VS_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_CONSTANT_VS_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_CONSTANT_VS_3DCommandSubOpcode_bits 8 #define GFX75_3DSTATE_CONSTANT_VS_3DCommandSubOpcode_bits 8 #define GFX7_3DSTATE_CONSTANT_VS_3DCommandSubOpcode_bits 8 #define GFX6_3DSTATE_CONSTANT_VS_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_VS_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CONSTANT_VS_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_CONSTANT_VS_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_CONSTANT_VS_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_CONSTANT_VS_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_CONSTANT_VS_3DCommandSubOpcode_start 16 #define GFX75_3DSTATE_CONSTANT_VS_3DCommandSubOpcode_start 16 #define GFX7_3DSTATE_CONSTANT_VS_3DCommandSubOpcode_start 16 #define GFX6_3DSTATE_CONSTANT_VS_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_VS_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 16; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_VS::Buffer 0 Valid */ #define GFX6_3DSTATE_CONSTANT_VS_Buffer0Valid_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_VS_Buffer0Valid_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_CONSTANT_VS_Buffer0Valid_start 12 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_VS_Buffer0Valid_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 12; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_VS::Buffer 1 Valid */ #define GFX6_3DSTATE_CONSTANT_VS_Buffer1Valid_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_VS_Buffer1Valid_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_CONSTANT_VS_Buffer1Valid_start 13 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_VS_Buffer1Valid_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 13; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_VS::Buffer 2 Valid */ #define GFX6_3DSTATE_CONSTANT_VS_Buffer2Valid_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_VS_Buffer2Valid_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_CONSTANT_VS_Buffer2Valid_start 14 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_VS_Buffer2Valid_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 14; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_VS::Buffer 3 Valid */ #define GFX6_3DSTATE_CONSTANT_VS_Buffer3Valid_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_VS_Buffer3Valid_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_CONSTANT_VS_Buffer3Valid_start 15 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_VS_Buffer3Valid_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 15; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_VS::Command SubType */ #define GFX125_3DSTATE_CONSTANT_VS_CommandSubType_bits 2 #define GFX12_3DSTATE_CONSTANT_VS_CommandSubType_bits 2 #define GFX11_3DSTATE_CONSTANT_VS_CommandSubType_bits 2 #define GFX9_3DSTATE_CONSTANT_VS_CommandSubType_bits 2 #define GFX8_3DSTATE_CONSTANT_VS_CommandSubType_bits 2 #define GFX75_3DSTATE_CONSTANT_VS_CommandSubType_bits 2 #define GFX7_3DSTATE_CONSTANT_VS_CommandSubType_bits 2 #define GFX6_3DSTATE_CONSTANT_VS_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_VS_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CONSTANT_VS_CommandSubType_start 27 #define GFX12_3DSTATE_CONSTANT_VS_CommandSubType_start 27 #define GFX11_3DSTATE_CONSTANT_VS_CommandSubType_start 27 #define GFX9_3DSTATE_CONSTANT_VS_CommandSubType_start 27 #define GFX8_3DSTATE_CONSTANT_VS_CommandSubType_start 27 #define GFX75_3DSTATE_CONSTANT_VS_CommandSubType_start 27 #define GFX7_3DSTATE_CONSTANT_VS_CommandSubType_start 27 #define GFX6_3DSTATE_CONSTANT_VS_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_VS_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 27; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_VS::Command Type */ #define GFX125_3DSTATE_CONSTANT_VS_CommandType_bits 3 #define GFX12_3DSTATE_CONSTANT_VS_CommandType_bits 3 #define GFX11_3DSTATE_CONSTANT_VS_CommandType_bits 3 #define GFX9_3DSTATE_CONSTANT_VS_CommandType_bits 3 #define GFX8_3DSTATE_CONSTANT_VS_CommandType_bits 3 #define GFX75_3DSTATE_CONSTANT_VS_CommandType_bits 3 #define GFX7_3DSTATE_CONSTANT_VS_CommandType_bits 3 #define GFX6_3DSTATE_CONSTANT_VS_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_VS_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CONSTANT_VS_CommandType_start 29 #define GFX12_3DSTATE_CONSTANT_VS_CommandType_start 29 #define GFX11_3DSTATE_CONSTANT_VS_CommandType_start 29 #define GFX9_3DSTATE_CONSTANT_VS_CommandType_start 29 #define GFX8_3DSTATE_CONSTANT_VS_CommandType_start 29 #define GFX75_3DSTATE_CONSTANT_VS_CommandType_start 29 #define GFX7_3DSTATE_CONSTANT_VS_CommandType_start 29 #define GFX6_3DSTATE_CONSTANT_VS_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_VS_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 29; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_VS::Constant Body */ #define GFX125_3DSTATE_CONSTANT_VS_ConstantBody_bits 320 #define GFX12_3DSTATE_CONSTANT_VS_ConstantBody_bits 320 #define GFX11_3DSTATE_CONSTANT_VS_ConstantBody_bits 320 #define GFX9_3DSTATE_CONSTANT_VS_ConstantBody_bits 320 #define GFX8_3DSTATE_CONSTANT_VS_ConstantBody_bits 320 #define GFX75_3DSTATE_CONSTANT_VS_ConstantBody_bits 192 #define GFX7_3DSTATE_CONSTANT_VS_ConstantBody_bits 192 #define GFX6_3DSTATE_CONSTANT_VS_ConstantBody_bits 128 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_VS_ConstantBody_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 320; case 120: return 320; case 110: return 320; case 90: return 320; case 80: return 320; case 75: return 192; case 70: return 192; case 60: return 128; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CONSTANT_VS_ConstantBody_start 32 #define GFX12_3DSTATE_CONSTANT_VS_ConstantBody_start 32 #define GFX11_3DSTATE_CONSTANT_VS_ConstantBody_start 32 #define GFX9_3DSTATE_CONSTANT_VS_ConstantBody_start 32 #define GFX8_3DSTATE_CONSTANT_VS_ConstantBody_start 32 #define GFX75_3DSTATE_CONSTANT_VS_ConstantBody_start 32 #define GFX7_3DSTATE_CONSTANT_VS_ConstantBody_start 32 #define GFX6_3DSTATE_CONSTANT_VS_ConstantBody_start 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_VS_ConstantBody_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 32; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_VS::DWord Length */ #define GFX125_3DSTATE_CONSTANT_VS_DWordLength_bits 8 #define GFX12_3DSTATE_CONSTANT_VS_DWordLength_bits 8 #define GFX11_3DSTATE_CONSTANT_VS_DWordLength_bits 8 #define GFX9_3DSTATE_CONSTANT_VS_DWordLength_bits 8 #define GFX8_3DSTATE_CONSTANT_VS_DWordLength_bits 8 #define GFX75_3DSTATE_CONSTANT_VS_DWordLength_bits 8 #define GFX7_3DSTATE_CONSTANT_VS_DWordLength_bits 8 #define GFX6_3DSTATE_CONSTANT_VS_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_VS_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CONSTANT_VS_DWordLength_start 0 #define GFX12_3DSTATE_CONSTANT_VS_DWordLength_start 0 #define GFX11_3DSTATE_CONSTANT_VS_DWordLength_start 0 #define GFX9_3DSTATE_CONSTANT_VS_DWordLength_start 0 #define GFX8_3DSTATE_CONSTANT_VS_DWordLength_start 0 #define GFX75_3DSTATE_CONSTANT_VS_DWordLength_start 0 #define GFX7_3DSTATE_CONSTANT_VS_DWordLength_start 0 #define GFX6_3DSTATE_CONSTANT_VS_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_VS_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CONSTANT_VS::MOCS */ #define GFX125_3DSTATE_CONSTANT_VS_MOCS_bits 7 #define GFX12_3DSTATE_CONSTANT_VS_MOCS_bits 7 #define GFX11_3DSTATE_CONSTANT_VS_MOCS_bits 7 #define GFX9_3DSTATE_CONSTANT_VS_MOCS_bits 7 #define GFX8_3DSTATE_CONSTANT_VS_MOCS_bits 7 #define GFX6_3DSTATE_CONSTANT_VS_MOCS_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_VS_MOCS_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 7; case 120: return 7; case 110: return 7; case 90: return 7; case 80: return 7; case 75: return 0; case 70: return 0; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CONSTANT_VS_MOCS_start 8 #define GFX12_3DSTATE_CONSTANT_VS_MOCS_start 8 #define GFX11_3DSTATE_CONSTANT_VS_MOCS_start 8 #define GFX9_3DSTATE_CONSTANT_VS_MOCS_start 8 #define GFX8_3DSTATE_CONSTANT_VS_MOCS_start 8 #define GFX6_3DSTATE_CONSTANT_VS_MOCS_start 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CONSTANT_VS_MOCS_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CPS */ #define GFX11_3DSTATE_CPS_length 9 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CPS_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 9; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CPS::3D Command Opcode */ #define GFX11_3DSTATE_CPS_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CPS_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 3; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX11_3DSTATE_CPS_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CPS_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 24; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CPS::3D Command Sub Opcode */ #define GFX11_3DSTATE_CPS_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CPS_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 8; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX11_3DSTATE_CPS_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CPS_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 16; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CPS::Aspect */ #define GFX11_3DSTATE_CPS_Aspect_bits 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CPS_Aspect_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 32; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX11_3DSTATE_CPS_Aspect_start 256 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CPS_Aspect_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 256; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CPS::Coarse Pixel Shading Mode */ #define GFX11_3DSTATE_CPS_CoarsePixelShadingMode_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CPS_CoarsePixelShadingMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 2; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX11_3DSTATE_CPS_CoarsePixelShadingMode_start 44 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CPS_CoarsePixelShadingMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 44; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CPS::Command SubType */ #define GFX11_3DSTATE_CPS_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CPS_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 2; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX11_3DSTATE_CPS_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CPS_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 27; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CPS::Command Type */ #define GFX11_3DSTATE_CPS_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CPS_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 3; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX11_3DSTATE_CPS_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CPS_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 29; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CPS::DWord Length */ #define GFX11_3DSTATE_CPS_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CPS_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 8; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX11_3DSTATE_CPS_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CPS_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CPS::Max CP Size X */ #define GFX11_3DSTATE_CPS_MaxCPSizeX_bits 11 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CPS_MaxCPSizeX_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 11; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX11_3DSTATE_CPS_MaxCPSizeX_start 64 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CPS_MaxCPSizeX_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 64; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CPS::Max CP Size Y */ #define GFX11_3DSTATE_CPS_MaxCPSizeY_bits 11 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CPS_MaxCPSizeY_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 11; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX11_3DSTATE_CPS_MaxCPSizeY_start 80 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CPS_MaxCPSizeY_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 80; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CPS::Min CP Size X */ #define GFX11_3DSTATE_CPS_MinCPSizeX_bits 11 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CPS_MinCPSizeX_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 11; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX11_3DSTATE_CPS_MinCPSizeX_start 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CPS_MinCPSizeX_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 32; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CPS::Min CP Size Y */ #define GFX11_3DSTATE_CPS_MinCPSizeY_bits 11 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CPS_MinCPSizeY_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 11; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX11_3DSTATE_CPS_MinCPSizeY_start 48 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CPS_MinCPSizeY_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 48; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CPS::M x */ #define GFX11_3DSTATE_CPS_Mx_bits 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CPS_Mx_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 32; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX11_3DSTATE_CPS_Mx_start 192 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CPS_Mx_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 192; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CPS::M y */ #define GFX11_3DSTATE_CPS_My_bits 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CPS_My_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 32; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX11_3DSTATE_CPS_My_start 160 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CPS_My_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 160; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CPS::R min */ #define GFX11_3DSTATE_CPS_Rmin_bits 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CPS_Rmin_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 32; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX11_3DSTATE_CPS_Rmin_start 224 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CPS_Rmin_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 224; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CPS::Scale Axis */ #define GFX11_3DSTATE_CPS_ScaleAxis_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CPS_ScaleAxis_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX11_3DSTATE_CPS_ScaleAxis_start 46 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CPS_ScaleAxis_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 46; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CPS::Statistics Enable */ #define GFX11_3DSTATE_CPS_StatisticsEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CPS_StatisticsEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX11_3DSTATE_CPS_StatisticsEnable_start 43 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CPS_StatisticsEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 43; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CPS::X Focal */ #define GFX11_3DSTATE_CPS_XFocal_bits 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CPS_XFocal_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 16; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX11_3DSTATE_CPS_XFocal_start 128 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CPS_XFocal_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 128; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CPS::Y Focal */ #define GFX11_3DSTATE_CPS_YFocal_bits 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CPS_YFocal_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 16; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX11_3DSTATE_CPS_YFocal_start 96 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CPS_YFocal_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 96; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CPS_POINTERS */ #define GFX125_3DSTATE_CPS_POINTERS_length 2 #define GFX12_3DSTATE_CPS_POINTERS_length 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CPS_POINTERS_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CPS_POINTERS::3D Command Opcode */ #define GFX125_3DSTATE_CPS_POINTERS_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_CPS_POINTERS_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CPS_POINTERS_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CPS_POINTERS_3DCommandOpcode_start 24 #define GFX12_3DSTATE_CPS_POINTERS_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CPS_POINTERS_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CPS_POINTERS::3D Command Sub Opcode */ #define GFX125_3DSTATE_CPS_POINTERS_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_CPS_POINTERS_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CPS_POINTERS_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CPS_POINTERS_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_CPS_POINTERS_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CPS_POINTERS_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CPS_POINTERS::Coarse Pixel Shading State Array Pointer */ #define GFX125_3DSTATE_CPS_POINTERS_CoarsePixelShadingStateArrayPointer_bits 27 #define GFX12_3DSTATE_CPS_POINTERS_CoarsePixelShadingStateArrayPointer_bits 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CPS_POINTERS_CoarsePixelShadingStateArrayPointer_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CPS_POINTERS_CoarsePixelShadingStateArrayPointer_start 37 #define GFX12_3DSTATE_CPS_POINTERS_CoarsePixelShadingStateArrayPointer_start 37 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CPS_POINTERS_CoarsePixelShadingStateArrayPointer_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 37; case 120: return 37; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CPS_POINTERS::Command SubType */ #define GFX125_3DSTATE_CPS_POINTERS_CommandSubType_bits 2 #define GFX12_3DSTATE_CPS_POINTERS_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CPS_POINTERS_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CPS_POINTERS_CommandSubType_start 27 #define GFX12_3DSTATE_CPS_POINTERS_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CPS_POINTERS_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CPS_POINTERS::Command Type */ #define GFX125_3DSTATE_CPS_POINTERS_CommandType_bits 3 #define GFX12_3DSTATE_CPS_POINTERS_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CPS_POINTERS_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CPS_POINTERS_CommandType_start 29 #define GFX12_3DSTATE_CPS_POINTERS_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CPS_POINTERS_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_CPS_POINTERS::DWord Length */ #define GFX125_3DSTATE_CPS_POINTERS_DWordLength_bits 16 #define GFX12_3DSTATE_CPS_POINTERS_DWordLength_bits 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CPS_POINTERS_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_CPS_POINTERS_DWordLength_start 0 #define GFX12_3DSTATE_CPS_POINTERS_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_CPS_POINTERS_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DEPTH_BOUNDS */ #define GFX125_3DSTATE_DEPTH_BOUNDS_length 4 #define GFX12_3DSTATE_DEPTH_BOUNDS_length 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BOUNDS_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DEPTH_BOUNDS::3D Command Opcode */ #define GFX125_3DSTATE_DEPTH_BOUNDS_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_DEPTH_BOUNDS_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BOUNDS_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DEPTH_BOUNDS_3DCommandOpcode_start 24 #define GFX12_3DSTATE_DEPTH_BOUNDS_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BOUNDS_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DEPTH_BOUNDS::3DSTATE Command Sub Opcode */ #define GFX125_3DSTATE_DEPTH_BOUNDS_3DSTATECommandSubOpcode_bits 8 #define GFX12_3DSTATE_DEPTH_BOUNDS_3DSTATECommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BOUNDS_3DSTATECommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DEPTH_BOUNDS_3DSTATECommandSubOpcode_start 16 #define GFX12_3DSTATE_DEPTH_BOUNDS_3DSTATECommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BOUNDS_3DSTATECommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DEPTH_BOUNDS::Command SubType */ #define GFX125_3DSTATE_DEPTH_BOUNDS_CommandSubType_bits 2 #define GFX12_3DSTATE_DEPTH_BOUNDS_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BOUNDS_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DEPTH_BOUNDS_CommandSubType_start 27 #define GFX12_3DSTATE_DEPTH_BOUNDS_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BOUNDS_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DEPTH_BOUNDS::Command Type */ #define GFX125_3DSTATE_DEPTH_BOUNDS_CommandType_bits 3 #define GFX12_3DSTATE_DEPTH_BOUNDS_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BOUNDS_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DEPTH_BOUNDS_CommandType_start 29 #define GFX12_3DSTATE_DEPTH_BOUNDS_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BOUNDS_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DEPTH_BOUNDS::Depth Bounds Test Enable */ #define GFX125_3DSTATE_DEPTH_BOUNDS_DepthBoundsTestEnable_bits 1 #define GFX12_3DSTATE_DEPTH_BOUNDS_DepthBoundsTestEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BOUNDS_DepthBoundsTestEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DEPTH_BOUNDS_DepthBoundsTestEnable_start 32 #define GFX12_3DSTATE_DEPTH_BOUNDS_DepthBoundsTestEnable_start 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BOUNDS_DepthBoundsTestEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DEPTH_BOUNDS::Depth Bounds Test Enable Modify Disable */ #define GFX125_3DSTATE_DEPTH_BOUNDS_DepthBoundsTestEnableModifyDisable_bits 1 #define GFX12_3DSTATE_DEPTH_BOUNDS_DepthBoundsTestEnableModifyDisable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BOUNDS_DepthBoundsTestEnableModifyDisable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DEPTH_BOUNDS_DepthBoundsTestEnableModifyDisable_start 15 #define GFX12_3DSTATE_DEPTH_BOUNDS_DepthBoundsTestEnableModifyDisable_start 15 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BOUNDS_DepthBoundsTestEnableModifyDisable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 15; case 120: return 15; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DEPTH_BOUNDS::Depth Bounds Test Max Value */ #define GFX125_3DSTATE_DEPTH_BOUNDS_DepthBoundsTestMaxValue_bits 32 #define GFX12_3DSTATE_DEPTH_BOUNDS_DepthBoundsTestMaxValue_bits 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BOUNDS_DepthBoundsTestMaxValue_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DEPTH_BOUNDS_DepthBoundsTestMaxValue_start 96 #define GFX12_3DSTATE_DEPTH_BOUNDS_DepthBoundsTestMaxValue_start 96 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BOUNDS_DepthBoundsTestMaxValue_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 96; case 120: return 96; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DEPTH_BOUNDS::Depth Bounds Test Min Value */ #define GFX125_3DSTATE_DEPTH_BOUNDS_DepthBoundsTestMinValue_bits 32 #define GFX12_3DSTATE_DEPTH_BOUNDS_DepthBoundsTestMinValue_bits 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BOUNDS_DepthBoundsTestMinValue_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DEPTH_BOUNDS_DepthBoundsTestMinValue_start 64 #define GFX12_3DSTATE_DEPTH_BOUNDS_DepthBoundsTestMinValue_start 64 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BOUNDS_DepthBoundsTestMinValue_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DEPTH_BOUNDS::Depth Bounds Test Value Modify Disable */ #define GFX125_3DSTATE_DEPTH_BOUNDS_DepthBoundsTestValueModifyDisable_bits 1 #define GFX12_3DSTATE_DEPTH_BOUNDS_DepthBoundsTestValueModifyDisable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BOUNDS_DepthBoundsTestValueModifyDisable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DEPTH_BOUNDS_DepthBoundsTestValueModifyDisable_start 14 #define GFX12_3DSTATE_DEPTH_BOUNDS_DepthBoundsTestValueModifyDisable_start 14 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BOUNDS_DepthBoundsTestValueModifyDisable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 14; case 120: return 14; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DEPTH_BOUNDS::Length */ #define GFX125_3DSTATE_DEPTH_BOUNDS_Length_bits 8 #define GFX12_3DSTATE_DEPTH_BOUNDS_Length_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BOUNDS_Length_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DEPTH_BOUNDS_Length_start 0 #define GFX12_3DSTATE_DEPTH_BOUNDS_Length_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BOUNDS_Length_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DEPTH_BUFFER */ #define GFX125_3DSTATE_DEPTH_BUFFER_length 8 #define GFX12_3DSTATE_DEPTH_BUFFER_length 8 #define GFX11_3DSTATE_DEPTH_BUFFER_length 8 #define GFX9_3DSTATE_DEPTH_BUFFER_length 8 #define GFX8_3DSTATE_DEPTH_BUFFER_length 8 #define GFX75_3DSTATE_DEPTH_BUFFER_length 7 #define GFX7_3DSTATE_DEPTH_BUFFER_length 7 #define GFX6_3DSTATE_DEPTH_BUFFER_length 7 #define GFX5_3DSTATE_DEPTH_BUFFER_length 6 #define GFX45_3DSTATE_DEPTH_BUFFER_length 6 #define GFX4_3DSTATE_DEPTH_BUFFER_length 5 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BUFFER_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 7; case 70: return 7; case 60: return 7; case 50: return 6; case 45: return 6; case 40: return 5; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DEPTH_BUFFER::3D Command Opcode */ #define GFX125_3DSTATE_DEPTH_BUFFER_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_DEPTH_BUFFER_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_DEPTH_BUFFER_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_DEPTH_BUFFER_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_DEPTH_BUFFER_3DCommandOpcode_bits 3 #define GFX75_3DSTATE_DEPTH_BUFFER_3DCommandOpcode_bits 3 #define GFX7_3DSTATE_DEPTH_BUFFER_3DCommandOpcode_bits 3 #define GFX6_3DSTATE_DEPTH_BUFFER_3DCommandOpcode_bits 3 #define GFX5_3DSTATE_DEPTH_BUFFER_3DCommandOpcode_bits 3 #define GFX45_3DSTATE_DEPTH_BUFFER_3DCommandOpcode_bits 3 #define GFX4_3DSTATE_DEPTH_BUFFER_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BUFFER_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DEPTH_BUFFER_3DCommandOpcode_start 24 #define GFX12_3DSTATE_DEPTH_BUFFER_3DCommandOpcode_start 24 #define GFX11_3DSTATE_DEPTH_BUFFER_3DCommandOpcode_start 24 #define GFX9_3DSTATE_DEPTH_BUFFER_3DCommandOpcode_start 24 #define GFX8_3DSTATE_DEPTH_BUFFER_3DCommandOpcode_start 24 #define GFX75_3DSTATE_DEPTH_BUFFER_3DCommandOpcode_start 24 #define GFX7_3DSTATE_DEPTH_BUFFER_3DCommandOpcode_start 24 #define GFX6_3DSTATE_DEPTH_BUFFER_3DCommandOpcode_start 24 #define GFX5_3DSTATE_DEPTH_BUFFER_3DCommandOpcode_start 24 #define GFX45_3DSTATE_DEPTH_BUFFER_3DCommandOpcode_start 24 #define GFX4_3DSTATE_DEPTH_BUFFER_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BUFFER_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 24; case 50: return 24; case 45: return 24; case 40: return 24; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DEPTH_BUFFER::3D Command Sub Opcode */ #define GFX125_3DSTATE_DEPTH_BUFFER_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_DEPTH_BUFFER_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_DEPTH_BUFFER_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_DEPTH_BUFFER_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_DEPTH_BUFFER_3DCommandSubOpcode_bits 8 #define GFX75_3DSTATE_DEPTH_BUFFER_3DCommandSubOpcode_bits 8 #define GFX7_3DSTATE_DEPTH_BUFFER_3DCommandSubOpcode_bits 8 #define GFX6_3DSTATE_DEPTH_BUFFER_3DCommandSubOpcode_bits 8 #define GFX5_3DSTATE_DEPTH_BUFFER_3DCommandSubOpcode_bits 8 #define GFX45_3DSTATE_DEPTH_BUFFER_3DCommandSubOpcode_bits 8 #define GFX4_3DSTATE_DEPTH_BUFFER_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BUFFER_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 8; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DEPTH_BUFFER_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_DEPTH_BUFFER_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_DEPTH_BUFFER_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_DEPTH_BUFFER_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_DEPTH_BUFFER_3DCommandSubOpcode_start 16 #define GFX75_3DSTATE_DEPTH_BUFFER_3DCommandSubOpcode_start 16 #define GFX7_3DSTATE_DEPTH_BUFFER_3DCommandSubOpcode_start 16 #define GFX6_3DSTATE_DEPTH_BUFFER_3DCommandSubOpcode_start 16 #define GFX5_3DSTATE_DEPTH_BUFFER_3DCommandSubOpcode_start 16 #define GFX45_3DSTATE_DEPTH_BUFFER_3DCommandSubOpcode_start 16 #define GFX4_3DSTATE_DEPTH_BUFFER_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BUFFER_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 16; case 50: return 16; case 45: return 16; case 40: return 16; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DEPTH_BUFFER::Command SubType */ #define GFX125_3DSTATE_DEPTH_BUFFER_CommandSubType_bits 2 #define GFX12_3DSTATE_DEPTH_BUFFER_CommandSubType_bits 2 #define GFX11_3DSTATE_DEPTH_BUFFER_CommandSubType_bits 2 #define GFX9_3DSTATE_DEPTH_BUFFER_CommandSubType_bits 2 #define GFX8_3DSTATE_DEPTH_BUFFER_CommandSubType_bits 2 #define GFX75_3DSTATE_DEPTH_BUFFER_CommandSubType_bits 2 #define GFX7_3DSTATE_DEPTH_BUFFER_CommandSubType_bits 2 #define GFX6_3DSTATE_DEPTH_BUFFER_CommandSubType_bits 2 #define GFX5_3DSTATE_DEPTH_BUFFER_CommandSubType_bits 2 #define GFX45_3DSTATE_DEPTH_BUFFER_CommandSubType_bits 2 #define GFX4_3DSTATE_DEPTH_BUFFER_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BUFFER_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 2; case 45: return 2; case 40: return 2; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DEPTH_BUFFER_CommandSubType_start 27 #define GFX12_3DSTATE_DEPTH_BUFFER_CommandSubType_start 27 #define GFX11_3DSTATE_DEPTH_BUFFER_CommandSubType_start 27 #define GFX9_3DSTATE_DEPTH_BUFFER_CommandSubType_start 27 #define GFX8_3DSTATE_DEPTH_BUFFER_CommandSubType_start 27 #define GFX75_3DSTATE_DEPTH_BUFFER_CommandSubType_start 27 #define GFX7_3DSTATE_DEPTH_BUFFER_CommandSubType_start 27 #define GFX6_3DSTATE_DEPTH_BUFFER_CommandSubType_start 27 #define GFX5_3DSTATE_DEPTH_BUFFER_CommandSubType_start 27 #define GFX45_3DSTATE_DEPTH_BUFFER_CommandSubType_start 27 #define GFX4_3DSTATE_DEPTH_BUFFER_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BUFFER_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 27; case 50: return 27; case 45: return 27; case 40: return 27; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DEPTH_BUFFER::Command Type */ #define GFX125_3DSTATE_DEPTH_BUFFER_CommandType_bits 3 #define GFX12_3DSTATE_DEPTH_BUFFER_CommandType_bits 3 #define GFX11_3DSTATE_DEPTH_BUFFER_CommandType_bits 3 #define GFX9_3DSTATE_DEPTH_BUFFER_CommandType_bits 3 #define GFX8_3DSTATE_DEPTH_BUFFER_CommandType_bits 3 #define GFX75_3DSTATE_DEPTH_BUFFER_CommandType_bits 3 #define GFX7_3DSTATE_DEPTH_BUFFER_CommandType_bits 3 #define GFX6_3DSTATE_DEPTH_BUFFER_CommandType_bits 3 #define GFX5_3DSTATE_DEPTH_BUFFER_CommandType_bits 3 #define GFX45_3DSTATE_DEPTH_BUFFER_CommandType_bits 3 #define GFX4_3DSTATE_DEPTH_BUFFER_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BUFFER_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DEPTH_BUFFER_CommandType_start 29 #define GFX12_3DSTATE_DEPTH_BUFFER_CommandType_start 29 #define GFX11_3DSTATE_DEPTH_BUFFER_CommandType_start 29 #define GFX9_3DSTATE_DEPTH_BUFFER_CommandType_start 29 #define GFX8_3DSTATE_DEPTH_BUFFER_CommandType_start 29 #define GFX75_3DSTATE_DEPTH_BUFFER_CommandType_start 29 #define GFX7_3DSTATE_DEPTH_BUFFER_CommandType_start 29 #define GFX6_3DSTATE_DEPTH_BUFFER_CommandType_start 29 #define GFX5_3DSTATE_DEPTH_BUFFER_CommandType_start 29 #define GFX45_3DSTATE_DEPTH_BUFFER_CommandType_start 29 #define GFX4_3DSTATE_DEPTH_BUFFER_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BUFFER_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 29; case 50: return 29; case 45: return 29; case 40: return 29; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DEPTH_BUFFER::Compression Mode */ #define GFX125_3DSTATE_DEPTH_BUFFER_CompressionMode_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BUFFER_CompressionMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DEPTH_BUFFER_CompressionMode_start 197 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BUFFER_CompressionMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 197; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DEPTH_BUFFER::Control Surface Enable */ #define GFX125_3DSTATE_DEPTH_BUFFER_ControlSurfaceEnable_bits 1 #define GFX12_3DSTATE_DEPTH_BUFFER_ControlSurfaceEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BUFFER_ControlSurfaceEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DEPTH_BUFFER_ControlSurfaceEnable_start 51 #define GFX12_3DSTATE_DEPTH_BUFFER_ControlSurfaceEnable_start 51 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BUFFER_ControlSurfaceEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 51; case 120: return 51; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DEPTH_BUFFER::Corner Texel Mode */ #define GFX125_3DSTATE_DEPTH_BUFFER_CornerTexelMode_bits 1 #define GFX12_3DSTATE_DEPTH_BUFFER_CornerTexelMode_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BUFFER_CornerTexelMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DEPTH_BUFFER_CornerTexelMode_start 55 #define GFX12_3DSTATE_DEPTH_BUFFER_CornerTexelMode_start 55 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BUFFER_CornerTexelMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 55; case 120: return 55; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DEPTH_BUFFER::DWord Length */ #define GFX125_3DSTATE_DEPTH_BUFFER_DWordLength_bits 8 #define GFX12_3DSTATE_DEPTH_BUFFER_DWordLength_bits 8 #define GFX11_3DSTATE_DEPTH_BUFFER_DWordLength_bits 8 #define GFX9_3DSTATE_DEPTH_BUFFER_DWordLength_bits 8 #define GFX8_3DSTATE_DEPTH_BUFFER_DWordLength_bits 8 #define GFX75_3DSTATE_DEPTH_BUFFER_DWordLength_bits 8 #define GFX7_3DSTATE_DEPTH_BUFFER_DWordLength_bits 8 #define GFX6_3DSTATE_DEPTH_BUFFER_DWordLength_bits 8 #define GFX5_3DSTATE_DEPTH_BUFFER_DWordLength_bits 8 #define GFX45_3DSTATE_DEPTH_BUFFER_DWordLength_bits 8 #define GFX4_3DSTATE_DEPTH_BUFFER_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BUFFER_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 8; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DEPTH_BUFFER_DWordLength_start 0 #define GFX12_3DSTATE_DEPTH_BUFFER_DWordLength_start 0 #define GFX11_3DSTATE_DEPTH_BUFFER_DWordLength_start 0 #define GFX9_3DSTATE_DEPTH_BUFFER_DWordLength_start 0 #define GFX8_3DSTATE_DEPTH_BUFFER_DWordLength_start 0 #define GFX75_3DSTATE_DEPTH_BUFFER_DWordLength_start 0 #define GFX7_3DSTATE_DEPTH_BUFFER_DWordLength_start 0 #define GFX6_3DSTATE_DEPTH_BUFFER_DWordLength_start 0 #define GFX5_3DSTATE_DEPTH_BUFFER_DWordLength_start 0 #define GFX45_3DSTATE_DEPTH_BUFFER_DWordLength_start 0 #define GFX4_3DSTATE_DEPTH_BUFFER_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BUFFER_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DEPTH_BUFFER::Depth */ #define GFX125_3DSTATE_DEPTH_BUFFER_Depth_bits 11 #define GFX12_3DSTATE_DEPTH_BUFFER_Depth_bits 11 #define GFX11_3DSTATE_DEPTH_BUFFER_Depth_bits 11 #define GFX9_3DSTATE_DEPTH_BUFFER_Depth_bits 11 #define GFX8_3DSTATE_DEPTH_BUFFER_Depth_bits 11 #define GFX75_3DSTATE_DEPTH_BUFFER_Depth_bits 11 #define GFX7_3DSTATE_DEPTH_BUFFER_Depth_bits 11 #define GFX6_3DSTATE_DEPTH_BUFFER_Depth_bits 11 #define GFX5_3DSTATE_DEPTH_BUFFER_Depth_bits 11 #define GFX45_3DSTATE_DEPTH_BUFFER_Depth_bits 11 #define GFX4_3DSTATE_DEPTH_BUFFER_Depth_bits 11 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BUFFER_Depth_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 11; case 120: return 11; case 110: return 11; case 90: return 11; case 80: return 11; case 75: return 11; case 70: return 11; case 60: return 11; case 50: return 11; case 45: return 11; case 40: return 11; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DEPTH_BUFFER_Depth_start 180 #define GFX12_3DSTATE_DEPTH_BUFFER_Depth_start 180 #define GFX11_3DSTATE_DEPTH_BUFFER_Depth_start 181 #define GFX9_3DSTATE_DEPTH_BUFFER_Depth_start 181 #define GFX8_3DSTATE_DEPTH_BUFFER_Depth_start 181 #define GFX75_3DSTATE_DEPTH_BUFFER_Depth_start 149 #define GFX7_3DSTATE_DEPTH_BUFFER_Depth_start 149 #define GFX6_3DSTATE_DEPTH_BUFFER_Depth_start 149 #define GFX5_3DSTATE_DEPTH_BUFFER_Depth_start 149 #define GFX45_3DSTATE_DEPTH_BUFFER_Depth_start 149 #define GFX4_3DSTATE_DEPTH_BUFFER_Depth_start 149 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BUFFER_Depth_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 180; case 120: return 180; case 110: return 181; case 90: return 181; case 80: return 181; case 75: return 149; case 70: return 149; case 60: return 149; case 50: return 149; case 45: return 149; case 40: return 149; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DEPTH_BUFFER::Depth Buffer Compression Enable */ #define GFX125_3DSTATE_DEPTH_BUFFER_DepthBufferCompressionEnable_bits 1 #define GFX12_3DSTATE_DEPTH_BUFFER_DepthBufferCompressionEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BUFFER_DepthBufferCompressionEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DEPTH_BUFFER_DepthBufferCompressionEnable_start 53 #define GFX12_3DSTATE_DEPTH_BUFFER_DepthBufferCompressionEnable_start 53 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BUFFER_DepthBufferCompressionEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 53; case 120: return 53; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DEPTH_BUFFER::Depth Buffer Coordinate Offset Disable */ #define GFX45_3DSTATE_DEPTH_BUFFER_DepthBufferCoordinateOffsetDisable_bits 1 #define GFX4_3DSTATE_DEPTH_BUFFER_DepthBufferCoordinateOffsetDisable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BUFFER_DepthBufferCoordinateOffsetDisable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX45_3DSTATE_DEPTH_BUFFER_DepthBufferCoordinateOffsetDisable_start 57 #define GFX4_3DSTATE_DEPTH_BUFFER_DepthBufferCoordinateOffsetDisable_start 57 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BUFFER_DepthBufferCoordinateOffsetDisable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 57; case 40: return 57; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DEPTH_BUFFER::Depth Coordinate Offset X */ #define GFX75_3DSTATE_DEPTH_BUFFER_DepthCoordinateOffsetX_bits 16 #define GFX7_3DSTATE_DEPTH_BUFFER_DepthCoordinateOffsetX_bits 16 #define GFX6_3DSTATE_DEPTH_BUFFER_DepthCoordinateOffsetX_bits 16 #define GFX5_3DSTATE_DEPTH_BUFFER_DepthCoordinateOffsetX_bits 16 #define GFX45_3DSTATE_DEPTH_BUFFER_DepthCoordinateOffsetX_bits 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BUFFER_DepthCoordinateOffsetX_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 16; case 70: return 16; case 60: return 16; case 50: return 16; case 45: return 16; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_DEPTH_BUFFER_DepthCoordinateOffsetX_start 160 #define GFX7_3DSTATE_DEPTH_BUFFER_DepthCoordinateOffsetX_start 160 #define GFX6_3DSTATE_DEPTH_BUFFER_DepthCoordinateOffsetX_start 160 #define GFX5_3DSTATE_DEPTH_BUFFER_DepthCoordinateOffsetX_start 160 #define GFX45_3DSTATE_DEPTH_BUFFER_DepthCoordinateOffsetX_start 160 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BUFFER_DepthCoordinateOffsetX_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 160; case 70: return 160; case 60: return 160; case 50: return 160; case 45: return 160; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DEPTH_BUFFER::Depth Coordinate Offset Y */ #define GFX75_3DSTATE_DEPTH_BUFFER_DepthCoordinateOffsetY_bits 16 #define GFX7_3DSTATE_DEPTH_BUFFER_DepthCoordinateOffsetY_bits 16 #define GFX6_3DSTATE_DEPTH_BUFFER_DepthCoordinateOffsetY_bits 16 #define GFX5_3DSTATE_DEPTH_BUFFER_DepthCoordinateOffsetY_bits 16 #define GFX45_3DSTATE_DEPTH_BUFFER_DepthCoordinateOffsetY_bits 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BUFFER_DepthCoordinateOffsetY_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 16; case 70: return 16; case 60: return 16; case 50: return 16; case 45: return 16; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_DEPTH_BUFFER_DepthCoordinateOffsetY_start 176 #define GFX7_3DSTATE_DEPTH_BUFFER_DepthCoordinateOffsetY_start 176 #define GFX6_3DSTATE_DEPTH_BUFFER_DepthCoordinateOffsetY_start 176 #define GFX5_3DSTATE_DEPTH_BUFFER_DepthCoordinateOffsetY_start 176 #define GFX45_3DSTATE_DEPTH_BUFFER_DepthCoordinateOffsetY_start 176 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BUFFER_DepthCoordinateOffsetY_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 176; case 70: return 176; case 60: return 176; case 50: return 176; case 45: return 176; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DEPTH_BUFFER::Depth Write Enable */ #define GFX125_3DSTATE_DEPTH_BUFFER_DepthWriteEnable_bits 1 #define GFX12_3DSTATE_DEPTH_BUFFER_DepthWriteEnable_bits 1 #define GFX11_3DSTATE_DEPTH_BUFFER_DepthWriteEnable_bits 1 #define GFX9_3DSTATE_DEPTH_BUFFER_DepthWriteEnable_bits 1 #define GFX8_3DSTATE_DEPTH_BUFFER_DepthWriteEnable_bits 1 #define GFX75_3DSTATE_DEPTH_BUFFER_DepthWriteEnable_bits 1 #define GFX7_3DSTATE_DEPTH_BUFFER_DepthWriteEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BUFFER_DepthWriteEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DEPTH_BUFFER_DepthWriteEnable_start 60 #define GFX12_3DSTATE_DEPTH_BUFFER_DepthWriteEnable_start 60 #define GFX11_3DSTATE_DEPTH_BUFFER_DepthWriteEnable_start 60 #define GFX9_3DSTATE_DEPTH_BUFFER_DepthWriteEnable_start 60 #define GFX8_3DSTATE_DEPTH_BUFFER_DepthWriteEnable_start 60 #define GFX75_3DSTATE_DEPTH_BUFFER_DepthWriteEnable_start 60 #define GFX7_3DSTATE_DEPTH_BUFFER_DepthWriteEnable_start 60 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BUFFER_DepthWriteEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 60; case 120: return 60; case 110: return 60; case 90: return 60; case 80: return 60; case 75: return 60; case 70: return 60; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DEPTH_BUFFER::Height */ #define GFX125_3DSTATE_DEPTH_BUFFER_Height_bits 14 #define GFX12_3DSTATE_DEPTH_BUFFER_Height_bits 14 #define GFX11_3DSTATE_DEPTH_BUFFER_Height_bits 14 #define GFX9_3DSTATE_DEPTH_BUFFER_Height_bits 14 #define GFX8_3DSTATE_DEPTH_BUFFER_Height_bits 14 #define GFX75_3DSTATE_DEPTH_BUFFER_Height_bits 14 #define GFX7_3DSTATE_DEPTH_BUFFER_Height_bits 14 #define GFX6_3DSTATE_DEPTH_BUFFER_Height_bits 13 #define GFX5_3DSTATE_DEPTH_BUFFER_Height_bits 13 #define GFX45_3DSTATE_DEPTH_BUFFER_Height_bits 13 #define GFX4_3DSTATE_DEPTH_BUFFER_Height_bits 13 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BUFFER_Height_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 14; case 120: return 14; case 110: return 14; case 90: return 14; case 80: return 14; case 75: return 14; case 70: return 14; case 60: return 13; case 50: return 13; case 45: return 13; case 40: return 13; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DEPTH_BUFFER_Height_start 145 #define GFX12_3DSTATE_DEPTH_BUFFER_Height_start 145 #define GFX11_3DSTATE_DEPTH_BUFFER_Height_start 146 #define GFX9_3DSTATE_DEPTH_BUFFER_Height_start 146 #define GFX8_3DSTATE_DEPTH_BUFFER_Height_start 146 #define GFX75_3DSTATE_DEPTH_BUFFER_Height_start 114 #define GFX7_3DSTATE_DEPTH_BUFFER_Height_start 114 #define GFX6_3DSTATE_DEPTH_BUFFER_Height_start 115 #define GFX5_3DSTATE_DEPTH_BUFFER_Height_start 115 #define GFX45_3DSTATE_DEPTH_BUFFER_Height_start 115 #define GFX4_3DSTATE_DEPTH_BUFFER_Height_start 115 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BUFFER_Height_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 145; case 120: return 145; case 110: return 146; case 90: return 146; case 80: return 146; case 75: return 114; case 70: return 114; case 60: return 115; case 50: return 115; case 45: return 115; case 40: return 115; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DEPTH_BUFFER::Hierarchical Depth Buffer Enable */ #define GFX125_3DSTATE_DEPTH_BUFFER_HierarchicalDepthBufferEnable_bits 1 #define GFX12_3DSTATE_DEPTH_BUFFER_HierarchicalDepthBufferEnable_bits 1 #define GFX11_3DSTATE_DEPTH_BUFFER_HierarchicalDepthBufferEnable_bits 1 #define GFX9_3DSTATE_DEPTH_BUFFER_HierarchicalDepthBufferEnable_bits 1 #define GFX8_3DSTATE_DEPTH_BUFFER_HierarchicalDepthBufferEnable_bits 1 #define GFX75_3DSTATE_DEPTH_BUFFER_HierarchicalDepthBufferEnable_bits 1 #define GFX7_3DSTATE_DEPTH_BUFFER_HierarchicalDepthBufferEnable_bits 1 #define GFX6_3DSTATE_DEPTH_BUFFER_HierarchicalDepthBufferEnable_bits 1 #define GFX5_3DSTATE_DEPTH_BUFFER_HierarchicalDepthBufferEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BUFFER_HierarchicalDepthBufferEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 1; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DEPTH_BUFFER_HierarchicalDepthBufferEnable_start 54 #define GFX12_3DSTATE_DEPTH_BUFFER_HierarchicalDepthBufferEnable_start 54 #define GFX11_3DSTATE_DEPTH_BUFFER_HierarchicalDepthBufferEnable_start 54 #define GFX9_3DSTATE_DEPTH_BUFFER_HierarchicalDepthBufferEnable_start 54 #define GFX8_3DSTATE_DEPTH_BUFFER_HierarchicalDepthBufferEnable_start 54 #define GFX75_3DSTATE_DEPTH_BUFFER_HierarchicalDepthBufferEnable_start 54 #define GFX7_3DSTATE_DEPTH_BUFFER_HierarchicalDepthBufferEnable_start 54 #define GFX6_3DSTATE_DEPTH_BUFFER_HierarchicalDepthBufferEnable_start 54 #define GFX5_3DSTATE_DEPTH_BUFFER_HierarchicalDepthBufferEnable_start 54 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BUFFER_HierarchicalDepthBufferEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 54; case 120: return 54; case 110: return 54; case 90: return 54; case 80: return 54; case 75: return 54; case 70: return 54; case 60: return 54; case 50: return 54; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DEPTH_BUFFER::LOD */ #define GFX125_3DSTATE_DEPTH_BUFFER_LOD_bits 4 #define GFX12_3DSTATE_DEPTH_BUFFER_LOD_bits 4 #define GFX11_3DSTATE_DEPTH_BUFFER_LOD_bits 4 #define GFX9_3DSTATE_DEPTH_BUFFER_LOD_bits 4 #define GFX8_3DSTATE_DEPTH_BUFFER_LOD_bits 4 #define GFX75_3DSTATE_DEPTH_BUFFER_LOD_bits 4 #define GFX7_3DSTATE_DEPTH_BUFFER_LOD_bits 4 #define GFX6_3DSTATE_DEPTH_BUFFER_LOD_bits 4 #define GFX5_3DSTATE_DEPTH_BUFFER_LOD_bits 4 #define GFX45_3DSTATE_DEPTH_BUFFER_LOD_bits 4 #define GFX4_3DSTATE_DEPTH_BUFFER_LOD_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BUFFER_LOD_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 4; case 70: return 4; case 60: return 4; case 50: return 4; case 45: return 4; case 40: return 4; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DEPTH_BUFFER_LOD_start 240 #define GFX12_3DSTATE_DEPTH_BUFFER_LOD_start 240 #define GFX11_3DSTATE_DEPTH_BUFFER_LOD_start 128 #define GFX9_3DSTATE_DEPTH_BUFFER_LOD_start 128 #define GFX8_3DSTATE_DEPTH_BUFFER_LOD_start 128 #define GFX75_3DSTATE_DEPTH_BUFFER_LOD_start 96 #define GFX7_3DSTATE_DEPTH_BUFFER_LOD_start 96 #define GFX6_3DSTATE_DEPTH_BUFFER_LOD_start 98 #define GFX5_3DSTATE_DEPTH_BUFFER_LOD_start 98 #define GFX45_3DSTATE_DEPTH_BUFFER_LOD_start 98 #define GFX4_3DSTATE_DEPTH_BUFFER_LOD_start 98 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BUFFER_LOD_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 240; case 120: return 240; case 110: return 128; case 90: return 128; case 80: return 128; case 75: return 96; case 70: return 96; case 60: return 98; case 50: return 98; case 45: return 98; case 40: return 98; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DEPTH_BUFFER::MIP Map Layout Mode */ #define GFX6_3DSTATE_DEPTH_BUFFER_MIPMapLayoutMode_bits 1 #define GFX5_3DSTATE_DEPTH_BUFFER_MIPMapLayoutMode_bits 1 #define GFX45_3DSTATE_DEPTH_BUFFER_MIPMapLayoutMode_bits 1 #define GFX4_3DSTATE_DEPTH_BUFFER_MIPMapLayoutMode_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BUFFER_MIPMapLayoutMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_DEPTH_BUFFER_MIPMapLayoutMode_start 97 #define GFX5_3DSTATE_DEPTH_BUFFER_MIPMapLayoutMode_start 97 #define GFX45_3DSTATE_DEPTH_BUFFER_MIPMapLayoutMode_start 97 #define GFX4_3DSTATE_DEPTH_BUFFER_MIPMapLayoutMode_start 97 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BUFFER_MIPMapLayoutMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 97; case 50: return 97; case 45: return 97; case 40: return 97; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DEPTH_BUFFER::MOCS */ #define GFX125_3DSTATE_DEPTH_BUFFER_MOCS_bits 7 #define GFX12_3DSTATE_DEPTH_BUFFER_MOCS_bits 7 #define GFX11_3DSTATE_DEPTH_BUFFER_MOCS_bits 7 #define GFX9_3DSTATE_DEPTH_BUFFER_MOCS_bits 7 #define GFX8_3DSTATE_DEPTH_BUFFER_MOCS_bits 7 #define GFX75_3DSTATE_DEPTH_BUFFER_MOCS_bits 4 #define GFX7_3DSTATE_DEPTH_BUFFER_MOCS_bits 4 #define GFX6_3DSTATE_DEPTH_BUFFER_MOCS_bits 5 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BUFFER_MOCS_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 7; case 120: return 7; case 110: return 7; case 90: return 7; case 80: return 7; case 75: return 4; case 70: return 4; case 60: return 5; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DEPTH_BUFFER_MOCS_start 160 #define GFX12_3DSTATE_DEPTH_BUFFER_MOCS_start 160 #define GFX11_3DSTATE_DEPTH_BUFFER_MOCS_start 160 #define GFX9_3DSTATE_DEPTH_BUFFER_MOCS_start 160 #define GFX8_3DSTATE_DEPTH_BUFFER_MOCS_start 160 #define GFX75_3DSTATE_DEPTH_BUFFER_MOCS_start 128 #define GFX7_3DSTATE_DEPTH_BUFFER_MOCS_start 128 #define GFX6_3DSTATE_DEPTH_BUFFER_MOCS_start 219 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BUFFER_MOCS_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 160; case 120: return 160; case 110: return 160; case 90: return 160; case 80: return 160; case 75: return 128; case 70: return 128; case 60: return 219; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DEPTH_BUFFER::Minimum Array Element */ #define GFX125_3DSTATE_DEPTH_BUFFER_MinimumArrayElement_bits 11 #define GFX12_3DSTATE_DEPTH_BUFFER_MinimumArrayElement_bits 11 #define GFX11_3DSTATE_DEPTH_BUFFER_MinimumArrayElement_bits 11 #define GFX9_3DSTATE_DEPTH_BUFFER_MinimumArrayElement_bits 11 #define GFX8_3DSTATE_DEPTH_BUFFER_MinimumArrayElement_bits 11 #define GFX75_3DSTATE_DEPTH_BUFFER_MinimumArrayElement_bits 11 #define GFX7_3DSTATE_DEPTH_BUFFER_MinimumArrayElement_bits 11 #define GFX6_3DSTATE_DEPTH_BUFFER_MinimumArrayElement_bits 11 #define GFX5_3DSTATE_DEPTH_BUFFER_MinimumArrayElement_bits 11 #define GFX45_3DSTATE_DEPTH_BUFFER_MinimumArrayElement_bits 11 #define GFX4_3DSTATE_DEPTH_BUFFER_MinimumArrayElement_bits 11 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BUFFER_MinimumArrayElement_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 11; case 120: return 11; case 110: return 11; case 90: return 11; case 80: return 11; case 75: return 11; case 70: return 11; case 60: return 11; case 50: return 11; case 45: return 11; case 40: return 11; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DEPTH_BUFFER_MinimumArrayElement_start 168 #define GFX12_3DSTATE_DEPTH_BUFFER_MinimumArrayElement_start 168 #define GFX11_3DSTATE_DEPTH_BUFFER_MinimumArrayElement_start 170 #define GFX9_3DSTATE_DEPTH_BUFFER_MinimumArrayElement_start 170 #define GFX8_3DSTATE_DEPTH_BUFFER_MinimumArrayElement_start 170 #define GFX75_3DSTATE_DEPTH_BUFFER_MinimumArrayElement_start 138 #define GFX7_3DSTATE_DEPTH_BUFFER_MinimumArrayElement_start 138 #define GFX6_3DSTATE_DEPTH_BUFFER_MinimumArrayElement_start 138 #define GFX5_3DSTATE_DEPTH_BUFFER_MinimumArrayElement_start 138 #define GFX45_3DSTATE_DEPTH_BUFFER_MinimumArrayElement_start 138 #define GFX4_3DSTATE_DEPTH_BUFFER_MinimumArrayElement_start 138 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BUFFER_MinimumArrayElement_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 168; case 120: return 168; case 110: return 170; case 90: return 170; case 80: return 170; case 75: return 138; case 70: return 138; case 60: return 138; case 50: return 138; case 45: return 138; case 40: return 138; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DEPTH_BUFFER::Mip Tail Start LOD */ #define GFX125_3DSTATE_DEPTH_BUFFER_MipTailStartLOD_bits 4 #define GFX12_3DSTATE_DEPTH_BUFFER_MipTailStartLOD_bits 4 #define GFX11_3DSTATE_DEPTH_BUFFER_MipTailStartLOD_bits 4 #define GFX9_3DSTATE_DEPTH_BUFFER_MipTailStartLOD_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BUFFER_MipTailStartLOD_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DEPTH_BUFFER_MipTailStartLOD_start 218 #define GFX12_3DSTATE_DEPTH_BUFFER_MipTailStartLOD_start 218 #define GFX11_3DSTATE_DEPTH_BUFFER_MipTailStartLOD_start 218 #define GFX9_3DSTATE_DEPTH_BUFFER_MipTailStartLOD_start 218 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BUFFER_MipTailStartLOD_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 218; case 120: return 218; case 110: return 218; case 90: return 218; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DEPTH_BUFFER::Null Page Coherency Enable */ #define GFX125_3DSTATE_DEPTH_BUFFER_NullPageCoherencyEnable_bits 1 #define GFX12_3DSTATE_DEPTH_BUFFER_NullPageCoherencyEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BUFFER_NullPageCoherencyEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DEPTH_BUFFER_NullPageCoherencyEnable_start 59 #define GFX12_3DSTATE_DEPTH_BUFFER_NullPageCoherencyEnable_start 59 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BUFFER_NullPageCoherencyEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 59; case 120: return 59; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DEPTH_BUFFER::Render Compression Format */ #define GFX125_3DSTATE_DEPTH_BUFFER_RenderCompressionFormat_bits 5 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BUFFER_RenderCompressionFormat_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DEPTH_BUFFER_RenderCompressionFormat_start 192 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BUFFER_RenderCompressionFormat_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 192; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DEPTH_BUFFER::Render Target View Extent */ #define GFX125_3DSTATE_DEPTH_BUFFER_RenderTargetViewExtent_bits 11 #define GFX12_3DSTATE_DEPTH_BUFFER_RenderTargetViewExtent_bits 11 #define GFX11_3DSTATE_DEPTH_BUFFER_RenderTargetViewExtent_bits 11 #define GFX9_3DSTATE_DEPTH_BUFFER_RenderTargetViewExtent_bits 11 #define GFX8_3DSTATE_DEPTH_BUFFER_RenderTargetViewExtent_bits 11 #define GFX75_3DSTATE_DEPTH_BUFFER_RenderTargetViewExtent_bits 11 #define GFX7_3DSTATE_DEPTH_BUFFER_RenderTargetViewExtent_bits 11 #define GFX6_3DSTATE_DEPTH_BUFFER_RenderTargetViewExtent_bits 9 #define GFX5_3DSTATE_DEPTH_BUFFER_RenderTargetViewExtent_bits 9 #define GFX45_3DSTATE_DEPTH_BUFFER_RenderTargetViewExtent_bits 9 #define GFX4_3DSTATE_DEPTH_BUFFER_RenderTargetViewExtent_bits 9 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BUFFER_RenderTargetViewExtent_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 11; case 120: return 11; case 110: return 11; case 90: return 11; case 80: return 11; case 75: return 11; case 70: return 11; case 60: return 9; case 50: return 9; case 45: return 9; case 40: return 9; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DEPTH_BUFFER_RenderTargetViewExtent_start 245 #define GFX12_3DSTATE_DEPTH_BUFFER_RenderTargetViewExtent_start 245 #define GFX11_3DSTATE_DEPTH_BUFFER_RenderTargetViewExtent_start 245 #define GFX9_3DSTATE_DEPTH_BUFFER_RenderTargetViewExtent_start 245 #define GFX8_3DSTATE_DEPTH_BUFFER_RenderTargetViewExtent_start 245 #define GFX75_3DSTATE_DEPTH_BUFFER_RenderTargetViewExtent_start 213 #define GFX7_3DSTATE_DEPTH_BUFFER_RenderTargetViewExtent_start 213 #define GFX6_3DSTATE_DEPTH_BUFFER_RenderTargetViewExtent_start 129 #define GFX5_3DSTATE_DEPTH_BUFFER_RenderTargetViewExtent_start 129 #define GFX45_3DSTATE_DEPTH_BUFFER_RenderTargetViewExtent_start 129 #define GFX4_3DSTATE_DEPTH_BUFFER_RenderTargetViewExtent_start 129 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BUFFER_RenderTargetViewExtent_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 245; case 120: return 245; case 110: return 245; case 90: return 245; case 80: return 245; case 75: return 213; case 70: return 213; case 60: return 129; case 50: return 129; case 45: return 129; case 40: return 129; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DEPTH_BUFFER::Separate Stencil Buffer Enable */ #define GFX6_3DSTATE_DEPTH_BUFFER_SeparateStencilBufferEnable_bits 1 #define GFX5_3DSTATE_DEPTH_BUFFER_SeparateStencilBufferEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BUFFER_SeparateStencilBufferEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 1; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_DEPTH_BUFFER_SeparateStencilBufferEnable_start 53 #define GFX5_3DSTATE_DEPTH_BUFFER_SeparateStencilBufferEnable_start 53 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BUFFER_SeparateStencilBufferEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 53; case 50: return 53; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DEPTH_BUFFER::Software Tiled Rendering Mode */ #define GFX6_3DSTATE_DEPTH_BUFFER_SoftwareTiledRenderingMode_bits 2 #define GFX5_3DSTATE_DEPTH_BUFFER_SoftwareTiledRenderingMode_bits 2 #define GFX45_3DSTATE_DEPTH_BUFFER_SoftwareTiledRenderingMode_bits 2 #define GFX4_3DSTATE_DEPTH_BUFFER_SoftwareTiledRenderingMode_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BUFFER_SoftwareTiledRenderingMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 2; case 50: return 2; case 45: return 2; case 40: return 2; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_DEPTH_BUFFER_SoftwareTiledRenderingMode_start 55 #define GFX5_3DSTATE_DEPTH_BUFFER_SoftwareTiledRenderingMode_start 55 #define GFX45_3DSTATE_DEPTH_BUFFER_SoftwareTiledRenderingMode_start 55 #define GFX4_3DSTATE_DEPTH_BUFFER_SoftwareTiledRenderingMode_start 55 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BUFFER_SoftwareTiledRenderingMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 55; case 50: return 55; case 45: return 55; case 40: return 55; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DEPTH_BUFFER::Stencil Write Enable */ #define GFX11_3DSTATE_DEPTH_BUFFER_StencilWriteEnable_bits 1 #define GFX9_3DSTATE_DEPTH_BUFFER_StencilWriteEnable_bits 1 #define GFX8_3DSTATE_DEPTH_BUFFER_StencilWriteEnable_bits 1 #define GFX75_3DSTATE_DEPTH_BUFFER_StencilWriteEnable_bits 1 #define GFX7_3DSTATE_DEPTH_BUFFER_StencilWriteEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BUFFER_StencilWriteEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX11_3DSTATE_DEPTH_BUFFER_StencilWriteEnable_start 59 #define GFX9_3DSTATE_DEPTH_BUFFER_StencilWriteEnable_start 59 #define GFX8_3DSTATE_DEPTH_BUFFER_StencilWriteEnable_start 59 #define GFX75_3DSTATE_DEPTH_BUFFER_StencilWriteEnable_start 59 #define GFX7_3DSTATE_DEPTH_BUFFER_StencilWriteEnable_start 59 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BUFFER_StencilWriteEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 59; case 90: return 59; case 80: return 59; case 75: return 59; case 70: return 59; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DEPTH_BUFFER::Surface Base Address */ #define GFX125_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_bits 64 #define GFX12_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_bits 64 #define GFX11_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_bits 64 #define GFX9_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_bits 64 #define GFX8_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_bits 64 #define GFX75_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_bits 32 #define GFX7_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_bits 32 #define GFX6_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_bits 32 #define GFX5_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_bits 32 #define GFX45_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_bits 32 #define GFX4_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_bits 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 64; case 80: return 64; case 75: return 32; case 70: return 32; case 60: return 32; case 50: return 32; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_start 64 #define GFX12_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_start 64 #define GFX11_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_start 64 #define GFX9_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_start 64 #define GFX8_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_start 64 #define GFX75_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_start 64 #define GFX7_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_start 64 #define GFX6_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_start 64 #define GFX5_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_start 64 #define GFX45_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_start 64 #define GFX4_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_start 64 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 64; case 80: return 64; case 75: return 64; case 70: return 64; case 60: return 64; case 50: return 64; case 45: return 64; case 40: return 64; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DEPTH_BUFFER::Surface Format */ #define GFX125_3DSTATE_DEPTH_BUFFER_SurfaceFormat_bits 3 #define GFX12_3DSTATE_DEPTH_BUFFER_SurfaceFormat_bits 3 #define GFX11_3DSTATE_DEPTH_BUFFER_SurfaceFormat_bits 3 #define GFX9_3DSTATE_DEPTH_BUFFER_SurfaceFormat_bits 3 #define GFX8_3DSTATE_DEPTH_BUFFER_SurfaceFormat_bits 3 #define GFX75_3DSTATE_DEPTH_BUFFER_SurfaceFormat_bits 3 #define GFX7_3DSTATE_DEPTH_BUFFER_SurfaceFormat_bits 3 #define GFX6_3DSTATE_DEPTH_BUFFER_SurfaceFormat_bits 3 #define GFX5_3DSTATE_DEPTH_BUFFER_SurfaceFormat_bits 3 #define GFX45_3DSTATE_DEPTH_BUFFER_SurfaceFormat_bits 3 #define GFX4_3DSTATE_DEPTH_BUFFER_SurfaceFormat_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BUFFER_SurfaceFormat_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DEPTH_BUFFER_SurfaceFormat_start 56 #define GFX12_3DSTATE_DEPTH_BUFFER_SurfaceFormat_start 56 #define GFX11_3DSTATE_DEPTH_BUFFER_SurfaceFormat_start 50 #define GFX9_3DSTATE_DEPTH_BUFFER_SurfaceFormat_start 50 #define GFX8_3DSTATE_DEPTH_BUFFER_SurfaceFormat_start 50 #define GFX75_3DSTATE_DEPTH_BUFFER_SurfaceFormat_start 50 #define GFX7_3DSTATE_DEPTH_BUFFER_SurfaceFormat_start 50 #define GFX6_3DSTATE_DEPTH_BUFFER_SurfaceFormat_start 50 #define GFX5_3DSTATE_DEPTH_BUFFER_SurfaceFormat_start 50 #define GFX45_3DSTATE_DEPTH_BUFFER_SurfaceFormat_start 50 #define GFX4_3DSTATE_DEPTH_BUFFER_SurfaceFormat_start 50 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BUFFER_SurfaceFormat_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 56; case 120: return 56; case 110: return 50; case 90: return 50; case 80: return 50; case 75: return 50; case 70: return 50; case 60: return 50; case 50: return 50; case 45: return 50; case 40: return 50; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DEPTH_BUFFER::Surface Pitch */ #define GFX125_3DSTATE_DEPTH_BUFFER_SurfacePitch_bits 18 #define GFX12_3DSTATE_DEPTH_BUFFER_SurfacePitch_bits 18 #define GFX11_3DSTATE_DEPTH_BUFFER_SurfacePitch_bits 18 #define GFX9_3DSTATE_DEPTH_BUFFER_SurfacePitch_bits 18 #define GFX8_3DSTATE_DEPTH_BUFFER_SurfacePitch_bits 18 #define GFX75_3DSTATE_DEPTH_BUFFER_SurfacePitch_bits 18 #define GFX7_3DSTATE_DEPTH_BUFFER_SurfacePitch_bits 18 #define GFX6_3DSTATE_DEPTH_BUFFER_SurfacePitch_bits 17 #define GFX5_3DSTATE_DEPTH_BUFFER_SurfacePitch_bits 17 #define GFX45_3DSTATE_DEPTH_BUFFER_SurfacePitch_bits 17 #define GFX4_3DSTATE_DEPTH_BUFFER_SurfacePitch_bits 17 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BUFFER_SurfacePitch_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 18; case 120: return 18; case 110: return 18; case 90: return 18; case 80: return 18; case 75: return 18; case 70: return 18; case 60: return 17; case 50: return 17; case 45: return 17; case 40: return 17; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DEPTH_BUFFER_SurfacePitch_start 32 #define GFX12_3DSTATE_DEPTH_BUFFER_SurfacePitch_start 32 #define GFX11_3DSTATE_DEPTH_BUFFER_SurfacePitch_start 32 #define GFX9_3DSTATE_DEPTH_BUFFER_SurfacePitch_start 32 #define GFX8_3DSTATE_DEPTH_BUFFER_SurfacePitch_start 32 #define GFX75_3DSTATE_DEPTH_BUFFER_SurfacePitch_start 32 #define GFX7_3DSTATE_DEPTH_BUFFER_SurfacePitch_start 32 #define GFX6_3DSTATE_DEPTH_BUFFER_SurfacePitch_start 32 #define GFX5_3DSTATE_DEPTH_BUFFER_SurfacePitch_start 32 #define GFX45_3DSTATE_DEPTH_BUFFER_SurfacePitch_start 32 #define GFX4_3DSTATE_DEPTH_BUFFER_SurfacePitch_start 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BUFFER_SurfacePitch_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 32; case 50: return 32; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DEPTH_BUFFER::Surface QPitch */ #define GFX125_3DSTATE_DEPTH_BUFFER_SurfaceQPitch_bits 15 #define GFX12_3DSTATE_DEPTH_BUFFER_SurfaceQPitch_bits 15 #define GFX11_3DSTATE_DEPTH_BUFFER_SurfaceQPitch_bits 15 #define GFX9_3DSTATE_DEPTH_BUFFER_SurfaceQPitch_bits 15 #define GFX8_3DSTATE_DEPTH_BUFFER_SurfaceQPitch_bits 15 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BUFFER_SurfaceQPitch_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 15; case 120: return 15; case 110: return 15; case 90: return 15; case 80: return 15; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DEPTH_BUFFER_SurfaceQPitch_start 224 #define GFX12_3DSTATE_DEPTH_BUFFER_SurfaceQPitch_start 224 #define GFX11_3DSTATE_DEPTH_BUFFER_SurfaceQPitch_start 224 #define GFX9_3DSTATE_DEPTH_BUFFER_SurfaceQPitch_start 224 #define GFX8_3DSTATE_DEPTH_BUFFER_SurfaceQPitch_start 224 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BUFFER_SurfaceQPitch_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 224; case 120: return 224; case 110: return 224; case 90: return 224; case 80: return 224; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DEPTH_BUFFER::Surface Type */ #define GFX125_3DSTATE_DEPTH_BUFFER_SurfaceType_bits 3 #define GFX12_3DSTATE_DEPTH_BUFFER_SurfaceType_bits 3 #define GFX11_3DSTATE_DEPTH_BUFFER_SurfaceType_bits 3 #define GFX9_3DSTATE_DEPTH_BUFFER_SurfaceType_bits 3 #define GFX8_3DSTATE_DEPTH_BUFFER_SurfaceType_bits 3 #define GFX75_3DSTATE_DEPTH_BUFFER_SurfaceType_bits 3 #define GFX7_3DSTATE_DEPTH_BUFFER_SurfaceType_bits 3 #define GFX6_3DSTATE_DEPTH_BUFFER_SurfaceType_bits 3 #define GFX5_3DSTATE_DEPTH_BUFFER_SurfaceType_bits 3 #define GFX45_3DSTATE_DEPTH_BUFFER_SurfaceType_bits 3 #define GFX4_3DSTATE_DEPTH_BUFFER_SurfaceType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BUFFER_SurfaceType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DEPTH_BUFFER_SurfaceType_start 61 #define GFX12_3DSTATE_DEPTH_BUFFER_SurfaceType_start 61 #define GFX11_3DSTATE_DEPTH_BUFFER_SurfaceType_start 61 #define GFX9_3DSTATE_DEPTH_BUFFER_SurfaceType_start 61 #define GFX8_3DSTATE_DEPTH_BUFFER_SurfaceType_start 61 #define GFX75_3DSTATE_DEPTH_BUFFER_SurfaceType_start 61 #define GFX7_3DSTATE_DEPTH_BUFFER_SurfaceType_start 61 #define GFX6_3DSTATE_DEPTH_BUFFER_SurfaceType_start 61 #define GFX5_3DSTATE_DEPTH_BUFFER_SurfaceType_start 61 #define GFX45_3DSTATE_DEPTH_BUFFER_SurfaceType_start 61 #define GFX4_3DSTATE_DEPTH_BUFFER_SurfaceType_start 61 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BUFFER_SurfaceType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 61; case 120: return 61; case 110: return 61; case 90: return 61; case 80: return 61; case 75: return 61; case 70: return 61; case 60: return 61; case 50: return 61; case 45: return 61; case 40: return 61; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DEPTH_BUFFER::Tile Walk */ #define GFX6_3DSTATE_DEPTH_BUFFER_TileWalk_bits 1 #define GFX5_3DSTATE_DEPTH_BUFFER_TileWalk_bits 1 #define GFX45_3DSTATE_DEPTH_BUFFER_TileWalk_bits 1 #define GFX4_3DSTATE_DEPTH_BUFFER_TileWalk_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BUFFER_TileWalk_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_DEPTH_BUFFER_TileWalk_start 58 #define GFX5_3DSTATE_DEPTH_BUFFER_TileWalk_start 58 #define GFX45_3DSTATE_DEPTH_BUFFER_TileWalk_start 58 #define GFX4_3DSTATE_DEPTH_BUFFER_TileWalk_start 58 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BUFFER_TileWalk_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 58; case 50: return 58; case 45: return 58; case 40: return 58; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DEPTH_BUFFER::Tiled Mode */ #define GFX125_3DSTATE_DEPTH_BUFFER_TiledMode_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BUFFER_TiledMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DEPTH_BUFFER_TiledMode_start 222 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BUFFER_TiledMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 222; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DEPTH_BUFFER::Tiled Resource Mode */ #define GFX12_3DSTATE_DEPTH_BUFFER_TiledResourceMode_bits 2 #define GFX11_3DSTATE_DEPTH_BUFFER_TiledResourceMode_bits 2 #define GFX9_3DSTATE_DEPTH_BUFFER_TiledResourceMode_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BUFFER_TiledResourceMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_3DSTATE_DEPTH_BUFFER_TiledResourceMode_start 222 #define GFX11_3DSTATE_DEPTH_BUFFER_TiledResourceMode_start 222 #define GFX9_3DSTATE_DEPTH_BUFFER_TiledResourceMode_start 222 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BUFFER_TiledResourceMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 222; case 110: return 222; case 90: return 222; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DEPTH_BUFFER::Tiled Surface */ #define GFX6_3DSTATE_DEPTH_BUFFER_TiledSurface_bits 1 #define GFX5_3DSTATE_DEPTH_BUFFER_TiledSurface_bits 1 #define GFX45_3DSTATE_DEPTH_BUFFER_TiledSurface_bits 1 #define GFX4_3DSTATE_DEPTH_BUFFER_TiledSurface_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BUFFER_TiledSurface_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_DEPTH_BUFFER_TiledSurface_start 59 #define GFX5_3DSTATE_DEPTH_BUFFER_TiledSurface_start 59 #define GFX45_3DSTATE_DEPTH_BUFFER_TiledSurface_start 59 #define GFX4_3DSTATE_DEPTH_BUFFER_TiledSurface_start 59 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BUFFER_TiledSurface_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 59; case 50: return 59; case 45: return 59; case 40: return 59; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DEPTH_BUFFER::Width */ #define GFX125_3DSTATE_DEPTH_BUFFER_Width_bits 14 #define GFX12_3DSTATE_DEPTH_BUFFER_Width_bits 14 #define GFX11_3DSTATE_DEPTH_BUFFER_Width_bits 14 #define GFX9_3DSTATE_DEPTH_BUFFER_Width_bits 14 #define GFX8_3DSTATE_DEPTH_BUFFER_Width_bits 14 #define GFX75_3DSTATE_DEPTH_BUFFER_Width_bits 14 #define GFX7_3DSTATE_DEPTH_BUFFER_Width_bits 14 #define GFX6_3DSTATE_DEPTH_BUFFER_Width_bits 13 #define GFX5_3DSTATE_DEPTH_BUFFER_Width_bits 13 #define GFX45_3DSTATE_DEPTH_BUFFER_Width_bits 13 #define GFX4_3DSTATE_DEPTH_BUFFER_Width_bits 13 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BUFFER_Width_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 14; case 120: return 14; case 110: return 14; case 90: return 14; case 80: return 14; case 75: return 14; case 70: return 14; case 60: return 13; case 50: return 13; case 45: return 13; case 40: return 13; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DEPTH_BUFFER_Width_start 129 #define GFX12_3DSTATE_DEPTH_BUFFER_Width_start 129 #define GFX11_3DSTATE_DEPTH_BUFFER_Width_start 132 #define GFX9_3DSTATE_DEPTH_BUFFER_Width_start 132 #define GFX8_3DSTATE_DEPTH_BUFFER_Width_start 132 #define GFX75_3DSTATE_DEPTH_BUFFER_Width_start 100 #define GFX7_3DSTATE_DEPTH_BUFFER_Width_start 100 #define GFX6_3DSTATE_DEPTH_BUFFER_Width_start 102 #define GFX5_3DSTATE_DEPTH_BUFFER_Width_start 102 #define GFX45_3DSTATE_DEPTH_BUFFER_Width_start 102 #define GFX4_3DSTATE_DEPTH_BUFFER_Width_start 102 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_BUFFER_Width_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 129; case 120: return 129; case 110: return 132; case 90: return 132; case 80: return 132; case 75: return 100; case 70: return 100; case 60: return 102; case 50: return 102; case 45: return 102; case 40: return 102; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DEPTH_STENCIL_STATE_POINTERS */ #define GFX75_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_length 2 #define GFX7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_length 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_STENCIL_STATE_POINTERS_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DEPTH_STENCIL_STATE_POINTERS::3D Command Opcode */ #define GFX75_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_3DCommandOpcode_bits 3 #define GFX7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_STENCIL_STATE_POINTERS_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_3DCommandOpcode_start 24 #define GFX7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_STENCIL_STATE_POINTERS_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 24; case 70: return 24; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DEPTH_STENCIL_STATE_POINTERS::3D Command Sub Opcode */ #define GFX75_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_3DCommandSubOpcode_bits 8 #define GFX7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_STENCIL_STATE_POINTERS_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_3DCommandSubOpcode_start 16 #define GFX7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_STENCIL_STATE_POINTERS_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 16; case 70: return 16; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DEPTH_STENCIL_STATE_POINTERS::Command SubType */ #define GFX75_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_CommandSubType_bits 2 #define GFX7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_STENCIL_STATE_POINTERS_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_CommandSubType_start 27 #define GFX7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_STENCIL_STATE_POINTERS_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 27; case 70: return 27; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DEPTH_STENCIL_STATE_POINTERS::Command Type */ #define GFX75_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_CommandType_bits 3 #define GFX7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_STENCIL_STATE_POINTERS_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_CommandType_start 29 #define GFX7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_STENCIL_STATE_POINTERS_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 29; case 70: return 29; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DEPTH_STENCIL_STATE_POINTERS::DWord Length */ #define GFX75_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_DWordLength_bits 8 #define GFX7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_STENCIL_STATE_POINTERS_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_DWordLength_start 0 #define GFX7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_STENCIL_STATE_POINTERS_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DEPTH_STENCIL_STATE_POINTERS::Pointer to DEPTH_STENCIL_STATE */ #define GFX75_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_PointertoDEPTH_STENCIL_STATE_bits 26 #define GFX7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_PointertoDEPTH_STENCIL_STATE_bits 26 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_STENCIL_STATE_POINTERS_PointertoDEPTH_STENCIL_STATE_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 26; case 70: return 26; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_PointertoDEPTH_STENCIL_STATE_start 38 #define GFX7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_PointertoDEPTH_STENCIL_STATE_start 38 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DEPTH_STENCIL_STATE_POINTERS_PointertoDEPTH_STENCIL_STATE_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 38; case 70: return 38; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DRAWING_RECTANGLE */ #define GFX125_3DSTATE_DRAWING_RECTANGLE_length 4 #define GFX12_3DSTATE_DRAWING_RECTANGLE_length 4 #define GFX11_3DSTATE_DRAWING_RECTANGLE_length 4 #define GFX9_3DSTATE_DRAWING_RECTANGLE_length 4 #define GFX8_3DSTATE_DRAWING_RECTANGLE_length 4 #define GFX75_3DSTATE_DRAWING_RECTANGLE_length 4 #define GFX7_3DSTATE_DRAWING_RECTANGLE_length 4 #define GFX6_3DSTATE_DRAWING_RECTANGLE_length 4 #define GFX5_3DSTATE_DRAWING_RECTANGLE_length 4 #define GFX45_3DSTATE_DRAWING_RECTANGLE_length 4 #define GFX4_3DSTATE_DRAWING_RECTANGLE_length 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DRAWING_RECTANGLE_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 4; case 70: return 4; case 60: return 4; case 50: return 4; case 45: return 4; case 40: return 4; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DRAWING_RECTANGLE::3D Command Opcode */ #define GFX125_3DSTATE_DRAWING_RECTANGLE_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_DRAWING_RECTANGLE_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_DRAWING_RECTANGLE_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_DRAWING_RECTANGLE_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_DRAWING_RECTANGLE_3DCommandOpcode_bits 3 #define GFX75_3DSTATE_DRAWING_RECTANGLE_3DCommandOpcode_bits 3 #define GFX7_3DSTATE_DRAWING_RECTANGLE_3DCommandOpcode_bits 3 #define GFX6_3DSTATE_DRAWING_RECTANGLE_3DCommandOpcode_bits 3 #define GFX5_3DSTATE_DRAWING_RECTANGLE_3DCommandOpcode_bits 3 #define GFX45_3DSTATE_DRAWING_RECTANGLE_3DCommandOpcode_bits 3 #define GFX4_3DSTATE_DRAWING_RECTANGLE_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DRAWING_RECTANGLE_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DRAWING_RECTANGLE_3DCommandOpcode_start 24 #define GFX12_3DSTATE_DRAWING_RECTANGLE_3DCommandOpcode_start 24 #define GFX11_3DSTATE_DRAWING_RECTANGLE_3DCommandOpcode_start 24 #define GFX9_3DSTATE_DRAWING_RECTANGLE_3DCommandOpcode_start 24 #define GFX8_3DSTATE_DRAWING_RECTANGLE_3DCommandOpcode_start 24 #define GFX75_3DSTATE_DRAWING_RECTANGLE_3DCommandOpcode_start 24 #define GFX7_3DSTATE_DRAWING_RECTANGLE_3DCommandOpcode_start 24 #define GFX6_3DSTATE_DRAWING_RECTANGLE_3DCommandOpcode_start 24 #define GFX5_3DSTATE_DRAWING_RECTANGLE_3DCommandOpcode_start 24 #define GFX45_3DSTATE_DRAWING_RECTANGLE_3DCommandOpcode_start 24 #define GFX4_3DSTATE_DRAWING_RECTANGLE_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DRAWING_RECTANGLE_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 24; case 50: return 24; case 45: return 24; case 40: return 24; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DRAWING_RECTANGLE::3D Command Sub Opcode */ #define GFX125_3DSTATE_DRAWING_RECTANGLE_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_DRAWING_RECTANGLE_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_DRAWING_RECTANGLE_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_DRAWING_RECTANGLE_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_DRAWING_RECTANGLE_3DCommandSubOpcode_bits 8 #define GFX75_3DSTATE_DRAWING_RECTANGLE_3DCommandSubOpcode_bits 8 #define GFX7_3DSTATE_DRAWING_RECTANGLE_3DCommandSubOpcode_bits 8 #define GFX6_3DSTATE_DRAWING_RECTANGLE_3DCommandSubOpcode_bits 8 #define GFX5_3DSTATE_DRAWING_RECTANGLE_3DCommandSubOpcode_bits 8 #define GFX45_3DSTATE_DRAWING_RECTANGLE_3DCommandSubOpcode_bits 8 #define GFX4_3DSTATE_DRAWING_RECTANGLE_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DRAWING_RECTANGLE_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 8; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DRAWING_RECTANGLE_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_DRAWING_RECTANGLE_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_DRAWING_RECTANGLE_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_DRAWING_RECTANGLE_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_DRAWING_RECTANGLE_3DCommandSubOpcode_start 16 #define GFX75_3DSTATE_DRAWING_RECTANGLE_3DCommandSubOpcode_start 16 #define GFX7_3DSTATE_DRAWING_RECTANGLE_3DCommandSubOpcode_start 16 #define GFX6_3DSTATE_DRAWING_RECTANGLE_3DCommandSubOpcode_start 16 #define GFX5_3DSTATE_DRAWING_RECTANGLE_3DCommandSubOpcode_start 16 #define GFX45_3DSTATE_DRAWING_RECTANGLE_3DCommandSubOpcode_start 16 #define GFX4_3DSTATE_DRAWING_RECTANGLE_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DRAWING_RECTANGLE_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 16; case 50: return 16; case 45: return 16; case 40: return 16; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DRAWING_RECTANGLE::Clipped Drawing Rectangle X Max */ #define GFX125_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMax_bits 16 #define GFX12_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMax_bits 16 #define GFX11_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMax_bits 16 #define GFX9_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMax_bits 16 #define GFX8_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMax_bits 16 #define GFX75_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMax_bits 16 #define GFX7_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMax_bits 16 #define GFX6_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMax_bits 16 #define GFX5_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMax_bits 16 #define GFX45_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMax_bits 16 #define GFX4_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMax_bits 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMax_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 16; case 50: return 16; case 45: return 16; case 40: return 16; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMax_start 64 #define GFX12_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMax_start 64 #define GFX11_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMax_start 64 #define GFX9_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMax_start 64 #define GFX8_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMax_start 64 #define GFX75_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMax_start 64 #define GFX7_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMax_start 64 #define GFX6_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMax_start 64 #define GFX5_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMax_start 64 #define GFX45_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMax_start 64 #define GFX4_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMax_start 64 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMax_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 64; case 80: return 64; case 75: return 64; case 70: return 64; case 60: return 64; case 50: return 64; case 45: return 64; case 40: return 64; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DRAWING_RECTANGLE::Clipped Drawing Rectangle X Min */ #define GFX125_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMin_bits 16 #define GFX12_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMin_bits 16 #define GFX11_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMin_bits 16 #define GFX9_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMin_bits 16 #define GFX8_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMin_bits 16 #define GFX75_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMin_bits 16 #define GFX7_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMin_bits 16 #define GFX6_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMin_bits 16 #define GFX5_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMin_bits 16 #define GFX45_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMin_bits 16 #define GFX4_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMin_bits 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMin_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 16; case 50: return 16; case 45: return 16; case 40: return 16; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMin_start 32 #define GFX12_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMin_start 32 #define GFX11_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMin_start 32 #define GFX9_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMin_start 32 #define GFX8_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMin_start 32 #define GFX75_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMin_start 32 #define GFX7_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMin_start 32 #define GFX6_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMin_start 32 #define GFX5_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMin_start 32 #define GFX45_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMin_start 32 #define GFX4_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMin_start 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMin_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 32; case 50: return 32; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DRAWING_RECTANGLE::Clipped Drawing Rectangle Y Max */ #define GFX125_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMax_bits 16 #define GFX12_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMax_bits 16 #define GFX11_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMax_bits 16 #define GFX9_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMax_bits 16 #define GFX8_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMax_bits 16 #define GFX75_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMax_bits 16 #define GFX7_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMax_bits 16 #define GFX6_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMax_bits 16 #define GFX5_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMax_bits 16 #define GFX45_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMax_bits 16 #define GFX4_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMax_bits 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMax_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 16; case 50: return 16; case 45: return 16; case 40: return 16; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMax_start 80 #define GFX12_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMax_start 80 #define GFX11_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMax_start 80 #define GFX9_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMax_start 80 #define GFX8_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMax_start 80 #define GFX75_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMax_start 80 #define GFX7_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMax_start 80 #define GFX6_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMax_start 80 #define GFX5_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMax_start 80 #define GFX45_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMax_start 80 #define GFX4_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMax_start 80 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMax_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 80; case 120: return 80; case 110: return 80; case 90: return 80; case 80: return 80; case 75: return 80; case 70: return 80; case 60: return 80; case 50: return 80; case 45: return 80; case 40: return 80; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DRAWING_RECTANGLE::Clipped Drawing Rectangle Y Min */ #define GFX125_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMin_bits 16 #define GFX12_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMin_bits 16 #define GFX11_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMin_bits 16 #define GFX9_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMin_bits 16 #define GFX8_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMin_bits 16 #define GFX75_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMin_bits 16 #define GFX7_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMin_bits 16 #define GFX6_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMin_bits 16 #define GFX5_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMin_bits 16 #define GFX45_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMin_bits 16 #define GFX4_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMin_bits 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMin_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 16; case 50: return 16; case 45: return 16; case 40: return 16; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMin_start 48 #define GFX12_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMin_start 48 #define GFX11_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMin_start 48 #define GFX9_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMin_start 48 #define GFX8_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMin_start 48 #define GFX75_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMin_start 48 #define GFX7_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMin_start 48 #define GFX6_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMin_start 48 #define GFX5_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMin_start 48 #define GFX45_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMin_start 48 #define GFX4_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMin_start 48 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMin_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 48; case 120: return 48; case 110: return 48; case 90: return 48; case 80: return 48; case 75: return 48; case 70: return 48; case 60: return 48; case 50: return 48; case 45: return 48; case 40: return 48; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DRAWING_RECTANGLE::Command SubType */ #define GFX125_3DSTATE_DRAWING_RECTANGLE_CommandSubType_bits 2 #define GFX12_3DSTATE_DRAWING_RECTANGLE_CommandSubType_bits 2 #define GFX11_3DSTATE_DRAWING_RECTANGLE_CommandSubType_bits 2 #define GFX9_3DSTATE_DRAWING_RECTANGLE_CommandSubType_bits 2 #define GFX8_3DSTATE_DRAWING_RECTANGLE_CommandSubType_bits 2 #define GFX75_3DSTATE_DRAWING_RECTANGLE_CommandSubType_bits 2 #define GFX7_3DSTATE_DRAWING_RECTANGLE_CommandSubType_bits 2 #define GFX6_3DSTATE_DRAWING_RECTANGLE_CommandSubType_bits 2 #define GFX5_3DSTATE_DRAWING_RECTANGLE_CommandSubType_bits 2 #define GFX45_3DSTATE_DRAWING_RECTANGLE_CommandSubType_bits 2 #define GFX4_3DSTATE_DRAWING_RECTANGLE_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DRAWING_RECTANGLE_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 2; case 45: return 2; case 40: return 2; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DRAWING_RECTANGLE_CommandSubType_start 27 #define GFX12_3DSTATE_DRAWING_RECTANGLE_CommandSubType_start 27 #define GFX11_3DSTATE_DRAWING_RECTANGLE_CommandSubType_start 27 #define GFX9_3DSTATE_DRAWING_RECTANGLE_CommandSubType_start 27 #define GFX8_3DSTATE_DRAWING_RECTANGLE_CommandSubType_start 27 #define GFX75_3DSTATE_DRAWING_RECTANGLE_CommandSubType_start 27 #define GFX7_3DSTATE_DRAWING_RECTANGLE_CommandSubType_start 27 #define GFX6_3DSTATE_DRAWING_RECTANGLE_CommandSubType_start 27 #define GFX5_3DSTATE_DRAWING_RECTANGLE_CommandSubType_start 27 #define GFX45_3DSTATE_DRAWING_RECTANGLE_CommandSubType_start 27 #define GFX4_3DSTATE_DRAWING_RECTANGLE_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DRAWING_RECTANGLE_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 27; case 50: return 27; case 45: return 27; case 40: return 27; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DRAWING_RECTANGLE::Command Type */ #define GFX125_3DSTATE_DRAWING_RECTANGLE_CommandType_bits 3 #define GFX12_3DSTATE_DRAWING_RECTANGLE_CommandType_bits 3 #define GFX11_3DSTATE_DRAWING_RECTANGLE_CommandType_bits 3 #define GFX9_3DSTATE_DRAWING_RECTANGLE_CommandType_bits 3 #define GFX8_3DSTATE_DRAWING_RECTANGLE_CommandType_bits 3 #define GFX75_3DSTATE_DRAWING_RECTANGLE_CommandType_bits 3 #define GFX7_3DSTATE_DRAWING_RECTANGLE_CommandType_bits 3 #define GFX6_3DSTATE_DRAWING_RECTANGLE_CommandType_bits 3 #define GFX5_3DSTATE_DRAWING_RECTANGLE_CommandType_bits 3 #define GFX45_3DSTATE_DRAWING_RECTANGLE_CommandType_bits 3 #define GFX4_3DSTATE_DRAWING_RECTANGLE_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DRAWING_RECTANGLE_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DRAWING_RECTANGLE_CommandType_start 29 #define GFX12_3DSTATE_DRAWING_RECTANGLE_CommandType_start 29 #define GFX11_3DSTATE_DRAWING_RECTANGLE_CommandType_start 29 #define GFX9_3DSTATE_DRAWING_RECTANGLE_CommandType_start 29 #define GFX8_3DSTATE_DRAWING_RECTANGLE_CommandType_start 29 #define GFX75_3DSTATE_DRAWING_RECTANGLE_CommandType_start 29 #define GFX7_3DSTATE_DRAWING_RECTANGLE_CommandType_start 29 #define GFX6_3DSTATE_DRAWING_RECTANGLE_CommandType_start 29 #define GFX5_3DSTATE_DRAWING_RECTANGLE_CommandType_start 29 #define GFX45_3DSTATE_DRAWING_RECTANGLE_CommandType_start 29 #define GFX4_3DSTATE_DRAWING_RECTANGLE_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DRAWING_RECTANGLE_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 29; case 50: return 29; case 45: return 29; case 40: return 29; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DRAWING_RECTANGLE::Core Mode Select */ #define GFX125_3DSTATE_DRAWING_RECTANGLE_CoreModeSelect_bits 2 #define GFX12_3DSTATE_DRAWING_RECTANGLE_CoreModeSelect_bits 2 #define GFX11_3DSTATE_DRAWING_RECTANGLE_CoreModeSelect_bits 2 #define GFX9_3DSTATE_DRAWING_RECTANGLE_CoreModeSelect_bits 2 #define GFX8_3DSTATE_DRAWING_RECTANGLE_CoreModeSelect_bits 2 #define GFX75_3DSTATE_DRAWING_RECTANGLE_CoreModeSelect_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DRAWING_RECTANGLE_CoreModeSelect_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DRAWING_RECTANGLE_CoreModeSelect_start 14 #define GFX12_3DSTATE_DRAWING_RECTANGLE_CoreModeSelect_start 14 #define GFX11_3DSTATE_DRAWING_RECTANGLE_CoreModeSelect_start 14 #define GFX9_3DSTATE_DRAWING_RECTANGLE_CoreModeSelect_start 14 #define GFX8_3DSTATE_DRAWING_RECTANGLE_CoreModeSelect_start 14 #define GFX75_3DSTATE_DRAWING_RECTANGLE_CoreModeSelect_start 14 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DRAWING_RECTANGLE_CoreModeSelect_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 14; case 120: return 14; case 110: return 14; case 90: return 14; case 80: return 14; case 75: return 14; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DRAWING_RECTANGLE::DWord Length */ #define GFX125_3DSTATE_DRAWING_RECTANGLE_DWordLength_bits 8 #define GFX12_3DSTATE_DRAWING_RECTANGLE_DWordLength_bits 8 #define GFX11_3DSTATE_DRAWING_RECTANGLE_DWordLength_bits 8 #define GFX9_3DSTATE_DRAWING_RECTANGLE_DWordLength_bits 8 #define GFX8_3DSTATE_DRAWING_RECTANGLE_DWordLength_bits 8 #define GFX75_3DSTATE_DRAWING_RECTANGLE_DWordLength_bits 8 #define GFX7_3DSTATE_DRAWING_RECTANGLE_DWordLength_bits 8 #define GFX6_3DSTATE_DRAWING_RECTANGLE_DWordLength_bits 8 #define GFX5_3DSTATE_DRAWING_RECTANGLE_DWordLength_bits 8 #define GFX45_3DSTATE_DRAWING_RECTANGLE_DWordLength_bits 8 #define GFX4_3DSTATE_DRAWING_RECTANGLE_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DRAWING_RECTANGLE_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 8; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DRAWING_RECTANGLE_DWordLength_start 0 #define GFX12_3DSTATE_DRAWING_RECTANGLE_DWordLength_start 0 #define GFX11_3DSTATE_DRAWING_RECTANGLE_DWordLength_start 0 #define GFX9_3DSTATE_DRAWING_RECTANGLE_DWordLength_start 0 #define GFX8_3DSTATE_DRAWING_RECTANGLE_DWordLength_start 0 #define GFX75_3DSTATE_DRAWING_RECTANGLE_DWordLength_start 0 #define GFX7_3DSTATE_DRAWING_RECTANGLE_DWordLength_start 0 #define GFX6_3DSTATE_DRAWING_RECTANGLE_DWordLength_start 0 #define GFX5_3DSTATE_DRAWING_RECTANGLE_DWordLength_start 0 #define GFX45_3DSTATE_DRAWING_RECTANGLE_DWordLength_start 0 #define GFX4_3DSTATE_DRAWING_RECTANGLE_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DRAWING_RECTANGLE_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DRAWING_RECTANGLE::Drawing Rectangle Origin X */ #define GFX125_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginX_bits 16 #define GFX12_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginX_bits 16 #define GFX11_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginX_bits 16 #define GFX9_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginX_bits 16 #define GFX8_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginX_bits 16 #define GFX75_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginX_bits 16 #define GFX7_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginX_bits 16 #define GFX6_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginX_bits 16 #define GFX5_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginX_bits 16 #define GFX45_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginX_bits 16 #define GFX4_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginX_bits 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginX_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 16; case 50: return 16; case 45: return 16; case 40: return 16; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginX_start 96 #define GFX12_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginX_start 96 #define GFX11_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginX_start 96 #define GFX9_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginX_start 96 #define GFX8_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginX_start 96 #define GFX75_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginX_start 96 #define GFX7_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginX_start 96 #define GFX6_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginX_start 96 #define GFX5_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginX_start 96 #define GFX45_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginX_start 96 #define GFX4_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginX_start 96 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginX_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 96; case 120: return 96; case 110: return 96; case 90: return 96; case 80: return 96; case 75: return 96; case 70: return 96; case 60: return 96; case 50: return 96; case 45: return 96; case 40: return 96; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DRAWING_RECTANGLE::Drawing Rectangle Origin Y */ #define GFX125_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginY_bits 16 #define GFX12_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginY_bits 16 #define GFX11_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginY_bits 16 #define GFX9_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginY_bits 16 #define GFX8_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginY_bits 16 #define GFX75_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginY_bits 16 #define GFX7_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginY_bits 16 #define GFX6_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginY_bits 16 #define GFX5_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginY_bits 16 #define GFX45_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginY_bits 16 #define GFX4_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginY_bits 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginY_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 16; case 50: return 16; case 45: return 16; case 40: return 16; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginY_start 112 #define GFX12_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginY_start 112 #define GFX11_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginY_start 112 #define GFX9_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginY_start 112 #define GFX8_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginY_start 112 #define GFX75_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginY_start 112 #define GFX7_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginY_start 112 #define GFX6_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginY_start 112 #define GFX5_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginY_start 112 #define GFX45_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginY_start 112 #define GFX4_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginY_start 112 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginY_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 112; case 120: return 112; case 110: return 112; case 90: return 112; case 80: return 112; case 75: return 112; case 70: return 112; case 60: return 112; case 50: return 112; case 45: return 112; case 40: return 112; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DS */ #define GFX125_3DSTATE_DS_length 11 #define GFX12_3DSTATE_DS_length 11 #define GFX11_3DSTATE_DS_length 11 #define GFX9_3DSTATE_DS_length 11 #define GFX8_3DSTATE_DS_length 9 #define GFX75_3DSTATE_DS_length 6 #define GFX7_3DSTATE_DS_length 6 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DS_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 11; case 120: return 11; case 110: return 11; case 90: return 11; case 80: return 9; case 75: return 6; case 70: return 6; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DS::3D Command Opcode */ #define GFX125_3DSTATE_DS_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_DS_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_DS_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_DS_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_DS_3DCommandOpcode_bits 3 #define GFX75_3DSTATE_DS_3DCommandOpcode_bits 3 #define GFX7_3DSTATE_DS_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DS_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DS_3DCommandOpcode_start 24 #define GFX12_3DSTATE_DS_3DCommandOpcode_start 24 #define GFX11_3DSTATE_DS_3DCommandOpcode_start 24 #define GFX9_3DSTATE_DS_3DCommandOpcode_start 24 #define GFX8_3DSTATE_DS_3DCommandOpcode_start 24 #define GFX75_3DSTATE_DS_3DCommandOpcode_start 24 #define GFX7_3DSTATE_DS_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DS_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DS::3D Command Sub Opcode */ #define GFX125_3DSTATE_DS_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_DS_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_DS_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_DS_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_DS_3DCommandSubOpcode_bits 8 #define GFX75_3DSTATE_DS_3DCommandSubOpcode_bits 8 #define GFX7_3DSTATE_DS_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DS_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DS_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_DS_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_DS_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_DS_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_DS_3DCommandSubOpcode_start 16 #define GFX75_3DSTATE_DS_3DCommandSubOpcode_start 16 #define GFX7_3DSTATE_DS_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DS_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DS::Accesses UAV */ #define GFX125_3DSTATE_DS_AccessesUAV_bits 1 #define GFX12_3DSTATE_DS_AccessesUAV_bits 1 #define GFX11_3DSTATE_DS_AccessesUAV_bits 1 #define GFX9_3DSTATE_DS_AccessesUAV_bits 1 #define GFX8_3DSTATE_DS_AccessesUAV_bits 1 #define GFX75_3DSTATE_DS_AccessesUAV_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DS_AccessesUAV_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DS_AccessesUAV_start 110 #define GFX12_3DSTATE_DS_AccessesUAV_start 110 #define GFX11_3DSTATE_DS_AccessesUAV_start 110 #define GFX9_3DSTATE_DS_AccessesUAV_start 110 #define GFX8_3DSTATE_DS_AccessesUAV_start 110 #define GFX75_3DSTATE_DS_AccessesUAV_start 78 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DS_AccessesUAV_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 110; case 120: return 110; case 110: return 110; case 90: return 110; case 80: return 110; case 75: return 78; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DS::Binding Table Entry Count */ #define GFX125_3DSTATE_DS_BindingTableEntryCount_bits 8 #define GFX12_3DSTATE_DS_BindingTableEntryCount_bits 8 #define GFX11_3DSTATE_DS_BindingTableEntryCount_bits 8 #define GFX9_3DSTATE_DS_BindingTableEntryCount_bits 8 #define GFX8_3DSTATE_DS_BindingTableEntryCount_bits 8 #define GFX75_3DSTATE_DS_BindingTableEntryCount_bits 8 #define GFX7_3DSTATE_DS_BindingTableEntryCount_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DS_BindingTableEntryCount_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DS_BindingTableEntryCount_start 114 #define GFX12_3DSTATE_DS_BindingTableEntryCount_start 114 #define GFX11_3DSTATE_DS_BindingTableEntryCount_start 114 #define GFX9_3DSTATE_DS_BindingTableEntryCount_start 114 #define GFX8_3DSTATE_DS_BindingTableEntryCount_start 114 #define GFX75_3DSTATE_DS_BindingTableEntryCount_start 82 #define GFX7_3DSTATE_DS_BindingTableEntryCount_start 82 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DS_BindingTableEntryCount_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 114; case 120: return 114; case 110: return 114; case 90: return 114; case 80: return 114; case 75: return 82; case 70: return 82; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DS::Cache Disable */ #define GFX125_3DSTATE_DS_CacheDisable_bits 1 #define GFX12_3DSTATE_DS_CacheDisable_bits 1 #define GFX11_3DSTATE_DS_CacheDisable_bits 1 #define GFX9_3DSTATE_DS_CacheDisable_bits 1 #define GFX8_3DSTATE_DS_CacheDisable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DS_CacheDisable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DS_CacheDisable_start 225 #define GFX12_3DSTATE_DS_CacheDisable_start 225 #define GFX11_3DSTATE_DS_CacheDisable_start 225 #define GFX9_3DSTATE_DS_CacheDisable_start 225 #define GFX8_3DSTATE_DS_CacheDisable_start 225 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DS_CacheDisable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 225; case 120: return 225; case 110: return 225; case 90: return 225; case 80: return 225; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DS::Command SubType */ #define GFX125_3DSTATE_DS_CommandSubType_bits 2 #define GFX12_3DSTATE_DS_CommandSubType_bits 2 #define GFX11_3DSTATE_DS_CommandSubType_bits 2 #define GFX9_3DSTATE_DS_CommandSubType_bits 2 #define GFX8_3DSTATE_DS_CommandSubType_bits 2 #define GFX75_3DSTATE_DS_CommandSubType_bits 2 #define GFX7_3DSTATE_DS_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DS_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DS_CommandSubType_start 27 #define GFX12_3DSTATE_DS_CommandSubType_start 27 #define GFX11_3DSTATE_DS_CommandSubType_start 27 #define GFX9_3DSTATE_DS_CommandSubType_start 27 #define GFX8_3DSTATE_DS_CommandSubType_start 27 #define GFX75_3DSTATE_DS_CommandSubType_start 27 #define GFX7_3DSTATE_DS_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DS_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DS::Command Type */ #define GFX125_3DSTATE_DS_CommandType_bits 3 #define GFX12_3DSTATE_DS_CommandType_bits 3 #define GFX11_3DSTATE_DS_CommandType_bits 3 #define GFX9_3DSTATE_DS_CommandType_bits 3 #define GFX8_3DSTATE_DS_CommandType_bits 3 #define GFX75_3DSTATE_DS_CommandType_bits 3 #define GFX7_3DSTATE_DS_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DS_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DS_CommandType_start 29 #define GFX12_3DSTATE_DS_CommandType_start 29 #define GFX11_3DSTATE_DS_CommandType_start 29 #define GFX9_3DSTATE_DS_CommandType_start 29 #define GFX8_3DSTATE_DS_CommandType_start 29 #define GFX75_3DSTATE_DS_CommandType_start 29 #define GFX7_3DSTATE_DS_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DS_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DS::Compute W Coordinate Enable */ #define GFX125_3DSTATE_DS_ComputeWCoordinateEnable_bits 1 #define GFX12_3DSTATE_DS_ComputeWCoordinateEnable_bits 1 #define GFX11_3DSTATE_DS_ComputeWCoordinateEnable_bits 1 #define GFX9_3DSTATE_DS_ComputeWCoordinateEnable_bits 1 #define GFX8_3DSTATE_DS_ComputeWCoordinateEnable_bits 1 #define GFX75_3DSTATE_DS_ComputeWCoordinateEnable_bits 1 #define GFX7_3DSTATE_DS_ComputeWCoordinateEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DS_ComputeWCoordinateEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DS_ComputeWCoordinateEnable_start 226 #define GFX12_3DSTATE_DS_ComputeWCoordinateEnable_start 226 #define GFX11_3DSTATE_DS_ComputeWCoordinateEnable_start 226 #define GFX9_3DSTATE_DS_ComputeWCoordinateEnable_start 226 #define GFX8_3DSTATE_DS_ComputeWCoordinateEnable_start 226 #define GFX75_3DSTATE_DS_ComputeWCoordinateEnable_start 162 #define GFX7_3DSTATE_DS_ComputeWCoordinateEnable_start 162 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DS_ComputeWCoordinateEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 226; case 120: return 226; case 110: return 226; case 90: return 226; case 80: return 226; case 75: return 162; case 70: return 162; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DS::DS Cache Disable */ #define GFX75_3DSTATE_DS_DSCacheDisable_bits 1 #define GFX7_3DSTATE_DS_DSCacheDisable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DS_DSCacheDisable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_DS_DSCacheDisable_start 161 #define GFX7_3DSTATE_DS_DSCacheDisable_start 161 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DS_DSCacheDisable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 161; case 70: return 161; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DS::DUAL_PATCH Kernel Start Pointer */ #define GFX125_3DSTATE_DS_DUAL_PATCHKernelStartPointer_bits 58 #define GFX12_3DSTATE_DS_DUAL_PATCHKernelStartPointer_bits 58 #define GFX11_3DSTATE_DS_DUAL_PATCHKernelStartPointer_bits 58 #define GFX9_3DSTATE_DS_DUAL_PATCHKernelStartPointer_bits 58 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DS_DUAL_PATCHKernelStartPointer_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 58; case 120: return 58; case 110: return 58; case 90: return 58; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DS_DUAL_PATCHKernelStartPointer_start 294 #define GFX12_3DSTATE_DS_DUAL_PATCHKernelStartPointer_start 294 #define GFX11_3DSTATE_DS_DUAL_PATCHKernelStartPointer_start 294 #define GFX9_3DSTATE_DS_DUAL_PATCHKernelStartPointer_start 294 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DS_DUAL_PATCHKernelStartPointer_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 294; case 120: return 294; case 110: return 294; case 90: return 294; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DS::DWord Length */ #define GFX125_3DSTATE_DS_DWordLength_bits 8 #define GFX12_3DSTATE_DS_DWordLength_bits 8 #define GFX11_3DSTATE_DS_DWordLength_bits 8 #define GFX9_3DSTATE_DS_DWordLength_bits 8 #define GFX8_3DSTATE_DS_DWordLength_bits 8 #define GFX75_3DSTATE_DS_DWordLength_bits 8 #define GFX7_3DSTATE_DS_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DS_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DS_DWordLength_start 0 #define GFX12_3DSTATE_DS_DWordLength_start 0 #define GFX11_3DSTATE_DS_DWordLength_start 0 #define GFX9_3DSTATE_DS_DWordLength_start 0 #define GFX8_3DSTATE_DS_DWordLength_start 0 #define GFX75_3DSTATE_DS_DWordLength_start 0 #define GFX7_3DSTATE_DS_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DS_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DS::Dispatch GRF Start Register For URB Data */ #define GFX125_3DSTATE_DS_DispatchGRFStartRegisterForURBData_bits 5 #define GFX12_3DSTATE_DS_DispatchGRFStartRegisterForURBData_bits 5 #define GFX11_3DSTATE_DS_DispatchGRFStartRegisterForURBData_bits 5 #define GFX9_3DSTATE_DS_DispatchGRFStartRegisterForURBData_bits 5 #define GFX8_3DSTATE_DS_DispatchGRFStartRegisterForURBData_bits 5 #define GFX75_3DSTATE_DS_DispatchGRFStartRegisterForURBData_bits 5 #define GFX7_3DSTATE_DS_DispatchGRFStartRegisterForURBData_bits 5 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DS_DispatchGRFStartRegisterForURBData_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 5; case 110: return 5; case 90: return 5; case 80: return 5; case 75: return 5; case 70: return 5; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DS_DispatchGRFStartRegisterForURBData_start 212 #define GFX12_3DSTATE_DS_DispatchGRFStartRegisterForURBData_start 212 #define GFX11_3DSTATE_DS_DispatchGRFStartRegisterForURBData_start 212 #define GFX9_3DSTATE_DS_DispatchGRFStartRegisterForURBData_start 212 #define GFX8_3DSTATE_DS_DispatchGRFStartRegisterForURBData_start 212 #define GFX75_3DSTATE_DS_DispatchGRFStartRegisterForURBData_start 148 #define GFX7_3DSTATE_DS_DispatchGRFStartRegisterForURBData_start 148 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DS_DispatchGRFStartRegisterForURBData_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 212; case 120: return 212; case 110: return 212; case 90: return 212; case 80: return 212; case 75: return 148; case 70: return 148; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DS::Dispatch Mode */ #define GFX125_3DSTATE_DS_DispatchMode_bits 2 #define GFX12_3DSTATE_DS_DispatchMode_bits 2 #define GFX11_3DSTATE_DS_DispatchMode_bits 2 #define GFX9_3DSTATE_DS_DispatchMode_bits 2 #define GFX8_3DSTATE_DS_DispatchMode_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DS_DispatchMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DS_DispatchMode_start 227 #define GFX12_3DSTATE_DS_DispatchMode_start 227 #define GFX11_3DSTATE_DS_DispatchMode_start 227 #define GFX9_3DSTATE_DS_DispatchMode_start 227 #define GFX8_3DSTATE_DS_DispatchMode_start 227 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DS_DispatchMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 227; case 120: return 227; case 110: return 227; case 90: return 227; case 80: return 227; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DS::Enable */ #define GFX125_3DSTATE_DS_Enable_bits 1 #define GFX12_3DSTATE_DS_Enable_bits 1 #define GFX11_3DSTATE_DS_Enable_bits 1 #define GFX9_3DSTATE_DS_Enable_bits 1 #define GFX8_3DSTATE_DS_Enable_bits 1 #define GFX75_3DSTATE_DS_Enable_bits 1 #define GFX7_3DSTATE_DS_Enable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DS_Enable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DS_Enable_start 224 #define GFX12_3DSTATE_DS_Enable_start 224 #define GFX11_3DSTATE_DS_Enable_start 224 #define GFX9_3DSTATE_DS_Enable_start 224 #define GFX8_3DSTATE_DS_Enable_start 224 #define GFX75_3DSTATE_DS_Enable_start 160 #define GFX7_3DSTATE_DS_Enable_start 160 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DS_Enable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 224; case 120: return 224; case 110: return 224; case 90: return 224; case 80: return 224; case 75: return 160; case 70: return 160; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DS::Floating Point Mode */ #define GFX125_3DSTATE_DS_FloatingPointMode_bits 1 #define GFX12_3DSTATE_DS_FloatingPointMode_bits 1 #define GFX11_3DSTATE_DS_FloatingPointMode_bits 1 #define GFX9_3DSTATE_DS_FloatingPointMode_bits 1 #define GFX8_3DSTATE_DS_FloatingPointMode_bits 1 #define GFX75_3DSTATE_DS_FloatingPointMode_bits 1 #define GFX7_3DSTATE_DS_FloatingPointMode_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DS_FloatingPointMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DS_FloatingPointMode_start 112 #define GFX12_3DSTATE_DS_FloatingPointMode_start 112 #define GFX11_3DSTATE_DS_FloatingPointMode_start 112 #define GFX9_3DSTATE_DS_FloatingPointMode_start 112 #define GFX8_3DSTATE_DS_FloatingPointMode_start 112 #define GFX75_3DSTATE_DS_FloatingPointMode_start 80 #define GFX7_3DSTATE_DS_FloatingPointMode_start 80 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DS_FloatingPointMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 112; case 120: return 112; case 110: return 112; case 90: return 112; case 80: return 112; case 75: return 80; case 70: return 80; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DS::Illegal Opcode Exception Enable */ #define GFX125_3DSTATE_DS_IllegalOpcodeExceptionEnable_bits 1 #define GFX12_3DSTATE_DS_IllegalOpcodeExceptionEnable_bits 1 #define GFX11_3DSTATE_DS_IllegalOpcodeExceptionEnable_bits 1 #define GFX9_3DSTATE_DS_IllegalOpcodeExceptionEnable_bits 1 #define GFX8_3DSTATE_DS_IllegalOpcodeExceptionEnable_bits 1 #define GFX75_3DSTATE_DS_IllegalOpcodeExceptionEnable_bits 1 #define GFX7_3DSTATE_DS_IllegalOpcodeExceptionEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DS_IllegalOpcodeExceptionEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DS_IllegalOpcodeExceptionEnable_start 109 #define GFX12_3DSTATE_DS_IllegalOpcodeExceptionEnable_start 109 #define GFX11_3DSTATE_DS_IllegalOpcodeExceptionEnable_start 109 #define GFX9_3DSTATE_DS_IllegalOpcodeExceptionEnable_start 109 #define GFX8_3DSTATE_DS_IllegalOpcodeExceptionEnable_start 109 #define GFX75_3DSTATE_DS_IllegalOpcodeExceptionEnable_start 77 #define GFX7_3DSTATE_DS_IllegalOpcodeExceptionEnable_start 77 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DS_IllegalOpcodeExceptionEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 109; case 120: return 109; case 110: return 109; case 90: return 109; case 80: return 109; case 75: return 77; case 70: return 77; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DS::Kernel Start Pointer */ #define GFX125_3DSTATE_DS_KernelStartPointer_bits 58 #define GFX12_3DSTATE_DS_KernelStartPointer_bits 58 #define GFX11_3DSTATE_DS_KernelStartPointer_bits 58 #define GFX9_3DSTATE_DS_KernelStartPointer_bits 58 #define GFX8_3DSTATE_DS_KernelStartPointer_bits 58 #define GFX75_3DSTATE_DS_KernelStartPointer_bits 26 #define GFX7_3DSTATE_DS_KernelStartPointer_bits 26 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DS_KernelStartPointer_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 58; case 120: return 58; case 110: return 58; case 90: return 58; case 80: return 58; case 75: return 26; case 70: return 26; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DS_KernelStartPointer_start 38 #define GFX12_3DSTATE_DS_KernelStartPointer_start 38 #define GFX11_3DSTATE_DS_KernelStartPointer_start 38 #define GFX9_3DSTATE_DS_KernelStartPointer_start 38 #define GFX8_3DSTATE_DS_KernelStartPointer_start 38 #define GFX75_3DSTATE_DS_KernelStartPointer_start 38 #define GFX7_3DSTATE_DS_KernelStartPointer_start 38 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DS_KernelStartPointer_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 38; case 120: return 38; case 110: return 38; case 90: return 38; case 80: return 38; case 75: return 38; case 70: return 38; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DS::Maximum Number of Threads */ #define GFX125_3DSTATE_DS_MaximumNumberofThreads_bits 10 #define GFX12_3DSTATE_DS_MaximumNumberofThreads_bits 10 #define GFX11_3DSTATE_DS_MaximumNumberofThreads_bits 10 #define GFX9_3DSTATE_DS_MaximumNumberofThreads_bits 9 #define GFX8_3DSTATE_DS_MaximumNumberofThreads_bits 9 #define GFX75_3DSTATE_DS_MaximumNumberofThreads_bits 9 #define GFX7_3DSTATE_DS_MaximumNumberofThreads_bits 7 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DS_MaximumNumberofThreads_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 10; case 120: return 10; case 110: return 10; case 90: return 9; case 80: return 9; case 75: return 9; case 70: return 7; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DS_MaximumNumberofThreads_start 245 #define GFX12_3DSTATE_DS_MaximumNumberofThreads_start 245 #define GFX11_3DSTATE_DS_MaximumNumberofThreads_start 245 #define GFX9_3DSTATE_DS_MaximumNumberofThreads_start 245 #define GFX8_3DSTATE_DS_MaximumNumberofThreads_start 245 #define GFX75_3DSTATE_DS_MaximumNumberofThreads_start 181 #define GFX7_3DSTATE_DS_MaximumNumberofThreads_start 185 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DS_MaximumNumberofThreads_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 245; case 120: return 245; case 110: return 245; case 90: return 245; case 80: return 245; case 75: return 181; case 70: return 185; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DS::Patch URB Entry Read Length */ #define GFX125_3DSTATE_DS_PatchURBEntryReadLength_bits 7 #define GFX12_3DSTATE_DS_PatchURBEntryReadLength_bits 7 #define GFX11_3DSTATE_DS_PatchURBEntryReadLength_bits 7 #define GFX9_3DSTATE_DS_PatchURBEntryReadLength_bits 7 #define GFX8_3DSTATE_DS_PatchURBEntryReadLength_bits 7 #define GFX75_3DSTATE_DS_PatchURBEntryReadLength_bits 7 #define GFX7_3DSTATE_DS_PatchURBEntryReadLength_bits 7 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DS_PatchURBEntryReadLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 7; case 120: return 7; case 110: return 7; case 90: return 7; case 80: return 7; case 75: return 7; case 70: return 7; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DS_PatchURBEntryReadLength_start 203 #define GFX12_3DSTATE_DS_PatchURBEntryReadLength_start 203 #define GFX11_3DSTATE_DS_PatchURBEntryReadLength_start 203 #define GFX9_3DSTATE_DS_PatchURBEntryReadLength_start 203 #define GFX8_3DSTATE_DS_PatchURBEntryReadLength_start 203 #define GFX75_3DSTATE_DS_PatchURBEntryReadLength_start 139 #define GFX7_3DSTATE_DS_PatchURBEntryReadLength_start 139 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DS_PatchURBEntryReadLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 203; case 120: return 203; case 110: return 203; case 90: return 203; case 80: return 203; case 75: return 139; case 70: return 139; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DS::Patch URB Entry Read Offset */ #define GFX125_3DSTATE_DS_PatchURBEntryReadOffset_bits 6 #define GFX12_3DSTATE_DS_PatchURBEntryReadOffset_bits 6 #define GFX11_3DSTATE_DS_PatchURBEntryReadOffset_bits 6 #define GFX9_3DSTATE_DS_PatchURBEntryReadOffset_bits 6 #define GFX8_3DSTATE_DS_PatchURBEntryReadOffset_bits 6 #define GFX75_3DSTATE_DS_PatchURBEntryReadOffset_bits 6 #define GFX7_3DSTATE_DS_PatchURBEntryReadOffset_bits 6 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DS_PatchURBEntryReadOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 6; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DS_PatchURBEntryReadOffset_start 196 #define GFX12_3DSTATE_DS_PatchURBEntryReadOffset_start 196 #define GFX11_3DSTATE_DS_PatchURBEntryReadOffset_start 196 #define GFX9_3DSTATE_DS_PatchURBEntryReadOffset_start 196 #define GFX8_3DSTATE_DS_PatchURBEntryReadOffset_start 196 #define GFX75_3DSTATE_DS_PatchURBEntryReadOffset_start 132 #define GFX7_3DSTATE_DS_PatchURBEntryReadOffset_start 132 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DS_PatchURBEntryReadOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 196; case 120: return 196; case 110: return 196; case 90: return 196; case 80: return 196; case 75: return 132; case 70: return 132; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DS::Per-Thread Scratch Space */ #define GFX12_3DSTATE_DS_PerThreadScratchSpace_bits 4 #define GFX11_3DSTATE_DS_PerThreadScratchSpace_bits 4 #define GFX9_3DSTATE_DS_PerThreadScratchSpace_bits 4 #define GFX8_3DSTATE_DS_PerThreadScratchSpace_bits 4 #define GFX75_3DSTATE_DS_PerThreadScratchSpace_bits 4 #define GFX7_3DSTATE_DS_PerThreadScratchSpace_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DS_PerThreadScratchSpace_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 4; case 70: return 4; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_3DSTATE_DS_PerThreadScratchSpace_start 128 #define GFX11_3DSTATE_DS_PerThreadScratchSpace_start 128 #define GFX9_3DSTATE_DS_PerThreadScratchSpace_start 128 #define GFX8_3DSTATE_DS_PerThreadScratchSpace_start 128 #define GFX75_3DSTATE_DS_PerThreadScratchSpace_start 96 #define GFX7_3DSTATE_DS_PerThreadScratchSpace_start 96 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DS_PerThreadScratchSpace_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 128; case 110: return 128; case 90: return 128; case 80: return 128; case 75: return 96; case 70: return 96; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DS::Sampler Count */ #define GFX125_3DSTATE_DS_SamplerCount_bits 3 #define GFX12_3DSTATE_DS_SamplerCount_bits 3 #define GFX11_3DSTATE_DS_SamplerCount_bits 3 #define GFX9_3DSTATE_DS_SamplerCount_bits 3 #define GFX8_3DSTATE_DS_SamplerCount_bits 3 #define GFX75_3DSTATE_DS_SamplerCount_bits 3 #define GFX7_3DSTATE_DS_SamplerCount_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DS_SamplerCount_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DS_SamplerCount_start 123 #define GFX12_3DSTATE_DS_SamplerCount_start 123 #define GFX11_3DSTATE_DS_SamplerCount_start 123 #define GFX9_3DSTATE_DS_SamplerCount_start 123 #define GFX8_3DSTATE_DS_SamplerCount_start 123 #define GFX75_3DSTATE_DS_SamplerCount_start 91 #define GFX7_3DSTATE_DS_SamplerCount_start 91 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DS_SamplerCount_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 123; case 120: return 123; case 110: return 123; case 90: return 123; case 80: return 123; case 75: return 91; case 70: return 91; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DS::Scratch Space Base Pointer */ #define GFX12_3DSTATE_DS_ScratchSpaceBasePointer_bits 54 #define GFX11_3DSTATE_DS_ScratchSpaceBasePointer_bits 54 #define GFX9_3DSTATE_DS_ScratchSpaceBasePointer_bits 54 #define GFX8_3DSTATE_DS_ScratchSpaceBasePointer_bits 54 #define GFX75_3DSTATE_DS_ScratchSpaceBasePointer_bits 22 #define GFX7_3DSTATE_DS_ScratchSpaceBasePointer_bits 22 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DS_ScratchSpaceBasePointer_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 54; case 110: return 54; case 90: return 54; case 80: return 54; case 75: return 22; case 70: return 22; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_3DSTATE_DS_ScratchSpaceBasePointer_start 138 #define GFX11_3DSTATE_DS_ScratchSpaceBasePointer_start 138 #define GFX9_3DSTATE_DS_ScratchSpaceBasePointer_start 138 #define GFX8_3DSTATE_DS_ScratchSpaceBasePointer_start 138 #define GFX75_3DSTATE_DS_ScratchSpaceBasePointer_start 106 #define GFX7_3DSTATE_DS_ScratchSpaceBasePointer_start 106 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DS_ScratchSpaceBasePointer_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 138; case 110: return 138; case 90: return 138; case 80: return 138; case 75: return 106; case 70: return 106; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DS::Scratch Space Buffer */ #define GFX125_3DSTATE_DS_ScratchSpaceBuffer_bits 22 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DS_ScratchSpaceBuffer_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 22; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DS_ScratchSpaceBuffer_start 138 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DS_ScratchSpaceBuffer_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 138; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DS::Single Domain Point Dispatch */ #define GFX8_3DSTATE_DS_SingleDomainPointDispatch_bits 1 #define GFX75_3DSTATE_DS_SingleDomainPointDispatch_bits 1 #define GFX7_3DSTATE_DS_SingleDomainPointDispatch_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DS_SingleDomainPointDispatch_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX8_3DSTATE_DS_SingleDomainPointDispatch_start 127 #define GFX75_3DSTATE_DS_SingleDomainPointDispatch_start 95 #define GFX7_3DSTATE_DS_SingleDomainPointDispatch_start 95 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DS_SingleDomainPointDispatch_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 127; case 75: return 95; case 70: return 95; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DS::Software Exception Enable */ #define GFX125_3DSTATE_DS_SoftwareExceptionEnable_bits 1 #define GFX12_3DSTATE_DS_SoftwareExceptionEnable_bits 1 #define GFX11_3DSTATE_DS_SoftwareExceptionEnable_bits 1 #define GFX9_3DSTATE_DS_SoftwareExceptionEnable_bits 1 #define GFX8_3DSTATE_DS_SoftwareExceptionEnable_bits 1 #define GFX75_3DSTATE_DS_SoftwareExceptionEnable_bits 1 #define GFX7_3DSTATE_DS_SoftwareExceptionEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DS_SoftwareExceptionEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DS_SoftwareExceptionEnable_start 103 #define GFX12_3DSTATE_DS_SoftwareExceptionEnable_start 103 #define GFX11_3DSTATE_DS_SoftwareExceptionEnable_start 103 #define GFX9_3DSTATE_DS_SoftwareExceptionEnable_start 103 #define GFX8_3DSTATE_DS_SoftwareExceptionEnable_start 103 #define GFX75_3DSTATE_DS_SoftwareExceptionEnable_start 71 #define GFX7_3DSTATE_DS_SoftwareExceptionEnable_start 71 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DS_SoftwareExceptionEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 103; case 120: return 103; case 110: return 103; case 90: return 103; case 80: return 103; case 75: return 71; case 70: return 71; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DS::Statistics Enable */ #define GFX125_3DSTATE_DS_StatisticsEnable_bits 1 #define GFX12_3DSTATE_DS_StatisticsEnable_bits 1 #define GFX11_3DSTATE_DS_StatisticsEnable_bits 1 #define GFX9_3DSTATE_DS_StatisticsEnable_bits 1 #define GFX8_3DSTATE_DS_StatisticsEnable_bits 1 #define GFX75_3DSTATE_DS_StatisticsEnable_bits 1 #define GFX7_3DSTATE_DS_StatisticsEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DS_StatisticsEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DS_StatisticsEnable_start 234 #define GFX12_3DSTATE_DS_StatisticsEnable_start 234 #define GFX11_3DSTATE_DS_StatisticsEnable_start 234 #define GFX9_3DSTATE_DS_StatisticsEnable_start 234 #define GFX8_3DSTATE_DS_StatisticsEnable_start 234 #define GFX75_3DSTATE_DS_StatisticsEnable_start 170 #define GFX7_3DSTATE_DS_StatisticsEnable_start 170 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DS_StatisticsEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 234; case 120: return 234; case 110: return 234; case 90: return 234; case 80: return 234; case 75: return 170; case 70: return 170; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DS::Thread Dispatch Priority */ #define GFX125_3DSTATE_DS_ThreadDispatchPriority_bits 1 #define GFX12_3DSTATE_DS_ThreadDispatchPriority_bits 1 #define GFX11_3DSTATE_DS_ThreadDispatchPriority_bits 1 #define GFX9_3DSTATE_DS_ThreadDispatchPriority_bits 1 #define GFX8_3DSTATE_DS_ThreadDispatchPriority_bits 1 #define GFX75_3DSTATE_DS_ThreadDispatchPriority_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DS_ThreadDispatchPriority_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DS_ThreadDispatchPriority_start 113 #define GFX12_3DSTATE_DS_ThreadDispatchPriority_start 113 #define GFX11_3DSTATE_DS_ThreadDispatchPriority_start 113 #define GFX9_3DSTATE_DS_ThreadDispatchPriority_start 113 #define GFX8_3DSTATE_DS_ThreadDispatchPriority_start 113 #define GFX75_3DSTATE_DS_ThreadDispatchPriority_start 81 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DS_ThreadDispatchPriority_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 113; case 120: return 113; case 110: return 113; case 90: return 113; case 80: return 113; case 75: return 81; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DS::User Clip Distance Clip Test Enable Bitmask */ #define GFX125_3DSTATE_DS_UserClipDistanceClipTestEnableBitmask_bits 8 #define GFX12_3DSTATE_DS_UserClipDistanceClipTestEnableBitmask_bits 8 #define GFX11_3DSTATE_DS_UserClipDistanceClipTestEnableBitmask_bits 8 #define GFX9_3DSTATE_DS_UserClipDistanceClipTestEnableBitmask_bits 8 #define GFX8_3DSTATE_DS_UserClipDistanceClipTestEnableBitmask_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DS_UserClipDistanceClipTestEnableBitmask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DS_UserClipDistanceClipTestEnableBitmask_start 264 #define GFX12_3DSTATE_DS_UserClipDistanceClipTestEnableBitmask_start 264 #define GFX11_3DSTATE_DS_UserClipDistanceClipTestEnableBitmask_start 264 #define GFX9_3DSTATE_DS_UserClipDistanceClipTestEnableBitmask_start 264 #define GFX8_3DSTATE_DS_UserClipDistanceClipTestEnableBitmask_start 264 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DS_UserClipDistanceClipTestEnableBitmask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 264; case 120: return 264; case 110: return 264; case 90: return 264; case 80: return 264; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DS::User Clip Distance Cull Test Enable Bitmask */ #define GFX125_3DSTATE_DS_UserClipDistanceCullTestEnableBitmask_bits 8 #define GFX12_3DSTATE_DS_UserClipDistanceCullTestEnableBitmask_bits 8 #define GFX11_3DSTATE_DS_UserClipDistanceCullTestEnableBitmask_bits 8 #define GFX9_3DSTATE_DS_UserClipDistanceCullTestEnableBitmask_bits 8 #define GFX8_3DSTATE_DS_UserClipDistanceCullTestEnableBitmask_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DS_UserClipDistanceCullTestEnableBitmask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DS_UserClipDistanceCullTestEnableBitmask_start 256 #define GFX12_3DSTATE_DS_UserClipDistanceCullTestEnableBitmask_start 256 #define GFX11_3DSTATE_DS_UserClipDistanceCullTestEnableBitmask_start 256 #define GFX9_3DSTATE_DS_UserClipDistanceCullTestEnableBitmask_start 256 #define GFX8_3DSTATE_DS_UserClipDistanceCullTestEnableBitmask_start 256 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DS_UserClipDistanceCullTestEnableBitmask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 256; case 120: return 256; case 110: return 256; case 90: return 256; case 80: return 256; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DS::Vector Mask Enable */ #define GFX125_3DSTATE_DS_VectorMaskEnable_bits 1 #define GFX12_3DSTATE_DS_VectorMaskEnable_bits 1 #define GFX11_3DSTATE_DS_VectorMaskEnable_bits 1 #define GFX9_3DSTATE_DS_VectorMaskEnable_bits 1 #define GFX8_3DSTATE_DS_VectorMaskEnable_bits 1 #define GFX75_3DSTATE_DS_VectorMaskEnable_bits 1 #define GFX7_3DSTATE_DS_VectorMaskEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DS_VectorMaskEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DS_VectorMaskEnable_start 126 #define GFX12_3DSTATE_DS_VectorMaskEnable_start 126 #define GFX11_3DSTATE_DS_VectorMaskEnable_start 126 #define GFX9_3DSTATE_DS_VectorMaskEnable_start 126 #define GFX8_3DSTATE_DS_VectorMaskEnable_start 126 #define GFX75_3DSTATE_DS_VectorMaskEnable_start 94 #define GFX7_3DSTATE_DS_VectorMaskEnable_start 94 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DS_VectorMaskEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 126; case 120: return 126; case 110: return 126; case 90: return 126; case 80: return 126; case 75: return 94; case 70: return 94; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DS::Vertex URB Entry Output Length */ #define GFX125_3DSTATE_DS_VertexURBEntryOutputLength_bits 5 #define GFX12_3DSTATE_DS_VertexURBEntryOutputLength_bits 5 #define GFX11_3DSTATE_DS_VertexURBEntryOutputLength_bits 5 #define GFX9_3DSTATE_DS_VertexURBEntryOutputLength_bits 5 #define GFX8_3DSTATE_DS_VertexURBEntryOutputLength_bits 5 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DS_VertexURBEntryOutputLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 5; case 110: return 5; case 90: return 5; case 80: return 5; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DS_VertexURBEntryOutputLength_start 272 #define GFX12_3DSTATE_DS_VertexURBEntryOutputLength_start 272 #define GFX11_3DSTATE_DS_VertexURBEntryOutputLength_start 272 #define GFX9_3DSTATE_DS_VertexURBEntryOutputLength_start 272 #define GFX8_3DSTATE_DS_VertexURBEntryOutputLength_start 272 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DS_VertexURBEntryOutputLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 272; case 120: return 272; case 110: return 272; case 90: return 272; case 80: return 272; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_DS::Vertex URB Entry Output Read Offset */ #define GFX125_3DSTATE_DS_VertexURBEntryOutputReadOffset_bits 6 #define GFX12_3DSTATE_DS_VertexURBEntryOutputReadOffset_bits 6 #define GFX11_3DSTATE_DS_VertexURBEntryOutputReadOffset_bits 6 #define GFX9_3DSTATE_DS_VertexURBEntryOutputReadOffset_bits 6 #define GFX8_3DSTATE_DS_VertexURBEntryOutputReadOffset_bits 6 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DS_VertexURBEntryOutputReadOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_DS_VertexURBEntryOutputReadOffset_start 277 #define GFX12_3DSTATE_DS_VertexURBEntryOutputReadOffset_start 277 #define GFX11_3DSTATE_DS_VertexURBEntryOutputReadOffset_start 277 #define GFX9_3DSTATE_DS_VertexURBEntryOutputReadOffset_start 277 #define GFX8_3DSTATE_DS_VertexURBEntryOutputReadOffset_start 277 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_DS_VertexURBEntryOutputReadOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 277; case 120: return 277; case 110: return 277; case 90: return 277; case 80: return 277; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GATHER_CONSTANT_DS */ /* 3DSTATE_GATHER_CONSTANT_DS::3D Command Opcode */ #define GFX125_3DSTATE_GATHER_CONSTANT_DS_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_GATHER_CONSTANT_DS_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_GATHER_CONSTANT_DS_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_GATHER_CONSTANT_DS_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_GATHER_CONSTANT_DS_3DCommandOpcode_bits 3 #define GFX75_3DSTATE_GATHER_CONSTANT_DS_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_DS_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GATHER_CONSTANT_DS_3DCommandOpcode_start 24 #define GFX12_3DSTATE_GATHER_CONSTANT_DS_3DCommandOpcode_start 24 #define GFX11_3DSTATE_GATHER_CONSTANT_DS_3DCommandOpcode_start 24 #define GFX9_3DSTATE_GATHER_CONSTANT_DS_3DCommandOpcode_start 24 #define GFX8_3DSTATE_GATHER_CONSTANT_DS_3DCommandOpcode_start 24 #define GFX75_3DSTATE_GATHER_CONSTANT_DS_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_DS_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GATHER_CONSTANT_DS::3D Command Sub Opcode */ #define GFX125_3DSTATE_GATHER_CONSTANT_DS_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_GATHER_CONSTANT_DS_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_GATHER_CONSTANT_DS_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_GATHER_CONSTANT_DS_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_GATHER_CONSTANT_DS_3DCommandSubOpcode_bits 8 #define GFX75_3DSTATE_GATHER_CONSTANT_DS_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_DS_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GATHER_CONSTANT_DS_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_GATHER_CONSTANT_DS_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_GATHER_CONSTANT_DS_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_GATHER_CONSTANT_DS_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_GATHER_CONSTANT_DS_3DCommandSubOpcode_start 16 #define GFX75_3DSTATE_GATHER_CONSTANT_DS_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_DS_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GATHER_CONSTANT_DS::Command SubType */ #define GFX125_3DSTATE_GATHER_CONSTANT_DS_CommandSubType_bits 2 #define GFX12_3DSTATE_GATHER_CONSTANT_DS_CommandSubType_bits 2 #define GFX11_3DSTATE_GATHER_CONSTANT_DS_CommandSubType_bits 2 #define GFX9_3DSTATE_GATHER_CONSTANT_DS_CommandSubType_bits 2 #define GFX8_3DSTATE_GATHER_CONSTANT_DS_CommandSubType_bits 2 #define GFX75_3DSTATE_GATHER_CONSTANT_DS_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_DS_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GATHER_CONSTANT_DS_CommandSubType_start 27 #define GFX12_3DSTATE_GATHER_CONSTANT_DS_CommandSubType_start 27 #define GFX11_3DSTATE_GATHER_CONSTANT_DS_CommandSubType_start 27 #define GFX9_3DSTATE_GATHER_CONSTANT_DS_CommandSubType_start 27 #define GFX8_3DSTATE_GATHER_CONSTANT_DS_CommandSubType_start 27 #define GFX75_3DSTATE_GATHER_CONSTANT_DS_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_DS_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GATHER_CONSTANT_DS::Command Type */ #define GFX125_3DSTATE_GATHER_CONSTANT_DS_CommandType_bits 3 #define GFX12_3DSTATE_GATHER_CONSTANT_DS_CommandType_bits 3 #define GFX11_3DSTATE_GATHER_CONSTANT_DS_CommandType_bits 3 #define GFX9_3DSTATE_GATHER_CONSTANT_DS_CommandType_bits 3 #define GFX8_3DSTATE_GATHER_CONSTANT_DS_CommandType_bits 3 #define GFX75_3DSTATE_GATHER_CONSTANT_DS_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_DS_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GATHER_CONSTANT_DS_CommandType_start 29 #define GFX12_3DSTATE_GATHER_CONSTANT_DS_CommandType_start 29 #define GFX11_3DSTATE_GATHER_CONSTANT_DS_CommandType_start 29 #define GFX9_3DSTATE_GATHER_CONSTANT_DS_CommandType_start 29 #define GFX8_3DSTATE_GATHER_CONSTANT_DS_CommandType_start 29 #define GFX75_3DSTATE_GATHER_CONSTANT_DS_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_DS_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GATHER_CONSTANT_DS::Constant Buffer Binding Table Block */ #define GFX125_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferBindingTableBlock_bits 4 #define GFX12_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferBindingTableBlock_bits 4 #define GFX11_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferBindingTableBlock_bits 4 #define GFX9_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferBindingTableBlock_bits 4 #define GFX8_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferBindingTableBlock_bits 4 #define GFX75_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferBindingTableBlock_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_DS_ConstantBufferBindingTableBlock_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 4; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferBindingTableBlock_start 44 #define GFX12_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferBindingTableBlock_start 44 #define GFX11_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferBindingTableBlock_start 44 #define GFX9_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferBindingTableBlock_start 44 #define GFX8_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferBindingTableBlock_start 44 #define GFX75_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferBindingTableBlock_start 44 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_DS_ConstantBufferBindingTableBlock_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 44; case 120: return 44; case 110: return 44; case 90: return 44; case 80: return 44; case 75: return 44; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GATHER_CONSTANT_DS::Constant Buffer Dx9 Generate Stall */ #define GFX125_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferDx9GenerateStall_bits 1 #define GFX12_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferDx9GenerateStall_bits 1 #define GFX11_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferDx9GenerateStall_bits 1 #define GFX9_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferDx9GenerateStall_bits 1 #define GFX8_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferDx9GenerateStall_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_DS_ConstantBufferDx9GenerateStall_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferDx9GenerateStall_start 69 #define GFX12_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferDx9GenerateStall_start 69 #define GFX11_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferDx9GenerateStall_start 69 #define GFX9_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferDx9GenerateStall_start 69 #define GFX8_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferDx9GenerateStall_start 69 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_DS_ConstantBufferDx9GenerateStall_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 69; case 120: return 69; case 110: return 69; case 90: return 69; case 80: return 69; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GATHER_CONSTANT_DS::Constant Buffer Valid */ #define GFX125_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferValid_bits 16 #define GFX12_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferValid_bits 16 #define GFX11_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferValid_bits 16 #define GFX9_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferValid_bits 16 #define GFX8_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferValid_bits 16 #define GFX75_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferValid_bits 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_DS_ConstantBufferValid_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferValid_start 48 #define GFX12_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferValid_start 48 #define GFX11_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferValid_start 48 #define GFX9_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferValid_start 48 #define GFX8_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferValid_start 48 #define GFX75_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferValid_start 48 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_DS_ConstantBufferValid_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 48; case 120: return 48; case 110: return 48; case 90: return 48; case 80: return 48; case 75: return 48; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GATHER_CONSTANT_DS::DWord Length */ #define GFX125_3DSTATE_GATHER_CONSTANT_DS_DWordLength_bits 8 #define GFX12_3DSTATE_GATHER_CONSTANT_DS_DWordLength_bits 8 #define GFX11_3DSTATE_GATHER_CONSTANT_DS_DWordLength_bits 8 #define GFX9_3DSTATE_GATHER_CONSTANT_DS_DWordLength_bits 8 #define GFX8_3DSTATE_GATHER_CONSTANT_DS_DWordLength_bits 8 #define GFX75_3DSTATE_GATHER_CONSTANT_DS_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_DS_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GATHER_CONSTANT_DS_DWordLength_start 0 #define GFX12_3DSTATE_GATHER_CONSTANT_DS_DWordLength_start 0 #define GFX11_3DSTATE_GATHER_CONSTANT_DS_DWordLength_start 0 #define GFX9_3DSTATE_GATHER_CONSTANT_DS_DWordLength_start 0 #define GFX8_3DSTATE_GATHER_CONSTANT_DS_DWordLength_start 0 #define GFX75_3DSTATE_GATHER_CONSTANT_DS_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_DS_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GATHER_CONSTANT_DS::Gather Buffer Offset */ #define GFX125_3DSTATE_GATHER_CONSTANT_DS_GatherBufferOffset_bits 17 #define GFX12_3DSTATE_GATHER_CONSTANT_DS_GatherBufferOffset_bits 17 #define GFX11_3DSTATE_GATHER_CONSTANT_DS_GatherBufferOffset_bits 17 #define GFX9_3DSTATE_GATHER_CONSTANT_DS_GatherBufferOffset_bits 17 #define GFX8_3DSTATE_GATHER_CONSTANT_DS_GatherBufferOffset_bits 17 #define GFX75_3DSTATE_GATHER_CONSTANT_DS_GatherBufferOffset_bits 17 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_DS_GatherBufferOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 17; case 120: return 17; case 110: return 17; case 90: return 17; case 80: return 17; case 75: return 17; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GATHER_CONSTANT_DS_GatherBufferOffset_start 70 #define GFX12_3DSTATE_GATHER_CONSTANT_DS_GatherBufferOffset_start 70 #define GFX11_3DSTATE_GATHER_CONSTANT_DS_GatherBufferOffset_start 70 #define GFX9_3DSTATE_GATHER_CONSTANT_DS_GatherBufferOffset_start 70 #define GFX8_3DSTATE_GATHER_CONSTANT_DS_GatherBufferOffset_start 70 #define GFX75_3DSTATE_GATHER_CONSTANT_DS_GatherBufferOffset_start 70 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_DS_GatherBufferOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 70; case 120: return 70; case 110: return 70; case 90: return 70; case 80: return 70; case 75: return 70; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GATHER_CONSTANT_DS::On-Die Table */ #define GFX125_3DSTATE_GATHER_CONSTANT_DS_OnDieTable_bits 1 #define GFX12_3DSTATE_GATHER_CONSTANT_DS_OnDieTable_bits 1 #define GFX11_3DSTATE_GATHER_CONSTANT_DS_OnDieTable_bits 1 #define GFX9_3DSTATE_GATHER_CONSTANT_DS_OnDieTable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_DS_OnDieTable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GATHER_CONSTANT_DS_OnDieTable_start 67 #define GFX12_3DSTATE_GATHER_CONSTANT_DS_OnDieTable_start 67 #define GFX11_3DSTATE_GATHER_CONSTANT_DS_OnDieTable_start 67 #define GFX9_3DSTATE_GATHER_CONSTANT_DS_OnDieTable_start 67 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_DS_OnDieTable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 67; case 120: return 67; case 110: return 67; case 90: return 67; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GATHER_CONSTANT_DS::Update Gather Table Only */ #define GFX125_3DSTATE_GATHER_CONSTANT_DS_UpdateGatherTableOnly_bits 1 #define GFX12_3DSTATE_GATHER_CONSTANT_DS_UpdateGatherTableOnly_bits 1 #define GFX11_3DSTATE_GATHER_CONSTANT_DS_UpdateGatherTableOnly_bits 1 #define GFX9_3DSTATE_GATHER_CONSTANT_DS_UpdateGatherTableOnly_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_DS_UpdateGatherTableOnly_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GATHER_CONSTANT_DS_UpdateGatherTableOnly_start 33 #define GFX12_3DSTATE_GATHER_CONSTANT_DS_UpdateGatherTableOnly_start 33 #define GFX11_3DSTATE_GATHER_CONSTANT_DS_UpdateGatherTableOnly_start 33 #define GFX9_3DSTATE_GATHER_CONSTANT_DS_UpdateGatherTableOnly_start 33 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_DS_UpdateGatherTableOnly_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 33; case 120: return 33; case 110: return 33; case 90: return 33; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GATHER_CONSTANT_GS */ /* 3DSTATE_GATHER_CONSTANT_GS::3D Command Opcode */ #define GFX125_3DSTATE_GATHER_CONSTANT_GS_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_GATHER_CONSTANT_GS_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_GATHER_CONSTANT_GS_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_GATHER_CONSTANT_GS_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_GATHER_CONSTANT_GS_3DCommandOpcode_bits 3 #define GFX75_3DSTATE_GATHER_CONSTANT_GS_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_GS_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GATHER_CONSTANT_GS_3DCommandOpcode_start 24 #define GFX12_3DSTATE_GATHER_CONSTANT_GS_3DCommandOpcode_start 24 #define GFX11_3DSTATE_GATHER_CONSTANT_GS_3DCommandOpcode_start 24 #define GFX9_3DSTATE_GATHER_CONSTANT_GS_3DCommandOpcode_start 24 #define GFX8_3DSTATE_GATHER_CONSTANT_GS_3DCommandOpcode_start 24 #define GFX75_3DSTATE_GATHER_CONSTANT_GS_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_GS_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GATHER_CONSTANT_GS::3D Command Sub Opcode */ #define GFX125_3DSTATE_GATHER_CONSTANT_GS_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_GATHER_CONSTANT_GS_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_GATHER_CONSTANT_GS_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_GATHER_CONSTANT_GS_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_GATHER_CONSTANT_GS_3DCommandSubOpcode_bits 8 #define GFX75_3DSTATE_GATHER_CONSTANT_GS_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_GS_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GATHER_CONSTANT_GS_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_GATHER_CONSTANT_GS_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_GATHER_CONSTANT_GS_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_GATHER_CONSTANT_GS_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_GATHER_CONSTANT_GS_3DCommandSubOpcode_start 16 #define GFX75_3DSTATE_GATHER_CONSTANT_GS_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_GS_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GATHER_CONSTANT_GS::Command SubType */ #define GFX125_3DSTATE_GATHER_CONSTANT_GS_CommandSubType_bits 2 #define GFX12_3DSTATE_GATHER_CONSTANT_GS_CommandSubType_bits 2 #define GFX11_3DSTATE_GATHER_CONSTANT_GS_CommandSubType_bits 2 #define GFX9_3DSTATE_GATHER_CONSTANT_GS_CommandSubType_bits 2 #define GFX8_3DSTATE_GATHER_CONSTANT_GS_CommandSubType_bits 2 #define GFX75_3DSTATE_GATHER_CONSTANT_GS_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_GS_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GATHER_CONSTANT_GS_CommandSubType_start 27 #define GFX12_3DSTATE_GATHER_CONSTANT_GS_CommandSubType_start 27 #define GFX11_3DSTATE_GATHER_CONSTANT_GS_CommandSubType_start 27 #define GFX9_3DSTATE_GATHER_CONSTANT_GS_CommandSubType_start 27 #define GFX8_3DSTATE_GATHER_CONSTANT_GS_CommandSubType_start 27 #define GFX75_3DSTATE_GATHER_CONSTANT_GS_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_GS_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GATHER_CONSTANT_GS::Command Type */ #define GFX125_3DSTATE_GATHER_CONSTANT_GS_CommandType_bits 3 #define GFX12_3DSTATE_GATHER_CONSTANT_GS_CommandType_bits 3 #define GFX11_3DSTATE_GATHER_CONSTANT_GS_CommandType_bits 3 #define GFX9_3DSTATE_GATHER_CONSTANT_GS_CommandType_bits 3 #define GFX8_3DSTATE_GATHER_CONSTANT_GS_CommandType_bits 3 #define GFX75_3DSTATE_GATHER_CONSTANT_GS_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_GS_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GATHER_CONSTANT_GS_CommandType_start 29 #define GFX12_3DSTATE_GATHER_CONSTANT_GS_CommandType_start 29 #define GFX11_3DSTATE_GATHER_CONSTANT_GS_CommandType_start 29 #define GFX9_3DSTATE_GATHER_CONSTANT_GS_CommandType_start 29 #define GFX8_3DSTATE_GATHER_CONSTANT_GS_CommandType_start 29 #define GFX75_3DSTATE_GATHER_CONSTANT_GS_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_GS_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GATHER_CONSTANT_GS::Constant Buffer Binding Table Block */ #define GFX125_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferBindingTableBlock_bits 4 #define GFX12_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferBindingTableBlock_bits 4 #define GFX11_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferBindingTableBlock_bits 4 #define GFX9_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferBindingTableBlock_bits 4 #define GFX8_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferBindingTableBlock_bits 4 #define GFX75_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferBindingTableBlock_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_GS_ConstantBufferBindingTableBlock_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 4; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferBindingTableBlock_start 44 #define GFX12_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferBindingTableBlock_start 44 #define GFX11_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferBindingTableBlock_start 44 #define GFX9_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferBindingTableBlock_start 44 #define GFX8_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferBindingTableBlock_start 44 #define GFX75_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferBindingTableBlock_start 44 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_GS_ConstantBufferBindingTableBlock_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 44; case 120: return 44; case 110: return 44; case 90: return 44; case 80: return 44; case 75: return 44; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GATHER_CONSTANT_GS::Constant Buffer Dx9 Generate Stall */ #define GFX125_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferDx9GenerateStall_bits 1 #define GFX12_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferDx9GenerateStall_bits 1 #define GFX11_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferDx9GenerateStall_bits 1 #define GFX9_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferDx9GenerateStall_bits 1 #define GFX8_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferDx9GenerateStall_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_GS_ConstantBufferDx9GenerateStall_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferDx9GenerateStall_start 69 #define GFX12_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferDx9GenerateStall_start 69 #define GFX11_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferDx9GenerateStall_start 69 #define GFX9_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferDx9GenerateStall_start 69 #define GFX8_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferDx9GenerateStall_start 69 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_GS_ConstantBufferDx9GenerateStall_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 69; case 120: return 69; case 110: return 69; case 90: return 69; case 80: return 69; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GATHER_CONSTANT_GS::Constant Buffer Valid */ #define GFX125_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferValid_bits 16 #define GFX12_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferValid_bits 16 #define GFX11_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferValid_bits 16 #define GFX9_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferValid_bits 16 #define GFX8_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferValid_bits 16 #define GFX75_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferValid_bits 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_GS_ConstantBufferValid_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferValid_start 48 #define GFX12_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferValid_start 48 #define GFX11_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferValid_start 48 #define GFX9_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferValid_start 48 #define GFX8_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferValid_start 48 #define GFX75_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferValid_start 48 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_GS_ConstantBufferValid_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 48; case 120: return 48; case 110: return 48; case 90: return 48; case 80: return 48; case 75: return 48; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GATHER_CONSTANT_GS::DWord Length */ #define GFX125_3DSTATE_GATHER_CONSTANT_GS_DWordLength_bits 8 #define GFX12_3DSTATE_GATHER_CONSTANT_GS_DWordLength_bits 8 #define GFX11_3DSTATE_GATHER_CONSTANT_GS_DWordLength_bits 8 #define GFX9_3DSTATE_GATHER_CONSTANT_GS_DWordLength_bits 8 #define GFX8_3DSTATE_GATHER_CONSTANT_GS_DWordLength_bits 8 #define GFX75_3DSTATE_GATHER_CONSTANT_GS_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_GS_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GATHER_CONSTANT_GS_DWordLength_start 0 #define GFX12_3DSTATE_GATHER_CONSTANT_GS_DWordLength_start 0 #define GFX11_3DSTATE_GATHER_CONSTANT_GS_DWordLength_start 0 #define GFX9_3DSTATE_GATHER_CONSTANT_GS_DWordLength_start 0 #define GFX8_3DSTATE_GATHER_CONSTANT_GS_DWordLength_start 0 #define GFX75_3DSTATE_GATHER_CONSTANT_GS_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_GS_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GATHER_CONSTANT_GS::Gather Buffer Offset */ #define GFX125_3DSTATE_GATHER_CONSTANT_GS_GatherBufferOffset_bits 17 #define GFX12_3DSTATE_GATHER_CONSTANT_GS_GatherBufferOffset_bits 17 #define GFX11_3DSTATE_GATHER_CONSTANT_GS_GatherBufferOffset_bits 17 #define GFX9_3DSTATE_GATHER_CONSTANT_GS_GatherBufferOffset_bits 17 #define GFX8_3DSTATE_GATHER_CONSTANT_GS_GatherBufferOffset_bits 17 #define GFX75_3DSTATE_GATHER_CONSTANT_GS_GatherBufferOffset_bits 17 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_GS_GatherBufferOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 17; case 120: return 17; case 110: return 17; case 90: return 17; case 80: return 17; case 75: return 17; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GATHER_CONSTANT_GS_GatherBufferOffset_start 70 #define GFX12_3DSTATE_GATHER_CONSTANT_GS_GatherBufferOffset_start 70 #define GFX11_3DSTATE_GATHER_CONSTANT_GS_GatherBufferOffset_start 70 #define GFX9_3DSTATE_GATHER_CONSTANT_GS_GatherBufferOffset_start 70 #define GFX8_3DSTATE_GATHER_CONSTANT_GS_GatherBufferOffset_start 70 #define GFX75_3DSTATE_GATHER_CONSTANT_GS_GatherBufferOffset_start 70 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_GS_GatherBufferOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 70; case 120: return 70; case 110: return 70; case 90: return 70; case 80: return 70; case 75: return 70; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GATHER_CONSTANT_GS::On-Die Table */ #define GFX125_3DSTATE_GATHER_CONSTANT_GS_OnDieTable_bits 1 #define GFX12_3DSTATE_GATHER_CONSTANT_GS_OnDieTable_bits 1 #define GFX11_3DSTATE_GATHER_CONSTANT_GS_OnDieTable_bits 1 #define GFX9_3DSTATE_GATHER_CONSTANT_GS_OnDieTable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_GS_OnDieTable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GATHER_CONSTANT_GS_OnDieTable_start 67 #define GFX12_3DSTATE_GATHER_CONSTANT_GS_OnDieTable_start 67 #define GFX11_3DSTATE_GATHER_CONSTANT_GS_OnDieTable_start 67 #define GFX9_3DSTATE_GATHER_CONSTANT_GS_OnDieTable_start 67 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_GS_OnDieTable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 67; case 120: return 67; case 110: return 67; case 90: return 67; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GATHER_CONSTANT_GS::Update Gather Table Only */ #define GFX125_3DSTATE_GATHER_CONSTANT_GS_UpdateGatherTableOnly_bits 1 #define GFX12_3DSTATE_GATHER_CONSTANT_GS_UpdateGatherTableOnly_bits 1 #define GFX11_3DSTATE_GATHER_CONSTANT_GS_UpdateGatherTableOnly_bits 1 #define GFX9_3DSTATE_GATHER_CONSTANT_GS_UpdateGatherTableOnly_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_GS_UpdateGatherTableOnly_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GATHER_CONSTANT_GS_UpdateGatherTableOnly_start 33 #define GFX12_3DSTATE_GATHER_CONSTANT_GS_UpdateGatherTableOnly_start 33 #define GFX11_3DSTATE_GATHER_CONSTANT_GS_UpdateGatherTableOnly_start 33 #define GFX9_3DSTATE_GATHER_CONSTANT_GS_UpdateGatherTableOnly_start 33 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_GS_UpdateGatherTableOnly_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 33; case 120: return 33; case 110: return 33; case 90: return 33; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GATHER_CONSTANT_HS */ /* 3DSTATE_GATHER_CONSTANT_HS::3D Command Opcode */ #define GFX125_3DSTATE_GATHER_CONSTANT_HS_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_GATHER_CONSTANT_HS_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_GATHER_CONSTANT_HS_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_GATHER_CONSTANT_HS_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_GATHER_CONSTANT_HS_3DCommandOpcode_bits 3 #define GFX75_3DSTATE_GATHER_CONSTANT_HS_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_HS_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GATHER_CONSTANT_HS_3DCommandOpcode_start 24 #define GFX12_3DSTATE_GATHER_CONSTANT_HS_3DCommandOpcode_start 24 #define GFX11_3DSTATE_GATHER_CONSTANT_HS_3DCommandOpcode_start 24 #define GFX9_3DSTATE_GATHER_CONSTANT_HS_3DCommandOpcode_start 24 #define GFX8_3DSTATE_GATHER_CONSTANT_HS_3DCommandOpcode_start 24 #define GFX75_3DSTATE_GATHER_CONSTANT_HS_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_HS_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GATHER_CONSTANT_HS::3D Command Sub Opcode */ #define GFX125_3DSTATE_GATHER_CONSTANT_HS_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_GATHER_CONSTANT_HS_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_GATHER_CONSTANT_HS_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_GATHER_CONSTANT_HS_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_GATHER_CONSTANT_HS_3DCommandSubOpcode_bits 8 #define GFX75_3DSTATE_GATHER_CONSTANT_HS_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_HS_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GATHER_CONSTANT_HS_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_GATHER_CONSTANT_HS_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_GATHER_CONSTANT_HS_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_GATHER_CONSTANT_HS_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_GATHER_CONSTANT_HS_3DCommandSubOpcode_start 16 #define GFX75_3DSTATE_GATHER_CONSTANT_HS_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_HS_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GATHER_CONSTANT_HS::Command SubType */ #define GFX125_3DSTATE_GATHER_CONSTANT_HS_CommandSubType_bits 2 #define GFX12_3DSTATE_GATHER_CONSTANT_HS_CommandSubType_bits 2 #define GFX11_3DSTATE_GATHER_CONSTANT_HS_CommandSubType_bits 2 #define GFX9_3DSTATE_GATHER_CONSTANT_HS_CommandSubType_bits 2 #define GFX8_3DSTATE_GATHER_CONSTANT_HS_CommandSubType_bits 2 #define GFX75_3DSTATE_GATHER_CONSTANT_HS_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_HS_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GATHER_CONSTANT_HS_CommandSubType_start 27 #define GFX12_3DSTATE_GATHER_CONSTANT_HS_CommandSubType_start 27 #define GFX11_3DSTATE_GATHER_CONSTANT_HS_CommandSubType_start 27 #define GFX9_3DSTATE_GATHER_CONSTANT_HS_CommandSubType_start 27 #define GFX8_3DSTATE_GATHER_CONSTANT_HS_CommandSubType_start 27 #define GFX75_3DSTATE_GATHER_CONSTANT_HS_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_HS_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GATHER_CONSTANT_HS::Command Type */ #define GFX125_3DSTATE_GATHER_CONSTANT_HS_CommandType_bits 3 #define GFX12_3DSTATE_GATHER_CONSTANT_HS_CommandType_bits 3 #define GFX11_3DSTATE_GATHER_CONSTANT_HS_CommandType_bits 3 #define GFX9_3DSTATE_GATHER_CONSTANT_HS_CommandType_bits 3 #define GFX8_3DSTATE_GATHER_CONSTANT_HS_CommandType_bits 3 #define GFX75_3DSTATE_GATHER_CONSTANT_HS_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_HS_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GATHER_CONSTANT_HS_CommandType_start 29 #define GFX12_3DSTATE_GATHER_CONSTANT_HS_CommandType_start 29 #define GFX11_3DSTATE_GATHER_CONSTANT_HS_CommandType_start 29 #define GFX9_3DSTATE_GATHER_CONSTANT_HS_CommandType_start 29 #define GFX8_3DSTATE_GATHER_CONSTANT_HS_CommandType_start 29 #define GFX75_3DSTATE_GATHER_CONSTANT_HS_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_HS_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GATHER_CONSTANT_HS::Constant Buffer Binding Table Block */ #define GFX125_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferBindingTableBlock_bits 4 #define GFX12_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferBindingTableBlock_bits 4 #define GFX11_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferBindingTableBlock_bits 4 #define GFX9_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferBindingTableBlock_bits 4 #define GFX8_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferBindingTableBlock_bits 4 #define GFX75_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferBindingTableBlock_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_HS_ConstantBufferBindingTableBlock_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 4; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferBindingTableBlock_start 44 #define GFX12_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferBindingTableBlock_start 44 #define GFX11_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferBindingTableBlock_start 44 #define GFX9_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferBindingTableBlock_start 44 #define GFX8_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferBindingTableBlock_start 44 #define GFX75_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferBindingTableBlock_start 44 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_HS_ConstantBufferBindingTableBlock_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 44; case 120: return 44; case 110: return 44; case 90: return 44; case 80: return 44; case 75: return 44; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GATHER_CONSTANT_HS::Constant Buffer Dx9 Generate Stall */ #define GFX125_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferDx9GenerateStall_bits 1 #define GFX12_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferDx9GenerateStall_bits 1 #define GFX11_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferDx9GenerateStall_bits 1 #define GFX9_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferDx9GenerateStall_bits 1 #define GFX8_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferDx9GenerateStall_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_HS_ConstantBufferDx9GenerateStall_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferDx9GenerateStall_start 69 #define GFX12_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferDx9GenerateStall_start 69 #define GFX11_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferDx9GenerateStall_start 69 #define GFX9_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferDx9GenerateStall_start 69 #define GFX8_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferDx9GenerateStall_start 69 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_HS_ConstantBufferDx9GenerateStall_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 69; case 120: return 69; case 110: return 69; case 90: return 69; case 80: return 69; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GATHER_CONSTANT_HS::Constant Buffer Valid */ #define GFX125_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferValid_bits 16 #define GFX12_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferValid_bits 16 #define GFX11_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferValid_bits 16 #define GFX9_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferValid_bits 16 #define GFX8_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferValid_bits 16 #define GFX75_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferValid_bits 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_HS_ConstantBufferValid_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferValid_start 48 #define GFX12_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferValid_start 48 #define GFX11_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferValid_start 48 #define GFX9_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferValid_start 48 #define GFX8_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferValid_start 48 #define GFX75_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferValid_start 48 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_HS_ConstantBufferValid_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 48; case 120: return 48; case 110: return 48; case 90: return 48; case 80: return 48; case 75: return 48; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GATHER_CONSTANT_HS::DWord Length */ #define GFX125_3DSTATE_GATHER_CONSTANT_HS_DWordLength_bits 8 #define GFX12_3DSTATE_GATHER_CONSTANT_HS_DWordLength_bits 8 #define GFX11_3DSTATE_GATHER_CONSTANT_HS_DWordLength_bits 8 #define GFX9_3DSTATE_GATHER_CONSTANT_HS_DWordLength_bits 8 #define GFX8_3DSTATE_GATHER_CONSTANT_HS_DWordLength_bits 8 #define GFX75_3DSTATE_GATHER_CONSTANT_HS_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_HS_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GATHER_CONSTANT_HS_DWordLength_start 0 #define GFX12_3DSTATE_GATHER_CONSTANT_HS_DWordLength_start 0 #define GFX11_3DSTATE_GATHER_CONSTANT_HS_DWordLength_start 0 #define GFX9_3DSTATE_GATHER_CONSTANT_HS_DWordLength_start 0 #define GFX8_3DSTATE_GATHER_CONSTANT_HS_DWordLength_start 0 #define GFX75_3DSTATE_GATHER_CONSTANT_HS_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_HS_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GATHER_CONSTANT_HS::Gather Buffer Offset */ #define GFX125_3DSTATE_GATHER_CONSTANT_HS_GatherBufferOffset_bits 17 #define GFX12_3DSTATE_GATHER_CONSTANT_HS_GatherBufferOffset_bits 17 #define GFX11_3DSTATE_GATHER_CONSTANT_HS_GatherBufferOffset_bits 17 #define GFX9_3DSTATE_GATHER_CONSTANT_HS_GatherBufferOffset_bits 17 #define GFX8_3DSTATE_GATHER_CONSTANT_HS_GatherBufferOffset_bits 17 #define GFX75_3DSTATE_GATHER_CONSTANT_HS_GatherBufferOffset_bits 17 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_HS_GatherBufferOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 17; case 120: return 17; case 110: return 17; case 90: return 17; case 80: return 17; case 75: return 17; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GATHER_CONSTANT_HS_GatherBufferOffset_start 70 #define GFX12_3DSTATE_GATHER_CONSTANT_HS_GatherBufferOffset_start 70 #define GFX11_3DSTATE_GATHER_CONSTANT_HS_GatherBufferOffset_start 70 #define GFX9_3DSTATE_GATHER_CONSTANT_HS_GatherBufferOffset_start 70 #define GFX8_3DSTATE_GATHER_CONSTANT_HS_GatherBufferOffset_start 70 #define GFX75_3DSTATE_GATHER_CONSTANT_HS_GatherBufferOffset_start 70 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_HS_GatherBufferOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 70; case 120: return 70; case 110: return 70; case 90: return 70; case 80: return 70; case 75: return 70; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GATHER_CONSTANT_HS::On-Die Table */ #define GFX125_3DSTATE_GATHER_CONSTANT_HS_OnDieTable_bits 1 #define GFX12_3DSTATE_GATHER_CONSTANT_HS_OnDieTable_bits 1 #define GFX11_3DSTATE_GATHER_CONSTANT_HS_OnDieTable_bits 1 #define GFX9_3DSTATE_GATHER_CONSTANT_HS_OnDieTable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_HS_OnDieTable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GATHER_CONSTANT_HS_OnDieTable_start 67 #define GFX12_3DSTATE_GATHER_CONSTANT_HS_OnDieTable_start 67 #define GFX11_3DSTATE_GATHER_CONSTANT_HS_OnDieTable_start 67 #define GFX9_3DSTATE_GATHER_CONSTANT_HS_OnDieTable_start 67 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_HS_OnDieTable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 67; case 120: return 67; case 110: return 67; case 90: return 67; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GATHER_CONSTANT_HS::Update Gather Table Only */ #define GFX125_3DSTATE_GATHER_CONSTANT_HS_UpdateGatherTableOnly_bits 1 #define GFX12_3DSTATE_GATHER_CONSTANT_HS_UpdateGatherTableOnly_bits 1 #define GFX11_3DSTATE_GATHER_CONSTANT_HS_UpdateGatherTableOnly_bits 1 #define GFX9_3DSTATE_GATHER_CONSTANT_HS_UpdateGatherTableOnly_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_HS_UpdateGatherTableOnly_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GATHER_CONSTANT_HS_UpdateGatherTableOnly_start 33 #define GFX12_3DSTATE_GATHER_CONSTANT_HS_UpdateGatherTableOnly_start 33 #define GFX11_3DSTATE_GATHER_CONSTANT_HS_UpdateGatherTableOnly_start 33 #define GFX9_3DSTATE_GATHER_CONSTANT_HS_UpdateGatherTableOnly_start 33 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_HS_UpdateGatherTableOnly_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 33; case 120: return 33; case 110: return 33; case 90: return 33; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GATHER_CONSTANT_PS */ /* 3DSTATE_GATHER_CONSTANT_PS::3D Command Opcode */ #define GFX125_3DSTATE_GATHER_CONSTANT_PS_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_GATHER_CONSTANT_PS_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_GATHER_CONSTANT_PS_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_GATHER_CONSTANT_PS_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_GATHER_CONSTANT_PS_3DCommandOpcode_bits 3 #define GFX75_3DSTATE_GATHER_CONSTANT_PS_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_PS_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GATHER_CONSTANT_PS_3DCommandOpcode_start 24 #define GFX12_3DSTATE_GATHER_CONSTANT_PS_3DCommandOpcode_start 24 #define GFX11_3DSTATE_GATHER_CONSTANT_PS_3DCommandOpcode_start 24 #define GFX9_3DSTATE_GATHER_CONSTANT_PS_3DCommandOpcode_start 24 #define GFX8_3DSTATE_GATHER_CONSTANT_PS_3DCommandOpcode_start 24 #define GFX75_3DSTATE_GATHER_CONSTANT_PS_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_PS_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GATHER_CONSTANT_PS::3D Command Sub Opcode */ #define GFX125_3DSTATE_GATHER_CONSTANT_PS_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_GATHER_CONSTANT_PS_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_GATHER_CONSTANT_PS_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_GATHER_CONSTANT_PS_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_GATHER_CONSTANT_PS_3DCommandSubOpcode_bits 8 #define GFX75_3DSTATE_GATHER_CONSTANT_PS_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_PS_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GATHER_CONSTANT_PS_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_GATHER_CONSTANT_PS_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_GATHER_CONSTANT_PS_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_GATHER_CONSTANT_PS_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_GATHER_CONSTANT_PS_3DCommandSubOpcode_start 16 #define GFX75_3DSTATE_GATHER_CONSTANT_PS_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_PS_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GATHER_CONSTANT_PS::Command SubType */ #define GFX125_3DSTATE_GATHER_CONSTANT_PS_CommandSubType_bits 2 #define GFX12_3DSTATE_GATHER_CONSTANT_PS_CommandSubType_bits 2 #define GFX11_3DSTATE_GATHER_CONSTANT_PS_CommandSubType_bits 2 #define GFX9_3DSTATE_GATHER_CONSTANT_PS_CommandSubType_bits 2 #define GFX8_3DSTATE_GATHER_CONSTANT_PS_CommandSubType_bits 2 #define GFX75_3DSTATE_GATHER_CONSTANT_PS_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_PS_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GATHER_CONSTANT_PS_CommandSubType_start 27 #define GFX12_3DSTATE_GATHER_CONSTANT_PS_CommandSubType_start 27 #define GFX11_3DSTATE_GATHER_CONSTANT_PS_CommandSubType_start 27 #define GFX9_3DSTATE_GATHER_CONSTANT_PS_CommandSubType_start 27 #define GFX8_3DSTATE_GATHER_CONSTANT_PS_CommandSubType_start 27 #define GFX75_3DSTATE_GATHER_CONSTANT_PS_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_PS_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GATHER_CONSTANT_PS::Command Type */ #define GFX125_3DSTATE_GATHER_CONSTANT_PS_CommandType_bits 3 #define GFX12_3DSTATE_GATHER_CONSTANT_PS_CommandType_bits 3 #define GFX11_3DSTATE_GATHER_CONSTANT_PS_CommandType_bits 3 #define GFX9_3DSTATE_GATHER_CONSTANT_PS_CommandType_bits 3 #define GFX8_3DSTATE_GATHER_CONSTANT_PS_CommandType_bits 3 #define GFX75_3DSTATE_GATHER_CONSTANT_PS_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_PS_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GATHER_CONSTANT_PS_CommandType_start 29 #define GFX12_3DSTATE_GATHER_CONSTANT_PS_CommandType_start 29 #define GFX11_3DSTATE_GATHER_CONSTANT_PS_CommandType_start 29 #define GFX9_3DSTATE_GATHER_CONSTANT_PS_CommandType_start 29 #define GFX8_3DSTATE_GATHER_CONSTANT_PS_CommandType_start 29 #define GFX75_3DSTATE_GATHER_CONSTANT_PS_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_PS_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GATHER_CONSTANT_PS::Constant Buffer Binding Table Block */ #define GFX125_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferBindingTableBlock_bits 4 #define GFX12_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferBindingTableBlock_bits 4 #define GFX11_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferBindingTableBlock_bits 4 #define GFX9_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferBindingTableBlock_bits 4 #define GFX8_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferBindingTableBlock_bits 4 #define GFX75_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferBindingTableBlock_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_PS_ConstantBufferBindingTableBlock_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 4; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferBindingTableBlock_start 44 #define GFX12_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferBindingTableBlock_start 44 #define GFX11_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferBindingTableBlock_start 44 #define GFX9_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferBindingTableBlock_start 44 #define GFX8_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferBindingTableBlock_start 44 #define GFX75_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferBindingTableBlock_start 44 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_PS_ConstantBufferBindingTableBlock_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 44; case 120: return 44; case 110: return 44; case 90: return 44; case 80: return 44; case 75: return 44; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GATHER_CONSTANT_PS::Constant Buffer Dx9 Enable */ #define GFX125_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferDx9Enable_bits 1 #define GFX12_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferDx9Enable_bits 1 #define GFX11_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferDx9Enable_bits 1 #define GFX9_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferDx9Enable_bits 1 #define GFX8_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferDx9Enable_bits 1 #define GFX75_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferDx9Enable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_PS_ConstantBufferDx9Enable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferDx9Enable_start 68 #define GFX12_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferDx9Enable_start 68 #define GFX11_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferDx9Enable_start 68 #define GFX9_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferDx9Enable_start 68 #define GFX8_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferDx9Enable_start 68 #define GFX75_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferDx9Enable_start 68 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_PS_ConstantBufferDx9Enable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 68; case 120: return 68; case 110: return 68; case 90: return 68; case 80: return 68; case 75: return 68; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GATHER_CONSTANT_PS::Constant Buffer Dx9 Generate Stall */ #define GFX125_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferDx9GenerateStall_bits 1 #define GFX12_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferDx9GenerateStall_bits 1 #define GFX11_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferDx9GenerateStall_bits 1 #define GFX9_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferDx9GenerateStall_bits 1 #define GFX8_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferDx9GenerateStall_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_PS_ConstantBufferDx9GenerateStall_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferDx9GenerateStall_start 69 #define GFX12_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferDx9GenerateStall_start 69 #define GFX11_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferDx9GenerateStall_start 69 #define GFX9_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferDx9GenerateStall_start 69 #define GFX8_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferDx9GenerateStall_start 69 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_PS_ConstantBufferDx9GenerateStall_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 69; case 120: return 69; case 110: return 69; case 90: return 69; case 80: return 69; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GATHER_CONSTANT_PS::Constant Buffer Valid */ #define GFX125_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferValid_bits 16 #define GFX12_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferValid_bits 16 #define GFX11_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferValid_bits 16 #define GFX9_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferValid_bits 16 #define GFX8_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferValid_bits 16 #define GFX75_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferValid_bits 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_PS_ConstantBufferValid_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferValid_start 48 #define GFX12_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferValid_start 48 #define GFX11_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferValid_start 48 #define GFX9_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferValid_start 48 #define GFX8_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferValid_start 48 #define GFX75_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferValid_start 48 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_PS_ConstantBufferValid_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 48; case 120: return 48; case 110: return 48; case 90: return 48; case 80: return 48; case 75: return 48; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GATHER_CONSTANT_PS::DWord Length */ #define GFX125_3DSTATE_GATHER_CONSTANT_PS_DWordLength_bits 8 #define GFX12_3DSTATE_GATHER_CONSTANT_PS_DWordLength_bits 8 #define GFX11_3DSTATE_GATHER_CONSTANT_PS_DWordLength_bits 8 #define GFX9_3DSTATE_GATHER_CONSTANT_PS_DWordLength_bits 8 #define GFX8_3DSTATE_GATHER_CONSTANT_PS_DWordLength_bits 8 #define GFX75_3DSTATE_GATHER_CONSTANT_PS_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_PS_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GATHER_CONSTANT_PS_DWordLength_start 0 #define GFX12_3DSTATE_GATHER_CONSTANT_PS_DWordLength_start 0 #define GFX11_3DSTATE_GATHER_CONSTANT_PS_DWordLength_start 0 #define GFX9_3DSTATE_GATHER_CONSTANT_PS_DWordLength_start 0 #define GFX8_3DSTATE_GATHER_CONSTANT_PS_DWordLength_start 0 #define GFX75_3DSTATE_GATHER_CONSTANT_PS_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_PS_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GATHER_CONSTANT_PS::DX9 On-Die Register Read Enable */ #define GFX125_3DSTATE_GATHER_CONSTANT_PS_DX9OnDieRegisterReadEnable_bits 1 #define GFX12_3DSTATE_GATHER_CONSTANT_PS_DX9OnDieRegisterReadEnable_bits 1 #define GFX11_3DSTATE_GATHER_CONSTANT_PS_DX9OnDieRegisterReadEnable_bits 1 #define GFX9_3DSTATE_GATHER_CONSTANT_PS_DX9OnDieRegisterReadEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_PS_DX9OnDieRegisterReadEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GATHER_CONSTANT_PS_DX9OnDieRegisterReadEnable_start 32 #define GFX12_3DSTATE_GATHER_CONSTANT_PS_DX9OnDieRegisterReadEnable_start 32 #define GFX11_3DSTATE_GATHER_CONSTANT_PS_DX9OnDieRegisterReadEnable_start 32 #define GFX9_3DSTATE_GATHER_CONSTANT_PS_DX9OnDieRegisterReadEnable_start 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_PS_DX9OnDieRegisterReadEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GATHER_CONSTANT_PS::Gather Buffer Offset */ #define GFX125_3DSTATE_GATHER_CONSTANT_PS_GatherBufferOffset_bits 17 #define GFX12_3DSTATE_GATHER_CONSTANT_PS_GatherBufferOffset_bits 17 #define GFX11_3DSTATE_GATHER_CONSTANT_PS_GatherBufferOffset_bits 17 #define GFX9_3DSTATE_GATHER_CONSTANT_PS_GatherBufferOffset_bits 17 #define GFX8_3DSTATE_GATHER_CONSTANT_PS_GatherBufferOffset_bits 17 #define GFX75_3DSTATE_GATHER_CONSTANT_PS_GatherBufferOffset_bits 17 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_PS_GatherBufferOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 17; case 120: return 17; case 110: return 17; case 90: return 17; case 80: return 17; case 75: return 17; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GATHER_CONSTANT_PS_GatherBufferOffset_start 70 #define GFX12_3DSTATE_GATHER_CONSTANT_PS_GatherBufferOffset_start 70 #define GFX11_3DSTATE_GATHER_CONSTANT_PS_GatherBufferOffset_start 70 #define GFX9_3DSTATE_GATHER_CONSTANT_PS_GatherBufferOffset_start 70 #define GFX8_3DSTATE_GATHER_CONSTANT_PS_GatherBufferOffset_start 70 #define GFX75_3DSTATE_GATHER_CONSTANT_PS_GatherBufferOffset_start 70 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_PS_GatherBufferOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 70; case 120: return 70; case 110: return 70; case 90: return 70; case 80: return 70; case 75: return 70; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GATHER_CONSTANT_PS::On-Die Table */ #define GFX125_3DSTATE_GATHER_CONSTANT_PS_OnDieTable_bits 1 #define GFX12_3DSTATE_GATHER_CONSTANT_PS_OnDieTable_bits 1 #define GFX11_3DSTATE_GATHER_CONSTANT_PS_OnDieTable_bits 1 #define GFX9_3DSTATE_GATHER_CONSTANT_PS_OnDieTable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_PS_OnDieTable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GATHER_CONSTANT_PS_OnDieTable_start 67 #define GFX12_3DSTATE_GATHER_CONSTANT_PS_OnDieTable_start 67 #define GFX11_3DSTATE_GATHER_CONSTANT_PS_OnDieTable_start 67 #define GFX9_3DSTATE_GATHER_CONSTANT_PS_OnDieTable_start 67 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_PS_OnDieTable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 67; case 120: return 67; case 110: return 67; case 90: return 67; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GATHER_CONSTANT_PS::Update Gather Table Only */ #define GFX125_3DSTATE_GATHER_CONSTANT_PS_UpdateGatherTableOnly_bits 1 #define GFX12_3DSTATE_GATHER_CONSTANT_PS_UpdateGatherTableOnly_bits 1 #define GFX11_3DSTATE_GATHER_CONSTANT_PS_UpdateGatherTableOnly_bits 1 #define GFX9_3DSTATE_GATHER_CONSTANT_PS_UpdateGatherTableOnly_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_PS_UpdateGatherTableOnly_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GATHER_CONSTANT_PS_UpdateGatherTableOnly_start 33 #define GFX12_3DSTATE_GATHER_CONSTANT_PS_UpdateGatherTableOnly_start 33 #define GFX11_3DSTATE_GATHER_CONSTANT_PS_UpdateGatherTableOnly_start 33 #define GFX9_3DSTATE_GATHER_CONSTANT_PS_UpdateGatherTableOnly_start 33 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_PS_UpdateGatherTableOnly_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 33; case 120: return 33; case 110: return 33; case 90: return 33; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GATHER_CONSTANT_VS */ /* 3DSTATE_GATHER_CONSTANT_VS::3D Command Opcode */ #define GFX125_3DSTATE_GATHER_CONSTANT_VS_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_GATHER_CONSTANT_VS_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_GATHER_CONSTANT_VS_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_GATHER_CONSTANT_VS_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_GATHER_CONSTANT_VS_3DCommandOpcode_bits 3 #define GFX75_3DSTATE_GATHER_CONSTANT_VS_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_VS_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GATHER_CONSTANT_VS_3DCommandOpcode_start 24 #define GFX12_3DSTATE_GATHER_CONSTANT_VS_3DCommandOpcode_start 24 #define GFX11_3DSTATE_GATHER_CONSTANT_VS_3DCommandOpcode_start 24 #define GFX9_3DSTATE_GATHER_CONSTANT_VS_3DCommandOpcode_start 24 #define GFX8_3DSTATE_GATHER_CONSTANT_VS_3DCommandOpcode_start 24 #define GFX75_3DSTATE_GATHER_CONSTANT_VS_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_VS_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GATHER_CONSTANT_VS::3D Command Sub Opcode */ #define GFX125_3DSTATE_GATHER_CONSTANT_VS_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_GATHER_CONSTANT_VS_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_GATHER_CONSTANT_VS_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_GATHER_CONSTANT_VS_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_GATHER_CONSTANT_VS_3DCommandSubOpcode_bits 8 #define GFX75_3DSTATE_GATHER_CONSTANT_VS_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_VS_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GATHER_CONSTANT_VS_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_GATHER_CONSTANT_VS_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_GATHER_CONSTANT_VS_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_GATHER_CONSTANT_VS_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_GATHER_CONSTANT_VS_3DCommandSubOpcode_start 16 #define GFX75_3DSTATE_GATHER_CONSTANT_VS_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_VS_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GATHER_CONSTANT_VS::Command SubType */ #define GFX125_3DSTATE_GATHER_CONSTANT_VS_CommandSubType_bits 2 #define GFX12_3DSTATE_GATHER_CONSTANT_VS_CommandSubType_bits 2 #define GFX11_3DSTATE_GATHER_CONSTANT_VS_CommandSubType_bits 2 #define GFX9_3DSTATE_GATHER_CONSTANT_VS_CommandSubType_bits 2 #define GFX8_3DSTATE_GATHER_CONSTANT_VS_CommandSubType_bits 2 #define GFX75_3DSTATE_GATHER_CONSTANT_VS_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_VS_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GATHER_CONSTANT_VS_CommandSubType_start 27 #define GFX12_3DSTATE_GATHER_CONSTANT_VS_CommandSubType_start 27 #define GFX11_3DSTATE_GATHER_CONSTANT_VS_CommandSubType_start 27 #define GFX9_3DSTATE_GATHER_CONSTANT_VS_CommandSubType_start 27 #define GFX8_3DSTATE_GATHER_CONSTANT_VS_CommandSubType_start 27 #define GFX75_3DSTATE_GATHER_CONSTANT_VS_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_VS_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GATHER_CONSTANT_VS::Command Type */ #define GFX125_3DSTATE_GATHER_CONSTANT_VS_CommandType_bits 3 #define GFX12_3DSTATE_GATHER_CONSTANT_VS_CommandType_bits 3 #define GFX11_3DSTATE_GATHER_CONSTANT_VS_CommandType_bits 3 #define GFX9_3DSTATE_GATHER_CONSTANT_VS_CommandType_bits 3 #define GFX8_3DSTATE_GATHER_CONSTANT_VS_CommandType_bits 3 #define GFX75_3DSTATE_GATHER_CONSTANT_VS_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_VS_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GATHER_CONSTANT_VS_CommandType_start 29 #define GFX12_3DSTATE_GATHER_CONSTANT_VS_CommandType_start 29 #define GFX11_3DSTATE_GATHER_CONSTANT_VS_CommandType_start 29 #define GFX9_3DSTATE_GATHER_CONSTANT_VS_CommandType_start 29 #define GFX8_3DSTATE_GATHER_CONSTANT_VS_CommandType_start 29 #define GFX75_3DSTATE_GATHER_CONSTANT_VS_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_VS_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GATHER_CONSTANT_VS::Constant Buffer Binding Table Block */ #define GFX125_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferBindingTableBlock_bits 4 #define GFX12_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferBindingTableBlock_bits 4 #define GFX11_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferBindingTableBlock_bits 4 #define GFX9_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferBindingTableBlock_bits 4 #define GFX8_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferBindingTableBlock_bits 4 #define GFX75_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferBindingTableBlock_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_VS_ConstantBufferBindingTableBlock_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 4; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferBindingTableBlock_start 44 #define GFX12_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferBindingTableBlock_start 44 #define GFX11_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferBindingTableBlock_start 44 #define GFX9_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferBindingTableBlock_start 44 #define GFX8_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferBindingTableBlock_start 44 #define GFX75_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferBindingTableBlock_start 44 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_VS_ConstantBufferBindingTableBlock_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 44; case 120: return 44; case 110: return 44; case 90: return 44; case 80: return 44; case 75: return 44; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GATHER_CONSTANT_VS::Constant Buffer Dx9 Enable */ #define GFX125_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferDx9Enable_bits 1 #define GFX12_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferDx9Enable_bits 1 #define GFX11_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferDx9Enable_bits 1 #define GFX9_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferDx9Enable_bits 1 #define GFX8_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferDx9Enable_bits 1 #define GFX75_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferDx9Enable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_VS_ConstantBufferDx9Enable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferDx9Enable_start 68 #define GFX12_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferDx9Enable_start 68 #define GFX11_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferDx9Enable_start 68 #define GFX9_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferDx9Enable_start 68 #define GFX8_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferDx9Enable_start 68 #define GFX75_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferDx9Enable_start 68 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_VS_ConstantBufferDx9Enable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 68; case 120: return 68; case 110: return 68; case 90: return 68; case 80: return 68; case 75: return 68; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GATHER_CONSTANT_VS::Constant Buffer Dx9 Generate Stall */ #define GFX125_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferDx9GenerateStall_bits 1 #define GFX12_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferDx9GenerateStall_bits 1 #define GFX11_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferDx9GenerateStall_bits 1 #define GFX9_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferDx9GenerateStall_bits 1 #define GFX8_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferDx9GenerateStall_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_VS_ConstantBufferDx9GenerateStall_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferDx9GenerateStall_start 69 #define GFX12_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferDx9GenerateStall_start 69 #define GFX11_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferDx9GenerateStall_start 69 #define GFX9_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferDx9GenerateStall_start 69 #define GFX8_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferDx9GenerateStall_start 69 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_VS_ConstantBufferDx9GenerateStall_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 69; case 120: return 69; case 110: return 69; case 90: return 69; case 80: return 69; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GATHER_CONSTANT_VS::Constant Buffer Valid */ #define GFX125_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferValid_bits 16 #define GFX12_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferValid_bits 16 #define GFX11_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferValid_bits 16 #define GFX9_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferValid_bits 16 #define GFX8_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferValid_bits 16 #define GFX75_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferValid_bits 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_VS_ConstantBufferValid_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferValid_start 48 #define GFX12_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferValid_start 48 #define GFX11_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferValid_start 48 #define GFX9_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferValid_start 48 #define GFX8_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferValid_start 48 #define GFX75_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferValid_start 48 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_VS_ConstantBufferValid_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 48; case 120: return 48; case 110: return 48; case 90: return 48; case 80: return 48; case 75: return 48; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GATHER_CONSTANT_VS::DWord Length */ #define GFX125_3DSTATE_GATHER_CONSTANT_VS_DWordLength_bits 8 #define GFX12_3DSTATE_GATHER_CONSTANT_VS_DWordLength_bits 8 #define GFX11_3DSTATE_GATHER_CONSTANT_VS_DWordLength_bits 8 #define GFX9_3DSTATE_GATHER_CONSTANT_VS_DWordLength_bits 8 #define GFX8_3DSTATE_GATHER_CONSTANT_VS_DWordLength_bits 8 #define GFX75_3DSTATE_GATHER_CONSTANT_VS_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_VS_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GATHER_CONSTANT_VS_DWordLength_start 0 #define GFX12_3DSTATE_GATHER_CONSTANT_VS_DWordLength_start 0 #define GFX11_3DSTATE_GATHER_CONSTANT_VS_DWordLength_start 0 #define GFX9_3DSTATE_GATHER_CONSTANT_VS_DWordLength_start 0 #define GFX8_3DSTATE_GATHER_CONSTANT_VS_DWordLength_start 0 #define GFX75_3DSTATE_GATHER_CONSTANT_VS_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_VS_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GATHER_CONSTANT_VS::DX9 On-Die Register Read Enable */ #define GFX125_3DSTATE_GATHER_CONSTANT_VS_DX9OnDieRegisterReadEnable_bits 1 #define GFX12_3DSTATE_GATHER_CONSTANT_VS_DX9OnDieRegisterReadEnable_bits 1 #define GFX11_3DSTATE_GATHER_CONSTANT_VS_DX9OnDieRegisterReadEnable_bits 1 #define GFX9_3DSTATE_GATHER_CONSTANT_VS_DX9OnDieRegisterReadEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_VS_DX9OnDieRegisterReadEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GATHER_CONSTANT_VS_DX9OnDieRegisterReadEnable_start 32 #define GFX12_3DSTATE_GATHER_CONSTANT_VS_DX9OnDieRegisterReadEnable_start 32 #define GFX11_3DSTATE_GATHER_CONSTANT_VS_DX9OnDieRegisterReadEnable_start 32 #define GFX9_3DSTATE_GATHER_CONSTANT_VS_DX9OnDieRegisterReadEnable_start 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_VS_DX9OnDieRegisterReadEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GATHER_CONSTANT_VS::Gather Buffer Offset */ #define GFX125_3DSTATE_GATHER_CONSTANT_VS_GatherBufferOffset_bits 17 #define GFX12_3DSTATE_GATHER_CONSTANT_VS_GatherBufferOffset_bits 17 #define GFX11_3DSTATE_GATHER_CONSTANT_VS_GatherBufferOffset_bits 17 #define GFX9_3DSTATE_GATHER_CONSTANT_VS_GatherBufferOffset_bits 17 #define GFX8_3DSTATE_GATHER_CONSTANT_VS_GatherBufferOffset_bits 17 #define GFX75_3DSTATE_GATHER_CONSTANT_VS_GatherBufferOffset_bits 17 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_VS_GatherBufferOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 17; case 120: return 17; case 110: return 17; case 90: return 17; case 80: return 17; case 75: return 17; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GATHER_CONSTANT_VS_GatherBufferOffset_start 70 #define GFX12_3DSTATE_GATHER_CONSTANT_VS_GatherBufferOffset_start 70 #define GFX11_3DSTATE_GATHER_CONSTANT_VS_GatherBufferOffset_start 70 #define GFX9_3DSTATE_GATHER_CONSTANT_VS_GatherBufferOffset_start 70 #define GFX8_3DSTATE_GATHER_CONSTANT_VS_GatherBufferOffset_start 70 #define GFX75_3DSTATE_GATHER_CONSTANT_VS_GatherBufferOffset_start 70 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_VS_GatherBufferOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 70; case 120: return 70; case 110: return 70; case 90: return 70; case 80: return 70; case 75: return 70; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GATHER_CONSTANT_VS::On-Die Table */ #define GFX125_3DSTATE_GATHER_CONSTANT_VS_OnDieTable_bits 1 #define GFX12_3DSTATE_GATHER_CONSTANT_VS_OnDieTable_bits 1 #define GFX11_3DSTATE_GATHER_CONSTANT_VS_OnDieTable_bits 1 #define GFX9_3DSTATE_GATHER_CONSTANT_VS_OnDieTable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_VS_OnDieTable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GATHER_CONSTANT_VS_OnDieTable_start 67 #define GFX12_3DSTATE_GATHER_CONSTANT_VS_OnDieTable_start 67 #define GFX11_3DSTATE_GATHER_CONSTANT_VS_OnDieTable_start 67 #define GFX9_3DSTATE_GATHER_CONSTANT_VS_OnDieTable_start 67 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_VS_OnDieTable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 67; case 120: return 67; case 110: return 67; case 90: return 67; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GATHER_CONSTANT_VS::Update Gather Table Only */ #define GFX125_3DSTATE_GATHER_CONSTANT_VS_UpdateGatherTableOnly_bits 1 #define GFX12_3DSTATE_GATHER_CONSTANT_VS_UpdateGatherTableOnly_bits 1 #define GFX11_3DSTATE_GATHER_CONSTANT_VS_UpdateGatherTableOnly_bits 1 #define GFX9_3DSTATE_GATHER_CONSTANT_VS_UpdateGatherTableOnly_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_VS_UpdateGatherTableOnly_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GATHER_CONSTANT_VS_UpdateGatherTableOnly_start 33 #define GFX12_3DSTATE_GATHER_CONSTANT_VS_UpdateGatherTableOnly_start 33 #define GFX11_3DSTATE_GATHER_CONSTANT_VS_UpdateGatherTableOnly_start 33 #define GFX9_3DSTATE_GATHER_CONSTANT_VS_UpdateGatherTableOnly_start 33 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_CONSTANT_VS_UpdateGatherTableOnly_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 33; case 120: return 33; case 110: return 33; case 90: return 33; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GATHER_POOL_ALLOC */ #define GFX125_3DSTATE_GATHER_POOL_ALLOC_length 4 #define GFX12_3DSTATE_GATHER_POOL_ALLOC_length 4 #define GFX11_3DSTATE_GATHER_POOL_ALLOC_length 4 #define GFX9_3DSTATE_GATHER_POOL_ALLOC_length 4 #define GFX8_3DSTATE_GATHER_POOL_ALLOC_length 4 #define GFX75_3DSTATE_GATHER_POOL_ALLOC_length 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_POOL_ALLOC_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 3; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GATHER_POOL_ALLOC::3D Command Opcode */ #define GFX125_3DSTATE_GATHER_POOL_ALLOC_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_GATHER_POOL_ALLOC_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_GATHER_POOL_ALLOC_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_GATHER_POOL_ALLOC_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_GATHER_POOL_ALLOC_3DCommandOpcode_bits 3 #define GFX75_3DSTATE_GATHER_POOL_ALLOC_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_POOL_ALLOC_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GATHER_POOL_ALLOC_3DCommandOpcode_start 24 #define GFX12_3DSTATE_GATHER_POOL_ALLOC_3DCommandOpcode_start 24 #define GFX11_3DSTATE_GATHER_POOL_ALLOC_3DCommandOpcode_start 24 #define GFX9_3DSTATE_GATHER_POOL_ALLOC_3DCommandOpcode_start 24 #define GFX8_3DSTATE_GATHER_POOL_ALLOC_3DCommandOpcode_start 24 #define GFX75_3DSTATE_GATHER_POOL_ALLOC_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_POOL_ALLOC_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GATHER_POOL_ALLOC::3D Command Sub Opcode */ #define GFX125_3DSTATE_GATHER_POOL_ALLOC_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_GATHER_POOL_ALLOC_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_GATHER_POOL_ALLOC_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_GATHER_POOL_ALLOC_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_GATHER_POOL_ALLOC_3DCommandSubOpcode_bits 8 #define GFX75_3DSTATE_GATHER_POOL_ALLOC_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_POOL_ALLOC_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GATHER_POOL_ALLOC_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_GATHER_POOL_ALLOC_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_GATHER_POOL_ALLOC_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_GATHER_POOL_ALLOC_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_GATHER_POOL_ALLOC_3DCommandSubOpcode_start 16 #define GFX75_3DSTATE_GATHER_POOL_ALLOC_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_POOL_ALLOC_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GATHER_POOL_ALLOC::Command SubType */ #define GFX125_3DSTATE_GATHER_POOL_ALLOC_CommandSubType_bits 2 #define GFX12_3DSTATE_GATHER_POOL_ALLOC_CommandSubType_bits 2 #define GFX11_3DSTATE_GATHER_POOL_ALLOC_CommandSubType_bits 2 #define GFX9_3DSTATE_GATHER_POOL_ALLOC_CommandSubType_bits 2 #define GFX8_3DSTATE_GATHER_POOL_ALLOC_CommandSubType_bits 2 #define GFX75_3DSTATE_GATHER_POOL_ALLOC_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_POOL_ALLOC_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GATHER_POOL_ALLOC_CommandSubType_start 27 #define GFX12_3DSTATE_GATHER_POOL_ALLOC_CommandSubType_start 27 #define GFX11_3DSTATE_GATHER_POOL_ALLOC_CommandSubType_start 27 #define GFX9_3DSTATE_GATHER_POOL_ALLOC_CommandSubType_start 27 #define GFX8_3DSTATE_GATHER_POOL_ALLOC_CommandSubType_start 27 #define GFX75_3DSTATE_GATHER_POOL_ALLOC_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_POOL_ALLOC_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GATHER_POOL_ALLOC::Command Type */ #define GFX125_3DSTATE_GATHER_POOL_ALLOC_CommandType_bits 3 #define GFX12_3DSTATE_GATHER_POOL_ALLOC_CommandType_bits 3 #define GFX11_3DSTATE_GATHER_POOL_ALLOC_CommandType_bits 3 #define GFX9_3DSTATE_GATHER_POOL_ALLOC_CommandType_bits 3 #define GFX8_3DSTATE_GATHER_POOL_ALLOC_CommandType_bits 3 #define GFX75_3DSTATE_GATHER_POOL_ALLOC_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_POOL_ALLOC_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GATHER_POOL_ALLOC_CommandType_start 29 #define GFX12_3DSTATE_GATHER_POOL_ALLOC_CommandType_start 29 #define GFX11_3DSTATE_GATHER_POOL_ALLOC_CommandType_start 29 #define GFX9_3DSTATE_GATHER_POOL_ALLOC_CommandType_start 29 #define GFX8_3DSTATE_GATHER_POOL_ALLOC_CommandType_start 29 #define GFX75_3DSTATE_GATHER_POOL_ALLOC_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_POOL_ALLOC_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GATHER_POOL_ALLOC::DWord Length */ #define GFX125_3DSTATE_GATHER_POOL_ALLOC_DWordLength_bits 8 #define GFX12_3DSTATE_GATHER_POOL_ALLOC_DWordLength_bits 8 #define GFX11_3DSTATE_GATHER_POOL_ALLOC_DWordLength_bits 8 #define GFX9_3DSTATE_GATHER_POOL_ALLOC_DWordLength_bits 8 #define GFX8_3DSTATE_GATHER_POOL_ALLOC_DWordLength_bits 8 #define GFX75_3DSTATE_GATHER_POOL_ALLOC_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_POOL_ALLOC_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GATHER_POOL_ALLOC_DWordLength_start 0 #define GFX12_3DSTATE_GATHER_POOL_ALLOC_DWordLength_start 0 #define GFX11_3DSTATE_GATHER_POOL_ALLOC_DWordLength_start 0 #define GFX9_3DSTATE_GATHER_POOL_ALLOC_DWordLength_start 0 #define GFX8_3DSTATE_GATHER_POOL_ALLOC_DWordLength_start 0 #define GFX75_3DSTATE_GATHER_POOL_ALLOC_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_POOL_ALLOC_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GATHER_POOL_ALLOC::Gather Pool Base Address */ #define GFX125_3DSTATE_GATHER_POOL_ALLOC_GatherPoolBaseAddress_bits 52 #define GFX12_3DSTATE_GATHER_POOL_ALLOC_GatherPoolBaseAddress_bits 52 #define GFX11_3DSTATE_GATHER_POOL_ALLOC_GatherPoolBaseAddress_bits 52 #define GFX9_3DSTATE_GATHER_POOL_ALLOC_GatherPoolBaseAddress_bits 52 #define GFX8_3DSTATE_GATHER_POOL_ALLOC_GatherPoolBaseAddress_bits 52 #define GFX75_3DSTATE_GATHER_POOL_ALLOC_GatherPoolBaseAddress_bits 20 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_POOL_ALLOC_GatherPoolBaseAddress_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 52; case 120: return 52; case 110: return 52; case 90: return 52; case 80: return 52; case 75: return 20; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GATHER_POOL_ALLOC_GatherPoolBaseAddress_start 44 #define GFX12_3DSTATE_GATHER_POOL_ALLOC_GatherPoolBaseAddress_start 44 #define GFX11_3DSTATE_GATHER_POOL_ALLOC_GatherPoolBaseAddress_start 44 #define GFX9_3DSTATE_GATHER_POOL_ALLOC_GatherPoolBaseAddress_start 44 #define GFX8_3DSTATE_GATHER_POOL_ALLOC_GatherPoolBaseAddress_start 44 #define GFX75_3DSTATE_GATHER_POOL_ALLOC_GatherPoolBaseAddress_start 44 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_POOL_ALLOC_GatherPoolBaseAddress_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 44; case 120: return 44; case 110: return 44; case 90: return 44; case 80: return 44; case 75: return 44; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GATHER_POOL_ALLOC::Gather Pool Buffer Size */ #define GFX125_3DSTATE_GATHER_POOL_ALLOC_GatherPoolBufferSize_bits 20 #define GFX12_3DSTATE_GATHER_POOL_ALLOC_GatherPoolBufferSize_bits 20 #define GFX11_3DSTATE_GATHER_POOL_ALLOC_GatherPoolBufferSize_bits 20 #define GFX9_3DSTATE_GATHER_POOL_ALLOC_GatherPoolBufferSize_bits 20 #define GFX8_3DSTATE_GATHER_POOL_ALLOC_GatherPoolBufferSize_bits 20 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_POOL_ALLOC_GatherPoolBufferSize_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 20; case 120: return 20; case 110: return 20; case 90: return 20; case 80: return 20; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GATHER_POOL_ALLOC_GatherPoolBufferSize_start 108 #define GFX12_3DSTATE_GATHER_POOL_ALLOC_GatherPoolBufferSize_start 108 #define GFX11_3DSTATE_GATHER_POOL_ALLOC_GatherPoolBufferSize_start 108 #define GFX9_3DSTATE_GATHER_POOL_ALLOC_GatherPoolBufferSize_start 108 #define GFX8_3DSTATE_GATHER_POOL_ALLOC_GatherPoolBufferSize_start 108 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_POOL_ALLOC_GatherPoolBufferSize_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 108; case 120: return 108; case 110: return 108; case 90: return 108; case 80: return 108; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GATHER_POOL_ALLOC::Gather Pool Enable */ #define GFX125_3DSTATE_GATHER_POOL_ALLOC_GatherPoolEnable_bits 1 #define GFX12_3DSTATE_GATHER_POOL_ALLOC_GatherPoolEnable_bits 1 #define GFX11_3DSTATE_GATHER_POOL_ALLOC_GatherPoolEnable_bits 1 #define GFX9_3DSTATE_GATHER_POOL_ALLOC_GatherPoolEnable_bits 1 #define GFX8_3DSTATE_GATHER_POOL_ALLOC_GatherPoolEnable_bits 1 #define GFX75_3DSTATE_GATHER_POOL_ALLOC_GatherPoolEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_POOL_ALLOC_GatherPoolEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GATHER_POOL_ALLOC_GatherPoolEnable_start 43 #define GFX12_3DSTATE_GATHER_POOL_ALLOC_GatherPoolEnable_start 43 #define GFX11_3DSTATE_GATHER_POOL_ALLOC_GatherPoolEnable_start 43 #define GFX9_3DSTATE_GATHER_POOL_ALLOC_GatherPoolEnable_start 43 #define GFX8_3DSTATE_GATHER_POOL_ALLOC_GatherPoolEnable_start 43 #define GFX75_3DSTATE_GATHER_POOL_ALLOC_GatherPoolEnable_start 43 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_POOL_ALLOC_GatherPoolEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 43; case 120: return 43; case 110: return 43; case 90: return 43; case 80: return 43; case 75: return 43; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GATHER_POOL_ALLOC::Gather Pool Upper Bound */ #define GFX75_3DSTATE_GATHER_POOL_ALLOC_GatherPoolUpperBound_bits 20 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_POOL_ALLOC_GatherPoolUpperBound_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 20; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_GATHER_POOL_ALLOC_GatherPoolUpperBound_start 76 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_POOL_ALLOC_GatherPoolUpperBound_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 76; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GATHER_POOL_ALLOC::MOCS */ #define GFX125_3DSTATE_GATHER_POOL_ALLOC_MOCS_bits 7 #define GFX12_3DSTATE_GATHER_POOL_ALLOC_MOCS_bits 7 #define GFX11_3DSTATE_GATHER_POOL_ALLOC_MOCS_bits 7 #define GFX9_3DSTATE_GATHER_POOL_ALLOC_MOCS_bits 7 #define GFX8_3DSTATE_GATHER_POOL_ALLOC_MOCS_bits 7 #define GFX75_3DSTATE_GATHER_POOL_ALLOC_MOCS_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_POOL_ALLOC_MOCS_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 7; case 120: return 7; case 110: return 7; case 90: return 7; case 80: return 7; case 75: return 4; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GATHER_POOL_ALLOC_MOCS_start 32 #define GFX12_3DSTATE_GATHER_POOL_ALLOC_MOCS_start 32 #define GFX11_3DSTATE_GATHER_POOL_ALLOC_MOCS_start 32 #define GFX9_3DSTATE_GATHER_POOL_ALLOC_MOCS_start 32 #define GFX8_3DSTATE_GATHER_POOL_ALLOC_MOCS_start 32 #define GFX75_3DSTATE_GATHER_POOL_ALLOC_MOCS_start 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GATHER_POOL_ALLOC_MOCS_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP */ #define GFX5_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_length 2 #define GFX45_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_length 2 #define GFX4_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_length 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 2; case 45: return 2; case 40: return 2; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP::3D Command Opcode */ #define GFX5_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_3DCommandOpcode_bits 3 #define GFX45_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_3DCommandOpcode_bits 3 #define GFX4_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX5_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_3DCommandOpcode_start 24 #define GFX45_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_3DCommandOpcode_start 24 #define GFX4_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 24; case 45: return 24; case 40: return 24; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP::3D Command Sub Opcode */ #define GFX5_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_3DCommandSubOpcode_bits 8 #define GFX45_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_3DCommandSubOpcode_bits 8 #define GFX4_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 8; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } #define GFX5_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_3DCommandSubOpcode_start 16 #define GFX45_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_3DCommandSubOpcode_start 16 #define GFX4_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 16; case 45: return 16; case 40: return 16; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP::Command SubType */ #define GFX5_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_CommandSubType_bits 2 #define GFX45_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_CommandSubType_bits 2 #define GFX4_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 2; case 45: return 2; case 40: return 2; default: unreachable("Invalid hardware generation"); } } #define GFX5_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_CommandSubType_start 27 #define GFX45_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_CommandSubType_start 27 #define GFX4_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 27; case 45: return 27; case 40: return 27; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP::Command Type */ #define GFX5_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_CommandType_bits 3 #define GFX45_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_CommandType_bits 3 #define GFX4_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX5_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_CommandType_start 29 #define GFX45_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_CommandType_start 29 #define GFX4_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 29; case 45: return 29; case 40: return 29; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP::DWord Length */ #define GFX5_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_DWordLength_bits 8 #define GFX45_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_DWordLength_bits 8 #define GFX4_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 8; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } #define GFX5_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_DWordLength_start 0 #define GFX45_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_DWordLength_start 0 #define GFX4_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP::Global Depth Offset Clamp */ #define GFX5_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_GlobalDepthOffsetClamp_bits 32 #define GFX45_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_GlobalDepthOffsetClamp_bits 32 #define GFX4_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_GlobalDepthOffsetClamp_bits 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_GlobalDepthOffsetClamp_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 32; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } #define GFX5_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_GlobalDepthOffsetClamp_start 32 #define GFX45_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_GlobalDepthOffsetClamp_start 32 #define GFX4_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_GlobalDepthOffsetClamp_start 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_GlobalDepthOffsetClamp_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 32; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GS */ #define GFX125_3DSTATE_GS_length 10 #define GFX12_3DSTATE_GS_length 10 #define GFX11_3DSTATE_GS_length 10 #define GFX9_3DSTATE_GS_length 10 #define GFX8_3DSTATE_GS_length 10 #define GFX75_3DSTATE_GS_length 7 #define GFX7_3DSTATE_GS_length 7 #define GFX6_3DSTATE_GS_length 7 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 10; case 120: return 10; case 110: return 10; case 90: return 10; case 80: return 10; case 75: return 7; case 70: return 7; case 60: return 7; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GS::3D Command Opcode */ #define GFX125_3DSTATE_GS_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_GS_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_GS_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_GS_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_GS_3DCommandOpcode_bits 3 #define GFX75_3DSTATE_GS_3DCommandOpcode_bits 3 #define GFX7_3DSTATE_GS_3DCommandOpcode_bits 3 #define GFX6_3DSTATE_GS_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GS_3DCommandOpcode_start 24 #define GFX12_3DSTATE_GS_3DCommandOpcode_start 24 #define GFX11_3DSTATE_GS_3DCommandOpcode_start 24 #define GFX9_3DSTATE_GS_3DCommandOpcode_start 24 #define GFX8_3DSTATE_GS_3DCommandOpcode_start 24 #define GFX75_3DSTATE_GS_3DCommandOpcode_start 24 #define GFX7_3DSTATE_GS_3DCommandOpcode_start 24 #define GFX6_3DSTATE_GS_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 24; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GS::3D Command Sub Opcode */ #define GFX125_3DSTATE_GS_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_GS_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_GS_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_GS_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_GS_3DCommandSubOpcode_bits 8 #define GFX75_3DSTATE_GS_3DCommandSubOpcode_bits 8 #define GFX7_3DSTATE_GS_3DCommandSubOpcode_bits 8 #define GFX6_3DSTATE_GS_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GS_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_GS_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_GS_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_GS_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_GS_3DCommandSubOpcode_start 16 #define GFX75_3DSTATE_GS_3DCommandSubOpcode_start 16 #define GFX7_3DSTATE_GS_3DCommandSubOpcode_start 16 #define GFX6_3DSTATE_GS_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 16; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GS::Accesses UAV */ #define GFX125_3DSTATE_GS_AccessesUAV_bits 1 #define GFX12_3DSTATE_GS_AccessesUAV_bits 1 #define GFX11_3DSTATE_GS_AccessesUAV_bits 1 #define GFX9_3DSTATE_GS_AccessesUAV_bits 1 #define GFX8_3DSTATE_GS_AccessesUAV_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_AccessesUAV_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GS_AccessesUAV_start 108 #define GFX12_3DSTATE_GS_AccessesUAV_start 108 #define GFX11_3DSTATE_GS_AccessesUAV_start 108 #define GFX9_3DSTATE_GS_AccessesUAV_start 108 #define GFX8_3DSTATE_GS_AccessesUAV_start 108 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_AccessesUAV_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 108; case 120: return 108; case 110: return 108; case 90: return 108; case 80: return 108; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GS::Binding Table Entry Count */ #define GFX125_3DSTATE_GS_BindingTableEntryCount_bits 8 #define GFX12_3DSTATE_GS_BindingTableEntryCount_bits 8 #define GFX11_3DSTATE_GS_BindingTableEntryCount_bits 8 #define GFX9_3DSTATE_GS_BindingTableEntryCount_bits 8 #define GFX8_3DSTATE_GS_BindingTableEntryCount_bits 8 #define GFX75_3DSTATE_GS_BindingTableEntryCount_bits 8 #define GFX7_3DSTATE_GS_BindingTableEntryCount_bits 8 #define GFX6_3DSTATE_GS_BindingTableEntryCount_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_BindingTableEntryCount_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GS_BindingTableEntryCount_start 114 #define GFX12_3DSTATE_GS_BindingTableEntryCount_start 114 #define GFX11_3DSTATE_GS_BindingTableEntryCount_start 114 #define GFX9_3DSTATE_GS_BindingTableEntryCount_start 114 #define GFX8_3DSTATE_GS_BindingTableEntryCount_start 114 #define GFX75_3DSTATE_GS_BindingTableEntryCount_start 82 #define GFX7_3DSTATE_GS_BindingTableEntryCount_start 82 #define GFX6_3DSTATE_GS_BindingTableEntryCount_start 82 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_BindingTableEntryCount_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 114; case 120: return 114; case 110: return 114; case 90: return 114; case 80: return 114; case 75: return 82; case 70: return 82; case 60: return 82; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GS::Command SubType */ #define GFX125_3DSTATE_GS_CommandSubType_bits 2 #define GFX12_3DSTATE_GS_CommandSubType_bits 2 #define GFX11_3DSTATE_GS_CommandSubType_bits 2 #define GFX9_3DSTATE_GS_CommandSubType_bits 2 #define GFX8_3DSTATE_GS_CommandSubType_bits 2 #define GFX75_3DSTATE_GS_CommandSubType_bits 2 #define GFX7_3DSTATE_GS_CommandSubType_bits 2 #define GFX6_3DSTATE_GS_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GS_CommandSubType_start 27 #define GFX12_3DSTATE_GS_CommandSubType_start 27 #define GFX11_3DSTATE_GS_CommandSubType_start 27 #define GFX9_3DSTATE_GS_CommandSubType_start 27 #define GFX8_3DSTATE_GS_CommandSubType_start 27 #define GFX75_3DSTATE_GS_CommandSubType_start 27 #define GFX7_3DSTATE_GS_CommandSubType_start 27 #define GFX6_3DSTATE_GS_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 27; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GS::Command Type */ #define GFX125_3DSTATE_GS_CommandType_bits 3 #define GFX12_3DSTATE_GS_CommandType_bits 3 #define GFX11_3DSTATE_GS_CommandType_bits 3 #define GFX9_3DSTATE_GS_CommandType_bits 3 #define GFX8_3DSTATE_GS_CommandType_bits 3 #define GFX75_3DSTATE_GS_CommandType_bits 3 #define GFX7_3DSTATE_GS_CommandType_bits 3 #define GFX6_3DSTATE_GS_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GS_CommandType_start 29 #define GFX12_3DSTATE_GS_CommandType_start 29 #define GFX11_3DSTATE_GS_CommandType_start 29 #define GFX9_3DSTATE_GS_CommandType_start 29 #define GFX8_3DSTATE_GS_CommandType_start 29 #define GFX75_3DSTATE_GS_CommandType_start 29 #define GFX7_3DSTATE_GS_CommandType_start 29 #define GFX6_3DSTATE_GS_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 29; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GS::Control Data Format */ #define GFX125_3DSTATE_GS_ControlDataFormat_bits 1 #define GFX12_3DSTATE_GS_ControlDataFormat_bits 1 #define GFX11_3DSTATE_GS_ControlDataFormat_bits 1 #define GFX9_3DSTATE_GS_ControlDataFormat_bits 1 #define GFX8_3DSTATE_GS_ControlDataFormat_bits 1 #define GFX75_3DSTATE_GS_ControlDataFormat_bits 1 #define GFX7_3DSTATE_GS_ControlDataFormat_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_ControlDataFormat_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GS_ControlDataFormat_start 287 #define GFX12_3DSTATE_GS_ControlDataFormat_start 287 #define GFX11_3DSTATE_GS_ControlDataFormat_start 287 #define GFX9_3DSTATE_GS_ControlDataFormat_start 287 #define GFX8_3DSTATE_GS_ControlDataFormat_start 287 #define GFX75_3DSTATE_GS_ControlDataFormat_start 223 #define GFX7_3DSTATE_GS_ControlDataFormat_start 184 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_ControlDataFormat_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 287; case 120: return 287; case 110: return 287; case 90: return 287; case 80: return 287; case 75: return 223; case 70: return 184; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GS::Control Data Header Size */ #define GFX125_3DSTATE_GS_ControlDataHeaderSize_bits 4 #define GFX12_3DSTATE_GS_ControlDataHeaderSize_bits 4 #define GFX11_3DSTATE_GS_ControlDataHeaderSize_bits 4 #define GFX9_3DSTATE_GS_ControlDataHeaderSize_bits 4 #define GFX8_3DSTATE_GS_ControlDataHeaderSize_bits 4 #define GFX75_3DSTATE_GS_ControlDataHeaderSize_bits 4 #define GFX7_3DSTATE_GS_ControlDataHeaderSize_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_ControlDataHeaderSize_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 4; case 70: return 4; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GS_ControlDataHeaderSize_start 244 #define GFX12_3DSTATE_GS_ControlDataHeaderSize_start 244 #define GFX11_3DSTATE_GS_ControlDataHeaderSize_start 244 #define GFX9_3DSTATE_GS_ControlDataHeaderSize_start 244 #define GFX8_3DSTATE_GS_ControlDataHeaderSize_start 244 #define GFX75_3DSTATE_GS_ControlDataHeaderSize_start 180 #define GFX7_3DSTATE_GS_ControlDataHeaderSize_start 180 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_ControlDataHeaderSize_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 244; case 120: return 244; case 110: return 244; case 90: return 244; case 80: return 244; case 75: return 180; case 70: return 180; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GS::DWord Length */ #define GFX125_3DSTATE_GS_DWordLength_bits 8 #define GFX12_3DSTATE_GS_DWordLength_bits 8 #define GFX11_3DSTATE_GS_DWordLength_bits 8 #define GFX9_3DSTATE_GS_DWordLength_bits 8 #define GFX8_3DSTATE_GS_DWordLength_bits 8 #define GFX75_3DSTATE_GS_DWordLength_bits 8 #define GFX7_3DSTATE_GS_DWordLength_bits 8 #define GFX6_3DSTATE_GS_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GS_DWordLength_start 0 #define GFX12_3DSTATE_GS_DWordLength_start 0 #define GFX11_3DSTATE_GS_DWordLength_start 0 #define GFX9_3DSTATE_GS_DWordLength_start 0 #define GFX8_3DSTATE_GS_DWordLength_start 0 #define GFX75_3DSTATE_GS_DWordLength_start 0 #define GFX7_3DSTATE_GS_DWordLength_start 0 #define GFX6_3DSTATE_GS_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GS::Default StreamID */ #define GFX75_3DSTATE_GS_DefaultStreamID_bits 2 #define GFX7_3DSTATE_GS_DefaultStreamID_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_DefaultStreamID_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_GS_DefaultStreamID_start 173 #define GFX7_3DSTATE_GS_DefaultStreamID_start 173 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_DefaultStreamID_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 173; case 70: return 173; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GS::Default Stream Id */ #define GFX125_3DSTATE_GS_DefaultStreamId_bits 2 #define GFX12_3DSTATE_GS_DefaultStreamId_bits 2 #define GFX11_3DSTATE_GS_DefaultStreamId_bits 2 #define GFX9_3DSTATE_GS_DefaultStreamId_bits 2 #define GFX8_3DSTATE_GS_DefaultStreamId_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_DefaultStreamId_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GS_DefaultStreamId_start 237 #define GFX12_3DSTATE_GS_DefaultStreamId_start 237 #define GFX11_3DSTATE_GS_DefaultStreamId_start 237 #define GFX9_3DSTATE_GS_DefaultStreamId_start 237 #define GFX8_3DSTATE_GS_DefaultStreamId_start 237 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_DefaultStreamId_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 237; case 120: return 237; case 110: return 237; case 90: return 237; case 80: return 237; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GS::Discard Adjacency */ #define GFX125_3DSTATE_GS_DiscardAdjacency_bits 1 #define GFX12_3DSTATE_GS_DiscardAdjacency_bits 1 #define GFX11_3DSTATE_GS_DiscardAdjacency_bits 1 #define GFX9_3DSTATE_GS_DiscardAdjacency_bits 1 #define GFX8_3DSTATE_GS_DiscardAdjacency_bits 1 #define GFX75_3DSTATE_GS_DiscardAdjacency_bits 1 #define GFX7_3DSTATE_GS_DiscardAdjacency_bits 1 #define GFX6_3DSTATE_GS_DiscardAdjacency_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_DiscardAdjacency_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GS_DiscardAdjacency_start 225 #define GFX12_3DSTATE_GS_DiscardAdjacency_start 225 #define GFX11_3DSTATE_GS_DiscardAdjacency_start 225 #define GFX9_3DSTATE_GS_DiscardAdjacency_start 225 #define GFX8_3DSTATE_GS_DiscardAdjacency_start 225 #define GFX75_3DSTATE_GS_DiscardAdjacency_start 161 #define GFX7_3DSTATE_GS_DiscardAdjacency_start 161 #define GFX6_3DSTATE_GS_DiscardAdjacency_start 221 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_DiscardAdjacency_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 225; case 120: return 225; case 110: return 225; case 90: return 225; case 80: return 225; case 75: return 161; case 70: return 161; case 60: return 221; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GS::Dispatch GRF Start Register For URB Data */ #define GFX125_3DSTATE_GS_DispatchGRFStartRegisterForURBData_bits 4 #define GFX12_3DSTATE_GS_DispatchGRFStartRegisterForURBData_bits 4 #define GFX11_3DSTATE_GS_DispatchGRFStartRegisterForURBData_bits 4 #define GFX9_3DSTATE_GS_DispatchGRFStartRegisterForURBData_bits 4 #define GFX8_3DSTATE_GS_DispatchGRFStartRegisterForURBData_bits 4 #define GFX75_3DSTATE_GS_DispatchGRFStartRegisterForURBData_bits 4 #define GFX7_3DSTATE_GS_DispatchGRFStartRegisterForURBData_bits 4 #define GFX6_3DSTATE_GS_DispatchGRFStartRegisterForURBData_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_DispatchGRFStartRegisterForURBData_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 4; case 70: return 4; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GS_DispatchGRFStartRegisterForURBData_start 192 #define GFX12_3DSTATE_GS_DispatchGRFStartRegisterForURBData_start 192 #define GFX11_3DSTATE_GS_DispatchGRFStartRegisterForURBData_start 192 #define GFX9_3DSTATE_GS_DispatchGRFStartRegisterForURBData_start 192 #define GFX8_3DSTATE_GS_DispatchGRFStartRegisterForURBData_start 192 #define GFX75_3DSTATE_GS_DispatchGRFStartRegisterForURBData_start 128 #define GFX7_3DSTATE_GS_DispatchGRFStartRegisterForURBData_start 128 #define GFX6_3DSTATE_GS_DispatchGRFStartRegisterForURBData_start 128 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_DispatchGRFStartRegisterForURBData_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 192; case 120: return 192; case 110: return 192; case 90: return 192; case 80: return 192; case 75: return 128; case 70: return 128; case 60: return 128; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GS::Dispatch GRF Start Register For URB Data [5:4] */ #define GFX125_3DSTATE_GS_DispatchGRFStartRegisterForURBData54_bits 2 #define GFX12_3DSTATE_GS_DispatchGRFStartRegisterForURBData54_bits 2 #define GFX11_3DSTATE_GS_DispatchGRFStartRegisterForURBData54_bits 2 #define GFX9_3DSTATE_GS_DispatchGRFStartRegisterForURBData54_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_DispatchGRFStartRegisterForURBData54_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GS_DispatchGRFStartRegisterForURBData54_start 221 #define GFX12_3DSTATE_GS_DispatchGRFStartRegisterForURBData54_start 221 #define GFX11_3DSTATE_GS_DispatchGRFStartRegisterForURBData54_start 221 #define GFX9_3DSTATE_GS_DispatchGRFStartRegisterForURBData54_start 221 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_DispatchGRFStartRegisterForURBData54_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 221; case 120: return 221; case 110: return 221; case 90: return 221; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GS::Dispatch Mode */ #define GFX125_3DSTATE_GS_DispatchMode_bits 2 #define GFX12_3DSTATE_GS_DispatchMode_bits 2 #define GFX11_3DSTATE_GS_DispatchMode_bits 2 #define GFX9_3DSTATE_GS_DispatchMode_bits 2 #define GFX8_3DSTATE_GS_DispatchMode_bits 2 #define GFX75_3DSTATE_GS_DispatchMode_bits 2 #define GFX7_3DSTATE_GS_DispatchMode_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_DispatchMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GS_DispatchMode_start 235 #define GFX12_3DSTATE_GS_DispatchMode_start 235 #define GFX11_3DSTATE_GS_DispatchMode_start 235 #define GFX9_3DSTATE_GS_DispatchMode_start 235 #define GFX8_3DSTATE_GS_DispatchMode_start 235 #define GFX75_3DSTATE_GS_DispatchMode_start 171 #define GFX7_3DSTATE_GS_DispatchMode_start 171 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_DispatchMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 235; case 120: return 235; case 110: return 235; case 90: return 235; case 80: return 235; case 75: return 171; case 70: return 171; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GS::Enable */ #define GFX125_3DSTATE_GS_Enable_bits 1 #define GFX12_3DSTATE_GS_Enable_bits 1 #define GFX11_3DSTATE_GS_Enable_bits 1 #define GFX9_3DSTATE_GS_Enable_bits 1 #define GFX8_3DSTATE_GS_Enable_bits 1 #define GFX75_3DSTATE_GS_Enable_bits 1 #define GFX7_3DSTATE_GS_Enable_bits 1 #define GFX6_3DSTATE_GS_Enable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_Enable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GS_Enable_start 224 #define GFX12_3DSTATE_GS_Enable_start 224 #define GFX11_3DSTATE_GS_Enable_start 224 #define GFX9_3DSTATE_GS_Enable_start 224 #define GFX8_3DSTATE_GS_Enable_start 224 #define GFX75_3DSTATE_GS_Enable_start 160 #define GFX7_3DSTATE_GS_Enable_start 160 #define GFX6_3DSTATE_GS_Enable_start 207 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_Enable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 224; case 120: return 224; case 110: return 224; case 90: return 224; case 80: return 224; case 75: return 160; case 70: return 160; case 60: return 207; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GS::Expected Vertex Count */ #define GFX125_3DSTATE_GS_ExpectedVertexCount_bits 6 #define GFX12_3DSTATE_GS_ExpectedVertexCount_bits 6 #define GFX11_3DSTATE_GS_ExpectedVertexCount_bits 6 #define GFX9_3DSTATE_GS_ExpectedVertexCount_bits 6 #define GFX8_3DSTATE_GS_ExpectedVertexCount_bits 6 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_ExpectedVertexCount_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GS_ExpectedVertexCount_start 96 #define GFX12_3DSTATE_GS_ExpectedVertexCount_start 96 #define GFX11_3DSTATE_GS_ExpectedVertexCount_start 96 #define GFX9_3DSTATE_GS_ExpectedVertexCount_start 96 #define GFX8_3DSTATE_GS_ExpectedVertexCount_start 96 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_ExpectedVertexCount_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 96; case 120: return 96; case 110: return 96; case 90: return 96; case 80: return 96; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GS::Floating Point Mode */ #define GFX125_3DSTATE_GS_FloatingPointMode_bits 1 #define GFX12_3DSTATE_GS_FloatingPointMode_bits 1 #define GFX11_3DSTATE_GS_FloatingPointMode_bits 1 #define GFX9_3DSTATE_GS_FloatingPointMode_bits 1 #define GFX8_3DSTATE_GS_FloatingPointMode_bits 1 #define GFX75_3DSTATE_GS_FloatingPointMode_bits 1 #define GFX7_3DSTATE_GS_FloatingPointMode_bits 1 #define GFX6_3DSTATE_GS_FloatingPointMode_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_FloatingPointMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GS_FloatingPointMode_start 112 #define GFX12_3DSTATE_GS_FloatingPointMode_start 112 #define GFX11_3DSTATE_GS_FloatingPointMode_start 112 #define GFX9_3DSTATE_GS_FloatingPointMode_start 112 #define GFX8_3DSTATE_GS_FloatingPointMode_start 112 #define GFX75_3DSTATE_GS_FloatingPointMode_start 80 #define GFX7_3DSTATE_GS_FloatingPointMode_start 80 #define GFX6_3DSTATE_GS_FloatingPointMode_start 80 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_FloatingPointMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 112; case 120: return 112; case 110: return 112; case 90: return 112; case 80: return 112; case 75: return 80; case 70: return 80; case 60: return 80; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GS::GS Invocations Increment Value */ #define GFX75_3DSTATE_GS_GSInvocationsIncrementValue_bits 5 #define GFX7_3DSTATE_GS_GSInvocationsIncrementValue_bits 5 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_GSInvocationsIncrementValue_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 5; case 70: return 5; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_GS_GSInvocationsIncrementValue_start 165 #define GFX7_3DSTATE_GS_GSInvocationsIncrementValue_start 165 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_GSInvocationsIncrementValue_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 165; case 70: return 165; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GS::GS accesses UAV */ #define GFX75_3DSTATE_GS_GSaccessesUAV_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_GSaccessesUAV_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_GS_GSaccessesUAV_start 76 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_GSaccessesUAV_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 76; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GS::Hint */ #define GFX125_3DSTATE_GS_Hint_bits 1 #define GFX12_3DSTATE_GS_Hint_bits 1 #define GFX11_3DSTATE_GS_Hint_bits 1 #define GFX9_3DSTATE_GS_Hint_bits 1 #define GFX8_3DSTATE_GS_Hint_bits 1 #define GFX75_3DSTATE_GS_Hint_bits 1 #define GFX7_3DSTATE_GS_Hint_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_Hint_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GS_Hint_start 227 #define GFX12_3DSTATE_GS_Hint_start 227 #define GFX11_3DSTATE_GS_Hint_start 227 #define GFX9_3DSTATE_GS_Hint_start 227 #define GFX8_3DSTATE_GS_Hint_start 227 #define GFX75_3DSTATE_GS_Hint_start 163 #define GFX7_3DSTATE_GS_Hint_start 163 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_Hint_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 227; case 120: return 227; case 110: return 227; case 90: return 227; case 80: return 227; case 75: return 163; case 70: return 163; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GS::Illegal Opcode Exception Enable */ #define GFX125_3DSTATE_GS_IllegalOpcodeExceptionEnable_bits 1 #define GFX12_3DSTATE_GS_IllegalOpcodeExceptionEnable_bits 1 #define GFX11_3DSTATE_GS_IllegalOpcodeExceptionEnable_bits 1 #define GFX9_3DSTATE_GS_IllegalOpcodeExceptionEnable_bits 1 #define GFX8_3DSTATE_GS_IllegalOpcodeExceptionEnable_bits 1 #define GFX75_3DSTATE_GS_IllegalOpcodeExceptionEnable_bits 1 #define GFX7_3DSTATE_GS_IllegalOpcodeExceptionEnable_bits 1 #define GFX6_3DSTATE_GS_IllegalOpcodeExceptionEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_IllegalOpcodeExceptionEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GS_IllegalOpcodeExceptionEnable_start 109 #define GFX12_3DSTATE_GS_IllegalOpcodeExceptionEnable_start 109 #define GFX11_3DSTATE_GS_IllegalOpcodeExceptionEnable_start 109 #define GFX9_3DSTATE_GS_IllegalOpcodeExceptionEnable_start 109 #define GFX8_3DSTATE_GS_IllegalOpcodeExceptionEnable_start 109 #define GFX75_3DSTATE_GS_IllegalOpcodeExceptionEnable_start 77 #define GFX7_3DSTATE_GS_IllegalOpcodeExceptionEnable_start 77 #define GFX6_3DSTATE_GS_IllegalOpcodeExceptionEnable_start 77 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_IllegalOpcodeExceptionEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 109; case 120: return 109; case 110: return 109; case 90: return 109; case 80: return 109; case 75: return 77; case 70: return 77; case 60: return 77; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GS::Include Primitive ID */ #define GFX125_3DSTATE_GS_IncludePrimitiveID_bits 1 #define GFX12_3DSTATE_GS_IncludePrimitiveID_bits 1 #define GFX11_3DSTATE_GS_IncludePrimitiveID_bits 1 #define GFX9_3DSTATE_GS_IncludePrimitiveID_bits 1 #define GFX8_3DSTATE_GS_IncludePrimitiveID_bits 1 #define GFX75_3DSTATE_GS_IncludePrimitiveID_bits 1 #define GFX7_3DSTATE_GS_IncludePrimitiveID_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_IncludePrimitiveID_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GS_IncludePrimitiveID_start 228 #define GFX12_3DSTATE_GS_IncludePrimitiveID_start 228 #define GFX11_3DSTATE_GS_IncludePrimitiveID_start 228 #define GFX9_3DSTATE_GS_IncludePrimitiveID_start 228 #define GFX8_3DSTATE_GS_IncludePrimitiveID_start 228 #define GFX75_3DSTATE_GS_IncludePrimitiveID_start 164 #define GFX7_3DSTATE_GS_IncludePrimitiveID_start 164 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_IncludePrimitiveID_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 228; case 120: return 228; case 110: return 228; case 90: return 228; case 80: return 228; case 75: return 164; case 70: return 164; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GS::Include Vertex Handles */ #define GFX125_3DSTATE_GS_IncludeVertexHandles_bits 1 #define GFX12_3DSTATE_GS_IncludeVertexHandles_bits 1 #define GFX11_3DSTATE_GS_IncludeVertexHandles_bits 1 #define GFX9_3DSTATE_GS_IncludeVertexHandles_bits 1 #define GFX8_3DSTATE_GS_IncludeVertexHandles_bits 1 #define GFX75_3DSTATE_GS_IncludeVertexHandles_bits 1 #define GFX7_3DSTATE_GS_IncludeVertexHandles_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_IncludeVertexHandles_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GS_IncludeVertexHandles_start 202 #define GFX12_3DSTATE_GS_IncludeVertexHandles_start 202 #define GFX11_3DSTATE_GS_IncludeVertexHandles_start 202 #define GFX9_3DSTATE_GS_IncludeVertexHandles_start 202 #define GFX8_3DSTATE_GS_IncludeVertexHandles_start 202 #define GFX75_3DSTATE_GS_IncludeVertexHandles_start 138 #define GFX7_3DSTATE_GS_IncludeVertexHandles_start 138 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_IncludeVertexHandles_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 202; case 120: return 202; case 110: return 202; case 90: return 202; case 80: return 202; case 75: return 138; case 70: return 138; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GS::Instance Control */ #define GFX125_3DSTATE_GS_InstanceControl_bits 5 #define GFX12_3DSTATE_GS_InstanceControl_bits 5 #define GFX11_3DSTATE_GS_InstanceControl_bits 5 #define GFX9_3DSTATE_GS_InstanceControl_bits 5 #define GFX8_3DSTATE_GS_InstanceControl_bits 5 #define GFX75_3DSTATE_GS_InstanceControl_bits 5 #define GFX7_3DSTATE_GS_InstanceControl_bits 5 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_InstanceControl_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 5; case 110: return 5; case 90: return 5; case 80: return 5; case 75: return 5; case 70: return 5; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GS_InstanceControl_start 239 #define GFX12_3DSTATE_GS_InstanceControl_start 239 #define GFX11_3DSTATE_GS_InstanceControl_start 239 #define GFX9_3DSTATE_GS_InstanceControl_start 239 #define GFX8_3DSTATE_GS_InstanceControl_start 239 #define GFX75_3DSTATE_GS_InstanceControl_start 175 #define GFX7_3DSTATE_GS_InstanceControl_start 175 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_InstanceControl_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 239; case 120: return 239; case 110: return 239; case 90: return 239; case 80: return 239; case 75: return 175; case 70: return 175; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GS::Invocations Increment Value */ #define GFX125_3DSTATE_GS_InvocationsIncrementValue_bits 5 #define GFX12_3DSTATE_GS_InvocationsIncrementValue_bits 5 #define GFX11_3DSTATE_GS_InvocationsIncrementValue_bits 5 #define GFX9_3DSTATE_GS_InvocationsIncrementValue_bits 5 #define GFX8_3DSTATE_GS_InvocationsIncrementValue_bits 5 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_InvocationsIncrementValue_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 5; case 110: return 5; case 90: return 5; case 80: return 5; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GS_InvocationsIncrementValue_start 229 #define GFX12_3DSTATE_GS_InvocationsIncrementValue_start 229 #define GFX11_3DSTATE_GS_InvocationsIncrementValue_start 229 #define GFX9_3DSTATE_GS_InvocationsIncrementValue_start 229 #define GFX8_3DSTATE_GS_InvocationsIncrementValue_start 229 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_InvocationsIncrementValue_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 229; case 120: return 229; case 110: return 229; case 90: return 229; case 80: return 229; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GS::Kernel Start Pointer */ #define GFX125_3DSTATE_GS_KernelStartPointer_bits 58 #define GFX12_3DSTATE_GS_KernelStartPointer_bits 58 #define GFX11_3DSTATE_GS_KernelStartPointer_bits 58 #define GFX9_3DSTATE_GS_KernelStartPointer_bits 58 #define GFX8_3DSTATE_GS_KernelStartPointer_bits 58 #define GFX75_3DSTATE_GS_KernelStartPointer_bits 26 #define GFX7_3DSTATE_GS_KernelStartPointer_bits 26 #define GFX6_3DSTATE_GS_KernelStartPointer_bits 26 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_KernelStartPointer_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 58; case 120: return 58; case 110: return 58; case 90: return 58; case 80: return 58; case 75: return 26; case 70: return 26; case 60: return 26; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GS_KernelStartPointer_start 38 #define GFX12_3DSTATE_GS_KernelStartPointer_start 38 #define GFX11_3DSTATE_GS_KernelStartPointer_start 38 #define GFX9_3DSTATE_GS_KernelStartPointer_start 38 #define GFX8_3DSTATE_GS_KernelStartPointer_start 38 #define GFX75_3DSTATE_GS_KernelStartPointer_start 38 #define GFX7_3DSTATE_GS_KernelStartPointer_start 38 #define GFX6_3DSTATE_GS_KernelStartPointer_start 38 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_KernelStartPointer_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 38; case 120: return 38; case 110: return 38; case 90: return 38; case 80: return 38; case 75: return 38; case 70: return 38; case 60: return 38; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GS::Mask Stack Exception Enable */ #define GFX125_3DSTATE_GS_MaskStackExceptionEnable_bits 1 #define GFX12_3DSTATE_GS_MaskStackExceptionEnable_bits 1 #define GFX11_3DSTATE_GS_MaskStackExceptionEnable_bits 1 #define GFX9_3DSTATE_GS_MaskStackExceptionEnable_bits 1 #define GFX8_3DSTATE_GS_MaskStackExceptionEnable_bits 1 #define GFX75_3DSTATE_GS_MaskStackExceptionEnable_bits 1 #define GFX7_3DSTATE_GS_MaskStackExceptionEnable_bits 1 #define GFX6_3DSTATE_GS_MaskStackExceptionEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_MaskStackExceptionEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GS_MaskStackExceptionEnable_start 107 #define GFX12_3DSTATE_GS_MaskStackExceptionEnable_start 107 #define GFX11_3DSTATE_GS_MaskStackExceptionEnable_start 107 #define GFX9_3DSTATE_GS_MaskStackExceptionEnable_start 107 #define GFX8_3DSTATE_GS_MaskStackExceptionEnable_start 107 #define GFX75_3DSTATE_GS_MaskStackExceptionEnable_start 75 #define GFX7_3DSTATE_GS_MaskStackExceptionEnable_start 75 #define GFX6_3DSTATE_GS_MaskStackExceptionEnable_start 75 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_MaskStackExceptionEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 107; case 120: return 107; case 110: return 107; case 90: return 107; case 80: return 107; case 75: return 75; case 70: return 75; case 60: return 75; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GS::Maximum Number of Threads */ #define GFX125_3DSTATE_GS_MaximumNumberofThreads_bits 9 #define GFX12_3DSTATE_GS_MaximumNumberofThreads_bits 9 #define GFX11_3DSTATE_GS_MaximumNumberofThreads_bits 9 #define GFX9_3DSTATE_GS_MaximumNumberofThreads_bits 9 #define GFX8_3DSTATE_GS_MaximumNumberofThreads_bits 8 #define GFX75_3DSTATE_GS_MaximumNumberofThreads_bits 8 #define GFX7_3DSTATE_GS_MaximumNumberofThreads_bits 7 #define GFX6_3DSTATE_GS_MaximumNumberofThreads_bits 7 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_MaximumNumberofThreads_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 9; case 120: return 9; case 110: return 9; case 90: return 9; case 80: return 8; case 75: return 8; case 70: return 7; case 60: return 7; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GS_MaximumNumberofThreads_start 256 #define GFX12_3DSTATE_GS_MaximumNumberofThreads_start 256 #define GFX11_3DSTATE_GS_MaximumNumberofThreads_start 256 #define GFX9_3DSTATE_GS_MaximumNumberofThreads_start 256 #define GFX8_3DSTATE_GS_MaximumNumberofThreads_start 248 #define GFX75_3DSTATE_GS_MaximumNumberofThreads_start 184 #define GFX7_3DSTATE_GS_MaximumNumberofThreads_start 185 #define GFX6_3DSTATE_GS_MaximumNumberofThreads_start 185 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_MaximumNumberofThreads_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 256; case 120: return 256; case 110: return 256; case 90: return 256; case 80: return 248; case 75: return 184; case 70: return 185; case 60: return 185; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GS::Output Topology */ #define GFX125_3DSTATE_GS_OutputTopology_bits 6 #define GFX12_3DSTATE_GS_OutputTopology_bits 6 #define GFX11_3DSTATE_GS_OutputTopology_bits 6 #define GFX9_3DSTATE_GS_OutputTopology_bits 6 #define GFX8_3DSTATE_GS_OutputTopology_bits 6 #define GFX75_3DSTATE_GS_OutputTopology_bits 6 #define GFX7_3DSTATE_GS_OutputTopology_bits 6 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_OutputTopology_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 6; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GS_OutputTopology_start 209 #define GFX12_3DSTATE_GS_OutputTopology_start 209 #define GFX11_3DSTATE_GS_OutputTopology_start 209 #define GFX9_3DSTATE_GS_OutputTopology_start 209 #define GFX8_3DSTATE_GS_OutputTopology_start 209 #define GFX75_3DSTATE_GS_OutputTopology_start 145 #define GFX7_3DSTATE_GS_OutputTopology_start 145 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_OutputTopology_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 209; case 120: return 209; case 110: return 209; case 90: return 209; case 80: return 209; case 75: return 145; case 70: return 145; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GS::Output Vertex Size */ #define GFX125_3DSTATE_GS_OutputVertexSize_bits 6 #define GFX12_3DSTATE_GS_OutputVertexSize_bits 6 #define GFX11_3DSTATE_GS_OutputVertexSize_bits 6 #define GFX9_3DSTATE_GS_OutputVertexSize_bits 6 #define GFX8_3DSTATE_GS_OutputVertexSize_bits 6 #define GFX75_3DSTATE_GS_OutputVertexSize_bits 6 #define GFX7_3DSTATE_GS_OutputVertexSize_bits 6 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_OutputVertexSize_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 6; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GS_OutputVertexSize_start 215 #define GFX12_3DSTATE_GS_OutputVertexSize_start 215 #define GFX11_3DSTATE_GS_OutputVertexSize_start 215 #define GFX9_3DSTATE_GS_OutputVertexSize_start 215 #define GFX8_3DSTATE_GS_OutputVertexSize_start 215 #define GFX75_3DSTATE_GS_OutputVertexSize_start 151 #define GFX7_3DSTATE_GS_OutputVertexSize_start 151 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_OutputVertexSize_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 215; case 120: return 215; case 110: return 215; case 90: return 215; case 80: return 215; case 75: return 151; case 70: return 151; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GS::Per-Thread Scratch Space */ #define GFX12_3DSTATE_GS_PerThreadScratchSpace_bits 4 #define GFX11_3DSTATE_GS_PerThreadScratchSpace_bits 4 #define GFX9_3DSTATE_GS_PerThreadScratchSpace_bits 4 #define GFX8_3DSTATE_GS_PerThreadScratchSpace_bits 4 #define GFX75_3DSTATE_GS_PerThreadScratchSpace_bits 4 #define GFX7_3DSTATE_GS_PerThreadScratchSpace_bits 4 #define GFX6_3DSTATE_GS_PerThreadScratchSpace_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_PerThreadScratchSpace_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 4; case 70: return 4; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_3DSTATE_GS_PerThreadScratchSpace_start 128 #define GFX11_3DSTATE_GS_PerThreadScratchSpace_start 128 #define GFX9_3DSTATE_GS_PerThreadScratchSpace_start 128 #define GFX8_3DSTATE_GS_PerThreadScratchSpace_start 128 #define GFX75_3DSTATE_GS_PerThreadScratchSpace_start 96 #define GFX7_3DSTATE_GS_PerThreadScratchSpace_start 96 #define GFX6_3DSTATE_GS_PerThreadScratchSpace_start 96 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_PerThreadScratchSpace_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 128; case 110: return 128; case 90: return 128; case 80: return 128; case 75: return 96; case 70: return 96; case 60: return 96; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GS::Rendering Enabled */ #define GFX6_3DSTATE_GS_RenderingEnabled_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_RenderingEnabled_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_GS_RenderingEnabled_start 168 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_RenderingEnabled_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 168; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GS::Reorder Mode */ #define GFX125_3DSTATE_GS_ReorderMode_bits 1 #define GFX12_3DSTATE_GS_ReorderMode_bits 1 #define GFX11_3DSTATE_GS_ReorderMode_bits 1 #define GFX9_3DSTATE_GS_ReorderMode_bits 1 #define GFX8_3DSTATE_GS_ReorderMode_bits 1 #define GFX75_3DSTATE_GS_ReorderMode_bits 1 #define GFX7_3DSTATE_GS_ReorderMode_bits 1 #define GFX6_3DSTATE_GS_ReorderMode_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_ReorderMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GS_ReorderMode_start 226 #define GFX12_3DSTATE_GS_ReorderMode_start 226 #define GFX11_3DSTATE_GS_ReorderMode_start 226 #define GFX9_3DSTATE_GS_ReorderMode_start 226 #define GFX8_3DSTATE_GS_ReorderMode_start 226 #define GFX75_3DSTATE_GS_ReorderMode_start 162 #define GFX7_3DSTATE_GS_ReorderMode_start 162 #define GFX6_3DSTATE_GS_ReorderMode_start 222 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_ReorderMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 226; case 120: return 226; case 110: return 226; case 90: return 226; case 80: return 226; case 75: return 162; case 70: return 162; case 60: return 222; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GS::SO Statistics Enable */ #define GFX6_3DSTATE_GS_SOStatisticsEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_SOStatisticsEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_GS_SOStatisticsEnable_start 169 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_SOStatisticsEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 169; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GS::SVBI Payload Enable */ #define GFX6_3DSTATE_GS_SVBIPayloadEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_SVBIPayloadEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_GS_SVBIPayloadEnable_start 220 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_SVBIPayloadEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 220; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GS::SVBI Post-Increment Enable */ #define GFX6_3DSTATE_GS_SVBIPostIncrementEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_SVBIPostIncrementEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_GS_SVBIPostIncrementEnable_start 219 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_SVBIPostIncrementEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 219; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GS::SVBI Post-Increment Value */ #define GFX6_3DSTATE_GS_SVBIPostIncrementValue_bits 10 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_SVBIPostIncrementValue_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 10; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_GS_SVBIPostIncrementValue_start 208 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_SVBIPostIncrementValue_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 208; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GS::Sampler Count */ #define GFX125_3DSTATE_GS_SamplerCount_bits 3 #define GFX12_3DSTATE_GS_SamplerCount_bits 3 #define GFX11_3DSTATE_GS_SamplerCount_bits 3 #define GFX9_3DSTATE_GS_SamplerCount_bits 3 #define GFX8_3DSTATE_GS_SamplerCount_bits 3 #define GFX75_3DSTATE_GS_SamplerCount_bits 3 #define GFX7_3DSTATE_GS_SamplerCount_bits 3 #define GFX6_3DSTATE_GS_SamplerCount_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_SamplerCount_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GS_SamplerCount_start 123 #define GFX12_3DSTATE_GS_SamplerCount_start 123 #define GFX11_3DSTATE_GS_SamplerCount_start 123 #define GFX9_3DSTATE_GS_SamplerCount_start 123 #define GFX8_3DSTATE_GS_SamplerCount_start 123 #define GFX75_3DSTATE_GS_SamplerCount_start 91 #define GFX7_3DSTATE_GS_SamplerCount_start 91 #define GFX6_3DSTATE_GS_SamplerCount_start 91 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_SamplerCount_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 123; case 120: return 123; case 110: return 123; case 90: return 123; case 80: return 123; case 75: return 91; case 70: return 91; case 60: return 91; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GS::Scratch Space Base Pointer */ #define GFX12_3DSTATE_GS_ScratchSpaceBasePointer_bits 54 #define GFX11_3DSTATE_GS_ScratchSpaceBasePointer_bits 54 #define GFX9_3DSTATE_GS_ScratchSpaceBasePointer_bits 54 #define GFX8_3DSTATE_GS_ScratchSpaceBasePointer_bits 54 #define GFX75_3DSTATE_GS_ScratchSpaceBasePointer_bits 22 #define GFX7_3DSTATE_GS_ScratchSpaceBasePointer_bits 22 #define GFX6_3DSTATE_GS_ScratchSpaceBasePointer_bits 22 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_ScratchSpaceBasePointer_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 54; case 110: return 54; case 90: return 54; case 80: return 54; case 75: return 22; case 70: return 22; case 60: return 22; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_3DSTATE_GS_ScratchSpaceBasePointer_start 138 #define GFX11_3DSTATE_GS_ScratchSpaceBasePointer_start 138 #define GFX9_3DSTATE_GS_ScratchSpaceBasePointer_start 138 #define GFX8_3DSTATE_GS_ScratchSpaceBasePointer_start 138 #define GFX75_3DSTATE_GS_ScratchSpaceBasePointer_start 106 #define GFX7_3DSTATE_GS_ScratchSpaceBasePointer_start 106 #define GFX6_3DSTATE_GS_ScratchSpaceBasePointer_start 106 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_ScratchSpaceBasePointer_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 138; case 110: return 138; case 90: return 138; case 80: return 138; case 75: return 106; case 70: return 106; case 60: return 106; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GS::Scratch Space Buffer */ #define GFX125_3DSTATE_GS_ScratchSpaceBuffer_bits 22 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_ScratchSpaceBuffer_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 22; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GS_ScratchSpaceBuffer_start 138 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_ScratchSpaceBuffer_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 138; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GS::Semaphore Handle */ #define GFX75_3DSTATE_GS_SemaphoreHandle_bits 13 #define GFX7_3DSTATE_GS_SemaphoreHandle_bits 12 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_SemaphoreHandle_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 13; case 70: return 12; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_GS_SemaphoreHandle_start 192 #define GFX7_3DSTATE_GS_SemaphoreHandle_start 192 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_SemaphoreHandle_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 192; case 70: return 192; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GS::Single Program Flow */ #define GFX125_3DSTATE_GS_SingleProgramFlow_bits 1 #define GFX12_3DSTATE_GS_SingleProgramFlow_bits 1 #define GFX11_3DSTATE_GS_SingleProgramFlow_bits 1 #define GFX9_3DSTATE_GS_SingleProgramFlow_bits 1 #define GFX8_3DSTATE_GS_SingleProgramFlow_bits 1 #define GFX75_3DSTATE_GS_SingleProgramFlow_bits 1 #define GFX7_3DSTATE_GS_SingleProgramFlow_bits 1 #define GFX6_3DSTATE_GS_SingleProgramFlow_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_SingleProgramFlow_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GS_SingleProgramFlow_start 127 #define GFX12_3DSTATE_GS_SingleProgramFlow_start 127 #define GFX11_3DSTATE_GS_SingleProgramFlow_start 127 #define GFX9_3DSTATE_GS_SingleProgramFlow_start 127 #define GFX8_3DSTATE_GS_SingleProgramFlow_start 127 #define GFX75_3DSTATE_GS_SingleProgramFlow_start 95 #define GFX7_3DSTATE_GS_SingleProgramFlow_start 95 #define GFX6_3DSTATE_GS_SingleProgramFlow_start 95 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_SingleProgramFlow_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 127; case 120: return 127; case 110: return 127; case 90: return 127; case 80: return 127; case 75: return 95; case 70: return 95; case 60: return 95; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GS::Software Exception Enable */ #define GFX125_3DSTATE_GS_SoftwareExceptionEnable_bits 1 #define GFX12_3DSTATE_GS_SoftwareExceptionEnable_bits 1 #define GFX11_3DSTATE_GS_SoftwareExceptionEnable_bits 1 #define GFX9_3DSTATE_GS_SoftwareExceptionEnable_bits 1 #define GFX8_3DSTATE_GS_SoftwareExceptionEnable_bits 1 #define GFX75_3DSTATE_GS_SoftwareExceptionEnable_bits 1 #define GFX7_3DSTATE_GS_SoftwareExceptionEnable_bits 1 #define GFX6_3DSTATE_GS_SoftwareExceptionEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_SoftwareExceptionEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GS_SoftwareExceptionEnable_start 103 #define GFX12_3DSTATE_GS_SoftwareExceptionEnable_start 103 #define GFX11_3DSTATE_GS_SoftwareExceptionEnable_start 103 #define GFX9_3DSTATE_GS_SoftwareExceptionEnable_start 103 #define GFX8_3DSTATE_GS_SoftwareExceptionEnable_start 103 #define GFX75_3DSTATE_GS_SoftwareExceptionEnable_start 71 #define GFX7_3DSTATE_GS_SoftwareExceptionEnable_start 71 #define GFX6_3DSTATE_GS_SoftwareExceptionEnable_start 71 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_SoftwareExceptionEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 103; case 120: return 103; case 110: return 103; case 90: return 103; case 80: return 103; case 75: return 71; case 70: return 71; case 60: return 71; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GS::Static Output */ #define GFX125_3DSTATE_GS_StaticOutput_bits 1 #define GFX12_3DSTATE_GS_StaticOutput_bits 1 #define GFX11_3DSTATE_GS_StaticOutput_bits 1 #define GFX9_3DSTATE_GS_StaticOutput_bits 1 #define GFX8_3DSTATE_GS_StaticOutput_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_StaticOutput_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GS_StaticOutput_start 286 #define GFX12_3DSTATE_GS_StaticOutput_start 286 #define GFX11_3DSTATE_GS_StaticOutput_start 286 #define GFX9_3DSTATE_GS_StaticOutput_start 286 #define GFX8_3DSTATE_GS_StaticOutput_start 286 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_StaticOutput_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 286; case 120: return 286; case 110: return 286; case 90: return 286; case 80: return 286; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GS::Static Output Vertex Count */ #define GFX125_3DSTATE_GS_StaticOutputVertexCount_bits 11 #define GFX12_3DSTATE_GS_StaticOutputVertexCount_bits 11 #define GFX11_3DSTATE_GS_StaticOutputVertexCount_bits 11 #define GFX9_3DSTATE_GS_StaticOutputVertexCount_bits 11 #define GFX8_3DSTATE_GS_StaticOutputVertexCount_bits 11 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_StaticOutputVertexCount_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 11; case 120: return 11; case 110: return 11; case 90: return 11; case 80: return 11; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GS_StaticOutputVertexCount_start 272 #define GFX12_3DSTATE_GS_StaticOutputVertexCount_start 272 #define GFX11_3DSTATE_GS_StaticOutputVertexCount_start 272 #define GFX9_3DSTATE_GS_StaticOutputVertexCount_start 272 #define GFX8_3DSTATE_GS_StaticOutputVertexCount_start 272 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_StaticOutputVertexCount_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 272; case 120: return 272; case 110: return 272; case 90: return 272; case 80: return 272; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GS::Statistics Enable */ #define GFX125_3DSTATE_GS_StatisticsEnable_bits 1 #define GFX12_3DSTATE_GS_StatisticsEnable_bits 1 #define GFX11_3DSTATE_GS_StatisticsEnable_bits 1 #define GFX9_3DSTATE_GS_StatisticsEnable_bits 1 #define GFX8_3DSTATE_GS_StatisticsEnable_bits 1 #define GFX75_3DSTATE_GS_StatisticsEnable_bits 1 #define GFX7_3DSTATE_GS_StatisticsEnable_bits 1 #define GFX6_3DSTATE_GS_StatisticsEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_StatisticsEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GS_StatisticsEnable_start 234 #define GFX12_3DSTATE_GS_StatisticsEnable_start 234 #define GFX11_3DSTATE_GS_StatisticsEnable_start 234 #define GFX9_3DSTATE_GS_StatisticsEnable_start 234 #define GFX8_3DSTATE_GS_StatisticsEnable_start 234 #define GFX75_3DSTATE_GS_StatisticsEnable_start 170 #define GFX7_3DSTATE_GS_StatisticsEnable_start 170 #define GFX6_3DSTATE_GS_StatisticsEnable_start 170 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_StatisticsEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 234; case 120: return 234; case 110: return 234; case 90: return 234; case 80: return 234; case 75: return 170; case 70: return 170; case 60: return 170; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GS::Thread Dispatch Priority */ #define GFX125_3DSTATE_GS_ThreadDispatchPriority_bits 1 #define GFX12_3DSTATE_GS_ThreadDispatchPriority_bits 1 #define GFX11_3DSTATE_GS_ThreadDispatchPriority_bits 1 #define GFX9_3DSTATE_GS_ThreadDispatchPriority_bits 1 #define GFX8_3DSTATE_GS_ThreadDispatchPriority_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_ThreadDispatchPriority_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GS_ThreadDispatchPriority_start 113 #define GFX12_3DSTATE_GS_ThreadDispatchPriority_start 113 #define GFX11_3DSTATE_GS_ThreadDispatchPriority_start 113 #define GFX9_3DSTATE_GS_ThreadDispatchPriority_start 113 #define GFX8_3DSTATE_GS_ThreadDispatchPriority_start 113 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_ThreadDispatchPriority_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 113; case 120: return 113; case 110: return 113; case 90: return 113; case 80: return 113; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GS::Thread Priority */ #define GFX75_3DSTATE_GS_ThreadPriority_bits 1 #define GFX7_3DSTATE_GS_ThreadPriority_bits 1 #define GFX6_3DSTATE_GS_ThreadPriority_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_ThreadPriority_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_GS_ThreadPriority_start 81 #define GFX7_3DSTATE_GS_ThreadPriority_start 81 #define GFX6_3DSTATE_GS_ThreadPriority_start 81 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_ThreadPriority_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 81; case 70: return 81; case 60: return 81; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GS::User Clip Distance Clip Test Enable Bitmask */ #define GFX125_3DSTATE_GS_UserClipDistanceClipTestEnableBitmask_bits 8 #define GFX12_3DSTATE_GS_UserClipDistanceClipTestEnableBitmask_bits 8 #define GFX11_3DSTATE_GS_UserClipDistanceClipTestEnableBitmask_bits 8 #define GFX9_3DSTATE_GS_UserClipDistanceClipTestEnableBitmask_bits 8 #define GFX8_3DSTATE_GS_UserClipDistanceClipTestEnableBitmask_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_UserClipDistanceClipTestEnableBitmask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GS_UserClipDistanceClipTestEnableBitmask_start 296 #define GFX12_3DSTATE_GS_UserClipDistanceClipTestEnableBitmask_start 296 #define GFX11_3DSTATE_GS_UserClipDistanceClipTestEnableBitmask_start 296 #define GFX9_3DSTATE_GS_UserClipDistanceClipTestEnableBitmask_start 296 #define GFX8_3DSTATE_GS_UserClipDistanceClipTestEnableBitmask_start 296 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_UserClipDistanceClipTestEnableBitmask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 296; case 120: return 296; case 110: return 296; case 90: return 296; case 80: return 296; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GS::User Clip Distance Cull Test Enable Bitmask */ #define GFX125_3DSTATE_GS_UserClipDistanceCullTestEnableBitmask_bits 8 #define GFX12_3DSTATE_GS_UserClipDistanceCullTestEnableBitmask_bits 8 #define GFX11_3DSTATE_GS_UserClipDistanceCullTestEnableBitmask_bits 8 #define GFX9_3DSTATE_GS_UserClipDistanceCullTestEnableBitmask_bits 8 #define GFX8_3DSTATE_GS_UserClipDistanceCullTestEnableBitmask_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_UserClipDistanceCullTestEnableBitmask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GS_UserClipDistanceCullTestEnableBitmask_start 288 #define GFX12_3DSTATE_GS_UserClipDistanceCullTestEnableBitmask_start 288 #define GFX11_3DSTATE_GS_UserClipDistanceCullTestEnableBitmask_start 288 #define GFX9_3DSTATE_GS_UserClipDistanceCullTestEnableBitmask_start 288 #define GFX8_3DSTATE_GS_UserClipDistanceCullTestEnableBitmask_start 288 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_UserClipDistanceCullTestEnableBitmask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 288; case 120: return 288; case 110: return 288; case 90: return 288; case 80: return 288; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GS::Vector Mask Enable */ #define GFX125_3DSTATE_GS_VectorMaskEnable_bits 1 #define GFX12_3DSTATE_GS_VectorMaskEnable_bits 1 #define GFX11_3DSTATE_GS_VectorMaskEnable_bits 1 #define GFX9_3DSTATE_GS_VectorMaskEnable_bits 1 #define GFX8_3DSTATE_GS_VectorMaskEnable_bits 1 #define GFX75_3DSTATE_GS_VectorMaskEnable_bits 1 #define GFX7_3DSTATE_GS_VectorMaskEnable_bits 1 #define GFX6_3DSTATE_GS_VectorMaskEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_VectorMaskEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GS_VectorMaskEnable_start 126 #define GFX12_3DSTATE_GS_VectorMaskEnable_start 126 #define GFX11_3DSTATE_GS_VectorMaskEnable_start 126 #define GFX9_3DSTATE_GS_VectorMaskEnable_start 126 #define GFX8_3DSTATE_GS_VectorMaskEnable_start 126 #define GFX75_3DSTATE_GS_VectorMaskEnable_start 94 #define GFX7_3DSTATE_GS_VectorMaskEnable_start 94 #define GFX6_3DSTATE_GS_VectorMaskEnable_start 94 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_VectorMaskEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 126; case 120: return 126; case 110: return 126; case 90: return 126; case 80: return 126; case 75: return 94; case 70: return 94; case 60: return 94; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GS::Vertex URB Entry Output Length */ #define GFX125_3DSTATE_GS_VertexURBEntryOutputLength_bits 5 #define GFX12_3DSTATE_GS_VertexURBEntryOutputLength_bits 5 #define GFX11_3DSTATE_GS_VertexURBEntryOutputLength_bits 5 #define GFX9_3DSTATE_GS_VertexURBEntryOutputLength_bits 5 #define GFX8_3DSTATE_GS_VertexURBEntryOutputLength_bits 5 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_VertexURBEntryOutputLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 5; case 110: return 5; case 90: return 5; case 80: return 5; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GS_VertexURBEntryOutputLength_start 304 #define GFX12_3DSTATE_GS_VertexURBEntryOutputLength_start 304 #define GFX11_3DSTATE_GS_VertexURBEntryOutputLength_start 304 #define GFX9_3DSTATE_GS_VertexURBEntryOutputLength_start 304 #define GFX8_3DSTATE_GS_VertexURBEntryOutputLength_start 304 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_VertexURBEntryOutputLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 304; case 120: return 304; case 110: return 304; case 90: return 304; case 80: return 304; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GS::Vertex URB Entry Output Read Offset */ #define GFX125_3DSTATE_GS_VertexURBEntryOutputReadOffset_bits 6 #define GFX12_3DSTATE_GS_VertexURBEntryOutputReadOffset_bits 6 #define GFX11_3DSTATE_GS_VertexURBEntryOutputReadOffset_bits 6 #define GFX9_3DSTATE_GS_VertexURBEntryOutputReadOffset_bits 6 #define GFX8_3DSTATE_GS_VertexURBEntryOutputReadOffset_bits 6 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_VertexURBEntryOutputReadOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GS_VertexURBEntryOutputReadOffset_start 309 #define GFX12_3DSTATE_GS_VertexURBEntryOutputReadOffset_start 309 #define GFX11_3DSTATE_GS_VertexURBEntryOutputReadOffset_start 309 #define GFX9_3DSTATE_GS_VertexURBEntryOutputReadOffset_start 309 #define GFX8_3DSTATE_GS_VertexURBEntryOutputReadOffset_start 309 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_VertexURBEntryOutputReadOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 309; case 120: return 309; case 110: return 309; case 90: return 309; case 80: return 309; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GS::Vertex URB Entry Read Length */ #define GFX125_3DSTATE_GS_VertexURBEntryReadLength_bits 6 #define GFX12_3DSTATE_GS_VertexURBEntryReadLength_bits 6 #define GFX11_3DSTATE_GS_VertexURBEntryReadLength_bits 6 #define GFX9_3DSTATE_GS_VertexURBEntryReadLength_bits 6 #define GFX8_3DSTATE_GS_VertexURBEntryReadLength_bits 6 #define GFX75_3DSTATE_GS_VertexURBEntryReadLength_bits 6 #define GFX7_3DSTATE_GS_VertexURBEntryReadLength_bits 6 #define GFX6_3DSTATE_GS_VertexURBEntryReadLength_bits 6 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_VertexURBEntryReadLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 6; case 60: return 6; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GS_VertexURBEntryReadLength_start 203 #define GFX12_3DSTATE_GS_VertexURBEntryReadLength_start 203 #define GFX11_3DSTATE_GS_VertexURBEntryReadLength_start 203 #define GFX9_3DSTATE_GS_VertexURBEntryReadLength_start 203 #define GFX8_3DSTATE_GS_VertexURBEntryReadLength_start 203 #define GFX75_3DSTATE_GS_VertexURBEntryReadLength_start 139 #define GFX7_3DSTATE_GS_VertexURBEntryReadLength_start 139 #define GFX6_3DSTATE_GS_VertexURBEntryReadLength_start 139 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_VertexURBEntryReadLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 203; case 120: return 203; case 110: return 203; case 90: return 203; case 80: return 203; case 75: return 139; case 70: return 139; case 60: return 139; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GS::Vertex URB Entry Read Offset */ #define GFX125_3DSTATE_GS_VertexURBEntryReadOffset_bits 6 #define GFX12_3DSTATE_GS_VertexURBEntryReadOffset_bits 6 #define GFX11_3DSTATE_GS_VertexURBEntryReadOffset_bits 6 #define GFX9_3DSTATE_GS_VertexURBEntryReadOffset_bits 6 #define GFX8_3DSTATE_GS_VertexURBEntryReadOffset_bits 6 #define GFX75_3DSTATE_GS_VertexURBEntryReadOffset_bits 6 #define GFX7_3DSTATE_GS_VertexURBEntryReadOffset_bits 6 #define GFX6_3DSTATE_GS_VertexURBEntryReadOffset_bits 6 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_VertexURBEntryReadOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 6; case 60: return 6; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_GS_VertexURBEntryReadOffset_start 196 #define GFX12_3DSTATE_GS_VertexURBEntryReadOffset_start 196 #define GFX11_3DSTATE_GS_VertexURBEntryReadOffset_start 196 #define GFX9_3DSTATE_GS_VertexURBEntryReadOffset_start 196 #define GFX8_3DSTATE_GS_VertexURBEntryReadOffset_start 196 #define GFX75_3DSTATE_GS_VertexURBEntryReadOffset_start 132 #define GFX7_3DSTATE_GS_VertexURBEntryReadOffset_start 132 #define GFX6_3DSTATE_GS_VertexURBEntryReadOffset_start 132 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_VertexURBEntryReadOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 196; case 120: return 196; case 110: return 196; case 90: return 196; case 80: return 196; case 75: return 132; case 70: return 132; case 60: return 132; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GS_SVB_INDEX */ #define GFX6_3DSTATE_GS_SVB_INDEX_length 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_SVB_INDEX_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GS_SVB_INDEX::3D Command Opcode */ #define GFX6_3DSTATE_GS_SVB_INDEX_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_SVB_INDEX_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_GS_SVB_INDEX_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_SVB_INDEX_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 24; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GS_SVB_INDEX::3D Command Sub Opcode */ #define GFX6_3DSTATE_GS_SVB_INDEX_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_SVB_INDEX_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_GS_SVB_INDEX_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_SVB_INDEX_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 16; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GS_SVB_INDEX::Command SubType */ #define GFX6_3DSTATE_GS_SVB_INDEX_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_SVB_INDEX_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_GS_SVB_INDEX_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_SVB_INDEX_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 27; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GS_SVB_INDEX::Command Type */ #define GFX6_3DSTATE_GS_SVB_INDEX_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_SVB_INDEX_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_GS_SVB_INDEX_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_SVB_INDEX_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 29; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GS_SVB_INDEX::DWord Length */ #define GFX6_3DSTATE_GS_SVB_INDEX_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_SVB_INDEX_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_GS_SVB_INDEX_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_SVB_INDEX_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GS_SVB_INDEX::Index Number */ #define GFX6_3DSTATE_GS_SVB_INDEX_IndexNumber_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_SVB_INDEX_IndexNumber_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_GS_SVB_INDEX_IndexNumber_start 61 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_SVB_INDEX_IndexNumber_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 61; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GS_SVB_INDEX::Load Internal Vertex Count */ #define GFX6_3DSTATE_GS_SVB_INDEX_LoadInternalVertexCount_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_SVB_INDEX_LoadInternalVertexCount_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_GS_SVB_INDEX_LoadInternalVertexCount_start 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_SVB_INDEX_LoadInternalVertexCount_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 32; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GS_SVB_INDEX::Maximum Index */ #define GFX6_3DSTATE_GS_SVB_INDEX_MaximumIndex_bits 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_SVB_INDEX_MaximumIndex_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 32; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_GS_SVB_INDEX_MaximumIndex_start 96 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_SVB_INDEX_MaximumIndex_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 96; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_GS_SVB_INDEX::Streamed Vertex Buffer Index */ #define GFX6_3DSTATE_GS_SVB_INDEX_StreamedVertexBufferIndex_bits 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_SVB_INDEX_StreamedVertexBufferIndex_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 32; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_GS_SVB_INDEX_StreamedVertexBufferIndex_start 64 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_GS_SVB_INDEX_StreamedVertexBufferIndex_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 64; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_HIER_DEPTH_BUFFER */ #define GFX125_3DSTATE_HIER_DEPTH_BUFFER_length 5 #define GFX12_3DSTATE_HIER_DEPTH_BUFFER_length 5 #define GFX11_3DSTATE_HIER_DEPTH_BUFFER_length 5 #define GFX9_3DSTATE_HIER_DEPTH_BUFFER_length 5 #define GFX8_3DSTATE_HIER_DEPTH_BUFFER_length 5 #define GFX75_3DSTATE_HIER_DEPTH_BUFFER_length 3 #define GFX7_3DSTATE_HIER_DEPTH_BUFFER_length 3 #define GFX6_3DSTATE_HIER_DEPTH_BUFFER_length 3 #define GFX5_3DSTATE_HIER_DEPTH_BUFFER_length 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HIER_DEPTH_BUFFER_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 5; case 110: return 5; case 90: return 5; case 80: return 5; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 3; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_HIER_DEPTH_BUFFER::3D Command Opcode */ #define GFX125_3DSTATE_HIER_DEPTH_BUFFER_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_HIER_DEPTH_BUFFER_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_HIER_DEPTH_BUFFER_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_HIER_DEPTH_BUFFER_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_HIER_DEPTH_BUFFER_3DCommandOpcode_bits 3 #define GFX75_3DSTATE_HIER_DEPTH_BUFFER_3DCommandOpcode_bits 3 #define GFX7_3DSTATE_HIER_DEPTH_BUFFER_3DCommandOpcode_bits 3 #define GFX6_3DSTATE_HIER_DEPTH_BUFFER_3DCommandOpcode_bits 3 #define GFX5_3DSTATE_HIER_DEPTH_BUFFER_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HIER_DEPTH_BUFFER_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 3; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_HIER_DEPTH_BUFFER_3DCommandOpcode_start 24 #define GFX12_3DSTATE_HIER_DEPTH_BUFFER_3DCommandOpcode_start 24 #define GFX11_3DSTATE_HIER_DEPTH_BUFFER_3DCommandOpcode_start 24 #define GFX9_3DSTATE_HIER_DEPTH_BUFFER_3DCommandOpcode_start 24 #define GFX8_3DSTATE_HIER_DEPTH_BUFFER_3DCommandOpcode_start 24 #define GFX75_3DSTATE_HIER_DEPTH_BUFFER_3DCommandOpcode_start 24 #define GFX7_3DSTATE_HIER_DEPTH_BUFFER_3DCommandOpcode_start 24 #define GFX6_3DSTATE_HIER_DEPTH_BUFFER_3DCommandOpcode_start 24 #define GFX5_3DSTATE_HIER_DEPTH_BUFFER_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HIER_DEPTH_BUFFER_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 24; case 50: return 24; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_HIER_DEPTH_BUFFER::3D Command Sub Opcode */ #define GFX125_3DSTATE_HIER_DEPTH_BUFFER_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_HIER_DEPTH_BUFFER_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_HIER_DEPTH_BUFFER_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_HIER_DEPTH_BUFFER_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_HIER_DEPTH_BUFFER_3DCommandSubOpcode_bits 8 #define GFX75_3DSTATE_HIER_DEPTH_BUFFER_3DCommandSubOpcode_bits 8 #define GFX7_3DSTATE_HIER_DEPTH_BUFFER_3DCommandSubOpcode_bits 8 #define GFX6_3DSTATE_HIER_DEPTH_BUFFER_3DCommandSubOpcode_bits 8 #define GFX5_3DSTATE_HIER_DEPTH_BUFFER_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HIER_DEPTH_BUFFER_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 8; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_HIER_DEPTH_BUFFER_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_HIER_DEPTH_BUFFER_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_HIER_DEPTH_BUFFER_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_HIER_DEPTH_BUFFER_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_HIER_DEPTH_BUFFER_3DCommandSubOpcode_start 16 #define GFX75_3DSTATE_HIER_DEPTH_BUFFER_3DCommandSubOpcode_start 16 #define GFX7_3DSTATE_HIER_DEPTH_BUFFER_3DCommandSubOpcode_start 16 #define GFX6_3DSTATE_HIER_DEPTH_BUFFER_3DCommandSubOpcode_start 16 #define GFX5_3DSTATE_HIER_DEPTH_BUFFER_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HIER_DEPTH_BUFFER_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 16; case 50: return 16; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_HIER_DEPTH_BUFFER::Command SubType */ #define GFX125_3DSTATE_HIER_DEPTH_BUFFER_CommandSubType_bits 2 #define GFX12_3DSTATE_HIER_DEPTH_BUFFER_CommandSubType_bits 2 #define GFX11_3DSTATE_HIER_DEPTH_BUFFER_CommandSubType_bits 2 #define GFX9_3DSTATE_HIER_DEPTH_BUFFER_CommandSubType_bits 2 #define GFX8_3DSTATE_HIER_DEPTH_BUFFER_CommandSubType_bits 2 #define GFX75_3DSTATE_HIER_DEPTH_BUFFER_CommandSubType_bits 2 #define GFX7_3DSTATE_HIER_DEPTH_BUFFER_CommandSubType_bits 2 #define GFX6_3DSTATE_HIER_DEPTH_BUFFER_CommandSubType_bits 2 #define GFX5_3DSTATE_HIER_DEPTH_BUFFER_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HIER_DEPTH_BUFFER_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 2; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_HIER_DEPTH_BUFFER_CommandSubType_start 27 #define GFX12_3DSTATE_HIER_DEPTH_BUFFER_CommandSubType_start 27 #define GFX11_3DSTATE_HIER_DEPTH_BUFFER_CommandSubType_start 27 #define GFX9_3DSTATE_HIER_DEPTH_BUFFER_CommandSubType_start 27 #define GFX8_3DSTATE_HIER_DEPTH_BUFFER_CommandSubType_start 27 #define GFX75_3DSTATE_HIER_DEPTH_BUFFER_CommandSubType_start 27 #define GFX7_3DSTATE_HIER_DEPTH_BUFFER_CommandSubType_start 27 #define GFX6_3DSTATE_HIER_DEPTH_BUFFER_CommandSubType_start 27 #define GFX5_3DSTATE_HIER_DEPTH_BUFFER_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HIER_DEPTH_BUFFER_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 27; case 50: return 27; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_HIER_DEPTH_BUFFER::Command Type */ #define GFX125_3DSTATE_HIER_DEPTH_BUFFER_CommandType_bits 3 #define GFX12_3DSTATE_HIER_DEPTH_BUFFER_CommandType_bits 3 #define GFX11_3DSTATE_HIER_DEPTH_BUFFER_CommandType_bits 3 #define GFX9_3DSTATE_HIER_DEPTH_BUFFER_CommandType_bits 3 #define GFX8_3DSTATE_HIER_DEPTH_BUFFER_CommandType_bits 3 #define GFX75_3DSTATE_HIER_DEPTH_BUFFER_CommandType_bits 3 #define GFX7_3DSTATE_HIER_DEPTH_BUFFER_CommandType_bits 3 #define GFX6_3DSTATE_HIER_DEPTH_BUFFER_CommandType_bits 3 #define GFX5_3DSTATE_HIER_DEPTH_BUFFER_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HIER_DEPTH_BUFFER_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 3; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_HIER_DEPTH_BUFFER_CommandType_start 29 #define GFX12_3DSTATE_HIER_DEPTH_BUFFER_CommandType_start 29 #define GFX11_3DSTATE_HIER_DEPTH_BUFFER_CommandType_start 29 #define GFX9_3DSTATE_HIER_DEPTH_BUFFER_CommandType_start 29 #define GFX8_3DSTATE_HIER_DEPTH_BUFFER_CommandType_start 29 #define GFX75_3DSTATE_HIER_DEPTH_BUFFER_CommandType_start 29 #define GFX7_3DSTATE_HIER_DEPTH_BUFFER_CommandType_start 29 #define GFX6_3DSTATE_HIER_DEPTH_BUFFER_CommandType_start 29 #define GFX5_3DSTATE_HIER_DEPTH_BUFFER_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HIER_DEPTH_BUFFER_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 29; case 50: return 29; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_HIER_DEPTH_BUFFER::DWord Length */ #define GFX125_3DSTATE_HIER_DEPTH_BUFFER_DWordLength_bits 8 #define GFX12_3DSTATE_HIER_DEPTH_BUFFER_DWordLength_bits 8 #define GFX11_3DSTATE_HIER_DEPTH_BUFFER_DWordLength_bits 8 #define GFX9_3DSTATE_HIER_DEPTH_BUFFER_DWordLength_bits 8 #define GFX8_3DSTATE_HIER_DEPTH_BUFFER_DWordLength_bits 8 #define GFX75_3DSTATE_HIER_DEPTH_BUFFER_DWordLength_bits 8 #define GFX7_3DSTATE_HIER_DEPTH_BUFFER_DWordLength_bits 8 #define GFX6_3DSTATE_HIER_DEPTH_BUFFER_DWordLength_bits 8 #define GFX5_3DSTATE_HIER_DEPTH_BUFFER_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HIER_DEPTH_BUFFER_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 8; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_HIER_DEPTH_BUFFER_DWordLength_start 0 #define GFX12_3DSTATE_HIER_DEPTH_BUFFER_DWordLength_start 0 #define GFX11_3DSTATE_HIER_DEPTH_BUFFER_DWordLength_start 0 #define GFX9_3DSTATE_HIER_DEPTH_BUFFER_DWordLength_start 0 #define GFX8_3DSTATE_HIER_DEPTH_BUFFER_DWordLength_start 0 #define GFX75_3DSTATE_HIER_DEPTH_BUFFER_DWordLength_start 0 #define GFX7_3DSTATE_HIER_DEPTH_BUFFER_DWordLength_start 0 #define GFX6_3DSTATE_HIER_DEPTH_BUFFER_DWordLength_start 0 #define GFX5_3DSTATE_HIER_DEPTH_BUFFER_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HIER_DEPTH_BUFFER_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_HIER_DEPTH_BUFFER::Hierarchical Depth Buffer MOCS */ #define GFX125_3DSTATE_HIER_DEPTH_BUFFER_HierarchicalDepthBufferMOCS_bits 7 #define GFX12_3DSTATE_HIER_DEPTH_BUFFER_HierarchicalDepthBufferMOCS_bits 7 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HIER_DEPTH_BUFFER_HierarchicalDepthBufferMOCS_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 7; case 120: return 7; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_HIER_DEPTH_BUFFER_HierarchicalDepthBufferMOCS_start 57 #define GFX12_3DSTATE_HIER_DEPTH_BUFFER_HierarchicalDepthBufferMOCS_start 57 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HIER_DEPTH_BUFFER_HierarchicalDepthBufferMOCS_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 57; case 120: return 57; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_HIER_DEPTH_BUFFER::Hierarchical Depth Buffer Write Thru Enable */ #define GFX125_3DSTATE_HIER_DEPTH_BUFFER_HierarchicalDepthBufferWriteThruEnable_bits 1 #define GFX12_3DSTATE_HIER_DEPTH_BUFFER_HierarchicalDepthBufferWriteThruEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HIER_DEPTH_BUFFER_HierarchicalDepthBufferWriteThruEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_HIER_DEPTH_BUFFER_HierarchicalDepthBufferWriteThruEnable_start 52 #define GFX12_3DSTATE_HIER_DEPTH_BUFFER_HierarchicalDepthBufferWriteThruEnable_start 52 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HIER_DEPTH_BUFFER_HierarchicalDepthBufferWriteThruEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 52; case 120: return 52; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_HIER_DEPTH_BUFFER::MOCS */ #define GFX125_3DSTATE_HIER_DEPTH_BUFFER_MOCS_bits 7 #define GFX12_3DSTATE_HIER_DEPTH_BUFFER_MOCS_bits 7 #define GFX11_3DSTATE_HIER_DEPTH_BUFFER_MOCS_bits 7 #define GFX9_3DSTATE_HIER_DEPTH_BUFFER_MOCS_bits 7 #define GFX8_3DSTATE_HIER_DEPTH_BUFFER_MOCS_bits 7 #define GFX75_3DSTATE_HIER_DEPTH_BUFFER_MOCS_bits 4 #define GFX7_3DSTATE_HIER_DEPTH_BUFFER_MOCS_bits 4 #define GFX6_3DSTATE_HIER_DEPTH_BUFFER_MOCS_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HIER_DEPTH_BUFFER_MOCS_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 7; case 120: return 7; case 110: return 7; case 90: return 7; case 80: return 7; case 75: return 4; case 70: return 4; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_HIER_DEPTH_BUFFER_MOCS_start 57 #define GFX12_3DSTATE_HIER_DEPTH_BUFFER_MOCS_start 57 #define GFX11_3DSTATE_HIER_DEPTH_BUFFER_MOCS_start 57 #define GFX9_3DSTATE_HIER_DEPTH_BUFFER_MOCS_start 57 #define GFX8_3DSTATE_HIER_DEPTH_BUFFER_MOCS_start 57 #define GFX75_3DSTATE_HIER_DEPTH_BUFFER_MOCS_start 57 #define GFX7_3DSTATE_HIER_DEPTH_BUFFER_MOCS_start 57 #define GFX6_3DSTATE_HIER_DEPTH_BUFFER_MOCS_start 57 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HIER_DEPTH_BUFFER_MOCS_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 57; case 120: return 57; case 110: return 57; case 90: return 57; case 80: return 57; case 75: return 57; case 70: return 57; case 60: return 57; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_HIER_DEPTH_BUFFER::Surface Base Address */ #define GFX125_3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_bits 64 #define GFX12_3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_bits 64 #define GFX11_3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_bits 64 #define GFX9_3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_bits 64 #define GFX8_3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_bits 64 #define GFX75_3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_bits 32 #define GFX7_3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_bits 32 #define GFX6_3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_bits 32 #define GFX5_3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_bits 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 64; case 80: return 64; case 75: return 32; case 70: return 32; case 60: return 32; case 50: return 32; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_start 64 #define GFX12_3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_start 64 #define GFX11_3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_start 64 #define GFX9_3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_start 64 #define GFX8_3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_start 64 #define GFX75_3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_start 64 #define GFX7_3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_start 64 #define GFX6_3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_start 64 #define GFX5_3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_start 64 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 64; case 80: return 64; case 75: return 64; case 70: return 64; case 60: return 64; case 50: return 64; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_HIER_DEPTH_BUFFER::Surface Pitch */ #define GFX125_3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_bits 17 #define GFX12_3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_bits 17 #define GFX11_3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_bits 17 #define GFX9_3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_bits 17 #define GFX8_3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_bits 17 #define GFX75_3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_bits 17 #define GFX7_3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_bits 17 #define GFX6_3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_bits 17 #define GFX5_3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_bits 17 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 17; case 120: return 17; case 110: return 17; case 90: return 17; case 80: return 17; case 75: return 17; case 70: return 17; case 60: return 17; case 50: return 17; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_start 32 #define GFX12_3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_start 32 #define GFX11_3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_start 32 #define GFX9_3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_start 32 #define GFX8_3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_start 32 #define GFX75_3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_start 32 #define GFX7_3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_start 32 #define GFX6_3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_start 32 #define GFX5_3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_start 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 32; case 50: return 32; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_HIER_DEPTH_BUFFER::Surface QPitch */ #define GFX125_3DSTATE_HIER_DEPTH_BUFFER_SurfaceQPitch_bits 15 #define GFX12_3DSTATE_HIER_DEPTH_BUFFER_SurfaceQPitch_bits 15 #define GFX11_3DSTATE_HIER_DEPTH_BUFFER_SurfaceQPitch_bits 15 #define GFX9_3DSTATE_HIER_DEPTH_BUFFER_SurfaceQPitch_bits 15 #define GFX8_3DSTATE_HIER_DEPTH_BUFFER_SurfaceQPitch_bits 15 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HIER_DEPTH_BUFFER_SurfaceQPitch_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 15; case 120: return 15; case 110: return 15; case 90: return 15; case 80: return 15; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_HIER_DEPTH_BUFFER_SurfaceQPitch_start 128 #define GFX12_3DSTATE_HIER_DEPTH_BUFFER_SurfaceQPitch_start 128 #define GFX11_3DSTATE_HIER_DEPTH_BUFFER_SurfaceQPitch_start 128 #define GFX9_3DSTATE_HIER_DEPTH_BUFFER_SurfaceQPitch_start 128 #define GFX8_3DSTATE_HIER_DEPTH_BUFFER_SurfaceQPitch_start 128 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HIER_DEPTH_BUFFER_SurfaceQPitch_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 128; case 120: return 128; case 110: return 128; case 90: return 128; case 80: return 128; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_HIER_DEPTH_BUFFER::Tiled Mode */ #define GFX125_3DSTATE_HIER_DEPTH_BUFFER_TiledMode_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HIER_DEPTH_BUFFER_TiledMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_HIER_DEPTH_BUFFER_TiledMode_start 54 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HIER_DEPTH_BUFFER_TiledMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 54; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_HIER_DEPTH_BUFFER::Tiled Resource Mode */ #define GFX12_3DSTATE_HIER_DEPTH_BUFFER_TiledResourceMode_bits 2 #define GFX11_3DSTATE_HIER_DEPTH_BUFFER_TiledResourceMode_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HIER_DEPTH_BUFFER_TiledResourceMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 2; case 110: return 2; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_3DSTATE_HIER_DEPTH_BUFFER_TiledResourceMode_start 54 #define GFX11_3DSTATE_HIER_DEPTH_BUFFER_TiledResourceMode_start 55 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HIER_DEPTH_BUFFER_TiledResourceMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 54; case 110: return 55; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_HS */ #define GFX125_3DSTATE_HS_length 9 #define GFX12_3DSTATE_HS_length 9 #define GFX11_3DSTATE_HS_length 9 #define GFX9_3DSTATE_HS_length 9 #define GFX8_3DSTATE_HS_length 9 #define GFX75_3DSTATE_HS_length 7 #define GFX7_3DSTATE_HS_length 7 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HS_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 9; case 120: return 9; case 110: return 9; case 90: return 9; case 80: return 9; case 75: return 7; case 70: return 7; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_HS::3D Command Opcode */ #define GFX125_3DSTATE_HS_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_HS_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_HS_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_HS_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_HS_3DCommandOpcode_bits 3 #define GFX75_3DSTATE_HS_3DCommandOpcode_bits 3 #define GFX7_3DSTATE_HS_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HS_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_HS_3DCommandOpcode_start 24 #define GFX12_3DSTATE_HS_3DCommandOpcode_start 24 #define GFX11_3DSTATE_HS_3DCommandOpcode_start 24 #define GFX9_3DSTATE_HS_3DCommandOpcode_start 24 #define GFX8_3DSTATE_HS_3DCommandOpcode_start 24 #define GFX75_3DSTATE_HS_3DCommandOpcode_start 24 #define GFX7_3DSTATE_HS_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HS_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_HS::3D Command Sub Opcode */ #define GFX125_3DSTATE_HS_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_HS_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_HS_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_HS_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_HS_3DCommandSubOpcode_bits 8 #define GFX75_3DSTATE_HS_3DCommandSubOpcode_bits 8 #define GFX7_3DSTATE_HS_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HS_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_HS_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_HS_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_HS_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_HS_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_HS_3DCommandSubOpcode_start 16 #define GFX75_3DSTATE_HS_3DCommandSubOpcode_start 16 #define GFX7_3DSTATE_HS_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HS_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_HS::Accesses UAV */ #define GFX125_3DSTATE_HS_AccessesUAV_bits 1 #define GFX12_3DSTATE_HS_AccessesUAV_bits 1 #define GFX11_3DSTATE_HS_AccessesUAV_bits 1 #define GFX9_3DSTATE_HS_AccessesUAV_bits 1 #define GFX8_3DSTATE_HS_AccessesUAV_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HS_AccessesUAV_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_HS_AccessesUAV_start 249 #define GFX12_3DSTATE_HS_AccessesUAV_start 249 #define GFX11_3DSTATE_HS_AccessesUAV_start 249 #define GFX9_3DSTATE_HS_AccessesUAV_start 249 #define GFX8_3DSTATE_HS_AccessesUAV_start 249 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HS_AccessesUAV_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 249; case 120: return 249; case 110: return 249; case 90: return 249; case 80: return 249; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_HS::Binding Table Entry Count */ #define GFX125_3DSTATE_HS_BindingTableEntryCount_bits 8 #define GFX12_3DSTATE_HS_BindingTableEntryCount_bits 8 #define GFX11_3DSTATE_HS_BindingTableEntryCount_bits 8 #define GFX9_3DSTATE_HS_BindingTableEntryCount_bits 8 #define GFX8_3DSTATE_HS_BindingTableEntryCount_bits 8 #define GFX75_3DSTATE_HS_BindingTableEntryCount_bits 8 #define GFX7_3DSTATE_HS_BindingTableEntryCount_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HS_BindingTableEntryCount_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_HS_BindingTableEntryCount_start 50 #define GFX12_3DSTATE_HS_BindingTableEntryCount_start 50 #define GFX11_3DSTATE_HS_BindingTableEntryCount_start 50 #define GFX9_3DSTATE_HS_BindingTableEntryCount_start 50 #define GFX8_3DSTATE_HS_BindingTableEntryCount_start 50 #define GFX75_3DSTATE_HS_BindingTableEntryCount_start 50 #define GFX7_3DSTATE_HS_BindingTableEntryCount_start 50 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HS_BindingTableEntryCount_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 50; case 120: return 50; case 110: return 50; case 90: return 50; case 80: return 50; case 75: return 50; case 70: return 50; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_HS::Command SubType */ #define GFX125_3DSTATE_HS_CommandSubType_bits 2 #define GFX12_3DSTATE_HS_CommandSubType_bits 2 #define GFX11_3DSTATE_HS_CommandSubType_bits 2 #define GFX9_3DSTATE_HS_CommandSubType_bits 2 #define GFX8_3DSTATE_HS_CommandSubType_bits 2 #define GFX75_3DSTATE_HS_CommandSubType_bits 2 #define GFX7_3DSTATE_HS_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HS_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_HS_CommandSubType_start 27 #define GFX12_3DSTATE_HS_CommandSubType_start 27 #define GFX11_3DSTATE_HS_CommandSubType_start 27 #define GFX9_3DSTATE_HS_CommandSubType_start 27 #define GFX8_3DSTATE_HS_CommandSubType_start 27 #define GFX75_3DSTATE_HS_CommandSubType_start 27 #define GFX7_3DSTATE_HS_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HS_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_HS::Command Type */ #define GFX125_3DSTATE_HS_CommandType_bits 3 #define GFX12_3DSTATE_HS_CommandType_bits 3 #define GFX11_3DSTATE_HS_CommandType_bits 3 #define GFX9_3DSTATE_HS_CommandType_bits 3 #define GFX8_3DSTATE_HS_CommandType_bits 3 #define GFX75_3DSTATE_HS_CommandType_bits 3 #define GFX7_3DSTATE_HS_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HS_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_HS_CommandType_start 29 #define GFX12_3DSTATE_HS_CommandType_start 29 #define GFX11_3DSTATE_HS_CommandType_start 29 #define GFX9_3DSTATE_HS_CommandType_start 29 #define GFX8_3DSTATE_HS_CommandType_start 29 #define GFX75_3DSTATE_HS_CommandType_start 29 #define GFX7_3DSTATE_HS_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HS_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_HS::DWord Length */ #define GFX125_3DSTATE_HS_DWordLength_bits 8 #define GFX12_3DSTATE_HS_DWordLength_bits 8 #define GFX11_3DSTATE_HS_DWordLength_bits 8 #define GFX9_3DSTATE_HS_DWordLength_bits 8 #define GFX8_3DSTATE_HS_DWordLength_bits 8 #define GFX75_3DSTATE_HS_DWordLength_bits 8 #define GFX7_3DSTATE_HS_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HS_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_HS_DWordLength_start 0 #define GFX12_3DSTATE_HS_DWordLength_start 0 #define GFX11_3DSTATE_HS_DWordLength_start 0 #define GFX9_3DSTATE_HS_DWordLength_start 0 #define GFX8_3DSTATE_HS_DWordLength_start 0 #define GFX75_3DSTATE_HS_DWordLength_start 0 #define GFX7_3DSTATE_HS_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HS_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_HS::Dispatch GRF Start Register For URB Data */ #define GFX125_3DSTATE_HS_DispatchGRFStartRegisterForURBData_bits 5 #define GFX12_3DSTATE_HS_DispatchGRFStartRegisterForURBData_bits 5 #define GFX11_3DSTATE_HS_DispatchGRFStartRegisterForURBData_bits 5 #define GFX9_3DSTATE_HS_DispatchGRFStartRegisterForURBData_bits 5 #define GFX8_3DSTATE_HS_DispatchGRFStartRegisterForURBData_bits 5 #define GFX75_3DSTATE_HS_DispatchGRFStartRegisterForURBData_bits 5 #define GFX7_3DSTATE_HS_DispatchGRFStartRegisterForURBData_bits 5 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HS_DispatchGRFStartRegisterForURBData_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 5; case 110: return 5; case 90: return 5; case 80: return 5; case 75: return 5; case 70: return 5; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_HS_DispatchGRFStartRegisterForURBData_start 243 #define GFX12_3DSTATE_HS_DispatchGRFStartRegisterForURBData_start 243 #define GFX11_3DSTATE_HS_DispatchGRFStartRegisterForURBData_start 243 #define GFX9_3DSTATE_HS_DispatchGRFStartRegisterForURBData_start 243 #define GFX8_3DSTATE_HS_DispatchGRFStartRegisterForURBData_start 243 #define GFX75_3DSTATE_HS_DispatchGRFStartRegisterForURBData_start 179 #define GFX7_3DSTATE_HS_DispatchGRFStartRegisterForURBData_start 179 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HS_DispatchGRFStartRegisterForURBData_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 243; case 120: return 243; case 110: return 243; case 90: return 243; case 80: return 243; case 75: return 179; case 70: return 179; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_HS::Dispatch GRF Start Register For URB Data [5] */ #define GFX125_3DSTATE_HS_DispatchGRFStartRegisterForURBData5_bits 1 #define GFX12_3DSTATE_HS_DispatchGRFStartRegisterForURBData5_bits 1 #define GFX11_3DSTATE_HS_DispatchGRFStartRegisterForURBData5_bits 1 #define GFX9_3DSTATE_HS_DispatchGRFStartRegisterForURBData5_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HS_DispatchGRFStartRegisterForURBData5_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_HS_DispatchGRFStartRegisterForURBData5_start 252 #define GFX12_3DSTATE_HS_DispatchGRFStartRegisterForURBData5_start 252 #define GFX11_3DSTATE_HS_DispatchGRFStartRegisterForURBData5_start 252 #define GFX9_3DSTATE_HS_DispatchGRFStartRegisterForURBData5_start 252 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HS_DispatchGRFStartRegisterForURBData5_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 252; case 120: return 252; case 110: return 252; case 90: return 252; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_HS::Dispatch Mode */ #define GFX125_3DSTATE_HS_DispatchMode_bits 2 #define GFX12_3DSTATE_HS_DispatchMode_bits 2 #define GFX11_3DSTATE_HS_DispatchMode_bits 2 #define GFX9_3DSTATE_HS_DispatchMode_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HS_DispatchMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_HS_DispatchMode_start 241 #define GFX12_3DSTATE_HS_DispatchMode_start 241 #define GFX11_3DSTATE_HS_DispatchMode_start 241 #define GFX9_3DSTATE_HS_DispatchMode_start 241 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HS_DispatchMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 241; case 120: return 241; case 110: return 241; case 90: return 241; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_HS::Enable */ #define GFX125_3DSTATE_HS_Enable_bits 1 #define GFX12_3DSTATE_HS_Enable_bits 1 #define GFX11_3DSTATE_HS_Enable_bits 1 #define GFX9_3DSTATE_HS_Enable_bits 1 #define GFX8_3DSTATE_HS_Enable_bits 1 #define GFX75_3DSTATE_HS_Enable_bits 1 #define GFX7_3DSTATE_HS_Enable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HS_Enable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_HS_Enable_start 95 #define GFX12_3DSTATE_HS_Enable_start 95 #define GFX11_3DSTATE_HS_Enable_start 95 #define GFX9_3DSTATE_HS_Enable_start 95 #define GFX8_3DSTATE_HS_Enable_start 95 #define GFX75_3DSTATE_HS_Enable_start 95 #define GFX7_3DSTATE_HS_Enable_start 95 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HS_Enable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 95; case 120: return 95; case 110: return 95; case 90: return 95; case 80: return 95; case 75: return 95; case 70: return 95; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_HS::Floating Point Mode */ #define GFX125_3DSTATE_HS_FloatingPointMode_bits 1 #define GFX12_3DSTATE_HS_FloatingPointMode_bits 1 #define GFX11_3DSTATE_HS_FloatingPointMode_bits 1 #define GFX9_3DSTATE_HS_FloatingPointMode_bits 1 #define GFX8_3DSTATE_HS_FloatingPointMode_bits 1 #define GFX75_3DSTATE_HS_FloatingPointMode_bits 1 #define GFX7_3DSTATE_HS_FloatingPointMode_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HS_FloatingPointMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_HS_FloatingPointMode_start 48 #define GFX12_3DSTATE_HS_FloatingPointMode_start 48 #define GFX11_3DSTATE_HS_FloatingPointMode_start 48 #define GFX9_3DSTATE_HS_FloatingPointMode_start 48 #define GFX8_3DSTATE_HS_FloatingPointMode_start 48 #define GFX75_3DSTATE_HS_FloatingPointMode_start 48 #define GFX7_3DSTATE_HS_FloatingPointMode_start 48 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HS_FloatingPointMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 48; case 120: return 48; case 110: return 48; case 90: return 48; case 80: return 48; case 75: return 48; case 70: return 48; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_HS::HS accesses UAV */ #define GFX75_3DSTATE_HS_HSaccessesUAV_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HS_HSaccessesUAV_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_HS_HSaccessesUAV_start 185 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HS_HSaccessesUAV_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 185; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_HS::Illegal Opcode Exception Enable */ #define GFX125_3DSTATE_HS_IllegalOpcodeExceptionEnable_bits 1 #define GFX12_3DSTATE_HS_IllegalOpcodeExceptionEnable_bits 1 #define GFX11_3DSTATE_HS_IllegalOpcodeExceptionEnable_bits 1 #define GFX9_3DSTATE_HS_IllegalOpcodeExceptionEnable_bits 1 #define GFX8_3DSTATE_HS_IllegalOpcodeExceptionEnable_bits 1 #define GFX75_3DSTATE_HS_IllegalOpcodeExceptionEnable_bits 1 #define GFX7_3DSTATE_HS_IllegalOpcodeExceptionEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HS_IllegalOpcodeExceptionEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_HS_IllegalOpcodeExceptionEnable_start 45 #define GFX12_3DSTATE_HS_IllegalOpcodeExceptionEnable_start 45 #define GFX11_3DSTATE_HS_IllegalOpcodeExceptionEnable_start 45 #define GFX9_3DSTATE_HS_IllegalOpcodeExceptionEnable_start 45 #define GFX8_3DSTATE_HS_IllegalOpcodeExceptionEnable_start 45 #define GFX75_3DSTATE_HS_IllegalOpcodeExceptionEnable_start 45 #define GFX7_3DSTATE_HS_IllegalOpcodeExceptionEnable_start 45 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HS_IllegalOpcodeExceptionEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 45; case 120: return 45; case 110: return 45; case 90: return 45; case 80: return 45; case 75: return 45; case 70: return 45; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_HS::Include Primitive ID */ #define GFX125_3DSTATE_HS_IncludePrimitiveID_bits 1 #define GFX12_3DSTATE_HS_IncludePrimitiveID_bits 1 #define GFX11_3DSTATE_HS_IncludePrimitiveID_bits 1 #define GFX9_3DSTATE_HS_IncludePrimitiveID_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HS_IncludePrimitiveID_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_HS_IncludePrimitiveID_start 224 #define GFX12_3DSTATE_HS_IncludePrimitiveID_start 224 #define GFX11_3DSTATE_HS_IncludePrimitiveID_start 224 #define GFX9_3DSTATE_HS_IncludePrimitiveID_start 224 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HS_IncludePrimitiveID_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 224; case 120: return 224; case 110: return 224; case 90: return 224; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_HS::Include Vertex Handles */ #define GFX125_3DSTATE_HS_IncludeVertexHandles_bits 1 #define GFX12_3DSTATE_HS_IncludeVertexHandles_bits 1 #define GFX11_3DSTATE_HS_IncludeVertexHandles_bits 1 #define GFX9_3DSTATE_HS_IncludeVertexHandles_bits 1 #define GFX8_3DSTATE_HS_IncludeVertexHandles_bits 1 #define GFX75_3DSTATE_HS_IncludeVertexHandles_bits 1 #define GFX7_3DSTATE_HS_IncludeVertexHandles_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HS_IncludeVertexHandles_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_HS_IncludeVertexHandles_start 248 #define GFX12_3DSTATE_HS_IncludeVertexHandles_start 248 #define GFX11_3DSTATE_HS_IncludeVertexHandles_start 248 #define GFX9_3DSTATE_HS_IncludeVertexHandles_start 248 #define GFX8_3DSTATE_HS_IncludeVertexHandles_start 248 #define GFX75_3DSTATE_HS_IncludeVertexHandles_start 184 #define GFX7_3DSTATE_HS_IncludeVertexHandles_start 184 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HS_IncludeVertexHandles_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 248; case 120: return 248; case 110: return 248; case 90: return 248; case 80: return 248; case 75: return 184; case 70: return 184; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_HS::Instance Count */ #define GFX125_3DSTATE_HS_InstanceCount_bits 5 #define GFX12_3DSTATE_HS_InstanceCount_bits 5 #define GFX11_3DSTATE_HS_InstanceCount_bits 4 #define GFX9_3DSTATE_HS_InstanceCount_bits 4 #define GFX8_3DSTATE_HS_InstanceCount_bits 4 #define GFX75_3DSTATE_HS_InstanceCount_bits 4 #define GFX7_3DSTATE_HS_InstanceCount_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HS_InstanceCount_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 5; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 4; case 70: return 4; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_HS_InstanceCount_start 64 #define GFX12_3DSTATE_HS_InstanceCount_start 64 #define GFX11_3DSTATE_HS_InstanceCount_start 64 #define GFX9_3DSTATE_HS_InstanceCount_start 64 #define GFX8_3DSTATE_HS_InstanceCount_start 64 #define GFX75_3DSTATE_HS_InstanceCount_start 64 #define GFX7_3DSTATE_HS_InstanceCount_start 64 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HS_InstanceCount_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 64; case 80: return 64; case 75: return 64; case 70: return 64; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_HS::Kernel Start Pointer */ #define GFX125_3DSTATE_HS_KernelStartPointer_bits 58 #define GFX12_3DSTATE_HS_KernelStartPointer_bits 58 #define GFX11_3DSTATE_HS_KernelStartPointer_bits 58 #define GFX9_3DSTATE_HS_KernelStartPointer_bits 58 #define GFX8_3DSTATE_HS_KernelStartPointer_bits 58 #define GFX75_3DSTATE_HS_KernelStartPointer_bits 26 #define GFX7_3DSTATE_HS_KernelStartPointer_bits 26 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HS_KernelStartPointer_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 58; case 120: return 58; case 110: return 58; case 90: return 58; case 80: return 58; case 75: return 26; case 70: return 26; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_HS_KernelStartPointer_start 102 #define GFX12_3DSTATE_HS_KernelStartPointer_start 102 #define GFX11_3DSTATE_HS_KernelStartPointer_start 102 #define GFX9_3DSTATE_HS_KernelStartPointer_start 102 #define GFX8_3DSTATE_HS_KernelStartPointer_start 102 #define GFX75_3DSTATE_HS_KernelStartPointer_start 102 #define GFX7_3DSTATE_HS_KernelStartPointer_start 102 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HS_KernelStartPointer_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 102; case 120: return 102; case 110: return 102; case 90: return 102; case 80: return 102; case 75: return 102; case 70: return 102; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_HS::Maximum Number of Threads */ #define GFX125_3DSTATE_HS_MaximumNumberofThreads_bits 9 #define GFX12_3DSTATE_HS_MaximumNumberofThreads_bits 9 #define GFX11_3DSTATE_HS_MaximumNumberofThreads_bits 9 #define GFX9_3DSTATE_HS_MaximumNumberofThreads_bits 9 #define GFX8_3DSTATE_HS_MaximumNumberofThreads_bits 9 #define GFX75_3DSTATE_HS_MaximumNumberofThreads_bits 8 #define GFX7_3DSTATE_HS_MaximumNumberofThreads_bits 7 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HS_MaximumNumberofThreads_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 9; case 120: return 9; case 110: return 9; case 90: return 9; case 80: return 9; case 75: return 8; case 70: return 7; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_HS_MaximumNumberofThreads_start 72 #define GFX12_3DSTATE_HS_MaximumNumberofThreads_start 72 #define GFX11_3DSTATE_HS_MaximumNumberofThreads_start 72 #define GFX9_3DSTATE_HS_MaximumNumberofThreads_start 72 #define GFX8_3DSTATE_HS_MaximumNumberofThreads_start 72 #define GFX75_3DSTATE_HS_MaximumNumberofThreads_start 32 #define GFX7_3DSTATE_HS_MaximumNumberofThreads_start 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HS_MaximumNumberofThreads_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 72; case 120: return 72; case 110: return 72; case 90: return 72; case 80: return 72; case 75: return 32; case 70: return 32; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_HS::Patch Count Threshold */ #define GFX125_3DSTATE_HS_PatchCountThreshold_bits 3 #define GFX12_3DSTATE_HS_PatchCountThreshold_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HS_PatchCountThreshold_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_HS_PatchCountThreshold_start 225 #define GFX12_3DSTATE_HS_PatchCountThreshold_start 225 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HS_PatchCountThreshold_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 225; case 120: return 225; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_HS::Per-Thread Scratch Space */ #define GFX12_3DSTATE_HS_PerThreadScratchSpace_bits 4 #define GFX11_3DSTATE_HS_PerThreadScratchSpace_bits 4 #define GFX9_3DSTATE_HS_PerThreadScratchSpace_bits 4 #define GFX8_3DSTATE_HS_PerThreadScratchSpace_bits 4 #define GFX75_3DSTATE_HS_PerThreadScratchSpace_bits 4 #define GFX7_3DSTATE_HS_PerThreadScratchSpace_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HS_PerThreadScratchSpace_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 4; case 70: return 4; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_3DSTATE_HS_PerThreadScratchSpace_start 160 #define GFX11_3DSTATE_HS_PerThreadScratchSpace_start 160 #define GFX9_3DSTATE_HS_PerThreadScratchSpace_start 160 #define GFX8_3DSTATE_HS_PerThreadScratchSpace_start 160 #define GFX75_3DSTATE_HS_PerThreadScratchSpace_start 128 #define GFX7_3DSTATE_HS_PerThreadScratchSpace_start 128 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HS_PerThreadScratchSpace_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 160; case 110: return 160; case 90: return 160; case 80: return 160; case 75: return 128; case 70: return 128; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_HS::Sampler Count */ #define GFX125_3DSTATE_HS_SamplerCount_bits 3 #define GFX12_3DSTATE_HS_SamplerCount_bits 3 #define GFX11_3DSTATE_HS_SamplerCount_bits 3 #define GFX9_3DSTATE_HS_SamplerCount_bits 3 #define GFX8_3DSTATE_HS_SamplerCount_bits 3 #define GFX75_3DSTATE_HS_SamplerCount_bits 3 #define GFX7_3DSTATE_HS_SamplerCount_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HS_SamplerCount_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_HS_SamplerCount_start 59 #define GFX12_3DSTATE_HS_SamplerCount_start 59 #define GFX11_3DSTATE_HS_SamplerCount_start 59 #define GFX9_3DSTATE_HS_SamplerCount_start 59 #define GFX8_3DSTATE_HS_SamplerCount_start 59 #define GFX75_3DSTATE_HS_SamplerCount_start 59 #define GFX7_3DSTATE_HS_SamplerCount_start 59 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HS_SamplerCount_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 59; case 120: return 59; case 110: return 59; case 90: return 59; case 80: return 59; case 75: return 59; case 70: return 59; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_HS::Scratch Space Base Pointer */ #define GFX12_3DSTATE_HS_ScratchSpaceBasePointer_bits 54 #define GFX11_3DSTATE_HS_ScratchSpaceBasePointer_bits 54 #define GFX9_3DSTATE_HS_ScratchSpaceBasePointer_bits 54 #define GFX8_3DSTATE_HS_ScratchSpaceBasePointer_bits 54 #define GFX75_3DSTATE_HS_ScratchSpaceBasePointer_bits 22 #define GFX7_3DSTATE_HS_ScratchSpaceBasePointer_bits 22 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HS_ScratchSpaceBasePointer_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 54; case 110: return 54; case 90: return 54; case 80: return 54; case 75: return 22; case 70: return 22; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_3DSTATE_HS_ScratchSpaceBasePointer_start 170 #define GFX11_3DSTATE_HS_ScratchSpaceBasePointer_start 170 #define GFX9_3DSTATE_HS_ScratchSpaceBasePointer_start 170 #define GFX8_3DSTATE_HS_ScratchSpaceBasePointer_start 170 #define GFX75_3DSTATE_HS_ScratchSpaceBasePointer_start 138 #define GFX7_3DSTATE_HS_ScratchSpaceBasePointer_start 138 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HS_ScratchSpaceBasePointer_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 170; case 110: return 170; case 90: return 170; case 80: return 170; case 75: return 138; case 70: return 138; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_HS::Scratch Space Buffer */ #define GFX125_3DSTATE_HS_ScratchSpaceBuffer_bits 22 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HS_ScratchSpaceBuffer_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 22; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_HS_ScratchSpaceBuffer_start 170 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HS_ScratchSpaceBuffer_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 170; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_HS::Semaphore Handle */ #define GFX75_3DSTATE_HS_SemaphoreHandle_bits 13 #define GFX7_3DSTATE_HS_SemaphoreHandle_bits 12 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HS_SemaphoreHandle_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 13; case 70: return 12; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_HS_SemaphoreHandle_start 192 #define GFX7_3DSTATE_HS_SemaphoreHandle_start 192 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HS_SemaphoreHandle_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 192; case 70: return 192; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_HS::Single Program Flow */ #define GFX125_3DSTATE_HS_SingleProgramFlow_bits 1 #define GFX12_3DSTATE_HS_SingleProgramFlow_bits 1 #define GFX11_3DSTATE_HS_SingleProgramFlow_bits 1 #define GFX9_3DSTATE_HS_SingleProgramFlow_bits 1 #define GFX8_3DSTATE_HS_SingleProgramFlow_bits 1 #define GFX75_3DSTATE_HS_SingleProgramFlow_bits 1 #define GFX7_3DSTATE_HS_SingleProgramFlow_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HS_SingleProgramFlow_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_HS_SingleProgramFlow_start 251 #define GFX12_3DSTATE_HS_SingleProgramFlow_start 251 #define GFX11_3DSTATE_HS_SingleProgramFlow_start 251 #define GFX9_3DSTATE_HS_SingleProgramFlow_start 251 #define GFX8_3DSTATE_HS_SingleProgramFlow_start 251 #define GFX75_3DSTATE_HS_SingleProgramFlow_start 187 #define GFX7_3DSTATE_HS_SingleProgramFlow_start 187 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HS_SingleProgramFlow_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 251; case 120: return 251; case 110: return 251; case 90: return 251; case 80: return 251; case 75: return 187; case 70: return 187; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_HS::Software Exception Enable */ #define GFX125_3DSTATE_HS_SoftwareExceptionEnable_bits 1 #define GFX12_3DSTATE_HS_SoftwareExceptionEnable_bits 1 #define GFX11_3DSTATE_HS_SoftwareExceptionEnable_bits 1 #define GFX9_3DSTATE_HS_SoftwareExceptionEnable_bits 1 #define GFX8_3DSTATE_HS_SoftwareExceptionEnable_bits 1 #define GFX75_3DSTATE_HS_SoftwareExceptionEnable_bits 1 #define GFX7_3DSTATE_HS_SoftwareExceptionEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HS_SoftwareExceptionEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_HS_SoftwareExceptionEnable_start 44 #define GFX12_3DSTATE_HS_SoftwareExceptionEnable_start 44 #define GFX11_3DSTATE_HS_SoftwareExceptionEnable_start 44 #define GFX9_3DSTATE_HS_SoftwareExceptionEnable_start 44 #define GFX8_3DSTATE_HS_SoftwareExceptionEnable_start 44 #define GFX75_3DSTATE_HS_SoftwareExceptionEnable_start 44 #define GFX7_3DSTATE_HS_SoftwareExceptionEnable_start 39 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HS_SoftwareExceptionEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 44; case 120: return 44; case 110: return 44; case 90: return 44; case 80: return 44; case 75: return 44; case 70: return 39; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_HS::Statistics Enable */ #define GFX125_3DSTATE_HS_StatisticsEnable_bits 1 #define GFX12_3DSTATE_HS_StatisticsEnable_bits 1 #define GFX11_3DSTATE_HS_StatisticsEnable_bits 1 #define GFX9_3DSTATE_HS_StatisticsEnable_bits 1 #define GFX8_3DSTATE_HS_StatisticsEnable_bits 1 #define GFX75_3DSTATE_HS_StatisticsEnable_bits 1 #define GFX7_3DSTATE_HS_StatisticsEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HS_StatisticsEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_HS_StatisticsEnable_start 93 #define GFX12_3DSTATE_HS_StatisticsEnable_start 93 #define GFX11_3DSTATE_HS_StatisticsEnable_start 93 #define GFX9_3DSTATE_HS_StatisticsEnable_start 93 #define GFX8_3DSTATE_HS_StatisticsEnable_start 93 #define GFX75_3DSTATE_HS_StatisticsEnable_start 93 #define GFX7_3DSTATE_HS_StatisticsEnable_start 93 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HS_StatisticsEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 93; case 120: return 93; case 110: return 93; case 90: return 93; case 80: return 93; case 75: return 93; case 70: return 93; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_HS::Thread Dispatch Priority */ #define GFX125_3DSTATE_HS_ThreadDispatchPriority_bits 1 #define GFX12_3DSTATE_HS_ThreadDispatchPriority_bits 1 #define GFX11_3DSTATE_HS_ThreadDispatchPriority_bits 1 #define GFX9_3DSTATE_HS_ThreadDispatchPriority_bits 1 #define GFX8_3DSTATE_HS_ThreadDispatchPriority_bits 1 #define GFX75_3DSTATE_HS_ThreadDispatchPriority_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HS_ThreadDispatchPriority_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_HS_ThreadDispatchPriority_start 49 #define GFX12_3DSTATE_HS_ThreadDispatchPriority_start 49 #define GFX11_3DSTATE_HS_ThreadDispatchPriority_start 49 #define GFX9_3DSTATE_HS_ThreadDispatchPriority_start 49 #define GFX8_3DSTATE_HS_ThreadDispatchPriority_start 49 #define GFX75_3DSTATE_HS_ThreadDispatchPriority_start 49 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HS_ThreadDispatchPriority_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 49; case 120: return 49; case 110: return 49; case 90: return 49; case 80: return 49; case 75: return 49; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_HS::Vector Mask Enable */ #define GFX125_3DSTATE_HS_VectorMaskEnable_bits 1 #define GFX12_3DSTATE_HS_VectorMaskEnable_bits 1 #define GFX11_3DSTATE_HS_VectorMaskEnable_bits 1 #define GFX9_3DSTATE_HS_VectorMaskEnable_bits 1 #define GFX8_3DSTATE_HS_VectorMaskEnable_bits 1 #define GFX75_3DSTATE_HS_VectorMaskEnable_bits 1 #define GFX7_3DSTATE_HS_VectorMaskEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HS_VectorMaskEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_HS_VectorMaskEnable_start 250 #define GFX12_3DSTATE_HS_VectorMaskEnable_start 250 #define GFX11_3DSTATE_HS_VectorMaskEnable_start 250 #define GFX9_3DSTATE_HS_VectorMaskEnable_start 250 #define GFX8_3DSTATE_HS_VectorMaskEnable_start 250 #define GFX75_3DSTATE_HS_VectorMaskEnable_start 186 #define GFX7_3DSTATE_HS_VectorMaskEnable_start 186 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HS_VectorMaskEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 250; case 120: return 250; case 110: return 250; case 90: return 250; case 80: return 250; case 75: return 186; case 70: return 186; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_HS::Vertex URB Entry Read Length */ #define GFX125_3DSTATE_HS_VertexURBEntryReadLength_bits 6 #define GFX12_3DSTATE_HS_VertexURBEntryReadLength_bits 6 #define GFX11_3DSTATE_HS_VertexURBEntryReadLength_bits 6 #define GFX9_3DSTATE_HS_VertexURBEntryReadLength_bits 6 #define GFX8_3DSTATE_HS_VertexURBEntryReadLength_bits 6 #define GFX75_3DSTATE_HS_VertexURBEntryReadLength_bits 6 #define GFX7_3DSTATE_HS_VertexURBEntryReadLength_bits 6 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HS_VertexURBEntryReadLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 6; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_HS_VertexURBEntryReadLength_start 235 #define GFX12_3DSTATE_HS_VertexURBEntryReadLength_start 235 #define GFX11_3DSTATE_HS_VertexURBEntryReadLength_start 235 #define GFX9_3DSTATE_HS_VertexURBEntryReadLength_start 235 #define GFX8_3DSTATE_HS_VertexURBEntryReadLength_start 235 #define GFX75_3DSTATE_HS_VertexURBEntryReadLength_start 171 #define GFX7_3DSTATE_HS_VertexURBEntryReadLength_start 171 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HS_VertexURBEntryReadLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 235; case 120: return 235; case 110: return 235; case 90: return 235; case 80: return 235; case 75: return 171; case 70: return 171; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_HS::Vertex URB Entry Read Offset */ #define GFX125_3DSTATE_HS_VertexURBEntryReadOffset_bits 6 #define GFX12_3DSTATE_HS_VertexURBEntryReadOffset_bits 6 #define GFX11_3DSTATE_HS_VertexURBEntryReadOffset_bits 6 #define GFX9_3DSTATE_HS_VertexURBEntryReadOffset_bits 6 #define GFX8_3DSTATE_HS_VertexURBEntryReadOffset_bits 6 #define GFX75_3DSTATE_HS_VertexURBEntryReadOffset_bits 6 #define GFX7_3DSTATE_HS_VertexURBEntryReadOffset_bits 6 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HS_VertexURBEntryReadOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 6; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_HS_VertexURBEntryReadOffset_start 228 #define GFX12_3DSTATE_HS_VertexURBEntryReadOffset_start 228 #define GFX11_3DSTATE_HS_VertexURBEntryReadOffset_start 228 #define GFX9_3DSTATE_HS_VertexURBEntryReadOffset_start 228 #define GFX8_3DSTATE_HS_VertexURBEntryReadOffset_start 228 #define GFX75_3DSTATE_HS_VertexURBEntryReadOffset_start 164 #define GFX7_3DSTATE_HS_VertexURBEntryReadOffset_start 164 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_HS_VertexURBEntryReadOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 228; case 120: return 228; case 110: return 228; case 90: return 228; case 80: return 228; case 75: return 164; case 70: return 164; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_INDEX_BUFFER */ #define GFX125_3DSTATE_INDEX_BUFFER_length 5 #define GFX12_3DSTATE_INDEX_BUFFER_length 5 #define GFX11_3DSTATE_INDEX_BUFFER_length 5 #define GFX9_3DSTATE_INDEX_BUFFER_length 5 #define GFX8_3DSTATE_INDEX_BUFFER_length 5 #define GFX75_3DSTATE_INDEX_BUFFER_length 3 #define GFX7_3DSTATE_INDEX_BUFFER_length 3 #define GFX6_3DSTATE_INDEX_BUFFER_length 3 #define GFX5_3DSTATE_INDEX_BUFFER_length 3 #define GFX45_3DSTATE_INDEX_BUFFER_length 3 #define GFX4_3DSTATE_INDEX_BUFFER_length 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_INDEX_BUFFER_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 5; case 110: return 5; case 90: return 5; case 80: return 5; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_INDEX_BUFFER::3D Command Opcode */ #define GFX125_3DSTATE_INDEX_BUFFER_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_INDEX_BUFFER_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_INDEX_BUFFER_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_INDEX_BUFFER_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_INDEX_BUFFER_3DCommandOpcode_bits 3 #define GFX75_3DSTATE_INDEX_BUFFER_3DCommandOpcode_bits 3 #define GFX7_3DSTATE_INDEX_BUFFER_3DCommandOpcode_bits 3 #define GFX6_3DSTATE_INDEX_BUFFER_3DCommandOpcode_bits 3 #define GFX5_3DSTATE_INDEX_BUFFER_3DCommandOpcode_bits 3 #define GFX45_3DSTATE_INDEX_BUFFER_3DCommandOpcode_bits 3 #define GFX4_3DSTATE_INDEX_BUFFER_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_INDEX_BUFFER_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_INDEX_BUFFER_3DCommandOpcode_start 24 #define GFX12_3DSTATE_INDEX_BUFFER_3DCommandOpcode_start 24 #define GFX11_3DSTATE_INDEX_BUFFER_3DCommandOpcode_start 24 #define GFX9_3DSTATE_INDEX_BUFFER_3DCommandOpcode_start 24 #define GFX8_3DSTATE_INDEX_BUFFER_3DCommandOpcode_start 24 #define GFX75_3DSTATE_INDEX_BUFFER_3DCommandOpcode_start 24 #define GFX7_3DSTATE_INDEX_BUFFER_3DCommandOpcode_start 24 #define GFX6_3DSTATE_INDEX_BUFFER_3DCommandOpcode_start 24 #define GFX5_3DSTATE_INDEX_BUFFER_3DCommandOpcode_start 24 #define GFX45_3DSTATE_INDEX_BUFFER_3DCommandOpcode_start 24 #define GFX4_3DSTATE_INDEX_BUFFER_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_INDEX_BUFFER_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 24; case 50: return 24; case 45: return 24; case 40: return 24; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_INDEX_BUFFER::3D Command Sub Opcode */ #define GFX125_3DSTATE_INDEX_BUFFER_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_INDEX_BUFFER_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_INDEX_BUFFER_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_INDEX_BUFFER_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_INDEX_BUFFER_3DCommandSubOpcode_bits 8 #define GFX75_3DSTATE_INDEX_BUFFER_3DCommandSubOpcode_bits 8 #define GFX7_3DSTATE_INDEX_BUFFER_3DCommandSubOpcode_bits 8 #define GFX6_3DSTATE_INDEX_BUFFER_3DCommandSubOpcode_bits 8 #define GFX5_3DSTATE_INDEX_BUFFER_3DCommandSubOpcode_bits 8 #define GFX45_3DSTATE_INDEX_BUFFER_3DCommandSubOpcode_bits 8 #define GFX4_3DSTATE_INDEX_BUFFER_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_INDEX_BUFFER_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 8; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_INDEX_BUFFER_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_INDEX_BUFFER_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_INDEX_BUFFER_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_INDEX_BUFFER_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_INDEX_BUFFER_3DCommandSubOpcode_start 16 #define GFX75_3DSTATE_INDEX_BUFFER_3DCommandSubOpcode_start 16 #define GFX7_3DSTATE_INDEX_BUFFER_3DCommandSubOpcode_start 16 #define GFX6_3DSTATE_INDEX_BUFFER_3DCommandSubOpcode_start 16 #define GFX5_3DSTATE_INDEX_BUFFER_3DCommandSubOpcode_start 16 #define GFX45_3DSTATE_INDEX_BUFFER_3DCommandSubOpcode_start 16 #define GFX4_3DSTATE_INDEX_BUFFER_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_INDEX_BUFFER_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 16; case 50: return 16; case 45: return 16; case 40: return 16; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_INDEX_BUFFER::Buffer Ending Address */ #define GFX75_3DSTATE_INDEX_BUFFER_BufferEndingAddress_bits 32 #define GFX7_3DSTATE_INDEX_BUFFER_BufferEndingAddress_bits 32 #define GFX6_3DSTATE_INDEX_BUFFER_BufferEndingAddress_bits 32 #define GFX5_3DSTATE_INDEX_BUFFER_BufferEndingAddress_bits 32 #define GFX45_3DSTATE_INDEX_BUFFER_BufferEndingAddress_bits 32 #define GFX4_3DSTATE_INDEX_BUFFER_BufferEndingAddress_bits 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_INDEX_BUFFER_BufferEndingAddress_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 32; case 70: return 32; case 60: return 32; case 50: return 32; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_INDEX_BUFFER_BufferEndingAddress_start 64 #define GFX7_3DSTATE_INDEX_BUFFER_BufferEndingAddress_start 64 #define GFX6_3DSTATE_INDEX_BUFFER_BufferEndingAddress_start 64 #define GFX5_3DSTATE_INDEX_BUFFER_BufferEndingAddress_start 64 #define GFX45_3DSTATE_INDEX_BUFFER_BufferEndingAddress_start 64 #define GFX4_3DSTATE_INDEX_BUFFER_BufferEndingAddress_start 64 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_INDEX_BUFFER_BufferEndingAddress_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 64; case 70: return 64; case 60: return 64; case 50: return 64; case 45: return 64; case 40: return 64; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_INDEX_BUFFER::Buffer Size */ #define GFX125_3DSTATE_INDEX_BUFFER_BufferSize_bits 32 #define GFX12_3DSTATE_INDEX_BUFFER_BufferSize_bits 32 #define GFX11_3DSTATE_INDEX_BUFFER_BufferSize_bits 32 #define GFX9_3DSTATE_INDEX_BUFFER_BufferSize_bits 32 #define GFX8_3DSTATE_INDEX_BUFFER_BufferSize_bits 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_INDEX_BUFFER_BufferSize_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_INDEX_BUFFER_BufferSize_start 128 #define GFX12_3DSTATE_INDEX_BUFFER_BufferSize_start 128 #define GFX11_3DSTATE_INDEX_BUFFER_BufferSize_start 128 #define GFX9_3DSTATE_INDEX_BUFFER_BufferSize_start 128 #define GFX8_3DSTATE_INDEX_BUFFER_BufferSize_start 128 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_INDEX_BUFFER_BufferSize_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 128; case 120: return 128; case 110: return 128; case 90: return 128; case 80: return 128; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_INDEX_BUFFER::Buffer Starting Address */ #define GFX125_3DSTATE_INDEX_BUFFER_BufferStartingAddress_bits 64 #define GFX12_3DSTATE_INDEX_BUFFER_BufferStartingAddress_bits 64 #define GFX11_3DSTATE_INDEX_BUFFER_BufferStartingAddress_bits 64 #define GFX9_3DSTATE_INDEX_BUFFER_BufferStartingAddress_bits 64 #define GFX8_3DSTATE_INDEX_BUFFER_BufferStartingAddress_bits 64 #define GFX75_3DSTATE_INDEX_BUFFER_BufferStartingAddress_bits 32 #define GFX7_3DSTATE_INDEX_BUFFER_BufferStartingAddress_bits 32 #define GFX6_3DSTATE_INDEX_BUFFER_BufferStartingAddress_bits 32 #define GFX5_3DSTATE_INDEX_BUFFER_BufferStartingAddress_bits 32 #define GFX45_3DSTATE_INDEX_BUFFER_BufferStartingAddress_bits 32 #define GFX4_3DSTATE_INDEX_BUFFER_BufferStartingAddress_bits 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_INDEX_BUFFER_BufferStartingAddress_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 64; case 80: return 64; case 75: return 32; case 70: return 32; case 60: return 32; case 50: return 32; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_INDEX_BUFFER_BufferStartingAddress_start 64 #define GFX12_3DSTATE_INDEX_BUFFER_BufferStartingAddress_start 64 #define GFX11_3DSTATE_INDEX_BUFFER_BufferStartingAddress_start 64 #define GFX9_3DSTATE_INDEX_BUFFER_BufferStartingAddress_start 64 #define GFX8_3DSTATE_INDEX_BUFFER_BufferStartingAddress_start 64 #define GFX75_3DSTATE_INDEX_BUFFER_BufferStartingAddress_start 32 #define GFX7_3DSTATE_INDEX_BUFFER_BufferStartingAddress_start 32 #define GFX6_3DSTATE_INDEX_BUFFER_BufferStartingAddress_start 32 #define GFX5_3DSTATE_INDEX_BUFFER_BufferStartingAddress_start 32 #define GFX45_3DSTATE_INDEX_BUFFER_BufferStartingAddress_start 32 #define GFX4_3DSTATE_INDEX_BUFFER_BufferStartingAddress_start 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_INDEX_BUFFER_BufferStartingAddress_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 64; case 80: return 64; case 75: return 32; case 70: return 32; case 60: return 32; case 50: return 32; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_INDEX_BUFFER::Command SubType */ #define GFX125_3DSTATE_INDEX_BUFFER_CommandSubType_bits 2 #define GFX12_3DSTATE_INDEX_BUFFER_CommandSubType_bits 2 #define GFX11_3DSTATE_INDEX_BUFFER_CommandSubType_bits 2 #define GFX9_3DSTATE_INDEX_BUFFER_CommandSubType_bits 2 #define GFX8_3DSTATE_INDEX_BUFFER_CommandSubType_bits 2 #define GFX75_3DSTATE_INDEX_BUFFER_CommandSubType_bits 2 #define GFX7_3DSTATE_INDEX_BUFFER_CommandSubType_bits 2 #define GFX6_3DSTATE_INDEX_BUFFER_CommandSubType_bits 2 #define GFX5_3DSTATE_INDEX_BUFFER_CommandSubType_bits 2 #define GFX45_3DSTATE_INDEX_BUFFER_CommandSubType_bits 2 #define GFX4_3DSTATE_INDEX_BUFFER_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_INDEX_BUFFER_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 2; case 45: return 2; case 40: return 2; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_INDEX_BUFFER_CommandSubType_start 27 #define GFX12_3DSTATE_INDEX_BUFFER_CommandSubType_start 27 #define GFX11_3DSTATE_INDEX_BUFFER_CommandSubType_start 27 #define GFX9_3DSTATE_INDEX_BUFFER_CommandSubType_start 27 #define GFX8_3DSTATE_INDEX_BUFFER_CommandSubType_start 27 #define GFX75_3DSTATE_INDEX_BUFFER_CommandSubType_start 27 #define GFX7_3DSTATE_INDEX_BUFFER_CommandSubType_start 27 #define GFX6_3DSTATE_INDEX_BUFFER_CommandSubType_start 27 #define GFX5_3DSTATE_INDEX_BUFFER_CommandSubType_start 27 #define GFX45_3DSTATE_INDEX_BUFFER_CommandSubType_start 27 #define GFX4_3DSTATE_INDEX_BUFFER_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_INDEX_BUFFER_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 27; case 50: return 27; case 45: return 27; case 40: return 27; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_INDEX_BUFFER::Command Type */ #define GFX125_3DSTATE_INDEX_BUFFER_CommandType_bits 3 #define GFX12_3DSTATE_INDEX_BUFFER_CommandType_bits 3 #define GFX11_3DSTATE_INDEX_BUFFER_CommandType_bits 3 #define GFX9_3DSTATE_INDEX_BUFFER_CommandType_bits 3 #define GFX8_3DSTATE_INDEX_BUFFER_CommandType_bits 3 #define GFX75_3DSTATE_INDEX_BUFFER_CommandType_bits 3 #define GFX7_3DSTATE_INDEX_BUFFER_CommandType_bits 3 #define GFX6_3DSTATE_INDEX_BUFFER_CommandType_bits 3 #define GFX5_3DSTATE_INDEX_BUFFER_CommandType_bits 3 #define GFX45_3DSTATE_INDEX_BUFFER_CommandType_bits 3 #define GFX4_3DSTATE_INDEX_BUFFER_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_INDEX_BUFFER_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_INDEX_BUFFER_CommandType_start 29 #define GFX12_3DSTATE_INDEX_BUFFER_CommandType_start 29 #define GFX11_3DSTATE_INDEX_BUFFER_CommandType_start 29 #define GFX9_3DSTATE_INDEX_BUFFER_CommandType_start 29 #define GFX8_3DSTATE_INDEX_BUFFER_CommandType_start 29 #define GFX75_3DSTATE_INDEX_BUFFER_CommandType_start 29 #define GFX7_3DSTATE_INDEX_BUFFER_CommandType_start 29 #define GFX6_3DSTATE_INDEX_BUFFER_CommandType_start 29 #define GFX5_3DSTATE_INDEX_BUFFER_CommandType_start 29 #define GFX45_3DSTATE_INDEX_BUFFER_CommandType_start 29 #define GFX4_3DSTATE_INDEX_BUFFER_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_INDEX_BUFFER_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 29; case 50: return 29; case 45: return 29; case 40: return 29; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_INDEX_BUFFER::Cut Index Enable */ #define GFX7_3DSTATE_INDEX_BUFFER_CutIndexEnable_bits 1 #define GFX6_3DSTATE_INDEX_BUFFER_CutIndexEnable_bits 1 #define GFX5_3DSTATE_INDEX_BUFFER_CutIndexEnable_bits 1 #define GFX45_3DSTATE_INDEX_BUFFER_CutIndexEnable_bits 1 #define GFX4_3DSTATE_INDEX_BUFFER_CutIndexEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_INDEX_BUFFER_CutIndexEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 1; case 60: return 1; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX7_3DSTATE_INDEX_BUFFER_CutIndexEnable_start 10 #define GFX6_3DSTATE_INDEX_BUFFER_CutIndexEnable_start 10 #define GFX5_3DSTATE_INDEX_BUFFER_CutIndexEnable_start 10 #define GFX45_3DSTATE_INDEX_BUFFER_CutIndexEnable_start 10 #define GFX4_3DSTATE_INDEX_BUFFER_CutIndexEnable_start 10 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_INDEX_BUFFER_CutIndexEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 10; case 60: return 10; case 50: return 10; case 45: return 10; case 40: return 10; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_INDEX_BUFFER::DWord Length */ #define GFX125_3DSTATE_INDEX_BUFFER_DWordLength_bits 8 #define GFX12_3DSTATE_INDEX_BUFFER_DWordLength_bits 8 #define GFX11_3DSTATE_INDEX_BUFFER_DWordLength_bits 8 #define GFX9_3DSTATE_INDEX_BUFFER_DWordLength_bits 8 #define GFX8_3DSTATE_INDEX_BUFFER_DWordLength_bits 8 #define GFX75_3DSTATE_INDEX_BUFFER_DWordLength_bits 8 #define GFX7_3DSTATE_INDEX_BUFFER_DWordLength_bits 8 #define GFX6_3DSTATE_INDEX_BUFFER_DWordLength_bits 8 #define GFX5_3DSTATE_INDEX_BUFFER_DWordLength_bits 8 #define GFX45_3DSTATE_INDEX_BUFFER_DWordLength_bits 8 #define GFX4_3DSTATE_INDEX_BUFFER_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_INDEX_BUFFER_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 8; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_INDEX_BUFFER_DWordLength_start 0 #define GFX12_3DSTATE_INDEX_BUFFER_DWordLength_start 0 #define GFX11_3DSTATE_INDEX_BUFFER_DWordLength_start 0 #define GFX9_3DSTATE_INDEX_BUFFER_DWordLength_start 0 #define GFX8_3DSTATE_INDEX_BUFFER_DWordLength_start 0 #define GFX75_3DSTATE_INDEX_BUFFER_DWordLength_start 0 #define GFX7_3DSTATE_INDEX_BUFFER_DWordLength_start 0 #define GFX6_3DSTATE_INDEX_BUFFER_DWordLength_start 0 #define GFX5_3DSTATE_INDEX_BUFFER_DWordLength_start 0 #define GFX45_3DSTATE_INDEX_BUFFER_DWordLength_start 0 #define GFX4_3DSTATE_INDEX_BUFFER_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_INDEX_BUFFER_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_INDEX_BUFFER::Index Format */ #define GFX125_3DSTATE_INDEX_BUFFER_IndexFormat_bits 2 #define GFX12_3DSTATE_INDEX_BUFFER_IndexFormat_bits 2 #define GFX11_3DSTATE_INDEX_BUFFER_IndexFormat_bits 2 #define GFX9_3DSTATE_INDEX_BUFFER_IndexFormat_bits 2 #define GFX8_3DSTATE_INDEX_BUFFER_IndexFormat_bits 2 #define GFX75_3DSTATE_INDEX_BUFFER_IndexFormat_bits 2 #define GFX7_3DSTATE_INDEX_BUFFER_IndexFormat_bits 2 #define GFX6_3DSTATE_INDEX_BUFFER_IndexFormat_bits 2 #define GFX5_3DSTATE_INDEX_BUFFER_IndexFormat_bits 2 #define GFX45_3DSTATE_INDEX_BUFFER_IndexFormat_bits 2 #define GFX4_3DSTATE_INDEX_BUFFER_IndexFormat_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_INDEX_BUFFER_IndexFormat_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 2; case 45: return 2; case 40: return 2; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_INDEX_BUFFER_IndexFormat_start 40 #define GFX12_3DSTATE_INDEX_BUFFER_IndexFormat_start 40 #define GFX11_3DSTATE_INDEX_BUFFER_IndexFormat_start 40 #define GFX9_3DSTATE_INDEX_BUFFER_IndexFormat_start 40 #define GFX8_3DSTATE_INDEX_BUFFER_IndexFormat_start 40 #define GFX75_3DSTATE_INDEX_BUFFER_IndexFormat_start 8 #define GFX7_3DSTATE_INDEX_BUFFER_IndexFormat_start 8 #define GFX6_3DSTATE_INDEX_BUFFER_IndexFormat_start 8 #define GFX5_3DSTATE_INDEX_BUFFER_IndexFormat_start 8 #define GFX45_3DSTATE_INDEX_BUFFER_IndexFormat_start 8 #define GFX4_3DSTATE_INDEX_BUFFER_IndexFormat_start 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_INDEX_BUFFER_IndexFormat_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 40; case 120: return 40; case 110: return 40; case 90: return 40; case 80: return 40; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 8; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_INDEX_BUFFER::L3 Bypass Disable */ #define GFX125_3DSTATE_INDEX_BUFFER_L3BypassDisable_bits 1 #define GFX12_3DSTATE_INDEX_BUFFER_L3BypassDisable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_INDEX_BUFFER_L3BypassDisable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_INDEX_BUFFER_L3BypassDisable_start 43 #define GFX12_3DSTATE_INDEX_BUFFER_L3BypassDisable_start 43 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_INDEX_BUFFER_L3BypassDisable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 43; case 120: return 43; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_INDEX_BUFFER::MOCS */ #define GFX125_3DSTATE_INDEX_BUFFER_MOCS_bits 7 #define GFX12_3DSTATE_INDEX_BUFFER_MOCS_bits 7 #define GFX11_3DSTATE_INDEX_BUFFER_MOCS_bits 7 #define GFX9_3DSTATE_INDEX_BUFFER_MOCS_bits 7 #define GFX8_3DSTATE_INDEX_BUFFER_MOCS_bits 7 #define GFX75_3DSTATE_INDEX_BUFFER_MOCS_bits 4 #define GFX7_3DSTATE_INDEX_BUFFER_MOCS_bits 4 #define GFX6_3DSTATE_INDEX_BUFFER_MOCS_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_INDEX_BUFFER_MOCS_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 7; case 120: return 7; case 110: return 7; case 90: return 7; case 80: return 7; case 75: return 4; case 70: return 4; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_INDEX_BUFFER_MOCS_start 32 #define GFX12_3DSTATE_INDEX_BUFFER_MOCS_start 32 #define GFX11_3DSTATE_INDEX_BUFFER_MOCS_start 32 #define GFX9_3DSTATE_INDEX_BUFFER_MOCS_start 32 #define GFX8_3DSTATE_INDEX_BUFFER_MOCS_start 32 #define GFX75_3DSTATE_INDEX_BUFFER_MOCS_start 12 #define GFX7_3DSTATE_INDEX_BUFFER_MOCS_start 12 #define GFX6_3DSTATE_INDEX_BUFFER_MOCS_start 12 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_INDEX_BUFFER_MOCS_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 12; case 70: return 12; case 60: return 12; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_LINE_STIPPLE */ #define GFX125_3DSTATE_LINE_STIPPLE_length 3 #define GFX12_3DSTATE_LINE_STIPPLE_length 3 #define GFX11_3DSTATE_LINE_STIPPLE_length 3 #define GFX9_3DSTATE_LINE_STIPPLE_length 3 #define GFX8_3DSTATE_LINE_STIPPLE_length 3 #define GFX75_3DSTATE_LINE_STIPPLE_length 3 #define GFX7_3DSTATE_LINE_STIPPLE_length 3 #define GFX6_3DSTATE_LINE_STIPPLE_length 3 #define GFX5_3DSTATE_LINE_STIPPLE_length 3 #define GFX45_3DSTATE_LINE_STIPPLE_length 3 #define GFX4_3DSTATE_LINE_STIPPLE_length 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_LINE_STIPPLE_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_LINE_STIPPLE::3D Command Opcode */ #define GFX125_3DSTATE_LINE_STIPPLE_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_LINE_STIPPLE_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_LINE_STIPPLE_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_LINE_STIPPLE_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_LINE_STIPPLE_3DCommandOpcode_bits 3 #define GFX75_3DSTATE_LINE_STIPPLE_3DCommandOpcode_bits 3 #define GFX7_3DSTATE_LINE_STIPPLE_3DCommandOpcode_bits 3 #define GFX6_3DSTATE_LINE_STIPPLE_3DCommandOpcode_bits 3 #define GFX5_3DSTATE_LINE_STIPPLE_3DCommandOpcode_bits 3 #define GFX45_3DSTATE_LINE_STIPPLE_3DCommandOpcode_bits 3 #define GFX4_3DSTATE_LINE_STIPPLE_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_LINE_STIPPLE_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_LINE_STIPPLE_3DCommandOpcode_start 24 #define GFX12_3DSTATE_LINE_STIPPLE_3DCommandOpcode_start 24 #define GFX11_3DSTATE_LINE_STIPPLE_3DCommandOpcode_start 24 #define GFX9_3DSTATE_LINE_STIPPLE_3DCommandOpcode_start 24 #define GFX8_3DSTATE_LINE_STIPPLE_3DCommandOpcode_start 24 #define GFX75_3DSTATE_LINE_STIPPLE_3DCommandOpcode_start 24 #define GFX7_3DSTATE_LINE_STIPPLE_3DCommandOpcode_start 24 #define GFX6_3DSTATE_LINE_STIPPLE_3DCommandOpcode_start 24 #define GFX5_3DSTATE_LINE_STIPPLE_3DCommandOpcode_start 24 #define GFX45_3DSTATE_LINE_STIPPLE_3DCommandOpcode_start 24 #define GFX4_3DSTATE_LINE_STIPPLE_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_LINE_STIPPLE_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 24; case 50: return 24; case 45: return 24; case 40: return 24; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_LINE_STIPPLE::3D Command Sub Opcode */ #define GFX125_3DSTATE_LINE_STIPPLE_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_LINE_STIPPLE_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_LINE_STIPPLE_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_LINE_STIPPLE_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_LINE_STIPPLE_3DCommandSubOpcode_bits 8 #define GFX75_3DSTATE_LINE_STIPPLE_3DCommandSubOpcode_bits 8 #define GFX7_3DSTATE_LINE_STIPPLE_3DCommandSubOpcode_bits 8 #define GFX6_3DSTATE_LINE_STIPPLE_3DCommandSubOpcode_bits 8 #define GFX5_3DSTATE_LINE_STIPPLE_3DCommandSubOpcode_bits 8 #define GFX45_3DSTATE_LINE_STIPPLE_3DCommandSubOpcode_bits 8 #define GFX4_3DSTATE_LINE_STIPPLE_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_LINE_STIPPLE_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 8; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_LINE_STIPPLE_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_LINE_STIPPLE_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_LINE_STIPPLE_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_LINE_STIPPLE_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_LINE_STIPPLE_3DCommandSubOpcode_start 16 #define GFX75_3DSTATE_LINE_STIPPLE_3DCommandSubOpcode_start 16 #define GFX7_3DSTATE_LINE_STIPPLE_3DCommandSubOpcode_start 16 #define GFX6_3DSTATE_LINE_STIPPLE_3DCommandSubOpcode_start 16 #define GFX5_3DSTATE_LINE_STIPPLE_3DCommandSubOpcode_start 16 #define GFX45_3DSTATE_LINE_STIPPLE_3DCommandSubOpcode_start 16 #define GFX4_3DSTATE_LINE_STIPPLE_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_LINE_STIPPLE_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 16; case 50: return 16; case 45: return 16; case 40: return 16; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_LINE_STIPPLE::Command SubType */ #define GFX125_3DSTATE_LINE_STIPPLE_CommandSubType_bits 2 #define GFX12_3DSTATE_LINE_STIPPLE_CommandSubType_bits 2 #define GFX11_3DSTATE_LINE_STIPPLE_CommandSubType_bits 2 #define GFX9_3DSTATE_LINE_STIPPLE_CommandSubType_bits 2 #define GFX8_3DSTATE_LINE_STIPPLE_CommandSubType_bits 2 #define GFX75_3DSTATE_LINE_STIPPLE_CommandSubType_bits 2 #define GFX7_3DSTATE_LINE_STIPPLE_CommandSubType_bits 2 #define GFX6_3DSTATE_LINE_STIPPLE_CommandSubType_bits 2 #define GFX5_3DSTATE_LINE_STIPPLE_CommandSubType_bits 2 #define GFX45_3DSTATE_LINE_STIPPLE_CommandSubType_bits 2 #define GFX4_3DSTATE_LINE_STIPPLE_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_LINE_STIPPLE_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 2; case 45: return 2; case 40: return 2; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_LINE_STIPPLE_CommandSubType_start 27 #define GFX12_3DSTATE_LINE_STIPPLE_CommandSubType_start 27 #define GFX11_3DSTATE_LINE_STIPPLE_CommandSubType_start 27 #define GFX9_3DSTATE_LINE_STIPPLE_CommandSubType_start 27 #define GFX8_3DSTATE_LINE_STIPPLE_CommandSubType_start 27 #define GFX75_3DSTATE_LINE_STIPPLE_CommandSubType_start 27 #define GFX7_3DSTATE_LINE_STIPPLE_CommandSubType_start 27 #define GFX6_3DSTATE_LINE_STIPPLE_CommandSubType_start 27 #define GFX5_3DSTATE_LINE_STIPPLE_CommandSubType_start 27 #define GFX45_3DSTATE_LINE_STIPPLE_CommandSubType_start 27 #define GFX4_3DSTATE_LINE_STIPPLE_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_LINE_STIPPLE_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 27; case 50: return 27; case 45: return 27; case 40: return 27; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_LINE_STIPPLE::Command Type */ #define GFX125_3DSTATE_LINE_STIPPLE_CommandType_bits 3 #define GFX12_3DSTATE_LINE_STIPPLE_CommandType_bits 3 #define GFX11_3DSTATE_LINE_STIPPLE_CommandType_bits 3 #define GFX9_3DSTATE_LINE_STIPPLE_CommandType_bits 3 #define GFX8_3DSTATE_LINE_STIPPLE_CommandType_bits 3 #define GFX75_3DSTATE_LINE_STIPPLE_CommandType_bits 3 #define GFX7_3DSTATE_LINE_STIPPLE_CommandType_bits 3 #define GFX6_3DSTATE_LINE_STIPPLE_CommandType_bits 3 #define GFX5_3DSTATE_LINE_STIPPLE_CommandType_bits 3 #define GFX45_3DSTATE_LINE_STIPPLE_CommandType_bits 3 #define GFX4_3DSTATE_LINE_STIPPLE_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_LINE_STIPPLE_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_LINE_STIPPLE_CommandType_start 29 #define GFX12_3DSTATE_LINE_STIPPLE_CommandType_start 29 #define GFX11_3DSTATE_LINE_STIPPLE_CommandType_start 29 #define GFX9_3DSTATE_LINE_STIPPLE_CommandType_start 29 #define GFX8_3DSTATE_LINE_STIPPLE_CommandType_start 29 #define GFX75_3DSTATE_LINE_STIPPLE_CommandType_start 29 #define GFX7_3DSTATE_LINE_STIPPLE_CommandType_start 29 #define GFX6_3DSTATE_LINE_STIPPLE_CommandType_start 29 #define GFX5_3DSTATE_LINE_STIPPLE_CommandType_start 29 #define GFX45_3DSTATE_LINE_STIPPLE_CommandType_start 29 #define GFX4_3DSTATE_LINE_STIPPLE_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_LINE_STIPPLE_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 29; case 50: return 29; case 45: return 29; case 40: return 29; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_LINE_STIPPLE::Current Repeat Counter */ #define GFX125_3DSTATE_LINE_STIPPLE_CurrentRepeatCounter_bits 9 #define GFX12_3DSTATE_LINE_STIPPLE_CurrentRepeatCounter_bits 9 #define GFX11_3DSTATE_LINE_STIPPLE_CurrentRepeatCounter_bits 9 #define GFX9_3DSTATE_LINE_STIPPLE_CurrentRepeatCounter_bits 9 #define GFX8_3DSTATE_LINE_STIPPLE_CurrentRepeatCounter_bits 9 #define GFX75_3DSTATE_LINE_STIPPLE_CurrentRepeatCounter_bits 9 #define GFX7_3DSTATE_LINE_STIPPLE_CurrentRepeatCounter_bits 9 #define GFX6_3DSTATE_LINE_STIPPLE_CurrentRepeatCounter_bits 9 #define GFX5_3DSTATE_LINE_STIPPLE_CurrentRepeatCounter_bits 9 #define GFX45_3DSTATE_LINE_STIPPLE_CurrentRepeatCounter_bits 9 #define GFX4_3DSTATE_LINE_STIPPLE_CurrentRepeatCounter_bits 9 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_LINE_STIPPLE_CurrentRepeatCounter_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 9; case 120: return 9; case 110: return 9; case 90: return 9; case 80: return 9; case 75: return 9; case 70: return 9; case 60: return 9; case 50: return 9; case 45: return 9; case 40: return 9; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_LINE_STIPPLE_CurrentRepeatCounter_start 53 #define GFX12_3DSTATE_LINE_STIPPLE_CurrentRepeatCounter_start 53 #define GFX11_3DSTATE_LINE_STIPPLE_CurrentRepeatCounter_start 53 #define GFX9_3DSTATE_LINE_STIPPLE_CurrentRepeatCounter_start 53 #define GFX8_3DSTATE_LINE_STIPPLE_CurrentRepeatCounter_start 53 #define GFX75_3DSTATE_LINE_STIPPLE_CurrentRepeatCounter_start 53 #define GFX7_3DSTATE_LINE_STIPPLE_CurrentRepeatCounter_start 53 #define GFX6_3DSTATE_LINE_STIPPLE_CurrentRepeatCounter_start 53 #define GFX5_3DSTATE_LINE_STIPPLE_CurrentRepeatCounter_start 53 #define GFX45_3DSTATE_LINE_STIPPLE_CurrentRepeatCounter_start 53 #define GFX4_3DSTATE_LINE_STIPPLE_CurrentRepeatCounter_start 53 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_LINE_STIPPLE_CurrentRepeatCounter_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 53; case 120: return 53; case 110: return 53; case 90: return 53; case 80: return 53; case 75: return 53; case 70: return 53; case 60: return 53; case 50: return 53; case 45: return 53; case 40: return 53; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_LINE_STIPPLE::Current Stipple Index */ #define GFX125_3DSTATE_LINE_STIPPLE_CurrentStippleIndex_bits 4 #define GFX12_3DSTATE_LINE_STIPPLE_CurrentStippleIndex_bits 4 #define GFX11_3DSTATE_LINE_STIPPLE_CurrentStippleIndex_bits 4 #define GFX9_3DSTATE_LINE_STIPPLE_CurrentStippleIndex_bits 4 #define GFX8_3DSTATE_LINE_STIPPLE_CurrentStippleIndex_bits 4 #define GFX75_3DSTATE_LINE_STIPPLE_CurrentStippleIndex_bits 4 #define GFX7_3DSTATE_LINE_STIPPLE_CurrentStippleIndex_bits 4 #define GFX6_3DSTATE_LINE_STIPPLE_CurrentStippleIndex_bits 4 #define GFX5_3DSTATE_LINE_STIPPLE_CurrentStippleIndex_bits 4 #define GFX45_3DSTATE_LINE_STIPPLE_CurrentStippleIndex_bits 4 #define GFX4_3DSTATE_LINE_STIPPLE_CurrentStippleIndex_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_LINE_STIPPLE_CurrentStippleIndex_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 4; case 70: return 4; case 60: return 4; case 50: return 4; case 45: return 4; case 40: return 4; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_LINE_STIPPLE_CurrentStippleIndex_start 48 #define GFX12_3DSTATE_LINE_STIPPLE_CurrentStippleIndex_start 48 #define GFX11_3DSTATE_LINE_STIPPLE_CurrentStippleIndex_start 48 #define GFX9_3DSTATE_LINE_STIPPLE_CurrentStippleIndex_start 48 #define GFX8_3DSTATE_LINE_STIPPLE_CurrentStippleIndex_start 48 #define GFX75_3DSTATE_LINE_STIPPLE_CurrentStippleIndex_start 48 #define GFX7_3DSTATE_LINE_STIPPLE_CurrentStippleIndex_start 48 #define GFX6_3DSTATE_LINE_STIPPLE_CurrentStippleIndex_start 48 #define GFX5_3DSTATE_LINE_STIPPLE_CurrentStippleIndex_start 48 #define GFX45_3DSTATE_LINE_STIPPLE_CurrentStippleIndex_start 48 #define GFX4_3DSTATE_LINE_STIPPLE_CurrentStippleIndex_start 48 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_LINE_STIPPLE_CurrentStippleIndex_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 48; case 120: return 48; case 110: return 48; case 90: return 48; case 80: return 48; case 75: return 48; case 70: return 48; case 60: return 48; case 50: return 48; case 45: return 48; case 40: return 48; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_LINE_STIPPLE::DWord Length */ #define GFX125_3DSTATE_LINE_STIPPLE_DWordLength_bits 8 #define GFX12_3DSTATE_LINE_STIPPLE_DWordLength_bits 8 #define GFX11_3DSTATE_LINE_STIPPLE_DWordLength_bits 8 #define GFX9_3DSTATE_LINE_STIPPLE_DWordLength_bits 8 #define GFX8_3DSTATE_LINE_STIPPLE_DWordLength_bits 8 #define GFX75_3DSTATE_LINE_STIPPLE_DWordLength_bits 8 #define GFX7_3DSTATE_LINE_STIPPLE_DWordLength_bits 8 #define GFX6_3DSTATE_LINE_STIPPLE_DWordLength_bits 8 #define GFX5_3DSTATE_LINE_STIPPLE_DWordLength_bits 8 #define GFX45_3DSTATE_LINE_STIPPLE_DWordLength_bits 8 #define GFX4_3DSTATE_LINE_STIPPLE_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_LINE_STIPPLE_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 8; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_LINE_STIPPLE_DWordLength_start 0 #define GFX12_3DSTATE_LINE_STIPPLE_DWordLength_start 0 #define GFX11_3DSTATE_LINE_STIPPLE_DWordLength_start 0 #define GFX9_3DSTATE_LINE_STIPPLE_DWordLength_start 0 #define GFX8_3DSTATE_LINE_STIPPLE_DWordLength_start 0 #define GFX75_3DSTATE_LINE_STIPPLE_DWordLength_start 0 #define GFX7_3DSTATE_LINE_STIPPLE_DWordLength_start 0 #define GFX6_3DSTATE_LINE_STIPPLE_DWordLength_start 0 #define GFX5_3DSTATE_LINE_STIPPLE_DWordLength_start 0 #define GFX45_3DSTATE_LINE_STIPPLE_DWordLength_start 0 #define GFX4_3DSTATE_LINE_STIPPLE_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_LINE_STIPPLE_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_LINE_STIPPLE::Line Stipple Inverse Repeat Count */ #define GFX125_3DSTATE_LINE_STIPPLE_LineStippleInverseRepeatCount_bits 17 #define GFX12_3DSTATE_LINE_STIPPLE_LineStippleInverseRepeatCount_bits 17 #define GFX11_3DSTATE_LINE_STIPPLE_LineStippleInverseRepeatCount_bits 17 #define GFX9_3DSTATE_LINE_STIPPLE_LineStippleInverseRepeatCount_bits 17 #define GFX8_3DSTATE_LINE_STIPPLE_LineStippleInverseRepeatCount_bits 17 #define GFX75_3DSTATE_LINE_STIPPLE_LineStippleInverseRepeatCount_bits 17 #define GFX7_3DSTATE_LINE_STIPPLE_LineStippleInverseRepeatCount_bits 17 #define GFX6_3DSTATE_LINE_STIPPLE_LineStippleInverseRepeatCount_bits 16 #define GFX5_3DSTATE_LINE_STIPPLE_LineStippleInverseRepeatCount_bits 16 #define GFX45_3DSTATE_LINE_STIPPLE_LineStippleInverseRepeatCount_bits 16 #define GFX4_3DSTATE_LINE_STIPPLE_LineStippleInverseRepeatCount_bits 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_LINE_STIPPLE_LineStippleInverseRepeatCount_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 17; case 120: return 17; case 110: return 17; case 90: return 17; case 80: return 17; case 75: return 17; case 70: return 17; case 60: return 16; case 50: return 16; case 45: return 16; case 40: return 16; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_LINE_STIPPLE_LineStippleInverseRepeatCount_start 79 #define GFX12_3DSTATE_LINE_STIPPLE_LineStippleInverseRepeatCount_start 79 #define GFX11_3DSTATE_LINE_STIPPLE_LineStippleInverseRepeatCount_start 79 #define GFX9_3DSTATE_LINE_STIPPLE_LineStippleInverseRepeatCount_start 79 #define GFX8_3DSTATE_LINE_STIPPLE_LineStippleInverseRepeatCount_start 79 #define GFX75_3DSTATE_LINE_STIPPLE_LineStippleInverseRepeatCount_start 79 #define GFX7_3DSTATE_LINE_STIPPLE_LineStippleInverseRepeatCount_start 79 #define GFX6_3DSTATE_LINE_STIPPLE_LineStippleInverseRepeatCount_start 80 #define GFX5_3DSTATE_LINE_STIPPLE_LineStippleInverseRepeatCount_start 80 #define GFX45_3DSTATE_LINE_STIPPLE_LineStippleInverseRepeatCount_start 80 #define GFX4_3DSTATE_LINE_STIPPLE_LineStippleInverseRepeatCount_start 80 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_LINE_STIPPLE_LineStippleInverseRepeatCount_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 79; case 120: return 79; case 110: return 79; case 90: return 79; case 80: return 79; case 75: return 79; case 70: return 79; case 60: return 80; case 50: return 80; case 45: return 80; case 40: return 80; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_LINE_STIPPLE::Line Stipple Pattern */ #define GFX125_3DSTATE_LINE_STIPPLE_LineStipplePattern_bits 16 #define GFX12_3DSTATE_LINE_STIPPLE_LineStipplePattern_bits 16 #define GFX11_3DSTATE_LINE_STIPPLE_LineStipplePattern_bits 16 #define GFX9_3DSTATE_LINE_STIPPLE_LineStipplePattern_bits 16 #define GFX8_3DSTATE_LINE_STIPPLE_LineStipplePattern_bits 16 #define GFX75_3DSTATE_LINE_STIPPLE_LineStipplePattern_bits 16 #define GFX7_3DSTATE_LINE_STIPPLE_LineStipplePattern_bits 16 #define GFX6_3DSTATE_LINE_STIPPLE_LineStipplePattern_bits 16 #define GFX5_3DSTATE_LINE_STIPPLE_LineStipplePattern_bits 16 #define GFX45_3DSTATE_LINE_STIPPLE_LineStipplePattern_bits 16 #define GFX4_3DSTATE_LINE_STIPPLE_LineStipplePattern_bits 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_LINE_STIPPLE_LineStipplePattern_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 16; case 50: return 16; case 45: return 16; case 40: return 16; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_LINE_STIPPLE_LineStipplePattern_start 32 #define GFX12_3DSTATE_LINE_STIPPLE_LineStipplePattern_start 32 #define GFX11_3DSTATE_LINE_STIPPLE_LineStipplePattern_start 32 #define GFX9_3DSTATE_LINE_STIPPLE_LineStipplePattern_start 32 #define GFX8_3DSTATE_LINE_STIPPLE_LineStipplePattern_start 32 #define GFX75_3DSTATE_LINE_STIPPLE_LineStipplePattern_start 32 #define GFX7_3DSTATE_LINE_STIPPLE_LineStipplePattern_start 32 #define GFX6_3DSTATE_LINE_STIPPLE_LineStipplePattern_start 32 #define GFX5_3DSTATE_LINE_STIPPLE_LineStipplePattern_start 32 #define GFX45_3DSTATE_LINE_STIPPLE_LineStipplePattern_start 32 #define GFX4_3DSTATE_LINE_STIPPLE_LineStipplePattern_start 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_LINE_STIPPLE_LineStipplePattern_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 32; case 50: return 32; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_LINE_STIPPLE::Line Stipple Repeat Count */ #define GFX125_3DSTATE_LINE_STIPPLE_LineStippleRepeatCount_bits 9 #define GFX12_3DSTATE_LINE_STIPPLE_LineStippleRepeatCount_bits 9 #define GFX11_3DSTATE_LINE_STIPPLE_LineStippleRepeatCount_bits 9 #define GFX9_3DSTATE_LINE_STIPPLE_LineStippleRepeatCount_bits 9 #define GFX8_3DSTATE_LINE_STIPPLE_LineStippleRepeatCount_bits 9 #define GFX75_3DSTATE_LINE_STIPPLE_LineStippleRepeatCount_bits 9 #define GFX7_3DSTATE_LINE_STIPPLE_LineStippleRepeatCount_bits 9 #define GFX6_3DSTATE_LINE_STIPPLE_LineStippleRepeatCount_bits 9 #define GFX5_3DSTATE_LINE_STIPPLE_LineStippleRepeatCount_bits 9 #define GFX45_3DSTATE_LINE_STIPPLE_LineStippleRepeatCount_bits 9 #define GFX4_3DSTATE_LINE_STIPPLE_LineStippleRepeatCount_bits 9 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_LINE_STIPPLE_LineStippleRepeatCount_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 9; case 120: return 9; case 110: return 9; case 90: return 9; case 80: return 9; case 75: return 9; case 70: return 9; case 60: return 9; case 50: return 9; case 45: return 9; case 40: return 9; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_LINE_STIPPLE_LineStippleRepeatCount_start 64 #define GFX12_3DSTATE_LINE_STIPPLE_LineStippleRepeatCount_start 64 #define GFX11_3DSTATE_LINE_STIPPLE_LineStippleRepeatCount_start 64 #define GFX9_3DSTATE_LINE_STIPPLE_LineStippleRepeatCount_start 64 #define GFX8_3DSTATE_LINE_STIPPLE_LineStippleRepeatCount_start 64 #define GFX75_3DSTATE_LINE_STIPPLE_LineStippleRepeatCount_start 64 #define GFX7_3DSTATE_LINE_STIPPLE_LineStippleRepeatCount_start 64 #define GFX6_3DSTATE_LINE_STIPPLE_LineStippleRepeatCount_start 64 #define GFX5_3DSTATE_LINE_STIPPLE_LineStippleRepeatCount_start 64 #define GFX45_3DSTATE_LINE_STIPPLE_LineStippleRepeatCount_start 64 #define GFX4_3DSTATE_LINE_STIPPLE_LineStippleRepeatCount_start 64 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_LINE_STIPPLE_LineStippleRepeatCount_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 64; case 80: return 64; case 75: return 64; case 70: return 64; case 60: return 64; case 50: return 64; case 45: return 64; case 40: return 64; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_LINE_STIPPLE::Modify Enable */ #define GFX5_3DSTATE_LINE_STIPPLE_ModifyEnable_bits 1 #define GFX4_3DSTATE_LINE_STIPPLE_ModifyEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_LINE_STIPPLE_ModifyEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 0; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_3DSTATE_LINE_STIPPLE_ModifyEnable_start 63 #define GFX4_3DSTATE_LINE_STIPPLE_ModifyEnable_start 63 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_LINE_STIPPLE_ModifyEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 63; case 45: return 0; case 40: return 63; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_LINE_STIPPLE::Modify Enable (Current Repeat Counter, Current Stipple Index) */ #define GFX125_3DSTATE_LINE_STIPPLE_ModifyEnableCurrentRepeatCounterCurrentStippleIndex_bits 1 #define GFX12_3DSTATE_LINE_STIPPLE_ModifyEnableCurrentRepeatCounterCurrentStippleIndex_bits 1 #define GFX11_3DSTATE_LINE_STIPPLE_ModifyEnableCurrentRepeatCounterCurrentStippleIndex_bits 1 #define GFX9_3DSTATE_LINE_STIPPLE_ModifyEnableCurrentRepeatCounterCurrentStippleIndex_bits 1 #define GFX8_3DSTATE_LINE_STIPPLE_ModifyEnableCurrentRepeatCounterCurrentStippleIndex_bits 1 #define GFX75_3DSTATE_LINE_STIPPLE_ModifyEnableCurrentRepeatCounterCurrentStippleIndex_bits 1 #define GFX7_3DSTATE_LINE_STIPPLE_ModifyEnableCurrentRepeatCounterCurrentStippleIndex_bits 1 #define GFX6_3DSTATE_LINE_STIPPLE_ModifyEnableCurrentRepeatCounterCurrentStippleIndex_bits 1 #define GFX45_3DSTATE_LINE_STIPPLE_ModifyEnableCurrentRepeatCounterCurrentStippleIndex_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_LINE_STIPPLE_ModifyEnableCurrentRepeatCounterCurrentStippleIndex_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 1; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_LINE_STIPPLE_ModifyEnableCurrentRepeatCounterCurrentStippleIndex_start 63 #define GFX12_3DSTATE_LINE_STIPPLE_ModifyEnableCurrentRepeatCounterCurrentStippleIndex_start 63 #define GFX11_3DSTATE_LINE_STIPPLE_ModifyEnableCurrentRepeatCounterCurrentStippleIndex_start 63 #define GFX9_3DSTATE_LINE_STIPPLE_ModifyEnableCurrentRepeatCounterCurrentStippleIndex_start 63 #define GFX8_3DSTATE_LINE_STIPPLE_ModifyEnableCurrentRepeatCounterCurrentStippleIndex_start 63 #define GFX75_3DSTATE_LINE_STIPPLE_ModifyEnableCurrentRepeatCounterCurrentStippleIndex_start 63 #define GFX7_3DSTATE_LINE_STIPPLE_ModifyEnableCurrentRepeatCounterCurrentStippleIndex_start 63 #define GFX6_3DSTATE_LINE_STIPPLE_ModifyEnableCurrentRepeatCounterCurrentStippleIndex_start 63 #define GFX45_3DSTATE_LINE_STIPPLE_ModifyEnableCurrentRepeatCounterCurrentStippleIndex_start 63 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_LINE_STIPPLE_ModifyEnableCurrentRepeatCounterCurrentStippleIndex_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 63; case 120: return 63; case 110: return 63; case 90: return 63; case 80: return 63; case 75: return 63; case 70: return 63; case 60: return 63; case 50: return 0; case 45: return 63; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_MONOFILTER_SIZE */ #define GFX125_3DSTATE_MONOFILTER_SIZE_length 2 #define GFX12_3DSTATE_MONOFILTER_SIZE_length 2 #define GFX11_3DSTATE_MONOFILTER_SIZE_length 2 #define GFX9_3DSTATE_MONOFILTER_SIZE_length 2 #define GFX8_3DSTATE_MONOFILTER_SIZE_length 2 #define GFX75_3DSTATE_MONOFILTER_SIZE_length 2 #define GFX7_3DSTATE_MONOFILTER_SIZE_length 2 #define GFX6_3DSTATE_MONOFILTER_SIZE_length 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_MONOFILTER_SIZE_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_MONOFILTER_SIZE::3D Command Opcode */ #define GFX125_3DSTATE_MONOFILTER_SIZE_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_MONOFILTER_SIZE_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_MONOFILTER_SIZE_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_MONOFILTER_SIZE_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_MONOFILTER_SIZE_3DCommandOpcode_bits 3 #define GFX75_3DSTATE_MONOFILTER_SIZE_3DCommandOpcode_bits 3 #define GFX7_3DSTATE_MONOFILTER_SIZE_3DCommandOpcode_bits 3 #define GFX6_3DSTATE_MONOFILTER_SIZE_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_MONOFILTER_SIZE_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_MONOFILTER_SIZE_3DCommandOpcode_start 24 #define GFX12_3DSTATE_MONOFILTER_SIZE_3DCommandOpcode_start 24 #define GFX11_3DSTATE_MONOFILTER_SIZE_3DCommandOpcode_start 24 #define GFX9_3DSTATE_MONOFILTER_SIZE_3DCommandOpcode_start 24 #define GFX8_3DSTATE_MONOFILTER_SIZE_3DCommandOpcode_start 24 #define GFX75_3DSTATE_MONOFILTER_SIZE_3DCommandOpcode_start 24 #define GFX7_3DSTATE_MONOFILTER_SIZE_3DCommandOpcode_start 24 #define GFX6_3DSTATE_MONOFILTER_SIZE_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_MONOFILTER_SIZE_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 24; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_MONOFILTER_SIZE::3D Command Sub Opcode */ #define GFX125_3DSTATE_MONOFILTER_SIZE_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_MONOFILTER_SIZE_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_MONOFILTER_SIZE_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_MONOFILTER_SIZE_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_MONOFILTER_SIZE_3DCommandSubOpcode_bits 8 #define GFX75_3DSTATE_MONOFILTER_SIZE_3DCommandSubOpcode_bits 8 #define GFX7_3DSTATE_MONOFILTER_SIZE_3DCommandSubOpcode_bits 8 #define GFX6_3DSTATE_MONOFILTER_SIZE_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_MONOFILTER_SIZE_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_MONOFILTER_SIZE_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_MONOFILTER_SIZE_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_MONOFILTER_SIZE_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_MONOFILTER_SIZE_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_MONOFILTER_SIZE_3DCommandSubOpcode_start 16 #define GFX75_3DSTATE_MONOFILTER_SIZE_3DCommandSubOpcode_start 16 #define GFX7_3DSTATE_MONOFILTER_SIZE_3DCommandSubOpcode_start 16 #define GFX6_3DSTATE_MONOFILTER_SIZE_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_MONOFILTER_SIZE_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 16; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_MONOFILTER_SIZE::Command SubType */ #define GFX125_3DSTATE_MONOFILTER_SIZE_CommandSubType_bits 2 #define GFX12_3DSTATE_MONOFILTER_SIZE_CommandSubType_bits 2 #define GFX11_3DSTATE_MONOFILTER_SIZE_CommandSubType_bits 2 #define GFX9_3DSTATE_MONOFILTER_SIZE_CommandSubType_bits 2 #define GFX8_3DSTATE_MONOFILTER_SIZE_CommandSubType_bits 2 #define GFX75_3DSTATE_MONOFILTER_SIZE_CommandSubType_bits 2 #define GFX7_3DSTATE_MONOFILTER_SIZE_CommandSubType_bits 2 #define GFX6_3DSTATE_MONOFILTER_SIZE_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_MONOFILTER_SIZE_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_MONOFILTER_SIZE_CommandSubType_start 27 #define GFX12_3DSTATE_MONOFILTER_SIZE_CommandSubType_start 27 #define GFX11_3DSTATE_MONOFILTER_SIZE_CommandSubType_start 27 #define GFX9_3DSTATE_MONOFILTER_SIZE_CommandSubType_start 27 #define GFX8_3DSTATE_MONOFILTER_SIZE_CommandSubType_start 27 #define GFX75_3DSTATE_MONOFILTER_SIZE_CommandSubType_start 27 #define GFX7_3DSTATE_MONOFILTER_SIZE_CommandSubType_start 27 #define GFX6_3DSTATE_MONOFILTER_SIZE_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_MONOFILTER_SIZE_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 27; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_MONOFILTER_SIZE::Command Type */ #define GFX125_3DSTATE_MONOFILTER_SIZE_CommandType_bits 3 #define GFX12_3DSTATE_MONOFILTER_SIZE_CommandType_bits 3 #define GFX11_3DSTATE_MONOFILTER_SIZE_CommandType_bits 3 #define GFX9_3DSTATE_MONOFILTER_SIZE_CommandType_bits 3 #define GFX8_3DSTATE_MONOFILTER_SIZE_CommandType_bits 3 #define GFX75_3DSTATE_MONOFILTER_SIZE_CommandType_bits 3 #define GFX7_3DSTATE_MONOFILTER_SIZE_CommandType_bits 3 #define GFX6_3DSTATE_MONOFILTER_SIZE_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_MONOFILTER_SIZE_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_MONOFILTER_SIZE_CommandType_start 29 #define GFX12_3DSTATE_MONOFILTER_SIZE_CommandType_start 29 #define GFX11_3DSTATE_MONOFILTER_SIZE_CommandType_start 29 #define GFX9_3DSTATE_MONOFILTER_SIZE_CommandType_start 29 #define GFX8_3DSTATE_MONOFILTER_SIZE_CommandType_start 29 #define GFX75_3DSTATE_MONOFILTER_SIZE_CommandType_start 29 #define GFX7_3DSTATE_MONOFILTER_SIZE_CommandType_start 29 #define GFX6_3DSTATE_MONOFILTER_SIZE_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_MONOFILTER_SIZE_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 29; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_MONOFILTER_SIZE::DWord Length */ #define GFX125_3DSTATE_MONOFILTER_SIZE_DWordLength_bits 8 #define GFX12_3DSTATE_MONOFILTER_SIZE_DWordLength_bits 8 #define GFX11_3DSTATE_MONOFILTER_SIZE_DWordLength_bits 8 #define GFX9_3DSTATE_MONOFILTER_SIZE_DWordLength_bits 8 #define GFX8_3DSTATE_MONOFILTER_SIZE_DWordLength_bits 8 #define GFX75_3DSTATE_MONOFILTER_SIZE_DWordLength_bits 8 #define GFX7_3DSTATE_MONOFILTER_SIZE_DWordLength_bits 8 #define GFX6_3DSTATE_MONOFILTER_SIZE_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_MONOFILTER_SIZE_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_MONOFILTER_SIZE_DWordLength_start 0 #define GFX12_3DSTATE_MONOFILTER_SIZE_DWordLength_start 0 #define GFX11_3DSTATE_MONOFILTER_SIZE_DWordLength_start 0 #define GFX9_3DSTATE_MONOFILTER_SIZE_DWordLength_start 0 #define GFX8_3DSTATE_MONOFILTER_SIZE_DWordLength_start 0 #define GFX75_3DSTATE_MONOFILTER_SIZE_DWordLength_start 0 #define GFX7_3DSTATE_MONOFILTER_SIZE_DWordLength_start 0 #define GFX6_3DSTATE_MONOFILTER_SIZE_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_MONOFILTER_SIZE_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_MONOFILTER_SIZE::Monochrome Filter Height */ #define GFX125_3DSTATE_MONOFILTER_SIZE_MonochromeFilterHeight_bits 3 #define GFX12_3DSTATE_MONOFILTER_SIZE_MonochromeFilterHeight_bits 3 #define GFX11_3DSTATE_MONOFILTER_SIZE_MonochromeFilterHeight_bits 3 #define GFX9_3DSTATE_MONOFILTER_SIZE_MonochromeFilterHeight_bits 3 #define GFX8_3DSTATE_MONOFILTER_SIZE_MonochromeFilterHeight_bits 3 #define GFX75_3DSTATE_MONOFILTER_SIZE_MonochromeFilterHeight_bits 3 #define GFX7_3DSTATE_MONOFILTER_SIZE_MonochromeFilterHeight_bits 3 #define GFX6_3DSTATE_MONOFILTER_SIZE_MonochromeFilterHeight_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_MONOFILTER_SIZE_MonochromeFilterHeight_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_MONOFILTER_SIZE_MonochromeFilterHeight_start 32 #define GFX12_3DSTATE_MONOFILTER_SIZE_MonochromeFilterHeight_start 32 #define GFX11_3DSTATE_MONOFILTER_SIZE_MonochromeFilterHeight_start 32 #define GFX9_3DSTATE_MONOFILTER_SIZE_MonochromeFilterHeight_start 32 #define GFX8_3DSTATE_MONOFILTER_SIZE_MonochromeFilterHeight_start 32 #define GFX75_3DSTATE_MONOFILTER_SIZE_MonochromeFilterHeight_start 32 #define GFX7_3DSTATE_MONOFILTER_SIZE_MonochromeFilterHeight_start 32 #define GFX6_3DSTATE_MONOFILTER_SIZE_MonochromeFilterHeight_start 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_MONOFILTER_SIZE_MonochromeFilterHeight_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 32; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_MONOFILTER_SIZE::Monochrome Filter Width */ #define GFX125_3DSTATE_MONOFILTER_SIZE_MonochromeFilterWidth_bits 3 #define GFX12_3DSTATE_MONOFILTER_SIZE_MonochromeFilterWidth_bits 3 #define GFX11_3DSTATE_MONOFILTER_SIZE_MonochromeFilterWidth_bits 3 #define GFX9_3DSTATE_MONOFILTER_SIZE_MonochromeFilterWidth_bits 3 #define GFX8_3DSTATE_MONOFILTER_SIZE_MonochromeFilterWidth_bits 3 #define GFX75_3DSTATE_MONOFILTER_SIZE_MonochromeFilterWidth_bits 3 #define GFX7_3DSTATE_MONOFILTER_SIZE_MonochromeFilterWidth_bits 3 #define GFX6_3DSTATE_MONOFILTER_SIZE_MonochromeFilterWidth_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_MONOFILTER_SIZE_MonochromeFilterWidth_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_MONOFILTER_SIZE_MonochromeFilterWidth_start 35 #define GFX12_3DSTATE_MONOFILTER_SIZE_MonochromeFilterWidth_start 35 #define GFX11_3DSTATE_MONOFILTER_SIZE_MonochromeFilterWidth_start 35 #define GFX9_3DSTATE_MONOFILTER_SIZE_MonochromeFilterWidth_start 35 #define GFX8_3DSTATE_MONOFILTER_SIZE_MonochromeFilterWidth_start 35 #define GFX75_3DSTATE_MONOFILTER_SIZE_MonochromeFilterWidth_start 35 #define GFX7_3DSTATE_MONOFILTER_SIZE_MonochromeFilterWidth_start 35 #define GFX6_3DSTATE_MONOFILTER_SIZE_MonochromeFilterWidth_start 35 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_MONOFILTER_SIZE_MonochromeFilterWidth_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 35; case 120: return 35; case 110: return 35; case 90: return 35; case 80: return 35; case 75: return 35; case 70: return 35; case 60: return 35; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_MULTISAMPLE */ #define GFX125_3DSTATE_MULTISAMPLE_length 2 #define GFX12_3DSTATE_MULTISAMPLE_length 2 #define GFX11_3DSTATE_MULTISAMPLE_length 2 #define GFX9_3DSTATE_MULTISAMPLE_length 2 #define GFX8_3DSTATE_MULTISAMPLE_length 2 #define GFX75_3DSTATE_MULTISAMPLE_length 4 #define GFX7_3DSTATE_MULTISAMPLE_length 4 #define GFX6_3DSTATE_MULTISAMPLE_length 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_MULTISAMPLE_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 4; case 70: return 4; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_MULTISAMPLE::3D Command Opcode */ #define GFX125_3DSTATE_MULTISAMPLE_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_MULTISAMPLE_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_MULTISAMPLE_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_MULTISAMPLE_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_MULTISAMPLE_3DCommandOpcode_bits 3 #define GFX75_3DSTATE_MULTISAMPLE_3DCommandOpcode_bits 3 #define GFX7_3DSTATE_MULTISAMPLE_3DCommandOpcode_bits 3 #define GFX6_3DSTATE_MULTISAMPLE_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_MULTISAMPLE_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_MULTISAMPLE_3DCommandOpcode_start 24 #define GFX12_3DSTATE_MULTISAMPLE_3DCommandOpcode_start 24 #define GFX11_3DSTATE_MULTISAMPLE_3DCommandOpcode_start 24 #define GFX9_3DSTATE_MULTISAMPLE_3DCommandOpcode_start 24 #define GFX8_3DSTATE_MULTISAMPLE_3DCommandOpcode_start 24 #define GFX75_3DSTATE_MULTISAMPLE_3DCommandOpcode_start 24 #define GFX7_3DSTATE_MULTISAMPLE_3DCommandOpcode_start 24 #define GFX6_3DSTATE_MULTISAMPLE_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_MULTISAMPLE_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 24; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_MULTISAMPLE::3D Command Sub Opcode */ #define GFX125_3DSTATE_MULTISAMPLE_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_MULTISAMPLE_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_MULTISAMPLE_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_MULTISAMPLE_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_MULTISAMPLE_3DCommandSubOpcode_bits 8 #define GFX75_3DSTATE_MULTISAMPLE_3DCommandSubOpcode_bits 8 #define GFX7_3DSTATE_MULTISAMPLE_3DCommandSubOpcode_bits 8 #define GFX6_3DSTATE_MULTISAMPLE_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_MULTISAMPLE_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_MULTISAMPLE_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_MULTISAMPLE_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_MULTISAMPLE_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_MULTISAMPLE_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_MULTISAMPLE_3DCommandSubOpcode_start 16 #define GFX75_3DSTATE_MULTISAMPLE_3DCommandSubOpcode_start 16 #define GFX7_3DSTATE_MULTISAMPLE_3DCommandSubOpcode_start 16 #define GFX6_3DSTATE_MULTISAMPLE_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_MULTISAMPLE_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 16; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_MULTISAMPLE::Command SubType */ #define GFX125_3DSTATE_MULTISAMPLE_CommandSubType_bits 2 #define GFX12_3DSTATE_MULTISAMPLE_CommandSubType_bits 2 #define GFX11_3DSTATE_MULTISAMPLE_CommandSubType_bits 2 #define GFX9_3DSTATE_MULTISAMPLE_CommandSubType_bits 2 #define GFX8_3DSTATE_MULTISAMPLE_CommandSubType_bits 2 #define GFX75_3DSTATE_MULTISAMPLE_CommandSubType_bits 2 #define GFX7_3DSTATE_MULTISAMPLE_CommandSubType_bits 2 #define GFX6_3DSTATE_MULTISAMPLE_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_MULTISAMPLE_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_MULTISAMPLE_CommandSubType_start 27 #define GFX12_3DSTATE_MULTISAMPLE_CommandSubType_start 27 #define GFX11_3DSTATE_MULTISAMPLE_CommandSubType_start 27 #define GFX9_3DSTATE_MULTISAMPLE_CommandSubType_start 27 #define GFX8_3DSTATE_MULTISAMPLE_CommandSubType_start 27 #define GFX75_3DSTATE_MULTISAMPLE_CommandSubType_start 27 #define GFX7_3DSTATE_MULTISAMPLE_CommandSubType_start 27 #define GFX6_3DSTATE_MULTISAMPLE_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_MULTISAMPLE_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 27; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_MULTISAMPLE::Command Type */ #define GFX125_3DSTATE_MULTISAMPLE_CommandType_bits 3 #define GFX12_3DSTATE_MULTISAMPLE_CommandType_bits 3 #define GFX11_3DSTATE_MULTISAMPLE_CommandType_bits 3 #define GFX9_3DSTATE_MULTISAMPLE_CommandType_bits 3 #define GFX8_3DSTATE_MULTISAMPLE_CommandType_bits 3 #define GFX75_3DSTATE_MULTISAMPLE_CommandType_bits 3 #define GFX7_3DSTATE_MULTISAMPLE_CommandType_bits 3 #define GFX6_3DSTATE_MULTISAMPLE_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_MULTISAMPLE_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_MULTISAMPLE_CommandType_start 29 #define GFX12_3DSTATE_MULTISAMPLE_CommandType_start 29 #define GFX11_3DSTATE_MULTISAMPLE_CommandType_start 29 #define GFX9_3DSTATE_MULTISAMPLE_CommandType_start 29 #define GFX8_3DSTATE_MULTISAMPLE_CommandType_start 29 #define GFX75_3DSTATE_MULTISAMPLE_CommandType_start 29 #define GFX7_3DSTATE_MULTISAMPLE_CommandType_start 29 #define GFX6_3DSTATE_MULTISAMPLE_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_MULTISAMPLE_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 29; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_MULTISAMPLE::DWord Length */ #define GFX125_3DSTATE_MULTISAMPLE_DWordLength_bits 8 #define GFX12_3DSTATE_MULTISAMPLE_DWordLength_bits 8 #define GFX11_3DSTATE_MULTISAMPLE_DWordLength_bits 8 #define GFX9_3DSTATE_MULTISAMPLE_DWordLength_bits 8 #define GFX8_3DSTATE_MULTISAMPLE_DWordLength_bits 8 #define GFX75_3DSTATE_MULTISAMPLE_DWordLength_bits 8 #define GFX7_3DSTATE_MULTISAMPLE_DWordLength_bits 8 #define GFX6_3DSTATE_MULTISAMPLE_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_MULTISAMPLE_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_MULTISAMPLE_DWordLength_start 0 #define GFX12_3DSTATE_MULTISAMPLE_DWordLength_start 0 #define GFX11_3DSTATE_MULTISAMPLE_DWordLength_start 0 #define GFX9_3DSTATE_MULTISAMPLE_DWordLength_start 0 #define GFX8_3DSTATE_MULTISAMPLE_DWordLength_start 0 #define GFX75_3DSTATE_MULTISAMPLE_DWordLength_start 0 #define GFX7_3DSTATE_MULTISAMPLE_DWordLength_start 0 #define GFX6_3DSTATE_MULTISAMPLE_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_MULTISAMPLE_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_MULTISAMPLE::Multi Sample Enable */ #define GFX75_3DSTATE_MULTISAMPLE_MultiSampleEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_MULTISAMPLE_MultiSampleEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_MULTISAMPLE_MultiSampleEnable_start 37 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_MULTISAMPLE_MultiSampleEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 37; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_MULTISAMPLE::Number of Multisamples */ #define GFX125_3DSTATE_MULTISAMPLE_NumberofMultisamples_bits 3 #define GFX12_3DSTATE_MULTISAMPLE_NumberofMultisamples_bits 3 #define GFX11_3DSTATE_MULTISAMPLE_NumberofMultisamples_bits 3 #define GFX9_3DSTATE_MULTISAMPLE_NumberofMultisamples_bits 3 #define GFX8_3DSTATE_MULTISAMPLE_NumberofMultisamples_bits 3 #define GFX75_3DSTATE_MULTISAMPLE_NumberofMultisamples_bits 3 #define GFX7_3DSTATE_MULTISAMPLE_NumberofMultisamples_bits 3 #define GFX6_3DSTATE_MULTISAMPLE_NumberofMultisamples_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_MULTISAMPLE_NumberofMultisamples_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_MULTISAMPLE_NumberofMultisamples_start 33 #define GFX12_3DSTATE_MULTISAMPLE_NumberofMultisamples_start 33 #define GFX11_3DSTATE_MULTISAMPLE_NumberofMultisamples_start 33 #define GFX9_3DSTATE_MULTISAMPLE_NumberofMultisamples_start 33 #define GFX8_3DSTATE_MULTISAMPLE_NumberofMultisamples_start 33 #define GFX75_3DSTATE_MULTISAMPLE_NumberofMultisamples_start 33 #define GFX7_3DSTATE_MULTISAMPLE_NumberofMultisamples_start 33 #define GFX6_3DSTATE_MULTISAMPLE_NumberofMultisamples_start 33 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_MULTISAMPLE_NumberofMultisamples_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 33; case 120: return 33; case 110: return 33; case 90: return 33; case 80: return 33; case 75: return 33; case 70: return 33; case 60: return 33; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_MULTISAMPLE::Pixel Location */ #define GFX125_3DSTATE_MULTISAMPLE_PixelLocation_bits 1 #define GFX12_3DSTATE_MULTISAMPLE_PixelLocation_bits 1 #define GFX11_3DSTATE_MULTISAMPLE_PixelLocation_bits 1 #define GFX9_3DSTATE_MULTISAMPLE_PixelLocation_bits 1 #define GFX8_3DSTATE_MULTISAMPLE_PixelLocation_bits 1 #define GFX75_3DSTATE_MULTISAMPLE_PixelLocation_bits 1 #define GFX7_3DSTATE_MULTISAMPLE_PixelLocation_bits 1 #define GFX6_3DSTATE_MULTISAMPLE_PixelLocation_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_MULTISAMPLE_PixelLocation_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_MULTISAMPLE_PixelLocation_start 36 #define GFX12_3DSTATE_MULTISAMPLE_PixelLocation_start 36 #define GFX11_3DSTATE_MULTISAMPLE_PixelLocation_start 36 #define GFX9_3DSTATE_MULTISAMPLE_PixelLocation_start 36 #define GFX8_3DSTATE_MULTISAMPLE_PixelLocation_start 36 #define GFX75_3DSTATE_MULTISAMPLE_PixelLocation_start 36 #define GFX7_3DSTATE_MULTISAMPLE_PixelLocation_start 36 #define GFX6_3DSTATE_MULTISAMPLE_PixelLocation_start 36 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_MULTISAMPLE_PixelLocation_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 36; case 120: return 36; case 110: return 36; case 90: return 36; case 80: return 36; case 75: return 36; case 70: return 36; case 60: return 36; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_MULTISAMPLE::Pixel Position Offset Enable */ #define GFX125_3DSTATE_MULTISAMPLE_PixelPositionOffsetEnable_bits 1 #define GFX12_3DSTATE_MULTISAMPLE_PixelPositionOffsetEnable_bits 1 #define GFX11_3DSTATE_MULTISAMPLE_PixelPositionOffsetEnable_bits 1 #define GFX9_3DSTATE_MULTISAMPLE_PixelPositionOffsetEnable_bits 1 #define GFX8_3DSTATE_MULTISAMPLE_PixelPositionOffsetEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_MULTISAMPLE_PixelPositionOffsetEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_MULTISAMPLE_PixelPositionOffsetEnable_start 37 #define GFX12_3DSTATE_MULTISAMPLE_PixelPositionOffsetEnable_start 37 #define GFX11_3DSTATE_MULTISAMPLE_PixelPositionOffsetEnable_start 37 #define GFX9_3DSTATE_MULTISAMPLE_PixelPositionOffsetEnable_start 37 #define GFX8_3DSTATE_MULTISAMPLE_PixelPositionOffsetEnable_start 37 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_MULTISAMPLE_PixelPositionOffsetEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 37; case 120: return 37; case 110: return 37; case 90: return 37; case 80: return 37; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_MULTISAMPLE::Sample0 X Offset */ #define GFX75_3DSTATE_MULTISAMPLE_Sample0XOffset_bits 4 #define GFX7_3DSTATE_MULTISAMPLE_Sample0XOffset_bits 4 #define GFX6_3DSTATE_MULTISAMPLE_Sample0XOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_MULTISAMPLE_Sample0XOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 4; case 70: return 4; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_MULTISAMPLE_Sample0XOffset_start 68 #define GFX7_3DSTATE_MULTISAMPLE_Sample0XOffset_start 68 #define GFX6_3DSTATE_MULTISAMPLE_Sample0XOffset_start 68 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_MULTISAMPLE_Sample0XOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 68; case 70: return 68; case 60: return 68; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_MULTISAMPLE::Sample0 Y Offset */ #define GFX75_3DSTATE_MULTISAMPLE_Sample0YOffset_bits 4 #define GFX7_3DSTATE_MULTISAMPLE_Sample0YOffset_bits 4 #define GFX6_3DSTATE_MULTISAMPLE_Sample0YOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_MULTISAMPLE_Sample0YOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 4; case 70: return 4; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_MULTISAMPLE_Sample0YOffset_start 64 #define GFX7_3DSTATE_MULTISAMPLE_Sample0YOffset_start 64 #define GFX6_3DSTATE_MULTISAMPLE_Sample0YOffset_start 64 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_MULTISAMPLE_Sample0YOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 64; case 70: return 64; case 60: return 64; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_MULTISAMPLE::Sample1 X Offset */ #define GFX75_3DSTATE_MULTISAMPLE_Sample1XOffset_bits 4 #define GFX7_3DSTATE_MULTISAMPLE_Sample1XOffset_bits 4 #define GFX6_3DSTATE_MULTISAMPLE_Sample1XOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_MULTISAMPLE_Sample1XOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 4; case 70: return 4; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_MULTISAMPLE_Sample1XOffset_start 76 #define GFX7_3DSTATE_MULTISAMPLE_Sample1XOffset_start 76 #define GFX6_3DSTATE_MULTISAMPLE_Sample1XOffset_start 76 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_MULTISAMPLE_Sample1XOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 76; case 70: return 76; case 60: return 76; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_MULTISAMPLE::Sample1 Y Offset */ #define GFX75_3DSTATE_MULTISAMPLE_Sample1YOffset_bits 4 #define GFX7_3DSTATE_MULTISAMPLE_Sample1YOffset_bits 4 #define GFX6_3DSTATE_MULTISAMPLE_Sample1YOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_MULTISAMPLE_Sample1YOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 4; case 70: return 4; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_MULTISAMPLE_Sample1YOffset_start 72 #define GFX7_3DSTATE_MULTISAMPLE_Sample1YOffset_start 72 #define GFX6_3DSTATE_MULTISAMPLE_Sample1YOffset_start 72 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_MULTISAMPLE_Sample1YOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 72; case 70: return 72; case 60: return 72; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_MULTISAMPLE::Sample2 X Offset */ #define GFX75_3DSTATE_MULTISAMPLE_Sample2XOffset_bits 4 #define GFX7_3DSTATE_MULTISAMPLE_Sample2XOffset_bits 4 #define GFX6_3DSTATE_MULTISAMPLE_Sample2XOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_MULTISAMPLE_Sample2XOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 4; case 70: return 4; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_MULTISAMPLE_Sample2XOffset_start 84 #define GFX7_3DSTATE_MULTISAMPLE_Sample2XOffset_start 84 #define GFX6_3DSTATE_MULTISAMPLE_Sample2XOffset_start 84 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_MULTISAMPLE_Sample2XOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 84; case 70: return 84; case 60: return 84; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_MULTISAMPLE::Sample2 Y Offset */ #define GFX75_3DSTATE_MULTISAMPLE_Sample2YOffset_bits 4 #define GFX7_3DSTATE_MULTISAMPLE_Sample2YOffset_bits 4 #define GFX6_3DSTATE_MULTISAMPLE_Sample2YOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_MULTISAMPLE_Sample2YOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 4; case 70: return 4; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_MULTISAMPLE_Sample2YOffset_start 80 #define GFX7_3DSTATE_MULTISAMPLE_Sample2YOffset_start 80 #define GFX6_3DSTATE_MULTISAMPLE_Sample2YOffset_start 80 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_MULTISAMPLE_Sample2YOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 80; case 70: return 80; case 60: return 80; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_MULTISAMPLE::Sample3 X Offset */ #define GFX75_3DSTATE_MULTISAMPLE_Sample3XOffset_bits 4 #define GFX7_3DSTATE_MULTISAMPLE_Sample3XOffset_bits 4 #define GFX6_3DSTATE_MULTISAMPLE_Sample3XOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_MULTISAMPLE_Sample3XOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 4; case 70: return 4; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_MULTISAMPLE_Sample3XOffset_start 92 #define GFX7_3DSTATE_MULTISAMPLE_Sample3XOffset_start 92 #define GFX6_3DSTATE_MULTISAMPLE_Sample3XOffset_start 92 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_MULTISAMPLE_Sample3XOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 92; case 70: return 92; case 60: return 92; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_MULTISAMPLE::Sample3 Y Offset */ #define GFX75_3DSTATE_MULTISAMPLE_Sample3YOffset_bits 4 #define GFX7_3DSTATE_MULTISAMPLE_Sample3YOffset_bits 4 #define GFX6_3DSTATE_MULTISAMPLE_Sample3YOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_MULTISAMPLE_Sample3YOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 4; case 70: return 4; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_MULTISAMPLE_Sample3YOffset_start 88 #define GFX7_3DSTATE_MULTISAMPLE_Sample3YOffset_start 88 #define GFX6_3DSTATE_MULTISAMPLE_Sample3YOffset_start 88 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_MULTISAMPLE_Sample3YOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 88; case 70: return 88; case 60: return 88; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_MULTISAMPLE::Sample4 X Offset */ #define GFX75_3DSTATE_MULTISAMPLE_Sample4XOffset_bits 4 #define GFX7_3DSTATE_MULTISAMPLE_Sample4XOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_MULTISAMPLE_Sample4XOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 4; case 70: return 4; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_MULTISAMPLE_Sample4XOffset_start 100 #define GFX7_3DSTATE_MULTISAMPLE_Sample4XOffset_start 100 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_MULTISAMPLE_Sample4XOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 100; case 70: return 100; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_MULTISAMPLE::Sample4 Y Offset */ #define GFX75_3DSTATE_MULTISAMPLE_Sample4YOffset_bits 4 #define GFX7_3DSTATE_MULTISAMPLE_Sample4YOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_MULTISAMPLE_Sample4YOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 4; case 70: return 4; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_MULTISAMPLE_Sample4YOffset_start 96 #define GFX7_3DSTATE_MULTISAMPLE_Sample4YOffset_start 96 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_MULTISAMPLE_Sample4YOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 96; case 70: return 96; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_MULTISAMPLE::Sample5 X Offset */ #define GFX75_3DSTATE_MULTISAMPLE_Sample5XOffset_bits 4 #define GFX7_3DSTATE_MULTISAMPLE_Sample5XOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_MULTISAMPLE_Sample5XOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 4; case 70: return 4; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_MULTISAMPLE_Sample5XOffset_start 108 #define GFX7_3DSTATE_MULTISAMPLE_Sample5XOffset_start 108 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_MULTISAMPLE_Sample5XOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 108; case 70: return 108; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_MULTISAMPLE::Sample5 Y Offset */ #define GFX75_3DSTATE_MULTISAMPLE_Sample5YOffset_bits 4 #define GFX7_3DSTATE_MULTISAMPLE_Sample5YOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_MULTISAMPLE_Sample5YOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 4; case 70: return 4; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_MULTISAMPLE_Sample5YOffset_start 104 #define GFX7_3DSTATE_MULTISAMPLE_Sample5YOffset_start 104 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_MULTISAMPLE_Sample5YOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 104; case 70: return 104; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_MULTISAMPLE::Sample6 X Offset */ #define GFX75_3DSTATE_MULTISAMPLE_Sample6XOffset_bits 4 #define GFX7_3DSTATE_MULTISAMPLE_Sample6XOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_MULTISAMPLE_Sample6XOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 4; case 70: return 4; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_MULTISAMPLE_Sample6XOffset_start 116 #define GFX7_3DSTATE_MULTISAMPLE_Sample6XOffset_start 116 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_MULTISAMPLE_Sample6XOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 116; case 70: return 116; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_MULTISAMPLE::Sample6 Y Offset */ #define GFX75_3DSTATE_MULTISAMPLE_Sample6YOffset_bits 4 #define GFX7_3DSTATE_MULTISAMPLE_Sample6YOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_MULTISAMPLE_Sample6YOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 4; case 70: return 4; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_MULTISAMPLE_Sample6YOffset_start 112 #define GFX7_3DSTATE_MULTISAMPLE_Sample6YOffset_start 112 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_MULTISAMPLE_Sample6YOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 112; case 70: return 112; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_MULTISAMPLE::Sample7 X Offset */ #define GFX75_3DSTATE_MULTISAMPLE_Sample7XOffset_bits 4 #define GFX7_3DSTATE_MULTISAMPLE_Sample7XOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_MULTISAMPLE_Sample7XOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 4; case 70: return 4; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_MULTISAMPLE_Sample7XOffset_start 124 #define GFX7_3DSTATE_MULTISAMPLE_Sample7XOffset_start 124 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_MULTISAMPLE_Sample7XOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 124; case 70: return 124; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_MULTISAMPLE::Sample7 Y Offset */ #define GFX75_3DSTATE_MULTISAMPLE_Sample7YOffset_bits 4 #define GFX7_3DSTATE_MULTISAMPLE_Sample7YOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_MULTISAMPLE_Sample7YOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 4; case 70: return 4; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_MULTISAMPLE_Sample7YOffset_start 120 #define GFX7_3DSTATE_MULTISAMPLE_Sample7YOffset_start 120 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_MULTISAMPLE_Sample7YOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 120; case 70: return 120; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PIPELINED_POINTERS */ #define GFX5_3DSTATE_PIPELINED_POINTERS_length 7 #define GFX45_3DSTATE_PIPELINED_POINTERS_length 7 #define GFX4_3DSTATE_PIPELINED_POINTERS_length 7 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PIPELINED_POINTERS_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 7; case 45: return 7; case 40: return 7; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PIPELINED_POINTERS::3D Command Opcode */ #define GFX5_3DSTATE_PIPELINED_POINTERS_3DCommandOpcode_bits 3 #define GFX45_3DSTATE_PIPELINED_POINTERS_3DCommandOpcode_bits 3 #define GFX4_3DSTATE_PIPELINED_POINTERS_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PIPELINED_POINTERS_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX5_3DSTATE_PIPELINED_POINTERS_3DCommandOpcode_start 24 #define GFX45_3DSTATE_PIPELINED_POINTERS_3DCommandOpcode_start 24 #define GFX4_3DSTATE_PIPELINED_POINTERS_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PIPELINED_POINTERS_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 24; case 45: return 24; case 40: return 24; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PIPELINED_POINTERS::3D Command Sub Opcode */ #define GFX5_3DSTATE_PIPELINED_POINTERS_3DCommandSubOpcode_bits 8 #define GFX45_3DSTATE_PIPELINED_POINTERS_3DCommandSubOpcode_bits 8 #define GFX4_3DSTATE_PIPELINED_POINTERS_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PIPELINED_POINTERS_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 8; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } #define GFX5_3DSTATE_PIPELINED_POINTERS_3DCommandSubOpcode_start 16 #define GFX45_3DSTATE_PIPELINED_POINTERS_3DCommandSubOpcode_start 16 #define GFX4_3DSTATE_PIPELINED_POINTERS_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PIPELINED_POINTERS_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 16; case 45: return 16; case 40: return 16; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PIPELINED_POINTERS::Clip Enable */ #define GFX5_3DSTATE_PIPELINED_POINTERS_ClipEnable_bits 1 #define GFX45_3DSTATE_PIPELINED_POINTERS_ClipEnable_bits 1 #define GFX4_3DSTATE_PIPELINED_POINTERS_ClipEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PIPELINED_POINTERS_ClipEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_3DSTATE_PIPELINED_POINTERS_ClipEnable_start 96 #define GFX45_3DSTATE_PIPELINED_POINTERS_ClipEnable_start 96 #define GFX4_3DSTATE_PIPELINED_POINTERS_ClipEnable_start 96 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PIPELINED_POINTERS_ClipEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 96; case 45: return 96; case 40: return 96; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PIPELINED_POINTERS::Command SubType */ #define GFX5_3DSTATE_PIPELINED_POINTERS_CommandSubType_bits 2 #define GFX45_3DSTATE_PIPELINED_POINTERS_CommandSubType_bits 2 #define GFX4_3DSTATE_PIPELINED_POINTERS_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PIPELINED_POINTERS_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 2; case 45: return 2; case 40: return 2; default: unreachable("Invalid hardware generation"); } } #define GFX5_3DSTATE_PIPELINED_POINTERS_CommandSubType_start 27 #define GFX45_3DSTATE_PIPELINED_POINTERS_CommandSubType_start 27 #define GFX4_3DSTATE_PIPELINED_POINTERS_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PIPELINED_POINTERS_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 27; case 45: return 27; case 40: return 27; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PIPELINED_POINTERS::Command Type */ #define GFX5_3DSTATE_PIPELINED_POINTERS_CommandType_bits 3 #define GFX45_3DSTATE_PIPELINED_POINTERS_CommandType_bits 3 #define GFX4_3DSTATE_PIPELINED_POINTERS_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PIPELINED_POINTERS_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX5_3DSTATE_PIPELINED_POINTERS_CommandType_start 29 #define GFX45_3DSTATE_PIPELINED_POINTERS_CommandType_start 29 #define GFX4_3DSTATE_PIPELINED_POINTERS_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PIPELINED_POINTERS_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 29; case 45: return 29; case 40: return 29; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PIPELINED_POINTERS::DWord Length */ #define GFX5_3DSTATE_PIPELINED_POINTERS_DWordLength_bits 8 #define GFX45_3DSTATE_PIPELINED_POINTERS_DWordLength_bits 8 #define GFX4_3DSTATE_PIPELINED_POINTERS_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PIPELINED_POINTERS_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 8; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } #define GFX5_3DSTATE_PIPELINED_POINTERS_DWordLength_start 0 #define GFX45_3DSTATE_PIPELINED_POINTERS_DWordLength_start 0 #define GFX4_3DSTATE_PIPELINED_POINTERS_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PIPELINED_POINTERS_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PIPELINED_POINTERS::GS Enable */ #define GFX5_3DSTATE_PIPELINED_POINTERS_GSEnable_bits 1 #define GFX45_3DSTATE_PIPELINED_POINTERS_GSEnable_bits 1 #define GFX4_3DSTATE_PIPELINED_POINTERS_GSEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PIPELINED_POINTERS_GSEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_3DSTATE_PIPELINED_POINTERS_GSEnable_start 64 #define GFX45_3DSTATE_PIPELINED_POINTERS_GSEnable_start 64 #define GFX4_3DSTATE_PIPELINED_POINTERS_GSEnable_start 64 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PIPELINED_POINTERS_GSEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 64; case 45: return 64; case 40: return 64; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PIPELINED_POINTERS::Pointer to CLIP State */ #define GFX5_3DSTATE_PIPELINED_POINTERS_PointertoCLIPState_bits 27 #define GFX45_3DSTATE_PIPELINED_POINTERS_PointertoCLIPState_bits 27 #define GFX4_3DSTATE_PIPELINED_POINTERS_PointertoCLIPState_bits 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PIPELINED_POINTERS_PointertoCLIPState_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 27; case 45: return 27; case 40: return 27; default: unreachable("Invalid hardware generation"); } } #define GFX5_3DSTATE_PIPELINED_POINTERS_PointertoCLIPState_start 101 #define GFX45_3DSTATE_PIPELINED_POINTERS_PointertoCLIPState_start 101 #define GFX4_3DSTATE_PIPELINED_POINTERS_PointertoCLIPState_start 101 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PIPELINED_POINTERS_PointertoCLIPState_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 101; case 45: return 101; case 40: return 101; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PIPELINED_POINTERS::Pointer to Color Calc State */ #define GFX5_3DSTATE_PIPELINED_POINTERS_PointertoColorCalcState_bits 27 #define GFX45_3DSTATE_PIPELINED_POINTERS_PointertoColorCalcState_bits 27 #define GFX4_3DSTATE_PIPELINED_POINTERS_PointertoColorCalcState_bits 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PIPELINED_POINTERS_PointertoColorCalcState_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 27; case 45: return 27; case 40: return 27; default: unreachable("Invalid hardware generation"); } } #define GFX5_3DSTATE_PIPELINED_POINTERS_PointertoColorCalcState_start 197 #define GFX45_3DSTATE_PIPELINED_POINTERS_PointertoColorCalcState_start 197 #define GFX4_3DSTATE_PIPELINED_POINTERS_PointertoColorCalcState_start 197 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PIPELINED_POINTERS_PointertoColorCalcState_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 197; case 45: return 197; case 40: return 197; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PIPELINED_POINTERS::Pointer to GS State */ #define GFX5_3DSTATE_PIPELINED_POINTERS_PointertoGSState_bits 27 #define GFX45_3DSTATE_PIPELINED_POINTERS_PointertoGSState_bits 27 #define GFX4_3DSTATE_PIPELINED_POINTERS_PointertoGSState_bits 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PIPELINED_POINTERS_PointertoGSState_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 27; case 45: return 27; case 40: return 27; default: unreachable("Invalid hardware generation"); } } #define GFX5_3DSTATE_PIPELINED_POINTERS_PointertoGSState_start 69 #define GFX45_3DSTATE_PIPELINED_POINTERS_PointertoGSState_start 69 #define GFX4_3DSTATE_PIPELINED_POINTERS_PointertoGSState_start 69 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PIPELINED_POINTERS_PointertoGSState_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 69; case 45: return 69; case 40: return 69; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PIPELINED_POINTERS::Pointer to SF State */ #define GFX5_3DSTATE_PIPELINED_POINTERS_PointertoSFState_bits 27 #define GFX45_3DSTATE_PIPELINED_POINTERS_PointertoSFState_bits 27 #define GFX4_3DSTATE_PIPELINED_POINTERS_PointertoSFState_bits 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PIPELINED_POINTERS_PointertoSFState_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 27; case 45: return 27; case 40: return 27; default: unreachable("Invalid hardware generation"); } } #define GFX5_3DSTATE_PIPELINED_POINTERS_PointertoSFState_start 133 #define GFX45_3DSTATE_PIPELINED_POINTERS_PointertoSFState_start 133 #define GFX4_3DSTATE_PIPELINED_POINTERS_PointertoSFState_start 133 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PIPELINED_POINTERS_PointertoSFState_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 133; case 45: return 133; case 40: return 133; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PIPELINED_POINTERS::Pointer to VS State */ #define GFX5_3DSTATE_PIPELINED_POINTERS_PointertoVSState_bits 27 #define GFX45_3DSTATE_PIPELINED_POINTERS_PointertoVSState_bits 27 #define GFX4_3DSTATE_PIPELINED_POINTERS_PointertoVSState_bits 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PIPELINED_POINTERS_PointertoVSState_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 27; case 45: return 27; case 40: return 27; default: unreachable("Invalid hardware generation"); } } #define GFX5_3DSTATE_PIPELINED_POINTERS_PointertoVSState_start 37 #define GFX45_3DSTATE_PIPELINED_POINTERS_PointertoVSState_start 37 #define GFX4_3DSTATE_PIPELINED_POINTERS_PointertoVSState_start 37 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PIPELINED_POINTERS_PointertoVSState_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 37; case 45: return 37; case 40: return 37; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PIPELINED_POINTERS::Pointer to WM State */ #define GFX5_3DSTATE_PIPELINED_POINTERS_PointertoWMState_bits 27 #define GFX45_3DSTATE_PIPELINED_POINTERS_PointertoWMState_bits 27 #define GFX4_3DSTATE_PIPELINED_POINTERS_PointertoWMState_bits 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PIPELINED_POINTERS_PointertoWMState_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 27; case 45: return 27; case 40: return 27; default: unreachable("Invalid hardware generation"); } } #define GFX5_3DSTATE_PIPELINED_POINTERS_PointertoWMState_start 165 #define GFX45_3DSTATE_PIPELINED_POINTERS_PointertoWMState_start 165 #define GFX4_3DSTATE_PIPELINED_POINTERS_PointertoWMState_start 165 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PIPELINED_POINTERS_PointertoWMState_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 165; case 45: return 165; case 40: return 165; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_POLY_STIPPLE_OFFSET */ #define GFX125_3DSTATE_POLY_STIPPLE_OFFSET_length 2 #define GFX12_3DSTATE_POLY_STIPPLE_OFFSET_length 2 #define GFX11_3DSTATE_POLY_STIPPLE_OFFSET_length 2 #define GFX9_3DSTATE_POLY_STIPPLE_OFFSET_length 2 #define GFX8_3DSTATE_POLY_STIPPLE_OFFSET_length 2 #define GFX75_3DSTATE_POLY_STIPPLE_OFFSET_length 2 #define GFX7_3DSTATE_POLY_STIPPLE_OFFSET_length 2 #define GFX6_3DSTATE_POLY_STIPPLE_OFFSET_length 2 #define GFX5_3DSTATE_POLY_STIPPLE_OFFSET_length 2 #define GFX45_3DSTATE_POLY_STIPPLE_OFFSET_length 2 #define GFX4_3DSTATE_POLY_STIPPLE_OFFSET_length 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_POLY_STIPPLE_OFFSET_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 2; case 45: return 2; case 40: return 2; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_POLY_STIPPLE_OFFSET::3D Command Opcode */ #define GFX125_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandOpcode_bits 3 #define GFX75_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandOpcode_bits 3 #define GFX7_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandOpcode_bits 3 #define GFX6_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandOpcode_bits 3 #define GFX5_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandOpcode_bits 3 #define GFX45_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandOpcode_bits 3 #define GFX4_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_POLY_STIPPLE_OFFSET_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandOpcode_start 24 #define GFX12_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandOpcode_start 24 #define GFX11_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandOpcode_start 24 #define GFX9_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandOpcode_start 24 #define GFX8_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandOpcode_start 24 #define GFX75_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandOpcode_start 24 #define GFX7_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandOpcode_start 24 #define GFX6_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandOpcode_start 24 #define GFX5_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandOpcode_start 24 #define GFX45_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandOpcode_start 24 #define GFX4_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_POLY_STIPPLE_OFFSET_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 24; case 50: return 24; case 45: return 24; case 40: return 24; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_POLY_STIPPLE_OFFSET::3D Command Sub Opcode */ #define GFX125_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandSubOpcode_bits 8 #define GFX75_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandSubOpcode_bits 8 #define GFX7_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandSubOpcode_bits 8 #define GFX6_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandSubOpcode_bits 8 #define GFX5_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandSubOpcode_bits 8 #define GFX45_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandSubOpcode_bits 8 #define GFX4_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_POLY_STIPPLE_OFFSET_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 8; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandSubOpcode_start 16 #define GFX75_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandSubOpcode_start 16 #define GFX7_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandSubOpcode_start 16 #define GFX6_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandSubOpcode_start 16 #define GFX5_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandSubOpcode_start 16 #define GFX45_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandSubOpcode_start 16 #define GFX4_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_POLY_STIPPLE_OFFSET_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 16; case 50: return 16; case 45: return 16; case 40: return 16; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_POLY_STIPPLE_OFFSET::Command SubType */ #define GFX125_3DSTATE_POLY_STIPPLE_OFFSET_CommandSubType_bits 2 #define GFX12_3DSTATE_POLY_STIPPLE_OFFSET_CommandSubType_bits 2 #define GFX11_3DSTATE_POLY_STIPPLE_OFFSET_CommandSubType_bits 2 #define GFX9_3DSTATE_POLY_STIPPLE_OFFSET_CommandSubType_bits 2 #define GFX8_3DSTATE_POLY_STIPPLE_OFFSET_CommandSubType_bits 2 #define GFX75_3DSTATE_POLY_STIPPLE_OFFSET_CommandSubType_bits 2 #define GFX7_3DSTATE_POLY_STIPPLE_OFFSET_CommandSubType_bits 2 #define GFX6_3DSTATE_POLY_STIPPLE_OFFSET_CommandSubType_bits 2 #define GFX5_3DSTATE_POLY_STIPPLE_OFFSET_CommandSubType_bits 2 #define GFX45_3DSTATE_POLY_STIPPLE_OFFSET_CommandSubType_bits 2 #define GFX4_3DSTATE_POLY_STIPPLE_OFFSET_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_POLY_STIPPLE_OFFSET_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 2; case 45: return 2; case 40: return 2; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_POLY_STIPPLE_OFFSET_CommandSubType_start 27 #define GFX12_3DSTATE_POLY_STIPPLE_OFFSET_CommandSubType_start 27 #define GFX11_3DSTATE_POLY_STIPPLE_OFFSET_CommandSubType_start 27 #define GFX9_3DSTATE_POLY_STIPPLE_OFFSET_CommandSubType_start 27 #define GFX8_3DSTATE_POLY_STIPPLE_OFFSET_CommandSubType_start 27 #define GFX75_3DSTATE_POLY_STIPPLE_OFFSET_CommandSubType_start 27 #define GFX7_3DSTATE_POLY_STIPPLE_OFFSET_CommandSubType_start 27 #define GFX6_3DSTATE_POLY_STIPPLE_OFFSET_CommandSubType_start 27 #define GFX5_3DSTATE_POLY_STIPPLE_OFFSET_CommandSubType_start 27 #define GFX45_3DSTATE_POLY_STIPPLE_OFFSET_CommandSubType_start 27 #define GFX4_3DSTATE_POLY_STIPPLE_OFFSET_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_POLY_STIPPLE_OFFSET_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 27; case 50: return 27; case 45: return 27; case 40: return 27; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_POLY_STIPPLE_OFFSET::Command Type */ #define GFX125_3DSTATE_POLY_STIPPLE_OFFSET_CommandType_bits 3 #define GFX12_3DSTATE_POLY_STIPPLE_OFFSET_CommandType_bits 3 #define GFX11_3DSTATE_POLY_STIPPLE_OFFSET_CommandType_bits 3 #define GFX9_3DSTATE_POLY_STIPPLE_OFFSET_CommandType_bits 3 #define GFX8_3DSTATE_POLY_STIPPLE_OFFSET_CommandType_bits 3 #define GFX75_3DSTATE_POLY_STIPPLE_OFFSET_CommandType_bits 3 #define GFX7_3DSTATE_POLY_STIPPLE_OFFSET_CommandType_bits 3 #define GFX6_3DSTATE_POLY_STIPPLE_OFFSET_CommandType_bits 3 #define GFX5_3DSTATE_POLY_STIPPLE_OFFSET_CommandType_bits 3 #define GFX45_3DSTATE_POLY_STIPPLE_OFFSET_CommandType_bits 3 #define GFX4_3DSTATE_POLY_STIPPLE_OFFSET_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_POLY_STIPPLE_OFFSET_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_POLY_STIPPLE_OFFSET_CommandType_start 29 #define GFX12_3DSTATE_POLY_STIPPLE_OFFSET_CommandType_start 29 #define GFX11_3DSTATE_POLY_STIPPLE_OFFSET_CommandType_start 29 #define GFX9_3DSTATE_POLY_STIPPLE_OFFSET_CommandType_start 29 #define GFX8_3DSTATE_POLY_STIPPLE_OFFSET_CommandType_start 29 #define GFX75_3DSTATE_POLY_STIPPLE_OFFSET_CommandType_start 29 #define GFX7_3DSTATE_POLY_STIPPLE_OFFSET_CommandType_start 29 #define GFX6_3DSTATE_POLY_STIPPLE_OFFSET_CommandType_start 29 #define GFX5_3DSTATE_POLY_STIPPLE_OFFSET_CommandType_start 29 #define GFX45_3DSTATE_POLY_STIPPLE_OFFSET_CommandType_start 29 #define GFX4_3DSTATE_POLY_STIPPLE_OFFSET_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_POLY_STIPPLE_OFFSET_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 29; case 50: return 29; case 45: return 29; case 40: return 29; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_POLY_STIPPLE_OFFSET::DWord Length */ #define GFX125_3DSTATE_POLY_STIPPLE_OFFSET_DWordLength_bits 8 #define GFX12_3DSTATE_POLY_STIPPLE_OFFSET_DWordLength_bits 8 #define GFX11_3DSTATE_POLY_STIPPLE_OFFSET_DWordLength_bits 8 #define GFX9_3DSTATE_POLY_STIPPLE_OFFSET_DWordLength_bits 8 #define GFX8_3DSTATE_POLY_STIPPLE_OFFSET_DWordLength_bits 8 #define GFX75_3DSTATE_POLY_STIPPLE_OFFSET_DWordLength_bits 8 #define GFX7_3DSTATE_POLY_STIPPLE_OFFSET_DWordLength_bits 8 #define GFX6_3DSTATE_POLY_STIPPLE_OFFSET_DWordLength_bits 8 #define GFX5_3DSTATE_POLY_STIPPLE_OFFSET_DWordLength_bits 8 #define GFX45_3DSTATE_POLY_STIPPLE_OFFSET_DWordLength_bits 8 #define GFX4_3DSTATE_POLY_STIPPLE_OFFSET_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_POLY_STIPPLE_OFFSET_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 8; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_POLY_STIPPLE_OFFSET_DWordLength_start 0 #define GFX12_3DSTATE_POLY_STIPPLE_OFFSET_DWordLength_start 0 #define GFX11_3DSTATE_POLY_STIPPLE_OFFSET_DWordLength_start 0 #define GFX9_3DSTATE_POLY_STIPPLE_OFFSET_DWordLength_start 0 #define GFX8_3DSTATE_POLY_STIPPLE_OFFSET_DWordLength_start 0 #define GFX75_3DSTATE_POLY_STIPPLE_OFFSET_DWordLength_start 0 #define GFX7_3DSTATE_POLY_STIPPLE_OFFSET_DWordLength_start 0 #define GFX6_3DSTATE_POLY_STIPPLE_OFFSET_DWordLength_start 0 #define GFX5_3DSTATE_POLY_STIPPLE_OFFSET_DWordLength_start 0 #define GFX45_3DSTATE_POLY_STIPPLE_OFFSET_DWordLength_start 0 #define GFX4_3DSTATE_POLY_STIPPLE_OFFSET_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_POLY_STIPPLE_OFFSET_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_POLY_STIPPLE_OFFSET::Polygon Stipple X Offset */ #define GFX125_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleXOffset_bits 5 #define GFX12_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleXOffset_bits 5 #define GFX11_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleXOffset_bits 5 #define GFX9_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleXOffset_bits 5 #define GFX8_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleXOffset_bits 5 #define GFX75_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleXOffset_bits 5 #define GFX7_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleXOffset_bits 5 #define GFX6_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleXOffset_bits 5 #define GFX5_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleXOffset_bits 5 #define GFX45_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleXOffset_bits 5 #define GFX4_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleXOffset_bits 5 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleXOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 5; case 110: return 5; case 90: return 5; case 80: return 5; case 75: return 5; case 70: return 5; case 60: return 5; case 50: return 5; case 45: return 5; case 40: return 5; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleXOffset_start 40 #define GFX12_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleXOffset_start 40 #define GFX11_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleXOffset_start 40 #define GFX9_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleXOffset_start 40 #define GFX8_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleXOffset_start 40 #define GFX75_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleXOffset_start 40 #define GFX7_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleXOffset_start 40 #define GFX6_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleXOffset_start 40 #define GFX5_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleXOffset_start 40 #define GFX45_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleXOffset_start 40 #define GFX4_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleXOffset_start 40 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleXOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 40; case 120: return 40; case 110: return 40; case 90: return 40; case 80: return 40; case 75: return 40; case 70: return 40; case 60: return 40; case 50: return 40; case 45: return 40; case 40: return 40; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_POLY_STIPPLE_OFFSET::Polygon Stipple Y Offset */ #define GFX125_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleYOffset_bits 5 #define GFX12_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleYOffset_bits 5 #define GFX11_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleYOffset_bits 5 #define GFX9_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleYOffset_bits 5 #define GFX8_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleYOffset_bits 5 #define GFX75_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleYOffset_bits 5 #define GFX7_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleYOffset_bits 5 #define GFX6_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleYOffset_bits 5 #define GFX5_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleYOffset_bits 5 #define GFX45_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleYOffset_bits 5 #define GFX4_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleYOffset_bits 5 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleYOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 5; case 110: return 5; case 90: return 5; case 80: return 5; case 75: return 5; case 70: return 5; case 60: return 5; case 50: return 5; case 45: return 5; case 40: return 5; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleYOffset_start 32 #define GFX12_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleYOffset_start 32 #define GFX11_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleYOffset_start 32 #define GFX9_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleYOffset_start 32 #define GFX8_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleYOffset_start 32 #define GFX75_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleYOffset_start 32 #define GFX7_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleYOffset_start 32 #define GFX6_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleYOffset_start 32 #define GFX5_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleYOffset_start 32 #define GFX45_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleYOffset_start 32 #define GFX4_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleYOffset_start 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleYOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 32; case 50: return 32; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_POLY_STIPPLE_PATTERN */ #define GFX125_3DSTATE_POLY_STIPPLE_PATTERN_length 33 #define GFX12_3DSTATE_POLY_STIPPLE_PATTERN_length 33 #define GFX11_3DSTATE_POLY_STIPPLE_PATTERN_length 33 #define GFX9_3DSTATE_POLY_STIPPLE_PATTERN_length 33 #define GFX8_3DSTATE_POLY_STIPPLE_PATTERN_length 33 #define GFX75_3DSTATE_POLY_STIPPLE_PATTERN_length 33 #define GFX7_3DSTATE_POLY_STIPPLE_PATTERN_length 33 #define GFX6_3DSTATE_POLY_STIPPLE_PATTERN_length 33 #define GFX5_3DSTATE_POLY_STIPPLE_PATTERN_length 33 #define GFX45_3DSTATE_POLY_STIPPLE_PATTERN_length 33 #define GFX4_3DSTATE_POLY_STIPPLE_PATTERN_length 33 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_POLY_STIPPLE_PATTERN_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 33; case 120: return 33; case 110: return 33; case 90: return 33; case 80: return 33; case 75: return 33; case 70: return 33; case 60: return 33; case 50: return 33; case 45: return 33; case 40: return 33; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_POLY_STIPPLE_PATTERN::3D Command Opcode */ #define GFX125_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandOpcode_bits 3 #define GFX75_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandOpcode_bits 3 #define GFX7_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandOpcode_bits 3 #define GFX6_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandOpcode_bits 3 #define GFX5_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandOpcode_bits 3 #define GFX45_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandOpcode_bits 3 #define GFX4_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_POLY_STIPPLE_PATTERN_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandOpcode_start 24 #define GFX12_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandOpcode_start 24 #define GFX11_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandOpcode_start 24 #define GFX9_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandOpcode_start 24 #define GFX8_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandOpcode_start 24 #define GFX75_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandOpcode_start 24 #define GFX7_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandOpcode_start 24 #define GFX6_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandOpcode_start 24 #define GFX5_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandOpcode_start 24 #define GFX45_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandOpcode_start 24 #define GFX4_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_POLY_STIPPLE_PATTERN_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 24; case 50: return 24; case 45: return 24; case 40: return 24; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_POLY_STIPPLE_PATTERN::3D Command Sub Opcode */ #define GFX125_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandSubOpcode_bits 8 #define GFX75_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandSubOpcode_bits 8 #define GFX7_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandSubOpcode_bits 8 #define GFX6_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandSubOpcode_bits 8 #define GFX5_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandSubOpcode_bits 8 #define GFX45_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandSubOpcode_bits 8 #define GFX4_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_POLY_STIPPLE_PATTERN_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 8; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandSubOpcode_start 16 #define GFX75_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandSubOpcode_start 16 #define GFX7_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandSubOpcode_start 16 #define GFX6_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandSubOpcode_start 16 #define GFX5_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandSubOpcode_start 16 #define GFX45_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandSubOpcode_start 16 #define GFX4_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_POLY_STIPPLE_PATTERN_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 16; case 50: return 16; case 45: return 16; case 40: return 16; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_POLY_STIPPLE_PATTERN::Command SubType */ #define GFX125_3DSTATE_POLY_STIPPLE_PATTERN_CommandSubType_bits 2 #define GFX12_3DSTATE_POLY_STIPPLE_PATTERN_CommandSubType_bits 2 #define GFX11_3DSTATE_POLY_STIPPLE_PATTERN_CommandSubType_bits 2 #define GFX9_3DSTATE_POLY_STIPPLE_PATTERN_CommandSubType_bits 2 #define GFX8_3DSTATE_POLY_STIPPLE_PATTERN_CommandSubType_bits 2 #define GFX75_3DSTATE_POLY_STIPPLE_PATTERN_CommandSubType_bits 2 #define GFX7_3DSTATE_POLY_STIPPLE_PATTERN_CommandSubType_bits 2 #define GFX6_3DSTATE_POLY_STIPPLE_PATTERN_CommandSubType_bits 2 #define GFX5_3DSTATE_POLY_STIPPLE_PATTERN_CommandSubType_bits 2 #define GFX45_3DSTATE_POLY_STIPPLE_PATTERN_CommandSubType_bits 2 #define GFX4_3DSTATE_POLY_STIPPLE_PATTERN_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_POLY_STIPPLE_PATTERN_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 2; case 45: return 2; case 40: return 2; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_POLY_STIPPLE_PATTERN_CommandSubType_start 27 #define GFX12_3DSTATE_POLY_STIPPLE_PATTERN_CommandSubType_start 27 #define GFX11_3DSTATE_POLY_STIPPLE_PATTERN_CommandSubType_start 27 #define GFX9_3DSTATE_POLY_STIPPLE_PATTERN_CommandSubType_start 27 #define GFX8_3DSTATE_POLY_STIPPLE_PATTERN_CommandSubType_start 27 #define GFX75_3DSTATE_POLY_STIPPLE_PATTERN_CommandSubType_start 27 #define GFX7_3DSTATE_POLY_STIPPLE_PATTERN_CommandSubType_start 27 #define GFX6_3DSTATE_POLY_STIPPLE_PATTERN_CommandSubType_start 27 #define GFX5_3DSTATE_POLY_STIPPLE_PATTERN_CommandSubType_start 27 #define GFX45_3DSTATE_POLY_STIPPLE_PATTERN_CommandSubType_start 27 #define GFX4_3DSTATE_POLY_STIPPLE_PATTERN_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_POLY_STIPPLE_PATTERN_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 27; case 50: return 27; case 45: return 27; case 40: return 27; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_POLY_STIPPLE_PATTERN::Command Type */ #define GFX125_3DSTATE_POLY_STIPPLE_PATTERN_CommandType_bits 3 #define GFX12_3DSTATE_POLY_STIPPLE_PATTERN_CommandType_bits 3 #define GFX11_3DSTATE_POLY_STIPPLE_PATTERN_CommandType_bits 3 #define GFX9_3DSTATE_POLY_STIPPLE_PATTERN_CommandType_bits 3 #define GFX8_3DSTATE_POLY_STIPPLE_PATTERN_CommandType_bits 3 #define GFX75_3DSTATE_POLY_STIPPLE_PATTERN_CommandType_bits 3 #define GFX7_3DSTATE_POLY_STIPPLE_PATTERN_CommandType_bits 3 #define GFX6_3DSTATE_POLY_STIPPLE_PATTERN_CommandType_bits 3 #define GFX5_3DSTATE_POLY_STIPPLE_PATTERN_CommandType_bits 3 #define GFX45_3DSTATE_POLY_STIPPLE_PATTERN_CommandType_bits 3 #define GFX4_3DSTATE_POLY_STIPPLE_PATTERN_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_POLY_STIPPLE_PATTERN_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_POLY_STIPPLE_PATTERN_CommandType_start 29 #define GFX12_3DSTATE_POLY_STIPPLE_PATTERN_CommandType_start 29 #define GFX11_3DSTATE_POLY_STIPPLE_PATTERN_CommandType_start 29 #define GFX9_3DSTATE_POLY_STIPPLE_PATTERN_CommandType_start 29 #define GFX8_3DSTATE_POLY_STIPPLE_PATTERN_CommandType_start 29 #define GFX75_3DSTATE_POLY_STIPPLE_PATTERN_CommandType_start 29 #define GFX7_3DSTATE_POLY_STIPPLE_PATTERN_CommandType_start 29 #define GFX6_3DSTATE_POLY_STIPPLE_PATTERN_CommandType_start 29 #define GFX5_3DSTATE_POLY_STIPPLE_PATTERN_CommandType_start 29 #define GFX45_3DSTATE_POLY_STIPPLE_PATTERN_CommandType_start 29 #define GFX4_3DSTATE_POLY_STIPPLE_PATTERN_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_POLY_STIPPLE_PATTERN_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 29; case 50: return 29; case 45: return 29; case 40: return 29; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_POLY_STIPPLE_PATTERN::DWord Length */ #define GFX125_3DSTATE_POLY_STIPPLE_PATTERN_DWordLength_bits 8 #define GFX12_3DSTATE_POLY_STIPPLE_PATTERN_DWordLength_bits 8 #define GFX11_3DSTATE_POLY_STIPPLE_PATTERN_DWordLength_bits 8 #define GFX9_3DSTATE_POLY_STIPPLE_PATTERN_DWordLength_bits 8 #define GFX8_3DSTATE_POLY_STIPPLE_PATTERN_DWordLength_bits 8 #define GFX75_3DSTATE_POLY_STIPPLE_PATTERN_DWordLength_bits 8 #define GFX7_3DSTATE_POLY_STIPPLE_PATTERN_DWordLength_bits 8 #define GFX6_3DSTATE_POLY_STIPPLE_PATTERN_DWordLength_bits 8 #define GFX5_3DSTATE_POLY_STIPPLE_PATTERN_DWordLength_bits 8 #define GFX45_3DSTATE_POLY_STIPPLE_PATTERN_DWordLength_bits 8 #define GFX4_3DSTATE_POLY_STIPPLE_PATTERN_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_POLY_STIPPLE_PATTERN_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 8; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_POLY_STIPPLE_PATTERN_DWordLength_start 0 #define GFX12_3DSTATE_POLY_STIPPLE_PATTERN_DWordLength_start 0 #define GFX11_3DSTATE_POLY_STIPPLE_PATTERN_DWordLength_start 0 #define GFX9_3DSTATE_POLY_STIPPLE_PATTERN_DWordLength_start 0 #define GFX8_3DSTATE_POLY_STIPPLE_PATTERN_DWordLength_start 0 #define GFX75_3DSTATE_POLY_STIPPLE_PATTERN_DWordLength_start 0 #define GFX7_3DSTATE_POLY_STIPPLE_PATTERN_DWordLength_start 0 #define GFX6_3DSTATE_POLY_STIPPLE_PATTERN_DWordLength_start 0 #define GFX5_3DSTATE_POLY_STIPPLE_PATTERN_DWordLength_start 0 #define GFX45_3DSTATE_POLY_STIPPLE_PATTERN_DWordLength_start 0 #define GFX4_3DSTATE_POLY_STIPPLE_PATTERN_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_POLY_STIPPLE_PATTERN_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PRIMITIVE_REPLICATION */ #define GFX125_3DSTATE_PRIMITIVE_REPLICATION_length 6 #define GFX12_3DSTATE_PRIMITIVE_REPLICATION_length 6 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PRIMITIVE_REPLICATION_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PRIMITIVE_REPLICATION::3D Command Opcode */ #define GFX125_3DSTATE_PRIMITIVE_REPLICATION_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_PRIMITIVE_REPLICATION_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PRIMITIVE_REPLICATION_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PRIMITIVE_REPLICATION_3DCommandOpcode_start 24 #define GFX12_3DSTATE_PRIMITIVE_REPLICATION_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PRIMITIVE_REPLICATION_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PRIMITIVE_REPLICATION::3D Command Sub Opcode */ #define GFX125_3DSTATE_PRIMITIVE_REPLICATION_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_PRIMITIVE_REPLICATION_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PRIMITIVE_REPLICATION_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PRIMITIVE_REPLICATION_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_PRIMITIVE_REPLICATION_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PRIMITIVE_REPLICATION_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PRIMITIVE_REPLICATION::Command SubType */ #define GFX125_3DSTATE_PRIMITIVE_REPLICATION_CommandSubType_bits 2 #define GFX12_3DSTATE_PRIMITIVE_REPLICATION_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PRIMITIVE_REPLICATION_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PRIMITIVE_REPLICATION_CommandSubType_start 27 #define GFX12_3DSTATE_PRIMITIVE_REPLICATION_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PRIMITIVE_REPLICATION_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PRIMITIVE_REPLICATION::Command Type */ #define GFX125_3DSTATE_PRIMITIVE_REPLICATION_CommandType_bits 3 #define GFX12_3DSTATE_PRIMITIVE_REPLICATION_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PRIMITIVE_REPLICATION_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PRIMITIVE_REPLICATION_CommandType_start 29 #define GFX12_3DSTATE_PRIMITIVE_REPLICATION_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PRIMITIVE_REPLICATION_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PRIMITIVE_REPLICATION::DWord Length */ #define GFX125_3DSTATE_PRIMITIVE_REPLICATION_DWordLength_bits 8 #define GFX12_3DSTATE_PRIMITIVE_REPLICATION_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PRIMITIVE_REPLICATION_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PRIMITIVE_REPLICATION_DWordLength_start 0 #define GFX12_3DSTATE_PRIMITIVE_REPLICATION_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PRIMITIVE_REPLICATION_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PRIMITIVE_REPLICATION::Replica Mask */ #define GFX125_3DSTATE_PRIMITIVE_REPLICATION_ReplicaMask_bits 16 #define GFX12_3DSTATE_PRIMITIVE_REPLICATION_ReplicaMask_bits 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PRIMITIVE_REPLICATION_ReplicaMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PRIMITIVE_REPLICATION_ReplicaMask_start 48 #define GFX12_3DSTATE_PRIMITIVE_REPLICATION_ReplicaMask_start 48 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PRIMITIVE_REPLICATION_ReplicaMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 48; case 120: return 48; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PRIMITIVE_REPLICATION::Replication Count */ #define GFX125_3DSTATE_PRIMITIVE_REPLICATION_ReplicationCount_bits 4 #define GFX12_3DSTATE_PRIMITIVE_REPLICATION_ReplicationCount_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PRIMITIVE_REPLICATION_ReplicationCount_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PRIMITIVE_REPLICATION_ReplicationCount_start 32 #define GFX12_3DSTATE_PRIMITIVE_REPLICATION_ReplicationCount_start 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PRIMITIVE_REPLICATION_ReplicationCount_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS */ #define GFX125_3DSTATE_PS_length 12 #define GFX12_3DSTATE_PS_length 12 #define GFX11_3DSTATE_PS_length 12 #define GFX9_3DSTATE_PS_length 12 #define GFX8_3DSTATE_PS_length 12 #define GFX75_3DSTATE_PS_length 8 #define GFX7_3DSTATE_PS_length 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 12; case 120: return 12; case 110: return 12; case 90: return 12; case 80: return 12; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS::16 Pixel Dispatch Enable */ #define GFX125_3DSTATE_PS_16PixelDispatchEnable_bits 1 #define GFX12_3DSTATE_PS_16PixelDispatchEnable_bits 1 #define GFX11_3DSTATE_PS_16PixelDispatchEnable_bits 1 #define GFX9_3DSTATE_PS_16PixelDispatchEnable_bits 1 #define GFX8_3DSTATE_PS_16PixelDispatchEnable_bits 1 #define GFX75_3DSTATE_PS_16PixelDispatchEnable_bits 1 #define GFX7_3DSTATE_PS_16PixelDispatchEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_16PixelDispatchEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PS_16PixelDispatchEnable_start 193 #define GFX12_3DSTATE_PS_16PixelDispatchEnable_start 193 #define GFX11_3DSTATE_PS_16PixelDispatchEnable_start 193 #define GFX9_3DSTATE_PS_16PixelDispatchEnable_start 193 #define GFX8_3DSTATE_PS_16PixelDispatchEnable_start 193 #define GFX75_3DSTATE_PS_16PixelDispatchEnable_start 129 #define GFX7_3DSTATE_PS_16PixelDispatchEnable_start 129 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_16PixelDispatchEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 193; case 120: return 193; case 110: return 193; case 90: return 193; case 80: return 193; case 75: return 129; case 70: return 129; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS::32 Pixel Dispatch Enable */ #define GFX125_3DSTATE_PS_32PixelDispatchEnable_bits 1 #define GFX12_3DSTATE_PS_32PixelDispatchEnable_bits 1 #define GFX11_3DSTATE_PS_32PixelDispatchEnable_bits 1 #define GFX9_3DSTATE_PS_32PixelDispatchEnable_bits 1 #define GFX8_3DSTATE_PS_32PixelDispatchEnable_bits 1 #define GFX75_3DSTATE_PS_32PixelDispatchEnable_bits 1 #define GFX7_3DSTATE_PS_32PixelDispatchEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_32PixelDispatchEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PS_32PixelDispatchEnable_start 194 #define GFX12_3DSTATE_PS_32PixelDispatchEnable_start 194 #define GFX11_3DSTATE_PS_32PixelDispatchEnable_start 194 #define GFX9_3DSTATE_PS_32PixelDispatchEnable_start 194 #define GFX8_3DSTATE_PS_32PixelDispatchEnable_start 194 #define GFX75_3DSTATE_PS_32PixelDispatchEnable_start 130 #define GFX7_3DSTATE_PS_32PixelDispatchEnable_start 130 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_32PixelDispatchEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 194; case 120: return 194; case 110: return 194; case 90: return 194; case 80: return 194; case 75: return 130; case 70: return 130; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS::3D Command Opcode */ #define GFX125_3DSTATE_PS_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_PS_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_PS_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_PS_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_PS_3DCommandOpcode_bits 3 #define GFX75_3DSTATE_PS_3DCommandOpcode_bits 3 #define GFX7_3DSTATE_PS_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PS_3DCommandOpcode_start 24 #define GFX12_3DSTATE_PS_3DCommandOpcode_start 24 #define GFX11_3DSTATE_PS_3DCommandOpcode_start 24 #define GFX9_3DSTATE_PS_3DCommandOpcode_start 24 #define GFX8_3DSTATE_PS_3DCommandOpcode_start 24 #define GFX75_3DSTATE_PS_3DCommandOpcode_start 24 #define GFX7_3DSTATE_PS_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS::3D Command Sub Opcode */ #define GFX125_3DSTATE_PS_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_PS_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_PS_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_PS_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_PS_3DCommandSubOpcode_bits 8 #define GFX75_3DSTATE_PS_3DCommandSubOpcode_bits 8 #define GFX7_3DSTATE_PS_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PS_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_PS_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_PS_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_PS_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_PS_3DCommandSubOpcode_start 16 #define GFX75_3DSTATE_PS_3DCommandSubOpcode_start 16 #define GFX7_3DSTATE_PS_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS::8 Pixel Dispatch Enable */ #define GFX125_3DSTATE_PS_8PixelDispatchEnable_bits 1 #define GFX12_3DSTATE_PS_8PixelDispatchEnable_bits 1 #define GFX11_3DSTATE_PS_8PixelDispatchEnable_bits 1 #define GFX9_3DSTATE_PS_8PixelDispatchEnable_bits 1 #define GFX8_3DSTATE_PS_8PixelDispatchEnable_bits 1 #define GFX75_3DSTATE_PS_8PixelDispatchEnable_bits 1 #define GFX7_3DSTATE_PS_8PixelDispatchEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_8PixelDispatchEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PS_8PixelDispatchEnable_start 192 #define GFX12_3DSTATE_PS_8PixelDispatchEnable_start 192 #define GFX11_3DSTATE_PS_8PixelDispatchEnable_start 192 #define GFX9_3DSTATE_PS_8PixelDispatchEnable_start 192 #define GFX8_3DSTATE_PS_8PixelDispatchEnable_start 192 #define GFX75_3DSTATE_PS_8PixelDispatchEnable_start 128 #define GFX7_3DSTATE_PS_8PixelDispatchEnable_start 128 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_8PixelDispatchEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 192; case 120: return 192; case 110: return 192; case 90: return 192; case 80: return 192; case 75: return 128; case 70: return 128; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS::Attribute Enable */ #define GFX75_3DSTATE_PS_AttributeEnable_bits 1 #define GFX7_3DSTATE_PS_AttributeEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_AttributeEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_PS_AttributeEnable_start 138 #define GFX7_3DSTATE_PS_AttributeEnable_start 138 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_AttributeEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 138; case 70: return 138; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS::Binding Table Entry Count */ #define GFX125_3DSTATE_PS_BindingTableEntryCount_bits 8 #define GFX12_3DSTATE_PS_BindingTableEntryCount_bits 8 #define GFX11_3DSTATE_PS_BindingTableEntryCount_bits 8 #define GFX9_3DSTATE_PS_BindingTableEntryCount_bits 8 #define GFX8_3DSTATE_PS_BindingTableEntryCount_bits 8 #define GFX75_3DSTATE_PS_BindingTableEntryCount_bits 8 #define GFX7_3DSTATE_PS_BindingTableEntryCount_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_BindingTableEntryCount_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PS_BindingTableEntryCount_start 114 #define GFX12_3DSTATE_PS_BindingTableEntryCount_start 114 #define GFX11_3DSTATE_PS_BindingTableEntryCount_start 114 #define GFX9_3DSTATE_PS_BindingTableEntryCount_start 114 #define GFX8_3DSTATE_PS_BindingTableEntryCount_start 114 #define GFX75_3DSTATE_PS_BindingTableEntryCount_start 82 #define GFX7_3DSTATE_PS_BindingTableEntryCount_start 82 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_BindingTableEntryCount_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 114; case 120: return 114; case 110: return 114; case 90: return 114; case 80: return 114; case 75: return 82; case 70: return 82; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS::Command SubType */ #define GFX125_3DSTATE_PS_CommandSubType_bits 2 #define GFX12_3DSTATE_PS_CommandSubType_bits 2 #define GFX11_3DSTATE_PS_CommandSubType_bits 2 #define GFX9_3DSTATE_PS_CommandSubType_bits 2 #define GFX8_3DSTATE_PS_CommandSubType_bits 2 #define GFX75_3DSTATE_PS_CommandSubType_bits 2 #define GFX7_3DSTATE_PS_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PS_CommandSubType_start 27 #define GFX12_3DSTATE_PS_CommandSubType_start 27 #define GFX11_3DSTATE_PS_CommandSubType_start 27 #define GFX9_3DSTATE_PS_CommandSubType_start 27 #define GFX8_3DSTATE_PS_CommandSubType_start 27 #define GFX75_3DSTATE_PS_CommandSubType_start 27 #define GFX7_3DSTATE_PS_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS::Command Type */ #define GFX125_3DSTATE_PS_CommandType_bits 3 #define GFX12_3DSTATE_PS_CommandType_bits 3 #define GFX11_3DSTATE_PS_CommandType_bits 3 #define GFX9_3DSTATE_PS_CommandType_bits 3 #define GFX8_3DSTATE_PS_CommandType_bits 3 #define GFX75_3DSTATE_PS_CommandType_bits 3 #define GFX7_3DSTATE_PS_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PS_CommandType_start 29 #define GFX12_3DSTATE_PS_CommandType_start 29 #define GFX11_3DSTATE_PS_CommandType_start 29 #define GFX9_3DSTATE_PS_CommandType_start 29 #define GFX8_3DSTATE_PS_CommandType_start 29 #define GFX75_3DSTATE_PS_CommandType_start 29 #define GFX7_3DSTATE_PS_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS::DWord Length */ #define GFX125_3DSTATE_PS_DWordLength_bits 8 #define GFX12_3DSTATE_PS_DWordLength_bits 8 #define GFX11_3DSTATE_PS_DWordLength_bits 8 #define GFX9_3DSTATE_PS_DWordLength_bits 8 #define GFX8_3DSTATE_PS_DWordLength_bits 8 #define GFX75_3DSTATE_PS_DWordLength_bits 8 #define GFX7_3DSTATE_PS_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PS_DWordLength_start 0 #define GFX12_3DSTATE_PS_DWordLength_start 0 #define GFX11_3DSTATE_PS_DWordLength_start 0 #define GFX9_3DSTATE_PS_DWordLength_start 0 #define GFX8_3DSTATE_PS_DWordLength_start 0 #define GFX75_3DSTATE_PS_DWordLength_start 0 #define GFX7_3DSTATE_PS_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS::Denormal Mode */ #define GFX75_3DSTATE_PS_DenormalMode_bits 1 #define GFX7_3DSTATE_PS_DenormalMode_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_DenormalMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_PS_DenormalMode_start 90 #define GFX7_3DSTATE_PS_DenormalMode_start 90 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_DenormalMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 90; case 70: return 90; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS::Dispatch GRF Start Register For Constant/Setup Data 0 */ #define GFX125_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData0_bits 7 #define GFX12_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData0_bits 7 #define GFX11_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData0_bits 7 #define GFX9_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData0_bits 7 #define GFX8_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData0_bits 7 #define GFX75_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData0_bits 7 #define GFX7_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData0_bits 7 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData0_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 7; case 120: return 7; case 110: return 7; case 90: return 7; case 80: return 7; case 75: return 7; case 70: return 7; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData0_start 240 #define GFX12_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData0_start 240 #define GFX11_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData0_start 240 #define GFX9_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData0_start 240 #define GFX8_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData0_start 240 #define GFX75_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData0_start 176 #define GFX7_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData0_start 176 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData0_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 240; case 120: return 240; case 110: return 240; case 90: return 240; case 80: return 240; case 75: return 176; case 70: return 176; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS::Dispatch GRF Start Register For Constant/Setup Data 1 */ #define GFX125_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData1_bits 7 #define GFX12_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData1_bits 7 #define GFX11_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData1_bits 7 #define GFX9_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData1_bits 7 #define GFX8_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData1_bits 7 #define GFX75_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData1_bits 7 #define GFX7_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData1_bits 7 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData1_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 7; case 120: return 7; case 110: return 7; case 90: return 7; case 80: return 7; case 75: return 7; case 70: return 7; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData1_start 232 #define GFX12_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData1_start 232 #define GFX11_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData1_start 232 #define GFX9_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData1_start 232 #define GFX8_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData1_start 232 #define GFX75_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData1_start 168 #define GFX7_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData1_start 168 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData1_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 232; case 120: return 232; case 110: return 232; case 90: return 232; case 80: return 232; case 75: return 168; case 70: return 168; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS::Dispatch GRF Start Register For Constant/Setup Data 2 */ #define GFX125_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData2_bits 7 #define GFX12_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData2_bits 7 #define GFX11_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData2_bits 7 #define GFX9_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData2_bits 7 #define GFX8_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData2_bits 7 #define GFX75_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData2_bits 7 #define GFX7_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData2_bits 7 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData2_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 7; case 120: return 7; case 110: return 7; case 90: return 7; case 80: return 7; case 75: return 7; case 70: return 7; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData2_start 224 #define GFX12_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData2_start 224 #define GFX11_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData2_start 224 #define GFX9_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData2_start 224 #define GFX8_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData2_start 224 #define GFX75_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData2_start 160 #define GFX7_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData2_start 160 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData2_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 224; case 120: return 224; case 110: return 224; case 90: return 224; case 80: return 224; case 75: return 160; case 70: return 160; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS::Dual Source Blend Enable */ #define GFX75_3DSTATE_PS_DualSourceBlendEnable_bits 1 #define GFX7_3DSTATE_PS_DualSourceBlendEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_DualSourceBlendEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_PS_DualSourceBlendEnable_start 135 #define GFX7_3DSTATE_PS_DualSourceBlendEnable_start 135 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_DualSourceBlendEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 135; case 70: return 135; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS::Floating Point Mode */ #define GFX125_3DSTATE_PS_FloatingPointMode_bits 1 #define GFX12_3DSTATE_PS_FloatingPointMode_bits 1 #define GFX11_3DSTATE_PS_FloatingPointMode_bits 1 #define GFX9_3DSTATE_PS_FloatingPointMode_bits 1 #define GFX8_3DSTATE_PS_FloatingPointMode_bits 1 #define GFX75_3DSTATE_PS_FloatingPointMode_bits 1 #define GFX7_3DSTATE_PS_FloatingPointMode_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_FloatingPointMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PS_FloatingPointMode_start 112 #define GFX12_3DSTATE_PS_FloatingPointMode_start 112 #define GFX11_3DSTATE_PS_FloatingPointMode_start 112 #define GFX9_3DSTATE_PS_FloatingPointMode_start 112 #define GFX8_3DSTATE_PS_FloatingPointMode_start 112 #define GFX75_3DSTATE_PS_FloatingPointMode_start 80 #define GFX7_3DSTATE_PS_FloatingPointMode_start 80 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_FloatingPointMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 112; case 120: return 112; case 110: return 112; case 90: return 112; case 80: return 112; case 75: return 80; case 70: return 80; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS::Illegal Opcode Exception Enable */ #define GFX125_3DSTATE_PS_IllegalOpcodeExceptionEnable_bits 1 #define GFX12_3DSTATE_PS_IllegalOpcodeExceptionEnable_bits 1 #define GFX11_3DSTATE_PS_IllegalOpcodeExceptionEnable_bits 1 #define GFX9_3DSTATE_PS_IllegalOpcodeExceptionEnable_bits 1 #define GFX8_3DSTATE_PS_IllegalOpcodeExceptionEnable_bits 1 #define GFX75_3DSTATE_PS_IllegalOpcodeExceptionEnable_bits 1 #define GFX7_3DSTATE_PS_IllegalOpcodeExceptionEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_IllegalOpcodeExceptionEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PS_IllegalOpcodeExceptionEnable_start 109 #define GFX12_3DSTATE_PS_IllegalOpcodeExceptionEnable_start 109 #define GFX11_3DSTATE_PS_IllegalOpcodeExceptionEnable_start 109 #define GFX9_3DSTATE_PS_IllegalOpcodeExceptionEnable_start 109 #define GFX8_3DSTATE_PS_IllegalOpcodeExceptionEnable_start 109 #define GFX75_3DSTATE_PS_IllegalOpcodeExceptionEnable_start 77 #define GFX7_3DSTATE_PS_IllegalOpcodeExceptionEnable_start 77 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_IllegalOpcodeExceptionEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 109; case 120: return 109; case 110: return 109; case 90: return 109; case 80: return 109; case 75: return 77; case 70: return 77; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS::Kernel Start Pointer 0 */ #define GFX125_3DSTATE_PS_KernelStartPointer0_bits 58 #define GFX12_3DSTATE_PS_KernelStartPointer0_bits 58 #define GFX11_3DSTATE_PS_KernelStartPointer0_bits 58 #define GFX9_3DSTATE_PS_KernelStartPointer0_bits 58 #define GFX8_3DSTATE_PS_KernelStartPointer0_bits 58 #define GFX75_3DSTATE_PS_KernelStartPointer0_bits 26 #define GFX7_3DSTATE_PS_KernelStartPointer0_bits 26 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_KernelStartPointer0_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 58; case 120: return 58; case 110: return 58; case 90: return 58; case 80: return 58; case 75: return 26; case 70: return 26; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PS_KernelStartPointer0_start 38 #define GFX12_3DSTATE_PS_KernelStartPointer0_start 38 #define GFX11_3DSTATE_PS_KernelStartPointer0_start 38 #define GFX9_3DSTATE_PS_KernelStartPointer0_start 38 #define GFX8_3DSTATE_PS_KernelStartPointer0_start 38 #define GFX75_3DSTATE_PS_KernelStartPointer0_start 38 #define GFX7_3DSTATE_PS_KernelStartPointer0_start 38 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_KernelStartPointer0_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 38; case 120: return 38; case 110: return 38; case 90: return 38; case 80: return 38; case 75: return 38; case 70: return 38; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS::Kernel Start Pointer 1 */ #define GFX125_3DSTATE_PS_KernelStartPointer1_bits 58 #define GFX12_3DSTATE_PS_KernelStartPointer1_bits 58 #define GFX11_3DSTATE_PS_KernelStartPointer1_bits 58 #define GFX9_3DSTATE_PS_KernelStartPointer1_bits 58 #define GFX8_3DSTATE_PS_KernelStartPointer1_bits 58 #define GFX75_3DSTATE_PS_KernelStartPointer1_bits 26 #define GFX7_3DSTATE_PS_KernelStartPointer1_bits 26 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_KernelStartPointer1_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 58; case 120: return 58; case 110: return 58; case 90: return 58; case 80: return 58; case 75: return 26; case 70: return 26; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PS_KernelStartPointer1_start 262 #define GFX12_3DSTATE_PS_KernelStartPointer1_start 262 #define GFX11_3DSTATE_PS_KernelStartPointer1_start 262 #define GFX9_3DSTATE_PS_KernelStartPointer1_start 262 #define GFX8_3DSTATE_PS_KernelStartPointer1_start 262 #define GFX75_3DSTATE_PS_KernelStartPointer1_start 198 #define GFX7_3DSTATE_PS_KernelStartPointer1_start 198 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_KernelStartPointer1_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 262; case 120: return 262; case 110: return 262; case 90: return 262; case 80: return 262; case 75: return 198; case 70: return 198; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS::Kernel Start Pointer 2 */ #define GFX125_3DSTATE_PS_KernelStartPointer2_bits 58 #define GFX12_3DSTATE_PS_KernelStartPointer2_bits 58 #define GFX11_3DSTATE_PS_KernelStartPointer2_bits 58 #define GFX9_3DSTATE_PS_KernelStartPointer2_bits 58 #define GFX8_3DSTATE_PS_KernelStartPointer2_bits 58 #define GFX75_3DSTATE_PS_KernelStartPointer2_bits 26 #define GFX7_3DSTATE_PS_KernelStartPointer2_bits 26 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_KernelStartPointer2_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 58; case 120: return 58; case 110: return 58; case 90: return 58; case 80: return 58; case 75: return 26; case 70: return 26; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PS_KernelStartPointer2_start 326 #define GFX12_3DSTATE_PS_KernelStartPointer2_start 326 #define GFX11_3DSTATE_PS_KernelStartPointer2_start 326 #define GFX9_3DSTATE_PS_KernelStartPointer2_start 326 #define GFX8_3DSTATE_PS_KernelStartPointer2_start 326 #define GFX75_3DSTATE_PS_KernelStartPointer2_start 230 #define GFX7_3DSTATE_PS_KernelStartPointer2_start 230 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_KernelStartPointer2_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 326; case 120: return 326; case 110: return 326; case 90: return 326; case 80: return 326; case 75: return 230; case 70: return 230; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS::Mask Stack Exception Enable */ #define GFX125_3DSTATE_PS_MaskStackExceptionEnable_bits 1 #define GFX12_3DSTATE_PS_MaskStackExceptionEnable_bits 1 #define GFX11_3DSTATE_PS_MaskStackExceptionEnable_bits 1 #define GFX9_3DSTATE_PS_MaskStackExceptionEnable_bits 1 #define GFX8_3DSTATE_PS_MaskStackExceptionEnable_bits 1 #define GFX75_3DSTATE_PS_MaskStackExceptionEnable_bits 1 #define GFX7_3DSTATE_PS_MaskStackExceptionEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_MaskStackExceptionEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PS_MaskStackExceptionEnable_start 107 #define GFX12_3DSTATE_PS_MaskStackExceptionEnable_start 107 #define GFX11_3DSTATE_PS_MaskStackExceptionEnable_start 107 #define GFX9_3DSTATE_PS_MaskStackExceptionEnable_start 107 #define GFX8_3DSTATE_PS_MaskStackExceptionEnable_start 107 #define GFX75_3DSTATE_PS_MaskStackExceptionEnable_start 75 #define GFX7_3DSTATE_PS_MaskStackExceptionEnable_start 75 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_MaskStackExceptionEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 107; case 120: return 107; case 110: return 107; case 90: return 107; case 80: return 107; case 75: return 75; case 70: return 75; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS::Maximum Number of Threads */ #define GFX75_3DSTATE_PS_MaximumNumberofThreads_bits 9 #define GFX7_3DSTATE_PS_MaximumNumberofThreads_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_MaximumNumberofThreads_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 9; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_PS_MaximumNumberofThreads_start 151 #define GFX7_3DSTATE_PS_MaximumNumberofThreads_start 152 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_MaximumNumberofThreads_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 151; case 70: return 152; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS::Maximum Number of Threads Per PSD */ #define GFX125_3DSTATE_PS_MaximumNumberofThreadsPerPSD_bits 9 #define GFX12_3DSTATE_PS_MaximumNumberofThreadsPerPSD_bits 9 #define GFX11_3DSTATE_PS_MaximumNumberofThreadsPerPSD_bits 9 #define GFX9_3DSTATE_PS_MaximumNumberofThreadsPerPSD_bits 9 #define GFX8_3DSTATE_PS_MaximumNumberofThreadsPerPSD_bits 9 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_MaximumNumberofThreadsPerPSD_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 9; case 120: return 9; case 110: return 9; case 90: return 9; case 80: return 9; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PS_MaximumNumberofThreadsPerPSD_start 215 #define GFX12_3DSTATE_PS_MaximumNumberofThreadsPerPSD_start 215 #define GFX11_3DSTATE_PS_MaximumNumberofThreadsPerPSD_start 215 #define GFX9_3DSTATE_PS_MaximumNumberofThreadsPerPSD_start 215 #define GFX8_3DSTATE_PS_MaximumNumberofThreadsPerPSD_start 215 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_MaximumNumberofThreadsPerPSD_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 215; case 120: return 215; case 110: return 215; case 90: return 215; case 80: return 215; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS::PS Accesses UAV */ #define GFX75_3DSTATE_PS_PSAccessesUAV_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_PSAccessesUAV_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_PS_PSAccessesUAV_start 133 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_PSAccessesUAV_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 133; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS::Per Thread Scratch Space */ #define GFX12_3DSTATE_PS_PerThreadScratchSpace_bits 4 #define GFX11_3DSTATE_PS_PerThreadScratchSpace_bits 4 #define GFX9_3DSTATE_PS_PerThreadScratchSpace_bits 4 #define GFX8_3DSTATE_PS_PerThreadScratchSpace_bits 4 #define GFX75_3DSTATE_PS_PerThreadScratchSpace_bits 4 #define GFX7_3DSTATE_PS_PerThreadScratchSpace_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_PerThreadScratchSpace_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 4; case 70: return 4; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_3DSTATE_PS_PerThreadScratchSpace_start 128 #define GFX11_3DSTATE_PS_PerThreadScratchSpace_start 128 #define GFX9_3DSTATE_PS_PerThreadScratchSpace_start 128 #define GFX8_3DSTATE_PS_PerThreadScratchSpace_start 128 #define GFX75_3DSTATE_PS_PerThreadScratchSpace_start 96 #define GFX7_3DSTATE_PS_PerThreadScratchSpace_start 96 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_PerThreadScratchSpace_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 128; case 110: return 128; case 90: return 128; case 80: return 128; case 75: return 96; case 70: return 96; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS::Position XY Offset Select */ #define GFX125_3DSTATE_PS_PositionXYOffsetSelect_bits 2 #define GFX12_3DSTATE_PS_PositionXYOffsetSelect_bits 2 #define GFX11_3DSTATE_PS_PositionXYOffsetSelect_bits 2 #define GFX9_3DSTATE_PS_PositionXYOffsetSelect_bits 2 #define GFX8_3DSTATE_PS_PositionXYOffsetSelect_bits 2 #define GFX75_3DSTATE_PS_PositionXYOffsetSelect_bits 2 #define GFX7_3DSTATE_PS_PositionXYOffsetSelect_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_PositionXYOffsetSelect_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PS_PositionXYOffsetSelect_start 195 #define GFX12_3DSTATE_PS_PositionXYOffsetSelect_start 195 #define GFX11_3DSTATE_PS_PositionXYOffsetSelect_start 195 #define GFX9_3DSTATE_PS_PositionXYOffsetSelect_start 195 #define GFX8_3DSTATE_PS_PositionXYOffsetSelect_start 195 #define GFX75_3DSTATE_PS_PositionXYOffsetSelect_start 131 #define GFX7_3DSTATE_PS_PositionXYOffsetSelect_start 131 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_PositionXYOffsetSelect_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 195; case 120: return 195; case 110: return 195; case 90: return 195; case 80: return 195; case 75: return 131; case 70: return 131; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS::Push Constant Enable */ #define GFX125_3DSTATE_PS_PushConstantEnable_bits 1 #define GFX12_3DSTATE_PS_PushConstantEnable_bits 1 #define GFX11_3DSTATE_PS_PushConstantEnable_bits 1 #define GFX9_3DSTATE_PS_PushConstantEnable_bits 1 #define GFX8_3DSTATE_PS_PushConstantEnable_bits 1 #define GFX75_3DSTATE_PS_PushConstantEnable_bits 1 #define GFX7_3DSTATE_PS_PushConstantEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_PushConstantEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PS_PushConstantEnable_start 203 #define GFX12_3DSTATE_PS_PushConstantEnable_start 203 #define GFX11_3DSTATE_PS_PushConstantEnable_start 203 #define GFX9_3DSTATE_PS_PushConstantEnable_start 203 #define GFX8_3DSTATE_PS_PushConstantEnable_start 203 #define GFX75_3DSTATE_PS_PushConstantEnable_start 139 #define GFX7_3DSTATE_PS_PushConstantEnable_start 139 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_PushConstantEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 203; case 120: return 203; case 110: return 203; case 90: return 203; case 80: return 203; case 75: return 139; case 70: return 139; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS::Render Target Fast Clear Enable */ #define GFX125_3DSTATE_PS_RenderTargetFastClearEnable_bits 1 #define GFX12_3DSTATE_PS_RenderTargetFastClearEnable_bits 1 #define GFX11_3DSTATE_PS_RenderTargetFastClearEnable_bits 1 #define GFX9_3DSTATE_PS_RenderTargetFastClearEnable_bits 1 #define GFX8_3DSTATE_PS_RenderTargetFastClearEnable_bits 1 #define GFX75_3DSTATE_PS_RenderTargetFastClearEnable_bits 1 #define GFX7_3DSTATE_PS_RenderTargetFastClearEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_RenderTargetFastClearEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PS_RenderTargetFastClearEnable_start 200 #define GFX12_3DSTATE_PS_RenderTargetFastClearEnable_start 200 #define GFX11_3DSTATE_PS_RenderTargetFastClearEnable_start 200 #define GFX9_3DSTATE_PS_RenderTargetFastClearEnable_start 200 #define GFX8_3DSTATE_PS_RenderTargetFastClearEnable_start 200 #define GFX75_3DSTATE_PS_RenderTargetFastClearEnable_start 136 #define GFX7_3DSTATE_PS_RenderTargetFastClearEnable_start 136 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_RenderTargetFastClearEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 200; case 120: return 200; case 110: return 200; case 90: return 200; case 80: return 200; case 75: return 136; case 70: return 136; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS::Render Target Resolve Enable */ #define GFX8_3DSTATE_PS_RenderTargetResolveEnable_bits 1 #define GFX75_3DSTATE_PS_RenderTargetResolveEnable_bits 1 #define GFX7_3DSTATE_PS_RenderTargetResolveEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_RenderTargetResolveEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX8_3DSTATE_PS_RenderTargetResolveEnable_start 198 #define GFX75_3DSTATE_PS_RenderTargetResolveEnable_start 134 #define GFX7_3DSTATE_PS_RenderTargetResolveEnable_start 134 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_RenderTargetResolveEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 198; case 75: return 134; case 70: return 134; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS::Render Target Resolve Type */ #define GFX125_3DSTATE_PS_RenderTargetResolveType_bits 2 #define GFX12_3DSTATE_PS_RenderTargetResolveType_bits 2 #define GFX11_3DSTATE_PS_RenderTargetResolveType_bits 2 #define GFX9_3DSTATE_PS_RenderTargetResolveType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_RenderTargetResolveType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PS_RenderTargetResolveType_start 198 #define GFX12_3DSTATE_PS_RenderTargetResolveType_start 198 #define GFX11_3DSTATE_PS_RenderTargetResolveType_start 198 #define GFX9_3DSTATE_PS_RenderTargetResolveType_start 198 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_RenderTargetResolveType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 198; case 120: return 198; case 110: return 198; case 90: return 198; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS::Rounding Mode */ #define GFX125_3DSTATE_PS_RoundingMode_bits 2 #define GFX12_3DSTATE_PS_RoundingMode_bits 2 #define GFX11_3DSTATE_PS_RoundingMode_bits 2 #define GFX9_3DSTATE_PS_RoundingMode_bits 2 #define GFX8_3DSTATE_PS_RoundingMode_bits 2 #define GFX75_3DSTATE_PS_RoundingMode_bits 2 #define GFX7_3DSTATE_PS_RoundingMode_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_RoundingMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PS_RoundingMode_start 110 #define GFX12_3DSTATE_PS_RoundingMode_start 110 #define GFX11_3DSTATE_PS_RoundingMode_start 110 #define GFX9_3DSTATE_PS_RoundingMode_start 110 #define GFX8_3DSTATE_PS_RoundingMode_start 110 #define GFX75_3DSTATE_PS_RoundingMode_start 78 #define GFX7_3DSTATE_PS_RoundingMode_start 78 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_RoundingMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 110; case 120: return 110; case 110: return 110; case 90: return 110; case 80: return 110; case 75: return 78; case 70: return 78; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS::Sample Mask */ #define GFX75_3DSTATE_PS_SampleMask_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_SampleMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 8; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_PS_SampleMask_start 140 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_SampleMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 140; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS::Sampler Count */ #define GFX125_3DSTATE_PS_SamplerCount_bits 3 #define GFX12_3DSTATE_PS_SamplerCount_bits 3 #define GFX11_3DSTATE_PS_SamplerCount_bits 3 #define GFX9_3DSTATE_PS_SamplerCount_bits 3 #define GFX8_3DSTATE_PS_SamplerCount_bits 3 #define GFX75_3DSTATE_PS_SamplerCount_bits 3 #define GFX7_3DSTATE_PS_SamplerCount_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_SamplerCount_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PS_SamplerCount_start 123 #define GFX12_3DSTATE_PS_SamplerCount_start 123 #define GFX11_3DSTATE_PS_SamplerCount_start 123 #define GFX9_3DSTATE_PS_SamplerCount_start 123 #define GFX8_3DSTATE_PS_SamplerCount_start 123 #define GFX75_3DSTATE_PS_SamplerCount_start 91 #define GFX7_3DSTATE_PS_SamplerCount_start 91 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_SamplerCount_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 123; case 120: return 123; case 110: return 123; case 90: return 123; case 80: return 123; case 75: return 91; case 70: return 91; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS::Scratch Space Base Pointer */ #define GFX12_3DSTATE_PS_ScratchSpaceBasePointer_bits 54 #define GFX11_3DSTATE_PS_ScratchSpaceBasePointer_bits 54 #define GFX9_3DSTATE_PS_ScratchSpaceBasePointer_bits 54 #define GFX8_3DSTATE_PS_ScratchSpaceBasePointer_bits 54 #define GFX75_3DSTATE_PS_ScratchSpaceBasePointer_bits 22 #define GFX7_3DSTATE_PS_ScratchSpaceBasePointer_bits 22 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_ScratchSpaceBasePointer_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 54; case 110: return 54; case 90: return 54; case 80: return 54; case 75: return 22; case 70: return 22; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_3DSTATE_PS_ScratchSpaceBasePointer_start 138 #define GFX11_3DSTATE_PS_ScratchSpaceBasePointer_start 138 #define GFX9_3DSTATE_PS_ScratchSpaceBasePointer_start 138 #define GFX8_3DSTATE_PS_ScratchSpaceBasePointer_start 138 #define GFX75_3DSTATE_PS_ScratchSpaceBasePointer_start 106 #define GFX7_3DSTATE_PS_ScratchSpaceBasePointer_start 106 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_ScratchSpaceBasePointer_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 138; case 110: return 138; case 90: return 138; case 80: return 138; case 75: return 106; case 70: return 106; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS::Scratch Space Buffer */ #define GFX125_3DSTATE_PS_ScratchSpaceBuffer_bits 22 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_ScratchSpaceBuffer_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 22; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PS_ScratchSpaceBuffer_start 138 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_ScratchSpaceBuffer_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 138; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS::Single Precision Denormal Mode */ #define GFX125_3DSTATE_PS_SinglePrecisionDenormalMode_bits 1 #define GFX12_3DSTATE_PS_SinglePrecisionDenormalMode_bits 1 #define GFX11_3DSTATE_PS_SinglePrecisionDenormalMode_bits 1 #define GFX9_3DSTATE_PS_SinglePrecisionDenormalMode_bits 1 #define GFX8_3DSTATE_PS_SinglePrecisionDenormalMode_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_SinglePrecisionDenormalMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PS_SinglePrecisionDenormalMode_start 122 #define GFX12_3DSTATE_PS_SinglePrecisionDenormalMode_start 122 #define GFX11_3DSTATE_PS_SinglePrecisionDenormalMode_start 122 #define GFX9_3DSTATE_PS_SinglePrecisionDenormalMode_start 122 #define GFX8_3DSTATE_PS_SinglePrecisionDenormalMode_start 122 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_SinglePrecisionDenormalMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 122; case 120: return 122; case 110: return 122; case 90: return 122; case 80: return 122; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS::Single Program Flow */ #define GFX125_3DSTATE_PS_SingleProgramFlow_bits 1 #define GFX12_3DSTATE_PS_SingleProgramFlow_bits 1 #define GFX11_3DSTATE_PS_SingleProgramFlow_bits 1 #define GFX9_3DSTATE_PS_SingleProgramFlow_bits 1 #define GFX8_3DSTATE_PS_SingleProgramFlow_bits 1 #define GFX75_3DSTATE_PS_SingleProgramFlow_bits 1 #define GFX7_3DSTATE_PS_SingleProgramFlow_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_SingleProgramFlow_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PS_SingleProgramFlow_start 127 #define GFX12_3DSTATE_PS_SingleProgramFlow_start 127 #define GFX11_3DSTATE_PS_SingleProgramFlow_start 127 #define GFX9_3DSTATE_PS_SingleProgramFlow_start 127 #define GFX8_3DSTATE_PS_SingleProgramFlow_start 127 #define GFX75_3DSTATE_PS_SingleProgramFlow_start 95 #define GFX7_3DSTATE_PS_SingleProgramFlow_start 95 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_SingleProgramFlow_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 127; case 120: return 127; case 110: return 127; case 90: return 127; case 80: return 127; case 75: return 95; case 70: return 95; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS::Software Exception Enable */ #define GFX125_3DSTATE_PS_SoftwareExceptionEnable_bits 1 #define GFX12_3DSTATE_PS_SoftwareExceptionEnable_bits 1 #define GFX11_3DSTATE_PS_SoftwareExceptionEnable_bits 1 #define GFX9_3DSTATE_PS_SoftwareExceptionEnable_bits 1 #define GFX8_3DSTATE_PS_SoftwareExceptionEnable_bits 1 #define GFX75_3DSTATE_PS_SoftwareExceptionEnable_bits 1 #define GFX7_3DSTATE_PS_SoftwareExceptionEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_SoftwareExceptionEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PS_SoftwareExceptionEnable_start 103 #define GFX12_3DSTATE_PS_SoftwareExceptionEnable_start 103 #define GFX11_3DSTATE_PS_SoftwareExceptionEnable_start 103 #define GFX9_3DSTATE_PS_SoftwareExceptionEnable_start 103 #define GFX8_3DSTATE_PS_SoftwareExceptionEnable_start 103 #define GFX75_3DSTATE_PS_SoftwareExceptionEnable_start 71 #define GFX7_3DSTATE_PS_SoftwareExceptionEnable_start 71 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_SoftwareExceptionEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 103; case 120: return 103; case 110: return 103; case 90: return 103; case 80: return 103; case 75: return 71; case 70: return 71; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS::Thread Dispatch Priority */ #define GFX125_3DSTATE_PS_ThreadDispatchPriority_bits 1 #define GFX12_3DSTATE_PS_ThreadDispatchPriority_bits 1 #define GFX11_3DSTATE_PS_ThreadDispatchPriority_bits 1 #define GFX9_3DSTATE_PS_ThreadDispatchPriority_bits 1 #define GFX8_3DSTATE_PS_ThreadDispatchPriority_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_ThreadDispatchPriority_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PS_ThreadDispatchPriority_start 113 #define GFX12_3DSTATE_PS_ThreadDispatchPriority_start 113 #define GFX11_3DSTATE_PS_ThreadDispatchPriority_start 113 #define GFX9_3DSTATE_PS_ThreadDispatchPriority_start 113 #define GFX8_3DSTATE_PS_ThreadDispatchPriority_start 113 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_ThreadDispatchPriority_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 113; case 120: return 113; case 110: return 113; case 90: return 113; case 80: return 113; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS::Thread Priority */ #define GFX75_3DSTATE_PS_ThreadPriority_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_ThreadPriority_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_PS_ThreadPriority_start 81 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_ThreadPriority_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 81; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS::Vector Mask Enable */ #define GFX125_3DSTATE_PS_VectorMaskEnable_bits 1 #define GFX12_3DSTATE_PS_VectorMaskEnable_bits 1 #define GFX11_3DSTATE_PS_VectorMaskEnable_bits 1 #define GFX9_3DSTATE_PS_VectorMaskEnable_bits 1 #define GFX8_3DSTATE_PS_VectorMaskEnable_bits 1 #define GFX75_3DSTATE_PS_VectorMaskEnable_bits 1 #define GFX7_3DSTATE_PS_VectorMaskEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_VectorMaskEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PS_VectorMaskEnable_start 126 #define GFX12_3DSTATE_PS_VectorMaskEnable_start 126 #define GFX11_3DSTATE_PS_VectorMaskEnable_start 126 #define GFX9_3DSTATE_PS_VectorMaskEnable_start 126 #define GFX8_3DSTATE_PS_VectorMaskEnable_start 126 #define GFX75_3DSTATE_PS_VectorMaskEnable_start 94 #define GFX7_3DSTATE_PS_VectorMaskEnable_start 94 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_VectorMaskEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 126; case 120: return 126; case 110: return 126; case 90: return 126; case 80: return 126; case 75: return 94; case 70: return 94; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS::oMask Present to RenderTarget */ #define GFX75_3DSTATE_PS_oMaskPresenttoRenderTarget_bits 1 #define GFX7_3DSTATE_PS_oMaskPresenttoRenderTarget_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_oMaskPresenttoRenderTarget_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_PS_oMaskPresenttoRenderTarget_start 137 #define GFX7_3DSTATE_PS_oMaskPresenttoRenderTarget_start 137 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_oMaskPresenttoRenderTarget_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 137; case 70: return 137; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS_BLEND */ #define GFX125_3DSTATE_PS_BLEND_length 2 #define GFX12_3DSTATE_PS_BLEND_length 2 #define GFX11_3DSTATE_PS_BLEND_length 2 #define GFX9_3DSTATE_PS_BLEND_length 2 #define GFX8_3DSTATE_PS_BLEND_length 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_BLEND_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS_BLEND::3D Command Opcode */ #define GFX125_3DSTATE_PS_BLEND_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_PS_BLEND_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_PS_BLEND_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_PS_BLEND_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_PS_BLEND_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_BLEND_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PS_BLEND_3DCommandOpcode_start 24 #define GFX12_3DSTATE_PS_BLEND_3DCommandOpcode_start 24 #define GFX11_3DSTATE_PS_BLEND_3DCommandOpcode_start 24 #define GFX9_3DSTATE_PS_BLEND_3DCommandOpcode_start 24 #define GFX8_3DSTATE_PS_BLEND_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_BLEND_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS_BLEND::3D Command Sub Opcode */ #define GFX125_3DSTATE_PS_BLEND_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_PS_BLEND_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_PS_BLEND_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_PS_BLEND_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_PS_BLEND_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_BLEND_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PS_BLEND_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_PS_BLEND_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_PS_BLEND_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_PS_BLEND_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_PS_BLEND_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_BLEND_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS_BLEND::Alpha Test Enable */ #define GFX125_3DSTATE_PS_BLEND_AlphaTestEnable_bits 1 #define GFX12_3DSTATE_PS_BLEND_AlphaTestEnable_bits 1 #define GFX11_3DSTATE_PS_BLEND_AlphaTestEnable_bits 1 #define GFX9_3DSTATE_PS_BLEND_AlphaTestEnable_bits 1 #define GFX8_3DSTATE_PS_BLEND_AlphaTestEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_BLEND_AlphaTestEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PS_BLEND_AlphaTestEnable_start 40 #define GFX12_3DSTATE_PS_BLEND_AlphaTestEnable_start 40 #define GFX11_3DSTATE_PS_BLEND_AlphaTestEnable_start 40 #define GFX9_3DSTATE_PS_BLEND_AlphaTestEnable_start 40 #define GFX8_3DSTATE_PS_BLEND_AlphaTestEnable_start 40 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_BLEND_AlphaTestEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 40; case 120: return 40; case 110: return 40; case 90: return 40; case 80: return 40; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS_BLEND::Alpha To Coverage Enable */ #define GFX125_3DSTATE_PS_BLEND_AlphaToCoverageEnable_bits 1 #define GFX12_3DSTATE_PS_BLEND_AlphaToCoverageEnable_bits 1 #define GFX11_3DSTATE_PS_BLEND_AlphaToCoverageEnable_bits 1 #define GFX9_3DSTATE_PS_BLEND_AlphaToCoverageEnable_bits 1 #define GFX8_3DSTATE_PS_BLEND_AlphaToCoverageEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_BLEND_AlphaToCoverageEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PS_BLEND_AlphaToCoverageEnable_start 63 #define GFX12_3DSTATE_PS_BLEND_AlphaToCoverageEnable_start 63 #define GFX11_3DSTATE_PS_BLEND_AlphaToCoverageEnable_start 63 #define GFX9_3DSTATE_PS_BLEND_AlphaToCoverageEnable_start 63 #define GFX8_3DSTATE_PS_BLEND_AlphaToCoverageEnable_start 63 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_BLEND_AlphaToCoverageEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 63; case 120: return 63; case 110: return 63; case 90: return 63; case 80: return 63; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS_BLEND::Color Buffer Blend Enable */ #define GFX125_3DSTATE_PS_BLEND_ColorBufferBlendEnable_bits 1 #define GFX12_3DSTATE_PS_BLEND_ColorBufferBlendEnable_bits 1 #define GFX11_3DSTATE_PS_BLEND_ColorBufferBlendEnable_bits 1 #define GFX9_3DSTATE_PS_BLEND_ColorBufferBlendEnable_bits 1 #define GFX8_3DSTATE_PS_BLEND_ColorBufferBlendEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_BLEND_ColorBufferBlendEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PS_BLEND_ColorBufferBlendEnable_start 61 #define GFX12_3DSTATE_PS_BLEND_ColorBufferBlendEnable_start 61 #define GFX11_3DSTATE_PS_BLEND_ColorBufferBlendEnable_start 61 #define GFX9_3DSTATE_PS_BLEND_ColorBufferBlendEnable_start 61 #define GFX8_3DSTATE_PS_BLEND_ColorBufferBlendEnable_start 61 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_BLEND_ColorBufferBlendEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 61; case 120: return 61; case 110: return 61; case 90: return 61; case 80: return 61; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS_BLEND::Command SubType */ #define GFX125_3DSTATE_PS_BLEND_CommandSubType_bits 2 #define GFX12_3DSTATE_PS_BLEND_CommandSubType_bits 2 #define GFX11_3DSTATE_PS_BLEND_CommandSubType_bits 2 #define GFX9_3DSTATE_PS_BLEND_CommandSubType_bits 2 #define GFX8_3DSTATE_PS_BLEND_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_BLEND_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PS_BLEND_CommandSubType_start 27 #define GFX12_3DSTATE_PS_BLEND_CommandSubType_start 27 #define GFX11_3DSTATE_PS_BLEND_CommandSubType_start 27 #define GFX9_3DSTATE_PS_BLEND_CommandSubType_start 27 #define GFX8_3DSTATE_PS_BLEND_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_BLEND_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS_BLEND::Command Type */ #define GFX125_3DSTATE_PS_BLEND_CommandType_bits 3 #define GFX12_3DSTATE_PS_BLEND_CommandType_bits 3 #define GFX11_3DSTATE_PS_BLEND_CommandType_bits 3 #define GFX9_3DSTATE_PS_BLEND_CommandType_bits 3 #define GFX8_3DSTATE_PS_BLEND_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_BLEND_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PS_BLEND_CommandType_start 29 #define GFX12_3DSTATE_PS_BLEND_CommandType_start 29 #define GFX11_3DSTATE_PS_BLEND_CommandType_start 29 #define GFX9_3DSTATE_PS_BLEND_CommandType_start 29 #define GFX8_3DSTATE_PS_BLEND_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_BLEND_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS_BLEND::DWord Length */ #define GFX125_3DSTATE_PS_BLEND_DWordLength_bits 8 #define GFX12_3DSTATE_PS_BLEND_DWordLength_bits 8 #define GFX11_3DSTATE_PS_BLEND_DWordLength_bits 8 #define GFX9_3DSTATE_PS_BLEND_DWordLength_bits 8 #define GFX8_3DSTATE_PS_BLEND_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_BLEND_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PS_BLEND_DWordLength_start 0 #define GFX12_3DSTATE_PS_BLEND_DWordLength_start 0 #define GFX11_3DSTATE_PS_BLEND_DWordLength_start 0 #define GFX9_3DSTATE_PS_BLEND_DWordLength_start 0 #define GFX8_3DSTATE_PS_BLEND_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_BLEND_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS_BLEND::Destination Alpha Blend Factor */ #define GFX125_3DSTATE_PS_BLEND_DestinationAlphaBlendFactor_bits 5 #define GFX12_3DSTATE_PS_BLEND_DestinationAlphaBlendFactor_bits 5 #define GFX11_3DSTATE_PS_BLEND_DestinationAlphaBlendFactor_bits 5 #define GFX9_3DSTATE_PS_BLEND_DestinationAlphaBlendFactor_bits 5 #define GFX8_3DSTATE_PS_BLEND_DestinationAlphaBlendFactor_bits 5 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_BLEND_DestinationAlphaBlendFactor_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 5; case 110: return 5; case 90: return 5; case 80: return 5; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PS_BLEND_DestinationAlphaBlendFactor_start 51 #define GFX12_3DSTATE_PS_BLEND_DestinationAlphaBlendFactor_start 51 #define GFX11_3DSTATE_PS_BLEND_DestinationAlphaBlendFactor_start 51 #define GFX9_3DSTATE_PS_BLEND_DestinationAlphaBlendFactor_start 51 #define GFX8_3DSTATE_PS_BLEND_DestinationAlphaBlendFactor_start 51 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_BLEND_DestinationAlphaBlendFactor_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 51; case 120: return 51; case 110: return 51; case 90: return 51; case 80: return 51; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS_BLEND::Destination Blend Factor */ #define GFX125_3DSTATE_PS_BLEND_DestinationBlendFactor_bits 5 #define GFX12_3DSTATE_PS_BLEND_DestinationBlendFactor_bits 5 #define GFX11_3DSTATE_PS_BLEND_DestinationBlendFactor_bits 5 #define GFX9_3DSTATE_PS_BLEND_DestinationBlendFactor_bits 5 #define GFX8_3DSTATE_PS_BLEND_DestinationBlendFactor_bits 5 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_BLEND_DestinationBlendFactor_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 5; case 110: return 5; case 90: return 5; case 80: return 5; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PS_BLEND_DestinationBlendFactor_start 41 #define GFX12_3DSTATE_PS_BLEND_DestinationBlendFactor_start 41 #define GFX11_3DSTATE_PS_BLEND_DestinationBlendFactor_start 41 #define GFX9_3DSTATE_PS_BLEND_DestinationBlendFactor_start 41 #define GFX8_3DSTATE_PS_BLEND_DestinationBlendFactor_start 41 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_BLEND_DestinationBlendFactor_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 41; case 120: return 41; case 110: return 41; case 90: return 41; case 80: return 41; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS_BLEND::Has Writeable RT */ #define GFX125_3DSTATE_PS_BLEND_HasWriteableRT_bits 1 #define GFX12_3DSTATE_PS_BLEND_HasWriteableRT_bits 1 #define GFX11_3DSTATE_PS_BLEND_HasWriteableRT_bits 1 #define GFX9_3DSTATE_PS_BLEND_HasWriteableRT_bits 1 #define GFX8_3DSTATE_PS_BLEND_HasWriteableRT_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_BLEND_HasWriteableRT_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PS_BLEND_HasWriteableRT_start 62 #define GFX12_3DSTATE_PS_BLEND_HasWriteableRT_start 62 #define GFX11_3DSTATE_PS_BLEND_HasWriteableRT_start 62 #define GFX9_3DSTATE_PS_BLEND_HasWriteableRT_start 62 #define GFX8_3DSTATE_PS_BLEND_HasWriteableRT_start 62 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_BLEND_HasWriteableRT_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 62; case 120: return 62; case 110: return 62; case 90: return 62; case 80: return 62; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS_BLEND::Independent Alpha Blend Enable */ #define GFX125_3DSTATE_PS_BLEND_IndependentAlphaBlendEnable_bits 1 #define GFX12_3DSTATE_PS_BLEND_IndependentAlphaBlendEnable_bits 1 #define GFX11_3DSTATE_PS_BLEND_IndependentAlphaBlendEnable_bits 1 #define GFX9_3DSTATE_PS_BLEND_IndependentAlphaBlendEnable_bits 1 #define GFX8_3DSTATE_PS_BLEND_IndependentAlphaBlendEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_BLEND_IndependentAlphaBlendEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PS_BLEND_IndependentAlphaBlendEnable_start 39 #define GFX12_3DSTATE_PS_BLEND_IndependentAlphaBlendEnable_start 39 #define GFX11_3DSTATE_PS_BLEND_IndependentAlphaBlendEnable_start 39 #define GFX9_3DSTATE_PS_BLEND_IndependentAlphaBlendEnable_start 39 #define GFX8_3DSTATE_PS_BLEND_IndependentAlphaBlendEnable_start 39 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_BLEND_IndependentAlphaBlendEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 39; case 120: return 39; case 110: return 39; case 90: return 39; case 80: return 39; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS_BLEND::Source Alpha Blend Factor */ #define GFX125_3DSTATE_PS_BLEND_SourceAlphaBlendFactor_bits 5 #define GFX12_3DSTATE_PS_BLEND_SourceAlphaBlendFactor_bits 5 #define GFX11_3DSTATE_PS_BLEND_SourceAlphaBlendFactor_bits 5 #define GFX9_3DSTATE_PS_BLEND_SourceAlphaBlendFactor_bits 5 #define GFX8_3DSTATE_PS_BLEND_SourceAlphaBlendFactor_bits 5 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_BLEND_SourceAlphaBlendFactor_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 5; case 110: return 5; case 90: return 5; case 80: return 5; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PS_BLEND_SourceAlphaBlendFactor_start 56 #define GFX12_3DSTATE_PS_BLEND_SourceAlphaBlendFactor_start 56 #define GFX11_3DSTATE_PS_BLEND_SourceAlphaBlendFactor_start 56 #define GFX9_3DSTATE_PS_BLEND_SourceAlphaBlendFactor_start 56 #define GFX8_3DSTATE_PS_BLEND_SourceAlphaBlendFactor_start 56 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_BLEND_SourceAlphaBlendFactor_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 56; case 120: return 56; case 110: return 56; case 90: return 56; case 80: return 56; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS_BLEND::Source Blend Factor */ #define GFX125_3DSTATE_PS_BLEND_SourceBlendFactor_bits 5 #define GFX12_3DSTATE_PS_BLEND_SourceBlendFactor_bits 5 #define GFX11_3DSTATE_PS_BLEND_SourceBlendFactor_bits 5 #define GFX9_3DSTATE_PS_BLEND_SourceBlendFactor_bits 5 #define GFX8_3DSTATE_PS_BLEND_SourceBlendFactor_bits 5 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_BLEND_SourceBlendFactor_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 5; case 110: return 5; case 90: return 5; case 80: return 5; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PS_BLEND_SourceBlendFactor_start 46 #define GFX12_3DSTATE_PS_BLEND_SourceBlendFactor_start 46 #define GFX11_3DSTATE_PS_BLEND_SourceBlendFactor_start 46 #define GFX9_3DSTATE_PS_BLEND_SourceBlendFactor_start 46 #define GFX8_3DSTATE_PS_BLEND_SourceBlendFactor_start 46 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_BLEND_SourceBlendFactor_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 46; case 120: return 46; case 110: return 46; case 90: return 46; case 80: return 46; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS_EXTRA */ #define GFX125_3DSTATE_PS_EXTRA_length 2 #define GFX12_3DSTATE_PS_EXTRA_length 2 #define GFX11_3DSTATE_PS_EXTRA_length 2 #define GFX9_3DSTATE_PS_EXTRA_length 2 #define GFX8_3DSTATE_PS_EXTRA_length 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_EXTRA_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS_EXTRA::3D Command Opcode */ #define GFX125_3DSTATE_PS_EXTRA_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_PS_EXTRA_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_PS_EXTRA_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_PS_EXTRA_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_PS_EXTRA_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_EXTRA_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PS_EXTRA_3DCommandOpcode_start 24 #define GFX12_3DSTATE_PS_EXTRA_3DCommandOpcode_start 24 #define GFX11_3DSTATE_PS_EXTRA_3DCommandOpcode_start 24 #define GFX9_3DSTATE_PS_EXTRA_3DCommandOpcode_start 24 #define GFX8_3DSTATE_PS_EXTRA_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_EXTRA_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS_EXTRA::3D Command Sub Opcode */ #define GFX125_3DSTATE_PS_EXTRA_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_PS_EXTRA_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_PS_EXTRA_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_PS_EXTRA_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_PS_EXTRA_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_EXTRA_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PS_EXTRA_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_PS_EXTRA_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_PS_EXTRA_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_PS_EXTRA_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_PS_EXTRA_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_EXTRA_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS_EXTRA::Attribute Enable */ #define GFX125_3DSTATE_PS_EXTRA_AttributeEnable_bits 1 #define GFX12_3DSTATE_PS_EXTRA_AttributeEnable_bits 1 #define GFX11_3DSTATE_PS_EXTRA_AttributeEnable_bits 1 #define GFX9_3DSTATE_PS_EXTRA_AttributeEnable_bits 1 #define GFX8_3DSTATE_PS_EXTRA_AttributeEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_EXTRA_AttributeEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PS_EXTRA_AttributeEnable_start 40 #define GFX12_3DSTATE_PS_EXTRA_AttributeEnable_start 40 #define GFX11_3DSTATE_PS_EXTRA_AttributeEnable_start 40 #define GFX9_3DSTATE_PS_EXTRA_AttributeEnable_start 40 #define GFX8_3DSTATE_PS_EXTRA_AttributeEnable_start 40 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_EXTRA_AttributeEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 40; case 120: return 40; case 110: return 40; case 90: return 40; case 80: return 40; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS_EXTRA::Command SubType */ #define GFX125_3DSTATE_PS_EXTRA_CommandSubType_bits 2 #define GFX12_3DSTATE_PS_EXTRA_CommandSubType_bits 2 #define GFX11_3DSTATE_PS_EXTRA_CommandSubType_bits 2 #define GFX9_3DSTATE_PS_EXTRA_CommandSubType_bits 2 #define GFX8_3DSTATE_PS_EXTRA_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_EXTRA_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PS_EXTRA_CommandSubType_start 27 #define GFX12_3DSTATE_PS_EXTRA_CommandSubType_start 27 #define GFX11_3DSTATE_PS_EXTRA_CommandSubType_start 27 #define GFX9_3DSTATE_PS_EXTRA_CommandSubType_start 27 #define GFX8_3DSTATE_PS_EXTRA_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_EXTRA_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS_EXTRA::Command Type */ #define GFX125_3DSTATE_PS_EXTRA_CommandType_bits 3 #define GFX12_3DSTATE_PS_EXTRA_CommandType_bits 3 #define GFX11_3DSTATE_PS_EXTRA_CommandType_bits 3 #define GFX9_3DSTATE_PS_EXTRA_CommandType_bits 3 #define GFX8_3DSTATE_PS_EXTRA_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_EXTRA_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PS_EXTRA_CommandType_start 29 #define GFX12_3DSTATE_PS_EXTRA_CommandType_start 29 #define GFX11_3DSTATE_PS_EXTRA_CommandType_start 29 #define GFX9_3DSTATE_PS_EXTRA_CommandType_start 29 #define GFX8_3DSTATE_PS_EXTRA_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_EXTRA_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS_EXTRA::DWord Length */ #define GFX125_3DSTATE_PS_EXTRA_DWordLength_bits 8 #define GFX12_3DSTATE_PS_EXTRA_DWordLength_bits 8 #define GFX11_3DSTATE_PS_EXTRA_DWordLength_bits 8 #define GFX9_3DSTATE_PS_EXTRA_DWordLength_bits 8 #define GFX8_3DSTATE_PS_EXTRA_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_EXTRA_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PS_EXTRA_DWordLength_start 0 #define GFX12_3DSTATE_PS_EXTRA_DWordLength_start 0 #define GFX11_3DSTATE_PS_EXTRA_DWordLength_start 0 #define GFX9_3DSTATE_PS_EXTRA_DWordLength_start 0 #define GFX8_3DSTATE_PS_EXTRA_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_EXTRA_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS_EXTRA::Force Computed Depth */ #define GFX125_3DSTATE_PS_EXTRA_ForceComputedDepth_bits 1 #define GFX12_3DSTATE_PS_EXTRA_ForceComputedDepth_bits 1 #define GFX11_3DSTATE_PS_EXTRA_ForceComputedDepth_bits 1 #define GFX9_3DSTATE_PS_EXTRA_ForceComputedDepth_bits 1 #define GFX8_3DSTATE_PS_EXTRA_ForceComputedDepth_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_EXTRA_ForceComputedDepth_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PS_EXTRA_ForceComputedDepth_start 57 #define GFX12_3DSTATE_PS_EXTRA_ForceComputedDepth_start 57 #define GFX11_3DSTATE_PS_EXTRA_ForceComputedDepth_start 57 #define GFX9_3DSTATE_PS_EXTRA_ForceComputedDepth_start 57 #define GFX8_3DSTATE_PS_EXTRA_ForceComputedDepth_start 57 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_EXTRA_ForceComputedDepth_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 57; case 120: return 57; case 110: return 57; case 90: return 57; case 80: return 57; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS_EXTRA::Input Coverage Mask State */ #define GFX125_3DSTATE_PS_EXTRA_InputCoverageMaskState_bits 2 #define GFX12_3DSTATE_PS_EXTRA_InputCoverageMaskState_bits 2 #define GFX11_3DSTATE_PS_EXTRA_InputCoverageMaskState_bits 2 #define GFX9_3DSTATE_PS_EXTRA_InputCoverageMaskState_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_EXTRA_InputCoverageMaskState_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PS_EXTRA_InputCoverageMaskState_start 32 #define GFX12_3DSTATE_PS_EXTRA_InputCoverageMaskState_start 32 #define GFX11_3DSTATE_PS_EXTRA_InputCoverageMaskState_start 32 #define GFX9_3DSTATE_PS_EXTRA_InputCoverageMaskState_start 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_EXTRA_InputCoverageMaskState_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS_EXTRA::Pixel Shader Computed Depth Mode */ #define GFX125_3DSTATE_PS_EXTRA_PixelShaderComputedDepthMode_bits 2 #define GFX12_3DSTATE_PS_EXTRA_PixelShaderComputedDepthMode_bits 2 #define GFX11_3DSTATE_PS_EXTRA_PixelShaderComputedDepthMode_bits 2 #define GFX9_3DSTATE_PS_EXTRA_PixelShaderComputedDepthMode_bits 2 #define GFX8_3DSTATE_PS_EXTRA_PixelShaderComputedDepthMode_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_EXTRA_PixelShaderComputedDepthMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PS_EXTRA_PixelShaderComputedDepthMode_start 58 #define GFX12_3DSTATE_PS_EXTRA_PixelShaderComputedDepthMode_start 58 #define GFX11_3DSTATE_PS_EXTRA_PixelShaderComputedDepthMode_start 58 #define GFX9_3DSTATE_PS_EXTRA_PixelShaderComputedDepthMode_start 58 #define GFX8_3DSTATE_PS_EXTRA_PixelShaderComputedDepthMode_start 58 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_EXTRA_PixelShaderComputedDepthMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 58; case 120: return 58; case 110: return 58; case 90: return 58; case 80: return 58; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS_EXTRA::Pixel Shader Computes Stencil */ #define GFX125_3DSTATE_PS_EXTRA_PixelShaderComputesStencil_bits 1 #define GFX12_3DSTATE_PS_EXTRA_PixelShaderComputesStencil_bits 1 #define GFX11_3DSTATE_PS_EXTRA_PixelShaderComputesStencil_bits 1 #define GFX9_3DSTATE_PS_EXTRA_PixelShaderComputesStencil_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_EXTRA_PixelShaderComputesStencil_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PS_EXTRA_PixelShaderComputesStencil_start 37 #define GFX12_3DSTATE_PS_EXTRA_PixelShaderComputesStencil_start 37 #define GFX11_3DSTATE_PS_EXTRA_PixelShaderComputesStencil_start 37 #define GFX9_3DSTATE_PS_EXTRA_PixelShaderComputesStencil_start 37 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_EXTRA_PixelShaderComputesStencil_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 37; case 120: return 37; case 110: return 37; case 90: return 37; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS_EXTRA::Pixel Shader Disables Alpha To Coverage */ #define GFX125_3DSTATE_PS_EXTRA_PixelShaderDisablesAlphaToCoverage_bits 1 #define GFX12_3DSTATE_PS_EXTRA_PixelShaderDisablesAlphaToCoverage_bits 1 #define GFX11_3DSTATE_PS_EXTRA_PixelShaderDisablesAlphaToCoverage_bits 1 #define GFX9_3DSTATE_PS_EXTRA_PixelShaderDisablesAlphaToCoverage_bits 1 #define GFX8_3DSTATE_PS_EXTRA_PixelShaderDisablesAlphaToCoverage_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_EXTRA_PixelShaderDisablesAlphaToCoverage_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PS_EXTRA_PixelShaderDisablesAlphaToCoverage_start 39 #define GFX12_3DSTATE_PS_EXTRA_PixelShaderDisablesAlphaToCoverage_start 39 #define GFX11_3DSTATE_PS_EXTRA_PixelShaderDisablesAlphaToCoverage_start 39 #define GFX9_3DSTATE_PS_EXTRA_PixelShaderDisablesAlphaToCoverage_start 39 #define GFX8_3DSTATE_PS_EXTRA_PixelShaderDisablesAlphaToCoverage_start 39 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_EXTRA_PixelShaderDisablesAlphaToCoverage_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 39; case 120: return 39; case 110: return 39; case 90: return 39; case 80: return 39; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS_EXTRA::Pixel Shader Does not write to RT */ #define GFX125_3DSTATE_PS_EXTRA_PixelShaderDoesnotwritetoRT_bits 1 #define GFX12_3DSTATE_PS_EXTRA_PixelShaderDoesnotwritetoRT_bits 1 #define GFX11_3DSTATE_PS_EXTRA_PixelShaderDoesnotwritetoRT_bits 1 #define GFX9_3DSTATE_PS_EXTRA_PixelShaderDoesnotwritetoRT_bits 1 #define GFX8_3DSTATE_PS_EXTRA_PixelShaderDoesnotwritetoRT_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_EXTRA_PixelShaderDoesnotwritetoRT_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PS_EXTRA_PixelShaderDoesnotwritetoRT_start 62 #define GFX12_3DSTATE_PS_EXTRA_PixelShaderDoesnotwritetoRT_start 62 #define GFX11_3DSTATE_PS_EXTRA_PixelShaderDoesnotwritetoRT_start 62 #define GFX9_3DSTATE_PS_EXTRA_PixelShaderDoesnotwritetoRT_start 62 #define GFX8_3DSTATE_PS_EXTRA_PixelShaderDoesnotwritetoRT_start 62 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_EXTRA_PixelShaderDoesnotwritetoRT_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 62; case 120: return 62; case 110: return 62; case 90: return 62; case 80: return 62; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS_EXTRA::Pixel Shader Has UAV */ #define GFX125_3DSTATE_PS_EXTRA_PixelShaderHasUAV_bits 1 #define GFX12_3DSTATE_PS_EXTRA_PixelShaderHasUAV_bits 1 #define GFX11_3DSTATE_PS_EXTRA_PixelShaderHasUAV_bits 1 #define GFX9_3DSTATE_PS_EXTRA_PixelShaderHasUAV_bits 1 #define GFX8_3DSTATE_PS_EXTRA_PixelShaderHasUAV_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_EXTRA_PixelShaderHasUAV_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PS_EXTRA_PixelShaderHasUAV_start 34 #define GFX12_3DSTATE_PS_EXTRA_PixelShaderHasUAV_start 34 #define GFX11_3DSTATE_PS_EXTRA_PixelShaderHasUAV_start 34 #define GFX9_3DSTATE_PS_EXTRA_PixelShaderHasUAV_start 34 #define GFX8_3DSTATE_PS_EXTRA_PixelShaderHasUAV_start 34 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_EXTRA_PixelShaderHasUAV_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 34; case 120: return 34; case 110: return 34; case 90: return 34; case 80: return 34; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS_EXTRA::Pixel Shader Is Per Coarse Pixel */ #define GFX125_3DSTATE_PS_EXTRA_PixelShaderIsPerCoarsePixel_bits 1 #define GFX12_3DSTATE_PS_EXTRA_PixelShaderIsPerCoarsePixel_bits 1 #define GFX11_3DSTATE_PS_EXTRA_PixelShaderIsPerCoarsePixel_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_EXTRA_PixelShaderIsPerCoarsePixel_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PS_EXTRA_PixelShaderIsPerCoarsePixel_start 36 #define GFX12_3DSTATE_PS_EXTRA_PixelShaderIsPerCoarsePixel_start 36 #define GFX11_3DSTATE_PS_EXTRA_PixelShaderIsPerCoarsePixel_start 36 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_EXTRA_PixelShaderIsPerCoarsePixel_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 36; case 120: return 36; case 110: return 36; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS_EXTRA::Pixel Shader Is Per Sample */ #define GFX125_3DSTATE_PS_EXTRA_PixelShaderIsPerSample_bits 1 #define GFX12_3DSTATE_PS_EXTRA_PixelShaderIsPerSample_bits 1 #define GFX11_3DSTATE_PS_EXTRA_PixelShaderIsPerSample_bits 1 #define GFX9_3DSTATE_PS_EXTRA_PixelShaderIsPerSample_bits 1 #define GFX8_3DSTATE_PS_EXTRA_PixelShaderIsPerSample_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_EXTRA_PixelShaderIsPerSample_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PS_EXTRA_PixelShaderIsPerSample_start 38 #define GFX12_3DSTATE_PS_EXTRA_PixelShaderIsPerSample_start 38 #define GFX11_3DSTATE_PS_EXTRA_PixelShaderIsPerSample_start 38 #define GFX9_3DSTATE_PS_EXTRA_PixelShaderIsPerSample_start 38 #define GFX8_3DSTATE_PS_EXTRA_PixelShaderIsPerSample_start 38 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_EXTRA_PixelShaderIsPerSample_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 38; case 120: return 38; case 110: return 38; case 90: return 38; case 80: return 38; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS_EXTRA::Pixel Shader Kills Pixel */ #define GFX125_3DSTATE_PS_EXTRA_PixelShaderKillsPixel_bits 1 #define GFX12_3DSTATE_PS_EXTRA_PixelShaderKillsPixel_bits 1 #define GFX11_3DSTATE_PS_EXTRA_PixelShaderKillsPixel_bits 1 #define GFX9_3DSTATE_PS_EXTRA_PixelShaderKillsPixel_bits 1 #define GFX8_3DSTATE_PS_EXTRA_PixelShaderKillsPixel_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_EXTRA_PixelShaderKillsPixel_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PS_EXTRA_PixelShaderKillsPixel_start 60 #define GFX12_3DSTATE_PS_EXTRA_PixelShaderKillsPixel_start 60 #define GFX11_3DSTATE_PS_EXTRA_PixelShaderKillsPixel_start 60 #define GFX9_3DSTATE_PS_EXTRA_PixelShaderKillsPixel_start 60 #define GFX8_3DSTATE_PS_EXTRA_PixelShaderKillsPixel_start 60 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_EXTRA_PixelShaderKillsPixel_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 60; case 120: return 60; case 110: return 60; case 90: return 60; case 80: return 60; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS_EXTRA::Pixel Shader Pulls Bary */ #define GFX125_3DSTATE_PS_EXTRA_PixelShaderPullsBary_bits 1 #define GFX12_3DSTATE_PS_EXTRA_PixelShaderPullsBary_bits 1 #define GFX11_3DSTATE_PS_EXTRA_PixelShaderPullsBary_bits 1 #define GFX9_3DSTATE_PS_EXTRA_PixelShaderPullsBary_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_EXTRA_PixelShaderPullsBary_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PS_EXTRA_PixelShaderPullsBary_start 35 #define GFX12_3DSTATE_PS_EXTRA_PixelShaderPullsBary_start 35 #define GFX11_3DSTATE_PS_EXTRA_PixelShaderPullsBary_start 35 #define GFX9_3DSTATE_PS_EXTRA_PixelShaderPullsBary_start 35 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_EXTRA_PixelShaderPullsBary_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 35; case 120: return 35; case 110: return 35; case 90: return 35; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS_EXTRA::Pixel Shader Requires Non-Perspective Bary Plane Coefficients */ #define GFX125_3DSTATE_PS_EXTRA_PixelShaderRequiresNonPerspectiveBaryPlaneCoefficients_bits 1 #define GFX12_3DSTATE_PS_EXTRA_PixelShaderRequiresNonPerspectiveBaryPlaneCoefficients_bits 1 #define GFX11_3DSTATE_PS_EXTRA_PixelShaderRequiresNonPerspectiveBaryPlaneCoefficients_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_EXTRA_PixelShaderRequiresNonPerspectiveBaryPlaneCoefficients_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PS_EXTRA_PixelShaderRequiresNonPerspectiveBaryPlaneCoefficients_start 51 #define GFX12_3DSTATE_PS_EXTRA_PixelShaderRequiresNonPerspectiveBaryPlaneCoefficients_start 51 #define GFX11_3DSTATE_PS_EXTRA_PixelShaderRequiresNonPerspectiveBaryPlaneCoefficients_start 51 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_EXTRA_PixelShaderRequiresNonPerspectiveBaryPlaneCoefficients_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 51; case 120: return 51; case 110: return 51; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS_EXTRA::Pixel Shader Requires Perspective Bary Plane Coefficients */ #define GFX125_3DSTATE_PS_EXTRA_PixelShaderRequiresPerspectiveBaryPlaneCoefficients_bits 1 #define GFX12_3DSTATE_PS_EXTRA_PixelShaderRequiresPerspectiveBaryPlaneCoefficients_bits 1 #define GFX11_3DSTATE_PS_EXTRA_PixelShaderRequiresPerspectiveBaryPlaneCoefficients_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_EXTRA_PixelShaderRequiresPerspectiveBaryPlaneCoefficients_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PS_EXTRA_PixelShaderRequiresPerspectiveBaryPlaneCoefficients_start 52 #define GFX12_3DSTATE_PS_EXTRA_PixelShaderRequiresPerspectiveBaryPlaneCoefficients_start 52 #define GFX11_3DSTATE_PS_EXTRA_PixelShaderRequiresPerspectiveBaryPlaneCoefficients_start 52 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_EXTRA_PixelShaderRequiresPerspectiveBaryPlaneCoefficients_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 52; case 120: return 52; case 110: return 52; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS_EXTRA::Pixel Shader Requires Requested Coarse Pixel Shading Size */ #define GFX125_3DSTATE_PS_EXTRA_PixelShaderRequiresRequestedCoarsePixelShadingSize_bits 1 #define GFX12_3DSTATE_PS_EXTRA_PixelShaderRequiresRequestedCoarsePixelShadingSize_bits 1 #define GFX11_3DSTATE_PS_EXTRA_PixelShaderRequiresRequestedCoarsePixelShadingSize_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_EXTRA_PixelShaderRequiresRequestedCoarsePixelShadingSize_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PS_EXTRA_PixelShaderRequiresRequestedCoarsePixelShadingSize_start 54 #define GFX12_3DSTATE_PS_EXTRA_PixelShaderRequiresRequestedCoarsePixelShadingSize_start 54 #define GFX11_3DSTATE_PS_EXTRA_PixelShaderRequiresRequestedCoarsePixelShadingSize_start 54 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_EXTRA_PixelShaderRequiresRequestedCoarsePixelShadingSize_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 54; case 120: return 54; case 110: return 54; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS_EXTRA::Pixel Shader Requires Source Depth and/or W Plane Coefficients */ #define GFX125_3DSTATE_PS_EXTRA_PixelShaderRequiresSourceDepthandorWPlaneCoefficients_bits 1 #define GFX12_3DSTATE_PS_EXTRA_PixelShaderRequiresSourceDepthandorWPlaneCoefficients_bits 1 #define GFX11_3DSTATE_PS_EXTRA_PixelShaderRequiresSourceDepthandorWPlaneCoefficients_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_EXTRA_PixelShaderRequiresSourceDepthandorWPlaneCoefficients_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PS_EXTRA_PixelShaderRequiresSourceDepthandorWPlaneCoefficients_start 53 #define GFX12_3DSTATE_PS_EXTRA_PixelShaderRequiresSourceDepthandorWPlaneCoefficients_start 53 #define GFX11_3DSTATE_PS_EXTRA_PixelShaderRequiresSourceDepthandorWPlaneCoefficients_start 53 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_EXTRA_PixelShaderRequiresSourceDepthandorWPlaneCoefficients_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 53; case 120: return 53; case 110: return 53; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS_EXTRA::Pixel Shader Requires Subpixel Sample Offsets */ #define GFX125_3DSTATE_PS_EXTRA_PixelShaderRequiresSubpixelSampleOffsets_bits 1 #define GFX12_3DSTATE_PS_EXTRA_PixelShaderRequiresSubpixelSampleOffsets_bits 1 #define GFX11_3DSTATE_PS_EXTRA_PixelShaderRequiresSubpixelSampleOffsets_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_EXTRA_PixelShaderRequiresSubpixelSampleOffsets_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PS_EXTRA_PixelShaderRequiresSubpixelSampleOffsets_start 50 #define GFX12_3DSTATE_PS_EXTRA_PixelShaderRequiresSubpixelSampleOffsets_start 50 #define GFX11_3DSTATE_PS_EXTRA_PixelShaderRequiresSubpixelSampleOffsets_start 50 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_EXTRA_PixelShaderRequiresSubpixelSampleOffsets_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 50; case 120: return 50; case 110: return 50; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS_EXTRA::Pixel Shader Uses Input Coverage Mask */ #define GFX8_3DSTATE_PS_EXTRA_PixelShaderUsesInputCoverageMask_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_EXTRA_PixelShaderUsesInputCoverageMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX8_3DSTATE_PS_EXTRA_PixelShaderUsesInputCoverageMask_start 33 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_EXTRA_PixelShaderUsesInputCoverageMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 33; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS_EXTRA::Pixel Shader Uses Source Depth */ #define GFX125_3DSTATE_PS_EXTRA_PixelShaderUsesSourceDepth_bits 1 #define GFX12_3DSTATE_PS_EXTRA_PixelShaderUsesSourceDepth_bits 1 #define GFX11_3DSTATE_PS_EXTRA_PixelShaderUsesSourceDepth_bits 1 #define GFX9_3DSTATE_PS_EXTRA_PixelShaderUsesSourceDepth_bits 1 #define GFX8_3DSTATE_PS_EXTRA_PixelShaderUsesSourceDepth_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_EXTRA_PixelShaderUsesSourceDepth_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PS_EXTRA_PixelShaderUsesSourceDepth_start 56 #define GFX12_3DSTATE_PS_EXTRA_PixelShaderUsesSourceDepth_start 56 #define GFX11_3DSTATE_PS_EXTRA_PixelShaderUsesSourceDepth_start 56 #define GFX9_3DSTATE_PS_EXTRA_PixelShaderUsesSourceDepth_start 56 #define GFX8_3DSTATE_PS_EXTRA_PixelShaderUsesSourceDepth_start 56 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_EXTRA_PixelShaderUsesSourceDepth_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 56; case 120: return 56; case 110: return 56; case 90: return 56; case 80: return 56; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS_EXTRA::Pixel Shader Uses Source W */ #define GFX125_3DSTATE_PS_EXTRA_PixelShaderUsesSourceW_bits 1 #define GFX12_3DSTATE_PS_EXTRA_PixelShaderUsesSourceW_bits 1 #define GFX11_3DSTATE_PS_EXTRA_PixelShaderUsesSourceW_bits 1 #define GFX9_3DSTATE_PS_EXTRA_PixelShaderUsesSourceW_bits 1 #define GFX8_3DSTATE_PS_EXTRA_PixelShaderUsesSourceW_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_EXTRA_PixelShaderUsesSourceW_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PS_EXTRA_PixelShaderUsesSourceW_start 55 #define GFX12_3DSTATE_PS_EXTRA_PixelShaderUsesSourceW_start 55 #define GFX11_3DSTATE_PS_EXTRA_PixelShaderUsesSourceW_start 55 #define GFX9_3DSTATE_PS_EXTRA_PixelShaderUsesSourceW_start 55 #define GFX8_3DSTATE_PS_EXTRA_PixelShaderUsesSourceW_start 55 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_EXTRA_PixelShaderUsesSourceW_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 55; case 120: return 55; case 110: return 55; case 90: return 55; case 80: return 55; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS_EXTRA::Pixel Shader Valid */ #define GFX125_3DSTATE_PS_EXTRA_PixelShaderValid_bits 1 #define GFX12_3DSTATE_PS_EXTRA_PixelShaderValid_bits 1 #define GFX11_3DSTATE_PS_EXTRA_PixelShaderValid_bits 1 #define GFX9_3DSTATE_PS_EXTRA_PixelShaderValid_bits 1 #define GFX8_3DSTATE_PS_EXTRA_PixelShaderValid_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_EXTRA_PixelShaderValid_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PS_EXTRA_PixelShaderValid_start 63 #define GFX12_3DSTATE_PS_EXTRA_PixelShaderValid_start 63 #define GFX11_3DSTATE_PS_EXTRA_PixelShaderValid_start 63 #define GFX9_3DSTATE_PS_EXTRA_PixelShaderValid_start 63 #define GFX8_3DSTATE_PS_EXTRA_PixelShaderValid_start 63 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_EXTRA_PixelShaderValid_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 63; case 120: return 63; case 110: return 63; case 90: return 63; case 80: return 63; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS_EXTRA::Simple PS Hint */ #define GFX125_3DSTATE_PS_EXTRA_SimplePSHint_bits 1 #define GFX12_3DSTATE_PS_EXTRA_SimplePSHint_bits 1 #define GFX11_3DSTATE_PS_EXTRA_SimplePSHint_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_EXTRA_SimplePSHint_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PS_EXTRA_SimplePSHint_start 41 #define GFX12_3DSTATE_PS_EXTRA_SimplePSHint_start 41 #define GFX11_3DSTATE_PS_EXTRA_SimplePSHint_start 41 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_EXTRA_SimplePSHint_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 41; case 120: return 41; case 110: return 41; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PS_EXTRA::oMask Present to Render Target */ #define GFX125_3DSTATE_PS_EXTRA_oMaskPresenttoRenderTarget_bits 1 #define GFX12_3DSTATE_PS_EXTRA_oMaskPresenttoRenderTarget_bits 1 #define GFX11_3DSTATE_PS_EXTRA_oMaskPresenttoRenderTarget_bits 1 #define GFX9_3DSTATE_PS_EXTRA_oMaskPresenttoRenderTarget_bits 1 #define GFX8_3DSTATE_PS_EXTRA_oMaskPresenttoRenderTarget_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_EXTRA_oMaskPresenttoRenderTarget_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PS_EXTRA_oMaskPresenttoRenderTarget_start 61 #define GFX12_3DSTATE_PS_EXTRA_oMaskPresenttoRenderTarget_start 61 #define GFX11_3DSTATE_PS_EXTRA_oMaskPresenttoRenderTarget_start 61 #define GFX9_3DSTATE_PS_EXTRA_oMaskPresenttoRenderTarget_start 61 #define GFX8_3DSTATE_PS_EXTRA_oMaskPresenttoRenderTarget_start 61 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PS_EXTRA_oMaskPresenttoRenderTarget_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 61; case 120: return 61; case 110: return 61; case 90: return 61; case 80: return 61; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PUSH_CONSTANT_ALLOC_DS */ #define GFX125_3DSTATE_PUSH_CONSTANT_ALLOC_DS_length 2 #define GFX12_3DSTATE_PUSH_CONSTANT_ALLOC_DS_length 2 #define GFX11_3DSTATE_PUSH_CONSTANT_ALLOC_DS_length 2 #define GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_DS_length 2 #define GFX8_3DSTATE_PUSH_CONSTANT_ALLOC_DS_length 2 #define GFX75_3DSTATE_PUSH_CONSTANT_ALLOC_DS_length 2 #define GFX7_3DSTATE_PUSH_CONSTANT_ALLOC_DS_length 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PUSH_CONSTANT_ALLOC_DS_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PUSH_CONSTANT_ALLOC_DS::3D Command Opcode */ #define GFX125_3DSTATE_PUSH_CONSTANT_ALLOC_DS_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_PUSH_CONSTANT_ALLOC_DS_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_PUSH_CONSTANT_ALLOC_DS_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_DS_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_PUSH_CONSTANT_ALLOC_DS_3DCommandOpcode_bits 3 #define GFX75_3DSTATE_PUSH_CONSTANT_ALLOC_DS_3DCommandOpcode_bits 3 #define GFX7_3DSTATE_PUSH_CONSTANT_ALLOC_DS_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PUSH_CONSTANT_ALLOC_DS_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PUSH_CONSTANT_ALLOC_DS_3DCommandOpcode_start 24 #define GFX12_3DSTATE_PUSH_CONSTANT_ALLOC_DS_3DCommandOpcode_start 24 #define GFX11_3DSTATE_PUSH_CONSTANT_ALLOC_DS_3DCommandOpcode_start 24 #define GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_DS_3DCommandOpcode_start 24 #define GFX8_3DSTATE_PUSH_CONSTANT_ALLOC_DS_3DCommandOpcode_start 24 #define GFX75_3DSTATE_PUSH_CONSTANT_ALLOC_DS_3DCommandOpcode_start 24 #define GFX7_3DSTATE_PUSH_CONSTANT_ALLOC_DS_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PUSH_CONSTANT_ALLOC_DS_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PUSH_CONSTANT_ALLOC_DS::3D Command Sub Opcode */ #define GFX125_3DSTATE_PUSH_CONSTANT_ALLOC_DS_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_PUSH_CONSTANT_ALLOC_DS_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_PUSH_CONSTANT_ALLOC_DS_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_DS_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_PUSH_CONSTANT_ALLOC_DS_3DCommandSubOpcode_bits 8 #define GFX75_3DSTATE_PUSH_CONSTANT_ALLOC_DS_3DCommandSubOpcode_bits 8 #define GFX7_3DSTATE_PUSH_CONSTANT_ALLOC_DS_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PUSH_CONSTANT_ALLOC_DS_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PUSH_CONSTANT_ALLOC_DS_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_PUSH_CONSTANT_ALLOC_DS_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_PUSH_CONSTANT_ALLOC_DS_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_DS_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_PUSH_CONSTANT_ALLOC_DS_3DCommandSubOpcode_start 16 #define GFX75_3DSTATE_PUSH_CONSTANT_ALLOC_DS_3DCommandSubOpcode_start 16 #define GFX7_3DSTATE_PUSH_CONSTANT_ALLOC_DS_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PUSH_CONSTANT_ALLOC_DS_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PUSH_CONSTANT_ALLOC_DS::Command SubType */ #define GFX125_3DSTATE_PUSH_CONSTANT_ALLOC_DS_CommandSubType_bits 2 #define GFX12_3DSTATE_PUSH_CONSTANT_ALLOC_DS_CommandSubType_bits 2 #define GFX11_3DSTATE_PUSH_CONSTANT_ALLOC_DS_CommandSubType_bits 2 #define GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_DS_CommandSubType_bits 2 #define GFX8_3DSTATE_PUSH_CONSTANT_ALLOC_DS_CommandSubType_bits 2 #define GFX75_3DSTATE_PUSH_CONSTANT_ALLOC_DS_CommandSubType_bits 2 #define GFX7_3DSTATE_PUSH_CONSTANT_ALLOC_DS_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PUSH_CONSTANT_ALLOC_DS_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PUSH_CONSTANT_ALLOC_DS_CommandSubType_start 27 #define GFX12_3DSTATE_PUSH_CONSTANT_ALLOC_DS_CommandSubType_start 27 #define GFX11_3DSTATE_PUSH_CONSTANT_ALLOC_DS_CommandSubType_start 27 #define GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_DS_CommandSubType_start 27 #define GFX8_3DSTATE_PUSH_CONSTANT_ALLOC_DS_CommandSubType_start 27 #define GFX75_3DSTATE_PUSH_CONSTANT_ALLOC_DS_CommandSubType_start 27 #define GFX7_3DSTATE_PUSH_CONSTANT_ALLOC_DS_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PUSH_CONSTANT_ALLOC_DS_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PUSH_CONSTANT_ALLOC_DS::Command Type */ #define GFX125_3DSTATE_PUSH_CONSTANT_ALLOC_DS_CommandType_bits 3 #define GFX12_3DSTATE_PUSH_CONSTANT_ALLOC_DS_CommandType_bits 3 #define GFX11_3DSTATE_PUSH_CONSTANT_ALLOC_DS_CommandType_bits 3 #define GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_DS_CommandType_bits 3 #define GFX8_3DSTATE_PUSH_CONSTANT_ALLOC_DS_CommandType_bits 3 #define GFX75_3DSTATE_PUSH_CONSTANT_ALLOC_DS_CommandType_bits 3 #define GFX7_3DSTATE_PUSH_CONSTANT_ALLOC_DS_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PUSH_CONSTANT_ALLOC_DS_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PUSH_CONSTANT_ALLOC_DS_CommandType_start 29 #define GFX12_3DSTATE_PUSH_CONSTANT_ALLOC_DS_CommandType_start 29 #define GFX11_3DSTATE_PUSH_CONSTANT_ALLOC_DS_CommandType_start 29 #define GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_DS_CommandType_start 29 #define GFX8_3DSTATE_PUSH_CONSTANT_ALLOC_DS_CommandType_start 29 #define GFX75_3DSTATE_PUSH_CONSTANT_ALLOC_DS_CommandType_start 29 #define GFX7_3DSTATE_PUSH_CONSTANT_ALLOC_DS_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PUSH_CONSTANT_ALLOC_DS_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PUSH_CONSTANT_ALLOC_DS::Constant Buffer Offset */ #define GFX125_3DSTATE_PUSH_CONSTANT_ALLOC_DS_ConstantBufferOffset_bits 5 #define GFX12_3DSTATE_PUSH_CONSTANT_ALLOC_DS_ConstantBufferOffset_bits 5 #define GFX11_3DSTATE_PUSH_CONSTANT_ALLOC_DS_ConstantBufferOffset_bits 5 #define GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_DS_ConstantBufferOffset_bits 5 #define GFX8_3DSTATE_PUSH_CONSTANT_ALLOC_DS_ConstantBufferOffset_bits 5 #define GFX75_3DSTATE_PUSH_CONSTANT_ALLOC_DS_ConstantBufferOffset_bits 5 #define GFX7_3DSTATE_PUSH_CONSTANT_ALLOC_DS_ConstantBufferOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PUSH_CONSTANT_ALLOC_DS_ConstantBufferOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 5; case 110: return 5; case 90: return 5; case 80: return 5; case 75: return 5; case 70: return 4; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PUSH_CONSTANT_ALLOC_DS_ConstantBufferOffset_start 48 #define GFX12_3DSTATE_PUSH_CONSTANT_ALLOC_DS_ConstantBufferOffset_start 48 #define GFX11_3DSTATE_PUSH_CONSTANT_ALLOC_DS_ConstantBufferOffset_start 48 #define GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_DS_ConstantBufferOffset_start 48 #define GFX8_3DSTATE_PUSH_CONSTANT_ALLOC_DS_ConstantBufferOffset_start 48 #define GFX75_3DSTATE_PUSH_CONSTANT_ALLOC_DS_ConstantBufferOffset_start 48 #define GFX7_3DSTATE_PUSH_CONSTANT_ALLOC_DS_ConstantBufferOffset_start 48 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PUSH_CONSTANT_ALLOC_DS_ConstantBufferOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 48; case 120: return 48; case 110: return 48; case 90: return 48; case 80: return 48; case 75: return 48; case 70: return 48; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PUSH_CONSTANT_ALLOC_DS::Constant Buffer Size */ #define GFX125_3DSTATE_PUSH_CONSTANT_ALLOC_DS_ConstantBufferSize_bits 6 #define GFX12_3DSTATE_PUSH_CONSTANT_ALLOC_DS_ConstantBufferSize_bits 6 #define GFX11_3DSTATE_PUSH_CONSTANT_ALLOC_DS_ConstantBufferSize_bits 6 #define GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_DS_ConstantBufferSize_bits 6 #define GFX8_3DSTATE_PUSH_CONSTANT_ALLOC_DS_ConstantBufferSize_bits 6 #define GFX75_3DSTATE_PUSH_CONSTANT_ALLOC_DS_ConstantBufferSize_bits 6 #define GFX7_3DSTATE_PUSH_CONSTANT_ALLOC_DS_ConstantBufferSize_bits 5 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PUSH_CONSTANT_ALLOC_DS_ConstantBufferSize_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 5; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PUSH_CONSTANT_ALLOC_DS_ConstantBufferSize_start 32 #define GFX12_3DSTATE_PUSH_CONSTANT_ALLOC_DS_ConstantBufferSize_start 32 #define GFX11_3DSTATE_PUSH_CONSTANT_ALLOC_DS_ConstantBufferSize_start 32 #define GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_DS_ConstantBufferSize_start 32 #define GFX8_3DSTATE_PUSH_CONSTANT_ALLOC_DS_ConstantBufferSize_start 32 #define GFX75_3DSTATE_PUSH_CONSTANT_ALLOC_DS_ConstantBufferSize_start 32 #define GFX7_3DSTATE_PUSH_CONSTANT_ALLOC_DS_ConstantBufferSize_start 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PUSH_CONSTANT_ALLOC_DS_ConstantBufferSize_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PUSH_CONSTANT_ALLOC_DS::DWord Length */ #define GFX125_3DSTATE_PUSH_CONSTANT_ALLOC_DS_DWordLength_bits 8 #define GFX12_3DSTATE_PUSH_CONSTANT_ALLOC_DS_DWordLength_bits 8 #define GFX11_3DSTATE_PUSH_CONSTANT_ALLOC_DS_DWordLength_bits 8 #define GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_DS_DWordLength_bits 8 #define GFX8_3DSTATE_PUSH_CONSTANT_ALLOC_DS_DWordLength_bits 8 #define GFX75_3DSTATE_PUSH_CONSTANT_ALLOC_DS_DWordLength_bits 8 #define GFX7_3DSTATE_PUSH_CONSTANT_ALLOC_DS_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PUSH_CONSTANT_ALLOC_DS_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PUSH_CONSTANT_ALLOC_DS_DWordLength_start 0 #define GFX12_3DSTATE_PUSH_CONSTANT_ALLOC_DS_DWordLength_start 0 #define GFX11_3DSTATE_PUSH_CONSTANT_ALLOC_DS_DWordLength_start 0 #define GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_DS_DWordLength_start 0 #define GFX8_3DSTATE_PUSH_CONSTANT_ALLOC_DS_DWordLength_start 0 #define GFX75_3DSTATE_PUSH_CONSTANT_ALLOC_DS_DWordLength_start 0 #define GFX7_3DSTATE_PUSH_CONSTANT_ALLOC_DS_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PUSH_CONSTANT_ALLOC_DS_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PUSH_CONSTANT_ALLOC_GS */ #define GFX125_3DSTATE_PUSH_CONSTANT_ALLOC_GS_length 2 #define GFX12_3DSTATE_PUSH_CONSTANT_ALLOC_GS_length 2 #define GFX11_3DSTATE_PUSH_CONSTANT_ALLOC_GS_length 2 #define GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_GS_length 2 #define GFX8_3DSTATE_PUSH_CONSTANT_ALLOC_GS_length 2 #define GFX75_3DSTATE_PUSH_CONSTANT_ALLOC_GS_length 2 #define GFX7_3DSTATE_PUSH_CONSTANT_ALLOC_GS_length 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PUSH_CONSTANT_ALLOC_GS_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PUSH_CONSTANT_ALLOC_GS::3D Command Opcode */ #define GFX125_3DSTATE_PUSH_CONSTANT_ALLOC_GS_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_PUSH_CONSTANT_ALLOC_GS_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_PUSH_CONSTANT_ALLOC_GS_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_GS_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_PUSH_CONSTANT_ALLOC_GS_3DCommandOpcode_bits 3 #define GFX75_3DSTATE_PUSH_CONSTANT_ALLOC_GS_3DCommandOpcode_bits 3 #define GFX7_3DSTATE_PUSH_CONSTANT_ALLOC_GS_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PUSH_CONSTANT_ALLOC_GS_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PUSH_CONSTANT_ALLOC_GS_3DCommandOpcode_start 24 #define GFX12_3DSTATE_PUSH_CONSTANT_ALLOC_GS_3DCommandOpcode_start 24 #define GFX11_3DSTATE_PUSH_CONSTANT_ALLOC_GS_3DCommandOpcode_start 24 #define GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_GS_3DCommandOpcode_start 24 #define GFX8_3DSTATE_PUSH_CONSTANT_ALLOC_GS_3DCommandOpcode_start 24 #define GFX75_3DSTATE_PUSH_CONSTANT_ALLOC_GS_3DCommandOpcode_start 24 #define GFX7_3DSTATE_PUSH_CONSTANT_ALLOC_GS_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PUSH_CONSTANT_ALLOC_GS_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PUSH_CONSTANT_ALLOC_GS::3D Command Sub Opcode */ #define GFX125_3DSTATE_PUSH_CONSTANT_ALLOC_GS_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_PUSH_CONSTANT_ALLOC_GS_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_PUSH_CONSTANT_ALLOC_GS_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_GS_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_PUSH_CONSTANT_ALLOC_GS_3DCommandSubOpcode_bits 8 #define GFX75_3DSTATE_PUSH_CONSTANT_ALLOC_GS_3DCommandSubOpcode_bits 8 #define GFX7_3DSTATE_PUSH_CONSTANT_ALLOC_GS_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PUSH_CONSTANT_ALLOC_GS_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PUSH_CONSTANT_ALLOC_GS_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_PUSH_CONSTANT_ALLOC_GS_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_PUSH_CONSTANT_ALLOC_GS_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_GS_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_PUSH_CONSTANT_ALLOC_GS_3DCommandSubOpcode_start 16 #define GFX75_3DSTATE_PUSH_CONSTANT_ALLOC_GS_3DCommandSubOpcode_start 16 #define GFX7_3DSTATE_PUSH_CONSTANT_ALLOC_GS_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PUSH_CONSTANT_ALLOC_GS_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PUSH_CONSTANT_ALLOC_GS::Command SubType */ #define GFX125_3DSTATE_PUSH_CONSTANT_ALLOC_GS_CommandSubType_bits 2 #define GFX12_3DSTATE_PUSH_CONSTANT_ALLOC_GS_CommandSubType_bits 2 #define GFX11_3DSTATE_PUSH_CONSTANT_ALLOC_GS_CommandSubType_bits 2 #define GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_GS_CommandSubType_bits 2 #define GFX8_3DSTATE_PUSH_CONSTANT_ALLOC_GS_CommandSubType_bits 2 #define GFX75_3DSTATE_PUSH_CONSTANT_ALLOC_GS_CommandSubType_bits 2 #define GFX7_3DSTATE_PUSH_CONSTANT_ALLOC_GS_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PUSH_CONSTANT_ALLOC_GS_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PUSH_CONSTANT_ALLOC_GS_CommandSubType_start 27 #define GFX12_3DSTATE_PUSH_CONSTANT_ALLOC_GS_CommandSubType_start 27 #define GFX11_3DSTATE_PUSH_CONSTANT_ALLOC_GS_CommandSubType_start 27 #define GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_GS_CommandSubType_start 27 #define GFX8_3DSTATE_PUSH_CONSTANT_ALLOC_GS_CommandSubType_start 27 #define GFX75_3DSTATE_PUSH_CONSTANT_ALLOC_GS_CommandSubType_start 27 #define GFX7_3DSTATE_PUSH_CONSTANT_ALLOC_GS_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PUSH_CONSTANT_ALLOC_GS_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PUSH_CONSTANT_ALLOC_GS::Command Type */ #define GFX125_3DSTATE_PUSH_CONSTANT_ALLOC_GS_CommandType_bits 3 #define GFX12_3DSTATE_PUSH_CONSTANT_ALLOC_GS_CommandType_bits 3 #define GFX11_3DSTATE_PUSH_CONSTANT_ALLOC_GS_CommandType_bits 3 #define GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_GS_CommandType_bits 3 #define GFX8_3DSTATE_PUSH_CONSTANT_ALLOC_GS_CommandType_bits 3 #define GFX75_3DSTATE_PUSH_CONSTANT_ALLOC_GS_CommandType_bits 3 #define GFX7_3DSTATE_PUSH_CONSTANT_ALLOC_GS_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PUSH_CONSTANT_ALLOC_GS_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PUSH_CONSTANT_ALLOC_GS_CommandType_start 29 #define GFX12_3DSTATE_PUSH_CONSTANT_ALLOC_GS_CommandType_start 29 #define GFX11_3DSTATE_PUSH_CONSTANT_ALLOC_GS_CommandType_start 29 #define GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_GS_CommandType_start 29 #define GFX8_3DSTATE_PUSH_CONSTANT_ALLOC_GS_CommandType_start 29 #define GFX75_3DSTATE_PUSH_CONSTANT_ALLOC_GS_CommandType_start 29 #define GFX7_3DSTATE_PUSH_CONSTANT_ALLOC_GS_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PUSH_CONSTANT_ALLOC_GS_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PUSH_CONSTANT_ALLOC_GS::Constant Buffer Offset */ #define GFX125_3DSTATE_PUSH_CONSTANT_ALLOC_GS_ConstantBufferOffset_bits 5 #define GFX12_3DSTATE_PUSH_CONSTANT_ALLOC_GS_ConstantBufferOffset_bits 5 #define GFX11_3DSTATE_PUSH_CONSTANT_ALLOC_GS_ConstantBufferOffset_bits 5 #define GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_GS_ConstantBufferOffset_bits 5 #define GFX8_3DSTATE_PUSH_CONSTANT_ALLOC_GS_ConstantBufferOffset_bits 5 #define GFX75_3DSTATE_PUSH_CONSTANT_ALLOC_GS_ConstantBufferOffset_bits 5 #define GFX7_3DSTATE_PUSH_CONSTANT_ALLOC_GS_ConstantBufferOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PUSH_CONSTANT_ALLOC_GS_ConstantBufferOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 5; case 110: return 5; case 90: return 5; case 80: return 5; case 75: return 5; case 70: return 4; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PUSH_CONSTANT_ALLOC_GS_ConstantBufferOffset_start 48 #define GFX12_3DSTATE_PUSH_CONSTANT_ALLOC_GS_ConstantBufferOffset_start 48 #define GFX11_3DSTATE_PUSH_CONSTANT_ALLOC_GS_ConstantBufferOffset_start 48 #define GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_GS_ConstantBufferOffset_start 48 #define GFX8_3DSTATE_PUSH_CONSTANT_ALLOC_GS_ConstantBufferOffset_start 48 #define GFX75_3DSTATE_PUSH_CONSTANT_ALLOC_GS_ConstantBufferOffset_start 48 #define GFX7_3DSTATE_PUSH_CONSTANT_ALLOC_GS_ConstantBufferOffset_start 48 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PUSH_CONSTANT_ALLOC_GS_ConstantBufferOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 48; case 120: return 48; case 110: return 48; case 90: return 48; case 80: return 48; case 75: return 48; case 70: return 48; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PUSH_CONSTANT_ALLOC_GS::Constant Buffer Size */ #define GFX125_3DSTATE_PUSH_CONSTANT_ALLOC_GS_ConstantBufferSize_bits 6 #define GFX12_3DSTATE_PUSH_CONSTANT_ALLOC_GS_ConstantBufferSize_bits 6 #define GFX11_3DSTATE_PUSH_CONSTANT_ALLOC_GS_ConstantBufferSize_bits 6 #define GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_GS_ConstantBufferSize_bits 6 #define GFX8_3DSTATE_PUSH_CONSTANT_ALLOC_GS_ConstantBufferSize_bits 6 #define GFX75_3DSTATE_PUSH_CONSTANT_ALLOC_GS_ConstantBufferSize_bits 6 #define GFX7_3DSTATE_PUSH_CONSTANT_ALLOC_GS_ConstantBufferSize_bits 5 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PUSH_CONSTANT_ALLOC_GS_ConstantBufferSize_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 5; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PUSH_CONSTANT_ALLOC_GS_ConstantBufferSize_start 32 #define GFX12_3DSTATE_PUSH_CONSTANT_ALLOC_GS_ConstantBufferSize_start 32 #define GFX11_3DSTATE_PUSH_CONSTANT_ALLOC_GS_ConstantBufferSize_start 32 #define GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_GS_ConstantBufferSize_start 32 #define GFX8_3DSTATE_PUSH_CONSTANT_ALLOC_GS_ConstantBufferSize_start 32 #define GFX75_3DSTATE_PUSH_CONSTANT_ALLOC_GS_ConstantBufferSize_start 32 #define GFX7_3DSTATE_PUSH_CONSTANT_ALLOC_GS_ConstantBufferSize_start 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PUSH_CONSTANT_ALLOC_GS_ConstantBufferSize_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PUSH_CONSTANT_ALLOC_GS::DWord Length */ #define GFX125_3DSTATE_PUSH_CONSTANT_ALLOC_GS_DWordLength_bits 8 #define GFX12_3DSTATE_PUSH_CONSTANT_ALLOC_GS_DWordLength_bits 8 #define GFX11_3DSTATE_PUSH_CONSTANT_ALLOC_GS_DWordLength_bits 8 #define GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_GS_DWordLength_bits 8 #define GFX8_3DSTATE_PUSH_CONSTANT_ALLOC_GS_DWordLength_bits 8 #define GFX75_3DSTATE_PUSH_CONSTANT_ALLOC_GS_DWordLength_bits 8 #define GFX7_3DSTATE_PUSH_CONSTANT_ALLOC_GS_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PUSH_CONSTANT_ALLOC_GS_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PUSH_CONSTANT_ALLOC_GS_DWordLength_start 0 #define GFX12_3DSTATE_PUSH_CONSTANT_ALLOC_GS_DWordLength_start 0 #define GFX11_3DSTATE_PUSH_CONSTANT_ALLOC_GS_DWordLength_start 0 #define GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_GS_DWordLength_start 0 #define GFX8_3DSTATE_PUSH_CONSTANT_ALLOC_GS_DWordLength_start 0 #define GFX75_3DSTATE_PUSH_CONSTANT_ALLOC_GS_DWordLength_start 0 #define GFX7_3DSTATE_PUSH_CONSTANT_ALLOC_GS_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PUSH_CONSTANT_ALLOC_GS_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PUSH_CONSTANT_ALLOC_HS */ #define GFX125_3DSTATE_PUSH_CONSTANT_ALLOC_HS_length 2 #define GFX12_3DSTATE_PUSH_CONSTANT_ALLOC_HS_length 2 #define GFX11_3DSTATE_PUSH_CONSTANT_ALLOC_HS_length 2 #define GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_HS_length 2 #define GFX8_3DSTATE_PUSH_CONSTANT_ALLOC_HS_length 2 #define GFX75_3DSTATE_PUSH_CONSTANT_ALLOC_HS_length 2 #define GFX7_3DSTATE_PUSH_CONSTANT_ALLOC_HS_length 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PUSH_CONSTANT_ALLOC_HS_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PUSH_CONSTANT_ALLOC_HS::3D Command Opcode */ #define GFX125_3DSTATE_PUSH_CONSTANT_ALLOC_HS_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_PUSH_CONSTANT_ALLOC_HS_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_PUSH_CONSTANT_ALLOC_HS_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_HS_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_PUSH_CONSTANT_ALLOC_HS_3DCommandOpcode_bits 3 #define GFX75_3DSTATE_PUSH_CONSTANT_ALLOC_HS_3DCommandOpcode_bits 3 #define GFX7_3DSTATE_PUSH_CONSTANT_ALLOC_HS_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PUSH_CONSTANT_ALLOC_HS_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PUSH_CONSTANT_ALLOC_HS_3DCommandOpcode_start 24 #define GFX12_3DSTATE_PUSH_CONSTANT_ALLOC_HS_3DCommandOpcode_start 24 #define GFX11_3DSTATE_PUSH_CONSTANT_ALLOC_HS_3DCommandOpcode_start 24 #define GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_HS_3DCommandOpcode_start 24 #define GFX8_3DSTATE_PUSH_CONSTANT_ALLOC_HS_3DCommandOpcode_start 24 #define GFX75_3DSTATE_PUSH_CONSTANT_ALLOC_HS_3DCommandOpcode_start 24 #define GFX7_3DSTATE_PUSH_CONSTANT_ALLOC_HS_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PUSH_CONSTANT_ALLOC_HS_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PUSH_CONSTANT_ALLOC_HS::3D Command Sub Opcode */ #define GFX125_3DSTATE_PUSH_CONSTANT_ALLOC_HS_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_PUSH_CONSTANT_ALLOC_HS_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_PUSH_CONSTANT_ALLOC_HS_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_HS_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_PUSH_CONSTANT_ALLOC_HS_3DCommandSubOpcode_bits 8 #define GFX75_3DSTATE_PUSH_CONSTANT_ALLOC_HS_3DCommandSubOpcode_bits 8 #define GFX7_3DSTATE_PUSH_CONSTANT_ALLOC_HS_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PUSH_CONSTANT_ALLOC_HS_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PUSH_CONSTANT_ALLOC_HS_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_PUSH_CONSTANT_ALLOC_HS_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_PUSH_CONSTANT_ALLOC_HS_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_HS_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_PUSH_CONSTANT_ALLOC_HS_3DCommandSubOpcode_start 16 #define GFX75_3DSTATE_PUSH_CONSTANT_ALLOC_HS_3DCommandSubOpcode_start 16 #define GFX7_3DSTATE_PUSH_CONSTANT_ALLOC_HS_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PUSH_CONSTANT_ALLOC_HS_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PUSH_CONSTANT_ALLOC_HS::Command SubType */ #define GFX125_3DSTATE_PUSH_CONSTANT_ALLOC_HS_CommandSubType_bits 2 #define GFX12_3DSTATE_PUSH_CONSTANT_ALLOC_HS_CommandSubType_bits 2 #define GFX11_3DSTATE_PUSH_CONSTANT_ALLOC_HS_CommandSubType_bits 2 #define GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_HS_CommandSubType_bits 2 #define GFX8_3DSTATE_PUSH_CONSTANT_ALLOC_HS_CommandSubType_bits 2 #define GFX75_3DSTATE_PUSH_CONSTANT_ALLOC_HS_CommandSubType_bits 2 #define GFX7_3DSTATE_PUSH_CONSTANT_ALLOC_HS_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PUSH_CONSTANT_ALLOC_HS_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PUSH_CONSTANT_ALLOC_HS_CommandSubType_start 27 #define GFX12_3DSTATE_PUSH_CONSTANT_ALLOC_HS_CommandSubType_start 27 #define GFX11_3DSTATE_PUSH_CONSTANT_ALLOC_HS_CommandSubType_start 27 #define GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_HS_CommandSubType_start 27 #define GFX8_3DSTATE_PUSH_CONSTANT_ALLOC_HS_CommandSubType_start 27 #define GFX75_3DSTATE_PUSH_CONSTANT_ALLOC_HS_CommandSubType_start 27 #define GFX7_3DSTATE_PUSH_CONSTANT_ALLOC_HS_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PUSH_CONSTANT_ALLOC_HS_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PUSH_CONSTANT_ALLOC_HS::Command Type */ #define GFX125_3DSTATE_PUSH_CONSTANT_ALLOC_HS_CommandType_bits 3 #define GFX12_3DSTATE_PUSH_CONSTANT_ALLOC_HS_CommandType_bits 3 #define GFX11_3DSTATE_PUSH_CONSTANT_ALLOC_HS_CommandType_bits 3 #define GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_HS_CommandType_bits 3 #define GFX8_3DSTATE_PUSH_CONSTANT_ALLOC_HS_CommandType_bits 3 #define GFX75_3DSTATE_PUSH_CONSTANT_ALLOC_HS_CommandType_bits 3 #define GFX7_3DSTATE_PUSH_CONSTANT_ALLOC_HS_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PUSH_CONSTANT_ALLOC_HS_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PUSH_CONSTANT_ALLOC_HS_CommandType_start 29 #define GFX12_3DSTATE_PUSH_CONSTANT_ALLOC_HS_CommandType_start 29 #define GFX11_3DSTATE_PUSH_CONSTANT_ALLOC_HS_CommandType_start 29 #define GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_HS_CommandType_start 29 #define GFX8_3DSTATE_PUSH_CONSTANT_ALLOC_HS_CommandType_start 29 #define GFX75_3DSTATE_PUSH_CONSTANT_ALLOC_HS_CommandType_start 29 #define GFX7_3DSTATE_PUSH_CONSTANT_ALLOC_HS_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PUSH_CONSTANT_ALLOC_HS_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PUSH_CONSTANT_ALLOC_HS::Constant Buffer Offset */ #define GFX125_3DSTATE_PUSH_CONSTANT_ALLOC_HS_ConstantBufferOffset_bits 5 #define GFX12_3DSTATE_PUSH_CONSTANT_ALLOC_HS_ConstantBufferOffset_bits 5 #define GFX11_3DSTATE_PUSH_CONSTANT_ALLOC_HS_ConstantBufferOffset_bits 5 #define GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_HS_ConstantBufferOffset_bits 5 #define GFX8_3DSTATE_PUSH_CONSTANT_ALLOC_HS_ConstantBufferOffset_bits 5 #define GFX75_3DSTATE_PUSH_CONSTANT_ALLOC_HS_ConstantBufferOffset_bits 5 #define GFX7_3DSTATE_PUSH_CONSTANT_ALLOC_HS_ConstantBufferOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PUSH_CONSTANT_ALLOC_HS_ConstantBufferOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 5; case 110: return 5; case 90: return 5; case 80: return 5; case 75: return 5; case 70: return 4; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PUSH_CONSTANT_ALLOC_HS_ConstantBufferOffset_start 48 #define GFX12_3DSTATE_PUSH_CONSTANT_ALLOC_HS_ConstantBufferOffset_start 48 #define GFX11_3DSTATE_PUSH_CONSTANT_ALLOC_HS_ConstantBufferOffset_start 48 #define GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_HS_ConstantBufferOffset_start 48 #define GFX8_3DSTATE_PUSH_CONSTANT_ALLOC_HS_ConstantBufferOffset_start 48 #define GFX75_3DSTATE_PUSH_CONSTANT_ALLOC_HS_ConstantBufferOffset_start 48 #define GFX7_3DSTATE_PUSH_CONSTANT_ALLOC_HS_ConstantBufferOffset_start 48 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PUSH_CONSTANT_ALLOC_HS_ConstantBufferOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 48; case 120: return 48; case 110: return 48; case 90: return 48; case 80: return 48; case 75: return 48; case 70: return 48; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PUSH_CONSTANT_ALLOC_HS::Constant Buffer Size */ #define GFX125_3DSTATE_PUSH_CONSTANT_ALLOC_HS_ConstantBufferSize_bits 6 #define GFX12_3DSTATE_PUSH_CONSTANT_ALLOC_HS_ConstantBufferSize_bits 6 #define GFX11_3DSTATE_PUSH_CONSTANT_ALLOC_HS_ConstantBufferSize_bits 6 #define GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_HS_ConstantBufferSize_bits 6 #define GFX8_3DSTATE_PUSH_CONSTANT_ALLOC_HS_ConstantBufferSize_bits 6 #define GFX75_3DSTATE_PUSH_CONSTANT_ALLOC_HS_ConstantBufferSize_bits 6 #define GFX7_3DSTATE_PUSH_CONSTANT_ALLOC_HS_ConstantBufferSize_bits 5 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PUSH_CONSTANT_ALLOC_HS_ConstantBufferSize_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 5; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PUSH_CONSTANT_ALLOC_HS_ConstantBufferSize_start 32 #define GFX12_3DSTATE_PUSH_CONSTANT_ALLOC_HS_ConstantBufferSize_start 32 #define GFX11_3DSTATE_PUSH_CONSTANT_ALLOC_HS_ConstantBufferSize_start 32 #define GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_HS_ConstantBufferSize_start 32 #define GFX8_3DSTATE_PUSH_CONSTANT_ALLOC_HS_ConstantBufferSize_start 32 #define GFX75_3DSTATE_PUSH_CONSTANT_ALLOC_HS_ConstantBufferSize_start 32 #define GFX7_3DSTATE_PUSH_CONSTANT_ALLOC_HS_ConstantBufferSize_start 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PUSH_CONSTANT_ALLOC_HS_ConstantBufferSize_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PUSH_CONSTANT_ALLOC_HS::DWord Length */ #define GFX125_3DSTATE_PUSH_CONSTANT_ALLOC_HS_DWordLength_bits 8 #define GFX12_3DSTATE_PUSH_CONSTANT_ALLOC_HS_DWordLength_bits 8 #define GFX11_3DSTATE_PUSH_CONSTANT_ALLOC_HS_DWordLength_bits 8 #define GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_HS_DWordLength_bits 8 #define GFX8_3DSTATE_PUSH_CONSTANT_ALLOC_HS_DWordLength_bits 8 #define GFX75_3DSTATE_PUSH_CONSTANT_ALLOC_HS_DWordLength_bits 8 #define GFX7_3DSTATE_PUSH_CONSTANT_ALLOC_HS_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PUSH_CONSTANT_ALLOC_HS_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PUSH_CONSTANT_ALLOC_HS_DWordLength_start 0 #define GFX12_3DSTATE_PUSH_CONSTANT_ALLOC_HS_DWordLength_start 0 #define GFX11_3DSTATE_PUSH_CONSTANT_ALLOC_HS_DWordLength_start 0 #define GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_HS_DWordLength_start 0 #define GFX8_3DSTATE_PUSH_CONSTANT_ALLOC_HS_DWordLength_start 0 #define GFX75_3DSTATE_PUSH_CONSTANT_ALLOC_HS_DWordLength_start 0 #define GFX7_3DSTATE_PUSH_CONSTANT_ALLOC_HS_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PUSH_CONSTANT_ALLOC_HS_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PUSH_CONSTANT_ALLOC_PS */ #define GFX125_3DSTATE_PUSH_CONSTANT_ALLOC_PS_length 2 #define GFX12_3DSTATE_PUSH_CONSTANT_ALLOC_PS_length 2 #define GFX11_3DSTATE_PUSH_CONSTANT_ALLOC_PS_length 2 #define GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_PS_length 2 #define GFX8_3DSTATE_PUSH_CONSTANT_ALLOC_PS_length 2 #define GFX75_3DSTATE_PUSH_CONSTANT_ALLOC_PS_length 2 #define GFX7_3DSTATE_PUSH_CONSTANT_ALLOC_PS_length 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PUSH_CONSTANT_ALLOC_PS_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PUSH_CONSTANT_ALLOC_PS::3D Command Opcode */ #define GFX125_3DSTATE_PUSH_CONSTANT_ALLOC_PS_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_PUSH_CONSTANT_ALLOC_PS_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_PUSH_CONSTANT_ALLOC_PS_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_PS_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_PUSH_CONSTANT_ALLOC_PS_3DCommandOpcode_bits 3 #define GFX75_3DSTATE_PUSH_CONSTANT_ALLOC_PS_3DCommandOpcode_bits 3 #define GFX7_3DSTATE_PUSH_CONSTANT_ALLOC_PS_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PUSH_CONSTANT_ALLOC_PS_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PUSH_CONSTANT_ALLOC_PS_3DCommandOpcode_start 24 #define GFX12_3DSTATE_PUSH_CONSTANT_ALLOC_PS_3DCommandOpcode_start 24 #define GFX11_3DSTATE_PUSH_CONSTANT_ALLOC_PS_3DCommandOpcode_start 24 #define GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_PS_3DCommandOpcode_start 24 #define GFX8_3DSTATE_PUSH_CONSTANT_ALLOC_PS_3DCommandOpcode_start 24 #define GFX75_3DSTATE_PUSH_CONSTANT_ALLOC_PS_3DCommandOpcode_start 24 #define GFX7_3DSTATE_PUSH_CONSTANT_ALLOC_PS_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PUSH_CONSTANT_ALLOC_PS_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PUSH_CONSTANT_ALLOC_PS::3D Command Sub Opcode */ #define GFX125_3DSTATE_PUSH_CONSTANT_ALLOC_PS_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_PUSH_CONSTANT_ALLOC_PS_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_PUSH_CONSTANT_ALLOC_PS_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_PS_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_PUSH_CONSTANT_ALLOC_PS_3DCommandSubOpcode_bits 8 #define GFX75_3DSTATE_PUSH_CONSTANT_ALLOC_PS_3DCommandSubOpcode_bits 8 #define GFX7_3DSTATE_PUSH_CONSTANT_ALLOC_PS_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PUSH_CONSTANT_ALLOC_PS_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PUSH_CONSTANT_ALLOC_PS_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_PUSH_CONSTANT_ALLOC_PS_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_PUSH_CONSTANT_ALLOC_PS_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_PS_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_PUSH_CONSTANT_ALLOC_PS_3DCommandSubOpcode_start 16 #define GFX75_3DSTATE_PUSH_CONSTANT_ALLOC_PS_3DCommandSubOpcode_start 16 #define GFX7_3DSTATE_PUSH_CONSTANT_ALLOC_PS_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PUSH_CONSTANT_ALLOC_PS_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PUSH_CONSTANT_ALLOC_PS::Command SubType */ #define GFX125_3DSTATE_PUSH_CONSTANT_ALLOC_PS_CommandSubType_bits 2 #define GFX12_3DSTATE_PUSH_CONSTANT_ALLOC_PS_CommandSubType_bits 2 #define GFX11_3DSTATE_PUSH_CONSTANT_ALLOC_PS_CommandSubType_bits 2 #define GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_PS_CommandSubType_bits 2 #define GFX8_3DSTATE_PUSH_CONSTANT_ALLOC_PS_CommandSubType_bits 2 #define GFX75_3DSTATE_PUSH_CONSTANT_ALLOC_PS_CommandSubType_bits 2 #define GFX7_3DSTATE_PUSH_CONSTANT_ALLOC_PS_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PUSH_CONSTANT_ALLOC_PS_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PUSH_CONSTANT_ALLOC_PS_CommandSubType_start 27 #define GFX12_3DSTATE_PUSH_CONSTANT_ALLOC_PS_CommandSubType_start 27 #define GFX11_3DSTATE_PUSH_CONSTANT_ALLOC_PS_CommandSubType_start 27 #define GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_PS_CommandSubType_start 27 #define GFX8_3DSTATE_PUSH_CONSTANT_ALLOC_PS_CommandSubType_start 27 #define GFX75_3DSTATE_PUSH_CONSTANT_ALLOC_PS_CommandSubType_start 27 #define GFX7_3DSTATE_PUSH_CONSTANT_ALLOC_PS_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PUSH_CONSTANT_ALLOC_PS_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PUSH_CONSTANT_ALLOC_PS::Command Type */ #define GFX125_3DSTATE_PUSH_CONSTANT_ALLOC_PS_CommandType_bits 3 #define GFX12_3DSTATE_PUSH_CONSTANT_ALLOC_PS_CommandType_bits 3 #define GFX11_3DSTATE_PUSH_CONSTANT_ALLOC_PS_CommandType_bits 3 #define GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_PS_CommandType_bits 3 #define GFX8_3DSTATE_PUSH_CONSTANT_ALLOC_PS_CommandType_bits 3 #define GFX75_3DSTATE_PUSH_CONSTANT_ALLOC_PS_CommandType_bits 3 #define GFX7_3DSTATE_PUSH_CONSTANT_ALLOC_PS_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PUSH_CONSTANT_ALLOC_PS_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PUSH_CONSTANT_ALLOC_PS_CommandType_start 29 #define GFX12_3DSTATE_PUSH_CONSTANT_ALLOC_PS_CommandType_start 29 #define GFX11_3DSTATE_PUSH_CONSTANT_ALLOC_PS_CommandType_start 29 #define GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_PS_CommandType_start 29 #define GFX8_3DSTATE_PUSH_CONSTANT_ALLOC_PS_CommandType_start 29 #define GFX75_3DSTATE_PUSH_CONSTANT_ALLOC_PS_CommandType_start 29 #define GFX7_3DSTATE_PUSH_CONSTANT_ALLOC_PS_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PUSH_CONSTANT_ALLOC_PS_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PUSH_CONSTANT_ALLOC_PS::Constant Buffer Offset */ #define GFX125_3DSTATE_PUSH_CONSTANT_ALLOC_PS_ConstantBufferOffset_bits 5 #define GFX12_3DSTATE_PUSH_CONSTANT_ALLOC_PS_ConstantBufferOffset_bits 5 #define GFX11_3DSTATE_PUSH_CONSTANT_ALLOC_PS_ConstantBufferOffset_bits 5 #define GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_PS_ConstantBufferOffset_bits 5 #define GFX8_3DSTATE_PUSH_CONSTANT_ALLOC_PS_ConstantBufferOffset_bits 5 #define GFX75_3DSTATE_PUSH_CONSTANT_ALLOC_PS_ConstantBufferOffset_bits 5 #define GFX7_3DSTATE_PUSH_CONSTANT_ALLOC_PS_ConstantBufferOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PUSH_CONSTANT_ALLOC_PS_ConstantBufferOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 5; case 110: return 5; case 90: return 5; case 80: return 5; case 75: return 5; case 70: return 4; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PUSH_CONSTANT_ALLOC_PS_ConstantBufferOffset_start 48 #define GFX12_3DSTATE_PUSH_CONSTANT_ALLOC_PS_ConstantBufferOffset_start 48 #define GFX11_3DSTATE_PUSH_CONSTANT_ALLOC_PS_ConstantBufferOffset_start 48 #define GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_PS_ConstantBufferOffset_start 48 #define GFX8_3DSTATE_PUSH_CONSTANT_ALLOC_PS_ConstantBufferOffset_start 48 #define GFX75_3DSTATE_PUSH_CONSTANT_ALLOC_PS_ConstantBufferOffset_start 48 #define GFX7_3DSTATE_PUSH_CONSTANT_ALLOC_PS_ConstantBufferOffset_start 48 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PUSH_CONSTANT_ALLOC_PS_ConstantBufferOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 48; case 120: return 48; case 110: return 48; case 90: return 48; case 80: return 48; case 75: return 48; case 70: return 48; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PUSH_CONSTANT_ALLOC_PS::Constant Buffer Size */ #define GFX125_3DSTATE_PUSH_CONSTANT_ALLOC_PS_ConstantBufferSize_bits 6 #define GFX12_3DSTATE_PUSH_CONSTANT_ALLOC_PS_ConstantBufferSize_bits 6 #define GFX11_3DSTATE_PUSH_CONSTANT_ALLOC_PS_ConstantBufferSize_bits 6 #define GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_PS_ConstantBufferSize_bits 6 #define GFX8_3DSTATE_PUSH_CONSTANT_ALLOC_PS_ConstantBufferSize_bits 6 #define GFX75_3DSTATE_PUSH_CONSTANT_ALLOC_PS_ConstantBufferSize_bits 6 #define GFX7_3DSTATE_PUSH_CONSTANT_ALLOC_PS_ConstantBufferSize_bits 5 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PUSH_CONSTANT_ALLOC_PS_ConstantBufferSize_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 5; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PUSH_CONSTANT_ALLOC_PS_ConstantBufferSize_start 32 #define GFX12_3DSTATE_PUSH_CONSTANT_ALLOC_PS_ConstantBufferSize_start 32 #define GFX11_3DSTATE_PUSH_CONSTANT_ALLOC_PS_ConstantBufferSize_start 32 #define GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_PS_ConstantBufferSize_start 32 #define GFX8_3DSTATE_PUSH_CONSTANT_ALLOC_PS_ConstantBufferSize_start 32 #define GFX75_3DSTATE_PUSH_CONSTANT_ALLOC_PS_ConstantBufferSize_start 32 #define GFX7_3DSTATE_PUSH_CONSTANT_ALLOC_PS_ConstantBufferSize_start 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PUSH_CONSTANT_ALLOC_PS_ConstantBufferSize_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PUSH_CONSTANT_ALLOC_PS::DWord Length */ #define GFX125_3DSTATE_PUSH_CONSTANT_ALLOC_PS_DWordLength_bits 8 #define GFX12_3DSTATE_PUSH_CONSTANT_ALLOC_PS_DWordLength_bits 8 #define GFX11_3DSTATE_PUSH_CONSTANT_ALLOC_PS_DWordLength_bits 8 #define GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_PS_DWordLength_bits 8 #define GFX8_3DSTATE_PUSH_CONSTANT_ALLOC_PS_DWordLength_bits 8 #define GFX75_3DSTATE_PUSH_CONSTANT_ALLOC_PS_DWordLength_bits 8 #define GFX7_3DSTATE_PUSH_CONSTANT_ALLOC_PS_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PUSH_CONSTANT_ALLOC_PS_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PUSH_CONSTANT_ALLOC_PS_DWordLength_start 0 #define GFX12_3DSTATE_PUSH_CONSTANT_ALLOC_PS_DWordLength_start 0 #define GFX11_3DSTATE_PUSH_CONSTANT_ALLOC_PS_DWordLength_start 0 #define GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_PS_DWordLength_start 0 #define GFX8_3DSTATE_PUSH_CONSTANT_ALLOC_PS_DWordLength_start 0 #define GFX75_3DSTATE_PUSH_CONSTANT_ALLOC_PS_DWordLength_start 0 #define GFX7_3DSTATE_PUSH_CONSTANT_ALLOC_PS_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PUSH_CONSTANT_ALLOC_PS_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PUSH_CONSTANT_ALLOC_VS */ #define GFX125_3DSTATE_PUSH_CONSTANT_ALLOC_VS_length 2 #define GFX12_3DSTATE_PUSH_CONSTANT_ALLOC_VS_length 2 #define GFX11_3DSTATE_PUSH_CONSTANT_ALLOC_VS_length 2 #define GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_VS_length 2 #define GFX8_3DSTATE_PUSH_CONSTANT_ALLOC_VS_length 2 #define GFX75_3DSTATE_PUSH_CONSTANT_ALLOC_VS_length 2 #define GFX7_3DSTATE_PUSH_CONSTANT_ALLOC_VS_length 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PUSH_CONSTANT_ALLOC_VS_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PUSH_CONSTANT_ALLOC_VS::3D Command Opcode */ #define GFX125_3DSTATE_PUSH_CONSTANT_ALLOC_VS_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_PUSH_CONSTANT_ALLOC_VS_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_PUSH_CONSTANT_ALLOC_VS_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_VS_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_PUSH_CONSTANT_ALLOC_VS_3DCommandOpcode_bits 3 #define GFX75_3DSTATE_PUSH_CONSTANT_ALLOC_VS_3DCommandOpcode_bits 3 #define GFX7_3DSTATE_PUSH_CONSTANT_ALLOC_VS_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PUSH_CONSTANT_ALLOC_VS_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PUSH_CONSTANT_ALLOC_VS_3DCommandOpcode_start 24 #define GFX12_3DSTATE_PUSH_CONSTANT_ALLOC_VS_3DCommandOpcode_start 24 #define GFX11_3DSTATE_PUSH_CONSTANT_ALLOC_VS_3DCommandOpcode_start 24 #define GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_VS_3DCommandOpcode_start 24 #define GFX8_3DSTATE_PUSH_CONSTANT_ALLOC_VS_3DCommandOpcode_start 24 #define GFX75_3DSTATE_PUSH_CONSTANT_ALLOC_VS_3DCommandOpcode_start 24 #define GFX7_3DSTATE_PUSH_CONSTANT_ALLOC_VS_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PUSH_CONSTANT_ALLOC_VS_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PUSH_CONSTANT_ALLOC_VS::3D Command Sub Opcode */ #define GFX125_3DSTATE_PUSH_CONSTANT_ALLOC_VS_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_PUSH_CONSTANT_ALLOC_VS_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_PUSH_CONSTANT_ALLOC_VS_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_VS_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_PUSH_CONSTANT_ALLOC_VS_3DCommandSubOpcode_bits 8 #define GFX75_3DSTATE_PUSH_CONSTANT_ALLOC_VS_3DCommandSubOpcode_bits 8 #define GFX7_3DSTATE_PUSH_CONSTANT_ALLOC_VS_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PUSH_CONSTANT_ALLOC_VS_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PUSH_CONSTANT_ALLOC_VS_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_PUSH_CONSTANT_ALLOC_VS_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_PUSH_CONSTANT_ALLOC_VS_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_VS_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_PUSH_CONSTANT_ALLOC_VS_3DCommandSubOpcode_start 16 #define GFX75_3DSTATE_PUSH_CONSTANT_ALLOC_VS_3DCommandSubOpcode_start 16 #define GFX7_3DSTATE_PUSH_CONSTANT_ALLOC_VS_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PUSH_CONSTANT_ALLOC_VS_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PUSH_CONSTANT_ALLOC_VS::Command SubType */ #define GFX125_3DSTATE_PUSH_CONSTANT_ALLOC_VS_CommandSubType_bits 2 #define GFX12_3DSTATE_PUSH_CONSTANT_ALLOC_VS_CommandSubType_bits 2 #define GFX11_3DSTATE_PUSH_CONSTANT_ALLOC_VS_CommandSubType_bits 2 #define GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_VS_CommandSubType_bits 2 #define GFX8_3DSTATE_PUSH_CONSTANT_ALLOC_VS_CommandSubType_bits 2 #define GFX75_3DSTATE_PUSH_CONSTANT_ALLOC_VS_CommandSubType_bits 2 #define GFX7_3DSTATE_PUSH_CONSTANT_ALLOC_VS_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PUSH_CONSTANT_ALLOC_VS_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PUSH_CONSTANT_ALLOC_VS_CommandSubType_start 27 #define GFX12_3DSTATE_PUSH_CONSTANT_ALLOC_VS_CommandSubType_start 27 #define GFX11_3DSTATE_PUSH_CONSTANT_ALLOC_VS_CommandSubType_start 27 #define GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_VS_CommandSubType_start 27 #define GFX8_3DSTATE_PUSH_CONSTANT_ALLOC_VS_CommandSubType_start 27 #define GFX75_3DSTATE_PUSH_CONSTANT_ALLOC_VS_CommandSubType_start 27 #define GFX7_3DSTATE_PUSH_CONSTANT_ALLOC_VS_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PUSH_CONSTANT_ALLOC_VS_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PUSH_CONSTANT_ALLOC_VS::Command Type */ #define GFX125_3DSTATE_PUSH_CONSTANT_ALLOC_VS_CommandType_bits 3 #define GFX12_3DSTATE_PUSH_CONSTANT_ALLOC_VS_CommandType_bits 3 #define GFX11_3DSTATE_PUSH_CONSTANT_ALLOC_VS_CommandType_bits 3 #define GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_VS_CommandType_bits 3 #define GFX8_3DSTATE_PUSH_CONSTANT_ALLOC_VS_CommandType_bits 3 #define GFX75_3DSTATE_PUSH_CONSTANT_ALLOC_VS_CommandType_bits 3 #define GFX7_3DSTATE_PUSH_CONSTANT_ALLOC_VS_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PUSH_CONSTANT_ALLOC_VS_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PUSH_CONSTANT_ALLOC_VS_CommandType_start 29 #define GFX12_3DSTATE_PUSH_CONSTANT_ALLOC_VS_CommandType_start 29 #define GFX11_3DSTATE_PUSH_CONSTANT_ALLOC_VS_CommandType_start 29 #define GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_VS_CommandType_start 29 #define GFX8_3DSTATE_PUSH_CONSTANT_ALLOC_VS_CommandType_start 29 #define GFX75_3DSTATE_PUSH_CONSTANT_ALLOC_VS_CommandType_start 29 #define GFX7_3DSTATE_PUSH_CONSTANT_ALLOC_VS_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PUSH_CONSTANT_ALLOC_VS_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PUSH_CONSTANT_ALLOC_VS::Constant Buffer Offset */ #define GFX125_3DSTATE_PUSH_CONSTANT_ALLOC_VS_ConstantBufferOffset_bits 5 #define GFX12_3DSTATE_PUSH_CONSTANT_ALLOC_VS_ConstantBufferOffset_bits 5 #define GFX11_3DSTATE_PUSH_CONSTANT_ALLOC_VS_ConstantBufferOffset_bits 5 #define GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_VS_ConstantBufferOffset_bits 5 #define GFX8_3DSTATE_PUSH_CONSTANT_ALLOC_VS_ConstantBufferOffset_bits 5 #define GFX75_3DSTATE_PUSH_CONSTANT_ALLOC_VS_ConstantBufferOffset_bits 5 #define GFX7_3DSTATE_PUSH_CONSTANT_ALLOC_VS_ConstantBufferOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PUSH_CONSTANT_ALLOC_VS_ConstantBufferOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 5; case 110: return 5; case 90: return 5; case 80: return 5; case 75: return 5; case 70: return 4; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PUSH_CONSTANT_ALLOC_VS_ConstantBufferOffset_start 48 #define GFX12_3DSTATE_PUSH_CONSTANT_ALLOC_VS_ConstantBufferOffset_start 48 #define GFX11_3DSTATE_PUSH_CONSTANT_ALLOC_VS_ConstantBufferOffset_start 48 #define GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_VS_ConstantBufferOffset_start 48 #define GFX8_3DSTATE_PUSH_CONSTANT_ALLOC_VS_ConstantBufferOffset_start 48 #define GFX75_3DSTATE_PUSH_CONSTANT_ALLOC_VS_ConstantBufferOffset_start 48 #define GFX7_3DSTATE_PUSH_CONSTANT_ALLOC_VS_ConstantBufferOffset_start 48 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PUSH_CONSTANT_ALLOC_VS_ConstantBufferOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 48; case 120: return 48; case 110: return 48; case 90: return 48; case 80: return 48; case 75: return 48; case 70: return 48; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PUSH_CONSTANT_ALLOC_VS::Constant Buffer Size */ #define GFX125_3DSTATE_PUSH_CONSTANT_ALLOC_VS_ConstantBufferSize_bits 6 #define GFX12_3DSTATE_PUSH_CONSTANT_ALLOC_VS_ConstantBufferSize_bits 6 #define GFX11_3DSTATE_PUSH_CONSTANT_ALLOC_VS_ConstantBufferSize_bits 6 #define GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_VS_ConstantBufferSize_bits 6 #define GFX8_3DSTATE_PUSH_CONSTANT_ALLOC_VS_ConstantBufferSize_bits 6 #define GFX75_3DSTATE_PUSH_CONSTANT_ALLOC_VS_ConstantBufferSize_bits 6 #define GFX7_3DSTATE_PUSH_CONSTANT_ALLOC_VS_ConstantBufferSize_bits 5 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PUSH_CONSTANT_ALLOC_VS_ConstantBufferSize_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 5; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PUSH_CONSTANT_ALLOC_VS_ConstantBufferSize_start 32 #define GFX12_3DSTATE_PUSH_CONSTANT_ALLOC_VS_ConstantBufferSize_start 32 #define GFX11_3DSTATE_PUSH_CONSTANT_ALLOC_VS_ConstantBufferSize_start 32 #define GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_VS_ConstantBufferSize_start 32 #define GFX8_3DSTATE_PUSH_CONSTANT_ALLOC_VS_ConstantBufferSize_start 32 #define GFX75_3DSTATE_PUSH_CONSTANT_ALLOC_VS_ConstantBufferSize_start 32 #define GFX7_3DSTATE_PUSH_CONSTANT_ALLOC_VS_ConstantBufferSize_start 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PUSH_CONSTANT_ALLOC_VS_ConstantBufferSize_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_PUSH_CONSTANT_ALLOC_VS::DWord Length */ #define GFX125_3DSTATE_PUSH_CONSTANT_ALLOC_VS_DWordLength_bits 8 #define GFX12_3DSTATE_PUSH_CONSTANT_ALLOC_VS_DWordLength_bits 8 #define GFX11_3DSTATE_PUSH_CONSTANT_ALLOC_VS_DWordLength_bits 8 #define GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_VS_DWordLength_bits 8 #define GFX8_3DSTATE_PUSH_CONSTANT_ALLOC_VS_DWordLength_bits 8 #define GFX75_3DSTATE_PUSH_CONSTANT_ALLOC_VS_DWordLength_bits 8 #define GFX7_3DSTATE_PUSH_CONSTANT_ALLOC_VS_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PUSH_CONSTANT_ALLOC_VS_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_PUSH_CONSTANT_ALLOC_VS_DWordLength_start 0 #define GFX12_3DSTATE_PUSH_CONSTANT_ALLOC_VS_DWordLength_start 0 #define GFX11_3DSTATE_PUSH_CONSTANT_ALLOC_VS_DWordLength_start 0 #define GFX9_3DSTATE_PUSH_CONSTANT_ALLOC_VS_DWordLength_start 0 #define GFX8_3DSTATE_PUSH_CONSTANT_ALLOC_VS_DWordLength_start 0 #define GFX75_3DSTATE_PUSH_CONSTANT_ALLOC_VS_DWordLength_start 0 #define GFX7_3DSTATE_PUSH_CONSTANT_ALLOC_VS_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_PUSH_CONSTANT_ALLOC_VS_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RASTER */ #define GFX125_3DSTATE_RASTER_length 5 #define GFX12_3DSTATE_RASTER_length 5 #define GFX11_3DSTATE_RASTER_length 5 #define GFX9_3DSTATE_RASTER_length 5 #define GFX8_3DSTATE_RASTER_length 5 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RASTER_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 5; case 110: return 5; case 90: return 5; case 80: return 5; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RASTER::3D Command Opcode */ #define GFX125_3DSTATE_RASTER_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_RASTER_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_RASTER_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_RASTER_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_RASTER_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RASTER_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_RASTER_3DCommandOpcode_start 24 #define GFX12_3DSTATE_RASTER_3DCommandOpcode_start 24 #define GFX11_3DSTATE_RASTER_3DCommandOpcode_start 24 #define GFX9_3DSTATE_RASTER_3DCommandOpcode_start 24 #define GFX8_3DSTATE_RASTER_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RASTER_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RASTER::3D Command Sub Opcode */ #define GFX125_3DSTATE_RASTER_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_RASTER_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_RASTER_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_RASTER_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_RASTER_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RASTER_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_RASTER_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_RASTER_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_RASTER_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_RASTER_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_RASTER_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RASTER_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RASTER::API Mode */ #define GFX125_3DSTATE_RASTER_APIMode_bits 2 #define GFX12_3DSTATE_RASTER_APIMode_bits 2 #define GFX11_3DSTATE_RASTER_APIMode_bits 2 #define GFX9_3DSTATE_RASTER_APIMode_bits 2 #define GFX8_3DSTATE_RASTER_APIMode_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RASTER_APIMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_RASTER_APIMode_start 54 #define GFX12_3DSTATE_RASTER_APIMode_start 54 #define GFX11_3DSTATE_RASTER_APIMode_start 54 #define GFX9_3DSTATE_RASTER_APIMode_start 54 #define GFX8_3DSTATE_RASTER_APIMode_start 54 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RASTER_APIMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 54; case 120: return 54; case 110: return 54; case 90: return 54; case 80: return 54; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RASTER::Antialiasing Enable */ #define GFX125_3DSTATE_RASTER_AntialiasingEnable_bits 1 #define GFX12_3DSTATE_RASTER_AntialiasingEnable_bits 1 #define GFX11_3DSTATE_RASTER_AntialiasingEnable_bits 1 #define GFX9_3DSTATE_RASTER_AntialiasingEnable_bits 1 #define GFX8_3DSTATE_RASTER_AntialiasingEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RASTER_AntialiasingEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_RASTER_AntialiasingEnable_start 34 #define GFX12_3DSTATE_RASTER_AntialiasingEnable_start 34 #define GFX11_3DSTATE_RASTER_AntialiasingEnable_start 34 #define GFX9_3DSTATE_RASTER_AntialiasingEnable_start 34 #define GFX8_3DSTATE_RASTER_AntialiasingEnable_start 34 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RASTER_AntialiasingEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 34; case 120: return 34; case 110: return 34; case 90: return 34; case 80: return 34; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RASTER::Back Face Fill Mode */ #define GFX125_3DSTATE_RASTER_BackFaceFillMode_bits 2 #define GFX12_3DSTATE_RASTER_BackFaceFillMode_bits 2 #define GFX11_3DSTATE_RASTER_BackFaceFillMode_bits 2 #define GFX9_3DSTATE_RASTER_BackFaceFillMode_bits 2 #define GFX8_3DSTATE_RASTER_BackFaceFillMode_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RASTER_BackFaceFillMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_RASTER_BackFaceFillMode_start 35 #define GFX12_3DSTATE_RASTER_BackFaceFillMode_start 35 #define GFX11_3DSTATE_RASTER_BackFaceFillMode_start 35 #define GFX9_3DSTATE_RASTER_BackFaceFillMode_start 35 #define GFX8_3DSTATE_RASTER_BackFaceFillMode_start 35 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RASTER_BackFaceFillMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 35; case 120: return 35; case 110: return 35; case 90: return 35; case 80: return 35; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RASTER::Command SubType */ #define GFX125_3DSTATE_RASTER_CommandSubType_bits 2 #define GFX12_3DSTATE_RASTER_CommandSubType_bits 2 #define GFX11_3DSTATE_RASTER_CommandSubType_bits 2 #define GFX9_3DSTATE_RASTER_CommandSubType_bits 2 #define GFX8_3DSTATE_RASTER_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RASTER_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_RASTER_CommandSubType_start 27 #define GFX12_3DSTATE_RASTER_CommandSubType_start 27 #define GFX11_3DSTATE_RASTER_CommandSubType_start 27 #define GFX9_3DSTATE_RASTER_CommandSubType_start 27 #define GFX8_3DSTATE_RASTER_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RASTER_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RASTER::Command Type */ #define GFX125_3DSTATE_RASTER_CommandType_bits 3 #define GFX12_3DSTATE_RASTER_CommandType_bits 3 #define GFX11_3DSTATE_RASTER_CommandType_bits 3 #define GFX9_3DSTATE_RASTER_CommandType_bits 3 #define GFX8_3DSTATE_RASTER_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RASTER_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_RASTER_CommandType_start 29 #define GFX12_3DSTATE_RASTER_CommandType_start 29 #define GFX11_3DSTATE_RASTER_CommandType_start 29 #define GFX9_3DSTATE_RASTER_CommandType_start 29 #define GFX8_3DSTATE_RASTER_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RASTER_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RASTER::Conservative Rasterization Enable */ #define GFX125_3DSTATE_RASTER_ConservativeRasterizationEnable_bits 1 #define GFX12_3DSTATE_RASTER_ConservativeRasterizationEnable_bits 1 #define GFX11_3DSTATE_RASTER_ConservativeRasterizationEnable_bits 1 #define GFX9_3DSTATE_RASTER_ConservativeRasterizationEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RASTER_ConservativeRasterizationEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_RASTER_ConservativeRasterizationEnable_start 56 #define GFX12_3DSTATE_RASTER_ConservativeRasterizationEnable_start 56 #define GFX11_3DSTATE_RASTER_ConservativeRasterizationEnable_start 56 #define GFX9_3DSTATE_RASTER_ConservativeRasterizationEnable_start 56 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RASTER_ConservativeRasterizationEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 56; case 120: return 56; case 110: return 56; case 90: return 56; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RASTER::Cull Mode */ #define GFX125_3DSTATE_RASTER_CullMode_bits 2 #define GFX12_3DSTATE_RASTER_CullMode_bits 2 #define GFX11_3DSTATE_RASTER_CullMode_bits 2 #define GFX9_3DSTATE_RASTER_CullMode_bits 2 #define GFX8_3DSTATE_RASTER_CullMode_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RASTER_CullMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_RASTER_CullMode_start 48 #define GFX12_3DSTATE_RASTER_CullMode_start 48 #define GFX11_3DSTATE_RASTER_CullMode_start 48 #define GFX9_3DSTATE_RASTER_CullMode_start 48 #define GFX8_3DSTATE_RASTER_CullMode_start 48 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RASTER_CullMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 48; case 120: return 48; case 110: return 48; case 90: return 48; case 80: return 48; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RASTER::DWord Length */ #define GFX125_3DSTATE_RASTER_DWordLength_bits 8 #define GFX12_3DSTATE_RASTER_DWordLength_bits 8 #define GFX11_3DSTATE_RASTER_DWordLength_bits 8 #define GFX9_3DSTATE_RASTER_DWordLength_bits 8 #define GFX8_3DSTATE_RASTER_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RASTER_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_RASTER_DWordLength_start 0 #define GFX12_3DSTATE_RASTER_DWordLength_start 0 #define GFX11_3DSTATE_RASTER_DWordLength_start 0 #define GFX9_3DSTATE_RASTER_DWordLength_start 0 #define GFX8_3DSTATE_RASTER_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RASTER_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RASTER::DX Multisample Rasterization Enable */ #define GFX125_3DSTATE_RASTER_DXMultisampleRasterizationEnable_bits 1 #define GFX12_3DSTATE_RASTER_DXMultisampleRasterizationEnable_bits 1 #define GFX11_3DSTATE_RASTER_DXMultisampleRasterizationEnable_bits 1 #define GFX9_3DSTATE_RASTER_DXMultisampleRasterizationEnable_bits 1 #define GFX8_3DSTATE_RASTER_DXMultisampleRasterizationEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RASTER_DXMultisampleRasterizationEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_RASTER_DXMultisampleRasterizationEnable_start 44 #define GFX12_3DSTATE_RASTER_DXMultisampleRasterizationEnable_start 44 #define GFX11_3DSTATE_RASTER_DXMultisampleRasterizationEnable_start 44 #define GFX9_3DSTATE_RASTER_DXMultisampleRasterizationEnable_start 44 #define GFX8_3DSTATE_RASTER_DXMultisampleRasterizationEnable_start 44 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RASTER_DXMultisampleRasterizationEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 44; case 120: return 44; case 110: return 44; case 90: return 44; case 80: return 44; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RASTER::DX Multisample Rasterization Mode */ #define GFX125_3DSTATE_RASTER_DXMultisampleRasterizationMode_bits 2 #define GFX12_3DSTATE_RASTER_DXMultisampleRasterizationMode_bits 2 #define GFX11_3DSTATE_RASTER_DXMultisampleRasterizationMode_bits 2 #define GFX9_3DSTATE_RASTER_DXMultisampleRasterizationMode_bits 2 #define GFX8_3DSTATE_RASTER_DXMultisampleRasterizationMode_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RASTER_DXMultisampleRasterizationMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_RASTER_DXMultisampleRasterizationMode_start 42 #define GFX12_3DSTATE_RASTER_DXMultisampleRasterizationMode_start 42 #define GFX11_3DSTATE_RASTER_DXMultisampleRasterizationMode_start 42 #define GFX9_3DSTATE_RASTER_DXMultisampleRasterizationMode_start 42 #define GFX8_3DSTATE_RASTER_DXMultisampleRasterizationMode_start 42 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RASTER_DXMultisampleRasterizationMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 42; case 120: return 42; case 110: return 42; case 90: return 42; case 80: return 42; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RASTER::Force Multisampling */ #define GFX125_3DSTATE_RASTER_ForceMultisampling_bits 1 #define GFX12_3DSTATE_RASTER_ForceMultisampling_bits 1 #define GFX11_3DSTATE_RASTER_ForceMultisampling_bits 1 #define GFX9_3DSTATE_RASTER_ForceMultisampling_bits 1 #define GFX8_3DSTATE_RASTER_ForceMultisampling_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RASTER_ForceMultisampling_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_RASTER_ForceMultisampling_start 46 #define GFX12_3DSTATE_RASTER_ForceMultisampling_start 46 #define GFX11_3DSTATE_RASTER_ForceMultisampling_start 46 #define GFX9_3DSTATE_RASTER_ForceMultisampling_start 46 #define GFX8_3DSTATE_RASTER_ForceMultisampling_start 46 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RASTER_ForceMultisampling_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 46; case 120: return 46; case 110: return 46; case 90: return 46; case 80: return 46; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RASTER::Forced Sample Count */ #define GFX125_3DSTATE_RASTER_ForcedSampleCount_bits 3 #define GFX12_3DSTATE_RASTER_ForcedSampleCount_bits 3 #define GFX11_3DSTATE_RASTER_ForcedSampleCount_bits 3 #define GFX9_3DSTATE_RASTER_ForcedSampleCount_bits 3 #define GFX8_3DSTATE_RASTER_ForcedSampleCount_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RASTER_ForcedSampleCount_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_RASTER_ForcedSampleCount_start 50 #define GFX12_3DSTATE_RASTER_ForcedSampleCount_start 50 #define GFX11_3DSTATE_RASTER_ForcedSampleCount_start 50 #define GFX9_3DSTATE_RASTER_ForcedSampleCount_start 50 #define GFX8_3DSTATE_RASTER_ForcedSampleCount_start 50 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RASTER_ForcedSampleCount_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 50; case 120: return 50; case 110: return 50; case 90: return 50; case 80: return 50; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RASTER::Front Face Fill Mode */ #define GFX125_3DSTATE_RASTER_FrontFaceFillMode_bits 2 #define GFX12_3DSTATE_RASTER_FrontFaceFillMode_bits 2 #define GFX11_3DSTATE_RASTER_FrontFaceFillMode_bits 2 #define GFX9_3DSTATE_RASTER_FrontFaceFillMode_bits 2 #define GFX8_3DSTATE_RASTER_FrontFaceFillMode_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RASTER_FrontFaceFillMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_RASTER_FrontFaceFillMode_start 37 #define GFX12_3DSTATE_RASTER_FrontFaceFillMode_start 37 #define GFX11_3DSTATE_RASTER_FrontFaceFillMode_start 37 #define GFX9_3DSTATE_RASTER_FrontFaceFillMode_start 37 #define GFX8_3DSTATE_RASTER_FrontFaceFillMode_start 37 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RASTER_FrontFaceFillMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 37; case 120: return 37; case 110: return 37; case 90: return 37; case 80: return 37; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RASTER::Front Winding */ #define GFX125_3DSTATE_RASTER_FrontWinding_bits 1 #define GFX12_3DSTATE_RASTER_FrontWinding_bits 1 #define GFX11_3DSTATE_RASTER_FrontWinding_bits 1 #define GFX9_3DSTATE_RASTER_FrontWinding_bits 1 #define GFX8_3DSTATE_RASTER_FrontWinding_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RASTER_FrontWinding_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_RASTER_FrontWinding_start 53 #define GFX12_3DSTATE_RASTER_FrontWinding_start 53 #define GFX11_3DSTATE_RASTER_FrontWinding_start 53 #define GFX9_3DSTATE_RASTER_FrontWinding_start 53 #define GFX8_3DSTATE_RASTER_FrontWinding_start 53 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RASTER_FrontWinding_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 53; case 120: return 53; case 110: return 53; case 90: return 53; case 80: return 53; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RASTER::Global Depth Offset Clamp */ #define GFX125_3DSTATE_RASTER_GlobalDepthOffsetClamp_bits 32 #define GFX12_3DSTATE_RASTER_GlobalDepthOffsetClamp_bits 32 #define GFX11_3DSTATE_RASTER_GlobalDepthOffsetClamp_bits 32 #define GFX9_3DSTATE_RASTER_GlobalDepthOffsetClamp_bits 32 #define GFX8_3DSTATE_RASTER_GlobalDepthOffsetClamp_bits 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RASTER_GlobalDepthOffsetClamp_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_RASTER_GlobalDepthOffsetClamp_start 128 #define GFX12_3DSTATE_RASTER_GlobalDepthOffsetClamp_start 128 #define GFX11_3DSTATE_RASTER_GlobalDepthOffsetClamp_start 128 #define GFX9_3DSTATE_RASTER_GlobalDepthOffsetClamp_start 128 #define GFX8_3DSTATE_RASTER_GlobalDepthOffsetClamp_start 128 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RASTER_GlobalDepthOffsetClamp_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 128; case 120: return 128; case 110: return 128; case 90: return 128; case 80: return 128; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RASTER::Global Depth Offset Constant */ #define GFX125_3DSTATE_RASTER_GlobalDepthOffsetConstant_bits 32 #define GFX12_3DSTATE_RASTER_GlobalDepthOffsetConstant_bits 32 #define GFX11_3DSTATE_RASTER_GlobalDepthOffsetConstant_bits 32 #define GFX9_3DSTATE_RASTER_GlobalDepthOffsetConstant_bits 32 #define GFX8_3DSTATE_RASTER_GlobalDepthOffsetConstant_bits 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RASTER_GlobalDepthOffsetConstant_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_RASTER_GlobalDepthOffsetConstant_start 64 #define GFX12_3DSTATE_RASTER_GlobalDepthOffsetConstant_start 64 #define GFX11_3DSTATE_RASTER_GlobalDepthOffsetConstant_start 64 #define GFX9_3DSTATE_RASTER_GlobalDepthOffsetConstant_start 64 #define GFX8_3DSTATE_RASTER_GlobalDepthOffsetConstant_start 64 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RASTER_GlobalDepthOffsetConstant_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 64; case 80: return 64; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RASTER::Global Depth Offset Enable Point */ #define GFX125_3DSTATE_RASTER_GlobalDepthOffsetEnablePoint_bits 1 #define GFX12_3DSTATE_RASTER_GlobalDepthOffsetEnablePoint_bits 1 #define GFX11_3DSTATE_RASTER_GlobalDepthOffsetEnablePoint_bits 1 #define GFX9_3DSTATE_RASTER_GlobalDepthOffsetEnablePoint_bits 1 #define GFX8_3DSTATE_RASTER_GlobalDepthOffsetEnablePoint_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RASTER_GlobalDepthOffsetEnablePoint_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_RASTER_GlobalDepthOffsetEnablePoint_start 39 #define GFX12_3DSTATE_RASTER_GlobalDepthOffsetEnablePoint_start 39 #define GFX11_3DSTATE_RASTER_GlobalDepthOffsetEnablePoint_start 39 #define GFX9_3DSTATE_RASTER_GlobalDepthOffsetEnablePoint_start 39 #define GFX8_3DSTATE_RASTER_GlobalDepthOffsetEnablePoint_start 39 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RASTER_GlobalDepthOffsetEnablePoint_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 39; case 120: return 39; case 110: return 39; case 90: return 39; case 80: return 39; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RASTER::Global Depth Offset Enable Solid */ #define GFX125_3DSTATE_RASTER_GlobalDepthOffsetEnableSolid_bits 1 #define GFX12_3DSTATE_RASTER_GlobalDepthOffsetEnableSolid_bits 1 #define GFX11_3DSTATE_RASTER_GlobalDepthOffsetEnableSolid_bits 1 #define GFX9_3DSTATE_RASTER_GlobalDepthOffsetEnableSolid_bits 1 #define GFX8_3DSTATE_RASTER_GlobalDepthOffsetEnableSolid_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RASTER_GlobalDepthOffsetEnableSolid_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_RASTER_GlobalDepthOffsetEnableSolid_start 41 #define GFX12_3DSTATE_RASTER_GlobalDepthOffsetEnableSolid_start 41 #define GFX11_3DSTATE_RASTER_GlobalDepthOffsetEnableSolid_start 41 #define GFX9_3DSTATE_RASTER_GlobalDepthOffsetEnableSolid_start 41 #define GFX8_3DSTATE_RASTER_GlobalDepthOffsetEnableSolid_start 41 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RASTER_GlobalDepthOffsetEnableSolid_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 41; case 120: return 41; case 110: return 41; case 90: return 41; case 80: return 41; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RASTER::Global Depth Offset Enable Wireframe */ #define GFX125_3DSTATE_RASTER_GlobalDepthOffsetEnableWireframe_bits 1 #define GFX12_3DSTATE_RASTER_GlobalDepthOffsetEnableWireframe_bits 1 #define GFX11_3DSTATE_RASTER_GlobalDepthOffsetEnableWireframe_bits 1 #define GFX9_3DSTATE_RASTER_GlobalDepthOffsetEnableWireframe_bits 1 #define GFX8_3DSTATE_RASTER_GlobalDepthOffsetEnableWireframe_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RASTER_GlobalDepthOffsetEnableWireframe_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_RASTER_GlobalDepthOffsetEnableWireframe_start 40 #define GFX12_3DSTATE_RASTER_GlobalDepthOffsetEnableWireframe_start 40 #define GFX11_3DSTATE_RASTER_GlobalDepthOffsetEnableWireframe_start 40 #define GFX9_3DSTATE_RASTER_GlobalDepthOffsetEnableWireframe_start 40 #define GFX8_3DSTATE_RASTER_GlobalDepthOffsetEnableWireframe_start 40 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RASTER_GlobalDepthOffsetEnableWireframe_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 40; case 120: return 40; case 110: return 40; case 90: return 40; case 80: return 40; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RASTER::Global Depth Offset Scale */ #define GFX125_3DSTATE_RASTER_GlobalDepthOffsetScale_bits 32 #define GFX12_3DSTATE_RASTER_GlobalDepthOffsetScale_bits 32 #define GFX11_3DSTATE_RASTER_GlobalDepthOffsetScale_bits 32 #define GFX9_3DSTATE_RASTER_GlobalDepthOffsetScale_bits 32 #define GFX8_3DSTATE_RASTER_GlobalDepthOffsetScale_bits 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RASTER_GlobalDepthOffsetScale_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_RASTER_GlobalDepthOffsetScale_start 96 #define GFX12_3DSTATE_RASTER_GlobalDepthOffsetScale_start 96 #define GFX11_3DSTATE_RASTER_GlobalDepthOffsetScale_start 96 #define GFX9_3DSTATE_RASTER_GlobalDepthOffsetScale_start 96 #define GFX8_3DSTATE_RASTER_GlobalDepthOffsetScale_start 96 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RASTER_GlobalDepthOffsetScale_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 96; case 120: return 96; case 110: return 96; case 90: return 96; case 80: return 96; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RASTER::Scissor Rectangle Enable */ #define GFX125_3DSTATE_RASTER_ScissorRectangleEnable_bits 1 #define GFX12_3DSTATE_RASTER_ScissorRectangleEnable_bits 1 #define GFX11_3DSTATE_RASTER_ScissorRectangleEnable_bits 1 #define GFX9_3DSTATE_RASTER_ScissorRectangleEnable_bits 1 #define GFX8_3DSTATE_RASTER_ScissorRectangleEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RASTER_ScissorRectangleEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_RASTER_ScissorRectangleEnable_start 33 #define GFX12_3DSTATE_RASTER_ScissorRectangleEnable_start 33 #define GFX11_3DSTATE_RASTER_ScissorRectangleEnable_start 33 #define GFX9_3DSTATE_RASTER_ScissorRectangleEnable_start 33 #define GFX8_3DSTATE_RASTER_ScissorRectangleEnable_start 33 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RASTER_ScissorRectangleEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 33; case 120: return 33; case 110: return 33; case 90: return 33; case 80: return 33; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RASTER::Smooth Point Enable */ #define GFX125_3DSTATE_RASTER_SmoothPointEnable_bits 1 #define GFX12_3DSTATE_RASTER_SmoothPointEnable_bits 1 #define GFX11_3DSTATE_RASTER_SmoothPointEnable_bits 1 #define GFX9_3DSTATE_RASTER_SmoothPointEnable_bits 1 #define GFX8_3DSTATE_RASTER_SmoothPointEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RASTER_SmoothPointEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_RASTER_SmoothPointEnable_start 45 #define GFX12_3DSTATE_RASTER_SmoothPointEnable_start 45 #define GFX11_3DSTATE_RASTER_SmoothPointEnable_start 45 #define GFX9_3DSTATE_RASTER_SmoothPointEnable_start 45 #define GFX8_3DSTATE_RASTER_SmoothPointEnable_start 45 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RASTER_SmoothPointEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 45; case 120: return 45; case 110: return 45; case 90: return 45; case 80: return 45; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RASTER::Viewport Z Clip Test Enable */ #define GFX8_3DSTATE_RASTER_ViewportZClipTestEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RASTER_ViewportZClipTestEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX8_3DSTATE_RASTER_ViewportZClipTestEnable_start 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RASTER_ViewportZClipTestEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 32; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RASTER::Viewport Z Far Clip Test Enable */ #define GFX125_3DSTATE_RASTER_ViewportZFarClipTestEnable_bits 1 #define GFX12_3DSTATE_RASTER_ViewportZFarClipTestEnable_bits 1 #define GFX11_3DSTATE_RASTER_ViewportZFarClipTestEnable_bits 1 #define GFX9_3DSTATE_RASTER_ViewportZFarClipTestEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RASTER_ViewportZFarClipTestEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_RASTER_ViewportZFarClipTestEnable_start 58 #define GFX12_3DSTATE_RASTER_ViewportZFarClipTestEnable_start 58 #define GFX11_3DSTATE_RASTER_ViewportZFarClipTestEnable_start 58 #define GFX9_3DSTATE_RASTER_ViewportZFarClipTestEnable_start 58 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RASTER_ViewportZFarClipTestEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 58; case 120: return 58; case 110: return 58; case 90: return 58; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RASTER::Viewport Z Near Clip Test Enable */ #define GFX125_3DSTATE_RASTER_ViewportZNearClipTestEnable_bits 1 #define GFX12_3DSTATE_RASTER_ViewportZNearClipTestEnable_bits 1 #define GFX11_3DSTATE_RASTER_ViewportZNearClipTestEnable_bits 1 #define GFX9_3DSTATE_RASTER_ViewportZNearClipTestEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RASTER_ViewportZNearClipTestEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_RASTER_ViewportZNearClipTestEnable_start 32 #define GFX12_3DSTATE_RASTER_ViewportZNearClipTestEnable_start 32 #define GFX11_3DSTATE_RASTER_ViewportZNearClipTestEnable_start 32 #define GFX9_3DSTATE_RASTER_ViewportZNearClipTestEnable_start 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RASTER_ViewportZNearClipTestEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RAST_MULTISAMPLE */ #define GFX75_3DSTATE_RAST_MULTISAMPLE_length 6 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 6; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RAST_MULTISAMPLE::3D Command Opcode */ #define GFX75_3DSTATE_RAST_MULTISAMPLE_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 3; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_RAST_MULTISAMPLE_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 24; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RAST_MULTISAMPLE::3D Command Sub Opcode */ #define GFX75_3DSTATE_RAST_MULTISAMPLE_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 8; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_RAST_MULTISAMPLE_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 16; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RAST_MULTISAMPLE::Command SubType */ #define GFX75_3DSTATE_RAST_MULTISAMPLE_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 2; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_RAST_MULTISAMPLE_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 27; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RAST_MULTISAMPLE::Command Type */ #define GFX75_3DSTATE_RAST_MULTISAMPLE_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 3; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_RAST_MULTISAMPLE_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 29; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RAST_MULTISAMPLE::DWord Length */ #define GFX75_3DSTATE_RAST_MULTISAMPLE_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 8; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_RAST_MULTISAMPLE_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RAST_MULTISAMPLE::Number of Rasterization Multisamples */ #define GFX75_3DSTATE_RAST_MULTISAMPLE_NumberofRasterizationMultisamples_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_NumberofRasterizationMultisamples_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 3; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_RAST_MULTISAMPLE_NumberofRasterizationMultisamples_start 33 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_NumberofRasterizationMultisamples_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 33; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RAST_MULTISAMPLE::Sample0 X Offset */ #define GFX75_3DSTATE_RAST_MULTISAMPLE_Sample0XOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_Sample0XOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 4; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_RAST_MULTISAMPLE_Sample0XOffset_start 68 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_Sample0XOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 68; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RAST_MULTISAMPLE::Sample0 Y Offset */ #define GFX75_3DSTATE_RAST_MULTISAMPLE_Sample0YOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_Sample0YOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 4; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_RAST_MULTISAMPLE_Sample0YOffset_start 64 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_Sample0YOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 64; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RAST_MULTISAMPLE::Sample10 X Offset */ #define GFX75_3DSTATE_RAST_MULTISAMPLE_Sample10XOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_Sample10XOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 4; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_RAST_MULTISAMPLE_Sample10XOffset_start 148 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_Sample10XOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 148; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RAST_MULTISAMPLE::Sample10 Y Offset */ #define GFX75_3DSTATE_RAST_MULTISAMPLE_Sample10YOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_Sample10YOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 4; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_RAST_MULTISAMPLE_Sample10YOffset_start 144 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_Sample10YOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 144; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RAST_MULTISAMPLE::Sample11 X Offset */ #define GFX75_3DSTATE_RAST_MULTISAMPLE_Sample11XOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_Sample11XOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 4; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_RAST_MULTISAMPLE_Sample11XOffset_start 156 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_Sample11XOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 156; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RAST_MULTISAMPLE::Sample11 Y Offset */ #define GFX75_3DSTATE_RAST_MULTISAMPLE_Sample11YOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_Sample11YOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 4; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_RAST_MULTISAMPLE_Sample11YOffset_start 152 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_Sample11YOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 152; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RAST_MULTISAMPLE::Sample12 X Offset */ #define GFX75_3DSTATE_RAST_MULTISAMPLE_Sample12XOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_Sample12XOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 4; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_RAST_MULTISAMPLE_Sample12XOffset_start 164 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_Sample12XOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 164; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RAST_MULTISAMPLE::Sample12 Y Offset */ #define GFX75_3DSTATE_RAST_MULTISAMPLE_Sample12YOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_Sample12YOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 4; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_RAST_MULTISAMPLE_Sample12YOffset_start 160 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_Sample12YOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 160; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RAST_MULTISAMPLE::Sample13 X Offset */ #define GFX75_3DSTATE_RAST_MULTISAMPLE_Sample13XOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_Sample13XOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 4; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_RAST_MULTISAMPLE_Sample13XOffset_start 172 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_Sample13XOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 172; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RAST_MULTISAMPLE::Sample13 Y Offset */ #define GFX75_3DSTATE_RAST_MULTISAMPLE_Sample13YOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_Sample13YOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 4; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_RAST_MULTISAMPLE_Sample13YOffset_start 168 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_Sample13YOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 168; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RAST_MULTISAMPLE::Sample14 X Offset */ #define GFX75_3DSTATE_RAST_MULTISAMPLE_Sample14XOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_Sample14XOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 4; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_RAST_MULTISAMPLE_Sample14XOffset_start 180 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_Sample14XOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 180; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RAST_MULTISAMPLE::Sample14 Y Offset */ #define GFX75_3DSTATE_RAST_MULTISAMPLE_Sample14YOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_Sample14YOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 4; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_RAST_MULTISAMPLE_Sample14YOffset_start 176 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_Sample14YOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 176; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RAST_MULTISAMPLE::Sample15 X Offset */ #define GFX75_3DSTATE_RAST_MULTISAMPLE_Sample15XOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_Sample15XOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 4; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_RAST_MULTISAMPLE_Sample15XOffset_start 188 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_Sample15XOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 188; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RAST_MULTISAMPLE::Sample15 Y Offset */ #define GFX75_3DSTATE_RAST_MULTISAMPLE_Sample15YOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_Sample15YOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 4; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_RAST_MULTISAMPLE_Sample15YOffset_start 184 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_Sample15YOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 184; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RAST_MULTISAMPLE::Sample1 X Offset */ #define GFX75_3DSTATE_RAST_MULTISAMPLE_Sample1XOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_Sample1XOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 4; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_RAST_MULTISAMPLE_Sample1XOffset_start 76 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_Sample1XOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 76; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RAST_MULTISAMPLE::Sample1 Y Offset */ #define GFX75_3DSTATE_RAST_MULTISAMPLE_Sample1YOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_Sample1YOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 4; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_RAST_MULTISAMPLE_Sample1YOffset_start 72 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_Sample1YOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 72; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RAST_MULTISAMPLE::Sample2 X Offset */ #define GFX75_3DSTATE_RAST_MULTISAMPLE_Sample2XOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_Sample2XOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 4; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_RAST_MULTISAMPLE_Sample2XOffset_start 84 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_Sample2XOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 84; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RAST_MULTISAMPLE::Sample2 Y Offset */ #define GFX75_3DSTATE_RAST_MULTISAMPLE_Sample2YOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_Sample2YOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 4; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_RAST_MULTISAMPLE_Sample2YOffset_start 80 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_Sample2YOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 80; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RAST_MULTISAMPLE::Sample3 X Offset */ #define GFX75_3DSTATE_RAST_MULTISAMPLE_Sample3XOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_Sample3XOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 4; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_RAST_MULTISAMPLE_Sample3XOffset_start 92 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_Sample3XOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 92; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RAST_MULTISAMPLE::Sample3 Y Offset */ #define GFX75_3DSTATE_RAST_MULTISAMPLE_Sample3YOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_Sample3YOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 4; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_RAST_MULTISAMPLE_Sample3YOffset_start 88 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_Sample3YOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 88; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RAST_MULTISAMPLE::Sample4 X Offset */ #define GFX75_3DSTATE_RAST_MULTISAMPLE_Sample4XOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_Sample4XOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 4; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_RAST_MULTISAMPLE_Sample4XOffset_start 100 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_Sample4XOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 100; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RAST_MULTISAMPLE::Sample4 Y Offset */ #define GFX75_3DSTATE_RAST_MULTISAMPLE_Sample4YOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_Sample4YOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 4; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_RAST_MULTISAMPLE_Sample4YOffset_start 96 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_Sample4YOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 96; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RAST_MULTISAMPLE::Sample5 X Offset */ #define GFX75_3DSTATE_RAST_MULTISAMPLE_Sample5XOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_Sample5XOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 4; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_RAST_MULTISAMPLE_Sample5XOffset_start 108 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_Sample5XOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 108; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RAST_MULTISAMPLE::Sample5 Y Offset */ #define GFX75_3DSTATE_RAST_MULTISAMPLE_Sample5YOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_Sample5YOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 4; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_RAST_MULTISAMPLE_Sample5YOffset_start 104 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_Sample5YOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 104; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RAST_MULTISAMPLE::Sample6 X Offset */ #define GFX75_3DSTATE_RAST_MULTISAMPLE_Sample6XOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_Sample6XOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 4; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_RAST_MULTISAMPLE_Sample6XOffset_start 116 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_Sample6XOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 116; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RAST_MULTISAMPLE::Sample6 Y Offset */ #define GFX75_3DSTATE_RAST_MULTISAMPLE_Sample6YOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_Sample6YOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 4; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_RAST_MULTISAMPLE_Sample6YOffset_start 112 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_Sample6YOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 112; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RAST_MULTISAMPLE::Sample7 X Offset */ #define GFX75_3DSTATE_RAST_MULTISAMPLE_Sample7XOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_Sample7XOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 4; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_RAST_MULTISAMPLE_Sample7XOffset_start 124 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_Sample7XOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 124; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RAST_MULTISAMPLE::Sample7 Y Offset */ #define GFX75_3DSTATE_RAST_MULTISAMPLE_Sample7YOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_Sample7YOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 4; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_RAST_MULTISAMPLE_Sample7YOffset_start 120 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_Sample7YOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 120; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RAST_MULTISAMPLE::Sample8 X Offset */ #define GFX75_3DSTATE_RAST_MULTISAMPLE_Sample8XOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_Sample8XOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 4; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_RAST_MULTISAMPLE_Sample8XOffset_start 132 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_Sample8XOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 132; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RAST_MULTISAMPLE::Sample8 Y Offset */ #define GFX75_3DSTATE_RAST_MULTISAMPLE_Sample8YOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_Sample8YOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 4; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_RAST_MULTISAMPLE_Sample8YOffset_start 128 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_Sample8YOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 128; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RAST_MULTISAMPLE::Sample9 X Offset */ #define GFX75_3DSTATE_RAST_MULTISAMPLE_Sample9XOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_Sample9XOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 4; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_RAST_MULTISAMPLE_Sample9XOffset_start 140 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_Sample9XOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 140; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RAST_MULTISAMPLE::Sample9 Y Offset */ #define GFX75_3DSTATE_RAST_MULTISAMPLE_Sample9YOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_Sample9YOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 4; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_RAST_MULTISAMPLE_Sample9YOffset_start 136 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RAST_MULTISAMPLE_Sample9YOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 136; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RS_CONSTANT_POINTER */ #define GFX125_3DSTATE_RS_CONSTANT_POINTER_length 4 #define GFX12_3DSTATE_RS_CONSTANT_POINTER_length 4 #define GFX11_3DSTATE_RS_CONSTANT_POINTER_length 4 #define GFX9_3DSTATE_RS_CONSTANT_POINTER_length 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RS_CONSTANT_POINTER_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RS_CONSTANT_POINTER::3D Command Opcode */ #define GFX125_3DSTATE_RS_CONSTANT_POINTER_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_RS_CONSTANT_POINTER_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_RS_CONSTANT_POINTER_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_RS_CONSTANT_POINTER_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RS_CONSTANT_POINTER_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_RS_CONSTANT_POINTER_3DCommandOpcode_start 24 #define GFX12_3DSTATE_RS_CONSTANT_POINTER_3DCommandOpcode_start 24 #define GFX11_3DSTATE_RS_CONSTANT_POINTER_3DCommandOpcode_start 24 #define GFX9_3DSTATE_RS_CONSTANT_POINTER_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RS_CONSTANT_POINTER_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RS_CONSTANT_POINTER::3D Command Sub Opcode */ #define GFX125_3DSTATE_RS_CONSTANT_POINTER_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_RS_CONSTANT_POINTER_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_RS_CONSTANT_POINTER_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_RS_CONSTANT_POINTER_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RS_CONSTANT_POINTER_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_RS_CONSTANT_POINTER_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_RS_CONSTANT_POINTER_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_RS_CONSTANT_POINTER_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_RS_CONSTANT_POINTER_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RS_CONSTANT_POINTER_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RS_CONSTANT_POINTER::Command SubType */ #define GFX125_3DSTATE_RS_CONSTANT_POINTER_CommandSubType_bits 2 #define GFX12_3DSTATE_RS_CONSTANT_POINTER_CommandSubType_bits 2 #define GFX11_3DSTATE_RS_CONSTANT_POINTER_CommandSubType_bits 2 #define GFX9_3DSTATE_RS_CONSTANT_POINTER_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RS_CONSTANT_POINTER_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_RS_CONSTANT_POINTER_CommandSubType_start 27 #define GFX12_3DSTATE_RS_CONSTANT_POINTER_CommandSubType_start 27 #define GFX11_3DSTATE_RS_CONSTANT_POINTER_CommandSubType_start 27 #define GFX9_3DSTATE_RS_CONSTANT_POINTER_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RS_CONSTANT_POINTER_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RS_CONSTANT_POINTER::Command Type */ #define GFX125_3DSTATE_RS_CONSTANT_POINTER_CommandType_bits 3 #define GFX12_3DSTATE_RS_CONSTANT_POINTER_CommandType_bits 3 #define GFX11_3DSTATE_RS_CONSTANT_POINTER_CommandType_bits 3 #define GFX9_3DSTATE_RS_CONSTANT_POINTER_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RS_CONSTANT_POINTER_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_RS_CONSTANT_POINTER_CommandType_start 29 #define GFX12_3DSTATE_RS_CONSTANT_POINTER_CommandType_start 29 #define GFX11_3DSTATE_RS_CONSTANT_POINTER_CommandType_start 29 #define GFX9_3DSTATE_RS_CONSTANT_POINTER_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RS_CONSTANT_POINTER_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RS_CONSTANT_POINTER::DWord Length */ #define GFX125_3DSTATE_RS_CONSTANT_POINTER_DWordLength_bits 8 #define GFX12_3DSTATE_RS_CONSTANT_POINTER_DWordLength_bits 8 #define GFX11_3DSTATE_RS_CONSTANT_POINTER_DWordLength_bits 8 #define GFX9_3DSTATE_RS_CONSTANT_POINTER_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RS_CONSTANT_POINTER_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_RS_CONSTANT_POINTER_DWordLength_start 0 #define GFX12_3DSTATE_RS_CONSTANT_POINTER_DWordLength_start 0 #define GFX11_3DSTATE_RS_CONSTANT_POINTER_DWordLength_start 0 #define GFX9_3DSTATE_RS_CONSTANT_POINTER_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RS_CONSTANT_POINTER_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RS_CONSTANT_POINTER::Global Constant Buffer Address */ #define GFX125_3DSTATE_RS_CONSTANT_POINTER_GlobalConstantBufferAddress_bits 26 #define GFX12_3DSTATE_RS_CONSTANT_POINTER_GlobalConstantBufferAddress_bits 26 #define GFX11_3DSTATE_RS_CONSTANT_POINTER_GlobalConstantBufferAddress_bits 26 #define GFX9_3DSTATE_RS_CONSTANT_POINTER_GlobalConstantBufferAddress_bits 26 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RS_CONSTANT_POINTER_GlobalConstantBufferAddress_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 26; case 120: return 26; case 110: return 26; case 90: return 26; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_RS_CONSTANT_POINTER_GlobalConstantBufferAddress_start 70 #define GFX12_3DSTATE_RS_CONSTANT_POINTER_GlobalConstantBufferAddress_start 70 #define GFX11_3DSTATE_RS_CONSTANT_POINTER_GlobalConstantBufferAddress_start 70 #define GFX9_3DSTATE_RS_CONSTANT_POINTER_GlobalConstantBufferAddress_start 70 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RS_CONSTANT_POINTER_GlobalConstantBufferAddress_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 70; case 120: return 70; case 110: return 70; case 90: return 70; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RS_CONSTANT_POINTER::Global Constant Buffer Address High */ #define GFX125_3DSTATE_RS_CONSTANT_POINTER_GlobalConstantBufferAddressHigh_bits 32 #define GFX12_3DSTATE_RS_CONSTANT_POINTER_GlobalConstantBufferAddressHigh_bits 32 #define GFX11_3DSTATE_RS_CONSTANT_POINTER_GlobalConstantBufferAddressHigh_bits 32 #define GFX9_3DSTATE_RS_CONSTANT_POINTER_GlobalConstantBufferAddressHigh_bits 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RS_CONSTANT_POINTER_GlobalConstantBufferAddressHigh_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_RS_CONSTANT_POINTER_GlobalConstantBufferAddressHigh_start 96 #define GFX12_3DSTATE_RS_CONSTANT_POINTER_GlobalConstantBufferAddressHigh_start 96 #define GFX11_3DSTATE_RS_CONSTANT_POINTER_GlobalConstantBufferAddressHigh_start 96 #define GFX9_3DSTATE_RS_CONSTANT_POINTER_GlobalConstantBufferAddressHigh_start 96 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RS_CONSTANT_POINTER_GlobalConstantBufferAddressHigh_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 96; case 120: return 96; case 110: return 96; case 90: return 96; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RS_CONSTANT_POINTER::Operation Load or Store */ #define GFX125_3DSTATE_RS_CONSTANT_POINTER_OperationLoadorStore_bits 1 #define GFX12_3DSTATE_RS_CONSTANT_POINTER_OperationLoadorStore_bits 1 #define GFX11_3DSTATE_RS_CONSTANT_POINTER_OperationLoadorStore_bits 1 #define GFX9_3DSTATE_RS_CONSTANT_POINTER_OperationLoadorStore_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RS_CONSTANT_POINTER_OperationLoadorStore_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_RS_CONSTANT_POINTER_OperationLoadorStore_start 44 #define GFX12_3DSTATE_RS_CONSTANT_POINTER_OperationLoadorStore_start 44 #define GFX11_3DSTATE_RS_CONSTANT_POINTER_OperationLoadorStore_start 44 #define GFX9_3DSTATE_RS_CONSTANT_POINTER_OperationLoadorStore_start 44 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RS_CONSTANT_POINTER_OperationLoadorStore_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 44; case 120: return 44; case 110: return 44; case 90: return 44; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_RS_CONSTANT_POINTER::Shader Select */ #define GFX125_3DSTATE_RS_CONSTANT_POINTER_ShaderSelect_bits 3 #define GFX12_3DSTATE_RS_CONSTANT_POINTER_ShaderSelect_bits 3 #define GFX11_3DSTATE_RS_CONSTANT_POINTER_ShaderSelect_bits 3 #define GFX9_3DSTATE_RS_CONSTANT_POINTER_ShaderSelect_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RS_CONSTANT_POINTER_ShaderSelect_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_RS_CONSTANT_POINTER_ShaderSelect_start 60 #define GFX12_3DSTATE_RS_CONSTANT_POINTER_ShaderSelect_start 60 #define GFX11_3DSTATE_RS_CONSTANT_POINTER_ShaderSelect_start 60 #define GFX9_3DSTATE_RS_CONSTANT_POINTER_ShaderSelect_start 60 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_RS_CONSTANT_POINTER_ShaderSelect_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 60; case 120: return 60; case 110: return 60; case 90: return 60; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLER_PALETTE_LOAD0 */ /* 3DSTATE_SAMPLER_PALETTE_LOAD0::3D Command Opcode */ #define GFX125_3DSTATE_SAMPLER_PALETTE_LOAD0_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_SAMPLER_PALETTE_LOAD0_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_SAMPLER_PALETTE_LOAD0_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_SAMPLER_PALETTE_LOAD0_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_SAMPLER_PALETTE_LOAD0_3DCommandOpcode_bits 3 #define GFX75_3DSTATE_SAMPLER_PALETTE_LOAD0_3DCommandOpcode_bits 3 #define GFX7_3DSTATE_SAMPLER_PALETTE_LOAD0_3DCommandOpcode_bits 3 #define GFX6_3DSTATE_SAMPLER_PALETTE_LOAD0_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_PALETTE_LOAD0_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLER_PALETTE_LOAD0_3DCommandOpcode_start 24 #define GFX12_3DSTATE_SAMPLER_PALETTE_LOAD0_3DCommandOpcode_start 24 #define GFX11_3DSTATE_SAMPLER_PALETTE_LOAD0_3DCommandOpcode_start 24 #define GFX9_3DSTATE_SAMPLER_PALETTE_LOAD0_3DCommandOpcode_start 24 #define GFX8_3DSTATE_SAMPLER_PALETTE_LOAD0_3DCommandOpcode_start 24 #define GFX75_3DSTATE_SAMPLER_PALETTE_LOAD0_3DCommandOpcode_start 24 #define GFX7_3DSTATE_SAMPLER_PALETTE_LOAD0_3DCommandOpcode_start 24 #define GFX6_3DSTATE_SAMPLER_PALETTE_LOAD0_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_PALETTE_LOAD0_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 24; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLER_PALETTE_LOAD0::3D Command Sub Opcode */ #define GFX125_3DSTATE_SAMPLER_PALETTE_LOAD0_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_SAMPLER_PALETTE_LOAD0_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_SAMPLER_PALETTE_LOAD0_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_SAMPLER_PALETTE_LOAD0_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_SAMPLER_PALETTE_LOAD0_3DCommandSubOpcode_bits 8 #define GFX75_3DSTATE_SAMPLER_PALETTE_LOAD0_3DCommandSubOpcode_bits 8 #define GFX7_3DSTATE_SAMPLER_PALETTE_LOAD0_3DCommandSubOpcode_bits 8 #define GFX6_3DSTATE_SAMPLER_PALETTE_LOAD0_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_PALETTE_LOAD0_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLER_PALETTE_LOAD0_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_SAMPLER_PALETTE_LOAD0_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_SAMPLER_PALETTE_LOAD0_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_SAMPLER_PALETTE_LOAD0_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_SAMPLER_PALETTE_LOAD0_3DCommandSubOpcode_start 16 #define GFX75_3DSTATE_SAMPLER_PALETTE_LOAD0_3DCommandSubOpcode_start 16 #define GFX7_3DSTATE_SAMPLER_PALETTE_LOAD0_3DCommandSubOpcode_start 16 #define GFX6_3DSTATE_SAMPLER_PALETTE_LOAD0_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_PALETTE_LOAD0_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 16; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLER_PALETTE_LOAD0::Command SubType */ #define GFX125_3DSTATE_SAMPLER_PALETTE_LOAD0_CommandSubType_bits 2 #define GFX12_3DSTATE_SAMPLER_PALETTE_LOAD0_CommandSubType_bits 2 #define GFX11_3DSTATE_SAMPLER_PALETTE_LOAD0_CommandSubType_bits 2 #define GFX9_3DSTATE_SAMPLER_PALETTE_LOAD0_CommandSubType_bits 2 #define GFX8_3DSTATE_SAMPLER_PALETTE_LOAD0_CommandSubType_bits 2 #define GFX75_3DSTATE_SAMPLER_PALETTE_LOAD0_CommandSubType_bits 2 #define GFX7_3DSTATE_SAMPLER_PALETTE_LOAD0_CommandSubType_bits 2 #define GFX6_3DSTATE_SAMPLER_PALETTE_LOAD0_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_PALETTE_LOAD0_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLER_PALETTE_LOAD0_CommandSubType_start 27 #define GFX12_3DSTATE_SAMPLER_PALETTE_LOAD0_CommandSubType_start 27 #define GFX11_3DSTATE_SAMPLER_PALETTE_LOAD0_CommandSubType_start 27 #define GFX9_3DSTATE_SAMPLER_PALETTE_LOAD0_CommandSubType_start 27 #define GFX8_3DSTATE_SAMPLER_PALETTE_LOAD0_CommandSubType_start 27 #define GFX75_3DSTATE_SAMPLER_PALETTE_LOAD0_CommandSubType_start 27 #define GFX7_3DSTATE_SAMPLER_PALETTE_LOAD0_CommandSubType_start 27 #define GFX6_3DSTATE_SAMPLER_PALETTE_LOAD0_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_PALETTE_LOAD0_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 27; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLER_PALETTE_LOAD0::Command Type */ #define GFX125_3DSTATE_SAMPLER_PALETTE_LOAD0_CommandType_bits 3 #define GFX12_3DSTATE_SAMPLER_PALETTE_LOAD0_CommandType_bits 3 #define GFX11_3DSTATE_SAMPLER_PALETTE_LOAD0_CommandType_bits 3 #define GFX9_3DSTATE_SAMPLER_PALETTE_LOAD0_CommandType_bits 3 #define GFX8_3DSTATE_SAMPLER_PALETTE_LOAD0_CommandType_bits 3 #define GFX75_3DSTATE_SAMPLER_PALETTE_LOAD0_CommandType_bits 3 #define GFX7_3DSTATE_SAMPLER_PALETTE_LOAD0_CommandType_bits 3 #define GFX6_3DSTATE_SAMPLER_PALETTE_LOAD0_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_PALETTE_LOAD0_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLER_PALETTE_LOAD0_CommandType_start 29 #define GFX12_3DSTATE_SAMPLER_PALETTE_LOAD0_CommandType_start 29 #define GFX11_3DSTATE_SAMPLER_PALETTE_LOAD0_CommandType_start 29 #define GFX9_3DSTATE_SAMPLER_PALETTE_LOAD0_CommandType_start 29 #define GFX8_3DSTATE_SAMPLER_PALETTE_LOAD0_CommandType_start 29 #define GFX75_3DSTATE_SAMPLER_PALETTE_LOAD0_CommandType_start 29 #define GFX7_3DSTATE_SAMPLER_PALETTE_LOAD0_CommandType_start 29 #define GFX6_3DSTATE_SAMPLER_PALETTE_LOAD0_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_PALETTE_LOAD0_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 29; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLER_PALETTE_LOAD0::DWord Length */ #define GFX125_3DSTATE_SAMPLER_PALETTE_LOAD0_DWordLength_bits 8 #define GFX12_3DSTATE_SAMPLER_PALETTE_LOAD0_DWordLength_bits 8 #define GFX11_3DSTATE_SAMPLER_PALETTE_LOAD0_DWordLength_bits 8 #define GFX9_3DSTATE_SAMPLER_PALETTE_LOAD0_DWordLength_bits 8 #define GFX8_3DSTATE_SAMPLER_PALETTE_LOAD0_DWordLength_bits 8 #define GFX75_3DSTATE_SAMPLER_PALETTE_LOAD0_DWordLength_bits 8 #define GFX7_3DSTATE_SAMPLER_PALETTE_LOAD0_DWordLength_bits 8 #define GFX6_3DSTATE_SAMPLER_PALETTE_LOAD0_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_PALETTE_LOAD0_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLER_PALETTE_LOAD0_DWordLength_start 0 #define GFX12_3DSTATE_SAMPLER_PALETTE_LOAD0_DWordLength_start 0 #define GFX11_3DSTATE_SAMPLER_PALETTE_LOAD0_DWordLength_start 0 #define GFX9_3DSTATE_SAMPLER_PALETTE_LOAD0_DWordLength_start 0 #define GFX8_3DSTATE_SAMPLER_PALETTE_LOAD0_DWordLength_start 0 #define GFX75_3DSTATE_SAMPLER_PALETTE_LOAD0_DWordLength_start 0 #define GFX7_3DSTATE_SAMPLER_PALETTE_LOAD0_DWordLength_start 0 #define GFX6_3DSTATE_SAMPLER_PALETTE_LOAD0_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_PALETTE_LOAD0_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLER_PALETTE_LOAD1 */ /* 3DSTATE_SAMPLER_PALETTE_LOAD1::3D Command Opcode */ #define GFX125_3DSTATE_SAMPLER_PALETTE_LOAD1_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_SAMPLER_PALETTE_LOAD1_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_SAMPLER_PALETTE_LOAD1_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_SAMPLER_PALETTE_LOAD1_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_SAMPLER_PALETTE_LOAD1_3DCommandOpcode_bits 3 #define GFX75_3DSTATE_SAMPLER_PALETTE_LOAD1_3DCommandOpcode_bits 3 #define GFX7_3DSTATE_SAMPLER_PALETTE_LOAD1_3DCommandOpcode_bits 3 #define GFX6_3DSTATE_SAMPLER_PALETTE_LOAD1_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_PALETTE_LOAD1_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLER_PALETTE_LOAD1_3DCommandOpcode_start 24 #define GFX12_3DSTATE_SAMPLER_PALETTE_LOAD1_3DCommandOpcode_start 24 #define GFX11_3DSTATE_SAMPLER_PALETTE_LOAD1_3DCommandOpcode_start 24 #define GFX9_3DSTATE_SAMPLER_PALETTE_LOAD1_3DCommandOpcode_start 24 #define GFX8_3DSTATE_SAMPLER_PALETTE_LOAD1_3DCommandOpcode_start 24 #define GFX75_3DSTATE_SAMPLER_PALETTE_LOAD1_3DCommandOpcode_start 24 #define GFX7_3DSTATE_SAMPLER_PALETTE_LOAD1_3DCommandOpcode_start 24 #define GFX6_3DSTATE_SAMPLER_PALETTE_LOAD1_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_PALETTE_LOAD1_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 24; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLER_PALETTE_LOAD1::3D Command Sub Opcode */ #define GFX125_3DSTATE_SAMPLER_PALETTE_LOAD1_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_SAMPLER_PALETTE_LOAD1_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_SAMPLER_PALETTE_LOAD1_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_SAMPLER_PALETTE_LOAD1_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_SAMPLER_PALETTE_LOAD1_3DCommandSubOpcode_bits 8 #define GFX75_3DSTATE_SAMPLER_PALETTE_LOAD1_3DCommandSubOpcode_bits 8 #define GFX7_3DSTATE_SAMPLER_PALETTE_LOAD1_3DCommandSubOpcode_bits 8 #define GFX6_3DSTATE_SAMPLER_PALETTE_LOAD1_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_PALETTE_LOAD1_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLER_PALETTE_LOAD1_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_SAMPLER_PALETTE_LOAD1_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_SAMPLER_PALETTE_LOAD1_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_SAMPLER_PALETTE_LOAD1_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_SAMPLER_PALETTE_LOAD1_3DCommandSubOpcode_start 16 #define GFX75_3DSTATE_SAMPLER_PALETTE_LOAD1_3DCommandSubOpcode_start 16 #define GFX7_3DSTATE_SAMPLER_PALETTE_LOAD1_3DCommandSubOpcode_start 16 #define GFX6_3DSTATE_SAMPLER_PALETTE_LOAD1_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_PALETTE_LOAD1_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 16; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLER_PALETTE_LOAD1::Command SubType */ #define GFX125_3DSTATE_SAMPLER_PALETTE_LOAD1_CommandSubType_bits 2 #define GFX12_3DSTATE_SAMPLER_PALETTE_LOAD1_CommandSubType_bits 2 #define GFX11_3DSTATE_SAMPLER_PALETTE_LOAD1_CommandSubType_bits 2 #define GFX9_3DSTATE_SAMPLER_PALETTE_LOAD1_CommandSubType_bits 2 #define GFX8_3DSTATE_SAMPLER_PALETTE_LOAD1_CommandSubType_bits 2 #define GFX75_3DSTATE_SAMPLER_PALETTE_LOAD1_CommandSubType_bits 2 #define GFX7_3DSTATE_SAMPLER_PALETTE_LOAD1_CommandSubType_bits 2 #define GFX6_3DSTATE_SAMPLER_PALETTE_LOAD1_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_PALETTE_LOAD1_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLER_PALETTE_LOAD1_CommandSubType_start 27 #define GFX12_3DSTATE_SAMPLER_PALETTE_LOAD1_CommandSubType_start 27 #define GFX11_3DSTATE_SAMPLER_PALETTE_LOAD1_CommandSubType_start 27 #define GFX9_3DSTATE_SAMPLER_PALETTE_LOAD1_CommandSubType_start 27 #define GFX8_3DSTATE_SAMPLER_PALETTE_LOAD1_CommandSubType_start 27 #define GFX75_3DSTATE_SAMPLER_PALETTE_LOAD1_CommandSubType_start 27 #define GFX7_3DSTATE_SAMPLER_PALETTE_LOAD1_CommandSubType_start 27 #define GFX6_3DSTATE_SAMPLER_PALETTE_LOAD1_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_PALETTE_LOAD1_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 27; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLER_PALETTE_LOAD1::Command Type */ #define GFX125_3DSTATE_SAMPLER_PALETTE_LOAD1_CommandType_bits 3 #define GFX12_3DSTATE_SAMPLER_PALETTE_LOAD1_CommandType_bits 3 #define GFX11_3DSTATE_SAMPLER_PALETTE_LOAD1_CommandType_bits 3 #define GFX9_3DSTATE_SAMPLER_PALETTE_LOAD1_CommandType_bits 3 #define GFX8_3DSTATE_SAMPLER_PALETTE_LOAD1_CommandType_bits 3 #define GFX75_3DSTATE_SAMPLER_PALETTE_LOAD1_CommandType_bits 3 #define GFX7_3DSTATE_SAMPLER_PALETTE_LOAD1_CommandType_bits 3 #define GFX6_3DSTATE_SAMPLER_PALETTE_LOAD1_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_PALETTE_LOAD1_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLER_PALETTE_LOAD1_CommandType_start 29 #define GFX12_3DSTATE_SAMPLER_PALETTE_LOAD1_CommandType_start 29 #define GFX11_3DSTATE_SAMPLER_PALETTE_LOAD1_CommandType_start 29 #define GFX9_3DSTATE_SAMPLER_PALETTE_LOAD1_CommandType_start 29 #define GFX8_3DSTATE_SAMPLER_PALETTE_LOAD1_CommandType_start 29 #define GFX75_3DSTATE_SAMPLER_PALETTE_LOAD1_CommandType_start 29 #define GFX7_3DSTATE_SAMPLER_PALETTE_LOAD1_CommandType_start 29 #define GFX6_3DSTATE_SAMPLER_PALETTE_LOAD1_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_PALETTE_LOAD1_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 29; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLER_PALETTE_LOAD1::DWord Length */ #define GFX125_3DSTATE_SAMPLER_PALETTE_LOAD1_DWordLength_bits 8 #define GFX12_3DSTATE_SAMPLER_PALETTE_LOAD1_DWordLength_bits 8 #define GFX11_3DSTATE_SAMPLER_PALETTE_LOAD1_DWordLength_bits 8 #define GFX9_3DSTATE_SAMPLER_PALETTE_LOAD1_DWordLength_bits 8 #define GFX8_3DSTATE_SAMPLER_PALETTE_LOAD1_DWordLength_bits 8 #define GFX75_3DSTATE_SAMPLER_PALETTE_LOAD1_DWordLength_bits 8 #define GFX7_3DSTATE_SAMPLER_PALETTE_LOAD1_DWordLength_bits 8 #define GFX6_3DSTATE_SAMPLER_PALETTE_LOAD1_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_PALETTE_LOAD1_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLER_PALETTE_LOAD1_DWordLength_start 0 #define GFX12_3DSTATE_SAMPLER_PALETTE_LOAD1_DWordLength_start 0 #define GFX11_3DSTATE_SAMPLER_PALETTE_LOAD1_DWordLength_start 0 #define GFX9_3DSTATE_SAMPLER_PALETTE_LOAD1_DWordLength_start 0 #define GFX8_3DSTATE_SAMPLER_PALETTE_LOAD1_DWordLength_start 0 #define GFX75_3DSTATE_SAMPLER_PALETTE_LOAD1_DWordLength_start 0 #define GFX7_3DSTATE_SAMPLER_PALETTE_LOAD1_DWordLength_start 0 #define GFX6_3DSTATE_SAMPLER_PALETTE_LOAD1_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_PALETTE_LOAD1_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLER_STATE_POINTERS */ #define GFX6_3DSTATE_SAMPLER_STATE_POINTERS_length 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLER_STATE_POINTERS::3D Command Opcode */ #define GFX6_3DSTATE_SAMPLER_STATE_POINTERS_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_SAMPLER_STATE_POINTERS_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 24; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLER_STATE_POINTERS::3D Command Sub Opcode */ #define GFX6_3DSTATE_SAMPLER_STATE_POINTERS_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_SAMPLER_STATE_POINTERS_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 16; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLER_STATE_POINTERS::Command SubType */ #define GFX6_3DSTATE_SAMPLER_STATE_POINTERS_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_SAMPLER_STATE_POINTERS_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 27; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLER_STATE_POINTERS::Command Type */ #define GFX6_3DSTATE_SAMPLER_STATE_POINTERS_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_SAMPLER_STATE_POINTERS_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 29; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLER_STATE_POINTERS::DWord Length */ #define GFX6_3DSTATE_SAMPLER_STATE_POINTERS_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_SAMPLER_STATE_POINTERS_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLER_STATE_POINTERS::GS Sampler State Change */ #define GFX6_3DSTATE_SAMPLER_STATE_POINTERS_GSSamplerStateChange_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_GSSamplerStateChange_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_SAMPLER_STATE_POINTERS_GSSamplerStateChange_start 9 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_GSSamplerStateChange_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 9; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLER_STATE_POINTERS::PS Sampler State Change */ #define GFX6_3DSTATE_SAMPLER_STATE_POINTERS_PSSamplerStateChange_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_PSSamplerStateChange_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_SAMPLER_STATE_POINTERS_PSSamplerStateChange_start 12 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_PSSamplerStateChange_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 12; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLER_STATE_POINTERS::Pointer to GS Sampler State */ #define GFX6_3DSTATE_SAMPLER_STATE_POINTERS_PointertoGSSamplerState_bits 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_PointertoGSSamplerState_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 27; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_SAMPLER_STATE_POINTERS_PointertoGSSamplerState_start 69 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_PointertoGSSamplerState_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 69; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLER_STATE_POINTERS::Pointer to PS Sampler State */ #define GFX6_3DSTATE_SAMPLER_STATE_POINTERS_PointertoPSSamplerState_bits 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_PointertoPSSamplerState_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 27; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_SAMPLER_STATE_POINTERS_PointertoPSSamplerState_start 101 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_PointertoPSSamplerState_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 101; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLER_STATE_POINTERS::Pointer to VS Sampler State */ #define GFX6_3DSTATE_SAMPLER_STATE_POINTERS_PointertoVSSamplerState_bits 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_PointertoVSSamplerState_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 27; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_SAMPLER_STATE_POINTERS_PointertoVSSamplerState_start 37 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_PointertoVSSamplerState_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 37; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLER_STATE_POINTERS::VS Sampler State Change */ #define GFX6_3DSTATE_SAMPLER_STATE_POINTERS_VSSamplerStateChange_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_VSSamplerStateChange_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_SAMPLER_STATE_POINTERS_VSSamplerStateChange_start 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_VSSamplerStateChange_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLER_STATE_POINTERS_DS */ #define GFX125_3DSTATE_SAMPLER_STATE_POINTERS_DS_length 2 #define GFX12_3DSTATE_SAMPLER_STATE_POINTERS_DS_length 2 #define GFX11_3DSTATE_SAMPLER_STATE_POINTERS_DS_length 2 #define GFX9_3DSTATE_SAMPLER_STATE_POINTERS_DS_length 2 #define GFX8_3DSTATE_SAMPLER_STATE_POINTERS_DS_length 2 #define GFX75_3DSTATE_SAMPLER_STATE_POINTERS_DS_length 2 #define GFX7_3DSTATE_SAMPLER_STATE_POINTERS_DS_length 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_DS_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLER_STATE_POINTERS_DS::3D Command Opcode */ #define GFX125_3DSTATE_SAMPLER_STATE_POINTERS_DS_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_SAMPLER_STATE_POINTERS_DS_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_SAMPLER_STATE_POINTERS_DS_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_SAMPLER_STATE_POINTERS_DS_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_SAMPLER_STATE_POINTERS_DS_3DCommandOpcode_bits 3 #define GFX75_3DSTATE_SAMPLER_STATE_POINTERS_DS_3DCommandOpcode_bits 3 #define GFX7_3DSTATE_SAMPLER_STATE_POINTERS_DS_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_DS_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLER_STATE_POINTERS_DS_3DCommandOpcode_start 24 #define GFX12_3DSTATE_SAMPLER_STATE_POINTERS_DS_3DCommandOpcode_start 24 #define GFX11_3DSTATE_SAMPLER_STATE_POINTERS_DS_3DCommandOpcode_start 24 #define GFX9_3DSTATE_SAMPLER_STATE_POINTERS_DS_3DCommandOpcode_start 24 #define GFX8_3DSTATE_SAMPLER_STATE_POINTERS_DS_3DCommandOpcode_start 24 #define GFX75_3DSTATE_SAMPLER_STATE_POINTERS_DS_3DCommandOpcode_start 24 #define GFX7_3DSTATE_SAMPLER_STATE_POINTERS_DS_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_DS_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLER_STATE_POINTERS_DS::3D Command Sub Opcode */ #define GFX125_3DSTATE_SAMPLER_STATE_POINTERS_DS_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_SAMPLER_STATE_POINTERS_DS_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_SAMPLER_STATE_POINTERS_DS_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_SAMPLER_STATE_POINTERS_DS_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_SAMPLER_STATE_POINTERS_DS_3DCommandSubOpcode_bits 8 #define GFX75_3DSTATE_SAMPLER_STATE_POINTERS_DS_3DCommandSubOpcode_bits 8 #define GFX7_3DSTATE_SAMPLER_STATE_POINTERS_DS_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_DS_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLER_STATE_POINTERS_DS_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_SAMPLER_STATE_POINTERS_DS_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_SAMPLER_STATE_POINTERS_DS_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_SAMPLER_STATE_POINTERS_DS_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_SAMPLER_STATE_POINTERS_DS_3DCommandSubOpcode_start 16 #define GFX75_3DSTATE_SAMPLER_STATE_POINTERS_DS_3DCommandSubOpcode_start 16 #define GFX7_3DSTATE_SAMPLER_STATE_POINTERS_DS_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_DS_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLER_STATE_POINTERS_DS::Command SubType */ #define GFX125_3DSTATE_SAMPLER_STATE_POINTERS_DS_CommandSubType_bits 2 #define GFX12_3DSTATE_SAMPLER_STATE_POINTERS_DS_CommandSubType_bits 2 #define GFX11_3DSTATE_SAMPLER_STATE_POINTERS_DS_CommandSubType_bits 2 #define GFX9_3DSTATE_SAMPLER_STATE_POINTERS_DS_CommandSubType_bits 2 #define GFX8_3DSTATE_SAMPLER_STATE_POINTERS_DS_CommandSubType_bits 2 #define GFX75_3DSTATE_SAMPLER_STATE_POINTERS_DS_CommandSubType_bits 2 #define GFX7_3DSTATE_SAMPLER_STATE_POINTERS_DS_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_DS_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLER_STATE_POINTERS_DS_CommandSubType_start 27 #define GFX12_3DSTATE_SAMPLER_STATE_POINTERS_DS_CommandSubType_start 27 #define GFX11_3DSTATE_SAMPLER_STATE_POINTERS_DS_CommandSubType_start 27 #define GFX9_3DSTATE_SAMPLER_STATE_POINTERS_DS_CommandSubType_start 27 #define GFX8_3DSTATE_SAMPLER_STATE_POINTERS_DS_CommandSubType_start 27 #define GFX75_3DSTATE_SAMPLER_STATE_POINTERS_DS_CommandSubType_start 27 #define GFX7_3DSTATE_SAMPLER_STATE_POINTERS_DS_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_DS_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLER_STATE_POINTERS_DS::Command Type */ #define GFX125_3DSTATE_SAMPLER_STATE_POINTERS_DS_CommandType_bits 3 #define GFX12_3DSTATE_SAMPLER_STATE_POINTERS_DS_CommandType_bits 3 #define GFX11_3DSTATE_SAMPLER_STATE_POINTERS_DS_CommandType_bits 3 #define GFX9_3DSTATE_SAMPLER_STATE_POINTERS_DS_CommandType_bits 3 #define GFX8_3DSTATE_SAMPLER_STATE_POINTERS_DS_CommandType_bits 3 #define GFX75_3DSTATE_SAMPLER_STATE_POINTERS_DS_CommandType_bits 3 #define GFX7_3DSTATE_SAMPLER_STATE_POINTERS_DS_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_DS_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLER_STATE_POINTERS_DS_CommandType_start 29 #define GFX12_3DSTATE_SAMPLER_STATE_POINTERS_DS_CommandType_start 29 #define GFX11_3DSTATE_SAMPLER_STATE_POINTERS_DS_CommandType_start 29 #define GFX9_3DSTATE_SAMPLER_STATE_POINTERS_DS_CommandType_start 29 #define GFX8_3DSTATE_SAMPLER_STATE_POINTERS_DS_CommandType_start 29 #define GFX75_3DSTATE_SAMPLER_STATE_POINTERS_DS_CommandType_start 29 #define GFX7_3DSTATE_SAMPLER_STATE_POINTERS_DS_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_DS_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLER_STATE_POINTERS_DS::DWord Length */ #define GFX125_3DSTATE_SAMPLER_STATE_POINTERS_DS_DWordLength_bits 8 #define GFX12_3DSTATE_SAMPLER_STATE_POINTERS_DS_DWordLength_bits 8 #define GFX11_3DSTATE_SAMPLER_STATE_POINTERS_DS_DWordLength_bits 8 #define GFX9_3DSTATE_SAMPLER_STATE_POINTERS_DS_DWordLength_bits 8 #define GFX8_3DSTATE_SAMPLER_STATE_POINTERS_DS_DWordLength_bits 8 #define GFX75_3DSTATE_SAMPLER_STATE_POINTERS_DS_DWordLength_bits 8 #define GFX7_3DSTATE_SAMPLER_STATE_POINTERS_DS_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_DS_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLER_STATE_POINTERS_DS_DWordLength_start 0 #define GFX12_3DSTATE_SAMPLER_STATE_POINTERS_DS_DWordLength_start 0 #define GFX11_3DSTATE_SAMPLER_STATE_POINTERS_DS_DWordLength_start 0 #define GFX9_3DSTATE_SAMPLER_STATE_POINTERS_DS_DWordLength_start 0 #define GFX8_3DSTATE_SAMPLER_STATE_POINTERS_DS_DWordLength_start 0 #define GFX75_3DSTATE_SAMPLER_STATE_POINTERS_DS_DWordLength_start 0 #define GFX7_3DSTATE_SAMPLER_STATE_POINTERS_DS_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_DS_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLER_STATE_POINTERS_DS::Pointer to DS Sampler State */ #define GFX125_3DSTATE_SAMPLER_STATE_POINTERS_DS_PointertoDSSamplerState_bits 27 #define GFX12_3DSTATE_SAMPLER_STATE_POINTERS_DS_PointertoDSSamplerState_bits 27 #define GFX11_3DSTATE_SAMPLER_STATE_POINTERS_DS_PointertoDSSamplerState_bits 27 #define GFX9_3DSTATE_SAMPLER_STATE_POINTERS_DS_PointertoDSSamplerState_bits 27 #define GFX8_3DSTATE_SAMPLER_STATE_POINTERS_DS_PointertoDSSamplerState_bits 27 #define GFX75_3DSTATE_SAMPLER_STATE_POINTERS_DS_PointertoDSSamplerState_bits 27 #define GFX7_3DSTATE_SAMPLER_STATE_POINTERS_DS_PointertoDSSamplerState_bits 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_DS_PointertoDSSamplerState_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLER_STATE_POINTERS_DS_PointertoDSSamplerState_start 37 #define GFX12_3DSTATE_SAMPLER_STATE_POINTERS_DS_PointertoDSSamplerState_start 37 #define GFX11_3DSTATE_SAMPLER_STATE_POINTERS_DS_PointertoDSSamplerState_start 37 #define GFX9_3DSTATE_SAMPLER_STATE_POINTERS_DS_PointertoDSSamplerState_start 37 #define GFX8_3DSTATE_SAMPLER_STATE_POINTERS_DS_PointertoDSSamplerState_start 37 #define GFX75_3DSTATE_SAMPLER_STATE_POINTERS_DS_PointertoDSSamplerState_start 37 #define GFX7_3DSTATE_SAMPLER_STATE_POINTERS_DS_PointertoDSSamplerState_start 37 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_DS_PointertoDSSamplerState_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 37; case 120: return 37; case 110: return 37; case 90: return 37; case 80: return 37; case 75: return 37; case 70: return 37; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLER_STATE_POINTERS_GS */ #define GFX125_3DSTATE_SAMPLER_STATE_POINTERS_GS_length 2 #define GFX12_3DSTATE_SAMPLER_STATE_POINTERS_GS_length 2 #define GFX11_3DSTATE_SAMPLER_STATE_POINTERS_GS_length 2 #define GFX9_3DSTATE_SAMPLER_STATE_POINTERS_GS_length 2 #define GFX8_3DSTATE_SAMPLER_STATE_POINTERS_GS_length 2 #define GFX75_3DSTATE_SAMPLER_STATE_POINTERS_GS_length 2 #define GFX7_3DSTATE_SAMPLER_STATE_POINTERS_GS_length 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_GS_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLER_STATE_POINTERS_GS::3D Command Opcode */ #define GFX125_3DSTATE_SAMPLER_STATE_POINTERS_GS_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_SAMPLER_STATE_POINTERS_GS_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_SAMPLER_STATE_POINTERS_GS_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_SAMPLER_STATE_POINTERS_GS_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_SAMPLER_STATE_POINTERS_GS_3DCommandOpcode_bits 3 #define GFX75_3DSTATE_SAMPLER_STATE_POINTERS_GS_3DCommandOpcode_bits 3 #define GFX7_3DSTATE_SAMPLER_STATE_POINTERS_GS_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_GS_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLER_STATE_POINTERS_GS_3DCommandOpcode_start 24 #define GFX12_3DSTATE_SAMPLER_STATE_POINTERS_GS_3DCommandOpcode_start 24 #define GFX11_3DSTATE_SAMPLER_STATE_POINTERS_GS_3DCommandOpcode_start 24 #define GFX9_3DSTATE_SAMPLER_STATE_POINTERS_GS_3DCommandOpcode_start 24 #define GFX8_3DSTATE_SAMPLER_STATE_POINTERS_GS_3DCommandOpcode_start 24 #define GFX75_3DSTATE_SAMPLER_STATE_POINTERS_GS_3DCommandOpcode_start 24 #define GFX7_3DSTATE_SAMPLER_STATE_POINTERS_GS_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_GS_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLER_STATE_POINTERS_GS::3D Command Sub Opcode */ #define GFX125_3DSTATE_SAMPLER_STATE_POINTERS_GS_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_SAMPLER_STATE_POINTERS_GS_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_SAMPLER_STATE_POINTERS_GS_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_SAMPLER_STATE_POINTERS_GS_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_SAMPLER_STATE_POINTERS_GS_3DCommandSubOpcode_bits 8 #define GFX75_3DSTATE_SAMPLER_STATE_POINTERS_GS_3DCommandSubOpcode_bits 8 #define GFX7_3DSTATE_SAMPLER_STATE_POINTERS_GS_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_GS_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLER_STATE_POINTERS_GS_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_SAMPLER_STATE_POINTERS_GS_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_SAMPLER_STATE_POINTERS_GS_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_SAMPLER_STATE_POINTERS_GS_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_SAMPLER_STATE_POINTERS_GS_3DCommandSubOpcode_start 16 #define GFX75_3DSTATE_SAMPLER_STATE_POINTERS_GS_3DCommandSubOpcode_start 16 #define GFX7_3DSTATE_SAMPLER_STATE_POINTERS_GS_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_GS_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLER_STATE_POINTERS_GS::Command SubType */ #define GFX125_3DSTATE_SAMPLER_STATE_POINTERS_GS_CommandSubType_bits 2 #define GFX12_3DSTATE_SAMPLER_STATE_POINTERS_GS_CommandSubType_bits 2 #define GFX11_3DSTATE_SAMPLER_STATE_POINTERS_GS_CommandSubType_bits 2 #define GFX9_3DSTATE_SAMPLER_STATE_POINTERS_GS_CommandSubType_bits 2 #define GFX8_3DSTATE_SAMPLER_STATE_POINTERS_GS_CommandSubType_bits 2 #define GFX75_3DSTATE_SAMPLER_STATE_POINTERS_GS_CommandSubType_bits 2 #define GFX7_3DSTATE_SAMPLER_STATE_POINTERS_GS_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_GS_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLER_STATE_POINTERS_GS_CommandSubType_start 27 #define GFX12_3DSTATE_SAMPLER_STATE_POINTERS_GS_CommandSubType_start 27 #define GFX11_3DSTATE_SAMPLER_STATE_POINTERS_GS_CommandSubType_start 27 #define GFX9_3DSTATE_SAMPLER_STATE_POINTERS_GS_CommandSubType_start 27 #define GFX8_3DSTATE_SAMPLER_STATE_POINTERS_GS_CommandSubType_start 27 #define GFX75_3DSTATE_SAMPLER_STATE_POINTERS_GS_CommandSubType_start 27 #define GFX7_3DSTATE_SAMPLER_STATE_POINTERS_GS_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_GS_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLER_STATE_POINTERS_GS::Command Type */ #define GFX125_3DSTATE_SAMPLER_STATE_POINTERS_GS_CommandType_bits 3 #define GFX12_3DSTATE_SAMPLER_STATE_POINTERS_GS_CommandType_bits 3 #define GFX11_3DSTATE_SAMPLER_STATE_POINTERS_GS_CommandType_bits 3 #define GFX9_3DSTATE_SAMPLER_STATE_POINTERS_GS_CommandType_bits 3 #define GFX8_3DSTATE_SAMPLER_STATE_POINTERS_GS_CommandType_bits 3 #define GFX75_3DSTATE_SAMPLER_STATE_POINTERS_GS_CommandType_bits 3 #define GFX7_3DSTATE_SAMPLER_STATE_POINTERS_GS_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_GS_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLER_STATE_POINTERS_GS_CommandType_start 29 #define GFX12_3DSTATE_SAMPLER_STATE_POINTERS_GS_CommandType_start 29 #define GFX11_3DSTATE_SAMPLER_STATE_POINTERS_GS_CommandType_start 29 #define GFX9_3DSTATE_SAMPLER_STATE_POINTERS_GS_CommandType_start 29 #define GFX8_3DSTATE_SAMPLER_STATE_POINTERS_GS_CommandType_start 29 #define GFX75_3DSTATE_SAMPLER_STATE_POINTERS_GS_CommandType_start 29 #define GFX7_3DSTATE_SAMPLER_STATE_POINTERS_GS_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_GS_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLER_STATE_POINTERS_GS::DWord Length */ #define GFX125_3DSTATE_SAMPLER_STATE_POINTERS_GS_DWordLength_bits 8 #define GFX12_3DSTATE_SAMPLER_STATE_POINTERS_GS_DWordLength_bits 8 #define GFX11_3DSTATE_SAMPLER_STATE_POINTERS_GS_DWordLength_bits 8 #define GFX9_3DSTATE_SAMPLER_STATE_POINTERS_GS_DWordLength_bits 8 #define GFX8_3DSTATE_SAMPLER_STATE_POINTERS_GS_DWordLength_bits 8 #define GFX75_3DSTATE_SAMPLER_STATE_POINTERS_GS_DWordLength_bits 8 #define GFX7_3DSTATE_SAMPLER_STATE_POINTERS_GS_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_GS_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLER_STATE_POINTERS_GS_DWordLength_start 0 #define GFX12_3DSTATE_SAMPLER_STATE_POINTERS_GS_DWordLength_start 0 #define GFX11_3DSTATE_SAMPLER_STATE_POINTERS_GS_DWordLength_start 0 #define GFX9_3DSTATE_SAMPLER_STATE_POINTERS_GS_DWordLength_start 0 #define GFX8_3DSTATE_SAMPLER_STATE_POINTERS_GS_DWordLength_start 0 #define GFX75_3DSTATE_SAMPLER_STATE_POINTERS_GS_DWordLength_start 0 #define GFX7_3DSTATE_SAMPLER_STATE_POINTERS_GS_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_GS_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLER_STATE_POINTERS_GS::Pointer to GS Sampler State */ #define GFX125_3DSTATE_SAMPLER_STATE_POINTERS_GS_PointertoGSSamplerState_bits 27 #define GFX12_3DSTATE_SAMPLER_STATE_POINTERS_GS_PointertoGSSamplerState_bits 27 #define GFX11_3DSTATE_SAMPLER_STATE_POINTERS_GS_PointertoGSSamplerState_bits 27 #define GFX9_3DSTATE_SAMPLER_STATE_POINTERS_GS_PointertoGSSamplerState_bits 27 #define GFX8_3DSTATE_SAMPLER_STATE_POINTERS_GS_PointertoGSSamplerState_bits 27 #define GFX75_3DSTATE_SAMPLER_STATE_POINTERS_GS_PointertoGSSamplerState_bits 27 #define GFX7_3DSTATE_SAMPLER_STATE_POINTERS_GS_PointertoGSSamplerState_bits 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_GS_PointertoGSSamplerState_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLER_STATE_POINTERS_GS_PointertoGSSamplerState_start 37 #define GFX12_3DSTATE_SAMPLER_STATE_POINTERS_GS_PointertoGSSamplerState_start 37 #define GFX11_3DSTATE_SAMPLER_STATE_POINTERS_GS_PointertoGSSamplerState_start 37 #define GFX9_3DSTATE_SAMPLER_STATE_POINTERS_GS_PointertoGSSamplerState_start 37 #define GFX8_3DSTATE_SAMPLER_STATE_POINTERS_GS_PointertoGSSamplerState_start 37 #define GFX75_3DSTATE_SAMPLER_STATE_POINTERS_GS_PointertoGSSamplerState_start 37 #define GFX7_3DSTATE_SAMPLER_STATE_POINTERS_GS_PointertoGSSamplerState_start 37 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_GS_PointertoGSSamplerState_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 37; case 120: return 37; case 110: return 37; case 90: return 37; case 80: return 37; case 75: return 37; case 70: return 37; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLER_STATE_POINTERS_HS */ #define GFX125_3DSTATE_SAMPLER_STATE_POINTERS_HS_length 2 #define GFX12_3DSTATE_SAMPLER_STATE_POINTERS_HS_length 2 #define GFX11_3DSTATE_SAMPLER_STATE_POINTERS_HS_length 2 #define GFX9_3DSTATE_SAMPLER_STATE_POINTERS_HS_length 2 #define GFX8_3DSTATE_SAMPLER_STATE_POINTERS_HS_length 2 #define GFX75_3DSTATE_SAMPLER_STATE_POINTERS_HS_length 2 #define GFX7_3DSTATE_SAMPLER_STATE_POINTERS_HS_length 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_HS_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLER_STATE_POINTERS_HS::3D Command Opcode */ #define GFX125_3DSTATE_SAMPLER_STATE_POINTERS_HS_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_SAMPLER_STATE_POINTERS_HS_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_SAMPLER_STATE_POINTERS_HS_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_SAMPLER_STATE_POINTERS_HS_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_SAMPLER_STATE_POINTERS_HS_3DCommandOpcode_bits 3 #define GFX75_3DSTATE_SAMPLER_STATE_POINTERS_HS_3DCommandOpcode_bits 3 #define GFX7_3DSTATE_SAMPLER_STATE_POINTERS_HS_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_HS_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLER_STATE_POINTERS_HS_3DCommandOpcode_start 24 #define GFX12_3DSTATE_SAMPLER_STATE_POINTERS_HS_3DCommandOpcode_start 24 #define GFX11_3DSTATE_SAMPLER_STATE_POINTERS_HS_3DCommandOpcode_start 24 #define GFX9_3DSTATE_SAMPLER_STATE_POINTERS_HS_3DCommandOpcode_start 24 #define GFX8_3DSTATE_SAMPLER_STATE_POINTERS_HS_3DCommandOpcode_start 24 #define GFX75_3DSTATE_SAMPLER_STATE_POINTERS_HS_3DCommandOpcode_start 24 #define GFX7_3DSTATE_SAMPLER_STATE_POINTERS_HS_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_HS_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLER_STATE_POINTERS_HS::3D Command Sub Opcode */ #define GFX125_3DSTATE_SAMPLER_STATE_POINTERS_HS_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_SAMPLER_STATE_POINTERS_HS_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_SAMPLER_STATE_POINTERS_HS_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_SAMPLER_STATE_POINTERS_HS_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_SAMPLER_STATE_POINTERS_HS_3DCommandSubOpcode_bits 8 #define GFX75_3DSTATE_SAMPLER_STATE_POINTERS_HS_3DCommandSubOpcode_bits 8 #define GFX7_3DSTATE_SAMPLER_STATE_POINTERS_HS_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_HS_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLER_STATE_POINTERS_HS_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_SAMPLER_STATE_POINTERS_HS_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_SAMPLER_STATE_POINTERS_HS_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_SAMPLER_STATE_POINTERS_HS_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_SAMPLER_STATE_POINTERS_HS_3DCommandSubOpcode_start 16 #define GFX75_3DSTATE_SAMPLER_STATE_POINTERS_HS_3DCommandSubOpcode_start 16 #define GFX7_3DSTATE_SAMPLER_STATE_POINTERS_HS_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_HS_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLER_STATE_POINTERS_HS::Command SubType */ #define GFX125_3DSTATE_SAMPLER_STATE_POINTERS_HS_CommandSubType_bits 2 #define GFX12_3DSTATE_SAMPLER_STATE_POINTERS_HS_CommandSubType_bits 2 #define GFX11_3DSTATE_SAMPLER_STATE_POINTERS_HS_CommandSubType_bits 2 #define GFX9_3DSTATE_SAMPLER_STATE_POINTERS_HS_CommandSubType_bits 2 #define GFX8_3DSTATE_SAMPLER_STATE_POINTERS_HS_CommandSubType_bits 2 #define GFX75_3DSTATE_SAMPLER_STATE_POINTERS_HS_CommandSubType_bits 2 #define GFX7_3DSTATE_SAMPLER_STATE_POINTERS_HS_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_HS_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLER_STATE_POINTERS_HS_CommandSubType_start 27 #define GFX12_3DSTATE_SAMPLER_STATE_POINTERS_HS_CommandSubType_start 27 #define GFX11_3DSTATE_SAMPLER_STATE_POINTERS_HS_CommandSubType_start 27 #define GFX9_3DSTATE_SAMPLER_STATE_POINTERS_HS_CommandSubType_start 27 #define GFX8_3DSTATE_SAMPLER_STATE_POINTERS_HS_CommandSubType_start 27 #define GFX75_3DSTATE_SAMPLER_STATE_POINTERS_HS_CommandSubType_start 27 #define GFX7_3DSTATE_SAMPLER_STATE_POINTERS_HS_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_HS_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLER_STATE_POINTERS_HS::Command Type */ #define GFX125_3DSTATE_SAMPLER_STATE_POINTERS_HS_CommandType_bits 3 #define GFX12_3DSTATE_SAMPLER_STATE_POINTERS_HS_CommandType_bits 3 #define GFX11_3DSTATE_SAMPLER_STATE_POINTERS_HS_CommandType_bits 3 #define GFX9_3DSTATE_SAMPLER_STATE_POINTERS_HS_CommandType_bits 3 #define GFX8_3DSTATE_SAMPLER_STATE_POINTERS_HS_CommandType_bits 3 #define GFX75_3DSTATE_SAMPLER_STATE_POINTERS_HS_CommandType_bits 3 #define GFX7_3DSTATE_SAMPLER_STATE_POINTERS_HS_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_HS_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLER_STATE_POINTERS_HS_CommandType_start 29 #define GFX12_3DSTATE_SAMPLER_STATE_POINTERS_HS_CommandType_start 29 #define GFX11_3DSTATE_SAMPLER_STATE_POINTERS_HS_CommandType_start 29 #define GFX9_3DSTATE_SAMPLER_STATE_POINTERS_HS_CommandType_start 29 #define GFX8_3DSTATE_SAMPLER_STATE_POINTERS_HS_CommandType_start 29 #define GFX75_3DSTATE_SAMPLER_STATE_POINTERS_HS_CommandType_start 29 #define GFX7_3DSTATE_SAMPLER_STATE_POINTERS_HS_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_HS_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLER_STATE_POINTERS_HS::DWord Length */ #define GFX125_3DSTATE_SAMPLER_STATE_POINTERS_HS_DWordLength_bits 8 #define GFX12_3DSTATE_SAMPLER_STATE_POINTERS_HS_DWordLength_bits 8 #define GFX11_3DSTATE_SAMPLER_STATE_POINTERS_HS_DWordLength_bits 8 #define GFX9_3DSTATE_SAMPLER_STATE_POINTERS_HS_DWordLength_bits 8 #define GFX8_3DSTATE_SAMPLER_STATE_POINTERS_HS_DWordLength_bits 8 #define GFX75_3DSTATE_SAMPLER_STATE_POINTERS_HS_DWordLength_bits 8 #define GFX7_3DSTATE_SAMPLER_STATE_POINTERS_HS_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_HS_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLER_STATE_POINTERS_HS_DWordLength_start 0 #define GFX12_3DSTATE_SAMPLER_STATE_POINTERS_HS_DWordLength_start 0 #define GFX11_3DSTATE_SAMPLER_STATE_POINTERS_HS_DWordLength_start 0 #define GFX9_3DSTATE_SAMPLER_STATE_POINTERS_HS_DWordLength_start 0 #define GFX8_3DSTATE_SAMPLER_STATE_POINTERS_HS_DWordLength_start 0 #define GFX75_3DSTATE_SAMPLER_STATE_POINTERS_HS_DWordLength_start 0 #define GFX7_3DSTATE_SAMPLER_STATE_POINTERS_HS_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_HS_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLER_STATE_POINTERS_HS::Pointer to HS Sampler State */ #define GFX125_3DSTATE_SAMPLER_STATE_POINTERS_HS_PointertoHSSamplerState_bits 27 #define GFX12_3DSTATE_SAMPLER_STATE_POINTERS_HS_PointertoHSSamplerState_bits 27 #define GFX11_3DSTATE_SAMPLER_STATE_POINTERS_HS_PointertoHSSamplerState_bits 27 #define GFX9_3DSTATE_SAMPLER_STATE_POINTERS_HS_PointertoHSSamplerState_bits 27 #define GFX8_3DSTATE_SAMPLER_STATE_POINTERS_HS_PointertoHSSamplerState_bits 27 #define GFX75_3DSTATE_SAMPLER_STATE_POINTERS_HS_PointertoHSSamplerState_bits 27 #define GFX7_3DSTATE_SAMPLER_STATE_POINTERS_HS_PointertoHSSamplerState_bits 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_HS_PointertoHSSamplerState_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLER_STATE_POINTERS_HS_PointertoHSSamplerState_start 37 #define GFX12_3DSTATE_SAMPLER_STATE_POINTERS_HS_PointertoHSSamplerState_start 37 #define GFX11_3DSTATE_SAMPLER_STATE_POINTERS_HS_PointertoHSSamplerState_start 37 #define GFX9_3DSTATE_SAMPLER_STATE_POINTERS_HS_PointertoHSSamplerState_start 37 #define GFX8_3DSTATE_SAMPLER_STATE_POINTERS_HS_PointertoHSSamplerState_start 37 #define GFX75_3DSTATE_SAMPLER_STATE_POINTERS_HS_PointertoHSSamplerState_start 37 #define GFX7_3DSTATE_SAMPLER_STATE_POINTERS_HS_PointertoHSSamplerState_start 37 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_HS_PointertoHSSamplerState_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 37; case 120: return 37; case 110: return 37; case 90: return 37; case 80: return 37; case 75: return 37; case 70: return 37; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLER_STATE_POINTERS_PS */ #define GFX125_3DSTATE_SAMPLER_STATE_POINTERS_PS_length 2 #define GFX12_3DSTATE_SAMPLER_STATE_POINTERS_PS_length 2 #define GFX11_3DSTATE_SAMPLER_STATE_POINTERS_PS_length 2 #define GFX9_3DSTATE_SAMPLER_STATE_POINTERS_PS_length 2 #define GFX8_3DSTATE_SAMPLER_STATE_POINTERS_PS_length 2 #define GFX75_3DSTATE_SAMPLER_STATE_POINTERS_PS_length 2 #define GFX7_3DSTATE_SAMPLER_STATE_POINTERS_PS_length 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_PS_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLER_STATE_POINTERS_PS::3D Command Opcode */ #define GFX125_3DSTATE_SAMPLER_STATE_POINTERS_PS_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_SAMPLER_STATE_POINTERS_PS_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_SAMPLER_STATE_POINTERS_PS_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_SAMPLER_STATE_POINTERS_PS_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_SAMPLER_STATE_POINTERS_PS_3DCommandOpcode_bits 3 #define GFX75_3DSTATE_SAMPLER_STATE_POINTERS_PS_3DCommandOpcode_bits 3 #define GFX7_3DSTATE_SAMPLER_STATE_POINTERS_PS_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_PS_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLER_STATE_POINTERS_PS_3DCommandOpcode_start 24 #define GFX12_3DSTATE_SAMPLER_STATE_POINTERS_PS_3DCommandOpcode_start 24 #define GFX11_3DSTATE_SAMPLER_STATE_POINTERS_PS_3DCommandOpcode_start 24 #define GFX9_3DSTATE_SAMPLER_STATE_POINTERS_PS_3DCommandOpcode_start 24 #define GFX8_3DSTATE_SAMPLER_STATE_POINTERS_PS_3DCommandOpcode_start 24 #define GFX75_3DSTATE_SAMPLER_STATE_POINTERS_PS_3DCommandOpcode_start 24 #define GFX7_3DSTATE_SAMPLER_STATE_POINTERS_PS_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_PS_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLER_STATE_POINTERS_PS::3D Command Sub Opcode */ #define GFX125_3DSTATE_SAMPLER_STATE_POINTERS_PS_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_SAMPLER_STATE_POINTERS_PS_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_SAMPLER_STATE_POINTERS_PS_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_SAMPLER_STATE_POINTERS_PS_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_SAMPLER_STATE_POINTERS_PS_3DCommandSubOpcode_bits 8 #define GFX75_3DSTATE_SAMPLER_STATE_POINTERS_PS_3DCommandSubOpcode_bits 8 #define GFX7_3DSTATE_SAMPLER_STATE_POINTERS_PS_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_PS_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLER_STATE_POINTERS_PS_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_SAMPLER_STATE_POINTERS_PS_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_SAMPLER_STATE_POINTERS_PS_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_SAMPLER_STATE_POINTERS_PS_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_SAMPLER_STATE_POINTERS_PS_3DCommandSubOpcode_start 16 #define GFX75_3DSTATE_SAMPLER_STATE_POINTERS_PS_3DCommandSubOpcode_start 16 #define GFX7_3DSTATE_SAMPLER_STATE_POINTERS_PS_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_PS_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLER_STATE_POINTERS_PS::Command SubType */ #define GFX125_3DSTATE_SAMPLER_STATE_POINTERS_PS_CommandSubType_bits 2 #define GFX12_3DSTATE_SAMPLER_STATE_POINTERS_PS_CommandSubType_bits 2 #define GFX11_3DSTATE_SAMPLER_STATE_POINTERS_PS_CommandSubType_bits 2 #define GFX9_3DSTATE_SAMPLER_STATE_POINTERS_PS_CommandSubType_bits 2 #define GFX8_3DSTATE_SAMPLER_STATE_POINTERS_PS_CommandSubType_bits 2 #define GFX75_3DSTATE_SAMPLER_STATE_POINTERS_PS_CommandSubType_bits 2 #define GFX7_3DSTATE_SAMPLER_STATE_POINTERS_PS_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_PS_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLER_STATE_POINTERS_PS_CommandSubType_start 27 #define GFX12_3DSTATE_SAMPLER_STATE_POINTERS_PS_CommandSubType_start 27 #define GFX11_3DSTATE_SAMPLER_STATE_POINTERS_PS_CommandSubType_start 27 #define GFX9_3DSTATE_SAMPLER_STATE_POINTERS_PS_CommandSubType_start 27 #define GFX8_3DSTATE_SAMPLER_STATE_POINTERS_PS_CommandSubType_start 27 #define GFX75_3DSTATE_SAMPLER_STATE_POINTERS_PS_CommandSubType_start 27 #define GFX7_3DSTATE_SAMPLER_STATE_POINTERS_PS_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_PS_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLER_STATE_POINTERS_PS::Command Type */ #define GFX125_3DSTATE_SAMPLER_STATE_POINTERS_PS_CommandType_bits 3 #define GFX12_3DSTATE_SAMPLER_STATE_POINTERS_PS_CommandType_bits 3 #define GFX11_3DSTATE_SAMPLER_STATE_POINTERS_PS_CommandType_bits 3 #define GFX9_3DSTATE_SAMPLER_STATE_POINTERS_PS_CommandType_bits 3 #define GFX8_3DSTATE_SAMPLER_STATE_POINTERS_PS_CommandType_bits 3 #define GFX75_3DSTATE_SAMPLER_STATE_POINTERS_PS_CommandType_bits 3 #define GFX7_3DSTATE_SAMPLER_STATE_POINTERS_PS_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_PS_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLER_STATE_POINTERS_PS_CommandType_start 29 #define GFX12_3DSTATE_SAMPLER_STATE_POINTERS_PS_CommandType_start 29 #define GFX11_3DSTATE_SAMPLER_STATE_POINTERS_PS_CommandType_start 29 #define GFX9_3DSTATE_SAMPLER_STATE_POINTERS_PS_CommandType_start 29 #define GFX8_3DSTATE_SAMPLER_STATE_POINTERS_PS_CommandType_start 29 #define GFX75_3DSTATE_SAMPLER_STATE_POINTERS_PS_CommandType_start 29 #define GFX7_3DSTATE_SAMPLER_STATE_POINTERS_PS_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_PS_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLER_STATE_POINTERS_PS::DWord Length */ #define GFX125_3DSTATE_SAMPLER_STATE_POINTERS_PS_DWordLength_bits 8 #define GFX12_3DSTATE_SAMPLER_STATE_POINTERS_PS_DWordLength_bits 8 #define GFX11_3DSTATE_SAMPLER_STATE_POINTERS_PS_DWordLength_bits 8 #define GFX9_3DSTATE_SAMPLER_STATE_POINTERS_PS_DWordLength_bits 8 #define GFX8_3DSTATE_SAMPLER_STATE_POINTERS_PS_DWordLength_bits 8 #define GFX75_3DSTATE_SAMPLER_STATE_POINTERS_PS_DWordLength_bits 8 #define GFX7_3DSTATE_SAMPLER_STATE_POINTERS_PS_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_PS_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLER_STATE_POINTERS_PS_DWordLength_start 0 #define GFX12_3DSTATE_SAMPLER_STATE_POINTERS_PS_DWordLength_start 0 #define GFX11_3DSTATE_SAMPLER_STATE_POINTERS_PS_DWordLength_start 0 #define GFX9_3DSTATE_SAMPLER_STATE_POINTERS_PS_DWordLength_start 0 #define GFX8_3DSTATE_SAMPLER_STATE_POINTERS_PS_DWordLength_start 0 #define GFX75_3DSTATE_SAMPLER_STATE_POINTERS_PS_DWordLength_start 0 #define GFX7_3DSTATE_SAMPLER_STATE_POINTERS_PS_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_PS_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLER_STATE_POINTERS_PS::Pointer to PS Sampler State */ #define GFX125_3DSTATE_SAMPLER_STATE_POINTERS_PS_PointertoPSSamplerState_bits 27 #define GFX12_3DSTATE_SAMPLER_STATE_POINTERS_PS_PointertoPSSamplerState_bits 27 #define GFX11_3DSTATE_SAMPLER_STATE_POINTERS_PS_PointertoPSSamplerState_bits 27 #define GFX9_3DSTATE_SAMPLER_STATE_POINTERS_PS_PointertoPSSamplerState_bits 27 #define GFX8_3DSTATE_SAMPLER_STATE_POINTERS_PS_PointertoPSSamplerState_bits 27 #define GFX75_3DSTATE_SAMPLER_STATE_POINTERS_PS_PointertoPSSamplerState_bits 27 #define GFX7_3DSTATE_SAMPLER_STATE_POINTERS_PS_PointertoPSSamplerState_bits 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_PS_PointertoPSSamplerState_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLER_STATE_POINTERS_PS_PointertoPSSamplerState_start 37 #define GFX12_3DSTATE_SAMPLER_STATE_POINTERS_PS_PointertoPSSamplerState_start 37 #define GFX11_3DSTATE_SAMPLER_STATE_POINTERS_PS_PointertoPSSamplerState_start 37 #define GFX9_3DSTATE_SAMPLER_STATE_POINTERS_PS_PointertoPSSamplerState_start 37 #define GFX8_3DSTATE_SAMPLER_STATE_POINTERS_PS_PointertoPSSamplerState_start 37 #define GFX75_3DSTATE_SAMPLER_STATE_POINTERS_PS_PointertoPSSamplerState_start 37 #define GFX7_3DSTATE_SAMPLER_STATE_POINTERS_PS_PointertoPSSamplerState_start 37 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_PS_PointertoPSSamplerState_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 37; case 120: return 37; case 110: return 37; case 90: return 37; case 80: return 37; case 75: return 37; case 70: return 37; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLER_STATE_POINTERS_VS */ #define GFX125_3DSTATE_SAMPLER_STATE_POINTERS_VS_length 2 #define GFX12_3DSTATE_SAMPLER_STATE_POINTERS_VS_length 2 #define GFX11_3DSTATE_SAMPLER_STATE_POINTERS_VS_length 2 #define GFX9_3DSTATE_SAMPLER_STATE_POINTERS_VS_length 2 #define GFX8_3DSTATE_SAMPLER_STATE_POINTERS_VS_length 2 #define GFX75_3DSTATE_SAMPLER_STATE_POINTERS_VS_length 2 #define GFX7_3DSTATE_SAMPLER_STATE_POINTERS_VS_length 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_VS_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLER_STATE_POINTERS_VS::3D Command Opcode */ #define GFX125_3DSTATE_SAMPLER_STATE_POINTERS_VS_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_SAMPLER_STATE_POINTERS_VS_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_SAMPLER_STATE_POINTERS_VS_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_SAMPLER_STATE_POINTERS_VS_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_SAMPLER_STATE_POINTERS_VS_3DCommandOpcode_bits 3 #define GFX75_3DSTATE_SAMPLER_STATE_POINTERS_VS_3DCommandOpcode_bits 3 #define GFX7_3DSTATE_SAMPLER_STATE_POINTERS_VS_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_VS_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLER_STATE_POINTERS_VS_3DCommandOpcode_start 24 #define GFX12_3DSTATE_SAMPLER_STATE_POINTERS_VS_3DCommandOpcode_start 24 #define GFX11_3DSTATE_SAMPLER_STATE_POINTERS_VS_3DCommandOpcode_start 24 #define GFX9_3DSTATE_SAMPLER_STATE_POINTERS_VS_3DCommandOpcode_start 24 #define GFX8_3DSTATE_SAMPLER_STATE_POINTERS_VS_3DCommandOpcode_start 24 #define GFX75_3DSTATE_SAMPLER_STATE_POINTERS_VS_3DCommandOpcode_start 24 #define GFX7_3DSTATE_SAMPLER_STATE_POINTERS_VS_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_VS_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLER_STATE_POINTERS_VS::3D Command Sub Opcode */ #define GFX125_3DSTATE_SAMPLER_STATE_POINTERS_VS_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_SAMPLER_STATE_POINTERS_VS_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_SAMPLER_STATE_POINTERS_VS_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_SAMPLER_STATE_POINTERS_VS_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_SAMPLER_STATE_POINTERS_VS_3DCommandSubOpcode_bits 8 #define GFX75_3DSTATE_SAMPLER_STATE_POINTERS_VS_3DCommandSubOpcode_bits 8 #define GFX7_3DSTATE_SAMPLER_STATE_POINTERS_VS_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_VS_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLER_STATE_POINTERS_VS_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_SAMPLER_STATE_POINTERS_VS_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_SAMPLER_STATE_POINTERS_VS_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_SAMPLER_STATE_POINTERS_VS_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_SAMPLER_STATE_POINTERS_VS_3DCommandSubOpcode_start 16 #define GFX75_3DSTATE_SAMPLER_STATE_POINTERS_VS_3DCommandSubOpcode_start 16 #define GFX7_3DSTATE_SAMPLER_STATE_POINTERS_VS_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_VS_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLER_STATE_POINTERS_VS::Command SubType */ #define GFX125_3DSTATE_SAMPLER_STATE_POINTERS_VS_CommandSubType_bits 2 #define GFX12_3DSTATE_SAMPLER_STATE_POINTERS_VS_CommandSubType_bits 2 #define GFX11_3DSTATE_SAMPLER_STATE_POINTERS_VS_CommandSubType_bits 2 #define GFX9_3DSTATE_SAMPLER_STATE_POINTERS_VS_CommandSubType_bits 2 #define GFX8_3DSTATE_SAMPLER_STATE_POINTERS_VS_CommandSubType_bits 2 #define GFX75_3DSTATE_SAMPLER_STATE_POINTERS_VS_CommandSubType_bits 2 #define GFX7_3DSTATE_SAMPLER_STATE_POINTERS_VS_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_VS_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLER_STATE_POINTERS_VS_CommandSubType_start 27 #define GFX12_3DSTATE_SAMPLER_STATE_POINTERS_VS_CommandSubType_start 27 #define GFX11_3DSTATE_SAMPLER_STATE_POINTERS_VS_CommandSubType_start 27 #define GFX9_3DSTATE_SAMPLER_STATE_POINTERS_VS_CommandSubType_start 27 #define GFX8_3DSTATE_SAMPLER_STATE_POINTERS_VS_CommandSubType_start 27 #define GFX75_3DSTATE_SAMPLER_STATE_POINTERS_VS_CommandSubType_start 27 #define GFX7_3DSTATE_SAMPLER_STATE_POINTERS_VS_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_VS_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLER_STATE_POINTERS_VS::Command Type */ #define GFX125_3DSTATE_SAMPLER_STATE_POINTERS_VS_CommandType_bits 3 #define GFX12_3DSTATE_SAMPLER_STATE_POINTERS_VS_CommandType_bits 3 #define GFX11_3DSTATE_SAMPLER_STATE_POINTERS_VS_CommandType_bits 3 #define GFX9_3DSTATE_SAMPLER_STATE_POINTERS_VS_CommandType_bits 3 #define GFX8_3DSTATE_SAMPLER_STATE_POINTERS_VS_CommandType_bits 3 #define GFX75_3DSTATE_SAMPLER_STATE_POINTERS_VS_CommandType_bits 3 #define GFX7_3DSTATE_SAMPLER_STATE_POINTERS_VS_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_VS_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLER_STATE_POINTERS_VS_CommandType_start 29 #define GFX12_3DSTATE_SAMPLER_STATE_POINTERS_VS_CommandType_start 29 #define GFX11_3DSTATE_SAMPLER_STATE_POINTERS_VS_CommandType_start 29 #define GFX9_3DSTATE_SAMPLER_STATE_POINTERS_VS_CommandType_start 29 #define GFX8_3DSTATE_SAMPLER_STATE_POINTERS_VS_CommandType_start 29 #define GFX75_3DSTATE_SAMPLER_STATE_POINTERS_VS_CommandType_start 29 #define GFX7_3DSTATE_SAMPLER_STATE_POINTERS_VS_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_VS_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLER_STATE_POINTERS_VS::DWord Length */ #define GFX125_3DSTATE_SAMPLER_STATE_POINTERS_VS_DWordLength_bits 8 #define GFX12_3DSTATE_SAMPLER_STATE_POINTERS_VS_DWordLength_bits 8 #define GFX11_3DSTATE_SAMPLER_STATE_POINTERS_VS_DWordLength_bits 8 #define GFX9_3DSTATE_SAMPLER_STATE_POINTERS_VS_DWordLength_bits 8 #define GFX8_3DSTATE_SAMPLER_STATE_POINTERS_VS_DWordLength_bits 8 #define GFX75_3DSTATE_SAMPLER_STATE_POINTERS_VS_DWordLength_bits 8 #define GFX7_3DSTATE_SAMPLER_STATE_POINTERS_VS_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_VS_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLER_STATE_POINTERS_VS_DWordLength_start 0 #define GFX12_3DSTATE_SAMPLER_STATE_POINTERS_VS_DWordLength_start 0 #define GFX11_3DSTATE_SAMPLER_STATE_POINTERS_VS_DWordLength_start 0 #define GFX9_3DSTATE_SAMPLER_STATE_POINTERS_VS_DWordLength_start 0 #define GFX8_3DSTATE_SAMPLER_STATE_POINTERS_VS_DWordLength_start 0 #define GFX75_3DSTATE_SAMPLER_STATE_POINTERS_VS_DWordLength_start 0 #define GFX7_3DSTATE_SAMPLER_STATE_POINTERS_VS_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_VS_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLER_STATE_POINTERS_VS::Pointer to VS Sampler State */ #define GFX125_3DSTATE_SAMPLER_STATE_POINTERS_VS_PointertoVSSamplerState_bits 27 #define GFX12_3DSTATE_SAMPLER_STATE_POINTERS_VS_PointertoVSSamplerState_bits 27 #define GFX11_3DSTATE_SAMPLER_STATE_POINTERS_VS_PointertoVSSamplerState_bits 27 #define GFX9_3DSTATE_SAMPLER_STATE_POINTERS_VS_PointertoVSSamplerState_bits 27 #define GFX8_3DSTATE_SAMPLER_STATE_POINTERS_VS_PointertoVSSamplerState_bits 27 #define GFX75_3DSTATE_SAMPLER_STATE_POINTERS_VS_PointertoVSSamplerState_bits 27 #define GFX7_3DSTATE_SAMPLER_STATE_POINTERS_VS_PointertoVSSamplerState_bits 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_VS_PointertoVSSamplerState_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLER_STATE_POINTERS_VS_PointertoVSSamplerState_start 37 #define GFX12_3DSTATE_SAMPLER_STATE_POINTERS_VS_PointertoVSSamplerState_start 37 #define GFX11_3DSTATE_SAMPLER_STATE_POINTERS_VS_PointertoVSSamplerState_start 37 #define GFX9_3DSTATE_SAMPLER_STATE_POINTERS_VS_PointertoVSSamplerState_start 37 #define GFX8_3DSTATE_SAMPLER_STATE_POINTERS_VS_PointertoVSSamplerState_start 37 #define GFX75_3DSTATE_SAMPLER_STATE_POINTERS_VS_PointertoVSSamplerState_start 37 #define GFX7_3DSTATE_SAMPLER_STATE_POINTERS_VS_PointertoVSSamplerState_start 37 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLER_STATE_POINTERS_VS_PointertoVSSamplerState_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 37; case 120: return 37; case 110: return 37; case 90: return 37; case 80: return 37; case 75: return 37; case 70: return 37; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLE_MASK */ #define GFX125_3DSTATE_SAMPLE_MASK_length 2 #define GFX12_3DSTATE_SAMPLE_MASK_length 2 #define GFX11_3DSTATE_SAMPLE_MASK_length 2 #define GFX9_3DSTATE_SAMPLE_MASK_length 2 #define GFX8_3DSTATE_SAMPLE_MASK_length 2 #define GFX75_3DSTATE_SAMPLE_MASK_length 2 #define GFX7_3DSTATE_SAMPLE_MASK_length 2 #define GFX6_3DSTATE_SAMPLE_MASK_length 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_MASK_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLE_MASK::3D Command Opcode */ #define GFX125_3DSTATE_SAMPLE_MASK_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_SAMPLE_MASK_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_SAMPLE_MASK_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_SAMPLE_MASK_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_SAMPLE_MASK_3DCommandOpcode_bits 3 #define GFX75_3DSTATE_SAMPLE_MASK_3DCommandOpcode_bits 3 #define GFX7_3DSTATE_SAMPLE_MASK_3DCommandOpcode_bits 3 #define GFX6_3DSTATE_SAMPLE_MASK_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_MASK_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLE_MASK_3DCommandOpcode_start 24 #define GFX12_3DSTATE_SAMPLE_MASK_3DCommandOpcode_start 24 #define GFX11_3DSTATE_SAMPLE_MASK_3DCommandOpcode_start 24 #define GFX9_3DSTATE_SAMPLE_MASK_3DCommandOpcode_start 24 #define GFX8_3DSTATE_SAMPLE_MASK_3DCommandOpcode_start 24 #define GFX75_3DSTATE_SAMPLE_MASK_3DCommandOpcode_start 24 #define GFX7_3DSTATE_SAMPLE_MASK_3DCommandOpcode_start 24 #define GFX6_3DSTATE_SAMPLE_MASK_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_MASK_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 24; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLE_MASK::3D Command Sub Opcode */ #define GFX125_3DSTATE_SAMPLE_MASK_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_SAMPLE_MASK_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_SAMPLE_MASK_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_SAMPLE_MASK_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_SAMPLE_MASK_3DCommandSubOpcode_bits 8 #define GFX75_3DSTATE_SAMPLE_MASK_3DCommandSubOpcode_bits 8 #define GFX7_3DSTATE_SAMPLE_MASK_3DCommandSubOpcode_bits 8 #define GFX6_3DSTATE_SAMPLE_MASK_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_MASK_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLE_MASK_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_SAMPLE_MASK_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_SAMPLE_MASK_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_SAMPLE_MASK_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_SAMPLE_MASK_3DCommandSubOpcode_start 16 #define GFX75_3DSTATE_SAMPLE_MASK_3DCommandSubOpcode_start 16 #define GFX7_3DSTATE_SAMPLE_MASK_3DCommandSubOpcode_start 16 #define GFX6_3DSTATE_SAMPLE_MASK_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_MASK_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 16; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLE_MASK::Command SubType */ #define GFX125_3DSTATE_SAMPLE_MASK_CommandSubType_bits 2 #define GFX12_3DSTATE_SAMPLE_MASK_CommandSubType_bits 2 #define GFX11_3DSTATE_SAMPLE_MASK_CommandSubType_bits 2 #define GFX9_3DSTATE_SAMPLE_MASK_CommandSubType_bits 2 #define GFX8_3DSTATE_SAMPLE_MASK_CommandSubType_bits 2 #define GFX75_3DSTATE_SAMPLE_MASK_CommandSubType_bits 2 #define GFX7_3DSTATE_SAMPLE_MASK_CommandSubType_bits 2 #define GFX6_3DSTATE_SAMPLE_MASK_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_MASK_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLE_MASK_CommandSubType_start 27 #define GFX12_3DSTATE_SAMPLE_MASK_CommandSubType_start 27 #define GFX11_3DSTATE_SAMPLE_MASK_CommandSubType_start 27 #define GFX9_3DSTATE_SAMPLE_MASK_CommandSubType_start 27 #define GFX8_3DSTATE_SAMPLE_MASK_CommandSubType_start 27 #define GFX75_3DSTATE_SAMPLE_MASK_CommandSubType_start 27 #define GFX7_3DSTATE_SAMPLE_MASK_CommandSubType_start 27 #define GFX6_3DSTATE_SAMPLE_MASK_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_MASK_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 27; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLE_MASK::Command Type */ #define GFX125_3DSTATE_SAMPLE_MASK_CommandType_bits 3 #define GFX12_3DSTATE_SAMPLE_MASK_CommandType_bits 3 #define GFX11_3DSTATE_SAMPLE_MASK_CommandType_bits 3 #define GFX9_3DSTATE_SAMPLE_MASK_CommandType_bits 3 #define GFX8_3DSTATE_SAMPLE_MASK_CommandType_bits 3 #define GFX75_3DSTATE_SAMPLE_MASK_CommandType_bits 3 #define GFX7_3DSTATE_SAMPLE_MASK_CommandType_bits 3 #define GFX6_3DSTATE_SAMPLE_MASK_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_MASK_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLE_MASK_CommandType_start 29 #define GFX12_3DSTATE_SAMPLE_MASK_CommandType_start 29 #define GFX11_3DSTATE_SAMPLE_MASK_CommandType_start 29 #define GFX9_3DSTATE_SAMPLE_MASK_CommandType_start 29 #define GFX8_3DSTATE_SAMPLE_MASK_CommandType_start 29 #define GFX75_3DSTATE_SAMPLE_MASK_CommandType_start 29 #define GFX7_3DSTATE_SAMPLE_MASK_CommandType_start 29 #define GFX6_3DSTATE_SAMPLE_MASK_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_MASK_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 29; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLE_MASK::DWord Length */ #define GFX125_3DSTATE_SAMPLE_MASK_DWordLength_bits 8 #define GFX12_3DSTATE_SAMPLE_MASK_DWordLength_bits 8 #define GFX11_3DSTATE_SAMPLE_MASK_DWordLength_bits 8 #define GFX9_3DSTATE_SAMPLE_MASK_DWordLength_bits 8 #define GFX8_3DSTATE_SAMPLE_MASK_DWordLength_bits 8 #define GFX75_3DSTATE_SAMPLE_MASK_DWordLength_bits 8 #define GFX7_3DSTATE_SAMPLE_MASK_DWordLength_bits 8 #define GFX6_3DSTATE_SAMPLE_MASK_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_MASK_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLE_MASK_DWordLength_start 0 #define GFX12_3DSTATE_SAMPLE_MASK_DWordLength_start 0 #define GFX11_3DSTATE_SAMPLE_MASK_DWordLength_start 0 #define GFX9_3DSTATE_SAMPLE_MASK_DWordLength_start 0 #define GFX8_3DSTATE_SAMPLE_MASK_DWordLength_start 0 #define GFX75_3DSTATE_SAMPLE_MASK_DWordLength_start 0 #define GFX7_3DSTATE_SAMPLE_MASK_DWordLength_start 0 #define GFX6_3DSTATE_SAMPLE_MASK_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_MASK_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLE_MASK::Sample Mask */ #define GFX125_3DSTATE_SAMPLE_MASK_SampleMask_bits 16 #define GFX12_3DSTATE_SAMPLE_MASK_SampleMask_bits 16 #define GFX11_3DSTATE_SAMPLE_MASK_SampleMask_bits 16 #define GFX9_3DSTATE_SAMPLE_MASK_SampleMask_bits 16 #define GFX8_3DSTATE_SAMPLE_MASK_SampleMask_bits 16 #define GFX75_3DSTATE_SAMPLE_MASK_SampleMask_bits 8 #define GFX7_3DSTATE_SAMPLE_MASK_SampleMask_bits 8 #define GFX6_3DSTATE_SAMPLE_MASK_SampleMask_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_MASK_SampleMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 8; case 70: return 8; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLE_MASK_SampleMask_start 32 #define GFX12_3DSTATE_SAMPLE_MASK_SampleMask_start 32 #define GFX11_3DSTATE_SAMPLE_MASK_SampleMask_start 32 #define GFX9_3DSTATE_SAMPLE_MASK_SampleMask_start 32 #define GFX8_3DSTATE_SAMPLE_MASK_SampleMask_start 32 #define GFX75_3DSTATE_SAMPLE_MASK_SampleMask_start 32 #define GFX7_3DSTATE_SAMPLE_MASK_SampleMask_start 32 #define GFX6_3DSTATE_SAMPLE_MASK_SampleMask_start 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_MASK_SampleMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 32; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLE_PATTERN */ #define GFX125_3DSTATE_SAMPLE_PATTERN_length 9 #define GFX12_3DSTATE_SAMPLE_PATTERN_length 9 #define GFX11_3DSTATE_SAMPLE_PATTERN_length 9 #define GFX9_3DSTATE_SAMPLE_PATTERN_length 9 #define GFX8_3DSTATE_SAMPLE_PATTERN_length 9 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 9; case 120: return 9; case 110: return 9; case 90: return 9; case 80: return 9; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLE_PATTERN::16x Sample0 X Offset */ #define GFX125_3DSTATE_SAMPLE_PATTERN_16xSample0XOffset_bits 4 #define GFX12_3DSTATE_SAMPLE_PATTERN_16xSample0XOffset_bits 4 #define GFX11_3DSTATE_SAMPLE_PATTERN_16xSample0XOffset_bits 4 #define GFX9_3DSTATE_SAMPLE_PATTERN_16xSample0XOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_16xSample0XOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLE_PATTERN_16xSample0XOffset_start 36 #define GFX12_3DSTATE_SAMPLE_PATTERN_16xSample0XOffset_start 36 #define GFX11_3DSTATE_SAMPLE_PATTERN_16xSample0XOffset_start 36 #define GFX9_3DSTATE_SAMPLE_PATTERN_16xSample0XOffset_start 36 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_16xSample0XOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 36; case 120: return 36; case 110: return 36; case 90: return 36; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLE_PATTERN::16x Sample0 Y Offset */ #define GFX125_3DSTATE_SAMPLE_PATTERN_16xSample0YOffset_bits 4 #define GFX12_3DSTATE_SAMPLE_PATTERN_16xSample0YOffset_bits 4 #define GFX11_3DSTATE_SAMPLE_PATTERN_16xSample0YOffset_bits 4 #define GFX9_3DSTATE_SAMPLE_PATTERN_16xSample0YOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_16xSample0YOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLE_PATTERN_16xSample0YOffset_start 32 #define GFX12_3DSTATE_SAMPLE_PATTERN_16xSample0YOffset_start 32 #define GFX11_3DSTATE_SAMPLE_PATTERN_16xSample0YOffset_start 32 #define GFX9_3DSTATE_SAMPLE_PATTERN_16xSample0YOffset_start 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_16xSample0YOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLE_PATTERN::16x Sample10 X Offset */ #define GFX125_3DSTATE_SAMPLE_PATTERN_16xSample10XOffset_bits 4 #define GFX12_3DSTATE_SAMPLE_PATTERN_16xSample10XOffset_bits 4 #define GFX11_3DSTATE_SAMPLE_PATTERN_16xSample10XOffset_bits 4 #define GFX9_3DSTATE_SAMPLE_PATTERN_16xSample10XOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_16xSample10XOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLE_PATTERN_16xSample10XOffset_start 116 #define GFX12_3DSTATE_SAMPLE_PATTERN_16xSample10XOffset_start 116 #define GFX11_3DSTATE_SAMPLE_PATTERN_16xSample10XOffset_start 116 #define GFX9_3DSTATE_SAMPLE_PATTERN_16xSample10XOffset_start 116 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_16xSample10XOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 116; case 120: return 116; case 110: return 116; case 90: return 116; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLE_PATTERN::16x Sample10 Y Offset */ #define GFX125_3DSTATE_SAMPLE_PATTERN_16xSample10YOffset_bits 4 #define GFX12_3DSTATE_SAMPLE_PATTERN_16xSample10YOffset_bits 4 #define GFX11_3DSTATE_SAMPLE_PATTERN_16xSample10YOffset_bits 4 #define GFX9_3DSTATE_SAMPLE_PATTERN_16xSample10YOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_16xSample10YOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLE_PATTERN_16xSample10YOffset_start 112 #define GFX12_3DSTATE_SAMPLE_PATTERN_16xSample10YOffset_start 112 #define GFX11_3DSTATE_SAMPLE_PATTERN_16xSample10YOffset_start 112 #define GFX9_3DSTATE_SAMPLE_PATTERN_16xSample10YOffset_start 112 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_16xSample10YOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 112; case 120: return 112; case 110: return 112; case 90: return 112; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLE_PATTERN::16x Sample11 X Offset */ #define GFX125_3DSTATE_SAMPLE_PATTERN_16xSample11XOffset_bits 4 #define GFX12_3DSTATE_SAMPLE_PATTERN_16xSample11XOffset_bits 4 #define GFX11_3DSTATE_SAMPLE_PATTERN_16xSample11XOffset_bits 4 #define GFX9_3DSTATE_SAMPLE_PATTERN_16xSample11XOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_16xSample11XOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLE_PATTERN_16xSample11XOffset_start 124 #define GFX12_3DSTATE_SAMPLE_PATTERN_16xSample11XOffset_start 124 #define GFX11_3DSTATE_SAMPLE_PATTERN_16xSample11XOffset_start 124 #define GFX9_3DSTATE_SAMPLE_PATTERN_16xSample11XOffset_start 124 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_16xSample11XOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 124; case 120: return 124; case 110: return 124; case 90: return 124; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLE_PATTERN::16x Sample11 Y Offset */ #define GFX125_3DSTATE_SAMPLE_PATTERN_16xSample11YOffset_bits 4 #define GFX12_3DSTATE_SAMPLE_PATTERN_16xSample11YOffset_bits 4 #define GFX11_3DSTATE_SAMPLE_PATTERN_16xSample11YOffset_bits 4 #define GFX9_3DSTATE_SAMPLE_PATTERN_16xSample11YOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_16xSample11YOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLE_PATTERN_16xSample11YOffset_start 120 #define GFX12_3DSTATE_SAMPLE_PATTERN_16xSample11YOffset_start 120 #define GFX11_3DSTATE_SAMPLE_PATTERN_16xSample11YOffset_start 120 #define GFX9_3DSTATE_SAMPLE_PATTERN_16xSample11YOffset_start 120 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_16xSample11YOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 120; case 120: return 120; case 110: return 120; case 90: return 120; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLE_PATTERN::16x Sample12 X Offset */ #define GFX125_3DSTATE_SAMPLE_PATTERN_16xSample12XOffset_bits 4 #define GFX12_3DSTATE_SAMPLE_PATTERN_16xSample12XOffset_bits 4 #define GFX11_3DSTATE_SAMPLE_PATTERN_16xSample12XOffset_bits 4 #define GFX9_3DSTATE_SAMPLE_PATTERN_16xSample12XOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_16xSample12XOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLE_PATTERN_16xSample12XOffset_start 132 #define GFX12_3DSTATE_SAMPLE_PATTERN_16xSample12XOffset_start 132 #define GFX11_3DSTATE_SAMPLE_PATTERN_16xSample12XOffset_start 132 #define GFX9_3DSTATE_SAMPLE_PATTERN_16xSample12XOffset_start 132 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_16xSample12XOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 132; case 120: return 132; case 110: return 132; case 90: return 132; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLE_PATTERN::16x Sample12 Y Offset */ #define GFX125_3DSTATE_SAMPLE_PATTERN_16xSample12YOffset_bits 4 #define GFX12_3DSTATE_SAMPLE_PATTERN_16xSample12YOffset_bits 4 #define GFX11_3DSTATE_SAMPLE_PATTERN_16xSample12YOffset_bits 4 #define GFX9_3DSTATE_SAMPLE_PATTERN_16xSample12YOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_16xSample12YOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLE_PATTERN_16xSample12YOffset_start 128 #define GFX12_3DSTATE_SAMPLE_PATTERN_16xSample12YOffset_start 128 #define GFX11_3DSTATE_SAMPLE_PATTERN_16xSample12YOffset_start 128 #define GFX9_3DSTATE_SAMPLE_PATTERN_16xSample12YOffset_start 128 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_16xSample12YOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 128; case 120: return 128; case 110: return 128; case 90: return 128; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLE_PATTERN::16x Sample13 X Offset */ #define GFX125_3DSTATE_SAMPLE_PATTERN_16xSample13XOffset_bits 4 #define GFX12_3DSTATE_SAMPLE_PATTERN_16xSample13XOffset_bits 4 #define GFX11_3DSTATE_SAMPLE_PATTERN_16xSample13XOffset_bits 4 #define GFX9_3DSTATE_SAMPLE_PATTERN_16xSample13XOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_16xSample13XOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLE_PATTERN_16xSample13XOffset_start 140 #define GFX12_3DSTATE_SAMPLE_PATTERN_16xSample13XOffset_start 140 #define GFX11_3DSTATE_SAMPLE_PATTERN_16xSample13XOffset_start 140 #define GFX9_3DSTATE_SAMPLE_PATTERN_16xSample13XOffset_start 140 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_16xSample13XOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 140; case 120: return 140; case 110: return 140; case 90: return 140; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLE_PATTERN::16x Sample13 Y Offset */ #define GFX125_3DSTATE_SAMPLE_PATTERN_16xSample13YOffset_bits 4 #define GFX12_3DSTATE_SAMPLE_PATTERN_16xSample13YOffset_bits 4 #define GFX11_3DSTATE_SAMPLE_PATTERN_16xSample13YOffset_bits 4 #define GFX9_3DSTATE_SAMPLE_PATTERN_16xSample13YOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_16xSample13YOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLE_PATTERN_16xSample13YOffset_start 136 #define GFX12_3DSTATE_SAMPLE_PATTERN_16xSample13YOffset_start 136 #define GFX11_3DSTATE_SAMPLE_PATTERN_16xSample13YOffset_start 136 #define GFX9_3DSTATE_SAMPLE_PATTERN_16xSample13YOffset_start 136 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_16xSample13YOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 136; case 120: return 136; case 110: return 136; case 90: return 136; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLE_PATTERN::16x Sample14 X Offset */ #define GFX125_3DSTATE_SAMPLE_PATTERN_16xSample14XOffset_bits 4 #define GFX12_3DSTATE_SAMPLE_PATTERN_16xSample14XOffset_bits 4 #define GFX11_3DSTATE_SAMPLE_PATTERN_16xSample14XOffset_bits 4 #define GFX9_3DSTATE_SAMPLE_PATTERN_16xSample14XOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_16xSample14XOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLE_PATTERN_16xSample14XOffset_start 148 #define GFX12_3DSTATE_SAMPLE_PATTERN_16xSample14XOffset_start 148 #define GFX11_3DSTATE_SAMPLE_PATTERN_16xSample14XOffset_start 148 #define GFX9_3DSTATE_SAMPLE_PATTERN_16xSample14XOffset_start 148 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_16xSample14XOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 148; case 120: return 148; case 110: return 148; case 90: return 148; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLE_PATTERN::16x Sample14 Y Offset */ #define GFX125_3DSTATE_SAMPLE_PATTERN_16xSample14YOffset_bits 4 #define GFX12_3DSTATE_SAMPLE_PATTERN_16xSample14YOffset_bits 4 #define GFX11_3DSTATE_SAMPLE_PATTERN_16xSample14YOffset_bits 4 #define GFX9_3DSTATE_SAMPLE_PATTERN_16xSample14YOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_16xSample14YOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLE_PATTERN_16xSample14YOffset_start 144 #define GFX12_3DSTATE_SAMPLE_PATTERN_16xSample14YOffset_start 144 #define GFX11_3DSTATE_SAMPLE_PATTERN_16xSample14YOffset_start 144 #define GFX9_3DSTATE_SAMPLE_PATTERN_16xSample14YOffset_start 144 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_16xSample14YOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 144; case 120: return 144; case 110: return 144; case 90: return 144; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLE_PATTERN::16x Sample15 X Offset */ #define GFX125_3DSTATE_SAMPLE_PATTERN_16xSample15XOffset_bits 4 #define GFX12_3DSTATE_SAMPLE_PATTERN_16xSample15XOffset_bits 4 #define GFX11_3DSTATE_SAMPLE_PATTERN_16xSample15XOffset_bits 4 #define GFX9_3DSTATE_SAMPLE_PATTERN_16xSample15XOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_16xSample15XOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLE_PATTERN_16xSample15XOffset_start 156 #define GFX12_3DSTATE_SAMPLE_PATTERN_16xSample15XOffset_start 156 #define GFX11_3DSTATE_SAMPLE_PATTERN_16xSample15XOffset_start 156 #define GFX9_3DSTATE_SAMPLE_PATTERN_16xSample15XOffset_start 156 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_16xSample15XOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 156; case 120: return 156; case 110: return 156; case 90: return 156; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLE_PATTERN::16x Sample15 Y Offset */ #define GFX125_3DSTATE_SAMPLE_PATTERN_16xSample15YOffset_bits 4 #define GFX12_3DSTATE_SAMPLE_PATTERN_16xSample15YOffset_bits 4 #define GFX11_3DSTATE_SAMPLE_PATTERN_16xSample15YOffset_bits 4 #define GFX9_3DSTATE_SAMPLE_PATTERN_16xSample15YOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_16xSample15YOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLE_PATTERN_16xSample15YOffset_start 152 #define GFX12_3DSTATE_SAMPLE_PATTERN_16xSample15YOffset_start 152 #define GFX11_3DSTATE_SAMPLE_PATTERN_16xSample15YOffset_start 152 #define GFX9_3DSTATE_SAMPLE_PATTERN_16xSample15YOffset_start 152 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_16xSample15YOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 152; case 120: return 152; case 110: return 152; case 90: return 152; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLE_PATTERN::16x Sample1 X Offset */ #define GFX125_3DSTATE_SAMPLE_PATTERN_16xSample1XOffset_bits 4 #define GFX12_3DSTATE_SAMPLE_PATTERN_16xSample1XOffset_bits 4 #define GFX11_3DSTATE_SAMPLE_PATTERN_16xSample1XOffset_bits 4 #define GFX9_3DSTATE_SAMPLE_PATTERN_16xSample1XOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_16xSample1XOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLE_PATTERN_16xSample1XOffset_start 44 #define GFX12_3DSTATE_SAMPLE_PATTERN_16xSample1XOffset_start 44 #define GFX11_3DSTATE_SAMPLE_PATTERN_16xSample1XOffset_start 44 #define GFX9_3DSTATE_SAMPLE_PATTERN_16xSample1XOffset_start 44 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_16xSample1XOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 44; case 120: return 44; case 110: return 44; case 90: return 44; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLE_PATTERN::16x Sample1 Y Offset */ #define GFX125_3DSTATE_SAMPLE_PATTERN_16xSample1YOffset_bits 4 #define GFX12_3DSTATE_SAMPLE_PATTERN_16xSample1YOffset_bits 4 #define GFX11_3DSTATE_SAMPLE_PATTERN_16xSample1YOffset_bits 4 #define GFX9_3DSTATE_SAMPLE_PATTERN_16xSample1YOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_16xSample1YOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLE_PATTERN_16xSample1YOffset_start 40 #define GFX12_3DSTATE_SAMPLE_PATTERN_16xSample1YOffset_start 40 #define GFX11_3DSTATE_SAMPLE_PATTERN_16xSample1YOffset_start 40 #define GFX9_3DSTATE_SAMPLE_PATTERN_16xSample1YOffset_start 40 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_16xSample1YOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 40; case 120: return 40; case 110: return 40; case 90: return 40; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLE_PATTERN::16x Sample2 X Offset */ #define GFX125_3DSTATE_SAMPLE_PATTERN_16xSample2XOffset_bits 4 #define GFX12_3DSTATE_SAMPLE_PATTERN_16xSample2XOffset_bits 4 #define GFX11_3DSTATE_SAMPLE_PATTERN_16xSample2XOffset_bits 4 #define GFX9_3DSTATE_SAMPLE_PATTERN_16xSample2XOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_16xSample2XOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLE_PATTERN_16xSample2XOffset_start 52 #define GFX12_3DSTATE_SAMPLE_PATTERN_16xSample2XOffset_start 52 #define GFX11_3DSTATE_SAMPLE_PATTERN_16xSample2XOffset_start 52 #define GFX9_3DSTATE_SAMPLE_PATTERN_16xSample2XOffset_start 52 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_16xSample2XOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 52; case 120: return 52; case 110: return 52; case 90: return 52; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLE_PATTERN::16x Sample2 Y Offset */ #define GFX125_3DSTATE_SAMPLE_PATTERN_16xSample2YOffset_bits 4 #define GFX12_3DSTATE_SAMPLE_PATTERN_16xSample2YOffset_bits 4 #define GFX11_3DSTATE_SAMPLE_PATTERN_16xSample2YOffset_bits 4 #define GFX9_3DSTATE_SAMPLE_PATTERN_16xSample2YOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_16xSample2YOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLE_PATTERN_16xSample2YOffset_start 48 #define GFX12_3DSTATE_SAMPLE_PATTERN_16xSample2YOffset_start 48 #define GFX11_3DSTATE_SAMPLE_PATTERN_16xSample2YOffset_start 48 #define GFX9_3DSTATE_SAMPLE_PATTERN_16xSample2YOffset_start 48 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_16xSample2YOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 48; case 120: return 48; case 110: return 48; case 90: return 48; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLE_PATTERN::16x Sample3 X Offset */ #define GFX125_3DSTATE_SAMPLE_PATTERN_16xSample3XOffset_bits 4 #define GFX12_3DSTATE_SAMPLE_PATTERN_16xSample3XOffset_bits 4 #define GFX11_3DSTATE_SAMPLE_PATTERN_16xSample3XOffset_bits 4 #define GFX9_3DSTATE_SAMPLE_PATTERN_16xSample3XOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_16xSample3XOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLE_PATTERN_16xSample3XOffset_start 60 #define GFX12_3DSTATE_SAMPLE_PATTERN_16xSample3XOffset_start 60 #define GFX11_3DSTATE_SAMPLE_PATTERN_16xSample3XOffset_start 60 #define GFX9_3DSTATE_SAMPLE_PATTERN_16xSample3XOffset_start 60 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_16xSample3XOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 60; case 120: return 60; case 110: return 60; case 90: return 60; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLE_PATTERN::16x Sample3 Y Offset */ #define GFX125_3DSTATE_SAMPLE_PATTERN_16xSample3YOffset_bits 4 #define GFX12_3DSTATE_SAMPLE_PATTERN_16xSample3YOffset_bits 4 #define GFX11_3DSTATE_SAMPLE_PATTERN_16xSample3YOffset_bits 4 #define GFX9_3DSTATE_SAMPLE_PATTERN_16xSample3YOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_16xSample3YOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLE_PATTERN_16xSample3YOffset_start 56 #define GFX12_3DSTATE_SAMPLE_PATTERN_16xSample3YOffset_start 56 #define GFX11_3DSTATE_SAMPLE_PATTERN_16xSample3YOffset_start 56 #define GFX9_3DSTATE_SAMPLE_PATTERN_16xSample3YOffset_start 56 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_16xSample3YOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 56; case 120: return 56; case 110: return 56; case 90: return 56; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLE_PATTERN::16x Sample4 X Offset */ #define GFX125_3DSTATE_SAMPLE_PATTERN_16xSample4XOffset_bits 4 #define GFX12_3DSTATE_SAMPLE_PATTERN_16xSample4XOffset_bits 4 #define GFX11_3DSTATE_SAMPLE_PATTERN_16xSample4XOffset_bits 4 #define GFX9_3DSTATE_SAMPLE_PATTERN_16xSample4XOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_16xSample4XOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLE_PATTERN_16xSample4XOffset_start 68 #define GFX12_3DSTATE_SAMPLE_PATTERN_16xSample4XOffset_start 68 #define GFX11_3DSTATE_SAMPLE_PATTERN_16xSample4XOffset_start 68 #define GFX9_3DSTATE_SAMPLE_PATTERN_16xSample4XOffset_start 68 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_16xSample4XOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 68; case 120: return 68; case 110: return 68; case 90: return 68; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLE_PATTERN::16x Sample4 Y Offset */ #define GFX125_3DSTATE_SAMPLE_PATTERN_16xSample4YOffset_bits 4 #define GFX12_3DSTATE_SAMPLE_PATTERN_16xSample4YOffset_bits 4 #define GFX11_3DSTATE_SAMPLE_PATTERN_16xSample4YOffset_bits 4 #define GFX9_3DSTATE_SAMPLE_PATTERN_16xSample4YOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_16xSample4YOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLE_PATTERN_16xSample4YOffset_start 64 #define GFX12_3DSTATE_SAMPLE_PATTERN_16xSample4YOffset_start 64 #define GFX11_3DSTATE_SAMPLE_PATTERN_16xSample4YOffset_start 64 #define GFX9_3DSTATE_SAMPLE_PATTERN_16xSample4YOffset_start 64 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_16xSample4YOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 64; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLE_PATTERN::16x Sample5 X Offset */ #define GFX125_3DSTATE_SAMPLE_PATTERN_16xSample5XOffset_bits 4 #define GFX12_3DSTATE_SAMPLE_PATTERN_16xSample5XOffset_bits 4 #define GFX11_3DSTATE_SAMPLE_PATTERN_16xSample5XOffset_bits 4 #define GFX9_3DSTATE_SAMPLE_PATTERN_16xSample5XOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_16xSample5XOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLE_PATTERN_16xSample5XOffset_start 76 #define GFX12_3DSTATE_SAMPLE_PATTERN_16xSample5XOffset_start 76 #define GFX11_3DSTATE_SAMPLE_PATTERN_16xSample5XOffset_start 76 #define GFX9_3DSTATE_SAMPLE_PATTERN_16xSample5XOffset_start 76 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_16xSample5XOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 76; case 120: return 76; case 110: return 76; case 90: return 76; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLE_PATTERN::16x Sample5 Y Offset */ #define GFX125_3DSTATE_SAMPLE_PATTERN_16xSample5YOffset_bits 4 #define GFX12_3DSTATE_SAMPLE_PATTERN_16xSample5YOffset_bits 4 #define GFX11_3DSTATE_SAMPLE_PATTERN_16xSample5YOffset_bits 4 #define GFX9_3DSTATE_SAMPLE_PATTERN_16xSample5YOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_16xSample5YOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLE_PATTERN_16xSample5YOffset_start 72 #define GFX12_3DSTATE_SAMPLE_PATTERN_16xSample5YOffset_start 72 #define GFX11_3DSTATE_SAMPLE_PATTERN_16xSample5YOffset_start 72 #define GFX9_3DSTATE_SAMPLE_PATTERN_16xSample5YOffset_start 72 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_16xSample5YOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 72; case 120: return 72; case 110: return 72; case 90: return 72; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLE_PATTERN::16x Sample6 X Offset */ #define GFX125_3DSTATE_SAMPLE_PATTERN_16xSample6XOffset_bits 4 #define GFX12_3DSTATE_SAMPLE_PATTERN_16xSample6XOffset_bits 4 #define GFX11_3DSTATE_SAMPLE_PATTERN_16xSample6XOffset_bits 4 #define GFX9_3DSTATE_SAMPLE_PATTERN_16xSample6XOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_16xSample6XOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLE_PATTERN_16xSample6XOffset_start 84 #define GFX12_3DSTATE_SAMPLE_PATTERN_16xSample6XOffset_start 84 #define GFX11_3DSTATE_SAMPLE_PATTERN_16xSample6XOffset_start 84 #define GFX9_3DSTATE_SAMPLE_PATTERN_16xSample6XOffset_start 84 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_16xSample6XOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 84; case 120: return 84; case 110: return 84; case 90: return 84; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLE_PATTERN::16x Sample6 Y Offset */ #define GFX125_3DSTATE_SAMPLE_PATTERN_16xSample6YOffset_bits 4 #define GFX12_3DSTATE_SAMPLE_PATTERN_16xSample6YOffset_bits 4 #define GFX11_3DSTATE_SAMPLE_PATTERN_16xSample6YOffset_bits 4 #define GFX9_3DSTATE_SAMPLE_PATTERN_16xSample6YOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_16xSample6YOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLE_PATTERN_16xSample6YOffset_start 80 #define GFX12_3DSTATE_SAMPLE_PATTERN_16xSample6YOffset_start 80 #define GFX11_3DSTATE_SAMPLE_PATTERN_16xSample6YOffset_start 80 #define GFX9_3DSTATE_SAMPLE_PATTERN_16xSample6YOffset_start 80 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_16xSample6YOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 80; case 120: return 80; case 110: return 80; case 90: return 80; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLE_PATTERN::16x Sample7 X Offset */ #define GFX125_3DSTATE_SAMPLE_PATTERN_16xSample7XOffset_bits 4 #define GFX12_3DSTATE_SAMPLE_PATTERN_16xSample7XOffset_bits 4 #define GFX11_3DSTATE_SAMPLE_PATTERN_16xSample7XOffset_bits 4 #define GFX9_3DSTATE_SAMPLE_PATTERN_16xSample7XOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_16xSample7XOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLE_PATTERN_16xSample7XOffset_start 92 #define GFX12_3DSTATE_SAMPLE_PATTERN_16xSample7XOffset_start 92 #define GFX11_3DSTATE_SAMPLE_PATTERN_16xSample7XOffset_start 92 #define GFX9_3DSTATE_SAMPLE_PATTERN_16xSample7XOffset_start 92 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_16xSample7XOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 92; case 120: return 92; case 110: return 92; case 90: return 92; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLE_PATTERN::16x Sample7 Y Offset */ #define GFX125_3DSTATE_SAMPLE_PATTERN_16xSample7YOffset_bits 4 #define GFX12_3DSTATE_SAMPLE_PATTERN_16xSample7YOffset_bits 4 #define GFX11_3DSTATE_SAMPLE_PATTERN_16xSample7YOffset_bits 4 #define GFX9_3DSTATE_SAMPLE_PATTERN_16xSample7YOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_16xSample7YOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLE_PATTERN_16xSample7YOffset_start 88 #define GFX12_3DSTATE_SAMPLE_PATTERN_16xSample7YOffset_start 88 #define GFX11_3DSTATE_SAMPLE_PATTERN_16xSample7YOffset_start 88 #define GFX9_3DSTATE_SAMPLE_PATTERN_16xSample7YOffset_start 88 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_16xSample7YOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 88; case 120: return 88; case 110: return 88; case 90: return 88; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLE_PATTERN::16x Sample8 X Offset */ #define GFX125_3DSTATE_SAMPLE_PATTERN_16xSample8XOffset_bits 4 #define GFX12_3DSTATE_SAMPLE_PATTERN_16xSample8XOffset_bits 4 #define GFX11_3DSTATE_SAMPLE_PATTERN_16xSample8XOffset_bits 4 #define GFX9_3DSTATE_SAMPLE_PATTERN_16xSample8XOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_16xSample8XOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLE_PATTERN_16xSample8XOffset_start 100 #define GFX12_3DSTATE_SAMPLE_PATTERN_16xSample8XOffset_start 100 #define GFX11_3DSTATE_SAMPLE_PATTERN_16xSample8XOffset_start 100 #define GFX9_3DSTATE_SAMPLE_PATTERN_16xSample8XOffset_start 100 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_16xSample8XOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 100; case 120: return 100; case 110: return 100; case 90: return 100; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLE_PATTERN::16x Sample8 Y Offset */ #define GFX125_3DSTATE_SAMPLE_PATTERN_16xSample8YOffset_bits 4 #define GFX12_3DSTATE_SAMPLE_PATTERN_16xSample8YOffset_bits 4 #define GFX11_3DSTATE_SAMPLE_PATTERN_16xSample8YOffset_bits 4 #define GFX9_3DSTATE_SAMPLE_PATTERN_16xSample8YOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_16xSample8YOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLE_PATTERN_16xSample8YOffset_start 96 #define GFX12_3DSTATE_SAMPLE_PATTERN_16xSample8YOffset_start 96 #define GFX11_3DSTATE_SAMPLE_PATTERN_16xSample8YOffset_start 96 #define GFX9_3DSTATE_SAMPLE_PATTERN_16xSample8YOffset_start 96 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_16xSample8YOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 96; case 120: return 96; case 110: return 96; case 90: return 96; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLE_PATTERN::16x Sample9 X Offset */ #define GFX125_3DSTATE_SAMPLE_PATTERN_16xSample9XOffset_bits 4 #define GFX12_3DSTATE_SAMPLE_PATTERN_16xSample9XOffset_bits 4 #define GFX11_3DSTATE_SAMPLE_PATTERN_16xSample9XOffset_bits 4 #define GFX9_3DSTATE_SAMPLE_PATTERN_16xSample9XOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_16xSample9XOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLE_PATTERN_16xSample9XOffset_start 108 #define GFX12_3DSTATE_SAMPLE_PATTERN_16xSample9XOffset_start 108 #define GFX11_3DSTATE_SAMPLE_PATTERN_16xSample9XOffset_start 108 #define GFX9_3DSTATE_SAMPLE_PATTERN_16xSample9XOffset_start 108 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_16xSample9XOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 108; case 120: return 108; case 110: return 108; case 90: return 108; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLE_PATTERN::16x Sample9 Y Offset */ #define GFX125_3DSTATE_SAMPLE_PATTERN_16xSample9YOffset_bits 4 #define GFX12_3DSTATE_SAMPLE_PATTERN_16xSample9YOffset_bits 4 #define GFX11_3DSTATE_SAMPLE_PATTERN_16xSample9YOffset_bits 4 #define GFX9_3DSTATE_SAMPLE_PATTERN_16xSample9YOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_16xSample9YOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLE_PATTERN_16xSample9YOffset_start 104 #define GFX12_3DSTATE_SAMPLE_PATTERN_16xSample9YOffset_start 104 #define GFX11_3DSTATE_SAMPLE_PATTERN_16xSample9YOffset_start 104 #define GFX9_3DSTATE_SAMPLE_PATTERN_16xSample9YOffset_start 104 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_16xSample9YOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 104; case 120: return 104; case 110: return 104; case 90: return 104; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLE_PATTERN::1x Sample0 X Offset */ #define GFX125_3DSTATE_SAMPLE_PATTERN_1xSample0XOffset_bits 4 #define GFX12_3DSTATE_SAMPLE_PATTERN_1xSample0XOffset_bits 4 #define GFX11_3DSTATE_SAMPLE_PATTERN_1xSample0XOffset_bits 4 #define GFX9_3DSTATE_SAMPLE_PATTERN_1xSample0XOffset_bits 4 #define GFX8_3DSTATE_SAMPLE_PATTERN_1xSample0XOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_1xSample0XOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLE_PATTERN_1xSample0XOffset_start 276 #define GFX12_3DSTATE_SAMPLE_PATTERN_1xSample0XOffset_start 276 #define GFX11_3DSTATE_SAMPLE_PATTERN_1xSample0XOffset_start 276 #define GFX9_3DSTATE_SAMPLE_PATTERN_1xSample0XOffset_start 276 #define GFX8_3DSTATE_SAMPLE_PATTERN_1xSample0XOffset_start 276 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_1xSample0XOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 276; case 120: return 276; case 110: return 276; case 90: return 276; case 80: return 276; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLE_PATTERN::1x Sample0 Y Offset */ #define GFX125_3DSTATE_SAMPLE_PATTERN_1xSample0YOffset_bits 4 #define GFX12_3DSTATE_SAMPLE_PATTERN_1xSample0YOffset_bits 4 #define GFX11_3DSTATE_SAMPLE_PATTERN_1xSample0YOffset_bits 4 #define GFX9_3DSTATE_SAMPLE_PATTERN_1xSample0YOffset_bits 4 #define GFX8_3DSTATE_SAMPLE_PATTERN_1xSample0YOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_1xSample0YOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLE_PATTERN_1xSample0YOffset_start 272 #define GFX12_3DSTATE_SAMPLE_PATTERN_1xSample0YOffset_start 272 #define GFX11_3DSTATE_SAMPLE_PATTERN_1xSample0YOffset_start 272 #define GFX9_3DSTATE_SAMPLE_PATTERN_1xSample0YOffset_start 272 #define GFX8_3DSTATE_SAMPLE_PATTERN_1xSample0YOffset_start 272 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_1xSample0YOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 272; case 120: return 272; case 110: return 272; case 90: return 272; case 80: return 272; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLE_PATTERN::2x Sample0 X Offset */ #define GFX125_3DSTATE_SAMPLE_PATTERN_2xSample0XOffset_bits 4 #define GFX12_3DSTATE_SAMPLE_PATTERN_2xSample0XOffset_bits 4 #define GFX11_3DSTATE_SAMPLE_PATTERN_2xSample0XOffset_bits 4 #define GFX9_3DSTATE_SAMPLE_PATTERN_2xSample0XOffset_bits 4 #define GFX8_3DSTATE_SAMPLE_PATTERN_2xSample0XOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_2xSample0XOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLE_PATTERN_2xSample0XOffset_start 260 #define GFX12_3DSTATE_SAMPLE_PATTERN_2xSample0XOffset_start 260 #define GFX11_3DSTATE_SAMPLE_PATTERN_2xSample0XOffset_start 260 #define GFX9_3DSTATE_SAMPLE_PATTERN_2xSample0XOffset_start 260 #define GFX8_3DSTATE_SAMPLE_PATTERN_2xSample0XOffset_start 260 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_2xSample0XOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 260; case 120: return 260; case 110: return 260; case 90: return 260; case 80: return 260; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLE_PATTERN::2x Sample0 Y Offset */ #define GFX125_3DSTATE_SAMPLE_PATTERN_2xSample0YOffset_bits 4 #define GFX12_3DSTATE_SAMPLE_PATTERN_2xSample0YOffset_bits 4 #define GFX11_3DSTATE_SAMPLE_PATTERN_2xSample0YOffset_bits 4 #define GFX9_3DSTATE_SAMPLE_PATTERN_2xSample0YOffset_bits 4 #define GFX8_3DSTATE_SAMPLE_PATTERN_2xSample0YOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_2xSample0YOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLE_PATTERN_2xSample0YOffset_start 256 #define GFX12_3DSTATE_SAMPLE_PATTERN_2xSample0YOffset_start 256 #define GFX11_3DSTATE_SAMPLE_PATTERN_2xSample0YOffset_start 256 #define GFX9_3DSTATE_SAMPLE_PATTERN_2xSample0YOffset_start 256 #define GFX8_3DSTATE_SAMPLE_PATTERN_2xSample0YOffset_start 256 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_2xSample0YOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 256; case 120: return 256; case 110: return 256; case 90: return 256; case 80: return 256; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLE_PATTERN::2x Sample1 X Offset */ #define GFX125_3DSTATE_SAMPLE_PATTERN_2xSample1XOffset_bits 4 #define GFX12_3DSTATE_SAMPLE_PATTERN_2xSample1XOffset_bits 4 #define GFX11_3DSTATE_SAMPLE_PATTERN_2xSample1XOffset_bits 4 #define GFX9_3DSTATE_SAMPLE_PATTERN_2xSample1XOffset_bits 4 #define GFX8_3DSTATE_SAMPLE_PATTERN_2xSample1XOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_2xSample1XOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLE_PATTERN_2xSample1XOffset_start 268 #define GFX12_3DSTATE_SAMPLE_PATTERN_2xSample1XOffset_start 268 #define GFX11_3DSTATE_SAMPLE_PATTERN_2xSample1XOffset_start 268 #define GFX9_3DSTATE_SAMPLE_PATTERN_2xSample1XOffset_start 268 #define GFX8_3DSTATE_SAMPLE_PATTERN_2xSample1XOffset_start 268 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_2xSample1XOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 268; case 120: return 268; case 110: return 268; case 90: return 268; case 80: return 268; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLE_PATTERN::2x Sample1 Y Offset */ #define GFX125_3DSTATE_SAMPLE_PATTERN_2xSample1YOffset_bits 4 #define GFX12_3DSTATE_SAMPLE_PATTERN_2xSample1YOffset_bits 4 #define GFX11_3DSTATE_SAMPLE_PATTERN_2xSample1YOffset_bits 4 #define GFX9_3DSTATE_SAMPLE_PATTERN_2xSample1YOffset_bits 4 #define GFX8_3DSTATE_SAMPLE_PATTERN_2xSample1YOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_2xSample1YOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLE_PATTERN_2xSample1YOffset_start 264 #define GFX12_3DSTATE_SAMPLE_PATTERN_2xSample1YOffset_start 264 #define GFX11_3DSTATE_SAMPLE_PATTERN_2xSample1YOffset_start 264 #define GFX9_3DSTATE_SAMPLE_PATTERN_2xSample1YOffset_start 264 #define GFX8_3DSTATE_SAMPLE_PATTERN_2xSample1YOffset_start 264 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_2xSample1YOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 264; case 120: return 264; case 110: return 264; case 90: return 264; case 80: return 264; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLE_PATTERN::3D Command Opcode */ #define GFX125_3DSTATE_SAMPLE_PATTERN_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_SAMPLE_PATTERN_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_SAMPLE_PATTERN_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_SAMPLE_PATTERN_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_SAMPLE_PATTERN_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLE_PATTERN_3DCommandOpcode_start 24 #define GFX12_3DSTATE_SAMPLE_PATTERN_3DCommandOpcode_start 24 #define GFX11_3DSTATE_SAMPLE_PATTERN_3DCommandOpcode_start 24 #define GFX9_3DSTATE_SAMPLE_PATTERN_3DCommandOpcode_start 24 #define GFX8_3DSTATE_SAMPLE_PATTERN_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLE_PATTERN::3D Command Sub Opcode */ #define GFX125_3DSTATE_SAMPLE_PATTERN_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_SAMPLE_PATTERN_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_SAMPLE_PATTERN_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_SAMPLE_PATTERN_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_SAMPLE_PATTERN_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLE_PATTERN_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_SAMPLE_PATTERN_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_SAMPLE_PATTERN_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_SAMPLE_PATTERN_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_SAMPLE_PATTERN_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLE_PATTERN::4x Sample0 X Offset */ #define GFX125_3DSTATE_SAMPLE_PATTERN_4xSample0XOffset_bits 4 #define GFX12_3DSTATE_SAMPLE_PATTERN_4xSample0XOffset_bits 4 #define GFX11_3DSTATE_SAMPLE_PATTERN_4xSample0XOffset_bits 4 #define GFX9_3DSTATE_SAMPLE_PATTERN_4xSample0XOffset_bits 4 #define GFX8_3DSTATE_SAMPLE_PATTERN_4xSample0XOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_4xSample0XOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLE_PATTERN_4xSample0XOffset_start 228 #define GFX12_3DSTATE_SAMPLE_PATTERN_4xSample0XOffset_start 228 #define GFX11_3DSTATE_SAMPLE_PATTERN_4xSample0XOffset_start 228 #define GFX9_3DSTATE_SAMPLE_PATTERN_4xSample0XOffset_start 228 #define GFX8_3DSTATE_SAMPLE_PATTERN_4xSample0XOffset_start 228 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_4xSample0XOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 228; case 120: return 228; case 110: return 228; case 90: return 228; case 80: return 228; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLE_PATTERN::4x Sample0 Y Offset */ #define GFX125_3DSTATE_SAMPLE_PATTERN_4xSample0YOffset_bits 4 #define GFX12_3DSTATE_SAMPLE_PATTERN_4xSample0YOffset_bits 4 #define GFX11_3DSTATE_SAMPLE_PATTERN_4xSample0YOffset_bits 4 #define GFX9_3DSTATE_SAMPLE_PATTERN_4xSample0YOffset_bits 4 #define GFX8_3DSTATE_SAMPLE_PATTERN_4xSample0YOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_4xSample0YOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLE_PATTERN_4xSample0YOffset_start 224 #define GFX12_3DSTATE_SAMPLE_PATTERN_4xSample0YOffset_start 224 #define GFX11_3DSTATE_SAMPLE_PATTERN_4xSample0YOffset_start 224 #define GFX9_3DSTATE_SAMPLE_PATTERN_4xSample0YOffset_start 224 #define GFX8_3DSTATE_SAMPLE_PATTERN_4xSample0YOffset_start 224 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_4xSample0YOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 224; case 120: return 224; case 110: return 224; case 90: return 224; case 80: return 224; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLE_PATTERN::4x Sample1 X Offset */ #define GFX125_3DSTATE_SAMPLE_PATTERN_4xSample1XOffset_bits 4 #define GFX12_3DSTATE_SAMPLE_PATTERN_4xSample1XOffset_bits 4 #define GFX11_3DSTATE_SAMPLE_PATTERN_4xSample1XOffset_bits 4 #define GFX9_3DSTATE_SAMPLE_PATTERN_4xSample1XOffset_bits 4 #define GFX8_3DSTATE_SAMPLE_PATTERN_4xSample1XOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_4xSample1XOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLE_PATTERN_4xSample1XOffset_start 236 #define GFX12_3DSTATE_SAMPLE_PATTERN_4xSample1XOffset_start 236 #define GFX11_3DSTATE_SAMPLE_PATTERN_4xSample1XOffset_start 236 #define GFX9_3DSTATE_SAMPLE_PATTERN_4xSample1XOffset_start 236 #define GFX8_3DSTATE_SAMPLE_PATTERN_4xSample1XOffset_start 236 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_4xSample1XOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 236; case 120: return 236; case 110: return 236; case 90: return 236; case 80: return 236; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLE_PATTERN::4x Sample1 Y Offset */ #define GFX125_3DSTATE_SAMPLE_PATTERN_4xSample1YOffset_bits 4 #define GFX12_3DSTATE_SAMPLE_PATTERN_4xSample1YOffset_bits 4 #define GFX11_3DSTATE_SAMPLE_PATTERN_4xSample1YOffset_bits 4 #define GFX9_3DSTATE_SAMPLE_PATTERN_4xSample1YOffset_bits 4 #define GFX8_3DSTATE_SAMPLE_PATTERN_4xSample1YOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_4xSample1YOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLE_PATTERN_4xSample1YOffset_start 232 #define GFX12_3DSTATE_SAMPLE_PATTERN_4xSample1YOffset_start 232 #define GFX11_3DSTATE_SAMPLE_PATTERN_4xSample1YOffset_start 232 #define GFX9_3DSTATE_SAMPLE_PATTERN_4xSample1YOffset_start 232 #define GFX8_3DSTATE_SAMPLE_PATTERN_4xSample1YOffset_start 232 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_4xSample1YOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 232; case 120: return 232; case 110: return 232; case 90: return 232; case 80: return 232; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLE_PATTERN::4x Sample2 X Offset */ #define GFX125_3DSTATE_SAMPLE_PATTERN_4xSample2XOffset_bits 4 #define GFX12_3DSTATE_SAMPLE_PATTERN_4xSample2XOffset_bits 4 #define GFX11_3DSTATE_SAMPLE_PATTERN_4xSample2XOffset_bits 4 #define GFX9_3DSTATE_SAMPLE_PATTERN_4xSample2XOffset_bits 4 #define GFX8_3DSTATE_SAMPLE_PATTERN_4xSample2XOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_4xSample2XOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLE_PATTERN_4xSample2XOffset_start 244 #define GFX12_3DSTATE_SAMPLE_PATTERN_4xSample2XOffset_start 244 #define GFX11_3DSTATE_SAMPLE_PATTERN_4xSample2XOffset_start 244 #define GFX9_3DSTATE_SAMPLE_PATTERN_4xSample2XOffset_start 244 #define GFX8_3DSTATE_SAMPLE_PATTERN_4xSample2XOffset_start 244 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_4xSample2XOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 244; case 120: return 244; case 110: return 244; case 90: return 244; case 80: return 244; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLE_PATTERN::4x Sample2 Y Offset */ #define GFX125_3DSTATE_SAMPLE_PATTERN_4xSample2YOffset_bits 4 #define GFX12_3DSTATE_SAMPLE_PATTERN_4xSample2YOffset_bits 4 #define GFX11_3DSTATE_SAMPLE_PATTERN_4xSample2YOffset_bits 4 #define GFX9_3DSTATE_SAMPLE_PATTERN_4xSample2YOffset_bits 4 #define GFX8_3DSTATE_SAMPLE_PATTERN_4xSample2YOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_4xSample2YOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLE_PATTERN_4xSample2YOffset_start 240 #define GFX12_3DSTATE_SAMPLE_PATTERN_4xSample2YOffset_start 240 #define GFX11_3DSTATE_SAMPLE_PATTERN_4xSample2YOffset_start 240 #define GFX9_3DSTATE_SAMPLE_PATTERN_4xSample2YOffset_start 240 #define GFX8_3DSTATE_SAMPLE_PATTERN_4xSample2YOffset_start 240 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_4xSample2YOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 240; case 120: return 240; case 110: return 240; case 90: return 240; case 80: return 240; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLE_PATTERN::4x Sample3 X Offset */ #define GFX125_3DSTATE_SAMPLE_PATTERN_4xSample3XOffset_bits 4 #define GFX12_3DSTATE_SAMPLE_PATTERN_4xSample3XOffset_bits 4 #define GFX11_3DSTATE_SAMPLE_PATTERN_4xSample3XOffset_bits 4 #define GFX9_3DSTATE_SAMPLE_PATTERN_4xSample3XOffset_bits 4 #define GFX8_3DSTATE_SAMPLE_PATTERN_4xSample3XOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_4xSample3XOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLE_PATTERN_4xSample3XOffset_start 252 #define GFX12_3DSTATE_SAMPLE_PATTERN_4xSample3XOffset_start 252 #define GFX11_3DSTATE_SAMPLE_PATTERN_4xSample3XOffset_start 252 #define GFX9_3DSTATE_SAMPLE_PATTERN_4xSample3XOffset_start 252 #define GFX8_3DSTATE_SAMPLE_PATTERN_4xSample3XOffset_start 252 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_4xSample3XOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 252; case 120: return 252; case 110: return 252; case 90: return 252; case 80: return 252; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLE_PATTERN::4x Sample3 Y Offset */ #define GFX125_3DSTATE_SAMPLE_PATTERN_4xSample3YOffset_bits 4 #define GFX12_3DSTATE_SAMPLE_PATTERN_4xSample3YOffset_bits 4 #define GFX11_3DSTATE_SAMPLE_PATTERN_4xSample3YOffset_bits 4 #define GFX9_3DSTATE_SAMPLE_PATTERN_4xSample3YOffset_bits 4 #define GFX8_3DSTATE_SAMPLE_PATTERN_4xSample3YOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_4xSample3YOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLE_PATTERN_4xSample3YOffset_start 248 #define GFX12_3DSTATE_SAMPLE_PATTERN_4xSample3YOffset_start 248 #define GFX11_3DSTATE_SAMPLE_PATTERN_4xSample3YOffset_start 248 #define GFX9_3DSTATE_SAMPLE_PATTERN_4xSample3YOffset_start 248 #define GFX8_3DSTATE_SAMPLE_PATTERN_4xSample3YOffset_start 248 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_4xSample3YOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 248; case 120: return 248; case 110: return 248; case 90: return 248; case 80: return 248; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLE_PATTERN::8x Sample0 X Offset */ #define GFX125_3DSTATE_SAMPLE_PATTERN_8xSample0XOffset_bits 4 #define GFX12_3DSTATE_SAMPLE_PATTERN_8xSample0XOffset_bits 4 #define GFX11_3DSTATE_SAMPLE_PATTERN_8xSample0XOffset_bits 4 #define GFX9_3DSTATE_SAMPLE_PATTERN_8xSample0XOffset_bits 4 #define GFX8_3DSTATE_SAMPLE_PATTERN_8xSample0XOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_8xSample0XOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLE_PATTERN_8xSample0XOffset_start 196 #define GFX12_3DSTATE_SAMPLE_PATTERN_8xSample0XOffset_start 196 #define GFX11_3DSTATE_SAMPLE_PATTERN_8xSample0XOffset_start 196 #define GFX9_3DSTATE_SAMPLE_PATTERN_8xSample0XOffset_start 196 #define GFX8_3DSTATE_SAMPLE_PATTERN_8xSample0XOffset_start 196 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_8xSample0XOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 196; case 120: return 196; case 110: return 196; case 90: return 196; case 80: return 196; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLE_PATTERN::8x Sample0 Y Offset */ #define GFX125_3DSTATE_SAMPLE_PATTERN_8xSample0YOffset_bits 4 #define GFX12_3DSTATE_SAMPLE_PATTERN_8xSample0YOffset_bits 4 #define GFX11_3DSTATE_SAMPLE_PATTERN_8xSample0YOffset_bits 4 #define GFX9_3DSTATE_SAMPLE_PATTERN_8xSample0YOffset_bits 4 #define GFX8_3DSTATE_SAMPLE_PATTERN_8xSample0YOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_8xSample0YOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLE_PATTERN_8xSample0YOffset_start 192 #define GFX12_3DSTATE_SAMPLE_PATTERN_8xSample0YOffset_start 192 #define GFX11_3DSTATE_SAMPLE_PATTERN_8xSample0YOffset_start 192 #define GFX9_3DSTATE_SAMPLE_PATTERN_8xSample0YOffset_start 192 #define GFX8_3DSTATE_SAMPLE_PATTERN_8xSample0YOffset_start 192 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_8xSample0YOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 192; case 120: return 192; case 110: return 192; case 90: return 192; case 80: return 192; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLE_PATTERN::8x Sample1 X Offset */ #define GFX125_3DSTATE_SAMPLE_PATTERN_8xSample1XOffset_bits 4 #define GFX12_3DSTATE_SAMPLE_PATTERN_8xSample1XOffset_bits 4 #define GFX11_3DSTATE_SAMPLE_PATTERN_8xSample1XOffset_bits 4 #define GFX9_3DSTATE_SAMPLE_PATTERN_8xSample1XOffset_bits 4 #define GFX8_3DSTATE_SAMPLE_PATTERN_8xSample1XOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_8xSample1XOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLE_PATTERN_8xSample1XOffset_start 204 #define GFX12_3DSTATE_SAMPLE_PATTERN_8xSample1XOffset_start 204 #define GFX11_3DSTATE_SAMPLE_PATTERN_8xSample1XOffset_start 204 #define GFX9_3DSTATE_SAMPLE_PATTERN_8xSample1XOffset_start 204 #define GFX8_3DSTATE_SAMPLE_PATTERN_8xSample1XOffset_start 204 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_8xSample1XOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 204; case 120: return 204; case 110: return 204; case 90: return 204; case 80: return 204; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLE_PATTERN::8x Sample1 Y Offset */ #define GFX125_3DSTATE_SAMPLE_PATTERN_8xSample1YOffset_bits 4 #define GFX12_3DSTATE_SAMPLE_PATTERN_8xSample1YOffset_bits 4 #define GFX11_3DSTATE_SAMPLE_PATTERN_8xSample1YOffset_bits 4 #define GFX9_3DSTATE_SAMPLE_PATTERN_8xSample1YOffset_bits 4 #define GFX8_3DSTATE_SAMPLE_PATTERN_8xSample1YOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_8xSample1YOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLE_PATTERN_8xSample1YOffset_start 200 #define GFX12_3DSTATE_SAMPLE_PATTERN_8xSample1YOffset_start 200 #define GFX11_3DSTATE_SAMPLE_PATTERN_8xSample1YOffset_start 200 #define GFX9_3DSTATE_SAMPLE_PATTERN_8xSample1YOffset_start 200 #define GFX8_3DSTATE_SAMPLE_PATTERN_8xSample1YOffset_start 200 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_8xSample1YOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 200; case 120: return 200; case 110: return 200; case 90: return 200; case 80: return 200; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLE_PATTERN::8x Sample2 X Offset */ #define GFX125_3DSTATE_SAMPLE_PATTERN_8xSample2XOffset_bits 4 #define GFX12_3DSTATE_SAMPLE_PATTERN_8xSample2XOffset_bits 4 #define GFX11_3DSTATE_SAMPLE_PATTERN_8xSample2XOffset_bits 4 #define GFX9_3DSTATE_SAMPLE_PATTERN_8xSample2XOffset_bits 4 #define GFX8_3DSTATE_SAMPLE_PATTERN_8xSample2XOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_8xSample2XOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLE_PATTERN_8xSample2XOffset_start 212 #define GFX12_3DSTATE_SAMPLE_PATTERN_8xSample2XOffset_start 212 #define GFX11_3DSTATE_SAMPLE_PATTERN_8xSample2XOffset_start 212 #define GFX9_3DSTATE_SAMPLE_PATTERN_8xSample2XOffset_start 212 #define GFX8_3DSTATE_SAMPLE_PATTERN_8xSample2XOffset_start 212 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_8xSample2XOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 212; case 120: return 212; case 110: return 212; case 90: return 212; case 80: return 212; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLE_PATTERN::8x Sample2 Y Offset */ #define GFX125_3DSTATE_SAMPLE_PATTERN_8xSample2YOffset_bits 4 #define GFX12_3DSTATE_SAMPLE_PATTERN_8xSample2YOffset_bits 4 #define GFX11_3DSTATE_SAMPLE_PATTERN_8xSample2YOffset_bits 4 #define GFX9_3DSTATE_SAMPLE_PATTERN_8xSample2YOffset_bits 4 #define GFX8_3DSTATE_SAMPLE_PATTERN_8xSample2YOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_8xSample2YOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLE_PATTERN_8xSample2YOffset_start 208 #define GFX12_3DSTATE_SAMPLE_PATTERN_8xSample2YOffset_start 208 #define GFX11_3DSTATE_SAMPLE_PATTERN_8xSample2YOffset_start 208 #define GFX9_3DSTATE_SAMPLE_PATTERN_8xSample2YOffset_start 208 #define GFX8_3DSTATE_SAMPLE_PATTERN_8xSample2YOffset_start 208 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_8xSample2YOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 208; case 120: return 208; case 110: return 208; case 90: return 208; case 80: return 208; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLE_PATTERN::8x Sample3 X Offset */ #define GFX125_3DSTATE_SAMPLE_PATTERN_8xSample3XOffset_bits 4 #define GFX12_3DSTATE_SAMPLE_PATTERN_8xSample3XOffset_bits 4 #define GFX11_3DSTATE_SAMPLE_PATTERN_8xSample3XOffset_bits 4 #define GFX9_3DSTATE_SAMPLE_PATTERN_8xSample3XOffset_bits 4 #define GFX8_3DSTATE_SAMPLE_PATTERN_8xSample3XOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_8xSample3XOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLE_PATTERN_8xSample3XOffset_start 220 #define GFX12_3DSTATE_SAMPLE_PATTERN_8xSample3XOffset_start 220 #define GFX11_3DSTATE_SAMPLE_PATTERN_8xSample3XOffset_start 220 #define GFX9_3DSTATE_SAMPLE_PATTERN_8xSample3XOffset_start 220 #define GFX8_3DSTATE_SAMPLE_PATTERN_8xSample3XOffset_start 220 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_8xSample3XOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 220; case 120: return 220; case 110: return 220; case 90: return 220; case 80: return 220; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLE_PATTERN::8x Sample3 Y Offset */ #define GFX125_3DSTATE_SAMPLE_PATTERN_8xSample3YOffset_bits 4 #define GFX12_3DSTATE_SAMPLE_PATTERN_8xSample3YOffset_bits 4 #define GFX11_3DSTATE_SAMPLE_PATTERN_8xSample3YOffset_bits 4 #define GFX9_3DSTATE_SAMPLE_PATTERN_8xSample3YOffset_bits 4 #define GFX8_3DSTATE_SAMPLE_PATTERN_8xSample3YOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_8xSample3YOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLE_PATTERN_8xSample3YOffset_start 216 #define GFX12_3DSTATE_SAMPLE_PATTERN_8xSample3YOffset_start 216 #define GFX11_3DSTATE_SAMPLE_PATTERN_8xSample3YOffset_start 216 #define GFX9_3DSTATE_SAMPLE_PATTERN_8xSample3YOffset_start 216 #define GFX8_3DSTATE_SAMPLE_PATTERN_8xSample3YOffset_start 216 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_8xSample3YOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 216; case 120: return 216; case 110: return 216; case 90: return 216; case 80: return 216; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLE_PATTERN::8x Sample4 X Offset */ #define GFX125_3DSTATE_SAMPLE_PATTERN_8xSample4XOffset_bits 4 #define GFX12_3DSTATE_SAMPLE_PATTERN_8xSample4XOffset_bits 4 #define GFX11_3DSTATE_SAMPLE_PATTERN_8xSample4XOffset_bits 4 #define GFX9_3DSTATE_SAMPLE_PATTERN_8xSample4XOffset_bits 4 #define GFX8_3DSTATE_SAMPLE_PATTERN_8xSample4XOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_8xSample4XOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLE_PATTERN_8xSample4XOffset_start 164 #define GFX12_3DSTATE_SAMPLE_PATTERN_8xSample4XOffset_start 164 #define GFX11_3DSTATE_SAMPLE_PATTERN_8xSample4XOffset_start 164 #define GFX9_3DSTATE_SAMPLE_PATTERN_8xSample4XOffset_start 164 #define GFX8_3DSTATE_SAMPLE_PATTERN_8xSample4XOffset_start 164 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_8xSample4XOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 164; case 120: return 164; case 110: return 164; case 90: return 164; case 80: return 164; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLE_PATTERN::8x Sample4 Y Offset */ #define GFX125_3DSTATE_SAMPLE_PATTERN_8xSample4YOffset_bits 4 #define GFX12_3DSTATE_SAMPLE_PATTERN_8xSample4YOffset_bits 4 #define GFX11_3DSTATE_SAMPLE_PATTERN_8xSample4YOffset_bits 4 #define GFX9_3DSTATE_SAMPLE_PATTERN_8xSample4YOffset_bits 4 #define GFX8_3DSTATE_SAMPLE_PATTERN_8xSample4YOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_8xSample4YOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLE_PATTERN_8xSample4YOffset_start 160 #define GFX12_3DSTATE_SAMPLE_PATTERN_8xSample4YOffset_start 160 #define GFX11_3DSTATE_SAMPLE_PATTERN_8xSample4YOffset_start 160 #define GFX9_3DSTATE_SAMPLE_PATTERN_8xSample4YOffset_start 160 #define GFX8_3DSTATE_SAMPLE_PATTERN_8xSample4YOffset_start 160 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_8xSample4YOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 160; case 120: return 160; case 110: return 160; case 90: return 160; case 80: return 160; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLE_PATTERN::8x Sample5 X Offset */ #define GFX125_3DSTATE_SAMPLE_PATTERN_8xSample5XOffset_bits 4 #define GFX12_3DSTATE_SAMPLE_PATTERN_8xSample5XOffset_bits 4 #define GFX11_3DSTATE_SAMPLE_PATTERN_8xSample5XOffset_bits 4 #define GFX9_3DSTATE_SAMPLE_PATTERN_8xSample5XOffset_bits 4 #define GFX8_3DSTATE_SAMPLE_PATTERN_8xSample5XOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_8xSample5XOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLE_PATTERN_8xSample5XOffset_start 172 #define GFX12_3DSTATE_SAMPLE_PATTERN_8xSample5XOffset_start 172 #define GFX11_3DSTATE_SAMPLE_PATTERN_8xSample5XOffset_start 172 #define GFX9_3DSTATE_SAMPLE_PATTERN_8xSample5XOffset_start 172 #define GFX8_3DSTATE_SAMPLE_PATTERN_8xSample5XOffset_start 172 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_8xSample5XOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 172; case 120: return 172; case 110: return 172; case 90: return 172; case 80: return 172; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLE_PATTERN::8x Sample5 Y Offset */ #define GFX125_3DSTATE_SAMPLE_PATTERN_8xSample5YOffset_bits 4 #define GFX12_3DSTATE_SAMPLE_PATTERN_8xSample5YOffset_bits 4 #define GFX11_3DSTATE_SAMPLE_PATTERN_8xSample5YOffset_bits 4 #define GFX9_3DSTATE_SAMPLE_PATTERN_8xSample5YOffset_bits 4 #define GFX8_3DSTATE_SAMPLE_PATTERN_8xSample5YOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_8xSample5YOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLE_PATTERN_8xSample5YOffset_start 168 #define GFX12_3DSTATE_SAMPLE_PATTERN_8xSample5YOffset_start 168 #define GFX11_3DSTATE_SAMPLE_PATTERN_8xSample5YOffset_start 168 #define GFX9_3DSTATE_SAMPLE_PATTERN_8xSample5YOffset_start 168 #define GFX8_3DSTATE_SAMPLE_PATTERN_8xSample5YOffset_start 168 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_8xSample5YOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 168; case 120: return 168; case 110: return 168; case 90: return 168; case 80: return 168; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLE_PATTERN::8x Sample6 X Offset */ #define GFX125_3DSTATE_SAMPLE_PATTERN_8xSample6XOffset_bits 4 #define GFX12_3DSTATE_SAMPLE_PATTERN_8xSample6XOffset_bits 4 #define GFX11_3DSTATE_SAMPLE_PATTERN_8xSample6XOffset_bits 4 #define GFX9_3DSTATE_SAMPLE_PATTERN_8xSample6XOffset_bits 4 #define GFX8_3DSTATE_SAMPLE_PATTERN_8xSample6XOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_8xSample6XOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLE_PATTERN_8xSample6XOffset_start 180 #define GFX12_3DSTATE_SAMPLE_PATTERN_8xSample6XOffset_start 180 #define GFX11_3DSTATE_SAMPLE_PATTERN_8xSample6XOffset_start 180 #define GFX9_3DSTATE_SAMPLE_PATTERN_8xSample6XOffset_start 180 #define GFX8_3DSTATE_SAMPLE_PATTERN_8xSample6XOffset_start 180 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_8xSample6XOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 180; case 120: return 180; case 110: return 180; case 90: return 180; case 80: return 180; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLE_PATTERN::8x Sample6 Y Offset */ #define GFX125_3DSTATE_SAMPLE_PATTERN_8xSample6YOffset_bits 4 #define GFX12_3DSTATE_SAMPLE_PATTERN_8xSample6YOffset_bits 4 #define GFX11_3DSTATE_SAMPLE_PATTERN_8xSample6YOffset_bits 4 #define GFX9_3DSTATE_SAMPLE_PATTERN_8xSample6YOffset_bits 4 #define GFX8_3DSTATE_SAMPLE_PATTERN_8xSample6YOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_8xSample6YOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLE_PATTERN_8xSample6YOffset_start 176 #define GFX12_3DSTATE_SAMPLE_PATTERN_8xSample6YOffset_start 176 #define GFX11_3DSTATE_SAMPLE_PATTERN_8xSample6YOffset_start 176 #define GFX9_3DSTATE_SAMPLE_PATTERN_8xSample6YOffset_start 176 #define GFX8_3DSTATE_SAMPLE_PATTERN_8xSample6YOffset_start 176 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_8xSample6YOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 176; case 120: return 176; case 110: return 176; case 90: return 176; case 80: return 176; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLE_PATTERN::8x Sample7 X Offset */ #define GFX125_3DSTATE_SAMPLE_PATTERN_8xSample7XOffset_bits 4 #define GFX12_3DSTATE_SAMPLE_PATTERN_8xSample7XOffset_bits 4 #define GFX11_3DSTATE_SAMPLE_PATTERN_8xSample7XOffset_bits 4 #define GFX9_3DSTATE_SAMPLE_PATTERN_8xSample7XOffset_bits 4 #define GFX8_3DSTATE_SAMPLE_PATTERN_8xSample7XOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_8xSample7XOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLE_PATTERN_8xSample7XOffset_start 188 #define GFX12_3DSTATE_SAMPLE_PATTERN_8xSample7XOffset_start 188 #define GFX11_3DSTATE_SAMPLE_PATTERN_8xSample7XOffset_start 188 #define GFX9_3DSTATE_SAMPLE_PATTERN_8xSample7XOffset_start 188 #define GFX8_3DSTATE_SAMPLE_PATTERN_8xSample7XOffset_start 188 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_8xSample7XOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 188; case 120: return 188; case 110: return 188; case 90: return 188; case 80: return 188; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLE_PATTERN::8x Sample7 Y Offset */ #define GFX125_3DSTATE_SAMPLE_PATTERN_8xSample7YOffset_bits 4 #define GFX12_3DSTATE_SAMPLE_PATTERN_8xSample7YOffset_bits 4 #define GFX11_3DSTATE_SAMPLE_PATTERN_8xSample7YOffset_bits 4 #define GFX9_3DSTATE_SAMPLE_PATTERN_8xSample7YOffset_bits 4 #define GFX8_3DSTATE_SAMPLE_PATTERN_8xSample7YOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_8xSample7YOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLE_PATTERN_8xSample7YOffset_start 184 #define GFX12_3DSTATE_SAMPLE_PATTERN_8xSample7YOffset_start 184 #define GFX11_3DSTATE_SAMPLE_PATTERN_8xSample7YOffset_start 184 #define GFX9_3DSTATE_SAMPLE_PATTERN_8xSample7YOffset_start 184 #define GFX8_3DSTATE_SAMPLE_PATTERN_8xSample7YOffset_start 184 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_8xSample7YOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 184; case 120: return 184; case 110: return 184; case 90: return 184; case 80: return 184; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLE_PATTERN::Command SubType */ #define GFX125_3DSTATE_SAMPLE_PATTERN_CommandSubType_bits 2 #define GFX12_3DSTATE_SAMPLE_PATTERN_CommandSubType_bits 2 #define GFX11_3DSTATE_SAMPLE_PATTERN_CommandSubType_bits 2 #define GFX9_3DSTATE_SAMPLE_PATTERN_CommandSubType_bits 2 #define GFX8_3DSTATE_SAMPLE_PATTERN_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLE_PATTERN_CommandSubType_start 27 #define GFX12_3DSTATE_SAMPLE_PATTERN_CommandSubType_start 27 #define GFX11_3DSTATE_SAMPLE_PATTERN_CommandSubType_start 27 #define GFX9_3DSTATE_SAMPLE_PATTERN_CommandSubType_start 27 #define GFX8_3DSTATE_SAMPLE_PATTERN_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLE_PATTERN::Command Type */ #define GFX125_3DSTATE_SAMPLE_PATTERN_CommandType_bits 3 #define GFX12_3DSTATE_SAMPLE_PATTERN_CommandType_bits 3 #define GFX11_3DSTATE_SAMPLE_PATTERN_CommandType_bits 3 #define GFX9_3DSTATE_SAMPLE_PATTERN_CommandType_bits 3 #define GFX8_3DSTATE_SAMPLE_PATTERN_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLE_PATTERN_CommandType_start 29 #define GFX12_3DSTATE_SAMPLE_PATTERN_CommandType_start 29 #define GFX11_3DSTATE_SAMPLE_PATTERN_CommandType_start 29 #define GFX9_3DSTATE_SAMPLE_PATTERN_CommandType_start 29 #define GFX8_3DSTATE_SAMPLE_PATTERN_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SAMPLE_PATTERN::DWord Length */ #define GFX125_3DSTATE_SAMPLE_PATTERN_DWordLength_bits 8 #define GFX12_3DSTATE_SAMPLE_PATTERN_DWordLength_bits 8 #define GFX11_3DSTATE_SAMPLE_PATTERN_DWordLength_bits 8 #define GFX9_3DSTATE_SAMPLE_PATTERN_DWordLength_bits 8 #define GFX8_3DSTATE_SAMPLE_PATTERN_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SAMPLE_PATTERN_DWordLength_start 0 #define GFX12_3DSTATE_SAMPLE_PATTERN_DWordLength_start 0 #define GFX11_3DSTATE_SAMPLE_PATTERN_DWordLength_start 0 #define GFX9_3DSTATE_SAMPLE_PATTERN_DWordLength_start 0 #define GFX8_3DSTATE_SAMPLE_PATTERN_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SAMPLE_PATTERN_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SBE */ #define GFX125_3DSTATE_SBE_length 6 #define GFX12_3DSTATE_SBE_length 6 #define GFX11_3DSTATE_SBE_length 6 #define GFX9_3DSTATE_SBE_length 6 #define GFX8_3DSTATE_SBE_length 4 #define GFX75_3DSTATE_SBE_length 14 #define GFX7_3DSTATE_SBE_length 14 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 4; case 75: return 14; case 70: return 14; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SBE::3D Command Opcode */ #define GFX125_3DSTATE_SBE_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_SBE_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_SBE_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_SBE_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_SBE_3DCommandOpcode_bits 3 #define GFX75_3DSTATE_SBE_3DCommandOpcode_bits 3 #define GFX7_3DSTATE_SBE_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SBE_3DCommandOpcode_start 24 #define GFX12_3DSTATE_SBE_3DCommandOpcode_start 24 #define GFX11_3DSTATE_SBE_3DCommandOpcode_start 24 #define GFX9_3DSTATE_SBE_3DCommandOpcode_start 24 #define GFX8_3DSTATE_SBE_3DCommandOpcode_start 24 #define GFX75_3DSTATE_SBE_3DCommandOpcode_start 24 #define GFX7_3DSTATE_SBE_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SBE::3D Command Sub Opcode */ #define GFX125_3DSTATE_SBE_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_SBE_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_SBE_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_SBE_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_SBE_3DCommandSubOpcode_bits 8 #define GFX75_3DSTATE_SBE_3DCommandSubOpcode_bits 8 #define GFX7_3DSTATE_SBE_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SBE_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_SBE_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_SBE_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_SBE_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_SBE_3DCommandSubOpcode_start 16 #define GFX75_3DSTATE_SBE_3DCommandSubOpcode_start 16 #define GFX7_3DSTATE_SBE_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SBE::Attribute 0 WrapShortest Enables */ #define GFX75_3DSTATE_SBE_Attribute0WrapShortestEnables_bits 4 #define GFX7_3DSTATE_SBE_Attribute0WrapShortestEnables_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_Attribute0WrapShortestEnables_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 4; case 70: return 4; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_SBE_Attribute0WrapShortestEnables_start 384 #define GFX7_3DSTATE_SBE_Attribute0WrapShortestEnables_start 384 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_Attribute0WrapShortestEnables_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 384; case 70: return 384; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SBE::Attribute 10 WrapShortest Enables */ #define GFX75_3DSTATE_SBE_Attribute10WrapShortestEnables_bits 4 #define GFX7_3DSTATE_SBE_Attribute10WrapShortestEnables_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_Attribute10WrapShortestEnables_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 4; case 70: return 4; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_SBE_Attribute10WrapShortestEnables_start 424 #define GFX7_3DSTATE_SBE_Attribute10WrapShortestEnables_start 424 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_Attribute10WrapShortestEnables_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 424; case 70: return 424; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SBE::Attribute 11 WrapShortest Enables */ #define GFX75_3DSTATE_SBE_Attribute11WrapShortestEnables_bits 4 #define GFX7_3DSTATE_SBE_Attribute11WrapShortestEnables_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_Attribute11WrapShortestEnables_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 4; case 70: return 4; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_SBE_Attribute11WrapShortestEnables_start 428 #define GFX7_3DSTATE_SBE_Attribute11WrapShortestEnables_start 428 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_Attribute11WrapShortestEnables_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 428; case 70: return 428; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SBE::Attribute 12 WrapShortest Enables */ #define GFX75_3DSTATE_SBE_Attribute12WrapShortestEnables_bits 4 #define GFX7_3DSTATE_SBE_Attribute12WrapShortestEnables_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_Attribute12WrapShortestEnables_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 4; case 70: return 4; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_SBE_Attribute12WrapShortestEnables_start 432 #define GFX7_3DSTATE_SBE_Attribute12WrapShortestEnables_start 432 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_Attribute12WrapShortestEnables_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 432; case 70: return 432; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SBE::Attribute 13 WrapShortest Enables */ #define GFX75_3DSTATE_SBE_Attribute13WrapShortestEnables_bits 4 #define GFX7_3DSTATE_SBE_Attribute13WrapShortestEnables_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_Attribute13WrapShortestEnables_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 4; case 70: return 4; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_SBE_Attribute13WrapShortestEnables_start 436 #define GFX7_3DSTATE_SBE_Attribute13WrapShortestEnables_start 436 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_Attribute13WrapShortestEnables_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 436; case 70: return 436; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SBE::Attribute 14 WrapShortest Enables */ #define GFX75_3DSTATE_SBE_Attribute14WrapShortestEnables_bits 4 #define GFX7_3DSTATE_SBE_Attribute14WrapShortestEnables_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_Attribute14WrapShortestEnables_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 4; case 70: return 4; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_SBE_Attribute14WrapShortestEnables_start 440 #define GFX7_3DSTATE_SBE_Attribute14WrapShortestEnables_start 440 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_Attribute14WrapShortestEnables_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 440; case 70: return 440; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SBE::Attribute 15 WrapShortest Enables */ #define GFX75_3DSTATE_SBE_Attribute15WrapShortestEnables_bits 4 #define GFX7_3DSTATE_SBE_Attribute15WrapShortestEnables_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_Attribute15WrapShortestEnables_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 4; case 70: return 4; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_SBE_Attribute15WrapShortestEnables_start 444 #define GFX7_3DSTATE_SBE_Attribute15WrapShortestEnables_start 444 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_Attribute15WrapShortestEnables_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 444; case 70: return 444; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SBE::Attribute 1 WrapShortest Enables */ #define GFX75_3DSTATE_SBE_Attribute1WrapShortestEnables_bits 4 #define GFX7_3DSTATE_SBE_Attribute1WrapShortestEnables_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_Attribute1WrapShortestEnables_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 4; case 70: return 4; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_SBE_Attribute1WrapShortestEnables_start 388 #define GFX7_3DSTATE_SBE_Attribute1WrapShortestEnables_start 388 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_Attribute1WrapShortestEnables_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 388; case 70: return 388; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SBE::Attribute 2 WrapShortest Enables */ #define GFX75_3DSTATE_SBE_Attribute2WrapShortestEnables_bits 4 #define GFX7_3DSTATE_SBE_Attribute2WrapShortestEnables_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_Attribute2WrapShortestEnables_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 4; case 70: return 4; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_SBE_Attribute2WrapShortestEnables_start 392 #define GFX7_3DSTATE_SBE_Attribute2WrapShortestEnables_start 392 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_Attribute2WrapShortestEnables_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 392; case 70: return 392; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SBE::Attribute 3 WrapShortest Enables */ #define GFX75_3DSTATE_SBE_Attribute3WrapShortestEnables_bits 4 #define GFX7_3DSTATE_SBE_Attribute3WrapShortestEnables_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_Attribute3WrapShortestEnables_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 4; case 70: return 4; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_SBE_Attribute3WrapShortestEnables_start 396 #define GFX7_3DSTATE_SBE_Attribute3WrapShortestEnables_start 396 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_Attribute3WrapShortestEnables_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 396; case 70: return 396; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SBE::Attribute 4 WrapShortest Enables */ #define GFX75_3DSTATE_SBE_Attribute4WrapShortestEnables_bits 4 #define GFX7_3DSTATE_SBE_Attribute4WrapShortestEnables_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_Attribute4WrapShortestEnables_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 4; case 70: return 4; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_SBE_Attribute4WrapShortestEnables_start 400 #define GFX7_3DSTATE_SBE_Attribute4WrapShortestEnables_start 400 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_Attribute4WrapShortestEnables_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 400; case 70: return 400; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SBE::Attribute 5 WrapShortest Enables */ #define GFX75_3DSTATE_SBE_Attribute5WrapShortestEnables_bits 4 #define GFX7_3DSTATE_SBE_Attribute5WrapShortestEnables_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_Attribute5WrapShortestEnables_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 4; case 70: return 4; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_SBE_Attribute5WrapShortestEnables_start 404 #define GFX7_3DSTATE_SBE_Attribute5WrapShortestEnables_start 404 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_Attribute5WrapShortestEnables_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 404; case 70: return 404; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SBE::Attribute 6 WrapShortest Enables */ #define GFX75_3DSTATE_SBE_Attribute6WrapShortestEnables_bits 4 #define GFX7_3DSTATE_SBE_Attribute6WrapShortestEnables_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_Attribute6WrapShortestEnables_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 4; case 70: return 4; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_SBE_Attribute6WrapShortestEnables_start 408 #define GFX7_3DSTATE_SBE_Attribute6WrapShortestEnables_start 408 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_Attribute6WrapShortestEnables_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 408; case 70: return 408; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SBE::Attribute 7 WrapShortest Enables */ #define GFX75_3DSTATE_SBE_Attribute7WrapShortestEnables_bits 4 #define GFX7_3DSTATE_SBE_Attribute7WrapShortestEnables_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_Attribute7WrapShortestEnables_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 4; case 70: return 4; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_SBE_Attribute7WrapShortestEnables_start 412 #define GFX7_3DSTATE_SBE_Attribute7WrapShortestEnables_start 412 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_Attribute7WrapShortestEnables_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 412; case 70: return 412; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SBE::Attribute 8 WrapShortest Enables */ #define GFX75_3DSTATE_SBE_Attribute8WrapShortestEnables_bits 4 #define GFX7_3DSTATE_SBE_Attribute8WrapShortestEnables_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_Attribute8WrapShortestEnables_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 4; case 70: return 4; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_SBE_Attribute8WrapShortestEnables_start 416 #define GFX7_3DSTATE_SBE_Attribute8WrapShortestEnables_start 416 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_Attribute8WrapShortestEnables_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 416; case 70: return 416; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SBE::Attribute 9 WrapShortest Enables */ #define GFX75_3DSTATE_SBE_Attribute9WrapShortestEnables_bits 4 #define GFX7_3DSTATE_SBE_Attribute9WrapShortestEnables_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_Attribute9WrapShortestEnables_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 4; case 70: return 4; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_SBE_Attribute9WrapShortestEnables_start 420 #define GFX7_3DSTATE_SBE_Attribute9WrapShortestEnables_start 420 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_Attribute9WrapShortestEnables_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 420; case 70: return 420; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SBE::Attribute Swizzle Control Mode */ #define GFX75_3DSTATE_SBE_AttributeSwizzleControlMode_bits 1 #define GFX7_3DSTATE_SBE_AttributeSwizzleControlMode_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_AttributeSwizzleControlMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_SBE_AttributeSwizzleControlMode_start 60 #define GFX7_3DSTATE_SBE_AttributeSwizzleControlMode_start 60 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_AttributeSwizzleControlMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 60; case 70: return 60; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SBE::Attribute Swizzle Enable */ #define GFX125_3DSTATE_SBE_AttributeSwizzleEnable_bits 1 #define GFX12_3DSTATE_SBE_AttributeSwizzleEnable_bits 1 #define GFX11_3DSTATE_SBE_AttributeSwizzleEnable_bits 1 #define GFX9_3DSTATE_SBE_AttributeSwizzleEnable_bits 1 #define GFX8_3DSTATE_SBE_AttributeSwizzleEnable_bits 1 #define GFX75_3DSTATE_SBE_AttributeSwizzleEnable_bits 1 #define GFX7_3DSTATE_SBE_AttributeSwizzleEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_AttributeSwizzleEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SBE_AttributeSwizzleEnable_start 53 #define GFX12_3DSTATE_SBE_AttributeSwizzleEnable_start 53 #define GFX11_3DSTATE_SBE_AttributeSwizzleEnable_start 53 #define GFX9_3DSTATE_SBE_AttributeSwizzleEnable_start 53 #define GFX8_3DSTATE_SBE_AttributeSwizzleEnable_start 53 #define GFX75_3DSTATE_SBE_AttributeSwizzleEnable_start 53 #define GFX7_3DSTATE_SBE_AttributeSwizzleEnable_start 53 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_AttributeSwizzleEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 53; case 120: return 53; case 110: return 53; case 90: return 53; case 80: return 53; case 75: return 53; case 70: return 53; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SBE::Command SubType */ #define GFX125_3DSTATE_SBE_CommandSubType_bits 2 #define GFX12_3DSTATE_SBE_CommandSubType_bits 2 #define GFX11_3DSTATE_SBE_CommandSubType_bits 2 #define GFX9_3DSTATE_SBE_CommandSubType_bits 2 #define GFX8_3DSTATE_SBE_CommandSubType_bits 2 #define GFX75_3DSTATE_SBE_CommandSubType_bits 2 #define GFX7_3DSTATE_SBE_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SBE_CommandSubType_start 27 #define GFX12_3DSTATE_SBE_CommandSubType_start 27 #define GFX11_3DSTATE_SBE_CommandSubType_start 27 #define GFX9_3DSTATE_SBE_CommandSubType_start 27 #define GFX8_3DSTATE_SBE_CommandSubType_start 27 #define GFX75_3DSTATE_SBE_CommandSubType_start 27 #define GFX7_3DSTATE_SBE_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SBE::Command Type */ #define GFX125_3DSTATE_SBE_CommandType_bits 3 #define GFX12_3DSTATE_SBE_CommandType_bits 3 #define GFX11_3DSTATE_SBE_CommandType_bits 3 #define GFX9_3DSTATE_SBE_CommandType_bits 3 #define GFX8_3DSTATE_SBE_CommandType_bits 3 #define GFX75_3DSTATE_SBE_CommandType_bits 3 #define GFX7_3DSTATE_SBE_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SBE_CommandType_start 29 #define GFX12_3DSTATE_SBE_CommandType_start 29 #define GFX11_3DSTATE_SBE_CommandType_start 29 #define GFX9_3DSTATE_SBE_CommandType_start 29 #define GFX8_3DSTATE_SBE_CommandType_start 29 #define GFX75_3DSTATE_SBE_CommandType_start 29 #define GFX7_3DSTATE_SBE_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SBE::Constant Interpolation Enable */ #define GFX125_3DSTATE_SBE_ConstantInterpolationEnable_bits 32 #define GFX12_3DSTATE_SBE_ConstantInterpolationEnable_bits 32 #define GFX11_3DSTATE_SBE_ConstantInterpolationEnable_bits 32 #define GFX9_3DSTATE_SBE_ConstantInterpolationEnable_bits 32 #define GFX8_3DSTATE_SBE_ConstantInterpolationEnable_bits 32 #define GFX75_3DSTATE_SBE_ConstantInterpolationEnable_bits 32 #define GFX7_3DSTATE_SBE_ConstantInterpolationEnable_bits 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_ConstantInterpolationEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SBE_ConstantInterpolationEnable_start 96 #define GFX12_3DSTATE_SBE_ConstantInterpolationEnable_start 96 #define GFX11_3DSTATE_SBE_ConstantInterpolationEnable_start 96 #define GFX9_3DSTATE_SBE_ConstantInterpolationEnable_start 96 #define GFX8_3DSTATE_SBE_ConstantInterpolationEnable_start 96 #define GFX75_3DSTATE_SBE_ConstantInterpolationEnable_start 352 #define GFX7_3DSTATE_SBE_ConstantInterpolationEnable_start 352 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_ConstantInterpolationEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 96; case 120: return 96; case 110: return 96; case 90: return 96; case 80: return 96; case 75: return 352; case 70: return 352; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SBE::DWord Length */ #define GFX125_3DSTATE_SBE_DWordLength_bits 8 #define GFX12_3DSTATE_SBE_DWordLength_bits 8 #define GFX11_3DSTATE_SBE_DWordLength_bits 8 #define GFX9_3DSTATE_SBE_DWordLength_bits 8 #define GFX8_3DSTATE_SBE_DWordLength_bits 8 #define GFX75_3DSTATE_SBE_DWordLength_bits 8 #define GFX7_3DSTATE_SBE_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SBE_DWordLength_start 0 #define GFX12_3DSTATE_SBE_DWordLength_start 0 #define GFX11_3DSTATE_SBE_DWordLength_start 0 #define GFX9_3DSTATE_SBE_DWordLength_start 0 #define GFX8_3DSTATE_SBE_DWordLength_start 0 #define GFX75_3DSTATE_SBE_DWordLength_start 0 #define GFX7_3DSTATE_SBE_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SBE::Force Vertex URB Entry Read Length */ #define GFX125_3DSTATE_SBE_ForceVertexURBEntryReadLength_bits 1 #define GFX12_3DSTATE_SBE_ForceVertexURBEntryReadLength_bits 1 #define GFX11_3DSTATE_SBE_ForceVertexURBEntryReadLength_bits 1 #define GFX9_3DSTATE_SBE_ForceVertexURBEntryReadLength_bits 1 #define GFX8_3DSTATE_SBE_ForceVertexURBEntryReadLength_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_ForceVertexURBEntryReadLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SBE_ForceVertexURBEntryReadLength_start 61 #define GFX12_3DSTATE_SBE_ForceVertexURBEntryReadLength_start 61 #define GFX11_3DSTATE_SBE_ForceVertexURBEntryReadLength_start 61 #define GFX9_3DSTATE_SBE_ForceVertexURBEntryReadLength_start 61 #define GFX8_3DSTATE_SBE_ForceVertexURBEntryReadLength_start 61 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_ForceVertexURBEntryReadLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 61; case 120: return 61; case 110: return 61; case 90: return 61; case 80: return 61; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SBE::Force Vertex URB Entry Read Offset */ #define GFX125_3DSTATE_SBE_ForceVertexURBEntryReadOffset_bits 1 #define GFX12_3DSTATE_SBE_ForceVertexURBEntryReadOffset_bits 1 #define GFX11_3DSTATE_SBE_ForceVertexURBEntryReadOffset_bits 1 #define GFX9_3DSTATE_SBE_ForceVertexURBEntryReadOffset_bits 1 #define GFX8_3DSTATE_SBE_ForceVertexURBEntryReadOffset_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_ForceVertexURBEntryReadOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SBE_ForceVertexURBEntryReadOffset_start 60 #define GFX12_3DSTATE_SBE_ForceVertexURBEntryReadOffset_start 60 #define GFX11_3DSTATE_SBE_ForceVertexURBEntryReadOffset_start 60 #define GFX9_3DSTATE_SBE_ForceVertexURBEntryReadOffset_start 60 #define GFX8_3DSTATE_SBE_ForceVertexURBEntryReadOffset_start 60 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_ForceVertexURBEntryReadOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 60; case 120: return 60; case 110: return 60; case 90: return 60; case 80: return 60; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SBE::Number of SF Output Attributes */ #define GFX125_3DSTATE_SBE_NumberofSFOutputAttributes_bits 6 #define GFX12_3DSTATE_SBE_NumberofSFOutputAttributes_bits 6 #define GFX11_3DSTATE_SBE_NumberofSFOutputAttributes_bits 6 #define GFX9_3DSTATE_SBE_NumberofSFOutputAttributes_bits 6 #define GFX8_3DSTATE_SBE_NumberofSFOutputAttributes_bits 6 #define GFX75_3DSTATE_SBE_NumberofSFOutputAttributes_bits 6 #define GFX7_3DSTATE_SBE_NumberofSFOutputAttributes_bits 6 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_NumberofSFOutputAttributes_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 6; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SBE_NumberofSFOutputAttributes_start 54 #define GFX12_3DSTATE_SBE_NumberofSFOutputAttributes_start 54 #define GFX11_3DSTATE_SBE_NumberofSFOutputAttributes_start 54 #define GFX9_3DSTATE_SBE_NumberofSFOutputAttributes_start 54 #define GFX8_3DSTATE_SBE_NumberofSFOutputAttributes_start 54 #define GFX75_3DSTATE_SBE_NumberofSFOutputAttributes_start 54 #define GFX7_3DSTATE_SBE_NumberofSFOutputAttributes_start 54 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_NumberofSFOutputAttributes_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 54; case 120: return 54; case 110: return 54; case 90: return 54; case 80: return 54; case 75: return 54; case 70: return 54; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SBE::Point Sprite Texture Coordinate Enable */ #define GFX125_3DSTATE_SBE_PointSpriteTextureCoordinateEnable_bits 32 #define GFX12_3DSTATE_SBE_PointSpriteTextureCoordinateEnable_bits 32 #define GFX11_3DSTATE_SBE_PointSpriteTextureCoordinateEnable_bits 32 #define GFX9_3DSTATE_SBE_PointSpriteTextureCoordinateEnable_bits 32 #define GFX8_3DSTATE_SBE_PointSpriteTextureCoordinateEnable_bits 32 #define GFX75_3DSTATE_SBE_PointSpriteTextureCoordinateEnable_bits 32 #define GFX7_3DSTATE_SBE_PointSpriteTextureCoordinateEnable_bits 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_PointSpriteTextureCoordinateEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SBE_PointSpriteTextureCoordinateEnable_start 64 #define GFX12_3DSTATE_SBE_PointSpriteTextureCoordinateEnable_start 64 #define GFX11_3DSTATE_SBE_PointSpriteTextureCoordinateEnable_start 64 #define GFX9_3DSTATE_SBE_PointSpriteTextureCoordinateEnable_start 64 #define GFX8_3DSTATE_SBE_PointSpriteTextureCoordinateEnable_start 64 #define GFX75_3DSTATE_SBE_PointSpriteTextureCoordinateEnable_start 320 #define GFX7_3DSTATE_SBE_PointSpriteTextureCoordinateEnable_start 320 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_PointSpriteTextureCoordinateEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 64; case 80: return 64; case 75: return 320; case 70: return 320; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SBE::Point Sprite Texture Coordinate Origin */ #define GFX125_3DSTATE_SBE_PointSpriteTextureCoordinateOrigin_bits 1 #define GFX12_3DSTATE_SBE_PointSpriteTextureCoordinateOrigin_bits 1 #define GFX11_3DSTATE_SBE_PointSpriteTextureCoordinateOrigin_bits 1 #define GFX9_3DSTATE_SBE_PointSpriteTextureCoordinateOrigin_bits 1 #define GFX8_3DSTATE_SBE_PointSpriteTextureCoordinateOrigin_bits 1 #define GFX75_3DSTATE_SBE_PointSpriteTextureCoordinateOrigin_bits 1 #define GFX7_3DSTATE_SBE_PointSpriteTextureCoordinateOrigin_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_PointSpriteTextureCoordinateOrigin_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SBE_PointSpriteTextureCoordinateOrigin_start 52 #define GFX12_3DSTATE_SBE_PointSpriteTextureCoordinateOrigin_start 52 #define GFX11_3DSTATE_SBE_PointSpriteTextureCoordinateOrigin_start 52 #define GFX9_3DSTATE_SBE_PointSpriteTextureCoordinateOrigin_start 52 #define GFX8_3DSTATE_SBE_PointSpriteTextureCoordinateOrigin_start 52 #define GFX75_3DSTATE_SBE_PointSpriteTextureCoordinateOrigin_start 52 #define GFX7_3DSTATE_SBE_PointSpriteTextureCoordinateOrigin_start 52 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_PointSpriteTextureCoordinateOrigin_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 52; case 120: return 52; case 110: return 52; case 90: return 52; case 80: return 52; case 75: return 52; case 70: return 52; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SBE::Primitive ID Override Attribute Select */ #define GFX125_3DSTATE_SBE_PrimitiveIDOverrideAttributeSelect_bits 5 #define GFX12_3DSTATE_SBE_PrimitiveIDOverrideAttributeSelect_bits 5 #define GFX11_3DSTATE_SBE_PrimitiveIDOverrideAttributeSelect_bits 5 #define GFX9_3DSTATE_SBE_PrimitiveIDOverrideAttributeSelect_bits 5 #define GFX8_3DSTATE_SBE_PrimitiveIDOverrideAttributeSelect_bits 5 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_PrimitiveIDOverrideAttributeSelect_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 5; case 110: return 5; case 90: return 5; case 80: return 5; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SBE_PrimitiveIDOverrideAttributeSelect_start 32 #define GFX12_3DSTATE_SBE_PrimitiveIDOverrideAttributeSelect_start 32 #define GFX11_3DSTATE_SBE_PrimitiveIDOverrideAttributeSelect_start 32 #define GFX9_3DSTATE_SBE_PrimitiveIDOverrideAttributeSelect_start 32 #define GFX8_3DSTATE_SBE_PrimitiveIDOverrideAttributeSelect_start 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_PrimitiveIDOverrideAttributeSelect_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SBE::Primitive ID Override Component W */ #define GFX125_3DSTATE_SBE_PrimitiveIDOverrideComponentW_bits 1 #define GFX12_3DSTATE_SBE_PrimitiveIDOverrideComponentW_bits 1 #define GFX11_3DSTATE_SBE_PrimitiveIDOverrideComponentW_bits 1 #define GFX9_3DSTATE_SBE_PrimitiveIDOverrideComponentW_bits 1 #define GFX8_3DSTATE_SBE_PrimitiveIDOverrideComponentW_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_PrimitiveIDOverrideComponentW_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SBE_PrimitiveIDOverrideComponentW_start 51 #define GFX12_3DSTATE_SBE_PrimitiveIDOverrideComponentW_start 51 #define GFX11_3DSTATE_SBE_PrimitiveIDOverrideComponentW_start 51 #define GFX9_3DSTATE_SBE_PrimitiveIDOverrideComponentW_start 51 #define GFX8_3DSTATE_SBE_PrimitiveIDOverrideComponentW_start 51 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_PrimitiveIDOverrideComponentW_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 51; case 120: return 51; case 110: return 51; case 90: return 51; case 80: return 51; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SBE::Primitive ID Override Component X */ #define GFX125_3DSTATE_SBE_PrimitiveIDOverrideComponentX_bits 1 #define GFX12_3DSTATE_SBE_PrimitiveIDOverrideComponentX_bits 1 #define GFX11_3DSTATE_SBE_PrimitiveIDOverrideComponentX_bits 1 #define GFX9_3DSTATE_SBE_PrimitiveIDOverrideComponentX_bits 1 #define GFX8_3DSTATE_SBE_PrimitiveIDOverrideComponentX_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_PrimitiveIDOverrideComponentX_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SBE_PrimitiveIDOverrideComponentX_start 48 #define GFX12_3DSTATE_SBE_PrimitiveIDOverrideComponentX_start 48 #define GFX11_3DSTATE_SBE_PrimitiveIDOverrideComponentX_start 48 #define GFX9_3DSTATE_SBE_PrimitiveIDOverrideComponentX_start 48 #define GFX8_3DSTATE_SBE_PrimitiveIDOverrideComponentX_start 48 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_PrimitiveIDOverrideComponentX_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 48; case 120: return 48; case 110: return 48; case 90: return 48; case 80: return 48; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SBE::Primitive ID Override Component Y */ #define GFX125_3DSTATE_SBE_PrimitiveIDOverrideComponentY_bits 1 #define GFX12_3DSTATE_SBE_PrimitiveIDOverrideComponentY_bits 1 #define GFX11_3DSTATE_SBE_PrimitiveIDOverrideComponentY_bits 1 #define GFX9_3DSTATE_SBE_PrimitiveIDOverrideComponentY_bits 1 #define GFX8_3DSTATE_SBE_PrimitiveIDOverrideComponentY_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_PrimitiveIDOverrideComponentY_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SBE_PrimitiveIDOverrideComponentY_start 49 #define GFX12_3DSTATE_SBE_PrimitiveIDOverrideComponentY_start 49 #define GFX11_3DSTATE_SBE_PrimitiveIDOverrideComponentY_start 49 #define GFX9_3DSTATE_SBE_PrimitiveIDOverrideComponentY_start 49 #define GFX8_3DSTATE_SBE_PrimitiveIDOverrideComponentY_start 49 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_PrimitiveIDOverrideComponentY_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 49; case 120: return 49; case 110: return 49; case 90: return 49; case 80: return 49; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SBE::Primitive ID Override Component Z */ #define GFX125_3DSTATE_SBE_PrimitiveIDOverrideComponentZ_bits 1 #define GFX12_3DSTATE_SBE_PrimitiveIDOverrideComponentZ_bits 1 #define GFX11_3DSTATE_SBE_PrimitiveIDOverrideComponentZ_bits 1 #define GFX9_3DSTATE_SBE_PrimitiveIDOverrideComponentZ_bits 1 #define GFX8_3DSTATE_SBE_PrimitiveIDOverrideComponentZ_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_PrimitiveIDOverrideComponentZ_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SBE_PrimitiveIDOverrideComponentZ_start 50 #define GFX12_3DSTATE_SBE_PrimitiveIDOverrideComponentZ_start 50 #define GFX11_3DSTATE_SBE_PrimitiveIDOverrideComponentZ_start 50 #define GFX9_3DSTATE_SBE_PrimitiveIDOverrideComponentZ_start 50 #define GFX8_3DSTATE_SBE_PrimitiveIDOverrideComponentZ_start 50 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_PrimitiveIDOverrideComponentZ_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 50; case 120: return 50; case 110: return 50; case 90: return 50; case 80: return 50; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SBE::Vertex URB Entry Read Length */ #define GFX125_3DSTATE_SBE_VertexURBEntryReadLength_bits 5 #define GFX12_3DSTATE_SBE_VertexURBEntryReadLength_bits 5 #define GFX11_3DSTATE_SBE_VertexURBEntryReadLength_bits 5 #define GFX9_3DSTATE_SBE_VertexURBEntryReadLength_bits 5 #define GFX8_3DSTATE_SBE_VertexURBEntryReadLength_bits 5 #define GFX75_3DSTATE_SBE_VertexURBEntryReadLength_bits 5 #define GFX7_3DSTATE_SBE_VertexURBEntryReadLength_bits 5 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_VertexURBEntryReadLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 5; case 110: return 5; case 90: return 5; case 80: return 5; case 75: return 5; case 70: return 5; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SBE_VertexURBEntryReadLength_start 43 #define GFX12_3DSTATE_SBE_VertexURBEntryReadLength_start 43 #define GFX11_3DSTATE_SBE_VertexURBEntryReadLength_start 43 #define GFX9_3DSTATE_SBE_VertexURBEntryReadLength_start 43 #define GFX8_3DSTATE_SBE_VertexURBEntryReadLength_start 43 #define GFX75_3DSTATE_SBE_VertexURBEntryReadLength_start 43 #define GFX7_3DSTATE_SBE_VertexURBEntryReadLength_start 43 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_VertexURBEntryReadLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 43; case 120: return 43; case 110: return 43; case 90: return 43; case 80: return 43; case 75: return 43; case 70: return 43; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SBE::Vertex URB Entry Read Offset */ #define GFX125_3DSTATE_SBE_VertexURBEntryReadOffset_bits 6 #define GFX12_3DSTATE_SBE_VertexURBEntryReadOffset_bits 6 #define GFX11_3DSTATE_SBE_VertexURBEntryReadOffset_bits 6 #define GFX9_3DSTATE_SBE_VertexURBEntryReadOffset_bits 6 #define GFX8_3DSTATE_SBE_VertexURBEntryReadOffset_bits 6 #define GFX75_3DSTATE_SBE_VertexURBEntryReadOffset_bits 6 #define GFX7_3DSTATE_SBE_VertexURBEntryReadOffset_bits 6 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_VertexURBEntryReadOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 6; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SBE_VertexURBEntryReadOffset_start 37 #define GFX12_3DSTATE_SBE_VertexURBEntryReadOffset_start 37 #define GFX11_3DSTATE_SBE_VertexURBEntryReadOffset_start 37 #define GFX9_3DSTATE_SBE_VertexURBEntryReadOffset_start 37 #define GFX8_3DSTATE_SBE_VertexURBEntryReadOffset_start 37 #define GFX75_3DSTATE_SBE_VertexURBEntryReadOffset_start 36 #define GFX7_3DSTATE_SBE_VertexURBEntryReadOffset_start 36 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_VertexURBEntryReadOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 37; case 120: return 37; case 110: return 37; case 90: return 37; case 80: return 37; case 75: return 36; case 70: return 36; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SBE_SWIZ */ #define GFX125_3DSTATE_SBE_SWIZ_length 11 #define GFX12_3DSTATE_SBE_SWIZ_length 11 #define GFX11_3DSTATE_SBE_SWIZ_length 11 #define GFX9_3DSTATE_SBE_SWIZ_length 11 #define GFX8_3DSTATE_SBE_SWIZ_length 11 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_SWIZ_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 11; case 120: return 11; case 110: return 11; case 90: return 11; case 80: return 11; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SBE_SWIZ::3D Command Opcode */ #define GFX125_3DSTATE_SBE_SWIZ_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_SBE_SWIZ_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_SBE_SWIZ_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_SBE_SWIZ_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_SBE_SWIZ_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_SWIZ_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SBE_SWIZ_3DCommandOpcode_start 24 #define GFX12_3DSTATE_SBE_SWIZ_3DCommandOpcode_start 24 #define GFX11_3DSTATE_SBE_SWIZ_3DCommandOpcode_start 24 #define GFX9_3DSTATE_SBE_SWIZ_3DCommandOpcode_start 24 #define GFX8_3DSTATE_SBE_SWIZ_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_SWIZ_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SBE_SWIZ::3D Command Sub Opcode */ #define GFX125_3DSTATE_SBE_SWIZ_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_SBE_SWIZ_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_SBE_SWIZ_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_SBE_SWIZ_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_SBE_SWIZ_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_SWIZ_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SBE_SWIZ_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_SBE_SWIZ_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_SBE_SWIZ_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_SBE_SWIZ_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_SBE_SWIZ_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_SWIZ_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SBE_SWIZ::Command SubType */ #define GFX125_3DSTATE_SBE_SWIZ_CommandSubType_bits 2 #define GFX12_3DSTATE_SBE_SWIZ_CommandSubType_bits 2 #define GFX11_3DSTATE_SBE_SWIZ_CommandSubType_bits 2 #define GFX9_3DSTATE_SBE_SWIZ_CommandSubType_bits 2 #define GFX8_3DSTATE_SBE_SWIZ_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_SWIZ_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SBE_SWIZ_CommandSubType_start 27 #define GFX12_3DSTATE_SBE_SWIZ_CommandSubType_start 27 #define GFX11_3DSTATE_SBE_SWIZ_CommandSubType_start 27 #define GFX9_3DSTATE_SBE_SWIZ_CommandSubType_start 27 #define GFX8_3DSTATE_SBE_SWIZ_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_SWIZ_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SBE_SWIZ::Command Type */ #define GFX125_3DSTATE_SBE_SWIZ_CommandType_bits 3 #define GFX12_3DSTATE_SBE_SWIZ_CommandType_bits 3 #define GFX11_3DSTATE_SBE_SWIZ_CommandType_bits 3 #define GFX9_3DSTATE_SBE_SWIZ_CommandType_bits 3 #define GFX8_3DSTATE_SBE_SWIZ_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_SWIZ_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SBE_SWIZ_CommandType_start 29 #define GFX12_3DSTATE_SBE_SWIZ_CommandType_start 29 #define GFX11_3DSTATE_SBE_SWIZ_CommandType_start 29 #define GFX9_3DSTATE_SBE_SWIZ_CommandType_start 29 #define GFX8_3DSTATE_SBE_SWIZ_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_SWIZ_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SBE_SWIZ::DWord Length */ #define GFX125_3DSTATE_SBE_SWIZ_DWordLength_bits 8 #define GFX12_3DSTATE_SBE_SWIZ_DWordLength_bits 8 #define GFX11_3DSTATE_SBE_SWIZ_DWordLength_bits 8 #define GFX9_3DSTATE_SBE_SWIZ_DWordLength_bits 8 #define GFX8_3DSTATE_SBE_SWIZ_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_SWIZ_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SBE_SWIZ_DWordLength_start 0 #define GFX12_3DSTATE_SBE_SWIZ_DWordLength_start 0 #define GFX11_3DSTATE_SBE_SWIZ_DWordLength_start 0 #define GFX9_3DSTATE_SBE_SWIZ_DWordLength_start 0 #define GFX8_3DSTATE_SBE_SWIZ_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SBE_SWIZ_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SCISSOR_STATE_POINTERS */ #define GFX125_3DSTATE_SCISSOR_STATE_POINTERS_length 2 #define GFX12_3DSTATE_SCISSOR_STATE_POINTERS_length 2 #define GFX11_3DSTATE_SCISSOR_STATE_POINTERS_length 2 #define GFX9_3DSTATE_SCISSOR_STATE_POINTERS_length 2 #define GFX8_3DSTATE_SCISSOR_STATE_POINTERS_length 2 #define GFX75_3DSTATE_SCISSOR_STATE_POINTERS_length 2 #define GFX7_3DSTATE_SCISSOR_STATE_POINTERS_length 2 #define GFX6_3DSTATE_SCISSOR_STATE_POINTERS_length 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SCISSOR_STATE_POINTERS_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SCISSOR_STATE_POINTERS::3D Command Opcode */ #define GFX125_3DSTATE_SCISSOR_STATE_POINTERS_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_SCISSOR_STATE_POINTERS_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_SCISSOR_STATE_POINTERS_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_SCISSOR_STATE_POINTERS_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_SCISSOR_STATE_POINTERS_3DCommandOpcode_bits 3 #define GFX75_3DSTATE_SCISSOR_STATE_POINTERS_3DCommandOpcode_bits 3 #define GFX7_3DSTATE_SCISSOR_STATE_POINTERS_3DCommandOpcode_bits 3 #define GFX6_3DSTATE_SCISSOR_STATE_POINTERS_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SCISSOR_STATE_POINTERS_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SCISSOR_STATE_POINTERS_3DCommandOpcode_start 24 #define GFX12_3DSTATE_SCISSOR_STATE_POINTERS_3DCommandOpcode_start 24 #define GFX11_3DSTATE_SCISSOR_STATE_POINTERS_3DCommandOpcode_start 24 #define GFX9_3DSTATE_SCISSOR_STATE_POINTERS_3DCommandOpcode_start 24 #define GFX8_3DSTATE_SCISSOR_STATE_POINTERS_3DCommandOpcode_start 24 #define GFX75_3DSTATE_SCISSOR_STATE_POINTERS_3DCommandOpcode_start 24 #define GFX7_3DSTATE_SCISSOR_STATE_POINTERS_3DCommandOpcode_start 24 #define GFX6_3DSTATE_SCISSOR_STATE_POINTERS_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SCISSOR_STATE_POINTERS_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 24; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SCISSOR_STATE_POINTERS::3D Command Sub Opcode */ #define GFX125_3DSTATE_SCISSOR_STATE_POINTERS_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_SCISSOR_STATE_POINTERS_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_SCISSOR_STATE_POINTERS_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_SCISSOR_STATE_POINTERS_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_SCISSOR_STATE_POINTERS_3DCommandSubOpcode_bits 8 #define GFX75_3DSTATE_SCISSOR_STATE_POINTERS_3DCommandSubOpcode_bits 8 #define GFX7_3DSTATE_SCISSOR_STATE_POINTERS_3DCommandSubOpcode_bits 8 #define GFX6_3DSTATE_SCISSOR_STATE_POINTERS_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SCISSOR_STATE_POINTERS_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SCISSOR_STATE_POINTERS_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_SCISSOR_STATE_POINTERS_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_SCISSOR_STATE_POINTERS_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_SCISSOR_STATE_POINTERS_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_SCISSOR_STATE_POINTERS_3DCommandSubOpcode_start 16 #define GFX75_3DSTATE_SCISSOR_STATE_POINTERS_3DCommandSubOpcode_start 16 #define GFX7_3DSTATE_SCISSOR_STATE_POINTERS_3DCommandSubOpcode_start 16 #define GFX6_3DSTATE_SCISSOR_STATE_POINTERS_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SCISSOR_STATE_POINTERS_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 16; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SCISSOR_STATE_POINTERS::Command SubType */ #define GFX125_3DSTATE_SCISSOR_STATE_POINTERS_CommandSubType_bits 2 #define GFX12_3DSTATE_SCISSOR_STATE_POINTERS_CommandSubType_bits 2 #define GFX11_3DSTATE_SCISSOR_STATE_POINTERS_CommandSubType_bits 2 #define GFX9_3DSTATE_SCISSOR_STATE_POINTERS_CommandSubType_bits 2 #define GFX8_3DSTATE_SCISSOR_STATE_POINTERS_CommandSubType_bits 2 #define GFX75_3DSTATE_SCISSOR_STATE_POINTERS_CommandSubType_bits 2 #define GFX7_3DSTATE_SCISSOR_STATE_POINTERS_CommandSubType_bits 2 #define GFX6_3DSTATE_SCISSOR_STATE_POINTERS_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SCISSOR_STATE_POINTERS_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SCISSOR_STATE_POINTERS_CommandSubType_start 27 #define GFX12_3DSTATE_SCISSOR_STATE_POINTERS_CommandSubType_start 27 #define GFX11_3DSTATE_SCISSOR_STATE_POINTERS_CommandSubType_start 27 #define GFX9_3DSTATE_SCISSOR_STATE_POINTERS_CommandSubType_start 27 #define GFX8_3DSTATE_SCISSOR_STATE_POINTERS_CommandSubType_start 27 #define GFX75_3DSTATE_SCISSOR_STATE_POINTERS_CommandSubType_start 27 #define GFX7_3DSTATE_SCISSOR_STATE_POINTERS_CommandSubType_start 27 #define GFX6_3DSTATE_SCISSOR_STATE_POINTERS_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SCISSOR_STATE_POINTERS_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 27; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SCISSOR_STATE_POINTERS::Command Type */ #define GFX125_3DSTATE_SCISSOR_STATE_POINTERS_CommandType_bits 3 #define GFX12_3DSTATE_SCISSOR_STATE_POINTERS_CommandType_bits 3 #define GFX11_3DSTATE_SCISSOR_STATE_POINTERS_CommandType_bits 3 #define GFX9_3DSTATE_SCISSOR_STATE_POINTERS_CommandType_bits 3 #define GFX8_3DSTATE_SCISSOR_STATE_POINTERS_CommandType_bits 3 #define GFX75_3DSTATE_SCISSOR_STATE_POINTERS_CommandType_bits 3 #define GFX7_3DSTATE_SCISSOR_STATE_POINTERS_CommandType_bits 3 #define GFX6_3DSTATE_SCISSOR_STATE_POINTERS_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SCISSOR_STATE_POINTERS_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SCISSOR_STATE_POINTERS_CommandType_start 29 #define GFX12_3DSTATE_SCISSOR_STATE_POINTERS_CommandType_start 29 #define GFX11_3DSTATE_SCISSOR_STATE_POINTERS_CommandType_start 29 #define GFX9_3DSTATE_SCISSOR_STATE_POINTERS_CommandType_start 29 #define GFX8_3DSTATE_SCISSOR_STATE_POINTERS_CommandType_start 29 #define GFX75_3DSTATE_SCISSOR_STATE_POINTERS_CommandType_start 29 #define GFX7_3DSTATE_SCISSOR_STATE_POINTERS_CommandType_start 29 #define GFX6_3DSTATE_SCISSOR_STATE_POINTERS_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SCISSOR_STATE_POINTERS_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 29; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SCISSOR_STATE_POINTERS::DWord Length */ #define GFX125_3DSTATE_SCISSOR_STATE_POINTERS_DWordLength_bits 8 #define GFX12_3DSTATE_SCISSOR_STATE_POINTERS_DWordLength_bits 8 #define GFX11_3DSTATE_SCISSOR_STATE_POINTERS_DWordLength_bits 8 #define GFX9_3DSTATE_SCISSOR_STATE_POINTERS_DWordLength_bits 8 #define GFX8_3DSTATE_SCISSOR_STATE_POINTERS_DWordLength_bits 8 #define GFX75_3DSTATE_SCISSOR_STATE_POINTERS_DWordLength_bits 8 #define GFX7_3DSTATE_SCISSOR_STATE_POINTERS_DWordLength_bits 8 #define GFX6_3DSTATE_SCISSOR_STATE_POINTERS_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SCISSOR_STATE_POINTERS_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SCISSOR_STATE_POINTERS_DWordLength_start 0 #define GFX12_3DSTATE_SCISSOR_STATE_POINTERS_DWordLength_start 0 #define GFX11_3DSTATE_SCISSOR_STATE_POINTERS_DWordLength_start 0 #define GFX9_3DSTATE_SCISSOR_STATE_POINTERS_DWordLength_start 0 #define GFX8_3DSTATE_SCISSOR_STATE_POINTERS_DWordLength_start 0 #define GFX75_3DSTATE_SCISSOR_STATE_POINTERS_DWordLength_start 0 #define GFX7_3DSTATE_SCISSOR_STATE_POINTERS_DWordLength_start 0 #define GFX6_3DSTATE_SCISSOR_STATE_POINTERS_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SCISSOR_STATE_POINTERS_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SCISSOR_STATE_POINTERS::Scissor Rect Pointer */ #define GFX125_3DSTATE_SCISSOR_STATE_POINTERS_ScissorRectPointer_bits 27 #define GFX12_3DSTATE_SCISSOR_STATE_POINTERS_ScissorRectPointer_bits 27 #define GFX11_3DSTATE_SCISSOR_STATE_POINTERS_ScissorRectPointer_bits 27 #define GFX9_3DSTATE_SCISSOR_STATE_POINTERS_ScissorRectPointer_bits 27 #define GFX8_3DSTATE_SCISSOR_STATE_POINTERS_ScissorRectPointer_bits 27 #define GFX75_3DSTATE_SCISSOR_STATE_POINTERS_ScissorRectPointer_bits 27 #define GFX7_3DSTATE_SCISSOR_STATE_POINTERS_ScissorRectPointer_bits 27 #define GFX6_3DSTATE_SCISSOR_STATE_POINTERS_ScissorRectPointer_bits 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SCISSOR_STATE_POINTERS_ScissorRectPointer_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 27; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SCISSOR_STATE_POINTERS_ScissorRectPointer_start 37 #define GFX12_3DSTATE_SCISSOR_STATE_POINTERS_ScissorRectPointer_start 37 #define GFX11_3DSTATE_SCISSOR_STATE_POINTERS_ScissorRectPointer_start 37 #define GFX9_3DSTATE_SCISSOR_STATE_POINTERS_ScissorRectPointer_start 37 #define GFX8_3DSTATE_SCISSOR_STATE_POINTERS_ScissorRectPointer_start 37 #define GFX75_3DSTATE_SCISSOR_STATE_POINTERS_ScissorRectPointer_start 37 #define GFX7_3DSTATE_SCISSOR_STATE_POINTERS_ScissorRectPointer_start 37 #define GFX6_3DSTATE_SCISSOR_STATE_POINTERS_ScissorRectPointer_start 37 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SCISSOR_STATE_POINTERS_ScissorRectPointer_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 37; case 120: return 37; case 110: return 37; case 90: return 37; case 80: return 37; case 75: return 37; case 70: return 37; case 60: return 37; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SF */ #define GFX125_3DSTATE_SF_length 4 #define GFX12_3DSTATE_SF_length 4 #define GFX11_3DSTATE_SF_length 4 #define GFX9_3DSTATE_SF_length 4 #define GFX8_3DSTATE_SF_length 4 #define GFX75_3DSTATE_SF_length 7 #define GFX7_3DSTATE_SF_length 7 #define GFX6_3DSTATE_SF_length 20 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 7; case 70: return 7; case 60: return 20; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SF::3D Command Opcode */ #define GFX125_3DSTATE_SF_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_SF_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_SF_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_SF_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_SF_3DCommandOpcode_bits 3 #define GFX75_3DSTATE_SF_3DCommandOpcode_bits 3 #define GFX7_3DSTATE_SF_3DCommandOpcode_bits 3 #define GFX6_3DSTATE_SF_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SF_3DCommandOpcode_start 24 #define GFX12_3DSTATE_SF_3DCommandOpcode_start 24 #define GFX11_3DSTATE_SF_3DCommandOpcode_start 24 #define GFX9_3DSTATE_SF_3DCommandOpcode_start 24 #define GFX8_3DSTATE_SF_3DCommandOpcode_start 24 #define GFX75_3DSTATE_SF_3DCommandOpcode_start 24 #define GFX7_3DSTATE_SF_3DCommandOpcode_start 24 #define GFX6_3DSTATE_SF_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 24; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SF::3D Command Sub Opcode */ #define GFX125_3DSTATE_SF_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_SF_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_SF_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_SF_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_SF_3DCommandSubOpcode_bits 8 #define GFX75_3DSTATE_SF_3DCommandSubOpcode_bits 8 #define GFX7_3DSTATE_SF_3DCommandSubOpcode_bits 8 #define GFX6_3DSTATE_SF_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SF_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_SF_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_SF_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_SF_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_SF_3DCommandSubOpcode_start 16 #define GFX75_3DSTATE_SF_3DCommandSubOpcode_start 16 #define GFX7_3DSTATE_SF_3DCommandSubOpcode_start 16 #define GFX6_3DSTATE_SF_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 16; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SF::AA Line Distance Mode */ #define GFX125_3DSTATE_SF_AALineDistanceMode_bits 1 #define GFX12_3DSTATE_SF_AALineDistanceMode_bits 1 #define GFX11_3DSTATE_SF_AALineDistanceMode_bits 1 #define GFX9_3DSTATE_SF_AALineDistanceMode_bits 1 #define GFX8_3DSTATE_SF_AALineDistanceMode_bits 1 #define GFX75_3DSTATE_SF_AALineDistanceMode_bits 1 #define GFX7_3DSTATE_SF_AALineDistanceMode_bits 1 #define GFX6_3DSTATE_SF_AALineDistanceMode_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_AALineDistanceMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SF_AALineDistanceMode_start 110 #define GFX12_3DSTATE_SF_AALineDistanceMode_start 110 #define GFX11_3DSTATE_SF_AALineDistanceMode_start 110 #define GFX9_3DSTATE_SF_AALineDistanceMode_start 110 #define GFX8_3DSTATE_SF_AALineDistanceMode_start 110 #define GFX75_3DSTATE_SF_AALineDistanceMode_start 110 #define GFX7_3DSTATE_SF_AALineDistanceMode_start 110 #define GFX6_3DSTATE_SF_AALineDistanceMode_start 142 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_AALineDistanceMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 110; case 120: return 110; case 110: return 110; case 90: return 110; case 80: return 110; case 75: return 110; case 70: return 110; case 60: return 142; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SF::Antialiasing Enable */ #define GFX75_3DSTATE_SF_AntialiasingEnable_bits 1 #define GFX7_3DSTATE_SF_AntialiasingEnable_bits 1 #define GFX6_3DSTATE_SF_AntialiasingEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_AntialiasingEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_SF_AntialiasingEnable_start 95 #define GFX7_3DSTATE_SF_AntialiasingEnable_start 95 #define GFX6_3DSTATE_SF_AntialiasingEnable_start 127 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_AntialiasingEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 95; case 70: return 95; case 60: return 127; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SF::Attribute 0 WrapShortest Enables */ #define GFX6_3DSTATE_SF_Attribute0WrapShortestEnables_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_Attribute0WrapShortestEnables_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_SF_Attribute0WrapShortestEnables_start 576 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_Attribute0WrapShortestEnables_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 576; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SF::Attribute 10 WrapShortest Enables */ #define GFX6_3DSTATE_SF_Attribute10WrapShortestEnables_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_Attribute10WrapShortestEnables_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_SF_Attribute10WrapShortestEnables_start 616 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_Attribute10WrapShortestEnables_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 616; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SF::Attribute 11 WrapShortest Enables */ #define GFX6_3DSTATE_SF_Attribute11WrapShortestEnables_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_Attribute11WrapShortestEnables_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_SF_Attribute11WrapShortestEnables_start 620 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_Attribute11WrapShortestEnables_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 620; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SF::Attribute 12 WrapShortest Enables */ #define GFX6_3DSTATE_SF_Attribute12WrapShortestEnables_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_Attribute12WrapShortestEnables_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_SF_Attribute12WrapShortestEnables_start 624 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_Attribute12WrapShortestEnables_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 624; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SF::Attribute 13 WrapShortest Enables */ #define GFX6_3DSTATE_SF_Attribute13WrapShortestEnables_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_Attribute13WrapShortestEnables_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_SF_Attribute13WrapShortestEnables_start 628 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_Attribute13WrapShortestEnables_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 628; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SF::Attribute 14 WrapShortest Enables */ #define GFX6_3DSTATE_SF_Attribute14WrapShortestEnables_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_Attribute14WrapShortestEnables_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_SF_Attribute14WrapShortestEnables_start 632 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_Attribute14WrapShortestEnables_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 632; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SF::Attribute 15 WrapShortest Enables */ #define GFX6_3DSTATE_SF_Attribute15WrapShortestEnables_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_Attribute15WrapShortestEnables_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_SF_Attribute15WrapShortestEnables_start 636 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_Attribute15WrapShortestEnables_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 636; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SF::Attribute 1 WrapShortest Enables */ #define GFX6_3DSTATE_SF_Attribute1WrapShortestEnables_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_Attribute1WrapShortestEnables_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_SF_Attribute1WrapShortestEnables_start 580 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_Attribute1WrapShortestEnables_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 580; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SF::Attribute 2 WrapShortest Enables */ #define GFX6_3DSTATE_SF_Attribute2WrapShortestEnables_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_Attribute2WrapShortestEnables_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_SF_Attribute2WrapShortestEnables_start 584 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_Attribute2WrapShortestEnables_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 584; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SF::Attribute 3 WrapShortest Enables */ #define GFX6_3DSTATE_SF_Attribute3WrapShortestEnables_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_Attribute3WrapShortestEnables_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_SF_Attribute3WrapShortestEnables_start 588 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_Attribute3WrapShortestEnables_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 588; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SF::Attribute 4 WrapShortest Enables */ #define GFX6_3DSTATE_SF_Attribute4WrapShortestEnables_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_Attribute4WrapShortestEnables_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_SF_Attribute4WrapShortestEnables_start 592 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_Attribute4WrapShortestEnables_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 592; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SF::Attribute 5 WrapShortest Enables */ #define GFX6_3DSTATE_SF_Attribute5WrapShortestEnables_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_Attribute5WrapShortestEnables_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_SF_Attribute5WrapShortestEnables_start 596 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_Attribute5WrapShortestEnables_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 596; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SF::Attribute 6 WrapShortest Enables */ #define GFX6_3DSTATE_SF_Attribute6WrapShortestEnables_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_Attribute6WrapShortestEnables_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_SF_Attribute6WrapShortestEnables_start 600 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_Attribute6WrapShortestEnables_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 600; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SF::Attribute 7 WrapShortest Enables */ #define GFX6_3DSTATE_SF_Attribute7WrapShortestEnables_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_Attribute7WrapShortestEnables_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_SF_Attribute7WrapShortestEnables_start 604 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_Attribute7WrapShortestEnables_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 604; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SF::Attribute 8 WrapShortest Enables */ #define GFX6_3DSTATE_SF_Attribute8WrapShortestEnables_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_Attribute8WrapShortestEnables_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_SF_Attribute8WrapShortestEnables_start 608 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_Attribute8WrapShortestEnables_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 608; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SF::Attribute 9 WrapShortest Enables */ #define GFX6_3DSTATE_SF_Attribute9WrapShortestEnables_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_Attribute9WrapShortestEnables_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_SF_Attribute9WrapShortestEnables_start 612 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_Attribute9WrapShortestEnables_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 612; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SF::Attribute Swizzle Enable */ #define GFX6_3DSTATE_SF_AttributeSwizzleEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_AttributeSwizzleEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_SF_AttributeSwizzleEnable_start 53 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_AttributeSwizzleEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 53; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SF::BackFace Fill Mode */ #define GFX75_3DSTATE_SF_BackFaceFillMode_bits 2 #define GFX7_3DSTATE_SF_BackFaceFillMode_bits 2 #define GFX6_3DSTATE_SF_BackFaceFillMode_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_BackFaceFillMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_SF_BackFaceFillMode_start 35 #define GFX7_3DSTATE_SF_BackFaceFillMode_start 35 #define GFX6_3DSTATE_SF_BackFaceFillMode_start 67 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_BackFaceFillMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 35; case 70: return 35; case 60: return 67; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SF::CHV Line Width */ #define GFX8_3DSTATE_SF_CHVLineWidth_bits 18 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_CHVLineWidth_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 18; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX8_3DSTATE_SF_CHVLineWidth_start 44 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_CHVLineWidth_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 44; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SF::Command SubType */ #define GFX125_3DSTATE_SF_CommandSubType_bits 2 #define GFX12_3DSTATE_SF_CommandSubType_bits 2 #define GFX11_3DSTATE_SF_CommandSubType_bits 2 #define GFX9_3DSTATE_SF_CommandSubType_bits 2 #define GFX8_3DSTATE_SF_CommandSubType_bits 2 #define GFX75_3DSTATE_SF_CommandSubType_bits 2 #define GFX7_3DSTATE_SF_CommandSubType_bits 2 #define GFX6_3DSTATE_SF_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SF_CommandSubType_start 27 #define GFX12_3DSTATE_SF_CommandSubType_start 27 #define GFX11_3DSTATE_SF_CommandSubType_start 27 #define GFX9_3DSTATE_SF_CommandSubType_start 27 #define GFX8_3DSTATE_SF_CommandSubType_start 27 #define GFX75_3DSTATE_SF_CommandSubType_start 27 #define GFX7_3DSTATE_SF_CommandSubType_start 27 #define GFX6_3DSTATE_SF_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 27; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SF::Command Type */ #define GFX125_3DSTATE_SF_CommandType_bits 3 #define GFX12_3DSTATE_SF_CommandType_bits 3 #define GFX11_3DSTATE_SF_CommandType_bits 3 #define GFX9_3DSTATE_SF_CommandType_bits 3 #define GFX8_3DSTATE_SF_CommandType_bits 3 #define GFX75_3DSTATE_SF_CommandType_bits 3 #define GFX7_3DSTATE_SF_CommandType_bits 3 #define GFX6_3DSTATE_SF_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SF_CommandType_start 29 #define GFX12_3DSTATE_SF_CommandType_start 29 #define GFX11_3DSTATE_SF_CommandType_start 29 #define GFX9_3DSTATE_SF_CommandType_start 29 #define GFX8_3DSTATE_SF_CommandType_start 29 #define GFX75_3DSTATE_SF_CommandType_start 29 #define GFX7_3DSTATE_SF_CommandType_start 29 #define GFX6_3DSTATE_SF_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 29; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SF::Constant Interpolation Enable */ #define GFX6_3DSTATE_SF_ConstantInterpolationEnable_bits 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_ConstantInterpolationEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 32; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_SF_ConstantInterpolationEnable_start 544 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_ConstantInterpolationEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 544; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SF::Cull Mode */ #define GFX75_3DSTATE_SF_CullMode_bits 2 #define GFX7_3DSTATE_SF_CullMode_bits 2 #define GFX6_3DSTATE_SF_CullMode_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_CullMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_SF_CullMode_start 93 #define GFX7_3DSTATE_SF_CullMode_start 93 #define GFX6_3DSTATE_SF_CullMode_start 125 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_CullMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 93; case 70: return 93; case 60: return 125; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SF::DWord Length */ #define GFX125_3DSTATE_SF_DWordLength_bits 8 #define GFX12_3DSTATE_SF_DWordLength_bits 8 #define GFX11_3DSTATE_SF_DWordLength_bits 8 #define GFX9_3DSTATE_SF_DWordLength_bits 8 #define GFX8_3DSTATE_SF_DWordLength_bits 8 #define GFX75_3DSTATE_SF_DWordLength_bits 8 #define GFX7_3DSTATE_SF_DWordLength_bits 8 #define GFX6_3DSTATE_SF_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SF_DWordLength_start 0 #define GFX12_3DSTATE_SF_DWordLength_start 0 #define GFX11_3DSTATE_SF_DWordLength_start 0 #define GFX9_3DSTATE_SF_DWordLength_start 0 #define GFX8_3DSTATE_SF_DWordLength_start 0 #define GFX75_3DSTATE_SF_DWordLength_start 0 #define GFX7_3DSTATE_SF_DWordLength_start 0 #define GFX6_3DSTATE_SF_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SF::Depth Buffer Surface Format */ #define GFX75_3DSTATE_SF_DepthBufferSurfaceFormat_bits 3 #define GFX7_3DSTATE_SF_DepthBufferSurfaceFormat_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_DepthBufferSurfaceFormat_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_SF_DepthBufferSurfaceFormat_start 44 #define GFX7_3DSTATE_SF_DepthBufferSurfaceFormat_start 44 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_DepthBufferSurfaceFormat_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 44; case 70: return 44; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SF::Deref Block Size */ #define GFX125_3DSTATE_SF_DerefBlockSize_bits 2 #define GFX12_3DSTATE_SF_DerefBlockSize_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_DerefBlockSize_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SF_DerefBlockSize_start 93 #define GFX12_3DSTATE_SF_DerefBlockSize_start 93 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_DerefBlockSize_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 93; case 120: return 93; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SF::FrontFace Fill Mode */ #define GFX75_3DSTATE_SF_FrontFaceFillMode_bits 2 #define GFX7_3DSTATE_SF_FrontFaceFillMode_bits 2 #define GFX6_3DSTATE_SF_FrontFaceFillMode_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_FrontFaceFillMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_SF_FrontFaceFillMode_start 37 #define GFX7_3DSTATE_SF_FrontFaceFillMode_start 37 #define GFX6_3DSTATE_SF_FrontFaceFillMode_start 69 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_FrontFaceFillMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 37; case 70: return 37; case 60: return 69; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SF::Front Winding */ #define GFX75_3DSTATE_SF_FrontWinding_bits 1 #define GFX7_3DSTATE_SF_FrontWinding_bits 1 #define GFX6_3DSTATE_SF_FrontWinding_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_FrontWinding_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_SF_FrontWinding_start 32 #define GFX7_3DSTATE_SF_FrontWinding_start 32 #define GFX6_3DSTATE_SF_FrontWinding_start 64 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_FrontWinding_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 32; case 70: return 32; case 60: return 64; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SF::Global Depth Offset Clamp */ #define GFX75_3DSTATE_SF_GlobalDepthOffsetClamp_bits 32 #define GFX7_3DSTATE_SF_GlobalDepthOffsetClamp_bits 32 #define GFX6_3DSTATE_SF_GlobalDepthOffsetClamp_bits 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_GlobalDepthOffsetClamp_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 32; case 70: return 32; case 60: return 32; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_SF_GlobalDepthOffsetClamp_start 192 #define GFX7_3DSTATE_SF_GlobalDepthOffsetClamp_start 192 #define GFX6_3DSTATE_SF_GlobalDepthOffsetClamp_start 224 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_GlobalDepthOffsetClamp_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 192; case 70: return 192; case 60: return 224; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SF::Global Depth Offset Constant */ #define GFX75_3DSTATE_SF_GlobalDepthOffsetConstant_bits 32 #define GFX7_3DSTATE_SF_GlobalDepthOffsetConstant_bits 32 #define GFX6_3DSTATE_SF_GlobalDepthOffsetConstant_bits 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_GlobalDepthOffsetConstant_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 32; case 70: return 32; case 60: return 32; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_SF_GlobalDepthOffsetConstant_start 128 #define GFX7_3DSTATE_SF_GlobalDepthOffsetConstant_start 128 #define GFX6_3DSTATE_SF_GlobalDepthOffsetConstant_start 160 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_GlobalDepthOffsetConstant_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 128; case 70: return 128; case 60: return 160; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SF::Global Depth Offset Enable Point */ #define GFX75_3DSTATE_SF_GlobalDepthOffsetEnablePoint_bits 1 #define GFX7_3DSTATE_SF_GlobalDepthOffsetEnablePoint_bits 1 #define GFX6_3DSTATE_SF_GlobalDepthOffsetEnablePoint_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_GlobalDepthOffsetEnablePoint_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_SF_GlobalDepthOffsetEnablePoint_start 39 #define GFX7_3DSTATE_SF_GlobalDepthOffsetEnablePoint_start 39 #define GFX6_3DSTATE_SF_GlobalDepthOffsetEnablePoint_start 71 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_GlobalDepthOffsetEnablePoint_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 39; case 70: return 39; case 60: return 71; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SF::Global Depth Offset Enable Solid */ #define GFX75_3DSTATE_SF_GlobalDepthOffsetEnableSolid_bits 1 #define GFX7_3DSTATE_SF_GlobalDepthOffsetEnableSolid_bits 1 #define GFX6_3DSTATE_SF_GlobalDepthOffsetEnableSolid_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_GlobalDepthOffsetEnableSolid_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_SF_GlobalDepthOffsetEnableSolid_start 41 #define GFX7_3DSTATE_SF_GlobalDepthOffsetEnableSolid_start 41 #define GFX6_3DSTATE_SF_GlobalDepthOffsetEnableSolid_start 73 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_GlobalDepthOffsetEnableSolid_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 41; case 70: return 41; case 60: return 73; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SF::Global Depth Offset Enable Wireframe */ #define GFX75_3DSTATE_SF_GlobalDepthOffsetEnableWireframe_bits 1 #define GFX7_3DSTATE_SF_GlobalDepthOffsetEnableWireframe_bits 1 #define GFX6_3DSTATE_SF_GlobalDepthOffsetEnableWireframe_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_GlobalDepthOffsetEnableWireframe_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_SF_GlobalDepthOffsetEnableWireframe_start 40 #define GFX7_3DSTATE_SF_GlobalDepthOffsetEnableWireframe_start 40 #define GFX6_3DSTATE_SF_GlobalDepthOffsetEnableWireframe_start 72 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_GlobalDepthOffsetEnableWireframe_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 40; case 70: return 40; case 60: return 72; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SF::Global Depth Offset Scale */ #define GFX75_3DSTATE_SF_GlobalDepthOffsetScale_bits 32 #define GFX7_3DSTATE_SF_GlobalDepthOffsetScale_bits 32 #define GFX6_3DSTATE_SF_GlobalDepthOffsetScale_bits 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_GlobalDepthOffsetScale_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 32; case 70: return 32; case 60: return 32; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_SF_GlobalDepthOffsetScale_start 160 #define GFX7_3DSTATE_SF_GlobalDepthOffsetScale_start 160 #define GFX6_3DSTATE_SF_GlobalDepthOffsetScale_start 192 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_GlobalDepthOffsetScale_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 160; case 70: return 160; case 60: return 192; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SF::Last Pixel Enable */ #define GFX125_3DSTATE_SF_LastPixelEnable_bits 1 #define GFX12_3DSTATE_SF_LastPixelEnable_bits 1 #define GFX11_3DSTATE_SF_LastPixelEnable_bits 1 #define GFX9_3DSTATE_SF_LastPixelEnable_bits 1 #define GFX8_3DSTATE_SF_LastPixelEnable_bits 1 #define GFX75_3DSTATE_SF_LastPixelEnable_bits 1 #define GFX7_3DSTATE_SF_LastPixelEnable_bits 1 #define GFX6_3DSTATE_SF_LastPixelEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_LastPixelEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SF_LastPixelEnable_start 127 #define GFX12_3DSTATE_SF_LastPixelEnable_start 127 #define GFX11_3DSTATE_SF_LastPixelEnable_start 127 #define GFX9_3DSTATE_SF_LastPixelEnable_start 127 #define GFX8_3DSTATE_SF_LastPixelEnable_start 127 #define GFX75_3DSTATE_SF_LastPixelEnable_start 127 #define GFX7_3DSTATE_SF_LastPixelEnable_start 127 #define GFX6_3DSTATE_SF_LastPixelEnable_start 159 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_LastPixelEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 127; case 120: return 127; case 110: return 127; case 90: return 127; case 80: return 127; case 75: return 127; case 70: return 127; case 60: return 159; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SF::Legacy Global Depth Bias Enable */ #define GFX125_3DSTATE_SF_LegacyGlobalDepthBiasEnable_bits 1 #define GFX12_3DSTATE_SF_LegacyGlobalDepthBiasEnable_bits 1 #define GFX11_3DSTATE_SF_LegacyGlobalDepthBiasEnable_bits 1 #define GFX9_3DSTATE_SF_LegacyGlobalDepthBiasEnable_bits 1 #define GFX8_3DSTATE_SF_LegacyGlobalDepthBiasEnable_bits 1 #define GFX75_3DSTATE_SF_LegacyGlobalDepthBiasEnable_bits 1 #define GFX7_3DSTATE_SF_LegacyGlobalDepthBiasEnable_bits 1 #define GFX6_3DSTATE_SF_LegacyGlobalDepthBiasEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_LegacyGlobalDepthBiasEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SF_LegacyGlobalDepthBiasEnable_start 43 #define GFX12_3DSTATE_SF_LegacyGlobalDepthBiasEnable_start 43 #define GFX11_3DSTATE_SF_LegacyGlobalDepthBiasEnable_start 43 #define GFX9_3DSTATE_SF_LegacyGlobalDepthBiasEnable_start 43 #define GFX8_3DSTATE_SF_LegacyGlobalDepthBiasEnable_start 43 #define GFX75_3DSTATE_SF_LegacyGlobalDepthBiasEnable_start 43 #define GFX7_3DSTATE_SF_LegacyGlobalDepthBiasEnable_start 43 #define GFX6_3DSTATE_SF_LegacyGlobalDepthBiasEnable_start 75 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_LegacyGlobalDepthBiasEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 43; case 120: return 43; case 110: return 43; case 90: return 43; case 80: return 43; case 75: return 43; case 70: return 43; case 60: return 75; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SF::Line End Cap Antialiasing Region Width */ #define GFX125_3DSTATE_SF_LineEndCapAntialiasingRegionWidth_bits 2 #define GFX12_3DSTATE_SF_LineEndCapAntialiasingRegionWidth_bits 2 #define GFX11_3DSTATE_SF_LineEndCapAntialiasingRegionWidth_bits 2 #define GFX9_3DSTATE_SF_LineEndCapAntialiasingRegionWidth_bits 2 #define GFX8_3DSTATE_SF_LineEndCapAntialiasingRegionWidth_bits 2 #define GFX75_3DSTATE_SF_LineEndCapAntialiasingRegionWidth_bits 2 #define GFX7_3DSTATE_SF_LineEndCapAntialiasingRegionWidth_bits 2 #define GFX6_3DSTATE_SF_LineEndCapAntialiasingRegionWidth_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_LineEndCapAntialiasingRegionWidth_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SF_LineEndCapAntialiasingRegionWidth_start 80 #define GFX12_3DSTATE_SF_LineEndCapAntialiasingRegionWidth_start 80 #define GFX11_3DSTATE_SF_LineEndCapAntialiasingRegionWidth_start 80 #define GFX9_3DSTATE_SF_LineEndCapAntialiasingRegionWidth_start 80 #define GFX8_3DSTATE_SF_LineEndCapAntialiasingRegionWidth_start 80 #define GFX75_3DSTATE_SF_LineEndCapAntialiasingRegionWidth_start 80 #define GFX7_3DSTATE_SF_LineEndCapAntialiasingRegionWidth_start 80 #define GFX6_3DSTATE_SF_LineEndCapAntialiasingRegionWidth_start 112 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_LineEndCapAntialiasingRegionWidth_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 80; case 120: return 80; case 110: return 80; case 90: return 80; case 80: return 80; case 75: return 80; case 70: return 80; case 60: return 112; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SF::Line Stipple Enable */ #define GFX75_3DSTATE_SF_LineStippleEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_LineStippleEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_SF_LineStippleEnable_start 78 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_LineStippleEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 78; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SF::Line Strip/List Provoking Vertex Select */ #define GFX125_3DSTATE_SF_LineStripListProvokingVertexSelect_bits 2 #define GFX12_3DSTATE_SF_LineStripListProvokingVertexSelect_bits 2 #define GFX11_3DSTATE_SF_LineStripListProvokingVertexSelect_bits 2 #define GFX9_3DSTATE_SF_LineStripListProvokingVertexSelect_bits 2 #define GFX8_3DSTATE_SF_LineStripListProvokingVertexSelect_bits 2 #define GFX75_3DSTATE_SF_LineStripListProvokingVertexSelect_bits 2 #define GFX7_3DSTATE_SF_LineStripListProvokingVertexSelect_bits 2 #define GFX6_3DSTATE_SF_LineStripListProvokingVertexSelect_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_LineStripListProvokingVertexSelect_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SF_LineStripListProvokingVertexSelect_start 123 #define GFX12_3DSTATE_SF_LineStripListProvokingVertexSelect_start 123 #define GFX11_3DSTATE_SF_LineStripListProvokingVertexSelect_start 123 #define GFX9_3DSTATE_SF_LineStripListProvokingVertexSelect_start 123 #define GFX8_3DSTATE_SF_LineStripListProvokingVertexSelect_start 123 #define GFX75_3DSTATE_SF_LineStripListProvokingVertexSelect_start 123 #define GFX7_3DSTATE_SF_LineStripListProvokingVertexSelect_start 123 #define GFX6_3DSTATE_SF_LineStripListProvokingVertexSelect_start 155 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_LineStripListProvokingVertexSelect_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 123; case 120: return 123; case 110: return 123; case 90: return 123; case 80: return 123; case 75: return 123; case 70: return 123; case 60: return 155; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SF::Line Width */ #define GFX125_3DSTATE_SF_LineWidth_bits 18 #define GFX12_3DSTATE_SF_LineWidth_bits 18 #define GFX11_3DSTATE_SF_LineWidth_bits 18 #define GFX9_3DSTATE_SF_LineWidth_bits 18 #define GFX8_3DSTATE_SF_LineWidth_bits 10 #define GFX75_3DSTATE_SF_LineWidth_bits 10 #define GFX7_3DSTATE_SF_LineWidth_bits 10 #define GFX6_3DSTATE_SF_LineWidth_bits 10 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_LineWidth_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 18; case 120: return 18; case 110: return 18; case 90: return 18; case 80: return 10; case 75: return 10; case 70: return 10; case 60: return 10; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SF_LineWidth_start 44 #define GFX12_3DSTATE_SF_LineWidth_start 44 #define GFX11_3DSTATE_SF_LineWidth_start 44 #define GFX9_3DSTATE_SF_LineWidth_start 44 #define GFX8_3DSTATE_SF_LineWidth_start 82 #define GFX75_3DSTATE_SF_LineWidth_start 82 #define GFX7_3DSTATE_SF_LineWidth_start 82 #define GFX6_3DSTATE_SF_LineWidth_start 114 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_LineWidth_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 44; case 120: return 44; case 110: return 44; case 90: return 44; case 80: return 82; case 75: return 82; case 70: return 82; case 60: return 114; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SF::Multisample Rasterization Mode */ #define GFX75_3DSTATE_SF_MultisampleRasterizationMode_bits 2 #define GFX7_3DSTATE_SF_MultisampleRasterizationMode_bits 2 #define GFX6_3DSTATE_SF_MultisampleRasterizationMode_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_MultisampleRasterizationMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_SF_MultisampleRasterizationMode_start 72 #define GFX7_3DSTATE_SF_MultisampleRasterizationMode_start 72 #define GFX6_3DSTATE_SF_MultisampleRasterizationMode_start 104 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_MultisampleRasterizationMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 72; case 70: return 72; case 60: return 104; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SF::Number of SF Output Attributes */ #define GFX6_3DSTATE_SF_NumberofSFOutputAttributes_bits 6 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_NumberofSFOutputAttributes_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 6; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_SF_NumberofSFOutputAttributes_start 54 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_NumberofSFOutputAttributes_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 54; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SF::Point Sprite Texture Coordinate Enable */ #define GFX6_3DSTATE_SF_PointSpriteTextureCoordinateEnable_bits 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_PointSpriteTextureCoordinateEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 32; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_SF_PointSpriteTextureCoordinateEnable_start 512 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_PointSpriteTextureCoordinateEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 512; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SF::Point Sprite Texture Coordinate Origin */ #define GFX6_3DSTATE_SF_PointSpriteTextureCoordinateOrigin_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_PointSpriteTextureCoordinateOrigin_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_SF_PointSpriteTextureCoordinateOrigin_start 52 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_PointSpriteTextureCoordinateOrigin_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 52; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SF::Point Width */ #define GFX125_3DSTATE_SF_PointWidth_bits 11 #define GFX12_3DSTATE_SF_PointWidth_bits 11 #define GFX11_3DSTATE_SF_PointWidth_bits 11 #define GFX9_3DSTATE_SF_PointWidth_bits 11 #define GFX8_3DSTATE_SF_PointWidth_bits 11 #define GFX75_3DSTATE_SF_PointWidth_bits 11 #define GFX7_3DSTATE_SF_PointWidth_bits 11 #define GFX6_3DSTATE_SF_PointWidth_bits 11 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_PointWidth_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 11; case 120: return 11; case 110: return 11; case 90: return 11; case 80: return 11; case 75: return 11; case 70: return 11; case 60: return 11; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SF_PointWidth_start 96 #define GFX12_3DSTATE_SF_PointWidth_start 96 #define GFX11_3DSTATE_SF_PointWidth_start 96 #define GFX9_3DSTATE_SF_PointWidth_start 96 #define GFX8_3DSTATE_SF_PointWidth_start 96 #define GFX75_3DSTATE_SF_PointWidth_start 96 #define GFX7_3DSTATE_SF_PointWidth_start 96 #define GFX6_3DSTATE_SF_PointWidth_start 128 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_PointWidth_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 96; case 120: return 96; case 110: return 96; case 90: return 96; case 80: return 96; case 75: return 96; case 70: return 96; case 60: return 128; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SF::Point Width Source */ #define GFX125_3DSTATE_SF_PointWidthSource_bits 1 #define GFX12_3DSTATE_SF_PointWidthSource_bits 1 #define GFX11_3DSTATE_SF_PointWidthSource_bits 1 #define GFX9_3DSTATE_SF_PointWidthSource_bits 1 #define GFX8_3DSTATE_SF_PointWidthSource_bits 1 #define GFX75_3DSTATE_SF_PointWidthSource_bits 1 #define GFX7_3DSTATE_SF_PointWidthSource_bits 1 #define GFX6_3DSTATE_SF_PointWidthSource_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_PointWidthSource_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SF_PointWidthSource_start 107 #define GFX12_3DSTATE_SF_PointWidthSource_start 107 #define GFX11_3DSTATE_SF_PointWidthSource_start 107 #define GFX9_3DSTATE_SF_PointWidthSource_start 107 #define GFX8_3DSTATE_SF_PointWidthSource_start 107 #define GFX75_3DSTATE_SF_PointWidthSource_start 107 #define GFX7_3DSTATE_SF_PointWidthSource_start 107 #define GFX6_3DSTATE_SF_PointWidthSource_start 139 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_PointWidthSource_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 107; case 120: return 107; case 110: return 107; case 90: return 107; case 80: return 107; case 75: return 107; case 70: return 107; case 60: return 139; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SF::RT Independent Rasterization Enable */ #define GFX75_3DSTATE_SF_RTIndependentRasterizationEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_RTIndependentRasterizationEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_SF_RTIndependentRasterizationEnable_start 74 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_RTIndependentRasterizationEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 74; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SF::Scissor Rectangle Enable */ #define GFX75_3DSTATE_SF_ScissorRectangleEnable_bits 1 #define GFX7_3DSTATE_SF_ScissorRectangleEnable_bits 1 #define GFX6_3DSTATE_SF_ScissorRectangleEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_ScissorRectangleEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_SF_ScissorRectangleEnable_start 75 #define GFX7_3DSTATE_SF_ScissorRectangleEnable_start 75 #define GFX6_3DSTATE_SF_ScissorRectangleEnable_start 107 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_ScissorRectangleEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 75; case 70: return 75; case 60: return 107; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SF::Smooth Point Enable */ #define GFX125_3DSTATE_SF_SmoothPointEnable_bits 1 #define GFX12_3DSTATE_SF_SmoothPointEnable_bits 1 #define GFX11_3DSTATE_SF_SmoothPointEnable_bits 1 #define GFX9_3DSTATE_SF_SmoothPointEnable_bits 1 #define GFX8_3DSTATE_SF_SmoothPointEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_SmoothPointEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SF_SmoothPointEnable_start 109 #define GFX12_3DSTATE_SF_SmoothPointEnable_start 109 #define GFX11_3DSTATE_SF_SmoothPointEnable_start 109 #define GFX9_3DSTATE_SF_SmoothPointEnable_start 109 #define GFX8_3DSTATE_SF_SmoothPointEnable_start 109 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_SmoothPointEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 109; case 120: return 109; case 110: return 109; case 90: return 109; case 80: return 109; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SF::Statistics Enable */ #define GFX125_3DSTATE_SF_StatisticsEnable_bits 1 #define GFX12_3DSTATE_SF_StatisticsEnable_bits 1 #define GFX11_3DSTATE_SF_StatisticsEnable_bits 1 #define GFX9_3DSTATE_SF_StatisticsEnable_bits 1 #define GFX8_3DSTATE_SF_StatisticsEnable_bits 1 #define GFX75_3DSTATE_SF_StatisticsEnable_bits 1 #define GFX7_3DSTATE_SF_StatisticsEnable_bits 1 #define GFX6_3DSTATE_SF_StatisticsEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_StatisticsEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SF_StatisticsEnable_start 42 #define GFX12_3DSTATE_SF_StatisticsEnable_start 42 #define GFX11_3DSTATE_SF_StatisticsEnable_start 42 #define GFX9_3DSTATE_SF_StatisticsEnable_start 42 #define GFX8_3DSTATE_SF_StatisticsEnable_start 42 #define GFX75_3DSTATE_SF_StatisticsEnable_start 42 #define GFX7_3DSTATE_SF_StatisticsEnable_start 42 #define GFX6_3DSTATE_SF_StatisticsEnable_start 74 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_StatisticsEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 42; case 120: return 42; case 110: return 42; case 90: return 42; case 80: return 42; case 75: return 42; case 70: return 42; case 60: return 74; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SF::Triangle Fan Provoking Vertex Select */ #define GFX125_3DSTATE_SF_TriangleFanProvokingVertexSelect_bits 2 #define GFX12_3DSTATE_SF_TriangleFanProvokingVertexSelect_bits 2 #define GFX11_3DSTATE_SF_TriangleFanProvokingVertexSelect_bits 2 #define GFX9_3DSTATE_SF_TriangleFanProvokingVertexSelect_bits 2 #define GFX8_3DSTATE_SF_TriangleFanProvokingVertexSelect_bits 2 #define GFX75_3DSTATE_SF_TriangleFanProvokingVertexSelect_bits 2 #define GFX7_3DSTATE_SF_TriangleFanProvokingVertexSelect_bits 2 #define GFX6_3DSTATE_SF_TriangleFanProvokingVertexSelect_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_TriangleFanProvokingVertexSelect_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SF_TriangleFanProvokingVertexSelect_start 121 #define GFX12_3DSTATE_SF_TriangleFanProvokingVertexSelect_start 121 #define GFX11_3DSTATE_SF_TriangleFanProvokingVertexSelect_start 121 #define GFX9_3DSTATE_SF_TriangleFanProvokingVertexSelect_start 121 #define GFX8_3DSTATE_SF_TriangleFanProvokingVertexSelect_start 121 #define GFX75_3DSTATE_SF_TriangleFanProvokingVertexSelect_start 121 #define GFX7_3DSTATE_SF_TriangleFanProvokingVertexSelect_start 121 #define GFX6_3DSTATE_SF_TriangleFanProvokingVertexSelect_start 153 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_TriangleFanProvokingVertexSelect_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 121; case 120: return 121; case 110: return 121; case 90: return 121; case 80: return 121; case 75: return 121; case 70: return 121; case 60: return 153; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SF::Triangle Strip/List Provoking Vertex Select */ #define GFX125_3DSTATE_SF_TriangleStripListProvokingVertexSelect_bits 2 #define GFX12_3DSTATE_SF_TriangleStripListProvokingVertexSelect_bits 2 #define GFX11_3DSTATE_SF_TriangleStripListProvokingVertexSelect_bits 2 #define GFX9_3DSTATE_SF_TriangleStripListProvokingVertexSelect_bits 2 #define GFX8_3DSTATE_SF_TriangleStripListProvokingVertexSelect_bits 2 #define GFX75_3DSTATE_SF_TriangleStripListProvokingVertexSelect_bits 2 #define GFX7_3DSTATE_SF_TriangleStripListProvokingVertexSelect_bits 2 #define GFX6_3DSTATE_SF_TriangleStripListProvokingVertexSelect_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_TriangleStripListProvokingVertexSelect_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SF_TriangleStripListProvokingVertexSelect_start 125 #define GFX12_3DSTATE_SF_TriangleStripListProvokingVertexSelect_start 125 #define GFX11_3DSTATE_SF_TriangleStripListProvokingVertexSelect_start 125 #define GFX9_3DSTATE_SF_TriangleStripListProvokingVertexSelect_start 125 #define GFX8_3DSTATE_SF_TriangleStripListProvokingVertexSelect_start 125 #define GFX75_3DSTATE_SF_TriangleStripListProvokingVertexSelect_start 125 #define GFX7_3DSTATE_SF_TriangleStripListProvokingVertexSelect_start 125 #define GFX6_3DSTATE_SF_TriangleStripListProvokingVertexSelect_start 157 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_TriangleStripListProvokingVertexSelect_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 125; case 120: return 125; case 110: return 125; case 90: return 125; case 80: return 125; case 75: return 125; case 70: return 125; case 60: return 157; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SF::Vertex Sub Pixel Precision Select */ #define GFX125_3DSTATE_SF_VertexSubPixelPrecisionSelect_bits 1 #define GFX12_3DSTATE_SF_VertexSubPixelPrecisionSelect_bits 1 #define GFX11_3DSTATE_SF_VertexSubPixelPrecisionSelect_bits 1 #define GFX9_3DSTATE_SF_VertexSubPixelPrecisionSelect_bits 1 #define GFX8_3DSTATE_SF_VertexSubPixelPrecisionSelect_bits 1 #define GFX75_3DSTATE_SF_VertexSubPixelPrecisionSelect_bits 1 #define GFX7_3DSTATE_SF_VertexSubPixelPrecisionSelect_bits 1 #define GFX6_3DSTATE_SF_VertexSubPixelPrecisionSelect_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_VertexSubPixelPrecisionSelect_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SF_VertexSubPixelPrecisionSelect_start 108 #define GFX12_3DSTATE_SF_VertexSubPixelPrecisionSelect_start 108 #define GFX11_3DSTATE_SF_VertexSubPixelPrecisionSelect_start 108 #define GFX9_3DSTATE_SF_VertexSubPixelPrecisionSelect_start 108 #define GFX8_3DSTATE_SF_VertexSubPixelPrecisionSelect_start 108 #define GFX75_3DSTATE_SF_VertexSubPixelPrecisionSelect_start 108 #define GFX7_3DSTATE_SF_VertexSubPixelPrecisionSelect_start 108 #define GFX6_3DSTATE_SF_VertexSubPixelPrecisionSelect_start 140 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_VertexSubPixelPrecisionSelect_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 108; case 120: return 108; case 110: return 108; case 90: return 108; case 80: return 108; case 75: return 108; case 70: return 108; case 60: return 140; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SF::Vertex URB Entry Read Length */ #define GFX6_3DSTATE_SF_VertexURBEntryReadLength_bits 5 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_VertexURBEntryReadLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 5; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_SF_VertexURBEntryReadLength_start 43 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_VertexURBEntryReadLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 43; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SF::Vertex URB Entry Read Offset */ #define GFX6_3DSTATE_SF_VertexURBEntryReadOffset_bits 6 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_VertexURBEntryReadOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 6; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_SF_VertexURBEntryReadOffset_start 36 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_VertexURBEntryReadOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 36; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SF::Viewport Transform Enable */ #define GFX125_3DSTATE_SF_ViewportTransformEnable_bits 1 #define GFX12_3DSTATE_SF_ViewportTransformEnable_bits 1 #define GFX11_3DSTATE_SF_ViewportTransformEnable_bits 1 #define GFX9_3DSTATE_SF_ViewportTransformEnable_bits 1 #define GFX8_3DSTATE_SF_ViewportTransformEnable_bits 1 #define GFX75_3DSTATE_SF_ViewportTransformEnable_bits 1 #define GFX7_3DSTATE_SF_ViewportTransformEnable_bits 1 #define GFX6_3DSTATE_SF_ViewportTransformEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_ViewportTransformEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SF_ViewportTransformEnable_start 33 #define GFX12_3DSTATE_SF_ViewportTransformEnable_start 33 #define GFX11_3DSTATE_SF_ViewportTransformEnable_start 33 #define GFX9_3DSTATE_SF_ViewportTransformEnable_start 33 #define GFX8_3DSTATE_SF_ViewportTransformEnable_start 33 #define GFX75_3DSTATE_SF_ViewportTransformEnable_start 33 #define GFX7_3DSTATE_SF_ViewportTransformEnable_start 33 #define GFX6_3DSTATE_SF_ViewportTransformEnable_start 65 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SF_ViewportTransformEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 33; case 120: return 33; case 110: return 33; case 90: return 33; case 80: return 33; case 75: return 33; case 70: return 33; case 60: return 65; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SLICE_TABLE_STATE_POINTERS */ #define GFX125_3DSTATE_SLICE_TABLE_STATE_POINTERS_length 2 #define GFX12_3DSTATE_SLICE_TABLE_STATE_POINTERS_length 2 #define GFX11_3DSTATE_SLICE_TABLE_STATE_POINTERS_length 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SLICE_TABLE_STATE_POINTERS_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SLICE_TABLE_STATE_POINTERS::3D Command Opcode */ #define GFX125_3DSTATE_SLICE_TABLE_STATE_POINTERS_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_SLICE_TABLE_STATE_POINTERS_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_SLICE_TABLE_STATE_POINTERS_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SLICE_TABLE_STATE_POINTERS_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SLICE_TABLE_STATE_POINTERS_3DCommandOpcode_start 24 #define GFX12_3DSTATE_SLICE_TABLE_STATE_POINTERS_3DCommandOpcode_start 24 #define GFX11_3DSTATE_SLICE_TABLE_STATE_POINTERS_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SLICE_TABLE_STATE_POINTERS_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SLICE_TABLE_STATE_POINTERS::3D Command Sub Opcode */ #define GFX125_3DSTATE_SLICE_TABLE_STATE_POINTERS_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_SLICE_TABLE_STATE_POINTERS_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_SLICE_TABLE_STATE_POINTERS_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SLICE_TABLE_STATE_POINTERS_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SLICE_TABLE_STATE_POINTERS_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_SLICE_TABLE_STATE_POINTERS_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_SLICE_TABLE_STATE_POINTERS_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SLICE_TABLE_STATE_POINTERS_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SLICE_TABLE_STATE_POINTERS::Command SubType */ #define GFX125_3DSTATE_SLICE_TABLE_STATE_POINTERS_CommandSubType_bits 2 #define GFX12_3DSTATE_SLICE_TABLE_STATE_POINTERS_CommandSubType_bits 2 #define GFX11_3DSTATE_SLICE_TABLE_STATE_POINTERS_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SLICE_TABLE_STATE_POINTERS_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SLICE_TABLE_STATE_POINTERS_CommandSubType_start 27 #define GFX12_3DSTATE_SLICE_TABLE_STATE_POINTERS_CommandSubType_start 27 #define GFX11_3DSTATE_SLICE_TABLE_STATE_POINTERS_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SLICE_TABLE_STATE_POINTERS_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SLICE_TABLE_STATE_POINTERS::Command Type */ #define GFX125_3DSTATE_SLICE_TABLE_STATE_POINTERS_CommandType_bits 3 #define GFX12_3DSTATE_SLICE_TABLE_STATE_POINTERS_CommandType_bits 3 #define GFX11_3DSTATE_SLICE_TABLE_STATE_POINTERS_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SLICE_TABLE_STATE_POINTERS_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SLICE_TABLE_STATE_POINTERS_CommandType_start 29 #define GFX12_3DSTATE_SLICE_TABLE_STATE_POINTERS_CommandType_start 29 #define GFX11_3DSTATE_SLICE_TABLE_STATE_POINTERS_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SLICE_TABLE_STATE_POINTERS_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SLICE_TABLE_STATE_POINTERS::DWord Length */ #define GFX125_3DSTATE_SLICE_TABLE_STATE_POINTERS_DWordLength_bits 8 #define GFX12_3DSTATE_SLICE_TABLE_STATE_POINTERS_DWordLength_bits 8 #define GFX11_3DSTATE_SLICE_TABLE_STATE_POINTERS_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SLICE_TABLE_STATE_POINTERS_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SLICE_TABLE_STATE_POINTERS_DWordLength_start 0 #define GFX12_3DSTATE_SLICE_TABLE_STATE_POINTERS_DWordLength_start 0 #define GFX11_3DSTATE_SLICE_TABLE_STATE_POINTERS_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SLICE_TABLE_STATE_POINTERS_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SLICE_TABLE_STATE_POINTERS::Slice Hash State Pointer Valid */ #define GFX125_3DSTATE_SLICE_TABLE_STATE_POINTERS_SliceHashStatePointerValid_bits 1 #define GFX12_3DSTATE_SLICE_TABLE_STATE_POINTERS_SliceHashStatePointerValid_bits 1 #define GFX11_3DSTATE_SLICE_TABLE_STATE_POINTERS_SliceHashStatePointerValid_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SLICE_TABLE_STATE_POINTERS_SliceHashStatePointerValid_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SLICE_TABLE_STATE_POINTERS_SliceHashStatePointerValid_start 32 #define GFX12_3DSTATE_SLICE_TABLE_STATE_POINTERS_SliceHashStatePointerValid_start 32 #define GFX11_3DSTATE_SLICE_TABLE_STATE_POINTERS_SliceHashStatePointerValid_start 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SLICE_TABLE_STATE_POINTERS_SliceHashStatePointerValid_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SLICE_TABLE_STATE_POINTERS::Slice Hash Table State Pointer */ #define GFX125_3DSTATE_SLICE_TABLE_STATE_POINTERS_SliceHashTableStatePointer_bits 26 #define GFX12_3DSTATE_SLICE_TABLE_STATE_POINTERS_SliceHashTableStatePointer_bits 26 #define GFX11_3DSTATE_SLICE_TABLE_STATE_POINTERS_SliceHashTableStatePointer_bits 26 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SLICE_TABLE_STATE_POINTERS_SliceHashTableStatePointer_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 26; case 120: return 26; case 110: return 26; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SLICE_TABLE_STATE_POINTERS_SliceHashTableStatePointer_start 38 #define GFX12_3DSTATE_SLICE_TABLE_STATE_POINTERS_SliceHashTableStatePointer_start 38 #define GFX11_3DSTATE_SLICE_TABLE_STATE_POINTERS_SliceHashTableStatePointer_start 38 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SLICE_TABLE_STATE_POINTERS_SliceHashTableStatePointer_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 38; case 120: return 38; case 110: return 38; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SO_BUFFER */ #define GFX125_3DSTATE_SO_BUFFER_length 8 #define GFX12_3DSTATE_SO_BUFFER_length 8 #define GFX11_3DSTATE_SO_BUFFER_length 8 #define GFX9_3DSTATE_SO_BUFFER_length 8 #define GFX8_3DSTATE_SO_BUFFER_length 8 #define GFX75_3DSTATE_SO_BUFFER_length 4 #define GFX7_3DSTATE_SO_BUFFER_length 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 4; case 70: return 4; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SO_BUFFER::3D Command Opcode */ #define GFX125_3DSTATE_SO_BUFFER_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_SO_BUFFER_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_SO_BUFFER_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_SO_BUFFER_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_SO_BUFFER_3DCommandOpcode_bits 3 #define GFX75_3DSTATE_SO_BUFFER_3DCommandOpcode_bits 3 #define GFX7_3DSTATE_SO_BUFFER_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SO_BUFFER_3DCommandOpcode_start 24 #define GFX12_3DSTATE_SO_BUFFER_3DCommandOpcode_start 24 #define GFX11_3DSTATE_SO_BUFFER_3DCommandOpcode_start 24 #define GFX9_3DSTATE_SO_BUFFER_3DCommandOpcode_start 24 #define GFX8_3DSTATE_SO_BUFFER_3DCommandOpcode_start 24 #define GFX75_3DSTATE_SO_BUFFER_3DCommandOpcode_start 24 #define GFX7_3DSTATE_SO_BUFFER_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SO_BUFFER::3D Command Sub Opcode */ #define GFX125_3DSTATE_SO_BUFFER_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_SO_BUFFER_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_SO_BUFFER_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_SO_BUFFER_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_SO_BUFFER_3DCommandSubOpcode_bits 8 #define GFX75_3DSTATE_SO_BUFFER_3DCommandSubOpcode_bits 8 #define GFX7_3DSTATE_SO_BUFFER_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SO_BUFFER_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_SO_BUFFER_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_SO_BUFFER_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_SO_BUFFER_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_SO_BUFFER_3DCommandSubOpcode_start 16 #define GFX75_3DSTATE_SO_BUFFER_3DCommandSubOpcode_start 16 #define GFX7_3DSTATE_SO_BUFFER_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SO_BUFFER::Command SubType */ #define GFX125_3DSTATE_SO_BUFFER_CommandSubType_bits 2 #define GFX12_3DSTATE_SO_BUFFER_CommandSubType_bits 2 #define GFX11_3DSTATE_SO_BUFFER_CommandSubType_bits 2 #define GFX9_3DSTATE_SO_BUFFER_CommandSubType_bits 2 #define GFX8_3DSTATE_SO_BUFFER_CommandSubType_bits 2 #define GFX75_3DSTATE_SO_BUFFER_CommandSubType_bits 2 #define GFX7_3DSTATE_SO_BUFFER_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SO_BUFFER_CommandSubType_start 27 #define GFX12_3DSTATE_SO_BUFFER_CommandSubType_start 27 #define GFX11_3DSTATE_SO_BUFFER_CommandSubType_start 27 #define GFX9_3DSTATE_SO_BUFFER_CommandSubType_start 27 #define GFX8_3DSTATE_SO_BUFFER_CommandSubType_start 27 #define GFX75_3DSTATE_SO_BUFFER_CommandSubType_start 27 #define GFX7_3DSTATE_SO_BUFFER_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SO_BUFFER::Command Type */ #define GFX125_3DSTATE_SO_BUFFER_CommandType_bits 3 #define GFX12_3DSTATE_SO_BUFFER_CommandType_bits 3 #define GFX11_3DSTATE_SO_BUFFER_CommandType_bits 3 #define GFX9_3DSTATE_SO_BUFFER_CommandType_bits 3 #define GFX8_3DSTATE_SO_BUFFER_CommandType_bits 3 #define GFX75_3DSTATE_SO_BUFFER_CommandType_bits 3 #define GFX7_3DSTATE_SO_BUFFER_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SO_BUFFER_CommandType_start 29 #define GFX12_3DSTATE_SO_BUFFER_CommandType_start 29 #define GFX11_3DSTATE_SO_BUFFER_CommandType_start 29 #define GFX9_3DSTATE_SO_BUFFER_CommandType_start 29 #define GFX8_3DSTATE_SO_BUFFER_CommandType_start 29 #define GFX75_3DSTATE_SO_BUFFER_CommandType_start 29 #define GFX7_3DSTATE_SO_BUFFER_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SO_BUFFER::DWord Length */ #define GFX125_3DSTATE_SO_BUFFER_DWordLength_bits 8 #define GFX12_3DSTATE_SO_BUFFER_DWordLength_bits 8 #define GFX11_3DSTATE_SO_BUFFER_DWordLength_bits 8 #define GFX9_3DSTATE_SO_BUFFER_DWordLength_bits 8 #define GFX8_3DSTATE_SO_BUFFER_DWordLength_bits 8 #define GFX75_3DSTATE_SO_BUFFER_DWordLength_bits 8 #define GFX7_3DSTATE_SO_BUFFER_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SO_BUFFER_DWordLength_start 0 #define GFX12_3DSTATE_SO_BUFFER_DWordLength_start 0 #define GFX11_3DSTATE_SO_BUFFER_DWordLength_start 0 #define GFX9_3DSTATE_SO_BUFFER_DWordLength_start 0 #define GFX8_3DSTATE_SO_BUFFER_DWordLength_start 0 #define GFX75_3DSTATE_SO_BUFFER_DWordLength_start 0 #define GFX7_3DSTATE_SO_BUFFER_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SO_BUFFER::MOCS */ #define GFX125_3DSTATE_SO_BUFFER_MOCS_bits 7 #define GFX12_3DSTATE_SO_BUFFER_MOCS_bits 7 #define GFX11_3DSTATE_SO_BUFFER_MOCS_bits 7 #define GFX9_3DSTATE_SO_BUFFER_MOCS_bits 7 #define GFX8_3DSTATE_SO_BUFFER_MOCS_bits 7 #define GFX75_3DSTATE_SO_BUFFER_MOCS_bits 4 #define GFX7_3DSTATE_SO_BUFFER_MOCS_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_MOCS_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 7; case 120: return 7; case 110: return 7; case 90: return 7; case 80: return 7; case 75: return 4; case 70: return 4; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SO_BUFFER_MOCS_start 54 #define GFX12_3DSTATE_SO_BUFFER_MOCS_start 54 #define GFX11_3DSTATE_SO_BUFFER_MOCS_start 54 #define GFX9_3DSTATE_SO_BUFFER_MOCS_start 54 #define GFX8_3DSTATE_SO_BUFFER_MOCS_start 54 #define GFX75_3DSTATE_SO_BUFFER_MOCS_start 57 #define GFX7_3DSTATE_SO_BUFFER_MOCS_start 57 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_MOCS_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 54; case 120: return 54; case 110: return 54; case 90: return 54; case 80: return 54; case 75: return 57; case 70: return 57; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SO_BUFFER::SO Buffer Enable */ #define GFX125_3DSTATE_SO_BUFFER_SOBufferEnable_bits 1 #define GFX12_3DSTATE_SO_BUFFER_SOBufferEnable_bits 1 #define GFX11_3DSTATE_SO_BUFFER_SOBufferEnable_bits 1 #define GFX9_3DSTATE_SO_BUFFER_SOBufferEnable_bits 1 #define GFX8_3DSTATE_SO_BUFFER_SOBufferEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_SOBufferEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SO_BUFFER_SOBufferEnable_start 63 #define GFX12_3DSTATE_SO_BUFFER_SOBufferEnable_start 63 #define GFX11_3DSTATE_SO_BUFFER_SOBufferEnable_start 63 #define GFX9_3DSTATE_SO_BUFFER_SOBufferEnable_start 63 #define GFX8_3DSTATE_SO_BUFFER_SOBufferEnable_start 63 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_SOBufferEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 63; case 120: return 63; case 110: return 63; case 90: return 63; case 80: return 63; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SO_BUFFER::SO Buffer Index */ #define GFX125_3DSTATE_SO_BUFFER_SOBufferIndex_bits 2 #define GFX12_3DSTATE_SO_BUFFER_SOBufferIndex_bits 2 #define GFX11_3DSTATE_SO_BUFFER_SOBufferIndex_bits 2 #define GFX9_3DSTATE_SO_BUFFER_SOBufferIndex_bits 2 #define GFX8_3DSTATE_SO_BUFFER_SOBufferIndex_bits 2 #define GFX75_3DSTATE_SO_BUFFER_SOBufferIndex_bits 2 #define GFX7_3DSTATE_SO_BUFFER_SOBufferIndex_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_SOBufferIndex_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SO_BUFFER_SOBufferIndex_start 61 #define GFX12_3DSTATE_SO_BUFFER_SOBufferIndex_start 61 #define GFX11_3DSTATE_SO_BUFFER_SOBufferIndex_start 61 #define GFX9_3DSTATE_SO_BUFFER_SOBufferIndex_start 61 #define GFX8_3DSTATE_SO_BUFFER_SOBufferIndex_start 61 #define GFX75_3DSTATE_SO_BUFFER_SOBufferIndex_start 61 #define GFX7_3DSTATE_SO_BUFFER_SOBufferIndex_start 61 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_SOBufferIndex_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 61; case 120: return 61; case 110: return 61; case 90: return 61; case 80: return 61; case 75: return 61; case 70: return 61; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SO_BUFFER::Stream Offset */ #define GFX125_3DSTATE_SO_BUFFER_StreamOffset_bits 32 #define GFX12_3DSTATE_SO_BUFFER_StreamOffset_bits 32 #define GFX11_3DSTATE_SO_BUFFER_StreamOffset_bits 32 #define GFX9_3DSTATE_SO_BUFFER_StreamOffset_bits 32 #define GFX8_3DSTATE_SO_BUFFER_StreamOffset_bits 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_StreamOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SO_BUFFER_StreamOffset_start 224 #define GFX12_3DSTATE_SO_BUFFER_StreamOffset_start 224 #define GFX11_3DSTATE_SO_BUFFER_StreamOffset_start 224 #define GFX9_3DSTATE_SO_BUFFER_StreamOffset_start 224 #define GFX8_3DSTATE_SO_BUFFER_StreamOffset_start 224 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_StreamOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 224; case 120: return 224; case 110: return 224; case 90: return 224; case 80: return 224; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SO_BUFFER::Stream Offset Write Enable */ #define GFX125_3DSTATE_SO_BUFFER_StreamOffsetWriteEnable_bits 1 #define GFX12_3DSTATE_SO_BUFFER_StreamOffsetWriteEnable_bits 1 #define GFX11_3DSTATE_SO_BUFFER_StreamOffsetWriteEnable_bits 1 #define GFX9_3DSTATE_SO_BUFFER_StreamOffsetWriteEnable_bits 1 #define GFX8_3DSTATE_SO_BUFFER_StreamOffsetWriteEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_StreamOffsetWriteEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SO_BUFFER_StreamOffsetWriteEnable_start 53 #define GFX12_3DSTATE_SO_BUFFER_StreamOffsetWriteEnable_start 53 #define GFX11_3DSTATE_SO_BUFFER_StreamOffsetWriteEnable_start 53 #define GFX9_3DSTATE_SO_BUFFER_StreamOffsetWriteEnable_start 53 #define GFX8_3DSTATE_SO_BUFFER_StreamOffsetWriteEnable_start 53 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_StreamOffsetWriteEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 53; case 120: return 53; case 110: return 53; case 90: return 53; case 80: return 53; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SO_BUFFER::Stream Output Buffer Offset Address */ #define GFX125_3DSTATE_SO_BUFFER_StreamOutputBufferOffsetAddress_bits 46 #define GFX12_3DSTATE_SO_BUFFER_StreamOutputBufferOffsetAddress_bits 46 #define GFX11_3DSTATE_SO_BUFFER_StreamOutputBufferOffsetAddress_bits 46 #define GFX9_3DSTATE_SO_BUFFER_StreamOutputBufferOffsetAddress_bits 46 #define GFX8_3DSTATE_SO_BUFFER_StreamOutputBufferOffsetAddress_bits 46 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_StreamOutputBufferOffsetAddress_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 46; case 120: return 46; case 110: return 46; case 90: return 46; case 80: return 46; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SO_BUFFER_StreamOutputBufferOffsetAddress_start 162 #define GFX12_3DSTATE_SO_BUFFER_StreamOutputBufferOffsetAddress_start 162 #define GFX11_3DSTATE_SO_BUFFER_StreamOutputBufferOffsetAddress_start 162 #define GFX9_3DSTATE_SO_BUFFER_StreamOutputBufferOffsetAddress_start 162 #define GFX8_3DSTATE_SO_BUFFER_StreamOutputBufferOffsetAddress_start 162 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_StreamOutputBufferOffsetAddress_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 162; case 120: return 162; case 110: return 162; case 90: return 162; case 80: return 162; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SO_BUFFER::Stream Output Buffer Offset Address Enable */ #define GFX125_3DSTATE_SO_BUFFER_StreamOutputBufferOffsetAddressEnable_bits 1 #define GFX12_3DSTATE_SO_BUFFER_StreamOutputBufferOffsetAddressEnable_bits 1 #define GFX11_3DSTATE_SO_BUFFER_StreamOutputBufferOffsetAddressEnable_bits 1 #define GFX9_3DSTATE_SO_BUFFER_StreamOutputBufferOffsetAddressEnable_bits 1 #define GFX8_3DSTATE_SO_BUFFER_StreamOutputBufferOffsetAddressEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_StreamOutputBufferOffsetAddressEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SO_BUFFER_StreamOutputBufferOffsetAddressEnable_start 52 #define GFX12_3DSTATE_SO_BUFFER_StreamOutputBufferOffsetAddressEnable_start 52 #define GFX11_3DSTATE_SO_BUFFER_StreamOutputBufferOffsetAddressEnable_start 52 #define GFX9_3DSTATE_SO_BUFFER_StreamOutputBufferOffsetAddressEnable_start 52 #define GFX8_3DSTATE_SO_BUFFER_StreamOutputBufferOffsetAddressEnable_start 52 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_StreamOutputBufferOffsetAddressEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 52; case 120: return 52; case 110: return 52; case 90: return 52; case 80: return 52; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SO_BUFFER::Surface Base Address */ #define GFX125_3DSTATE_SO_BUFFER_SurfaceBaseAddress_bits 46 #define GFX12_3DSTATE_SO_BUFFER_SurfaceBaseAddress_bits 46 #define GFX11_3DSTATE_SO_BUFFER_SurfaceBaseAddress_bits 46 #define GFX9_3DSTATE_SO_BUFFER_SurfaceBaseAddress_bits 46 #define GFX8_3DSTATE_SO_BUFFER_SurfaceBaseAddress_bits 46 #define GFX75_3DSTATE_SO_BUFFER_SurfaceBaseAddress_bits 30 #define GFX7_3DSTATE_SO_BUFFER_SurfaceBaseAddress_bits 30 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_SurfaceBaseAddress_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 46; case 120: return 46; case 110: return 46; case 90: return 46; case 80: return 46; case 75: return 30; case 70: return 30; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SO_BUFFER_SurfaceBaseAddress_start 66 #define GFX12_3DSTATE_SO_BUFFER_SurfaceBaseAddress_start 66 #define GFX11_3DSTATE_SO_BUFFER_SurfaceBaseAddress_start 66 #define GFX9_3DSTATE_SO_BUFFER_SurfaceBaseAddress_start 66 #define GFX8_3DSTATE_SO_BUFFER_SurfaceBaseAddress_start 66 #define GFX75_3DSTATE_SO_BUFFER_SurfaceBaseAddress_start 66 #define GFX7_3DSTATE_SO_BUFFER_SurfaceBaseAddress_start 66 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_SurfaceBaseAddress_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 66; case 120: return 66; case 110: return 66; case 90: return 66; case 80: return 66; case 75: return 66; case 70: return 66; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SO_BUFFER::Surface End Address */ #define GFX75_3DSTATE_SO_BUFFER_SurfaceEndAddress_bits 30 #define GFX7_3DSTATE_SO_BUFFER_SurfaceEndAddress_bits 30 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_SurfaceEndAddress_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 30; case 70: return 30; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_SO_BUFFER_SurfaceEndAddress_start 98 #define GFX7_3DSTATE_SO_BUFFER_SurfaceEndAddress_start 98 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_SurfaceEndAddress_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 98; case 70: return 98; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SO_BUFFER::Surface Pitch */ #define GFX75_3DSTATE_SO_BUFFER_SurfacePitch_bits 12 #define GFX7_3DSTATE_SO_BUFFER_SurfacePitch_bits 12 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_SurfacePitch_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 12; case 70: return 12; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_SO_BUFFER_SurfacePitch_start 32 #define GFX7_3DSTATE_SO_BUFFER_SurfacePitch_start 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_SurfacePitch_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 32; case 70: return 32; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SO_BUFFER::Surface Size */ #define GFX125_3DSTATE_SO_BUFFER_SurfaceSize_bits 30 #define GFX12_3DSTATE_SO_BUFFER_SurfaceSize_bits 30 #define GFX11_3DSTATE_SO_BUFFER_SurfaceSize_bits 30 #define GFX9_3DSTATE_SO_BUFFER_SurfaceSize_bits 30 #define GFX8_3DSTATE_SO_BUFFER_SurfaceSize_bits 30 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_SurfaceSize_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 30; case 120: return 30; case 110: return 30; case 90: return 30; case 80: return 30; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SO_BUFFER_SurfaceSize_start 128 #define GFX12_3DSTATE_SO_BUFFER_SurfaceSize_start 128 #define GFX11_3DSTATE_SO_BUFFER_SurfaceSize_start 128 #define GFX9_3DSTATE_SO_BUFFER_SurfaceSize_start 128 #define GFX8_3DSTATE_SO_BUFFER_SurfaceSize_start 128 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_SurfaceSize_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 128; case 120: return 128; case 110: return 128; case 90: return 128; case 80: return 128; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SO_BUFFER_INDEX_0 */ #define GFX125_3DSTATE_SO_BUFFER_INDEX_0_length 8 #define GFX12_3DSTATE_SO_BUFFER_INDEX_0_length 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_INDEX_0_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SO_BUFFER_INDEX_0::3D Command Opcode */ #define GFX125_3DSTATE_SO_BUFFER_INDEX_0_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_SO_BUFFER_INDEX_0_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_INDEX_0_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SO_BUFFER_INDEX_0_3DCommandOpcode_start 24 #define GFX12_3DSTATE_SO_BUFFER_INDEX_0_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_INDEX_0_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SO_BUFFER_INDEX_0::3D Command Sub Opcode */ #define GFX125_3DSTATE_SO_BUFFER_INDEX_0_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_SO_BUFFER_INDEX_0_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_INDEX_0_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SO_BUFFER_INDEX_0_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_SO_BUFFER_INDEX_0_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_INDEX_0_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SO_BUFFER_INDEX_0::Command SubType */ #define GFX125_3DSTATE_SO_BUFFER_INDEX_0_CommandSubType_bits 2 #define GFX12_3DSTATE_SO_BUFFER_INDEX_0_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_INDEX_0_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SO_BUFFER_INDEX_0_CommandSubType_start 27 #define GFX12_3DSTATE_SO_BUFFER_INDEX_0_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_INDEX_0_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SO_BUFFER_INDEX_0::Command Type */ #define GFX125_3DSTATE_SO_BUFFER_INDEX_0_CommandType_bits 3 #define GFX12_3DSTATE_SO_BUFFER_INDEX_0_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_INDEX_0_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SO_BUFFER_INDEX_0_CommandType_start 29 #define GFX12_3DSTATE_SO_BUFFER_INDEX_0_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_INDEX_0_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SO_BUFFER_INDEX_0::DWord Length */ #define GFX125_3DSTATE_SO_BUFFER_INDEX_0_DWordLength_bits 8 #define GFX12_3DSTATE_SO_BUFFER_INDEX_0_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_INDEX_0_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SO_BUFFER_INDEX_0_DWordLength_start 0 #define GFX12_3DSTATE_SO_BUFFER_INDEX_0_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_INDEX_0_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SO_BUFFER_INDEX_0::SO Buffer Index State Body */ #define GFX125_3DSTATE_SO_BUFFER_INDEX_0_SOBufferIndexStateBody_bits 224 #define GFX12_3DSTATE_SO_BUFFER_INDEX_0_SOBufferIndexStateBody_bits 224 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_INDEX_0_SOBufferIndexStateBody_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 224; case 120: return 224; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SO_BUFFER_INDEX_0_SOBufferIndexStateBody_start 32 #define GFX12_3DSTATE_SO_BUFFER_INDEX_0_SOBufferIndexStateBody_start 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_INDEX_0_SOBufferIndexStateBody_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SO_BUFFER_INDEX_1 */ #define GFX125_3DSTATE_SO_BUFFER_INDEX_1_length 8 #define GFX12_3DSTATE_SO_BUFFER_INDEX_1_length 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_INDEX_1_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SO_BUFFER_INDEX_1::3D Command Opcode */ #define GFX125_3DSTATE_SO_BUFFER_INDEX_1_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_SO_BUFFER_INDEX_1_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_INDEX_1_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SO_BUFFER_INDEX_1_3DCommandOpcode_start 24 #define GFX12_3DSTATE_SO_BUFFER_INDEX_1_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_INDEX_1_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SO_BUFFER_INDEX_1::3D Command Sub Opcode */ #define GFX125_3DSTATE_SO_BUFFER_INDEX_1_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_SO_BUFFER_INDEX_1_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_INDEX_1_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SO_BUFFER_INDEX_1_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_SO_BUFFER_INDEX_1_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_INDEX_1_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SO_BUFFER_INDEX_1::Command SubType */ #define GFX125_3DSTATE_SO_BUFFER_INDEX_1_CommandSubType_bits 2 #define GFX12_3DSTATE_SO_BUFFER_INDEX_1_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_INDEX_1_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SO_BUFFER_INDEX_1_CommandSubType_start 27 #define GFX12_3DSTATE_SO_BUFFER_INDEX_1_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_INDEX_1_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SO_BUFFER_INDEX_1::Command Type */ #define GFX125_3DSTATE_SO_BUFFER_INDEX_1_CommandType_bits 3 #define GFX12_3DSTATE_SO_BUFFER_INDEX_1_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_INDEX_1_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SO_BUFFER_INDEX_1_CommandType_start 29 #define GFX12_3DSTATE_SO_BUFFER_INDEX_1_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_INDEX_1_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SO_BUFFER_INDEX_1::DWord Length */ #define GFX125_3DSTATE_SO_BUFFER_INDEX_1_DWordLength_bits 8 #define GFX12_3DSTATE_SO_BUFFER_INDEX_1_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_INDEX_1_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SO_BUFFER_INDEX_1_DWordLength_start 0 #define GFX12_3DSTATE_SO_BUFFER_INDEX_1_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_INDEX_1_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SO_BUFFER_INDEX_1::SO Buffer Index State Body */ #define GFX125_3DSTATE_SO_BUFFER_INDEX_1_SOBufferIndexStateBody_bits 224 #define GFX12_3DSTATE_SO_BUFFER_INDEX_1_SOBufferIndexStateBody_bits 224 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_INDEX_1_SOBufferIndexStateBody_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 224; case 120: return 224; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SO_BUFFER_INDEX_1_SOBufferIndexStateBody_start 32 #define GFX12_3DSTATE_SO_BUFFER_INDEX_1_SOBufferIndexStateBody_start 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_INDEX_1_SOBufferIndexStateBody_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SO_BUFFER_INDEX_2 */ #define GFX125_3DSTATE_SO_BUFFER_INDEX_2_length 8 #define GFX12_3DSTATE_SO_BUFFER_INDEX_2_length 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_INDEX_2_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SO_BUFFER_INDEX_2::3D Command Opcode */ #define GFX125_3DSTATE_SO_BUFFER_INDEX_2_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_SO_BUFFER_INDEX_2_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_INDEX_2_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SO_BUFFER_INDEX_2_3DCommandOpcode_start 24 #define GFX12_3DSTATE_SO_BUFFER_INDEX_2_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_INDEX_2_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SO_BUFFER_INDEX_2::3D Command Sub Opcode */ #define GFX125_3DSTATE_SO_BUFFER_INDEX_2_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_SO_BUFFER_INDEX_2_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_INDEX_2_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SO_BUFFER_INDEX_2_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_SO_BUFFER_INDEX_2_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_INDEX_2_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SO_BUFFER_INDEX_2::Command SubType */ #define GFX125_3DSTATE_SO_BUFFER_INDEX_2_CommandSubType_bits 2 #define GFX12_3DSTATE_SO_BUFFER_INDEX_2_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_INDEX_2_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SO_BUFFER_INDEX_2_CommandSubType_start 27 #define GFX12_3DSTATE_SO_BUFFER_INDEX_2_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_INDEX_2_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SO_BUFFER_INDEX_2::Command Type */ #define GFX125_3DSTATE_SO_BUFFER_INDEX_2_CommandType_bits 3 #define GFX12_3DSTATE_SO_BUFFER_INDEX_2_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_INDEX_2_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SO_BUFFER_INDEX_2_CommandType_start 29 #define GFX12_3DSTATE_SO_BUFFER_INDEX_2_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_INDEX_2_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SO_BUFFER_INDEX_2::DWord Length */ #define GFX125_3DSTATE_SO_BUFFER_INDEX_2_DWordLength_bits 8 #define GFX12_3DSTATE_SO_BUFFER_INDEX_2_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_INDEX_2_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SO_BUFFER_INDEX_2_DWordLength_start 0 #define GFX12_3DSTATE_SO_BUFFER_INDEX_2_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_INDEX_2_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SO_BUFFER_INDEX_2::SO Buffer Index State Body */ #define GFX125_3DSTATE_SO_BUFFER_INDEX_2_SOBufferIndexStateBody_bits 224 #define GFX12_3DSTATE_SO_BUFFER_INDEX_2_SOBufferIndexStateBody_bits 224 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_INDEX_2_SOBufferIndexStateBody_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 224; case 120: return 224; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SO_BUFFER_INDEX_2_SOBufferIndexStateBody_start 32 #define GFX12_3DSTATE_SO_BUFFER_INDEX_2_SOBufferIndexStateBody_start 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_INDEX_2_SOBufferIndexStateBody_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SO_BUFFER_INDEX_3 */ #define GFX125_3DSTATE_SO_BUFFER_INDEX_3_length 8 #define GFX12_3DSTATE_SO_BUFFER_INDEX_3_length 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_INDEX_3_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SO_BUFFER_INDEX_3::3D Command Opcode */ #define GFX125_3DSTATE_SO_BUFFER_INDEX_3_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_SO_BUFFER_INDEX_3_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_INDEX_3_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SO_BUFFER_INDEX_3_3DCommandOpcode_start 24 #define GFX12_3DSTATE_SO_BUFFER_INDEX_3_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_INDEX_3_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SO_BUFFER_INDEX_3::3D Command Sub Opcode */ #define GFX125_3DSTATE_SO_BUFFER_INDEX_3_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_SO_BUFFER_INDEX_3_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_INDEX_3_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SO_BUFFER_INDEX_3_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_SO_BUFFER_INDEX_3_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_INDEX_3_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SO_BUFFER_INDEX_3::Command SubType */ #define GFX125_3DSTATE_SO_BUFFER_INDEX_3_CommandSubType_bits 2 #define GFX12_3DSTATE_SO_BUFFER_INDEX_3_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_INDEX_3_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SO_BUFFER_INDEX_3_CommandSubType_start 27 #define GFX12_3DSTATE_SO_BUFFER_INDEX_3_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_INDEX_3_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SO_BUFFER_INDEX_3::Command Type */ #define GFX125_3DSTATE_SO_BUFFER_INDEX_3_CommandType_bits 3 #define GFX12_3DSTATE_SO_BUFFER_INDEX_3_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_INDEX_3_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SO_BUFFER_INDEX_3_CommandType_start 29 #define GFX12_3DSTATE_SO_BUFFER_INDEX_3_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_INDEX_3_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SO_BUFFER_INDEX_3::DWord Length */ #define GFX125_3DSTATE_SO_BUFFER_INDEX_3_DWordLength_bits 8 #define GFX12_3DSTATE_SO_BUFFER_INDEX_3_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_INDEX_3_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SO_BUFFER_INDEX_3_DWordLength_start 0 #define GFX12_3DSTATE_SO_BUFFER_INDEX_3_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_INDEX_3_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SO_BUFFER_INDEX_3::SO Buffer Index State Body */ #define GFX125_3DSTATE_SO_BUFFER_INDEX_3_SOBufferIndexStateBody_bits 224 #define GFX12_3DSTATE_SO_BUFFER_INDEX_3_SOBufferIndexStateBody_bits 224 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_INDEX_3_SOBufferIndexStateBody_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 224; case 120: return 224; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SO_BUFFER_INDEX_3_SOBufferIndexStateBody_start 32 #define GFX12_3DSTATE_SO_BUFFER_INDEX_3_SOBufferIndexStateBody_start 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_INDEX_3_SOBufferIndexStateBody_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SO_BUFFER_INDEX_BODY */ #define GFX125_3DSTATE_SO_BUFFER_INDEX_BODY_length 7 #define GFX12_3DSTATE_SO_BUFFER_INDEX_BODY_length 7 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_INDEX_BODY_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 7; case 120: return 7; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SO_BUFFER_INDEX_BODY::MOCS */ #define GFX125_3DSTATE_SO_BUFFER_INDEX_BODY_MOCS_bits 7 #define GFX12_3DSTATE_SO_BUFFER_INDEX_BODY_MOCS_bits 7 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_INDEX_BODY_MOCS_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 7; case 120: return 7; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SO_BUFFER_INDEX_BODY_MOCS_start 22 #define GFX12_3DSTATE_SO_BUFFER_INDEX_BODY_MOCS_start 22 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_INDEX_BODY_MOCS_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 22; case 120: return 22; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SO_BUFFER_INDEX_BODY::SO Buffer Enable */ #define GFX125_3DSTATE_SO_BUFFER_INDEX_BODY_SOBufferEnable_bits 1 #define GFX12_3DSTATE_SO_BUFFER_INDEX_BODY_SOBufferEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_INDEX_BODY_SOBufferEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SO_BUFFER_INDEX_BODY_SOBufferEnable_start 31 #define GFX12_3DSTATE_SO_BUFFER_INDEX_BODY_SOBufferEnable_start 31 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_INDEX_BODY_SOBufferEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 31; case 120: return 31; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SO_BUFFER_INDEX_BODY::Stream Offset */ #define GFX125_3DSTATE_SO_BUFFER_INDEX_BODY_StreamOffset_bits 32 #define GFX12_3DSTATE_SO_BUFFER_INDEX_BODY_StreamOffset_bits 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_INDEX_BODY_StreamOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SO_BUFFER_INDEX_BODY_StreamOffset_start 192 #define GFX12_3DSTATE_SO_BUFFER_INDEX_BODY_StreamOffset_start 192 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_INDEX_BODY_StreamOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 192; case 120: return 192; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SO_BUFFER_INDEX_BODY::Stream Offset Write Enable */ #define GFX125_3DSTATE_SO_BUFFER_INDEX_BODY_StreamOffsetWriteEnable_bits 1 #define GFX12_3DSTATE_SO_BUFFER_INDEX_BODY_StreamOffsetWriteEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_INDEX_BODY_StreamOffsetWriteEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SO_BUFFER_INDEX_BODY_StreamOffsetWriteEnable_start 21 #define GFX12_3DSTATE_SO_BUFFER_INDEX_BODY_StreamOffsetWriteEnable_start 21 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_INDEX_BODY_StreamOffsetWriteEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 21; case 120: return 21; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SO_BUFFER_INDEX_BODY::Stream Output Buffer Offset Address */ #define GFX125_3DSTATE_SO_BUFFER_INDEX_BODY_StreamOutputBufferOffsetAddress_bits 46 #define GFX12_3DSTATE_SO_BUFFER_INDEX_BODY_StreamOutputBufferOffsetAddress_bits 46 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_INDEX_BODY_StreamOutputBufferOffsetAddress_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 46; case 120: return 46; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SO_BUFFER_INDEX_BODY_StreamOutputBufferOffsetAddress_start 130 #define GFX12_3DSTATE_SO_BUFFER_INDEX_BODY_StreamOutputBufferOffsetAddress_start 130 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_INDEX_BODY_StreamOutputBufferOffsetAddress_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 130; case 120: return 130; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SO_BUFFER_INDEX_BODY::Stream Output Buffer Offset Address Enable */ #define GFX125_3DSTATE_SO_BUFFER_INDEX_BODY_StreamOutputBufferOffsetAddressEnable_bits 1 #define GFX12_3DSTATE_SO_BUFFER_INDEX_BODY_StreamOutputBufferOffsetAddressEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_INDEX_BODY_StreamOutputBufferOffsetAddressEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SO_BUFFER_INDEX_BODY_StreamOutputBufferOffsetAddressEnable_start 20 #define GFX12_3DSTATE_SO_BUFFER_INDEX_BODY_StreamOutputBufferOffsetAddressEnable_start 20 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_INDEX_BODY_StreamOutputBufferOffsetAddressEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 20; case 120: return 20; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SO_BUFFER_INDEX_BODY::Surface Base Address */ #define GFX125_3DSTATE_SO_BUFFER_INDEX_BODY_SurfaceBaseAddress_bits 46 #define GFX12_3DSTATE_SO_BUFFER_INDEX_BODY_SurfaceBaseAddress_bits 46 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_INDEX_BODY_SurfaceBaseAddress_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 46; case 120: return 46; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SO_BUFFER_INDEX_BODY_SurfaceBaseAddress_start 34 #define GFX12_3DSTATE_SO_BUFFER_INDEX_BODY_SurfaceBaseAddress_start 34 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_INDEX_BODY_SurfaceBaseAddress_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 34; case 120: return 34; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SO_BUFFER_INDEX_BODY::Surface Size */ #define GFX125_3DSTATE_SO_BUFFER_INDEX_BODY_SurfaceSize_bits 30 #define GFX12_3DSTATE_SO_BUFFER_INDEX_BODY_SurfaceSize_bits 30 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_INDEX_BODY_SurfaceSize_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 30; case 120: return 30; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SO_BUFFER_INDEX_BODY_SurfaceSize_start 96 #define GFX12_3DSTATE_SO_BUFFER_INDEX_BODY_SurfaceSize_start 96 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_BUFFER_INDEX_BODY_SurfaceSize_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 96; case 120: return 96; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SO_DECL_LIST */ /* 3DSTATE_SO_DECL_LIST::3D Command Opcode */ #define GFX125_3DSTATE_SO_DECL_LIST_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_SO_DECL_LIST_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_SO_DECL_LIST_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_SO_DECL_LIST_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_SO_DECL_LIST_3DCommandOpcode_bits 3 #define GFX75_3DSTATE_SO_DECL_LIST_3DCommandOpcode_bits 3 #define GFX7_3DSTATE_SO_DECL_LIST_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_DECL_LIST_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SO_DECL_LIST_3DCommandOpcode_start 24 #define GFX12_3DSTATE_SO_DECL_LIST_3DCommandOpcode_start 24 #define GFX11_3DSTATE_SO_DECL_LIST_3DCommandOpcode_start 24 #define GFX9_3DSTATE_SO_DECL_LIST_3DCommandOpcode_start 24 #define GFX8_3DSTATE_SO_DECL_LIST_3DCommandOpcode_start 24 #define GFX75_3DSTATE_SO_DECL_LIST_3DCommandOpcode_start 24 #define GFX7_3DSTATE_SO_DECL_LIST_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_DECL_LIST_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SO_DECL_LIST::3D Command Sub Opcode */ #define GFX125_3DSTATE_SO_DECL_LIST_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_SO_DECL_LIST_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_SO_DECL_LIST_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_SO_DECL_LIST_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_SO_DECL_LIST_3DCommandSubOpcode_bits 8 #define GFX75_3DSTATE_SO_DECL_LIST_3DCommandSubOpcode_bits 8 #define GFX7_3DSTATE_SO_DECL_LIST_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_DECL_LIST_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SO_DECL_LIST_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_SO_DECL_LIST_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_SO_DECL_LIST_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_SO_DECL_LIST_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_SO_DECL_LIST_3DCommandSubOpcode_start 16 #define GFX75_3DSTATE_SO_DECL_LIST_3DCommandSubOpcode_start 16 #define GFX7_3DSTATE_SO_DECL_LIST_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_DECL_LIST_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SO_DECL_LIST::Command SubType */ #define GFX125_3DSTATE_SO_DECL_LIST_CommandSubType_bits 2 #define GFX12_3DSTATE_SO_DECL_LIST_CommandSubType_bits 2 #define GFX11_3DSTATE_SO_DECL_LIST_CommandSubType_bits 2 #define GFX9_3DSTATE_SO_DECL_LIST_CommandSubType_bits 2 #define GFX8_3DSTATE_SO_DECL_LIST_CommandSubType_bits 2 #define GFX75_3DSTATE_SO_DECL_LIST_CommandSubType_bits 2 #define GFX7_3DSTATE_SO_DECL_LIST_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_DECL_LIST_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SO_DECL_LIST_CommandSubType_start 27 #define GFX12_3DSTATE_SO_DECL_LIST_CommandSubType_start 27 #define GFX11_3DSTATE_SO_DECL_LIST_CommandSubType_start 27 #define GFX9_3DSTATE_SO_DECL_LIST_CommandSubType_start 27 #define GFX8_3DSTATE_SO_DECL_LIST_CommandSubType_start 27 #define GFX75_3DSTATE_SO_DECL_LIST_CommandSubType_start 27 #define GFX7_3DSTATE_SO_DECL_LIST_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_DECL_LIST_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SO_DECL_LIST::Command Type */ #define GFX125_3DSTATE_SO_DECL_LIST_CommandType_bits 3 #define GFX12_3DSTATE_SO_DECL_LIST_CommandType_bits 3 #define GFX11_3DSTATE_SO_DECL_LIST_CommandType_bits 3 #define GFX9_3DSTATE_SO_DECL_LIST_CommandType_bits 3 #define GFX8_3DSTATE_SO_DECL_LIST_CommandType_bits 3 #define GFX75_3DSTATE_SO_DECL_LIST_CommandType_bits 3 #define GFX7_3DSTATE_SO_DECL_LIST_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_DECL_LIST_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SO_DECL_LIST_CommandType_start 29 #define GFX12_3DSTATE_SO_DECL_LIST_CommandType_start 29 #define GFX11_3DSTATE_SO_DECL_LIST_CommandType_start 29 #define GFX9_3DSTATE_SO_DECL_LIST_CommandType_start 29 #define GFX8_3DSTATE_SO_DECL_LIST_CommandType_start 29 #define GFX75_3DSTATE_SO_DECL_LIST_CommandType_start 29 #define GFX7_3DSTATE_SO_DECL_LIST_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_DECL_LIST_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SO_DECL_LIST::DWord Length */ #define GFX125_3DSTATE_SO_DECL_LIST_DWordLength_bits 9 #define GFX12_3DSTATE_SO_DECL_LIST_DWordLength_bits 9 #define GFX11_3DSTATE_SO_DECL_LIST_DWordLength_bits 9 #define GFX9_3DSTATE_SO_DECL_LIST_DWordLength_bits 9 #define GFX8_3DSTATE_SO_DECL_LIST_DWordLength_bits 9 #define GFX75_3DSTATE_SO_DECL_LIST_DWordLength_bits 9 #define GFX7_3DSTATE_SO_DECL_LIST_DWordLength_bits 9 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_DECL_LIST_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 9; case 120: return 9; case 110: return 9; case 90: return 9; case 80: return 9; case 75: return 9; case 70: return 9; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SO_DECL_LIST_DWordLength_start 0 #define GFX12_3DSTATE_SO_DECL_LIST_DWordLength_start 0 #define GFX11_3DSTATE_SO_DECL_LIST_DWordLength_start 0 #define GFX9_3DSTATE_SO_DECL_LIST_DWordLength_start 0 #define GFX8_3DSTATE_SO_DECL_LIST_DWordLength_start 0 #define GFX75_3DSTATE_SO_DECL_LIST_DWordLength_start 0 #define GFX7_3DSTATE_SO_DECL_LIST_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_DECL_LIST_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SO_DECL_LIST::Num Entries [0] */ #define GFX125_3DSTATE_SO_DECL_LIST_NumEntries0_bits 8 #define GFX12_3DSTATE_SO_DECL_LIST_NumEntries0_bits 8 #define GFX11_3DSTATE_SO_DECL_LIST_NumEntries0_bits 8 #define GFX9_3DSTATE_SO_DECL_LIST_NumEntries0_bits 8 #define GFX8_3DSTATE_SO_DECL_LIST_NumEntries0_bits 8 #define GFX75_3DSTATE_SO_DECL_LIST_NumEntries0_bits 8 #define GFX7_3DSTATE_SO_DECL_LIST_NumEntries0_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_DECL_LIST_NumEntries0_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SO_DECL_LIST_NumEntries0_start 64 #define GFX12_3DSTATE_SO_DECL_LIST_NumEntries0_start 64 #define GFX11_3DSTATE_SO_DECL_LIST_NumEntries0_start 64 #define GFX9_3DSTATE_SO_DECL_LIST_NumEntries0_start 64 #define GFX8_3DSTATE_SO_DECL_LIST_NumEntries0_start 64 #define GFX75_3DSTATE_SO_DECL_LIST_NumEntries0_start 64 #define GFX7_3DSTATE_SO_DECL_LIST_NumEntries0_start 64 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_DECL_LIST_NumEntries0_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 64; case 80: return 64; case 75: return 64; case 70: return 64; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SO_DECL_LIST::Num Entries [1] */ #define GFX125_3DSTATE_SO_DECL_LIST_NumEntries1_bits 8 #define GFX12_3DSTATE_SO_DECL_LIST_NumEntries1_bits 8 #define GFX11_3DSTATE_SO_DECL_LIST_NumEntries1_bits 8 #define GFX9_3DSTATE_SO_DECL_LIST_NumEntries1_bits 8 #define GFX8_3DSTATE_SO_DECL_LIST_NumEntries1_bits 8 #define GFX75_3DSTATE_SO_DECL_LIST_NumEntries1_bits 8 #define GFX7_3DSTATE_SO_DECL_LIST_NumEntries1_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_DECL_LIST_NumEntries1_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SO_DECL_LIST_NumEntries1_start 72 #define GFX12_3DSTATE_SO_DECL_LIST_NumEntries1_start 72 #define GFX11_3DSTATE_SO_DECL_LIST_NumEntries1_start 72 #define GFX9_3DSTATE_SO_DECL_LIST_NumEntries1_start 72 #define GFX8_3DSTATE_SO_DECL_LIST_NumEntries1_start 72 #define GFX75_3DSTATE_SO_DECL_LIST_NumEntries1_start 72 #define GFX7_3DSTATE_SO_DECL_LIST_NumEntries1_start 72 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_DECL_LIST_NumEntries1_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 72; case 120: return 72; case 110: return 72; case 90: return 72; case 80: return 72; case 75: return 72; case 70: return 72; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SO_DECL_LIST::Num Entries [2] */ #define GFX125_3DSTATE_SO_DECL_LIST_NumEntries2_bits 8 #define GFX12_3DSTATE_SO_DECL_LIST_NumEntries2_bits 8 #define GFX11_3DSTATE_SO_DECL_LIST_NumEntries2_bits 8 #define GFX9_3DSTATE_SO_DECL_LIST_NumEntries2_bits 8 #define GFX8_3DSTATE_SO_DECL_LIST_NumEntries2_bits 8 #define GFX75_3DSTATE_SO_DECL_LIST_NumEntries2_bits 8 #define GFX7_3DSTATE_SO_DECL_LIST_NumEntries2_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_DECL_LIST_NumEntries2_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SO_DECL_LIST_NumEntries2_start 80 #define GFX12_3DSTATE_SO_DECL_LIST_NumEntries2_start 80 #define GFX11_3DSTATE_SO_DECL_LIST_NumEntries2_start 80 #define GFX9_3DSTATE_SO_DECL_LIST_NumEntries2_start 80 #define GFX8_3DSTATE_SO_DECL_LIST_NumEntries2_start 80 #define GFX75_3DSTATE_SO_DECL_LIST_NumEntries2_start 80 #define GFX7_3DSTATE_SO_DECL_LIST_NumEntries2_start 80 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_DECL_LIST_NumEntries2_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 80; case 120: return 80; case 110: return 80; case 90: return 80; case 80: return 80; case 75: return 80; case 70: return 80; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SO_DECL_LIST::Num Entries [3] */ #define GFX125_3DSTATE_SO_DECL_LIST_NumEntries3_bits 8 #define GFX12_3DSTATE_SO_DECL_LIST_NumEntries3_bits 8 #define GFX11_3DSTATE_SO_DECL_LIST_NumEntries3_bits 8 #define GFX9_3DSTATE_SO_DECL_LIST_NumEntries3_bits 8 #define GFX8_3DSTATE_SO_DECL_LIST_NumEntries3_bits 8 #define GFX75_3DSTATE_SO_DECL_LIST_NumEntries3_bits 8 #define GFX7_3DSTATE_SO_DECL_LIST_NumEntries3_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_DECL_LIST_NumEntries3_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SO_DECL_LIST_NumEntries3_start 88 #define GFX12_3DSTATE_SO_DECL_LIST_NumEntries3_start 88 #define GFX11_3DSTATE_SO_DECL_LIST_NumEntries3_start 88 #define GFX9_3DSTATE_SO_DECL_LIST_NumEntries3_start 88 #define GFX8_3DSTATE_SO_DECL_LIST_NumEntries3_start 88 #define GFX75_3DSTATE_SO_DECL_LIST_NumEntries3_start 88 #define GFX7_3DSTATE_SO_DECL_LIST_NumEntries3_start 88 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_DECL_LIST_NumEntries3_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 88; case 120: return 88; case 110: return 88; case 90: return 88; case 80: return 88; case 75: return 88; case 70: return 88; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SO_DECL_LIST::Stream to Buffer Selects [0] */ #define GFX125_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects0_bits 4 #define GFX12_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects0_bits 4 #define GFX11_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects0_bits 4 #define GFX9_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects0_bits 4 #define GFX8_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects0_bits 4 #define GFX75_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects0_bits 4 #define GFX7_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects0_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_DECL_LIST_StreamtoBufferSelects0_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 4; case 70: return 4; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects0_start 32 #define GFX12_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects0_start 32 #define GFX11_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects0_start 32 #define GFX9_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects0_start 32 #define GFX8_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects0_start 32 #define GFX75_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects0_start 32 #define GFX7_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects0_start 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_DECL_LIST_StreamtoBufferSelects0_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SO_DECL_LIST::Stream to Buffer Selects [1] */ #define GFX125_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects1_bits 4 #define GFX12_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects1_bits 4 #define GFX11_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects1_bits 4 #define GFX9_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects1_bits 4 #define GFX8_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects1_bits 4 #define GFX75_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects1_bits 4 #define GFX7_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects1_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_DECL_LIST_StreamtoBufferSelects1_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 4; case 70: return 4; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects1_start 36 #define GFX12_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects1_start 36 #define GFX11_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects1_start 36 #define GFX9_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects1_start 36 #define GFX8_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects1_start 36 #define GFX75_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects1_start 36 #define GFX7_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects1_start 36 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_DECL_LIST_StreamtoBufferSelects1_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 36; case 120: return 36; case 110: return 36; case 90: return 36; case 80: return 36; case 75: return 36; case 70: return 36; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SO_DECL_LIST::Stream to Buffer Selects [2] */ #define GFX125_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects2_bits 4 #define GFX12_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects2_bits 4 #define GFX11_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects2_bits 4 #define GFX9_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects2_bits 4 #define GFX8_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects2_bits 4 #define GFX75_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects2_bits 4 #define GFX7_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects2_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_DECL_LIST_StreamtoBufferSelects2_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 4; case 70: return 4; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects2_start 40 #define GFX12_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects2_start 40 #define GFX11_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects2_start 40 #define GFX9_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects2_start 40 #define GFX8_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects2_start 40 #define GFX75_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects2_start 40 #define GFX7_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects2_start 40 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_DECL_LIST_StreamtoBufferSelects2_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 40; case 120: return 40; case 110: return 40; case 90: return 40; case 80: return 40; case 75: return 40; case 70: return 40; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SO_DECL_LIST::Stream to Buffer Selects [3] */ #define GFX125_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects3_bits 4 #define GFX12_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects3_bits 4 #define GFX11_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects3_bits 4 #define GFX9_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects3_bits 4 #define GFX8_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects3_bits 4 #define GFX75_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects3_bits 4 #define GFX7_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects3_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_DECL_LIST_StreamtoBufferSelects3_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 4; case 70: return 4; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects3_start 44 #define GFX12_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects3_start 44 #define GFX11_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects3_start 44 #define GFX9_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects3_start 44 #define GFX8_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects3_start 44 #define GFX75_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects3_start 44 #define GFX7_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects3_start 44 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SO_DECL_LIST_StreamtoBufferSelects3_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 44; case 120: return 44; case 110: return 44; case 90: return 44; case 80: return 44; case 75: return 44; case 70: return 44; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_STENCIL_BUFFER */ #define GFX125_3DSTATE_STENCIL_BUFFER_length 8 #define GFX12_3DSTATE_STENCIL_BUFFER_length 8 #define GFX11_3DSTATE_STENCIL_BUFFER_length 5 #define GFX9_3DSTATE_STENCIL_BUFFER_length 5 #define GFX8_3DSTATE_STENCIL_BUFFER_length 5 #define GFX75_3DSTATE_STENCIL_BUFFER_length 3 #define GFX7_3DSTATE_STENCIL_BUFFER_length 3 #define GFX6_3DSTATE_STENCIL_BUFFER_length 3 #define GFX5_3DSTATE_STENCIL_BUFFER_length 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STENCIL_BUFFER_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 5; case 90: return 5; case 80: return 5; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 3; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_STENCIL_BUFFER::3D Command Opcode */ #define GFX125_3DSTATE_STENCIL_BUFFER_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_STENCIL_BUFFER_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_STENCIL_BUFFER_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_STENCIL_BUFFER_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_STENCIL_BUFFER_3DCommandOpcode_bits 3 #define GFX75_3DSTATE_STENCIL_BUFFER_3DCommandOpcode_bits 3 #define GFX7_3DSTATE_STENCIL_BUFFER_3DCommandOpcode_bits 3 #define GFX6_3DSTATE_STENCIL_BUFFER_3DCommandOpcode_bits 3 #define GFX5_3DSTATE_STENCIL_BUFFER_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STENCIL_BUFFER_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 3; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_STENCIL_BUFFER_3DCommandOpcode_start 24 #define GFX12_3DSTATE_STENCIL_BUFFER_3DCommandOpcode_start 24 #define GFX11_3DSTATE_STENCIL_BUFFER_3DCommandOpcode_start 24 #define GFX9_3DSTATE_STENCIL_BUFFER_3DCommandOpcode_start 24 #define GFX8_3DSTATE_STENCIL_BUFFER_3DCommandOpcode_start 24 #define GFX75_3DSTATE_STENCIL_BUFFER_3DCommandOpcode_start 24 #define GFX7_3DSTATE_STENCIL_BUFFER_3DCommandOpcode_start 24 #define GFX6_3DSTATE_STENCIL_BUFFER_3DCommandOpcode_start 24 #define GFX5_3DSTATE_STENCIL_BUFFER_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STENCIL_BUFFER_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 24; case 50: return 24; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_STENCIL_BUFFER::3D Command Sub Opcode */ #define GFX125_3DSTATE_STENCIL_BUFFER_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_STENCIL_BUFFER_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_STENCIL_BUFFER_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_STENCIL_BUFFER_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_STENCIL_BUFFER_3DCommandSubOpcode_bits 8 #define GFX75_3DSTATE_STENCIL_BUFFER_3DCommandSubOpcode_bits 8 #define GFX7_3DSTATE_STENCIL_BUFFER_3DCommandSubOpcode_bits 8 #define GFX6_3DSTATE_STENCIL_BUFFER_3DCommandSubOpcode_bits 8 #define GFX5_3DSTATE_STENCIL_BUFFER_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STENCIL_BUFFER_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 8; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_STENCIL_BUFFER_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_STENCIL_BUFFER_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_STENCIL_BUFFER_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_STENCIL_BUFFER_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_STENCIL_BUFFER_3DCommandSubOpcode_start 16 #define GFX75_3DSTATE_STENCIL_BUFFER_3DCommandSubOpcode_start 16 #define GFX7_3DSTATE_STENCIL_BUFFER_3DCommandSubOpcode_start 16 #define GFX6_3DSTATE_STENCIL_BUFFER_3DCommandSubOpcode_start 16 #define GFX5_3DSTATE_STENCIL_BUFFER_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STENCIL_BUFFER_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 16; case 50: return 16; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_STENCIL_BUFFER::Command SubType */ #define GFX125_3DSTATE_STENCIL_BUFFER_CommandSubType_bits 2 #define GFX12_3DSTATE_STENCIL_BUFFER_CommandSubType_bits 2 #define GFX11_3DSTATE_STENCIL_BUFFER_CommandSubType_bits 2 #define GFX9_3DSTATE_STENCIL_BUFFER_CommandSubType_bits 2 #define GFX8_3DSTATE_STENCIL_BUFFER_CommandSubType_bits 2 #define GFX75_3DSTATE_STENCIL_BUFFER_CommandSubType_bits 2 #define GFX7_3DSTATE_STENCIL_BUFFER_CommandSubType_bits 2 #define GFX6_3DSTATE_STENCIL_BUFFER_CommandSubType_bits 2 #define GFX5_3DSTATE_STENCIL_BUFFER_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STENCIL_BUFFER_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 2; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_STENCIL_BUFFER_CommandSubType_start 27 #define GFX12_3DSTATE_STENCIL_BUFFER_CommandSubType_start 27 #define GFX11_3DSTATE_STENCIL_BUFFER_CommandSubType_start 27 #define GFX9_3DSTATE_STENCIL_BUFFER_CommandSubType_start 27 #define GFX8_3DSTATE_STENCIL_BUFFER_CommandSubType_start 27 #define GFX75_3DSTATE_STENCIL_BUFFER_CommandSubType_start 27 #define GFX7_3DSTATE_STENCIL_BUFFER_CommandSubType_start 27 #define GFX6_3DSTATE_STENCIL_BUFFER_CommandSubType_start 27 #define GFX5_3DSTATE_STENCIL_BUFFER_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STENCIL_BUFFER_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 27; case 50: return 27; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_STENCIL_BUFFER::Command Type */ #define GFX125_3DSTATE_STENCIL_BUFFER_CommandType_bits 3 #define GFX12_3DSTATE_STENCIL_BUFFER_CommandType_bits 3 #define GFX11_3DSTATE_STENCIL_BUFFER_CommandType_bits 3 #define GFX9_3DSTATE_STENCIL_BUFFER_CommandType_bits 3 #define GFX8_3DSTATE_STENCIL_BUFFER_CommandType_bits 3 #define GFX75_3DSTATE_STENCIL_BUFFER_CommandType_bits 3 #define GFX7_3DSTATE_STENCIL_BUFFER_CommandType_bits 3 #define GFX6_3DSTATE_STENCIL_BUFFER_CommandType_bits 3 #define GFX5_3DSTATE_STENCIL_BUFFER_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STENCIL_BUFFER_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 3; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_STENCIL_BUFFER_CommandType_start 29 #define GFX12_3DSTATE_STENCIL_BUFFER_CommandType_start 29 #define GFX11_3DSTATE_STENCIL_BUFFER_CommandType_start 29 #define GFX9_3DSTATE_STENCIL_BUFFER_CommandType_start 29 #define GFX8_3DSTATE_STENCIL_BUFFER_CommandType_start 29 #define GFX75_3DSTATE_STENCIL_BUFFER_CommandType_start 29 #define GFX7_3DSTATE_STENCIL_BUFFER_CommandType_start 29 #define GFX6_3DSTATE_STENCIL_BUFFER_CommandType_start 29 #define GFX5_3DSTATE_STENCIL_BUFFER_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STENCIL_BUFFER_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 29; case 50: return 29; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_STENCIL_BUFFER::Compression Mode */ #define GFX125_3DSTATE_STENCIL_BUFFER_CompressionMode_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STENCIL_BUFFER_CompressionMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_STENCIL_BUFFER_CompressionMode_start 197 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STENCIL_BUFFER_CompressionMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 197; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_STENCIL_BUFFER::Control Surface Enable */ #define GFX125_3DSTATE_STENCIL_BUFFER_ControlSurfaceEnable_bits 1 #define GFX12_3DSTATE_STENCIL_BUFFER_ControlSurfaceEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STENCIL_BUFFER_ControlSurfaceEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_STENCIL_BUFFER_ControlSurfaceEnable_start 56 #define GFX12_3DSTATE_STENCIL_BUFFER_ControlSurfaceEnable_start 56 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STENCIL_BUFFER_ControlSurfaceEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 56; case 120: return 56; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_STENCIL_BUFFER::Corner Texel Mode */ #define GFX125_3DSTATE_STENCIL_BUFFER_CornerTexelMode_bits 1 #define GFX12_3DSTATE_STENCIL_BUFFER_CornerTexelMode_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STENCIL_BUFFER_CornerTexelMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_STENCIL_BUFFER_CornerTexelMode_start 55 #define GFX12_3DSTATE_STENCIL_BUFFER_CornerTexelMode_start 55 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STENCIL_BUFFER_CornerTexelMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 55; case 120: return 55; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_STENCIL_BUFFER::DWord Length */ #define GFX125_3DSTATE_STENCIL_BUFFER_DWordLength_bits 8 #define GFX12_3DSTATE_STENCIL_BUFFER_DWordLength_bits 8 #define GFX11_3DSTATE_STENCIL_BUFFER_DWordLength_bits 8 #define GFX9_3DSTATE_STENCIL_BUFFER_DWordLength_bits 8 #define GFX8_3DSTATE_STENCIL_BUFFER_DWordLength_bits 8 #define GFX75_3DSTATE_STENCIL_BUFFER_DWordLength_bits 8 #define GFX7_3DSTATE_STENCIL_BUFFER_DWordLength_bits 8 #define GFX6_3DSTATE_STENCIL_BUFFER_DWordLength_bits 8 #define GFX5_3DSTATE_STENCIL_BUFFER_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STENCIL_BUFFER_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 8; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_STENCIL_BUFFER_DWordLength_start 0 #define GFX12_3DSTATE_STENCIL_BUFFER_DWordLength_start 0 #define GFX11_3DSTATE_STENCIL_BUFFER_DWordLength_start 0 #define GFX9_3DSTATE_STENCIL_BUFFER_DWordLength_start 0 #define GFX8_3DSTATE_STENCIL_BUFFER_DWordLength_start 0 #define GFX75_3DSTATE_STENCIL_BUFFER_DWordLength_start 0 #define GFX7_3DSTATE_STENCIL_BUFFER_DWordLength_start 0 #define GFX6_3DSTATE_STENCIL_BUFFER_DWordLength_start 0 #define GFX5_3DSTATE_STENCIL_BUFFER_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STENCIL_BUFFER_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_STENCIL_BUFFER::Depth */ #define GFX125_3DSTATE_STENCIL_BUFFER_Depth_bits 11 #define GFX12_3DSTATE_STENCIL_BUFFER_Depth_bits 11 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STENCIL_BUFFER_Depth_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 11; case 120: return 11; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_STENCIL_BUFFER_Depth_start 180 #define GFX12_3DSTATE_STENCIL_BUFFER_Depth_start 180 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STENCIL_BUFFER_Depth_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 180; case 120: return 180; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_STENCIL_BUFFER::Height */ #define GFX125_3DSTATE_STENCIL_BUFFER_Height_bits 14 #define GFX12_3DSTATE_STENCIL_BUFFER_Height_bits 14 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STENCIL_BUFFER_Height_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 14; case 120: return 14; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_STENCIL_BUFFER_Height_start 145 #define GFX12_3DSTATE_STENCIL_BUFFER_Height_start 145 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STENCIL_BUFFER_Height_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 145; case 120: return 145; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_STENCIL_BUFFER::MOCS */ #define GFX125_3DSTATE_STENCIL_BUFFER_MOCS_bits 7 #define GFX12_3DSTATE_STENCIL_BUFFER_MOCS_bits 7 #define GFX11_3DSTATE_STENCIL_BUFFER_MOCS_bits 7 #define GFX9_3DSTATE_STENCIL_BUFFER_MOCS_bits 7 #define GFX8_3DSTATE_STENCIL_BUFFER_MOCS_bits 7 #define GFX75_3DSTATE_STENCIL_BUFFER_MOCS_bits 4 #define GFX7_3DSTATE_STENCIL_BUFFER_MOCS_bits 4 #define GFX6_3DSTATE_STENCIL_BUFFER_MOCS_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STENCIL_BUFFER_MOCS_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 7; case 120: return 7; case 110: return 7; case 90: return 7; case 80: return 7; case 75: return 4; case 70: return 4; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_STENCIL_BUFFER_MOCS_start 160 #define GFX12_3DSTATE_STENCIL_BUFFER_MOCS_start 160 #define GFX11_3DSTATE_STENCIL_BUFFER_MOCS_start 54 #define GFX9_3DSTATE_STENCIL_BUFFER_MOCS_start 54 #define GFX8_3DSTATE_STENCIL_BUFFER_MOCS_start 54 #define GFX75_3DSTATE_STENCIL_BUFFER_MOCS_start 57 #define GFX7_3DSTATE_STENCIL_BUFFER_MOCS_start 57 #define GFX6_3DSTATE_STENCIL_BUFFER_MOCS_start 57 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STENCIL_BUFFER_MOCS_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 160; case 120: return 160; case 110: return 54; case 90: return 54; case 80: return 54; case 75: return 57; case 70: return 57; case 60: return 57; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_STENCIL_BUFFER::Minimum Array Element */ #define GFX125_3DSTATE_STENCIL_BUFFER_MinimumArrayElement_bits 11 #define GFX12_3DSTATE_STENCIL_BUFFER_MinimumArrayElement_bits 11 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STENCIL_BUFFER_MinimumArrayElement_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 11; case 120: return 11; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_STENCIL_BUFFER_MinimumArrayElement_start 168 #define GFX12_3DSTATE_STENCIL_BUFFER_MinimumArrayElement_start 168 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STENCIL_BUFFER_MinimumArrayElement_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 168; case 120: return 168; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_STENCIL_BUFFER::Mip Tail Start LOD */ #define GFX125_3DSTATE_STENCIL_BUFFER_MipTailStartLOD_bits 4 #define GFX12_3DSTATE_STENCIL_BUFFER_MipTailStartLOD_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STENCIL_BUFFER_MipTailStartLOD_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_STENCIL_BUFFER_MipTailStartLOD_start 218 #define GFX12_3DSTATE_STENCIL_BUFFER_MipTailStartLOD_start 218 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STENCIL_BUFFER_MipTailStartLOD_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 218; case 120: return 218; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_STENCIL_BUFFER::Null Page Coherency Enable */ #define GFX125_3DSTATE_STENCIL_BUFFER_NullPageCoherencyEnable_bits 1 #define GFX12_3DSTATE_STENCIL_BUFFER_NullPageCoherencyEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STENCIL_BUFFER_NullPageCoherencyEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_STENCIL_BUFFER_NullPageCoherencyEnable_start 59 #define GFX12_3DSTATE_STENCIL_BUFFER_NullPageCoherencyEnable_start 59 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STENCIL_BUFFER_NullPageCoherencyEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 59; case 120: return 59; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_STENCIL_BUFFER::Render Compression Format */ #define GFX125_3DSTATE_STENCIL_BUFFER_RenderCompressionFormat_bits 5 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STENCIL_BUFFER_RenderCompressionFormat_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_STENCIL_BUFFER_RenderCompressionFormat_start 192 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STENCIL_BUFFER_RenderCompressionFormat_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 192; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_STENCIL_BUFFER::Render Target View Extent */ #define GFX125_3DSTATE_STENCIL_BUFFER_RenderTargetViewExtent_bits 11 #define GFX12_3DSTATE_STENCIL_BUFFER_RenderTargetViewExtent_bits 11 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STENCIL_BUFFER_RenderTargetViewExtent_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 11; case 120: return 11; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_STENCIL_BUFFER_RenderTargetViewExtent_start 245 #define GFX12_3DSTATE_STENCIL_BUFFER_RenderTargetViewExtent_start 245 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STENCIL_BUFFER_RenderTargetViewExtent_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 245; case 120: return 245; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_STENCIL_BUFFER::Stencil Buffer Enable */ #define GFX11_3DSTATE_STENCIL_BUFFER_StencilBufferEnable_bits 1 #define GFX9_3DSTATE_STENCIL_BUFFER_StencilBufferEnable_bits 1 #define GFX8_3DSTATE_STENCIL_BUFFER_StencilBufferEnable_bits 1 #define GFX75_3DSTATE_STENCIL_BUFFER_StencilBufferEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STENCIL_BUFFER_StencilBufferEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX11_3DSTATE_STENCIL_BUFFER_StencilBufferEnable_start 63 #define GFX9_3DSTATE_STENCIL_BUFFER_StencilBufferEnable_start 63 #define GFX8_3DSTATE_STENCIL_BUFFER_StencilBufferEnable_start 63 #define GFX75_3DSTATE_STENCIL_BUFFER_StencilBufferEnable_start 63 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STENCIL_BUFFER_StencilBufferEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 63; case 90: return 63; case 80: return 63; case 75: return 63; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_STENCIL_BUFFER::Stencil Compression Enable */ #define GFX125_3DSTATE_STENCIL_BUFFER_StencilCompressionEnable_bits 1 #define GFX12_3DSTATE_STENCIL_BUFFER_StencilCompressionEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STENCIL_BUFFER_StencilCompressionEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_STENCIL_BUFFER_StencilCompressionEnable_start 57 #define GFX12_3DSTATE_STENCIL_BUFFER_StencilCompressionEnable_start 57 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STENCIL_BUFFER_StencilCompressionEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 57; case 120: return 57; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_STENCIL_BUFFER::Stencil Write Enable */ #define GFX125_3DSTATE_STENCIL_BUFFER_StencilWriteEnable_bits 1 #define GFX12_3DSTATE_STENCIL_BUFFER_StencilWriteEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STENCIL_BUFFER_StencilWriteEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_STENCIL_BUFFER_StencilWriteEnable_start 60 #define GFX12_3DSTATE_STENCIL_BUFFER_StencilWriteEnable_start 60 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STENCIL_BUFFER_StencilWriteEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 60; case 120: return 60; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_STENCIL_BUFFER::Surf LOD */ #define GFX125_3DSTATE_STENCIL_BUFFER_SurfLOD_bits 4 #define GFX12_3DSTATE_STENCIL_BUFFER_SurfLOD_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STENCIL_BUFFER_SurfLOD_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_STENCIL_BUFFER_SurfLOD_start 240 #define GFX12_3DSTATE_STENCIL_BUFFER_SurfLOD_start 240 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STENCIL_BUFFER_SurfLOD_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 240; case 120: return 240; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_STENCIL_BUFFER::Surface Base Address */ #define GFX125_3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_bits 64 #define GFX12_3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_bits 64 #define GFX11_3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_bits 64 #define GFX9_3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_bits 64 #define GFX8_3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_bits 64 #define GFX75_3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_bits 32 #define GFX7_3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_bits 32 #define GFX6_3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_bits 32 #define GFX5_3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_bits 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 64; case 80: return 64; case 75: return 32; case 70: return 32; case 60: return 32; case 50: return 32; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_start 64 #define GFX12_3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_start 64 #define GFX11_3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_start 64 #define GFX9_3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_start 64 #define GFX8_3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_start 64 #define GFX75_3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_start 64 #define GFX7_3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_start 64 #define GFX6_3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_start 64 #define GFX5_3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_start 64 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 64; case 80: return 64; case 75: return 64; case 70: return 64; case 60: return 64; case 50: return 64; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_STENCIL_BUFFER::Surface Pitch */ #define GFX125_3DSTATE_STENCIL_BUFFER_SurfacePitch_bits 17 #define GFX12_3DSTATE_STENCIL_BUFFER_SurfacePitch_bits 17 #define GFX11_3DSTATE_STENCIL_BUFFER_SurfacePitch_bits 17 #define GFX9_3DSTATE_STENCIL_BUFFER_SurfacePitch_bits 17 #define GFX8_3DSTATE_STENCIL_BUFFER_SurfacePitch_bits 17 #define GFX75_3DSTATE_STENCIL_BUFFER_SurfacePitch_bits 17 #define GFX7_3DSTATE_STENCIL_BUFFER_SurfacePitch_bits 17 #define GFX6_3DSTATE_STENCIL_BUFFER_SurfacePitch_bits 17 #define GFX5_3DSTATE_STENCIL_BUFFER_SurfacePitch_bits 17 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STENCIL_BUFFER_SurfacePitch_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 17; case 120: return 17; case 110: return 17; case 90: return 17; case 80: return 17; case 75: return 17; case 70: return 17; case 60: return 17; case 50: return 17; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_STENCIL_BUFFER_SurfacePitch_start 32 #define GFX12_3DSTATE_STENCIL_BUFFER_SurfacePitch_start 32 #define GFX11_3DSTATE_STENCIL_BUFFER_SurfacePitch_start 32 #define GFX9_3DSTATE_STENCIL_BUFFER_SurfacePitch_start 32 #define GFX8_3DSTATE_STENCIL_BUFFER_SurfacePitch_start 32 #define GFX75_3DSTATE_STENCIL_BUFFER_SurfacePitch_start 32 #define GFX7_3DSTATE_STENCIL_BUFFER_SurfacePitch_start 32 #define GFX6_3DSTATE_STENCIL_BUFFER_SurfacePitch_start 32 #define GFX5_3DSTATE_STENCIL_BUFFER_SurfacePitch_start 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STENCIL_BUFFER_SurfacePitch_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 32; case 50: return 32; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_STENCIL_BUFFER::Surface QPitch */ #define GFX125_3DSTATE_STENCIL_BUFFER_SurfaceQPitch_bits 15 #define GFX12_3DSTATE_STENCIL_BUFFER_SurfaceQPitch_bits 15 #define GFX11_3DSTATE_STENCIL_BUFFER_SurfaceQPitch_bits 15 #define GFX9_3DSTATE_STENCIL_BUFFER_SurfaceQPitch_bits 15 #define GFX8_3DSTATE_STENCIL_BUFFER_SurfaceQPitch_bits 15 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STENCIL_BUFFER_SurfaceQPitch_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 15; case 120: return 15; case 110: return 15; case 90: return 15; case 80: return 15; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_STENCIL_BUFFER_SurfaceQPitch_start 224 #define GFX12_3DSTATE_STENCIL_BUFFER_SurfaceQPitch_start 224 #define GFX11_3DSTATE_STENCIL_BUFFER_SurfaceQPitch_start 128 #define GFX9_3DSTATE_STENCIL_BUFFER_SurfaceQPitch_start 128 #define GFX8_3DSTATE_STENCIL_BUFFER_SurfaceQPitch_start 128 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STENCIL_BUFFER_SurfaceQPitch_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 224; case 120: return 224; case 110: return 128; case 90: return 128; case 80: return 128; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_STENCIL_BUFFER::Surface Type */ #define GFX125_3DSTATE_STENCIL_BUFFER_SurfaceType_bits 3 #define GFX12_3DSTATE_STENCIL_BUFFER_SurfaceType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STENCIL_BUFFER_SurfaceType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_STENCIL_BUFFER_SurfaceType_start 61 #define GFX12_3DSTATE_STENCIL_BUFFER_SurfaceType_start 61 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STENCIL_BUFFER_SurfaceType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 61; case 120: return 61; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_STENCIL_BUFFER::Tiled Mode */ #define GFX125_3DSTATE_STENCIL_BUFFER_TiledMode_bits 2 #define GFX12_3DSTATE_STENCIL_BUFFER_TiledMode_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STENCIL_BUFFER_TiledMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_STENCIL_BUFFER_TiledMode_start 222 #define GFX12_3DSTATE_STENCIL_BUFFER_TiledMode_start 222 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STENCIL_BUFFER_TiledMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 222; case 120: return 222; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_STENCIL_BUFFER::Width */ #define GFX125_3DSTATE_STENCIL_BUFFER_Width_bits 14 #define GFX12_3DSTATE_STENCIL_BUFFER_Width_bits 14 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STENCIL_BUFFER_Width_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 14; case 120: return 14; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_STENCIL_BUFFER_Width_start 129 #define GFX12_3DSTATE_STENCIL_BUFFER_Width_start 129 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STENCIL_BUFFER_Width_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 129; case 120: return 129; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_STREAMOUT */ #define GFX125_3DSTATE_STREAMOUT_length 5 #define GFX12_3DSTATE_STREAMOUT_length 5 #define GFX11_3DSTATE_STREAMOUT_length 5 #define GFX9_3DSTATE_STREAMOUT_length 5 #define GFX8_3DSTATE_STREAMOUT_length 5 #define GFX75_3DSTATE_STREAMOUT_length 3 #define GFX7_3DSTATE_STREAMOUT_length 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STREAMOUT_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 5; case 110: return 5; case 90: return 5; case 80: return 5; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_STREAMOUT::3D Command Opcode */ #define GFX125_3DSTATE_STREAMOUT_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_STREAMOUT_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_STREAMOUT_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_STREAMOUT_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_STREAMOUT_3DCommandOpcode_bits 3 #define GFX75_3DSTATE_STREAMOUT_3DCommandOpcode_bits 3 #define GFX7_3DSTATE_STREAMOUT_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STREAMOUT_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_STREAMOUT_3DCommandOpcode_start 24 #define GFX12_3DSTATE_STREAMOUT_3DCommandOpcode_start 24 #define GFX11_3DSTATE_STREAMOUT_3DCommandOpcode_start 24 #define GFX9_3DSTATE_STREAMOUT_3DCommandOpcode_start 24 #define GFX8_3DSTATE_STREAMOUT_3DCommandOpcode_start 24 #define GFX75_3DSTATE_STREAMOUT_3DCommandOpcode_start 24 #define GFX7_3DSTATE_STREAMOUT_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STREAMOUT_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_STREAMOUT::3D Command Sub Opcode */ #define GFX125_3DSTATE_STREAMOUT_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_STREAMOUT_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_STREAMOUT_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_STREAMOUT_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_STREAMOUT_3DCommandSubOpcode_bits 8 #define GFX75_3DSTATE_STREAMOUT_3DCommandSubOpcode_bits 8 #define GFX7_3DSTATE_STREAMOUT_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STREAMOUT_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_STREAMOUT_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_STREAMOUT_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_STREAMOUT_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_STREAMOUT_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_STREAMOUT_3DCommandSubOpcode_start 16 #define GFX75_3DSTATE_STREAMOUT_3DCommandSubOpcode_start 16 #define GFX7_3DSTATE_STREAMOUT_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STREAMOUT_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_STREAMOUT::Buffer 0 Surface Pitch */ #define GFX125_3DSTATE_STREAMOUT_Buffer0SurfacePitch_bits 12 #define GFX12_3DSTATE_STREAMOUT_Buffer0SurfacePitch_bits 12 #define GFX11_3DSTATE_STREAMOUT_Buffer0SurfacePitch_bits 12 #define GFX9_3DSTATE_STREAMOUT_Buffer0SurfacePitch_bits 12 #define GFX8_3DSTATE_STREAMOUT_Buffer0SurfacePitch_bits 12 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STREAMOUT_Buffer0SurfacePitch_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 12; case 120: return 12; case 110: return 12; case 90: return 12; case 80: return 12; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_STREAMOUT_Buffer0SurfacePitch_start 96 #define GFX12_3DSTATE_STREAMOUT_Buffer0SurfacePitch_start 96 #define GFX11_3DSTATE_STREAMOUT_Buffer0SurfacePitch_start 96 #define GFX9_3DSTATE_STREAMOUT_Buffer0SurfacePitch_start 96 #define GFX8_3DSTATE_STREAMOUT_Buffer0SurfacePitch_start 96 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STREAMOUT_Buffer0SurfacePitch_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 96; case 120: return 96; case 110: return 96; case 90: return 96; case 80: return 96; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_STREAMOUT::Buffer 1 Surface Pitch */ #define GFX125_3DSTATE_STREAMOUT_Buffer1SurfacePitch_bits 12 #define GFX12_3DSTATE_STREAMOUT_Buffer1SurfacePitch_bits 12 #define GFX11_3DSTATE_STREAMOUT_Buffer1SurfacePitch_bits 12 #define GFX9_3DSTATE_STREAMOUT_Buffer1SurfacePitch_bits 12 #define GFX8_3DSTATE_STREAMOUT_Buffer1SurfacePitch_bits 12 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STREAMOUT_Buffer1SurfacePitch_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 12; case 120: return 12; case 110: return 12; case 90: return 12; case 80: return 12; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_STREAMOUT_Buffer1SurfacePitch_start 112 #define GFX12_3DSTATE_STREAMOUT_Buffer1SurfacePitch_start 112 #define GFX11_3DSTATE_STREAMOUT_Buffer1SurfacePitch_start 112 #define GFX9_3DSTATE_STREAMOUT_Buffer1SurfacePitch_start 112 #define GFX8_3DSTATE_STREAMOUT_Buffer1SurfacePitch_start 112 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STREAMOUT_Buffer1SurfacePitch_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 112; case 120: return 112; case 110: return 112; case 90: return 112; case 80: return 112; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_STREAMOUT::Buffer 2 Surface Pitch */ #define GFX125_3DSTATE_STREAMOUT_Buffer2SurfacePitch_bits 12 #define GFX12_3DSTATE_STREAMOUT_Buffer2SurfacePitch_bits 12 #define GFX11_3DSTATE_STREAMOUT_Buffer2SurfacePitch_bits 12 #define GFX9_3DSTATE_STREAMOUT_Buffer2SurfacePitch_bits 12 #define GFX8_3DSTATE_STREAMOUT_Buffer2SurfacePitch_bits 12 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STREAMOUT_Buffer2SurfacePitch_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 12; case 120: return 12; case 110: return 12; case 90: return 12; case 80: return 12; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_STREAMOUT_Buffer2SurfacePitch_start 128 #define GFX12_3DSTATE_STREAMOUT_Buffer2SurfacePitch_start 128 #define GFX11_3DSTATE_STREAMOUT_Buffer2SurfacePitch_start 128 #define GFX9_3DSTATE_STREAMOUT_Buffer2SurfacePitch_start 128 #define GFX8_3DSTATE_STREAMOUT_Buffer2SurfacePitch_start 128 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STREAMOUT_Buffer2SurfacePitch_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 128; case 120: return 128; case 110: return 128; case 90: return 128; case 80: return 128; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_STREAMOUT::Buffer 3 Surface Pitch */ #define GFX125_3DSTATE_STREAMOUT_Buffer3SurfacePitch_bits 12 #define GFX12_3DSTATE_STREAMOUT_Buffer3SurfacePitch_bits 12 #define GFX11_3DSTATE_STREAMOUT_Buffer3SurfacePitch_bits 12 #define GFX9_3DSTATE_STREAMOUT_Buffer3SurfacePitch_bits 12 #define GFX8_3DSTATE_STREAMOUT_Buffer3SurfacePitch_bits 12 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STREAMOUT_Buffer3SurfacePitch_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 12; case 120: return 12; case 110: return 12; case 90: return 12; case 80: return 12; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_STREAMOUT_Buffer3SurfacePitch_start 144 #define GFX12_3DSTATE_STREAMOUT_Buffer3SurfacePitch_start 144 #define GFX11_3DSTATE_STREAMOUT_Buffer3SurfacePitch_start 144 #define GFX9_3DSTATE_STREAMOUT_Buffer3SurfacePitch_start 144 #define GFX8_3DSTATE_STREAMOUT_Buffer3SurfacePitch_start 144 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STREAMOUT_Buffer3SurfacePitch_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 144; case 120: return 144; case 110: return 144; case 90: return 144; case 80: return 144; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_STREAMOUT::Command SubType */ #define GFX125_3DSTATE_STREAMOUT_CommandSubType_bits 2 #define GFX12_3DSTATE_STREAMOUT_CommandSubType_bits 2 #define GFX11_3DSTATE_STREAMOUT_CommandSubType_bits 2 #define GFX9_3DSTATE_STREAMOUT_CommandSubType_bits 2 #define GFX8_3DSTATE_STREAMOUT_CommandSubType_bits 2 #define GFX75_3DSTATE_STREAMOUT_CommandSubType_bits 2 #define GFX7_3DSTATE_STREAMOUT_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STREAMOUT_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_STREAMOUT_CommandSubType_start 27 #define GFX12_3DSTATE_STREAMOUT_CommandSubType_start 27 #define GFX11_3DSTATE_STREAMOUT_CommandSubType_start 27 #define GFX9_3DSTATE_STREAMOUT_CommandSubType_start 27 #define GFX8_3DSTATE_STREAMOUT_CommandSubType_start 27 #define GFX75_3DSTATE_STREAMOUT_CommandSubType_start 27 #define GFX7_3DSTATE_STREAMOUT_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STREAMOUT_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_STREAMOUT::Command Type */ #define GFX125_3DSTATE_STREAMOUT_CommandType_bits 3 #define GFX12_3DSTATE_STREAMOUT_CommandType_bits 3 #define GFX11_3DSTATE_STREAMOUT_CommandType_bits 3 #define GFX9_3DSTATE_STREAMOUT_CommandType_bits 3 #define GFX8_3DSTATE_STREAMOUT_CommandType_bits 3 #define GFX75_3DSTATE_STREAMOUT_CommandType_bits 3 #define GFX7_3DSTATE_STREAMOUT_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STREAMOUT_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_STREAMOUT_CommandType_start 29 #define GFX12_3DSTATE_STREAMOUT_CommandType_start 29 #define GFX11_3DSTATE_STREAMOUT_CommandType_start 29 #define GFX9_3DSTATE_STREAMOUT_CommandType_start 29 #define GFX8_3DSTATE_STREAMOUT_CommandType_start 29 #define GFX75_3DSTATE_STREAMOUT_CommandType_start 29 #define GFX7_3DSTATE_STREAMOUT_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STREAMOUT_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_STREAMOUT::DWord Length */ #define GFX125_3DSTATE_STREAMOUT_DWordLength_bits 8 #define GFX12_3DSTATE_STREAMOUT_DWordLength_bits 8 #define GFX11_3DSTATE_STREAMOUT_DWordLength_bits 8 #define GFX9_3DSTATE_STREAMOUT_DWordLength_bits 8 #define GFX8_3DSTATE_STREAMOUT_DWordLength_bits 8 #define GFX75_3DSTATE_STREAMOUT_DWordLength_bits 8 #define GFX7_3DSTATE_STREAMOUT_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STREAMOUT_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_STREAMOUT_DWordLength_start 0 #define GFX12_3DSTATE_STREAMOUT_DWordLength_start 0 #define GFX11_3DSTATE_STREAMOUT_DWordLength_start 0 #define GFX9_3DSTATE_STREAMOUT_DWordLength_start 0 #define GFX8_3DSTATE_STREAMOUT_DWordLength_start 0 #define GFX75_3DSTATE_STREAMOUT_DWordLength_start 0 #define GFX7_3DSTATE_STREAMOUT_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STREAMOUT_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_STREAMOUT::Force Rendering */ #define GFX125_3DSTATE_STREAMOUT_ForceRendering_bits 2 #define GFX12_3DSTATE_STREAMOUT_ForceRendering_bits 2 #define GFX11_3DSTATE_STREAMOUT_ForceRendering_bits 2 #define GFX9_3DSTATE_STREAMOUT_ForceRendering_bits 2 #define GFX8_3DSTATE_STREAMOUT_ForceRendering_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STREAMOUT_ForceRendering_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_STREAMOUT_ForceRendering_start 55 #define GFX12_3DSTATE_STREAMOUT_ForceRendering_start 55 #define GFX11_3DSTATE_STREAMOUT_ForceRendering_start 55 #define GFX9_3DSTATE_STREAMOUT_ForceRendering_start 55 #define GFX8_3DSTATE_STREAMOUT_ForceRendering_start 55 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STREAMOUT_ForceRendering_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 55; case 120: return 55; case 110: return 55; case 90: return 55; case 80: return 55; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_STREAMOUT::Render Stream Select */ #define GFX125_3DSTATE_STREAMOUT_RenderStreamSelect_bits 2 #define GFX12_3DSTATE_STREAMOUT_RenderStreamSelect_bits 2 #define GFX11_3DSTATE_STREAMOUT_RenderStreamSelect_bits 2 #define GFX9_3DSTATE_STREAMOUT_RenderStreamSelect_bits 2 #define GFX8_3DSTATE_STREAMOUT_RenderStreamSelect_bits 2 #define GFX75_3DSTATE_STREAMOUT_RenderStreamSelect_bits 2 #define GFX7_3DSTATE_STREAMOUT_RenderStreamSelect_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STREAMOUT_RenderStreamSelect_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_STREAMOUT_RenderStreamSelect_start 59 #define GFX12_3DSTATE_STREAMOUT_RenderStreamSelect_start 59 #define GFX11_3DSTATE_STREAMOUT_RenderStreamSelect_start 59 #define GFX9_3DSTATE_STREAMOUT_RenderStreamSelect_start 59 #define GFX8_3DSTATE_STREAMOUT_RenderStreamSelect_start 59 #define GFX75_3DSTATE_STREAMOUT_RenderStreamSelect_start 59 #define GFX7_3DSTATE_STREAMOUT_RenderStreamSelect_start 59 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STREAMOUT_RenderStreamSelect_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 59; case 120: return 59; case 110: return 59; case 90: return 59; case 80: return 59; case 75: return 59; case 70: return 59; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_STREAMOUT::Rendering Disable */ #define GFX125_3DSTATE_STREAMOUT_RenderingDisable_bits 1 #define GFX12_3DSTATE_STREAMOUT_RenderingDisable_bits 1 #define GFX11_3DSTATE_STREAMOUT_RenderingDisable_bits 1 #define GFX9_3DSTATE_STREAMOUT_RenderingDisable_bits 1 #define GFX8_3DSTATE_STREAMOUT_RenderingDisable_bits 1 #define GFX75_3DSTATE_STREAMOUT_RenderingDisable_bits 1 #define GFX7_3DSTATE_STREAMOUT_RenderingDisable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STREAMOUT_RenderingDisable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_STREAMOUT_RenderingDisable_start 62 #define GFX12_3DSTATE_STREAMOUT_RenderingDisable_start 62 #define GFX11_3DSTATE_STREAMOUT_RenderingDisable_start 62 #define GFX9_3DSTATE_STREAMOUT_RenderingDisable_start 62 #define GFX8_3DSTATE_STREAMOUT_RenderingDisable_start 62 #define GFX75_3DSTATE_STREAMOUT_RenderingDisable_start 62 #define GFX7_3DSTATE_STREAMOUT_RenderingDisable_start 62 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STREAMOUT_RenderingDisable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 62; case 120: return 62; case 110: return 62; case 90: return 62; case 80: return 62; case 75: return 62; case 70: return 62; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_STREAMOUT::Reorder Mode */ #define GFX125_3DSTATE_STREAMOUT_ReorderMode_bits 1 #define GFX12_3DSTATE_STREAMOUT_ReorderMode_bits 1 #define GFX11_3DSTATE_STREAMOUT_ReorderMode_bits 1 #define GFX9_3DSTATE_STREAMOUT_ReorderMode_bits 1 #define GFX8_3DSTATE_STREAMOUT_ReorderMode_bits 1 #define GFX75_3DSTATE_STREAMOUT_ReorderMode_bits 1 #define GFX7_3DSTATE_STREAMOUT_ReorderMode_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STREAMOUT_ReorderMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_STREAMOUT_ReorderMode_start 58 #define GFX12_3DSTATE_STREAMOUT_ReorderMode_start 58 #define GFX11_3DSTATE_STREAMOUT_ReorderMode_start 58 #define GFX9_3DSTATE_STREAMOUT_ReorderMode_start 58 #define GFX8_3DSTATE_STREAMOUT_ReorderMode_start 58 #define GFX75_3DSTATE_STREAMOUT_ReorderMode_start 58 #define GFX7_3DSTATE_STREAMOUT_ReorderMode_start 58 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STREAMOUT_ReorderMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 58; case 120: return 58; case 110: return 58; case 90: return 58; case 80: return 58; case 75: return 58; case 70: return 58; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_STREAMOUT::SO Buffer Enable [0] */ #define GFX75_3DSTATE_STREAMOUT_SOBufferEnable0_bits 1 #define GFX7_3DSTATE_STREAMOUT_SOBufferEnable0_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STREAMOUT_SOBufferEnable0_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_STREAMOUT_SOBufferEnable0_start 40 #define GFX7_3DSTATE_STREAMOUT_SOBufferEnable0_start 40 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STREAMOUT_SOBufferEnable0_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 40; case 70: return 40; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_STREAMOUT::SO Buffer Enable [1] */ #define GFX75_3DSTATE_STREAMOUT_SOBufferEnable1_bits 1 #define GFX7_3DSTATE_STREAMOUT_SOBufferEnable1_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STREAMOUT_SOBufferEnable1_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_STREAMOUT_SOBufferEnable1_start 41 #define GFX7_3DSTATE_STREAMOUT_SOBufferEnable1_start 41 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STREAMOUT_SOBufferEnable1_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 41; case 70: return 41; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_STREAMOUT::SO Buffer Enable [2] */ #define GFX75_3DSTATE_STREAMOUT_SOBufferEnable2_bits 1 #define GFX7_3DSTATE_STREAMOUT_SOBufferEnable2_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STREAMOUT_SOBufferEnable2_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_STREAMOUT_SOBufferEnable2_start 42 #define GFX7_3DSTATE_STREAMOUT_SOBufferEnable2_start 42 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STREAMOUT_SOBufferEnable2_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 42; case 70: return 42; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_STREAMOUT::SO Buffer Enable [3] */ #define GFX75_3DSTATE_STREAMOUT_SOBufferEnable3_bits 1 #define GFX7_3DSTATE_STREAMOUT_SOBufferEnable3_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STREAMOUT_SOBufferEnable3_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_STREAMOUT_SOBufferEnable3_start 43 #define GFX7_3DSTATE_STREAMOUT_SOBufferEnable3_start 43 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STREAMOUT_SOBufferEnable3_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 43; case 70: return 43; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_STREAMOUT::SO Function Enable */ #define GFX125_3DSTATE_STREAMOUT_SOFunctionEnable_bits 1 #define GFX12_3DSTATE_STREAMOUT_SOFunctionEnable_bits 1 #define GFX11_3DSTATE_STREAMOUT_SOFunctionEnable_bits 1 #define GFX9_3DSTATE_STREAMOUT_SOFunctionEnable_bits 1 #define GFX8_3DSTATE_STREAMOUT_SOFunctionEnable_bits 1 #define GFX75_3DSTATE_STREAMOUT_SOFunctionEnable_bits 1 #define GFX7_3DSTATE_STREAMOUT_SOFunctionEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STREAMOUT_SOFunctionEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_STREAMOUT_SOFunctionEnable_start 63 #define GFX12_3DSTATE_STREAMOUT_SOFunctionEnable_start 63 #define GFX11_3DSTATE_STREAMOUT_SOFunctionEnable_start 63 #define GFX9_3DSTATE_STREAMOUT_SOFunctionEnable_start 63 #define GFX8_3DSTATE_STREAMOUT_SOFunctionEnable_start 63 #define GFX75_3DSTATE_STREAMOUT_SOFunctionEnable_start 63 #define GFX7_3DSTATE_STREAMOUT_SOFunctionEnable_start 63 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STREAMOUT_SOFunctionEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 63; case 120: return 63; case 110: return 63; case 90: return 63; case 80: return 63; case 75: return 63; case 70: return 63; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_STREAMOUT::SO Statistics Enable */ #define GFX125_3DSTATE_STREAMOUT_SOStatisticsEnable_bits 1 #define GFX12_3DSTATE_STREAMOUT_SOStatisticsEnable_bits 1 #define GFX11_3DSTATE_STREAMOUT_SOStatisticsEnable_bits 1 #define GFX9_3DSTATE_STREAMOUT_SOStatisticsEnable_bits 1 #define GFX8_3DSTATE_STREAMOUT_SOStatisticsEnable_bits 1 #define GFX75_3DSTATE_STREAMOUT_SOStatisticsEnable_bits 1 #define GFX7_3DSTATE_STREAMOUT_SOStatisticsEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STREAMOUT_SOStatisticsEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_STREAMOUT_SOStatisticsEnable_start 57 #define GFX12_3DSTATE_STREAMOUT_SOStatisticsEnable_start 57 #define GFX11_3DSTATE_STREAMOUT_SOStatisticsEnable_start 57 #define GFX9_3DSTATE_STREAMOUT_SOStatisticsEnable_start 57 #define GFX8_3DSTATE_STREAMOUT_SOStatisticsEnable_start 57 #define GFX75_3DSTATE_STREAMOUT_SOStatisticsEnable_start 57 #define GFX7_3DSTATE_STREAMOUT_SOStatisticsEnable_start 57 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STREAMOUT_SOStatisticsEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 57; case 120: return 57; case 110: return 57; case 90: return 57; case 80: return 57; case 75: return 57; case 70: return 57; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_STREAMOUT::Stream 0 Vertex Read Length */ #define GFX125_3DSTATE_STREAMOUT_Stream0VertexReadLength_bits 5 #define GFX12_3DSTATE_STREAMOUT_Stream0VertexReadLength_bits 5 #define GFX11_3DSTATE_STREAMOUT_Stream0VertexReadLength_bits 5 #define GFX9_3DSTATE_STREAMOUT_Stream0VertexReadLength_bits 5 #define GFX8_3DSTATE_STREAMOUT_Stream0VertexReadLength_bits 5 #define GFX75_3DSTATE_STREAMOUT_Stream0VertexReadLength_bits 5 #define GFX7_3DSTATE_STREAMOUT_Stream0VertexReadLength_bits 5 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STREAMOUT_Stream0VertexReadLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 5; case 110: return 5; case 90: return 5; case 80: return 5; case 75: return 5; case 70: return 5; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_STREAMOUT_Stream0VertexReadLength_start 64 #define GFX12_3DSTATE_STREAMOUT_Stream0VertexReadLength_start 64 #define GFX11_3DSTATE_STREAMOUT_Stream0VertexReadLength_start 64 #define GFX9_3DSTATE_STREAMOUT_Stream0VertexReadLength_start 64 #define GFX8_3DSTATE_STREAMOUT_Stream0VertexReadLength_start 64 #define GFX75_3DSTATE_STREAMOUT_Stream0VertexReadLength_start 64 #define GFX7_3DSTATE_STREAMOUT_Stream0VertexReadLength_start 64 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STREAMOUT_Stream0VertexReadLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 64; case 80: return 64; case 75: return 64; case 70: return 64; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_STREAMOUT::Stream 0 Vertex Read Offset */ #define GFX125_3DSTATE_STREAMOUT_Stream0VertexReadOffset_bits 1 #define GFX12_3DSTATE_STREAMOUT_Stream0VertexReadOffset_bits 1 #define GFX11_3DSTATE_STREAMOUT_Stream0VertexReadOffset_bits 1 #define GFX9_3DSTATE_STREAMOUT_Stream0VertexReadOffset_bits 1 #define GFX8_3DSTATE_STREAMOUT_Stream0VertexReadOffset_bits 1 #define GFX75_3DSTATE_STREAMOUT_Stream0VertexReadOffset_bits 1 #define GFX7_3DSTATE_STREAMOUT_Stream0VertexReadOffset_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STREAMOUT_Stream0VertexReadOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_STREAMOUT_Stream0VertexReadOffset_start 69 #define GFX12_3DSTATE_STREAMOUT_Stream0VertexReadOffset_start 69 #define GFX11_3DSTATE_STREAMOUT_Stream0VertexReadOffset_start 69 #define GFX9_3DSTATE_STREAMOUT_Stream0VertexReadOffset_start 69 #define GFX8_3DSTATE_STREAMOUT_Stream0VertexReadOffset_start 69 #define GFX75_3DSTATE_STREAMOUT_Stream0VertexReadOffset_start 69 #define GFX7_3DSTATE_STREAMOUT_Stream0VertexReadOffset_start 69 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STREAMOUT_Stream0VertexReadOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 69; case 120: return 69; case 110: return 69; case 90: return 69; case 80: return 69; case 75: return 69; case 70: return 69; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_STREAMOUT::Stream 1 Vertex Read Length */ #define GFX125_3DSTATE_STREAMOUT_Stream1VertexReadLength_bits 5 #define GFX12_3DSTATE_STREAMOUT_Stream1VertexReadLength_bits 5 #define GFX11_3DSTATE_STREAMOUT_Stream1VertexReadLength_bits 5 #define GFX9_3DSTATE_STREAMOUT_Stream1VertexReadLength_bits 5 #define GFX8_3DSTATE_STREAMOUT_Stream1VertexReadLength_bits 5 #define GFX75_3DSTATE_STREAMOUT_Stream1VertexReadLength_bits 5 #define GFX7_3DSTATE_STREAMOUT_Stream1VertexReadLength_bits 5 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STREAMOUT_Stream1VertexReadLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 5; case 110: return 5; case 90: return 5; case 80: return 5; case 75: return 5; case 70: return 5; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_STREAMOUT_Stream1VertexReadLength_start 72 #define GFX12_3DSTATE_STREAMOUT_Stream1VertexReadLength_start 72 #define GFX11_3DSTATE_STREAMOUT_Stream1VertexReadLength_start 72 #define GFX9_3DSTATE_STREAMOUT_Stream1VertexReadLength_start 72 #define GFX8_3DSTATE_STREAMOUT_Stream1VertexReadLength_start 72 #define GFX75_3DSTATE_STREAMOUT_Stream1VertexReadLength_start 72 #define GFX7_3DSTATE_STREAMOUT_Stream1VertexReadLength_start 72 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STREAMOUT_Stream1VertexReadLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 72; case 120: return 72; case 110: return 72; case 90: return 72; case 80: return 72; case 75: return 72; case 70: return 72; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_STREAMOUT::Stream 1 Vertex Read Offset */ #define GFX125_3DSTATE_STREAMOUT_Stream1VertexReadOffset_bits 1 #define GFX12_3DSTATE_STREAMOUT_Stream1VertexReadOffset_bits 1 #define GFX11_3DSTATE_STREAMOUT_Stream1VertexReadOffset_bits 1 #define GFX9_3DSTATE_STREAMOUT_Stream1VertexReadOffset_bits 1 #define GFX8_3DSTATE_STREAMOUT_Stream1VertexReadOffset_bits 1 #define GFX75_3DSTATE_STREAMOUT_Stream1VertexReadOffset_bits 1 #define GFX7_3DSTATE_STREAMOUT_Stream1VertexReadOffset_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STREAMOUT_Stream1VertexReadOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_STREAMOUT_Stream1VertexReadOffset_start 77 #define GFX12_3DSTATE_STREAMOUT_Stream1VertexReadOffset_start 77 #define GFX11_3DSTATE_STREAMOUT_Stream1VertexReadOffset_start 77 #define GFX9_3DSTATE_STREAMOUT_Stream1VertexReadOffset_start 77 #define GFX8_3DSTATE_STREAMOUT_Stream1VertexReadOffset_start 77 #define GFX75_3DSTATE_STREAMOUT_Stream1VertexReadOffset_start 77 #define GFX7_3DSTATE_STREAMOUT_Stream1VertexReadOffset_start 77 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STREAMOUT_Stream1VertexReadOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 77; case 120: return 77; case 110: return 77; case 90: return 77; case 80: return 77; case 75: return 77; case 70: return 77; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_STREAMOUT::Stream 2 Vertex Read Length */ #define GFX125_3DSTATE_STREAMOUT_Stream2VertexReadLength_bits 5 #define GFX12_3DSTATE_STREAMOUT_Stream2VertexReadLength_bits 5 #define GFX11_3DSTATE_STREAMOUT_Stream2VertexReadLength_bits 5 #define GFX9_3DSTATE_STREAMOUT_Stream2VertexReadLength_bits 5 #define GFX8_3DSTATE_STREAMOUT_Stream2VertexReadLength_bits 5 #define GFX75_3DSTATE_STREAMOUT_Stream2VertexReadLength_bits 5 #define GFX7_3DSTATE_STREAMOUT_Stream2VertexReadLength_bits 5 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STREAMOUT_Stream2VertexReadLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 5; case 110: return 5; case 90: return 5; case 80: return 5; case 75: return 5; case 70: return 5; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_STREAMOUT_Stream2VertexReadLength_start 80 #define GFX12_3DSTATE_STREAMOUT_Stream2VertexReadLength_start 80 #define GFX11_3DSTATE_STREAMOUT_Stream2VertexReadLength_start 80 #define GFX9_3DSTATE_STREAMOUT_Stream2VertexReadLength_start 80 #define GFX8_3DSTATE_STREAMOUT_Stream2VertexReadLength_start 80 #define GFX75_3DSTATE_STREAMOUT_Stream2VertexReadLength_start 80 #define GFX7_3DSTATE_STREAMOUT_Stream2VertexReadLength_start 80 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STREAMOUT_Stream2VertexReadLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 80; case 120: return 80; case 110: return 80; case 90: return 80; case 80: return 80; case 75: return 80; case 70: return 80; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_STREAMOUT::Stream 2 Vertex Read Offset */ #define GFX125_3DSTATE_STREAMOUT_Stream2VertexReadOffset_bits 1 #define GFX12_3DSTATE_STREAMOUT_Stream2VertexReadOffset_bits 1 #define GFX11_3DSTATE_STREAMOUT_Stream2VertexReadOffset_bits 1 #define GFX9_3DSTATE_STREAMOUT_Stream2VertexReadOffset_bits 1 #define GFX8_3DSTATE_STREAMOUT_Stream2VertexReadOffset_bits 1 #define GFX75_3DSTATE_STREAMOUT_Stream2VertexReadOffset_bits 1 #define GFX7_3DSTATE_STREAMOUT_Stream2VertexReadOffset_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STREAMOUT_Stream2VertexReadOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_STREAMOUT_Stream2VertexReadOffset_start 85 #define GFX12_3DSTATE_STREAMOUT_Stream2VertexReadOffset_start 85 #define GFX11_3DSTATE_STREAMOUT_Stream2VertexReadOffset_start 85 #define GFX9_3DSTATE_STREAMOUT_Stream2VertexReadOffset_start 85 #define GFX8_3DSTATE_STREAMOUT_Stream2VertexReadOffset_start 85 #define GFX75_3DSTATE_STREAMOUT_Stream2VertexReadOffset_start 85 #define GFX7_3DSTATE_STREAMOUT_Stream2VertexReadOffset_start 85 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STREAMOUT_Stream2VertexReadOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 85; case 120: return 85; case 110: return 85; case 90: return 85; case 80: return 85; case 75: return 85; case 70: return 85; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_STREAMOUT::Stream 3 Vertex Read Length */ #define GFX125_3DSTATE_STREAMOUT_Stream3VertexReadLength_bits 5 #define GFX12_3DSTATE_STREAMOUT_Stream3VertexReadLength_bits 5 #define GFX11_3DSTATE_STREAMOUT_Stream3VertexReadLength_bits 5 #define GFX9_3DSTATE_STREAMOUT_Stream3VertexReadLength_bits 5 #define GFX8_3DSTATE_STREAMOUT_Stream3VertexReadLength_bits 5 #define GFX75_3DSTATE_STREAMOUT_Stream3VertexReadLength_bits 5 #define GFX7_3DSTATE_STREAMOUT_Stream3VertexReadLength_bits 5 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STREAMOUT_Stream3VertexReadLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 5; case 110: return 5; case 90: return 5; case 80: return 5; case 75: return 5; case 70: return 5; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_STREAMOUT_Stream3VertexReadLength_start 88 #define GFX12_3DSTATE_STREAMOUT_Stream3VertexReadLength_start 88 #define GFX11_3DSTATE_STREAMOUT_Stream3VertexReadLength_start 88 #define GFX9_3DSTATE_STREAMOUT_Stream3VertexReadLength_start 88 #define GFX8_3DSTATE_STREAMOUT_Stream3VertexReadLength_start 88 #define GFX75_3DSTATE_STREAMOUT_Stream3VertexReadLength_start 88 #define GFX7_3DSTATE_STREAMOUT_Stream3VertexReadLength_start 88 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STREAMOUT_Stream3VertexReadLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 88; case 120: return 88; case 110: return 88; case 90: return 88; case 80: return 88; case 75: return 88; case 70: return 88; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_STREAMOUT::Stream 3 Vertex Read Offset */ #define GFX125_3DSTATE_STREAMOUT_Stream3VertexReadOffset_bits 1 #define GFX12_3DSTATE_STREAMOUT_Stream3VertexReadOffset_bits 1 #define GFX11_3DSTATE_STREAMOUT_Stream3VertexReadOffset_bits 1 #define GFX9_3DSTATE_STREAMOUT_Stream3VertexReadOffset_bits 1 #define GFX8_3DSTATE_STREAMOUT_Stream3VertexReadOffset_bits 1 #define GFX75_3DSTATE_STREAMOUT_Stream3VertexReadOffset_bits 1 #define GFX7_3DSTATE_STREAMOUT_Stream3VertexReadOffset_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STREAMOUT_Stream3VertexReadOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_STREAMOUT_Stream3VertexReadOffset_start 93 #define GFX12_3DSTATE_STREAMOUT_Stream3VertexReadOffset_start 93 #define GFX11_3DSTATE_STREAMOUT_Stream3VertexReadOffset_start 93 #define GFX9_3DSTATE_STREAMOUT_Stream3VertexReadOffset_start 93 #define GFX8_3DSTATE_STREAMOUT_Stream3VertexReadOffset_start 93 #define GFX75_3DSTATE_STREAMOUT_Stream3VertexReadOffset_start 93 #define GFX7_3DSTATE_STREAMOUT_Stream3VertexReadOffset_start 93 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_STREAMOUT_Stream3VertexReadOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 93; case 120: return 93; case 110: return 93; case 90: return 93; case 80: return 93; case 75: return 93; case 70: return 93; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SUBSLICE_HASH_TABLE */ #define GFX125_3DSTATE_SUBSLICE_HASH_TABLE_length 14 #define GFX12_3DSTATE_SUBSLICE_HASH_TABLE_length 14 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SUBSLICE_HASH_TABLE_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 14; case 120: return 14; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SUBSLICE_HASH_TABLE::3D Command Opcode */ #define GFX125_3DSTATE_SUBSLICE_HASH_TABLE_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_SUBSLICE_HASH_TABLE_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SUBSLICE_HASH_TABLE_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SUBSLICE_HASH_TABLE_3DCommandOpcode_start 24 #define GFX12_3DSTATE_SUBSLICE_HASH_TABLE_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SUBSLICE_HASH_TABLE_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SUBSLICE_HASH_TABLE::3D Command Sub Opcode */ #define GFX125_3DSTATE_SUBSLICE_HASH_TABLE_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_SUBSLICE_HASH_TABLE_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SUBSLICE_HASH_TABLE_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SUBSLICE_HASH_TABLE_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_SUBSLICE_HASH_TABLE_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SUBSLICE_HASH_TABLE_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SUBSLICE_HASH_TABLE::Command SubType */ #define GFX125_3DSTATE_SUBSLICE_HASH_TABLE_CommandSubType_bits 2 #define GFX12_3DSTATE_SUBSLICE_HASH_TABLE_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SUBSLICE_HASH_TABLE_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SUBSLICE_HASH_TABLE_CommandSubType_start 27 #define GFX12_3DSTATE_SUBSLICE_HASH_TABLE_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SUBSLICE_HASH_TABLE_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SUBSLICE_HASH_TABLE::Command Type */ #define GFX125_3DSTATE_SUBSLICE_HASH_TABLE_CommandType_bits 3 #define GFX12_3DSTATE_SUBSLICE_HASH_TABLE_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SUBSLICE_HASH_TABLE_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SUBSLICE_HASH_TABLE_CommandType_start 29 #define GFX12_3DSTATE_SUBSLICE_HASH_TABLE_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SUBSLICE_HASH_TABLE_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SUBSLICE_HASH_TABLE::DWord Length */ #define GFX125_3DSTATE_SUBSLICE_HASH_TABLE_DWordLength_bits 8 #define GFX12_3DSTATE_SUBSLICE_HASH_TABLE_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SUBSLICE_HASH_TABLE_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SUBSLICE_HASH_TABLE_DWordLength_start 0 #define GFX12_3DSTATE_SUBSLICE_HASH_TABLE_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SUBSLICE_HASH_TABLE_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_SUBSLICE_HASH_TABLE::Slice Table Mode */ #define GFX125_3DSTATE_SUBSLICE_HASH_TABLE_SliceTableMode_bits 2 #define GFX12_3DSTATE_SUBSLICE_HASH_TABLE_SliceTableMode_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SUBSLICE_HASH_TABLE_SliceTableMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_SUBSLICE_HASH_TABLE_SliceTableMode_start 62 #define GFX12_3DSTATE_SUBSLICE_HASH_TABLE_SliceTableMode_start 62 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_SUBSLICE_HASH_TABLE_SliceTableMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 62; case 120: return 62; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_TE */ #define GFX125_3DSTATE_TE_length 4 #define GFX12_3DSTATE_TE_length 4 #define GFX11_3DSTATE_TE_length 4 #define GFX9_3DSTATE_TE_length 4 #define GFX8_3DSTATE_TE_length 4 #define GFX75_3DSTATE_TE_length 4 #define GFX7_3DSTATE_TE_length 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_TE_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 4; case 70: return 4; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_TE::3D Command Opcode */ #define GFX125_3DSTATE_TE_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_TE_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_TE_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_TE_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_TE_3DCommandOpcode_bits 3 #define GFX75_3DSTATE_TE_3DCommandOpcode_bits 3 #define GFX7_3DSTATE_TE_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_TE_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_TE_3DCommandOpcode_start 24 #define GFX12_3DSTATE_TE_3DCommandOpcode_start 24 #define GFX11_3DSTATE_TE_3DCommandOpcode_start 24 #define GFX9_3DSTATE_TE_3DCommandOpcode_start 24 #define GFX8_3DSTATE_TE_3DCommandOpcode_start 24 #define GFX75_3DSTATE_TE_3DCommandOpcode_start 24 #define GFX7_3DSTATE_TE_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_TE_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_TE::3D Command Sub Opcode */ #define GFX125_3DSTATE_TE_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_TE_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_TE_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_TE_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_TE_3DCommandSubOpcode_bits 8 #define GFX75_3DSTATE_TE_3DCommandSubOpcode_bits 8 #define GFX7_3DSTATE_TE_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_TE_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_TE_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_TE_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_TE_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_TE_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_TE_3DCommandSubOpcode_start 16 #define GFX75_3DSTATE_TE_3DCommandSubOpcode_start 16 #define GFX7_3DSTATE_TE_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_TE_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_TE::Command SubType */ #define GFX125_3DSTATE_TE_CommandSubType_bits 2 #define GFX12_3DSTATE_TE_CommandSubType_bits 2 #define GFX11_3DSTATE_TE_CommandSubType_bits 2 #define GFX9_3DSTATE_TE_CommandSubType_bits 2 #define GFX8_3DSTATE_TE_CommandSubType_bits 2 #define GFX75_3DSTATE_TE_CommandSubType_bits 2 #define GFX7_3DSTATE_TE_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_TE_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_TE_CommandSubType_start 27 #define GFX12_3DSTATE_TE_CommandSubType_start 27 #define GFX11_3DSTATE_TE_CommandSubType_start 27 #define GFX9_3DSTATE_TE_CommandSubType_start 27 #define GFX8_3DSTATE_TE_CommandSubType_start 27 #define GFX75_3DSTATE_TE_CommandSubType_start 27 #define GFX7_3DSTATE_TE_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_TE_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_TE::Command Type */ #define GFX125_3DSTATE_TE_CommandType_bits 3 #define GFX12_3DSTATE_TE_CommandType_bits 3 #define GFX11_3DSTATE_TE_CommandType_bits 3 #define GFX9_3DSTATE_TE_CommandType_bits 3 #define GFX8_3DSTATE_TE_CommandType_bits 3 #define GFX75_3DSTATE_TE_CommandType_bits 3 #define GFX7_3DSTATE_TE_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_TE_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_TE_CommandType_start 29 #define GFX12_3DSTATE_TE_CommandType_start 29 #define GFX11_3DSTATE_TE_CommandType_start 29 #define GFX9_3DSTATE_TE_CommandType_start 29 #define GFX8_3DSTATE_TE_CommandType_start 29 #define GFX75_3DSTATE_TE_CommandType_start 29 #define GFX7_3DSTATE_TE_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_TE_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_TE::DWord Length */ #define GFX125_3DSTATE_TE_DWordLength_bits 8 #define GFX12_3DSTATE_TE_DWordLength_bits 8 #define GFX11_3DSTATE_TE_DWordLength_bits 8 #define GFX9_3DSTATE_TE_DWordLength_bits 8 #define GFX8_3DSTATE_TE_DWordLength_bits 8 #define GFX75_3DSTATE_TE_DWordLength_bits 8 #define GFX7_3DSTATE_TE_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_TE_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_TE_DWordLength_start 0 #define GFX12_3DSTATE_TE_DWordLength_start 0 #define GFX11_3DSTATE_TE_DWordLength_start 0 #define GFX9_3DSTATE_TE_DWordLength_start 0 #define GFX8_3DSTATE_TE_DWordLength_start 0 #define GFX75_3DSTATE_TE_DWordLength_start 0 #define GFX7_3DSTATE_TE_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_TE_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_TE::Maximum Tessellation Factor Not Odd */ #define GFX125_3DSTATE_TE_MaximumTessellationFactorNotOdd_bits 32 #define GFX12_3DSTATE_TE_MaximumTessellationFactorNotOdd_bits 32 #define GFX11_3DSTATE_TE_MaximumTessellationFactorNotOdd_bits 32 #define GFX9_3DSTATE_TE_MaximumTessellationFactorNotOdd_bits 32 #define GFX8_3DSTATE_TE_MaximumTessellationFactorNotOdd_bits 32 #define GFX75_3DSTATE_TE_MaximumTessellationFactorNotOdd_bits 32 #define GFX7_3DSTATE_TE_MaximumTessellationFactorNotOdd_bits 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_TE_MaximumTessellationFactorNotOdd_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_TE_MaximumTessellationFactorNotOdd_start 96 #define GFX12_3DSTATE_TE_MaximumTessellationFactorNotOdd_start 96 #define GFX11_3DSTATE_TE_MaximumTessellationFactorNotOdd_start 96 #define GFX9_3DSTATE_TE_MaximumTessellationFactorNotOdd_start 96 #define GFX8_3DSTATE_TE_MaximumTessellationFactorNotOdd_start 96 #define GFX75_3DSTATE_TE_MaximumTessellationFactorNotOdd_start 96 #define GFX7_3DSTATE_TE_MaximumTessellationFactorNotOdd_start 96 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_TE_MaximumTessellationFactorNotOdd_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 96; case 120: return 96; case 110: return 96; case 90: return 96; case 80: return 96; case 75: return 96; case 70: return 96; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_TE::Maximum Tessellation Factor Odd */ #define GFX125_3DSTATE_TE_MaximumTessellationFactorOdd_bits 32 #define GFX12_3DSTATE_TE_MaximumTessellationFactorOdd_bits 32 #define GFX11_3DSTATE_TE_MaximumTessellationFactorOdd_bits 32 #define GFX9_3DSTATE_TE_MaximumTessellationFactorOdd_bits 32 #define GFX8_3DSTATE_TE_MaximumTessellationFactorOdd_bits 32 #define GFX75_3DSTATE_TE_MaximumTessellationFactorOdd_bits 32 #define GFX7_3DSTATE_TE_MaximumTessellationFactorOdd_bits 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_TE_MaximumTessellationFactorOdd_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_TE_MaximumTessellationFactorOdd_start 64 #define GFX12_3DSTATE_TE_MaximumTessellationFactorOdd_start 64 #define GFX11_3DSTATE_TE_MaximumTessellationFactorOdd_start 64 #define GFX9_3DSTATE_TE_MaximumTessellationFactorOdd_start 64 #define GFX8_3DSTATE_TE_MaximumTessellationFactorOdd_start 64 #define GFX75_3DSTATE_TE_MaximumTessellationFactorOdd_start 64 #define GFX7_3DSTATE_TE_MaximumTessellationFactorOdd_start 64 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_TE_MaximumTessellationFactorOdd_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 64; case 80: return 64; case 75: return 64; case 70: return 64; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_TE::Output Topology */ #define GFX125_3DSTATE_TE_OutputTopology_bits 2 #define GFX12_3DSTATE_TE_OutputTopology_bits 2 #define GFX11_3DSTATE_TE_OutputTopology_bits 2 #define GFX9_3DSTATE_TE_OutputTopology_bits 2 #define GFX8_3DSTATE_TE_OutputTopology_bits 2 #define GFX75_3DSTATE_TE_OutputTopology_bits 2 #define GFX7_3DSTATE_TE_OutputTopology_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_TE_OutputTopology_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_TE_OutputTopology_start 40 #define GFX12_3DSTATE_TE_OutputTopology_start 40 #define GFX11_3DSTATE_TE_OutputTopology_start 40 #define GFX9_3DSTATE_TE_OutputTopology_start 40 #define GFX8_3DSTATE_TE_OutputTopology_start 40 #define GFX75_3DSTATE_TE_OutputTopology_start 40 #define GFX7_3DSTATE_TE_OutputTopology_start 40 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_TE_OutputTopology_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 40; case 120: return 40; case 110: return 40; case 90: return 40; case 80: return 40; case 75: return 40; case 70: return 40; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_TE::Partitioning */ #define GFX125_3DSTATE_TE_Partitioning_bits 2 #define GFX12_3DSTATE_TE_Partitioning_bits 2 #define GFX11_3DSTATE_TE_Partitioning_bits 2 #define GFX9_3DSTATE_TE_Partitioning_bits 2 #define GFX8_3DSTATE_TE_Partitioning_bits 2 #define GFX75_3DSTATE_TE_Partitioning_bits 2 #define GFX7_3DSTATE_TE_Partitioning_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_TE_Partitioning_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_TE_Partitioning_start 44 #define GFX12_3DSTATE_TE_Partitioning_start 44 #define GFX11_3DSTATE_TE_Partitioning_start 44 #define GFX9_3DSTATE_TE_Partitioning_start 44 #define GFX8_3DSTATE_TE_Partitioning_start 44 #define GFX75_3DSTATE_TE_Partitioning_start 44 #define GFX7_3DSTATE_TE_Partitioning_start 44 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_TE_Partitioning_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 44; case 120: return 44; case 110: return 44; case 90: return 44; case 80: return 44; case 75: return 44; case 70: return 44; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_TE::TE Domain */ #define GFX125_3DSTATE_TE_TEDomain_bits 2 #define GFX12_3DSTATE_TE_TEDomain_bits 2 #define GFX11_3DSTATE_TE_TEDomain_bits 2 #define GFX9_3DSTATE_TE_TEDomain_bits 2 #define GFX8_3DSTATE_TE_TEDomain_bits 2 #define GFX75_3DSTATE_TE_TEDomain_bits 2 #define GFX7_3DSTATE_TE_TEDomain_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_TE_TEDomain_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_TE_TEDomain_start 36 #define GFX12_3DSTATE_TE_TEDomain_start 36 #define GFX11_3DSTATE_TE_TEDomain_start 36 #define GFX9_3DSTATE_TE_TEDomain_start 36 #define GFX8_3DSTATE_TE_TEDomain_start 36 #define GFX75_3DSTATE_TE_TEDomain_start 36 #define GFX7_3DSTATE_TE_TEDomain_start 36 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_TE_TEDomain_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 36; case 120: return 36; case 110: return 36; case 90: return 36; case 80: return 36; case 75: return 36; case 70: return 36; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_TE::TE Enable */ #define GFX125_3DSTATE_TE_TEEnable_bits 1 #define GFX12_3DSTATE_TE_TEEnable_bits 1 #define GFX11_3DSTATE_TE_TEEnable_bits 1 #define GFX9_3DSTATE_TE_TEEnable_bits 1 #define GFX8_3DSTATE_TE_TEEnable_bits 1 #define GFX75_3DSTATE_TE_TEEnable_bits 1 #define GFX7_3DSTATE_TE_TEEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_TE_TEEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_TE_TEEnable_start 32 #define GFX12_3DSTATE_TE_TEEnable_start 32 #define GFX11_3DSTATE_TE_TEEnable_start 32 #define GFX9_3DSTATE_TE_TEEnable_start 32 #define GFX8_3DSTATE_TE_TEEnable_start 32 #define GFX75_3DSTATE_TE_TEEnable_start 32 #define GFX7_3DSTATE_TE_TEEnable_start 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_TE_TEEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_TE::TE Mode */ #define GFX125_3DSTATE_TE_TEMode_bits 2 #define GFX12_3DSTATE_TE_TEMode_bits 2 #define GFX11_3DSTATE_TE_TEMode_bits 2 #define GFX9_3DSTATE_TE_TEMode_bits 2 #define GFX8_3DSTATE_TE_TEMode_bits 2 #define GFX75_3DSTATE_TE_TEMode_bits 2 #define GFX7_3DSTATE_TE_TEMode_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_TE_TEMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_TE_TEMode_start 33 #define GFX12_3DSTATE_TE_TEMode_start 33 #define GFX11_3DSTATE_TE_TEMode_start 33 #define GFX9_3DSTATE_TE_TEMode_start 33 #define GFX8_3DSTATE_TE_TEMode_start 33 #define GFX75_3DSTATE_TE_TEMode_start 33 #define GFX7_3DSTATE_TE_TEMode_start 33 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_TE_TEMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 33; case 120: return 33; case 110: return 33; case 90: return 33; case 80: return 33; case 75: return 33; case 70: return 33; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_URB */ #define GFX6_3DSTATE_URB_length 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_URB::3D Command Opcode */ #define GFX6_3DSTATE_URB_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_URB_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 24; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_URB::3D Command Sub Opcode */ #define GFX6_3DSTATE_URB_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_URB_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 16; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_URB::Command SubType */ #define GFX6_3DSTATE_URB_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_URB_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 27; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_URB::Command Type */ #define GFX6_3DSTATE_URB_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_URB_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 29; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_URB::DWord Length */ #define GFX6_3DSTATE_URB_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_URB_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_URB::GS Number of URB Entries */ #define GFX6_3DSTATE_URB_GSNumberofURBEntries_bits 10 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_GSNumberofURBEntries_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 10; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_URB_GSNumberofURBEntries_start 72 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_GSNumberofURBEntries_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 72; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_URB::GS URB Entry Allocation Size */ #define GFX6_3DSTATE_URB_GSURBEntryAllocationSize_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_GSURBEntryAllocationSize_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_URB_GSURBEntryAllocationSize_start 64 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_GSURBEntryAllocationSize_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 64; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_URB::VS Number of URB Entries */ #define GFX6_3DSTATE_URB_VSNumberofURBEntries_bits 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_VSNumberofURBEntries_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 16; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_URB_VSNumberofURBEntries_start 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_VSNumberofURBEntries_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 32; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_URB::VS URB Entry Allocation Size */ #define GFX6_3DSTATE_URB_VSURBEntryAllocationSize_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_VSURBEntryAllocationSize_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_URB_VSURBEntryAllocationSize_start 48 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_VSURBEntryAllocationSize_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 48; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_URB_CLEAR */ #define GFX125_3DSTATE_URB_CLEAR_length 2 #define GFX12_3DSTATE_URB_CLEAR_length 2 #define GFX11_3DSTATE_URB_CLEAR_length 2 #define GFX9_3DSTATE_URB_CLEAR_length 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_CLEAR_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_URB_CLEAR::3D Command Opcode */ #define GFX125_3DSTATE_URB_CLEAR_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_URB_CLEAR_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_URB_CLEAR_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_URB_CLEAR_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_CLEAR_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_URB_CLEAR_3DCommandOpcode_start 24 #define GFX12_3DSTATE_URB_CLEAR_3DCommandOpcode_start 24 #define GFX11_3DSTATE_URB_CLEAR_3DCommandOpcode_start 24 #define GFX9_3DSTATE_URB_CLEAR_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_CLEAR_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_URB_CLEAR::3D Command Sub Opcode */ #define GFX125_3DSTATE_URB_CLEAR_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_URB_CLEAR_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_URB_CLEAR_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_URB_CLEAR_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_CLEAR_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_URB_CLEAR_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_URB_CLEAR_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_URB_CLEAR_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_URB_CLEAR_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_CLEAR_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_URB_CLEAR::Command SubType */ #define GFX125_3DSTATE_URB_CLEAR_CommandSubType_bits 2 #define GFX12_3DSTATE_URB_CLEAR_CommandSubType_bits 2 #define GFX11_3DSTATE_URB_CLEAR_CommandSubType_bits 2 #define GFX9_3DSTATE_URB_CLEAR_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_CLEAR_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_URB_CLEAR_CommandSubType_start 27 #define GFX12_3DSTATE_URB_CLEAR_CommandSubType_start 27 #define GFX11_3DSTATE_URB_CLEAR_CommandSubType_start 27 #define GFX9_3DSTATE_URB_CLEAR_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_CLEAR_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_URB_CLEAR::Command Type */ #define GFX125_3DSTATE_URB_CLEAR_CommandType_bits 3 #define GFX12_3DSTATE_URB_CLEAR_CommandType_bits 3 #define GFX11_3DSTATE_URB_CLEAR_CommandType_bits 3 #define GFX9_3DSTATE_URB_CLEAR_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_CLEAR_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_URB_CLEAR_CommandType_start 29 #define GFX12_3DSTATE_URB_CLEAR_CommandType_start 29 #define GFX11_3DSTATE_URB_CLEAR_CommandType_start 29 #define GFX9_3DSTATE_URB_CLEAR_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_CLEAR_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_URB_CLEAR::DWord Length */ #define GFX125_3DSTATE_URB_CLEAR_DWordLength_bits 8 #define GFX12_3DSTATE_URB_CLEAR_DWordLength_bits 8 #define GFX11_3DSTATE_URB_CLEAR_DWordLength_bits 8 #define GFX9_3DSTATE_URB_CLEAR_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_CLEAR_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_URB_CLEAR_DWordLength_start 0 #define GFX12_3DSTATE_URB_CLEAR_DWordLength_start 0 #define GFX11_3DSTATE_URB_CLEAR_DWordLength_start 0 #define GFX9_3DSTATE_URB_CLEAR_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_CLEAR_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_URB_CLEAR::URB Address */ #define GFX125_3DSTATE_URB_CLEAR_URBAddress_bits 15 #define GFX12_3DSTATE_URB_CLEAR_URBAddress_bits 15 #define GFX11_3DSTATE_URB_CLEAR_URBAddress_bits 15 #define GFX9_3DSTATE_URB_CLEAR_URBAddress_bits 15 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_CLEAR_URBAddress_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 15; case 120: return 15; case 110: return 15; case 90: return 15; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_URB_CLEAR_URBAddress_start 32 #define GFX12_3DSTATE_URB_CLEAR_URBAddress_start 32 #define GFX11_3DSTATE_URB_CLEAR_URBAddress_start 32 #define GFX9_3DSTATE_URB_CLEAR_URBAddress_start 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_CLEAR_URBAddress_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_URB_CLEAR::URB Clear Length */ #define GFX125_3DSTATE_URB_CLEAR_URBClearLength_bits 14 #define GFX12_3DSTATE_URB_CLEAR_URBClearLength_bits 14 #define GFX11_3DSTATE_URB_CLEAR_URBClearLength_bits 14 #define GFX9_3DSTATE_URB_CLEAR_URBClearLength_bits 14 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_CLEAR_URBClearLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 14; case 120: return 14; case 110: return 14; case 90: return 14; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_URB_CLEAR_URBClearLength_start 48 #define GFX12_3DSTATE_URB_CLEAR_URBClearLength_start 48 #define GFX11_3DSTATE_URB_CLEAR_URBClearLength_start 48 #define GFX9_3DSTATE_URB_CLEAR_URBClearLength_start 48 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_CLEAR_URBClearLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 48; case 120: return 48; case 110: return 48; case 90: return 48; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_URB_DS */ #define GFX125_3DSTATE_URB_DS_length 2 #define GFX12_3DSTATE_URB_DS_length 2 #define GFX11_3DSTATE_URB_DS_length 2 #define GFX9_3DSTATE_URB_DS_length 2 #define GFX8_3DSTATE_URB_DS_length 2 #define GFX75_3DSTATE_URB_DS_length 2 #define GFX7_3DSTATE_URB_DS_length 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_DS_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_URB_DS::3D Command Opcode */ #define GFX125_3DSTATE_URB_DS_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_URB_DS_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_URB_DS_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_URB_DS_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_URB_DS_3DCommandOpcode_bits 3 #define GFX75_3DSTATE_URB_DS_3DCommandOpcode_bits 3 #define GFX7_3DSTATE_URB_DS_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_DS_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_URB_DS_3DCommandOpcode_start 24 #define GFX12_3DSTATE_URB_DS_3DCommandOpcode_start 24 #define GFX11_3DSTATE_URB_DS_3DCommandOpcode_start 24 #define GFX9_3DSTATE_URB_DS_3DCommandOpcode_start 24 #define GFX8_3DSTATE_URB_DS_3DCommandOpcode_start 24 #define GFX75_3DSTATE_URB_DS_3DCommandOpcode_start 24 #define GFX7_3DSTATE_URB_DS_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_DS_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_URB_DS::3D Command Sub Opcode */ #define GFX125_3DSTATE_URB_DS_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_URB_DS_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_URB_DS_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_URB_DS_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_URB_DS_3DCommandSubOpcode_bits 8 #define GFX75_3DSTATE_URB_DS_3DCommandSubOpcode_bits 8 #define GFX7_3DSTATE_URB_DS_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_DS_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_URB_DS_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_URB_DS_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_URB_DS_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_URB_DS_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_URB_DS_3DCommandSubOpcode_start 16 #define GFX75_3DSTATE_URB_DS_3DCommandSubOpcode_start 16 #define GFX7_3DSTATE_URB_DS_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_DS_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_URB_DS::Command SubType */ #define GFX125_3DSTATE_URB_DS_CommandSubType_bits 2 #define GFX12_3DSTATE_URB_DS_CommandSubType_bits 2 #define GFX11_3DSTATE_URB_DS_CommandSubType_bits 2 #define GFX9_3DSTATE_URB_DS_CommandSubType_bits 2 #define GFX8_3DSTATE_URB_DS_CommandSubType_bits 2 #define GFX75_3DSTATE_URB_DS_CommandSubType_bits 2 #define GFX7_3DSTATE_URB_DS_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_DS_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_URB_DS_CommandSubType_start 27 #define GFX12_3DSTATE_URB_DS_CommandSubType_start 27 #define GFX11_3DSTATE_URB_DS_CommandSubType_start 27 #define GFX9_3DSTATE_URB_DS_CommandSubType_start 27 #define GFX8_3DSTATE_URB_DS_CommandSubType_start 27 #define GFX75_3DSTATE_URB_DS_CommandSubType_start 27 #define GFX7_3DSTATE_URB_DS_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_DS_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_URB_DS::Command Type */ #define GFX125_3DSTATE_URB_DS_CommandType_bits 3 #define GFX12_3DSTATE_URB_DS_CommandType_bits 3 #define GFX11_3DSTATE_URB_DS_CommandType_bits 3 #define GFX9_3DSTATE_URB_DS_CommandType_bits 3 #define GFX8_3DSTATE_URB_DS_CommandType_bits 3 #define GFX75_3DSTATE_URB_DS_CommandType_bits 3 #define GFX7_3DSTATE_URB_DS_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_DS_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_URB_DS_CommandType_start 29 #define GFX12_3DSTATE_URB_DS_CommandType_start 29 #define GFX11_3DSTATE_URB_DS_CommandType_start 29 #define GFX9_3DSTATE_URB_DS_CommandType_start 29 #define GFX8_3DSTATE_URB_DS_CommandType_start 29 #define GFX75_3DSTATE_URB_DS_CommandType_start 29 #define GFX7_3DSTATE_URB_DS_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_DS_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_URB_DS::DS Number of URB Entries */ #define GFX125_3DSTATE_URB_DS_DSNumberofURBEntries_bits 16 #define GFX12_3DSTATE_URB_DS_DSNumberofURBEntries_bits 16 #define GFX11_3DSTATE_URB_DS_DSNumberofURBEntries_bits 16 #define GFX9_3DSTATE_URB_DS_DSNumberofURBEntries_bits 16 #define GFX8_3DSTATE_URB_DS_DSNumberofURBEntries_bits 16 #define GFX75_3DSTATE_URB_DS_DSNumberofURBEntries_bits 16 #define GFX7_3DSTATE_URB_DS_DSNumberofURBEntries_bits 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_DS_DSNumberofURBEntries_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_URB_DS_DSNumberofURBEntries_start 32 #define GFX12_3DSTATE_URB_DS_DSNumberofURBEntries_start 32 #define GFX11_3DSTATE_URB_DS_DSNumberofURBEntries_start 32 #define GFX9_3DSTATE_URB_DS_DSNumberofURBEntries_start 32 #define GFX8_3DSTATE_URB_DS_DSNumberofURBEntries_start 32 #define GFX75_3DSTATE_URB_DS_DSNumberofURBEntries_start 32 #define GFX7_3DSTATE_URB_DS_DSNumberofURBEntries_start 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_DS_DSNumberofURBEntries_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_URB_DS::DS URB Entry Allocation Size */ #define GFX125_3DSTATE_URB_DS_DSURBEntryAllocationSize_bits 9 #define GFX12_3DSTATE_URB_DS_DSURBEntryAllocationSize_bits 9 #define GFX11_3DSTATE_URB_DS_DSURBEntryAllocationSize_bits 9 #define GFX9_3DSTATE_URB_DS_DSURBEntryAllocationSize_bits 9 #define GFX8_3DSTATE_URB_DS_DSURBEntryAllocationSize_bits 9 #define GFX75_3DSTATE_URB_DS_DSURBEntryAllocationSize_bits 9 #define GFX7_3DSTATE_URB_DS_DSURBEntryAllocationSize_bits 9 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_DS_DSURBEntryAllocationSize_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 9; case 120: return 9; case 110: return 9; case 90: return 9; case 80: return 9; case 75: return 9; case 70: return 9; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_URB_DS_DSURBEntryAllocationSize_start 48 #define GFX12_3DSTATE_URB_DS_DSURBEntryAllocationSize_start 48 #define GFX11_3DSTATE_URB_DS_DSURBEntryAllocationSize_start 48 #define GFX9_3DSTATE_URB_DS_DSURBEntryAllocationSize_start 48 #define GFX8_3DSTATE_URB_DS_DSURBEntryAllocationSize_start 48 #define GFX75_3DSTATE_URB_DS_DSURBEntryAllocationSize_start 48 #define GFX7_3DSTATE_URB_DS_DSURBEntryAllocationSize_start 48 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_DS_DSURBEntryAllocationSize_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 48; case 120: return 48; case 110: return 48; case 90: return 48; case 80: return 48; case 75: return 48; case 70: return 48; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_URB_DS::DS URB Starting Address */ #define GFX125_3DSTATE_URB_DS_DSURBStartingAddress_bits 7 #define GFX12_3DSTATE_URB_DS_DSURBStartingAddress_bits 7 #define GFX11_3DSTATE_URB_DS_DSURBStartingAddress_bits 7 #define GFX9_3DSTATE_URB_DS_DSURBStartingAddress_bits 7 #define GFX8_3DSTATE_URB_DS_DSURBStartingAddress_bits 7 #define GFX75_3DSTATE_URB_DS_DSURBStartingAddress_bits 6 #define GFX7_3DSTATE_URB_DS_DSURBStartingAddress_bits 5 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_DS_DSURBStartingAddress_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 7; case 120: return 7; case 110: return 7; case 90: return 7; case 80: return 7; case 75: return 6; case 70: return 5; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_URB_DS_DSURBStartingAddress_start 57 #define GFX12_3DSTATE_URB_DS_DSURBStartingAddress_start 57 #define GFX11_3DSTATE_URB_DS_DSURBStartingAddress_start 57 #define GFX9_3DSTATE_URB_DS_DSURBStartingAddress_start 57 #define GFX8_3DSTATE_URB_DS_DSURBStartingAddress_start 57 #define GFX75_3DSTATE_URB_DS_DSURBStartingAddress_start 57 #define GFX7_3DSTATE_URB_DS_DSURBStartingAddress_start 57 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_DS_DSURBStartingAddress_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 57; case 120: return 57; case 110: return 57; case 90: return 57; case 80: return 57; case 75: return 57; case 70: return 57; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_URB_DS::DWord Length */ #define GFX125_3DSTATE_URB_DS_DWordLength_bits 8 #define GFX12_3DSTATE_URB_DS_DWordLength_bits 8 #define GFX11_3DSTATE_URB_DS_DWordLength_bits 8 #define GFX9_3DSTATE_URB_DS_DWordLength_bits 8 #define GFX8_3DSTATE_URB_DS_DWordLength_bits 8 #define GFX75_3DSTATE_URB_DS_DWordLength_bits 8 #define GFX7_3DSTATE_URB_DS_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_DS_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_URB_DS_DWordLength_start 0 #define GFX12_3DSTATE_URB_DS_DWordLength_start 0 #define GFX11_3DSTATE_URB_DS_DWordLength_start 0 #define GFX9_3DSTATE_URB_DS_DWordLength_start 0 #define GFX8_3DSTATE_URB_DS_DWordLength_start 0 #define GFX75_3DSTATE_URB_DS_DWordLength_start 0 #define GFX7_3DSTATE_URB_DS_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_DS_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_URB_GS */ #define GFX125_3DSTATE_URB_GS_length 2 #define GFX12_3DSTATE_URB_GS_length 2 #define GFX11_3DSTATE_URB_GS_length 2 #define GFX9_3DSTATE_URB_GS_length 2 #define GFX8_3DSTATE_URB_GS_length 2 #define GFX75_3DSTATE_URB_GS_length 2 #define GFX7_3DSTATE_URB_GS_length 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_GS_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_URB_GS::3D Command Opcode */ #define GFX125_3DSTATE_URB_GS_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_URB_GS_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_URB_GS_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_URB_GS_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_URB_GS_3DCommandOpcode_bits 3 #define GFX75_3DSTATE_URB_GS_3DCommandOpcode_bits 3 #define GFX7_3DSTATE_URB_GS_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_GS_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_URB_GS_3DCommandOpcode_start 24 #define GFX12_3DSTATE_URB_GS_3DCommandOpcode_start 24 #define GFX11_3DSTATE_URB_GS_3DCommandOpcode_start 24 #define GFX9_3DSTATE_URB_GS_3DCommandOpcode_start 24 #define GFX8_3DSTATE_URB_GS_3DCommandOpcode_start 24 #define GFX75_3DSTATE_URB_GS_3DCommandOpcode_start 24 #define GFX7_3DSTATE_URB_GS_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_GS_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_URB_GS::3D Command Sub Opcode */ #define GFX125_3DSTATE_URB_GS_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_URB_GS_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_URB_GS_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_URB_GS_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_URB_GS_3DCommandSubOpcode_bits 8 #define GFX75_3DSTATE_URB_GS_3DCommandSubOpcode_bits 8 #define GFX7_3DSTATE_URB_GS_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_GS_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_URB_GS_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_URB_GS_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_URB_GS_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_URB_GS_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_URB_GS_3DCommandSubOpcode_start 16 #define GFX75_3DSTATE_URB_GS_3DCommandSubOpcode_start 16 #define GFX7_3DSTATE_URB_GS_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_GS_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_URB_GS::Command SubType */ #define GFX125_3DSTATE_URB_GS_CommandSubType_bits 2 #define GFX12_3DSTATE_URB_GS_CommandSubType_bits 2 #define GFX11_3DSTATE_URB_GS_CommandSubType_bits 2 #define GFX9_3DSTATE_URB_GS_CommandSubType_bits 2 #define GFX8_3DSTATE_URB_GS_CommandSubType_bits 2 #define GFX75_3DSTATE_URB_GS_CommandSubType_bits 2 #define GFX7_3DSTATE_URB_GS_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_GS_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_URB_GS_CommandSubType_start 27 #define GFX12_3DSTATE_URB_GS_CommandSubType_start 27 #define GFX11_3DSTATE_URB_GS_CommandSubType_start 27 #define GFX9_3DSTATE_URB_GS_CommandSubType_start 27 #define GFX8_3DSTATE_URB_GS_CommandSubType_start 27 #define GFX75_3DSTATE_URB_GS_CommandSubType_start 27 #define GFX7_3DSTATE_URB_GS_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_GS_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_URB_GS::Command Type */ #define GFX125_3DSTATE_URB_GS_CommandType_bits 3 #define GFX12_3DSTATE_URB_GS_CommandType_bits 3 #define GFX11_3DSTATE_URB_GS_CommandType_bits 3 #define GFX9_3DSTATE_URB_GS_CommandType_bits 3 #define GFX8_3DSTATE_URB_GS_CommandType_bits 3 #define GFX75_3DSTATE_URB_GS_CommandType_bits 3 #define GFX7_3DSTATE_URB_GS_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_GS_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_URB_GS_CommandType_start 29 #define GFX12_3DSTATE_URB_GS_CommandType_start 29 #define GFX11_3DSTATE_URB_GS_CommandType_start 29 #define GFX9_3DSTATE_URB_GS_CommandType_start 29 #define GFX8_3DSTATE_URB_GS_CommandType_start 29 #define GFX75_3DSTATE_URB_GS_CommandType_start 29 #define GFX7_3DSTATE_URB_GS_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_GS_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_URB_GS::DWord Length */ #define GFX125_3DSTATE_URB_GS_DWordLength_bits 8 #define GFX12_3DSTATE_URB_GS_DWordLength_bits 8 #define GFX11_3DSTATE_URB_GS_DWordLength_bits 8 #define GFX9_3DSTATE_URB_GS_DWordLength_bits 8 #define GFX8_3DSTATE_URB_GS_DWordLength_bits 8 #define GFX75_3DSTATE_URB_GS_DWordLength_bits 8 #define GFX7_3DSTATE_URB_GS_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_GS_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_URB_GS_DWordLength_start 0 #define GFX12_3DSTATE_URB_GS_DWordLength_start 0 #define GFX11_3DSTATE_URB_GS_DWordLength_start 0 #define GFX9_3DSTATE_URB_GS_DWordLength_start 0 #define GFX8_3DSTATE_URB_GS_DWordLength_start 0 #define GFX75_3DSTATE_URB_GS_DWordLength_start 0 #define GFX7_3DSTATE_URB_GS_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_GS_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_URB_GS::GS Number of URB Entries */ #define GFX125_3DSTATE_URB_GS_GSNumberofURBEntries_bits 16 #define GFX12_3DSTATE_URB_GS_GSNumberofURBEntries_bits 16 #define GFX11_3DSTATE_URB_GS_GSNumberofURBEntries_bits 16 #define GFX9_3DSTATE_URB_GS_GSNumberofURBEntries_bits 16 #define GFX8_3DSTATE_URB_GS_GSNumberofURBEntries_bits 16 #define GFX75_3DSTATE_URB_GS_GSNumberofURBEntries_bits 16 #define GFX7_3DSTATE_URB_GS_GSNumberofURBEntries_bits 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_GS_GSNumberofURBEntries_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_URB_GS_GSNumberofURBEntries_start 32 #define GFX12_3DSTATE_URB_GS_GSNumberofURBEntries_start 32 #define GFX11_3DSTATE_URB_GS_GSNumberofURBEntries_start 32 #define GFX9_3DSTATE_URB_GS_GSNumberofURBEntries_start 32 #define GFX8_3DSTATE_URB_GS_GSNumberofURBEntries_start 32 #define GFX75_3DSTATE_URB_GS_GSNumberofURBEntries_start 32 #define GFX7_3DSTATE_URB_GS_GSNumberofURBEntries_start 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_GS_GSNumberofURBEntries_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_URB_GS::GS URB Entry Allocation Size */ #define GFX125_3DSTATE_URB_GS_GSURBEntryAllocationSize_bits 9 #define GFX12_3DSTATE_URB_GS_GSURBEntryAllocationSize_bits 9 #define GFX11_3DSTATE_URB_GS_GSURBEntryAllocationSize_bits 9 #define GFX9_3DSTATE_URB_GS_GSURBEntryAllocationSize_bits 9 #define GFX8_3DSTATE_URB_GS_GSURBEntryAllocationSize_bits 9 #define GFX75_3DSTATE_URB_GS_GSURBEntryAllocationSize_bits 9 #define GFX7_3DSTATE_URB_GS_GSURBEntryAllocationSize_bits 9 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_GS_GSURBEntryAllocationSize_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 9; case 120: return 9; case 110: return 9; case 90: return 9; case 80: return 9; case 75: return 9; case 70: return 9; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_URB_GS_GSURBEntryAllocationSize_start 48 #define GFX12_3DSTATE_URB_GS_GSURBEntryAllocationSize_start 48 #define GFX11_3DSTATE_URB_GS_GSURBEntryAllocationSize_start 48 #define GFX9_3DSTATE_URB_GS_GSURBEntryAllocationSize_start 48 #define GFX8_3DSTATE_URB_GS_GSURBEntryAllocationSize_start 48 #define GFX75_3DSTATE_URB_GS_GSURBEntryAllocationSize_start 48 #define GFX7_3DSTATE_URB_GS_GSURBEntryAllocationSize_start 48 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_GS_GSURBEntryAllocationSize_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 48; case 120: return 48; case 110: return 48; case 90: return 48; case 80: return 48; case 75: return 48; case 70: return 48; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_URB_GS::GS URB Starting Address */ #define GFX125_3DSTATE_URB_GS_GSURBStartingAddress_bits 7 #define GFX12_3DSTATE_URB_GS_GSURBStartingAddress_bits 7 #define GFX11_3DSTATE_URB_GS_GSURBStartingAddress_bits 7 #define GFX9_3DSTATE_URB_GS_GSURBStartingAddress_bits 7 #define GFX8_3DSTATE_URB_GS_GSURBStartingAddress_bits 7 #define GFX75_3DSTATE_URB_GS_GSURBStartingAddress_bits 6 #define GFX7_3DSTATE_URB_GS_GSURBStartingAddress_bits 5 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_GS_GSURBStartingAddress_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 7; case 120: return 7; case 110: return 7; case 90: return 7; case 80: return 7; case 75: return 6; case 70: return 5; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_URB_GS_GSURBStartingAddress_start 57 #define GFX12_3DSTATE_URB_GS_GSURBStartingAddress_start 57 #define GFX11_3DSTATE_URB_GS_GSURBStartingAddress_start 57 #define GFX9_3DSTATE_URB_GS_GSURBStartingAddress_start 57 #define GFX8_3DSTATE_URB_GS_GSURBStartingAddress_start 57 #define GFX75_3DSTATE_URB_GS_GSURBStartingAddress_start 57 #define GFX7_3DSTATE_URB_GS_GSURBStartingAddress_start 57 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_GS_GSURBStartingAddress_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 57; case 120: return 57; case 110: return 57; case 90: return 57; case 80: return 57; case 75: return 57; case 70: return 57; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_URB_HS */ #define GFX125_3DSTATE_URB_HS_length 2 #define GFX12_3DSTATE_URB_HS_length 2 #define GFX11_3DSTATE_URB_HS_length 2 #define GFX9_3DSTATE_URB_HS_length 2 #define GFX8_3DSTATE_URB_HS_length 2 #define GFX75_3DSTATE_URB_HS_length 2 #define GFX7_3DSTATE_URB_HS_length 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_HS_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_URB_HS::3D Command Opcode */ #define GFX125_3DSTATE_URB_HS_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_URB_HS_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_URB_HS_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_URB_HS_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_URB_HS_3DCommandOpcode_bits 3 #define GFX75_3DSTATE_URB_HS_3DCommandOpcode_bits 3 #define GFX7_3DSTATE_URB_HS_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_HS_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_URB_HS_3DCommandOpcode_start 24 #define GFX12_3DSTATE_URB_HS_3DCommandOpcode_start 24 #define GFX11_3DSTATE_URB_HS_3DCommandOpcode_start 24 #define GFX9_3DSTATE_URB_HS_3DCommandOpcode_start 24 #define GFX8_3DSTATE_URB_HS_3DCommandOpcode_start 24 #define GFX75_3DSTATE_URB_HS_3DCommandOpcode_start 24 #define GFX7_3DSTATE_URB_HS_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_HS_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_URB_HS::3D Command Sub Opcode */ #define GFX125_3DSTATE_URB_HS_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_URB_HS_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_URB_HS_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_URB_HS_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_URB_HS_3DCommandSubOpcode_bits 8 #define GFX75_3DSTATE_URB_HS_3DCommandSubOpcode_bits 8 #define GFX7_3DSTATE_URB_HS_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_HS_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_URB_HS_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_URB_HS_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_URB_HS_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_URB_HS_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_URB_HS_3DCommandSubOpcode_start 16 #define GFX75_3DSTATE_URB_HS_3DCommandSubOpcode_start 16 #define GFX7_3DSTATE_URB_HS_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_HS_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_URB_HS::Command SubType */ #define GFX125_3DSTATE_URB_HS_CommandSubType_bits 2 #define GFX12_3DSTATE_URB_HS_CommandSubType_bits 2 #define GFX11_3DSTATE_URB_HS_CommandSubType_bits 2 #define GFX9_3DSTATE_URB_HS_CommandSubType_bits 2 #define GFX8_3DSTATE_URB_HS_CommandSubType_bits 2 #define GFX75_3DSTATE_URB_HS_CommandSubType_bits 2 #define GFX7_3DSTATE_URB_HS_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_HS_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_URB_HS_CommandSubType_start 27 #define GFX12_3DSTATE_URB_HS_CommandSubType_start 27 #define GFX11_3DSTATE_URB_HS_CommandSubType_start 27 #define GFX9_3DSTATE_URB_HS_CommandSubType_start 27 #define GFX8_3DSTATE_URB_HS_CommandSubType_start 27 #define GFX75_3DSTATE_URB_HS_CommandSubType_start 27 #define GFX7_3DSTATE_URB_HS_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_HS_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_URB_HS::Command Type */ #define GFX125_3DSTATE_URB_HS_CommandType_bits 3 #define GFX12_3DSTATE_URB_HS_CommandType_bits 3 #define GFX11_3DSTATE_URB_HS_CommandType_bits 3 #define GFX9_3DSTATE_URB_HS_CommandType_bits 3 #define GFX8_3DSTATE_URB_HS_CommandType_bits 3 #define GFX75_3DSTATE_URB_HS_CommandType_bits 3 #define GFX7_3DSTATE_URB_HS_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_HS_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_URB_HS_CommandType_start 29 #define GFX12_3DSTATE_URB_HS_CommandType_start 29 #define GFX11_3DSTATE_URB_HS_CommandType_start 29 #define GFX9_3DSTATE_URB_HS_CommandType_start 29 #define GFX8_3DSTATE_URB_HS_CommandType_start 29 #define GFX75_3DSTATE_URB_HS_CommandType_start 29 #define GFX7_3DSTATE_URB_HS_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_HS_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_URB_HS::DWord Length */ #define GFX125_3DSTATE_URB_HS_DWordLength_bits 8 #define GFX12_3DSTATE_URB_HS_DWordLength_bits 8 #define GFX11_3DSTATE_URB_HS_DWordLength_bits 8 #define GFX9_3DSTATE_URB_HS_DWordLength_bits 8 #define GFX8_3DSTATE_URB_HS_DWordLength_bits 8 #define GFX75_3DSTATE_URB_HS_DWordLength_bits 8 #define GFX7_3DSTATE_URB_HS_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_HS_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_URB_HS_DWordLength_start 0 #define GFX12_3DSTATE_URB_HS_DWordLength_start 0 #define GFX11_3DSTATE_URB_HS_DWordLength_start 0 #define GFX9_3DSTATE_URB_HS_DWordLength_start 0 #define GFX8_3DSTATE_URB_HS_DWordLength_start 0 #define GFX75_3DSTATE_URB_HS_DWordLength_start 0 #define GFX7_3DSTATE_URB_HS_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_HS_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_URB_HS::HS Number of URB Entries */ #define GFX125_3DSTATE_URB_HS_HSNumberofURBEntries_bits 16 #define GFX12_3DSTATE_URB_HS_HSNumberofURBEntries_bits 16 #define GFX11_3DSTATE_URB_HS_HSNumberofURBEntries_bits 16 #define GFX9_3DSTATE_URB_HS_HSNumberofURBEntries_bits 16 #define GFX8_3DSTATE_URB_HS_HSNumberofURBEntries_bits 16 #define GFX75_3DSTATE_URB_HS_HSNumberofURBEntries_bits 16 #define GFX7_3DSTATE_URB_HS_HSNumberofURBEntries_bits 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_HS_HSNumberofURBEntries_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_URB_HS_HSNumberofURBEntries_start 32 #define GFX12_3DSTATE_URB_HS_HSNumberofURBEntries_start 32 #define GFX11_3DSTATE_URB_HS_HSNumberofURBEntries_start 32 #define GFX9_3DSTATE_URB_HS_HSNumberofURBEntries_start 32 #define GFX8_3DSTATE_URB_HS_HSNumberofURBEntries_start 32 #define GFX75_3DSTATE_URB_HS_HSNumberofURBEntries_start 32 #define GFX7_3DSTATE_URB_HS_HSNumberofURBEntries_start 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_HS_HSNumberofURBEntries_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_URB_HS::HS URB Entry Allocation Size */ #define GFX125_3DSTATE_URB_HS_HSURBEntryAllocationSize_bits 9 #define GFX12_3DSTATE_URB_HS_HSURBEntryAllocationSize_bits 9 #define GFX11_3DSTATE_URB_HS_HSURBEntryAllocationSize_bits 9 #define GFX9_3DSTATE_URB_HS_HSURBEntryAllocationSize_bits 9 #define GFX8_3DSTATE_URB_HS_HSURBEntryAllocationSize_bits 9 #define GFX75_3DSTATE_URB_HS_HSURBEntryAllocationSize_bits 9 #define GFX7_3DSTATE_URB_HS_HSURBEntryAllocationSize_bits 9 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_HS_HSURBEntryAllocationSize_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 9; case 120: return 9; case 110: return 9; case 90: return 9; case 80: return 9; case 75: return 9; case 70: return 9; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_URB_HS_HSURBEntryAllocationSize_start 48 #define GFX12_3DSTATE_URB_HS_HSURBEntryAllocationSize_start 48 #define GFX11_3DSTATE_URB_HS_HSURBEntryAllocationSize_start 48 #define GFX9_3DSTATE_URB_HS_HSURBEntryAllocationSize_start 48 #define GFX8_3DSTATE_URB_HS_HSURBEntryAllocationSize_start 48 #define GFX75_3DSTATE_URB_HS_HSURBEntryAllocationSize_start 48 #define GFX7_3DSTATE_URB_HS_HSURBEntryAllocationSize_start 48 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_HS_HSURBEntryAllocationSize_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 48; case 120: return 48; case 110: return 48; case 90: return 48; case 80: return 48; case 75: return 48; case 70: return 48; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_URB_HS::HS URB Starting Address */ #define GFX125_3DSTATE_URB_HS_HSURBStartingAddress_bits 7 #define GFX12_3DSTATE_URB_HS_HSURBStartingAddress_bits 7 #define GFX11_3DSTATE_URB_HS_HSURBStartingAddress_bits 7 #define GFX9_3DSTATE_URB_HS_HSURBStartingAddress_bits 7 #define GFX8_3DSTATE_URB_HS_HSURBStartingAddress_bits 7 #define GFX75_3DSTATE_URB_HS_HSURBStartingAddress_bits 6 #define GFX7_3DSTATE_URB_HS_HSURBStartingAddress_bits 5 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_HS_HSURBStartingAddress_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 7; case 120: return 7; case 110: return 7; case 90: return 7; case 80: return 7; case 75: return 6; case 70: return 5; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_URB_HS_HSURBStartingAddress_start 57 #define GFX12_3DSTATE_URB_HS_HSURBStartingAddress_start 57 #define GFX11_3DSTATE_URB_HS_HSURBStartingAddress_start 57 #define GFX9_3DSTATE_URB_HS_HSURBStartingAddress_start 57 #define GFX8_3DSTATE_URB_HS_HSURBStartingAddress_start 57 #define GFX75_3DSTATE_URB_HS_HSURBStartingAddress_start 57 #define GFX7_3DSTATE_URB_HS_HSURBStartingAddress_start 57 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_HS_HSURBStartingAddress_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 57; case 120: return 57; case 110: return 57; case 90: return 57; case 80: return 57; case 75: return 57; case 70: return 57; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_URB_VS */ #define GFX125_3DSTATE_URB_VS_length 2 #define GFX12_3DSTATE_URB_VS_length 2 #define GFX11_3DSTATE_URB_VS_length 2 #define GFX9_3DSTATE_URB_VS_length 2 #define GFX8_3DSTATE_URB_VS_length 2 #define GFX75_3DSTATE_URB_VS_length 2 #define GFX7_3DSTATE_URB_VS_length 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_VS_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_URB_VS::3D Command Opcode */ #define GFX125_3DSTATE_URB_VS_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_URB_VS_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_URB_VS_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_URB_VS_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_URB_VS_3DCommandOpcode_bits 3 #define GFX75_3DSTATE_URB_VS_3DCommandOpcode_bits 3 #define GFX7_3DSTATE_URB_VS_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_VS_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_URB_VS_3DCommandOpcode_start 24 #define GFX12_3DSTATE_URB_VS_3DCommandOpcode_start 24 #define GFX11_3DSTATE_URB_VS_3DCommandOpcode_start 24 #define GFX9_3DSTATE_URB_VS_3DCommandOpcode_start 24 #define GFX8_3DSTATE_URB_VS_3DCommandOpcode_start 24 #define GFX75_3DSTATE_URB_VS_3DCommandOpcode_start 24 #define GFX7_3DSTATE_URB_VS_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_VS_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_URB_VS::3D Command Sub Opcode */ #define GFX125_3DSTATE_URB_VS_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_URB_VS_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_URB_VS_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_URB_VS_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_URB_VS_3DCommandSubOpcode_bits 8 #define GFX75_3DSTATE_URB_VS_3DCommandSubOpcode_bits 8 #define GFX7_3DSTATE_URB_VS_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_VS_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_URB_VS_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_URB_VS_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_URB_VS_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_URB_VS_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_URB_VS_3DCommandSubOpcode_start 16 #define GFX75_3DSTATE_URB_VS_3DCommandSubOpcode_start 16 #define GFX7_3DSTATE_URB_VS_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_VS_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_URB_VS::Command SubType */ #define GFX125_3DSTATE_URB_VS_CommandSubType_bits 2 #define GFX12_3DSTATE_URB_VS_CommandSubType_bits 2 #define GFX11_3DSTATE_URB_VS_CommandSubType_bits 2 #define GFX9_3DSTATE_URB_VS_CommandSubType_bits 2 #define GFX8_3DSTATE_URB_VS_CommandSubType_bits 2 #define GFX75_3DSTATE_URB_VS_CommandSubType_bits 2 #define GFX7_3DSTATE_URB_VS_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_VS_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_URB_VS_CommandSubType_start 27 #define GFX12_3DSTATE_URB_VS_CommandSubType_start 27 #define GFX11_3DSTATE_URB_VS_CommandSubType_start 27 #define GFX9_3DSTATE_URB_VS_CommandSubType_start 27 #define GFX8_3DSTATE_URB_VS_CommandSubType_start 27 #define GFX75_3DSTATE_URB_VS_CommandSubType_start 27 #define GFX7_3DSTATE_URB_VS_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_VS_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_URB_VS::Command Type */ #define GFX125_3DSTATE_URB_VS_CommandType_bits 3 #define GFX12_3DSTATE_URB_VS_CommandType_bits 3 #define GFX11_3DSTATE_URB_VS_CommandType_bits 3 #define GFX9_3DSTATE_URB_VS_CommandType_bits 3 #define GFX8_3DSTATE_URB_VS_CommandType_bits 3 #define GFX75_3DSTATE_URB_VS_CommandType_bits 3 #define GFX7_3DSTATE_URB_VS_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_VS_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_URB_VS_CommandType_start 29 #define GFX12_3DSTATE_URB_VS_CommandType_start 29 #define GFX11_3DSTATE_URB_VS_CommandType_start 29 #define GFX9_3DSTATE_URB_VS_CommandType_start 29 #define GFX8_3DSTATE_URB_VS_CommandType_start 29 #define GFX75_3DSTATE_URB_VS_CommandType_start 29 #define GFX7_3DSTATE_URB_VS_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_VS_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_URB_VS::DWord Length */ #define GFX125_3DSTATE_URB_VS_DWordLength_bits 8 #define GFX12_3DSTATE_URB_VS_DWordLength_bits 8 #define GFX11_3DSTATE_URB_VS_DWordLength_bits 8 #define GFX9_3DSTATE_URB_VS_DWordLength_bits 8 #define GFX8_3DSTATE_URB_VS_DWordLength_bits 8 #define GFX75_3DSTATE_URB_VS_DWordLength_bits 8 #define GFX7_3DSTATE_URB_VS_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_VS_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_URB_VS_DWordLength_start 0 #define GFX12_3DSTATE_URB_VS_DWordLength_start 0 #define GFX11_3DSTATE_URB_VS_DWordLength_start 0 #define GFX9_3DSTATE_URB_VS_DWordLength_start 0 #define GFX8_3DSTATE_URB_VS_DWordLength_start 0 #define GFX75_3DSTATE_URB_VS_DWordLength_start 0 #define GFX7_3DSTATE_URB_VS_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_VS_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_URB_VS::VS Number of URB Entries */ #define GFX125_3DSTATE_URB_VS_VSNumberofURBEntries_bits 16 #define GFX12_3DSTATE_URB_VS_VSNumberofURBEntries_bits 16 #define GFX11_3DSTATE_URB_VS_VSNumberofURBEntries_bits 16 #define GFX9_3DSTATE_URB_VS_VSNumberofURBEntries_bits 16 #define GFX8_3DSTATE_URB_VS_VSNumberofURBEntries_bits 16 #define GFX75_3DSTATE_URB_VS_VSNumberofURBEntries_bits 16 #define GFX7_3DSTATE_URB_VS_VSNumberofURBEntries_bits 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_VS_VSNumberofURBEntries_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_URB_VS_VSNumberofURBEntries_start 32 #define GFX12_3DSTATE_URB_VS_VSNumberofURBEntries_start 32 #define GFX11_3DSTATE_URB_VS_VSNumberofURBEntries_start 32 #define GFX9_3DSTATE_URB_VS_VSNumberofURBEntries_start 32 #define GFX8_3DSTATE_URB_VS_VSNumberofURBEntries_start 32 #define GFX75_3DSTATE_URB_VS_VSNumberofURBEntries_start 32 #define GFX7_3DSTATE_URB_VS_VSNumberofURBEntries_start 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_VS_VSNumberofURBEntries_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_URB_VS::VS URB Entry Allocation Size */ #define GFX125_3DSTATE_URB_VS_VSURBEntryAllocationSize_bits 9 #define GFX12_3DSTATE_URB_VS_VSURBEntryAllocationSize_bits 9 #define GFX11_3DSTATE_URB_VS_VSURBEntryAllocationSize_bits 9 #define GFX9_3DSTATE_URB_VS_VSURBEntryAllocationSize_bits 9 #define GFX8_3DSTATE_URB_VS_VSURBEntryAllocationSize_bits 9 #define GFX75_3DSTATE_URB_VS_VSURBEntryAllocationSize_bits 9 #define GFX7_3DSTATE_URB_VS_VSURBEntryAllocationSize_bits 9 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_VS_VSURBEntryAllocationSize_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 9; case 120: return 9; case 110: return 9; case 90: return 9; case 80: return 9; case 75: return 9; case 70: return 9; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_URB_VS_VSURBEntryAllocationSize_start 48 #define GFX12_3DSTATE_URB_VS_VSURBEntryAllocationSize_start 48 #define GFX11_3DSTATE_URB_VS_VSURBEntryAllocationSize_start 48 #define GFX9_3DSTATE_URB_VS_VSURBEntryAllocationSize_start 48 #define GFX8_3DSTATE_URB_VS_VSURBEntryAllocationSize_start 48 #define GFX75_3DSTATE_URB_VS_VSURBEntryAllocationSize_start 48 #define GFX7_3DSTATE_URB_VS_VSURBEntryAllocationSize_start 48 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_VS_VSURBEntryAllocationSize_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 48; case 120: return 48; case 110: return 48; case 90: return 48; case 80: return 48; case 75: return 48; case 70: return 48; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_URB_VS::VS URB Starting Address */ #define GFX125_3DSTATE_URB_VS_VSURBStartingAddress_bits 7 #define GFX12_3DSTATE_URB_VS_VSURBStartingAddress_bits 7 #define GFX11_3DSTATE_URB_VS_VSURBStartingAddress_bits 7 #define GFX9_3DSTATE_URB_VS_VSURBStartingAddress_bits 7 #define GFX8_3DSTATE_URB_VS_VSURBStartingAddress_bits 7 #define GFX75_3DSTATE_URB_VS_VSURBStartingAddress_bits 6 #define GFX7_3DSTATE_URB_VS_VSURBStartingAddress_bits 5 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_VS_VSURBStartingAddress_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 7; case 120: return 7; case 110: return 7; case 90: return 7; case 80: return 7; case 75: return 6; case 70: return 5; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_URB_VS_VSURBStartingAddress_start 57 #define GFX12_3DSTATE_URB_VS_VSURBStartingAddress_start 57 #define GFX11_3DSTATE_URB_VS_VSURBStartingAddress_start 57 #define GFX9_3DSTATE_URB_VS_VSURBStartingAddress_start 57 #define GFX8_3DSTATE_URB_VS_VSURBStartingAddress_start 57 #define GFX75_3DSTATE_URB_VS_VSURBStartingAddress_start 57 #define GFX7_3DSTATE_URB_VS_VSURBStartingAddress_start 57 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_URB_VS_VSURBStartingAddress_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 57; case 120: return 57; case 110: return 57; case 90: return 57; case 80: return 57; case 75: return 57; case 70: return 57; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VERTEX_BUFFERS */ /* 3DSTATE_VERTEX_BUFFERS::3D Command Opcode */ #define GFX125_3DSTATE_VERTEX_BUFFERS_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_VERTEX_BUFFERS_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_VERTEX_BUFFERS_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_VERTEX_BUFFERS_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_VERTEX_BUFFERS_3DCommandOpcode_bits 3 #define GFX75_3DSTATE_VERTEX_BUFFERS_3DCommandOpcode_bits 3 #define GFX7_3DSTATE_VERTEX_BUFFERS_3DCommandOpcode_bits 3 #define GFX6_3DSTATE_VERTEX_BUFFERS_3DCommandOpcode_bits 3 #define GFX5_3DSTATE_VERTEX_BUFFERS_3DCommandOpcode_bits 3 #define GFX45_3DSTATE_VERTEX_BUFFERS_3DCommandOpcode_bits 3 #define GFX4_3DSTATE_VERTEX_BUFFERS_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VERTEX_BUFFERS_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VERTEX_BUFFERS_3DCommandOpcode_start 24 #define GFX12_3DSTATE_VERTEX_BUFFERS_3DCommandOpcode_start 24 #define GFX11_3DSTATE_VERTEX_BUFFERS_3DCommandOpcode_start 24 #define GFX9_3DSTATE_VERTEX_BUFFERS_3DCommandOpcode_start 24 #define GFX8_3DSTATE_VERTEX_BUFFERS_3DCommandOpcode_start 24 #define GFX75_3DSTATE_VERTEX_BUFFERS_3DCommandOpcode_start 24 #define GFX7_3DSTATE_VERTEX_BUFFERS_3DCommandOpcode_start 24 #define GFX6_3DSTATE_VERTEX_BUFFERS_3DCommandOpcode_start 24 #define GFX5_3DSTATE_VERTEX_BUFFERS_3DCommandOpcode_start 24 #define GFX45_3DSTATE_VERTEX_BUFFERS_3DCommandOpcode_start 24 #define GFX4_3DSTATE_VERTEX_BUFFERS_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VERTEX_BUFFERS_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 24; case 50: return 24; case 45: return 24; case 40: return 24; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VERTEX_BUFFERS::3D Command Sub Opcode */ #define GFX125_3DSTATE_VERTEX_BUFFERS_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_VERTEX_BUFFERS_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_VERTEX_BUFFERS_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_VERTEX_BUFFERS_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_VERTEX_BUFFERS_3DCommandSubOpcode_bits 8 #define GFX75_3DSTATE_VERTEX_BUFFERS_3DCommandSubOpcode_bits 8 #define GFX7_3DSTATE_VERTEX_BUFFERS_3DCommandSubOpcode_bits 8 #define GFX6_3DSTATE_VERTEX_BUFFERS_3DCommandSubOpcode_bits 8 #define GFX5_3DSTATE_VERTEX_BUFFERS_3DCommandSubOpcode_bits 8 #define GFX45_3DSTATE_VERTEX_BUFFERS_3DCommandSubOpcode_bits 8 #define GFX4_3DSTATE_VERTEX_BUFFERS_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VERTEX_BUFFERS_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 8; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VERTEX_BUFFERS_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_VERTEX_BUFFERS_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_VERTEX_BUFFERS_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_VERTEX_BUFFERS_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_VERTEX_BUFFERS_3DCommandSubOpcode_start 16 #define GFX75_3DSTATE_VERTEX_BUFFERS_3DCommandSubOpcode_start 16 #define GFX7_3DSTATE_VERTEX_BUFFERS_3DCommandSubOpcode_start 16 #define GFX6_3DSTATE_VERTEX_BUFFERS_3DCommandSubOpcode_start 16 #define GFX5_3DSTATE_VERTEX_BUFFERS_3DCommandSubOpcode_start 16 #define GFX45_3DSTATE_VERTEX_BUFFERS_3DCommandSubOpcode_start 16 #define GFX4_3DSTATE_VERTEX_BUFFERS_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VERTEX_BUFFERS_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 16; case 50: return 16; case 45: return 16; case 40: return 16; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VERTEX_BUFFERS::Command SubType */ #define GFX125_3DSTATE_VERTEX_BUFFERS_CommandSubType_bits 2 #define GFX12_3DSTATE_VERTEX_BUFFERS_CommandSubType_bits 2 #define GFX11_3DSTATE_VERTEX_BUFFERS_CommandSubType_bits 2 #define GFX9_3DSTATE_VERTEX_BUFFERS_CommandSubType_bits 2 #define GFX8_3DSTATE_VERTEX_BUFFERS_CommandSubType_bits 2 #define GFX75_3DSTATE_VERTEX_BUFFERS_CommandSubType_bits 2 #define GFX7_3DSTATE_VERTEX_BUFFERS_CommandSubType_bits 2 #define GFX6_3DSTATE_VERTEX_BUFFERS_CommandSubType_bits 2 #define GFX5_3DSTATE_VERTEX_BUFFERS_CommandSubType_bits 2 #define GFX45_3DSTATE_VERTEX_BUFFERS_CommandSubType_bits 2 #define GFX4_3DSTATE_VERTEX_BUFFERS_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VERTEX_BUFFERS_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 2; case 45: return 2; case 40: return 2; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VERTEX_BUFFERS_CommandSubType_start 27 #define GFX12_3DSTATE_VERTEX_BUFFERS_CommandSubType_start 27 #define GFX11_3DSTATE_VERTEX_BUFFERS_CommandSubType_start 27 #define GFX9_3DSTATE_VERTEX_BUFFERS_CommandSubType_start 27 #define GFX8_3DSTATE_VERTEX_BUFFERS_CommandSubType_start 27 #define GFX75_3DSTATE_VERTEX_BUFFERS_CommandSubType_start 27 #define GFX7_3DSTATE_VERTEX_BUFFERS_CommandSubType_start 27 #define GFX6_3DSTATE_VERTEX_BUFFERS_CommandSubType_start 27 #define GFX5_3DSTATE_VERTEX_BUFFERS_CommandSubType_start 27 #define GFX45_3DSTATE_VERTEX_BUFFERS_CommandSubType_start 27 #define GFX4_3DSTATE_VERTEX_BUFFERS_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VERTEX_BUFFERS_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 27; case 50: return 27; case 45: return 27; case 40: return 27; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VERTEX_BUFFERS::Command Type */ #define GFX125_3DSTATE_VERTEX_BUFFERS_CommandType_bits 3 #define GFX12_3DSTATE_VERTEX_BUFFERS_CommandType_bits 3 #define GFX11_3DSTATE_VERTEX_BUFFERS_CommandType_bits 3 #define GFX9_3DSTATE_VERTEX_BUFFERS_CommandType_bits 3 #define GFX8_3DSTATE_VERTEX_BUFFERS_CommandType_bits 3 #define GFX75_3DSTATE_VERTEX_BUFFERS_CommandType_bits 3 #define GFX7_3DSTATE_VERTEX_BUFFERS_CommandType_bits 3 #define GFX6_3DSTATE_VERTEX_BUFFERS_CommandType_bits 3 #define GFX5_3DSTATE_VERTEX_BUFFERS_CommandType_bits 3 #define GFX45_3DSTATE_VERTEX_BUFFERS_CommandType_bits 3 #define GFX4_3DSTATE_VERTEX_BUFFERS_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VERTEX_BUFFERS_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VERTEX_BUFFERS_CommandType_start 29 #define GFX12_3DSTATE_VERTEX_BUFFERS_CommandType_start 29 #define GFX11_3DSTATE_VERTEX_BUFFERS_CommandType_start 29 #define GFX9_3DSTATE_VERTEX_BUFFERS_CommandType_start 29 #define GFX8_3DSTATE_VERTEX_BUFFERS_CommandType_start 29 #define GFX75_3DSTATE_VERTEX_BUFFERS_CommandType_start 29 #define GFX7_3DSTATE_VERTEX_BUFFERS_CommandType_start 29 #define GFX6_3DSTATE_VERTEX_BUFFERS_CommandType_start 29 #define GFX5_3DSTATE_VERTEX_BUFFERS_CommandType_start 29 #define GFX45_3DSTATE_VERTEX_BUFFERS_CommandType_start 29 #define GFX4_3DSTATE_VERTEX_BUFFERS_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VERTEX_BUFFERS_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 29; case 50: return 29; case 45: return 29; case 40: return 29; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VERTEX_BUFFERS::DWord Length */ #define GFX125_3DSTATE_VERTEX_BUFFERS_DWordLength_bits 8 #define GFX12_3DSTATE_VERTEX_BUFFERS_DWordLength_bits 8 #define GFX11_3DSTATE_VERTEX_BUFFERS_DWordLength_bits 8 #define GFX9_3DSTATE_VERTEX_BUFFERS_DWordLength_bits 8 #define GFX8_3DSTATE_VERTEX_BUFFERS_DWordLength_bits 8 #define GFX75_3DSTATE_VERTEX_BUFFERS_DWordLength_bits 8 #define GFX7_3DSTATE_VERTEX_BUFFERS_DWordLength_bits 8 #define GFX6_3DSTATE_VERTEX_BUFFERS_DWordLength_bits 8 #define GFX5_3DSTATE_VERTEX_BUFFERS_DWordLength_bits 8 #define GFX45_3DSTATE_VERTEX_BUFFERS_DWordLength_bits 8 #define GFX4_3DSTATE_VERTEX_BUFFERS_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VERTEX_BUFFERS_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 8; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VERTEX_BUFFERS_DWordLength_start 0 #define GFX12_3DSTATE_VERTEX_BUFFERS_DWordLength_start 0 #define GFX11_3DSTATE_VERTEX_BUFFERS_DWordLength_start 0 #define GFX9_3DSTATE_VERTEX_BUFFERS_DWordLength_start 0 #define GFX8_3DSTATE_VERTEX_BUFFERS_DWordLength_start 0 #define GFX75_3DSTATE_VERTEX_BUFFERS_DWordLength_start 0 #define GFX7_3DSTATE_VERTEX_BUFFERS_DWordLength_start 0 #define GFX6_3DSTATE_VERTEX_BUFFERS_DWordLength_start 0 #define GFX5_3DSTATE_VERTEX_BUFFERS_DWordLength_start 0 #define GFX45_3DSTATE_VERTEX_BUFFERS_DWordLength_start 0 #define GFX4_3DSTATE_VERTEX_BUFFERS_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VERTEX_BUFFERS_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VERTEX_ELEMENTS */ /* 3DSTATE_VERTEX_ELEMENTS::3D Command Opcode */ #define GFX125_3DSTATE_VERTEX_ELEMENTS_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_VERTEX_ELEMENTS_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_VERTEX_ELEMENTS_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_VERTEX_ELEMENTS_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_VERTEX_ELEMENTS_3DCommandOpcode_bits 3 #define GFX75_3DSTATE_VERTEX_ELEMENTS_3DCommandOpcode_bits 3 #define GFX7_3DSTATE_VERTEX_ELEMENTS_3DCommandOpcode_bits 3 #define GFX6_3DSTATE_VERTEX_ELEMENTS_3DCommandOpcode_bits 3 #define GFX5_3DSTATE_VERTEX_ELEMENTS_3DCommandOpcode_bits 3 #define GFX45_3DSTATE_VERTEX_ELEMENTS_3DCommandOpcode_bits 3 #define GFX4_3DSTATE_VERTEX_ELEMENTS_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VERTEX_ELEMENTS_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VERTEX_ELEMENTS_3DCommandOpcode_start 24 #define GFX12_3DSTATE_VERTEX_ELEMENTS_3DCommandOpcode_start 24 #define GFX11_3DSTATE_VERTEX_ELEMENTS_3DCommandOpcode_start 24 #define GFX9_3DSTATE_VERTEX_ELEMENTS_3DCommandOpcode_start 24 #define GFX8_3DSTATE_VERTEX_ELEMENTS_3DCommandOpcode_start 24 #define GFX75_3DSTATE_VERTEX_ELEMENTS_3DCommandOpcode_start 24 #define GFX7_3DSTATE_VERTEX_ELEMENTS_3DCommandOpcode_start 24 #define GFX6_3DSTATE_VERTEX_ELEMENTS_3DCommandOpcode_start 24 #define GFX5_3DSTATE_VERTEX_ELEMENTS_3DCommandOpcode_start 24 #define GFX45_3DSTATE_VERTEX_ELEMENTS_3DCommandOpcode_start 24 #define GFX4_3DSTATE_VERTEX_ELEMENTS_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VERTEX_ELEMENTS_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 24; case 50: return 24; case 45: return 24; case 40: return 24; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VERTEX_ELEMENTS::3D Command Sub Opcode */ #define GFX125_3DSTATE_VERTEX_ELEMENTS_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_VERTEX_ELEMENTS_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_VERTEX_ELEMENTS_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_VERTEX_ELEMENTS_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_VERTEX_ELEMENTS_3DCommandSubOpcode_bits 8 #define GFX75_3DSTATE_VERTEX_ELEMENTS_3DCommandSubOpcode_bits 8 #define GFX7_3DSTATE_VERTEX_ELEMENTS_3DCommandSubOpcode_bits 8 #define GFX6_3DSTATE_VERTEX_ELEMENTS_3DCommandSubOpcode_bits 8 #define GFX5_3DSTATE_VERTEX_ELEMENTS_3DCommandSubOpcode_bits 8 #define GFX45_3DSTATE_VERTEX_ELEMENTS_3DCommandSubOpcode_bits 8 #define GFX4_3DSTATE_VERTEX_ELEMENTS_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VERTEX_ELEMENTS_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 8; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VERTEX_ELEMENTS_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_VERTEX_ELEMENTS_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_VERTEX_ELEMENTS_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_VERTEX_ELEMENTS_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_VERTEX_ELEMENTS_3DCommandSubOpcode_start 16 #define GFX75_3DSTATE_VERTEX_ELEMENTS_3DCommandSubOpcode_start 16 #define GFX7_3DSTATE_VERTEX_ELEMENTS_3DCommandSubOpcode_start 16 #define GFX6_3DSTATE_VERTEX_ELEMENTS_3DCommandSubOpcode_start 16 #define GFX5_3DSTATE_VERTEX_ELEMENTS_3DCommandSubOpcode_start 16 #define GFX45_3DSTATE_VERTEX_ELEMENTS_3DCommandSubOpcode_start 16 #define GFX4_3DSTATE_VERTEX_ELEMENTS_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VERTEX_ELEMENTS_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 16; case 50: return 16; case 45: return 16; case 40: return 16; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VERTEX_ELEMENTS::Command SubType */ #define GFX125_3DSTATE_VERTEX_ELEMENTS_CommandSubType_bits 2 #define GFX12_3DSTATE_VERTEX_ELEMENTS_CommandSubType_bits 2 #define GFX11_3DSTATE_VERTEX_ELEMENTS_CommandSubType_bits 2 #define GFX9_3DSTATE_VERTEX_ELEMENTS_CommandSubType_bits 2 #define GFX8_3DSTATE_VERTEX_ELEMENTS_CommandSubType_bits 2 #define GFX75_3DSTATE_VERTEX_ELEMENTS_CommandSubType_bits 2 #define GFX7_3DSTATE_VERTEX_ELEMENTS_CommandSubType_bits 2 #define GFX6_3DSTATE_VERTEX_ELEMENTS_CommandSubType_bits 2 #define GFX5_3DSTATE_VERTEX_ELEMENTS_CommandSubType_bits 2 #define GFX45_3DSTATE_VERTEX_ELEMENTS_CommandSubType_bits 2 #define GFX4_3DSTATE_VERTEX_ELEMENTS_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VERTEX_ELEMENTS_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 2; case 45: return 2; case 40: return 2; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VERTEX_ELEMENTS_CommandSubType_start 27 #define GFX12_3DSTATE_VERTEX_ELEMENTS_CommandSubType_start 27 #define GFX11_3DSTATE_VERTEX_ELEMENTS_CommandSubType_start 27 #define GFX9_3DSTATE_VERTEX_ELEMENTS_CommandSubType_start 27 #define GFX8_3DSTATE_VERTEX_ELEMENTS_CommandSubType_start 27 #define GFX75_3DSTATE_VERTEX_ELEMENTS_CommandSubType_start 27 #define GFX7_3DSTATE_VERTEX_ELEMENTS_CommandSubType_start 27 #define GFX6_3DSTATE_VERTEX_ELEMENTS_CommandSubType_start 27 #define GFX5_3DSTATE_VERTEX_ELEMENTS_CommandSubType_start 27 #define GFX45_3DSTATE_VERTEX_ELEMENTS_CommandSubType_start 27 #define GFX4_3DSTATE_VERTEX_ELEMENTS_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VERTEX_ELEMENTS_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 27; case 50: return 27; case 45: return 27; case 40: return 27; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VERTEX_ELEMENTS::Command Type */ #define GFX125_3DSTATE_VERTEX_ELEMENTS_CommandType_bits 3 #define GFX12_3DSTATE_VERTEX_ELEMENTS_CommandType_bits 3 #define GFX11_3DSTATE_VERTEX_ELEMENTS_CommandType_bits 3 #define GFX9_3DSTATE_VERTEX_ELEMENTS_CommandType_bits 3 #define GFX8_3DSTATE_VERTEX_ELEMENTS_CommandType_bits 3 #define GFX75_3DSTATE_VERTEX_ELEMENTS_CommandType_bits 3 #define GFX7_3DSTATE_VERTEX_ELEMENTS_CommandType_bits 3 #define GFX6_3DSTATE_VERTEX_ELEMENTS_CommandType_bits 3 #define GFX5_3DSTATE_VERTEX_ELEMENTS_CommandType_bits 3 #define GFX45_3DSTATE_VERTEX_ELEMENTS_CommandType_bits 3 #define GFX4_3DSTATE_VERTEX_ELEMENTS_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VERTEX_ELEMENTS_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VERTEX_ELEMENTS_CommandType_start 29 #define GFX12_3DSTATE_VERTEX_ELEMENTS_CommandType_start 29 #define GFX11_3DSTATE_VERTEX_ELEMENTS_CommandType_start 29 #define GFX9_3DSTATE_VERTEX_ELEMENTS_CommandType_start 29 #define GFX8_3DSTATE_VERTEX_ELEMENTS_CommandType_start 29 #define GFX75_3DSTATE_VERTEX_ELEMENTS_CommandType_start 29 #define GFX7_3DSTATE_VERTEX_ELEMENTS_CommandType_start 29 #define GFX6_3DSTATE_VERTEX_ELEMENTS_CommandType_start 29 #define GFX5_3DSTATE_VERTEX_ELEMENTS_CommandType_start 29 #define GFX45_3DSTATE_VERTEX_ELEMENTS_CommandType_start 29 #define GFX4_3DSTATE_VERTEX_ELEMENTS_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VERTEX_ELEMENTS_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 29; case 50: return 29; case 45: return 29; case 40: return 29; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VERTEX_ELEMENTS::DWord Length */ #define GFX125_3DSTATE_VERTEX_ELEMENTS_DWordLength_bits 8 #define GFX12_3DSTATE_VERTEX_ELEMENTS_DWordLength_bits 8 #define GFX11_3DSTATE_VERTEX_ELEMENTS_DWordLength_bits 8 #define GFX9_3DSTATE_VERTEX_ELEMENTS_DWordLength_bits 8 #define GFX8_3DSTATE_VERTEX_ELEMENTS_DWordLength_bits 8 #define GFX75_3DSTATE_VERTEX_ELEMENTS_DWordLength_bits 8 #define GFX7_3DSTATE_VERTEX_ELEMENTS_DWordLength_bits 8 #define GFX6_3DSTATE_VERTEX_ELEMENTS_DWordLength_bits 8 #define GFX5_3DSTATE_VERTEX_ELEMENTS_DWordLength_bits 8 #define GFX45_3DSTATE_VERTEX_ELEMENTS_DWordLength_bits 8 #define GFX4_3DSTATE_VERTEX_ELEMENTS_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VERTEX_ELEMENTS_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 8; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VERTEX_ELEMENTS_DWordLength_start 0 #define GFX12_3DSTATE_VERTEX_ELEMENTS_DWordLength_start 0 #define GFX11_3DSTATE_VERTEX_ELEMENTS_DWordLength_start 0 #define GFX9_3DSTATE_VERTEX_ELEMENTS_DWordLength_start 0 #define GFX8_3DSTATE_VERTEX_ELEMENTS_DWordLength_start 0 #define GFX75_3DSTATE_VERTEX_ELEMENTS_DWordLength_start 0 #define GFX7_3DSTATE_VERTEX_ELEMENTS_DWordLength_start 0 #define GFX6_3DSTATE_VERTEX_ELEMENTS_DWordLength_start 0 #define GFX5_3DSTATE_VERTEX_ELEMENTS_DWordLength_start 0 #define GFX45_3DSTATE_VERTEX_ELEMENTS_DWordLength_start 0 #define GFX4_3DSTATE_VERTEX_ELEMENTS_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VERTEX_ELEMENTS_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF */ #define GFX125_3DSTATE_VF_length 2 #define GFX12_3DSTATE_VF_length 2 #define GFX11_3DSTATE_VF_length 2 #define GFX9_3DSTATE_VF_length 2 #define GFX8_3DSTATE_VF_length 2 #define GFX75_3DSTATE_VF_length 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF::3D Command Opcode */ #define GFX125_3DSTATE_VF_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_VF_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_VF_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_VF_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_VF_3DCommandOpcode_bits 3 #define GFX75_3DSTATE_VF_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_3DCommandOpcode_start 24 #define GFX12_3DSTATE_VF_3DCommandOpcode_start 24 #define GFX11_3DSTATE_VF_3DCommandOpcode_start 24 #define GFX9_3DSTATE_VF_3DCommandOpcode_start 24 #define GFX8_3DSTATE_VF_3DCommandOpcode_start 24 #define GFX75_3DSTATE_VF_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF::3D Command Sub Opcode */ #define GFX125_3DSTATE_VF_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_VF_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_VF_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_VF_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_VF_3DCommandSubOpcode_bits 8 #define GFX75_3DSTATE_VF_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_VF_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_VF_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_VF_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_VF_3DCommandSubOpcode_start 16 #define GFX75_3DSTATE_VF_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF::Command SubType */ #define GFX125_3DSTATE_VF_CommandSubType_bits 2 #define GFX12_3DSTATE_VF_CommandSubType_bits 2 #define GFX11_3DSTATE_VF_CommandSubType_bits 2 #define GFX9_3DSTATE_VF_CommandSubType_bits 2 #define GFX8_3DSTATE_VF_CommandSubType_bits 2 #define GFX75_3DSTATE_VF_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_CommandSubType_start 27 #define GFX12_3DSTATE_VF_CommandSubType_start 27 #define GFX11_3DSTATE_VF_CommandSubType_start 27 #define GFX9_3DSTATE_VF_CommandSubType_start 27 #define GFX8_3DSTATE_VF_CommandSubType_start 27 #define GFX75_3DSTATE_VF_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF::Command Type */ #define GFX125_3DSTATE_VF_CommandType_bits 3 #define GFX12_3DSTATE_VF_CommandType_bits 3 #define GFX11_3DSTATE_VF_CommandType_bits 3 #define GFX9_3DSTATE_VF_CommandType_bits 3 #define GFX8_3DSTATE_VF_CommandType_bits 3 #define GFX75_3DSTATE_VF_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_CommandType_start 29 #define GFX12_3DSTATE_VF_CommandType_start 29 #define GFX11_3DSTATE_VF_CommandType_start 29 #define GFX9_3DSTATE_VF_CommandType_start 29 #define GFX8_3DSTATE_VF_CommandType_start 29 #define GFX75_3DSTATE_VF_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF::Component Packing Enable */ #define GFX125_3DSTATE_VF_ComponentPackingEnable_bits 1 #define GFX12_3DSTATE_VF_ComponentPackingEnable_bits 1 #define GFX11_3DSTATE_VF_ComponentPackingEnable_bits 1 #define GFX9_3DSTATE_VF_ComponentPackingEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_ComponentPackingEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_ComponentPackingEnable_start 9 #define GFX12_3DSTATE_VF_ComponentPackingEnable_start 9 #define GFX11_3DSTATE_VF_ComponentPackingEnable_start 9 #define GFX9_3DSTATE_VF_ComponentPackingEnable_start 9 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_ComponentPackingEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 9; case 120: return 9; case 110: return 9; case 90: return 9; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF::Cut Index */ #define GFX125_3DSTATE_VF_CutIndex_bits 32 #define GFX12_3DSTATE_VF_CutIndex_bits 32 #define GFX11_3DSTATE_VF_CutIndex_bits 32 #define GFX9_3DSTATE_VF_CutIndex_bits 32 #define GFX8_3DSTATE_VF_CutIndex_bits 32 #define GFX75_3DSTATE_VF_CutIndex_bits 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_CutIndex_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_CutIndex_start 32 #define GFX12_3DSTATE_VF_CutIndex_start 32 #define GFX11_3DSTATE_VF_CutIndex_start 32 #define GFX9_3DSTATE_VF_CutIndex_start 32 #define GFX8_3DSTATE_VF_CutIndex_start 32 #define GFX75_3DSTATE_VF_CutIndex_start 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_CutIndex_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF::DWord Length */ #define GFX125_3DSTATE_VF_DWordLength_bits 8 #define GFX12_3DSTATE_VF_DWordLength_bits 8 #define GFX11_3DSTATE_VF_DWordLength_bits 8 #define GFX9_3DSTATE_VF_DWordLength_bits 8 #define GFX8_3DSTATE_VF_DWordLength_bits 8 #define GFX75_3DSTATE_VF_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_DWordLength_start 0 #define GFX12_3DSTATE_VF_DWordLength_start 0 #define GFX11_3DSTATE_VF_DWordLength_start 0 #define GFX9_3DSTATE_VF_DWordLength_start 0 #define GFX8_3DSTATE_VF_DWordLength_start 0 #define GFX75_3DSTATE_VF_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF::Indexed Draw Cut Index Enable */ #define GFX125_3DSTATE_VF_IndexedDrawCutIndexEnable_bits 1 #define GFX12_3DSTATE_VF_IndexedDrawCutIndexEnable_bits 1 #define GFX11_3DSTATE_VF_IndexedDrawCutIndexEnable_bits 1 #define GFX9_3DSTATE_VF_IndexedDrawCutIndexEnable_bits 1 #define GFX8_3DSTATE_VF_IndexedDrawCutIndexEnable_bits 1 #define GFX75_3DSTATE_VF_IndexedDrawCutIndexEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_IndexedDrawCutIndexEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_IndexedDrawCutIndexEnable_start 8 #define GFX12_3DSTATE_VF_IndexedDrawCutIndexEnable_start 8 #define GFX11_3DSTATE_VF_IndexedDrawCutIndexEnable_start 8 #define GFX9_3DSTATE_VF_IndexedDrawCutIndexEnable_start 8 #define GFX8_3DSTATE_VF_IndexedDrawCutIndexEnable_start 8 #define GFX75_3DSTATE_VF_IndexedDrawCutIndexEnable_start 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_IndexedDrawCutIndexEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF::Sequential Draw Cut Index Enable */ #define GFX125_3DSTATE_VF_SequentialDrawCutIndexEnable_bits 1 #define GFX12_3DSTATE_VF_SequentialDrawCutIndexEnable_bits 1 #define GFX11_3DSTATE_VF_SequentialDrawCutIndexEnable_bits 1 #define GFX9_3DSTATE_VF_SequentialDrawCutIndexEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_SequentialDrawCutIndexEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_SequentialDrawCutIndexEnable_start 10 #define GFX12_3DSTATE_VF_SequentialDrawCutIndexEnable_start 10 #define GFX11_3DSTATE_VF_SequentialDrawCutIndexEnable_start 10 #define GFX9_3DSTATE_VF_SequentialDrawCutIndexEnable_start 10 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_SequentialDrawCutIndexEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 10; case 120: return 10; case 110: return 10; case 90: return 10; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF::VertexID Offset Enable */ #define GFX125_3DSTATE_VF_VertexIDOffsetEnable_bits 1 #define GFX12_3DSTATE_VF_VertexIDOffsetEnable_bits 1 #define GFX11_3DSTATE_VF_VertexIDOffsetEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_VertexIDOffsetEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_VertexIDOffsetEnable_start 11 #define GFX12_3DSTATE_VF_VertexIDOffsetEnable_start 11 #define GFX11_3DSTATE_VF_VertexIDOffsetEnable_start 11 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_VertexIDOffsetEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 11; case 120: return 11; case 110: return 11; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_COMPONENT_PACKING */ #define GFX125_3DSTATE_VF_COMPONENT_PACKING_length 5 #define GFX12_3DSTATE_VF_COMPONENT_PACKING_length 5 #define GFX11_3DSTATE_VF_COMPONENT_PACKING_length 5 #define GFX9_3DSTATE_VF_COMPONENT_PACKING_length 5 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_COMPONENT_PACKING_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 5; case 110: return 5; case 90: return 5; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_COMPONENT_PACKING::3D Command Opcode */ #define GFX125_3DSTATE_VF_COMPONENT_PACKING_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_VF_COMPONENT_PACKING_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_VF_COMPONENT_PACKING_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_VF_COMPONENT_PACKING_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_COMPONENT_PACKING_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_COMPONENT_PACKING_3DCommandOpcode_start 24 #define GFX12_3DSTATE_VF_COMPONENT_PACKING_3DCommandOpcode_start 24 #define GFX11_3DSTATE_VF_COMPONENT_PACKING_3DCommandOpcode_start 24 #define GFX9_3DSTATE_VF_COMPONENT_PACKING_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_COMPONENT_PACKING_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_COMPONENT_PACKING::3D Command Sub Opcode */ #define GFX125_3DSTATE_VF_COMPONENT_PACKING_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_VF_COMPONENT_PACKING_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_VF_COMPONENT_PACKING_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_VF_COMPONENT_PACKING_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_COMPONENT_PACKING_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_COMPONENT_PACKING_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_VF_COMPONENT_PACKING_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_VF_COMPONENT_PACKING_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_VF_COMPONENT_PACKING_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_COMPONENT_PACKING_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_COMPONENT_PACKING::Command SubType */ #define GFX125_3DSTATE_VF_COMPONENT_PACKING_CommandSubType_bits 2 #define GFX12_3DSTATE_VF_COMPONENT_PACKING_CommandSubType_bits 2 #define GFX11_3DSTATE_VF_COMPONENT_PACKING_CommandSubType_bits 2 #define GFX9_3DSTATE_VF_COMPONENT_PACKING_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_COMPONENT_PACKING_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_COMPONENT_PACKING_CommandSubType_start 27 #define GFX12_3DSTATE_VF_COMPONENT_PACKING_CommandSubType_start 27 #define GFX11_3DSTATE_VF_COMPONENT_PACKING_CommandSubType_start 27 #define GFX9_3DSTATE_VF_COMPONENT_PACKING_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_COMPONENT_PACKING_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_COMPONENT_PACKING::Command Type */ #define GFX125_3DSTATE_VF_COMPONENT_PACKING_CommandType_bits 3 #define GFX12_3DSTATE_VF_COMPONENT_PACKING_CommandType_bits 3 #define GFX11_3DSTATE_VF_COMPONENT_PACKING_CommandType_bits 3 #define GFX9_3DSTATE_VF_COMPONENT_PACKING_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_COMPONENT_PACKING_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_COMPONENT_PACKING_CommandType_start 29 #define GFX12_3DSTATE_VF_COMPONENT_PACKING_CommandType_start 29 #define GFX11_3DSTATE_VF_COMPONENT_PACKING_CommandType_start 29 #define GFX9_3DSTATE_VF_COMPONENT_PACKING_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_COMPONENT_PACKING_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_COMPONENT_PACKING::DWord Length */ #define GFX125_3DSTATE_VF_COMPONENT_PACKING_DWordLength_bits 8 #define GFX12_3DSTATE_VF_COMPONENT_PACKING_DWordLength_bits 8 #define GFX11_3DSTATE_VF_COMPONENT_PACKING_DWordLength_bits 8 #define GFX9_3DSTATE_VF_COMPONENT_PACKING_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_COMPONENT_PACKING_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_COMPONENT_PACKING_DWordLength_start 0 #define GFX12_3DSTATE_VF_COMPONENT_PACKING_DWordLength_start 0 #define GFX11_3DSTATE_VF_COMPONENT_PACKING_DWordLength_start 0 #define GFX9_3DSTATE_VF_COMPONENT_PACKING_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_COMPONENT_PACKING_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_COMPONENT_PACKING::Vertex Element 00 Enables */ #define GFX125_3DSTATE_VF_COMPONENT_PACKING_VertexElement00Enables_bits 4 #define GFX12_3DSTATE_VF_COMPONENT_PACKING_VertexElement00Enables_bits 4 #define GFX11_3DSTATE_VF_COMPONENT_PACKING_VertexElement00Enables_bits 4 #define GFX9_3DSTATE_VF_COMPONENT_PACKING_VertexElement00Enables_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_COMPONENT_PACKING_VertexElement00Enables_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_COMPONENT_PACKING_VertexElement00Enables_start 32 #define GFX12_3DSTATE_VF_COMPONENT_PACKING_VertexElement00Enables_start 32 #define GFX11_3DSTATE_VF_COMPONENT_PACKING_VertexElement00Enables_start 32 #define GFX9_3DSTATE_VF_COMPONENT_PACKING_VertexElement00Enables_start 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_COMPONENT_PACKING_VertexElement00Enables_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_COMPONENT_PACKING::Vertex Element 01 Enables */ #define GFX125_3DSTATE_VF_COMPONENT_PACKING_VertexElement01Enables_bits 4 #define GFX12_3DSTATE_VF_COMPONENT_PACKING_VertexElement01Enables_bits 4 #define GFX11_3DSTATE_VF_COMPONENT_PACKING_VertexElement01Enables_bits 4 #define GFX9_3DSTATE_VF_COMPONENT_PACKING_VertexElement01Enables_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_COMPONENT_PACKING_VertexElement01Enables_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_COMPONENT_PACKING_VertexElement01Enables_start 36 #define GFX12_3DSTATE_VF_COMPONENT_PACKING_VertexElement01Enables_start 36 #define GFX11_3DSTATE_VF_COMPONENT_PACKING_VertexElement01Enables_start 36 #define GFX9_3DSTATE_VF_COMPONENT_PACKING_VertexElement01Enables_start 36 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_COMPONENT_PACKING_VertexElement01Enables_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 36; case 120: return 36; case 110: return 36; case 90: return 36; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_COMPONENT_PACKING::Vertex Element 02 Enables */ #define GFX125_3DSTATE_VF_COMPONENT_PACKING_VertexElement02Enables_bits 4 #define GFX12_3DSTATE_VF_COMPONENT_PACKING_VertexElement02Enables_bits 4 #define GFX11_3DSTATE_VF_COMPONENT_PACKING_VertexElement02Enables_bits 4 #define GFX9_3DSTATE_VF_COMPONENT_PACKING_VertexElement02Enables_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_COMPONENT_PACKING_VertexElement02Enables_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_COMPONENT_PACKING_VertexElement02Enables_start 40 #define GFX12_3DSTATE_VF_COMPONENT_PACKING_VertexElement02Enables_start 40 #define GFX11_3DSTATE_VF_COMPONENT_PACKING_VertexElement02Enables_start 40 #define GFX9_3DSTATE_VF_COMPONENT_PACKING_VertexElement02Enables_start 40 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_COMPONENT_PACKING_VertexElement02Enables_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 40; case 120: return 40; case 110: return 40; case 90: return 40; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_COMPONENT_PACKING::Vertex Element 03 Enables */ #define GFX125_3DSTATE_VF_COMPONENT_PACKING_VertexElement03Enables_bits 4 #define GFX12_3DSTATE_VF_COMPONENT_PACKING_VertexElement03Enables_bits 4 #define GFX11_3DSTATE_VF_COMPONENT_PACKING_VertexElement03Enables_bits 4 #define GFX9_3DSTATE_VF_COMPONENT_PACKING_VertexElement03Enables_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_COMPONENT_PACKING_VertexElement03Enables_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_COMPONENT_PACKING_VertexElement03Enables_start 44 #define GFX12_3DSTATE_VF_COMPONENT_PACKING_VertexElement03Enables_start 44 #define GFX11_3DSTATE_VF_COMPONENT_PACKING_VertexElement03Enables_start 44 #define GFX9_3DSTATE_VF_COMPONENT_PACKING_VertexElement03Enables_start 44 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_COMPONENT_PACKING_VertexElement03Enables_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 44; case 120: return 44; case 110: return 44; case 90: return 44; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_COMPONENT_PACKING::Vertex Element 04 Enables */ #define GFX125_3DSTATE_VF_COMPONENT_PACKING_VertexElement04Enables_bits 4 #define GFX12_3DSTATE_VF_COMPONENT_PACKING_VertexElement04Enables_bits 4 #define GFX11_3DSTATE_VF_COMPONENT_PACKING_VertexElement04Enables_bits 4 #define GFX9_3DSTATE_VF_COMPONENT_PACKING_VertexElement04Enables_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_COMPONENT_PACKING_VertexElement04Enables_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_COMPONENT_PACKING_VertexElement04Enables_start 48 #define GFX12_3DSTATE_VF_COMPONENT_PACKING_VertexElement04Enables_start 48 #define GFX11_3DSTATE_VF_COMPONENT_PACKING_VertexElement04Enables_start 48 #define GFX9_3DSTATE_VF_COMPONENT_PACKING_VertexElement04Enables_start 48 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_COMPONENT_PACKING_VertexElement04Enables_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 48; case 120: return 48; case 110: return 48; case 90: return 48; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_COMPONENT_PACKING::Vertex Element 05 Enables */ #define GFX125_3DSTATE_VF_COMPONENT_PACKING_VertexElement05Enables_bits 4 #define GFX12_3DSTATE_VF_COMPONENT_PACKING_VertexElement05Enables_bits 4 #define GFX11_3DSTATE_VF_COMPONENT_PACKING_VertexElement05Enables_bits 4 #define GFX9_3DSTATE_VF_COMPONENT_PACKING_VertexElement05Enables_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_COMPONENT_PACKING_VertexElement05Enables_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_COMPONENT_PACKING_VertexElement05Enables_start 52 #define GFX12_3DSTATE_VF_COMPONENT_PACKING_VertexElement05Enables_start 52 #define GFX11_3DSTATE_VF_COMPONENT_PACKING_VertexElement05Enables_start 52 #define GFX9_3DSTATE_VF_COMPONENT_PACKING_VertexElement05Enables_start 52 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_COMPONENT_PACKING_VertexElement05Enables_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 52; case 120: return 52; case 110: return 52; case 90: return 52; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_COMPONENT_PACKING::Vertex Element 06 Enables */ #define GFX125_3DSTATE_VF_COMPONENT_PACKING_VertexElement06Enables_bits 4 #define GFX12_3DSTATE_VF_COMPONENT_PACKING_VertexElement06Enables_bits 4 #define GFX11_3DSTATE_VF_COMPONENT_PACKING_VertexElement06Enables_bits 4 #define GFX9_3DSTATE_VF_COMPONENT_PACKING_VertexElement06Enables_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_COMPONENT_PACKING_VertexElement06Enables_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_COMPONENT_PACKING_VertexElement06Enables_start 56 #define GFX12_3DSTATE_VF_COMPONENT_PACKING_VertexElement06Enables_start 56 #define GFX11_3DSTATE_VF_COMPONENT_PACKING_VertexElement06Enables_start 56 #define GFX9_3DSTATE_VF_COMPONENT_PACKING_VertexElement06Enables_start 56 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_COMPONENT_PACKING_VertexElement06Enables_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 56; case 120: return 56; case 110: return 56; case 90: return 56; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_COMPONENT_PACKING::Vertex Element 07 Enables */ #define GFX125_3DSTATE_VF_COMPONENT_PACKING_VertexElement07Enables_bits 4 #define GFX12_3DSTATE_VF_COMPONENT_PACKING_VertexElement07Enables_bits 4 #define GFX11_3DSTATE_VF_COMPONENT_PACKING_VertexElement07Enables_bits 4 #define GFX9_3DSTATE_VF_COMPONENT_PACKING_VertexElement07Enables_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_COMPONENT_PACKING_VertexElement07Enables_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_COMPONENT_PACKING_VertexElement07Enables_start 60 #define GFX12_3DSTATE_VF_COMPONENT_PACKING_VertexElement07Enables_start 60 #define GFX11_3DSTATE_VF_COMPONENT_PACKING_VertexElement07Enables_start 60 #define GFX9_3DSTATE_VF_COMPONENT_PACKING_VertexElement07Enables_start 60 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_COMPONENT_PACKING_VertexElement07Enables_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 60; case 120: return 60; case 110: return 60; case 90: return 60; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_COMPONENT_PACKING::Vertex Element 08 Enables */ #define GFX125_3DSTATE_VF_COMPONENT_PACKING_VertexElement08Enables_bits 4 #define GFX12_3DSTATE_VF_COMPONENT_PACKING_VertexElement08Enables_bits 4 #define GFX11_3DSTATE_VF_COMPONENT_PACKING_VertexElement08Enables_bits 4 #define GFX9_3DSTATE_VF_COMPONENT_PACKING_VertexElement08Enables_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_COMPONENT_PACKING_VertexElement08Enables_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_COMPONENT_PACKING_VertexElement08Enables_start 64 #define GFX12_3DSTATE_VF_COMPONENT_PACKING_VertexElement08Enables_start 64 #define GFX11_3DSTATE_VF_COMPONENT_PACKING_VertexElement08Enables_start 64 #define GFX9_3DSTATE_VF_COMPONENT_PACKING_VertexElement08Enables_start 64 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_COMPONENT_PACKING_VertexElement08Enables_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 64; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_COMPONENT_PACKING::Vertex Element 09 Enables */ #define GFX125_3DSTATE_VF_COMPONENT_PACKING_VertexElement09Enables_bits 4 #define GFX12_3DSTATE_VF_COMPONENT_PACKING_VertexElement09Enables_bits 4 #define GFX11_3DSTATE_VF_COMPONENT_PACKING_VertexElement09Enables_bits 4 #define GFX9_3DSTATE_VF_COMPONENT_PACKING_VertexElement09Enables_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_COMPONENT_PACKING_VertexElement09Enables_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_COMPONENT_PACKING_VertexElement09Enables_start 68 #define GFX12_3DSTATE_VF_COMPONENT_PACKING_VertexElement09Enables_start 68 #define GFX11_3DSTATE_VF_COMPONENT_PACKING_VertexElement09Enables_start 68 #define GFX9_3DSTATE_VF_COMPONENT_PACKING_VertexElement09Enables_start 68 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_COMPONENT_PACKING_VertexElement09Enables_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 68; case 120: return 68; case 110: return 68; case 90: return 68; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_COMPONENT_PACKING::Vertex Element 10 Enables */ #define GFX125_3DSTATE_VF_COMPONENT_PACKING_VertexElement10Enables_bits 4 #define GFX12_3DSTATE_VF_COMPONENT_PACKING_VertexElement10Enables_bits 4 #define GFX11_3DSTATE_VF_COMPONENT_PACKING_VertexElement10Enables_bits 4 #define GFX9_3DSTATE_VF_COMPONENT_PACKING_VertexElement10Enables_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_COMPONENT_PACKING_VertexElement10Enables_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_COMPONENT_PACKING_VertexElement10Enables_start 72 #define GFX12_3DSTATE_VF_COMPONENT_PACKING_VertexElement10Enables_start 72 #define GFX11_3DSTATE_VF_COMPONENT_PACKING_VertexElement10Enables_start 72 #define GFX9_3DSTATE_VF_COMPONENT_PACKING_VertexElement10Enables_start 72 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_COMPONENT_PACKING_VertexElement10Enables_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 72; case 120: return 72; case 110: return 72; case 90: return 72; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_COMPONENT_PACKING::Vertex Element 11 Enables */ #define GFX125_3DSTATE_VF_COMPONENT_PACKING_VertexElement11Enables_bits 4 #define GFX12_3DSTATE_VF_COMPONENT_PACKING_VertexElement11Enables_bits 4 #define GFX11_3DSTATE_VF_COMPONENT_PACKING_VertexElement11Enables_bits 4 #define GFX9_3DSTATE_VF_COMPONENT_PACKING_VertexElement11Enables_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_COMPONENT_PACKING_VertexElement11Enables_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_COMPONENT_PACKING_VertexElement11Enables_start 76 #define GFX12_3DSTATE_VF_COMPONENT_PACKING_VertexElement11Enables_start 76 #define GFX11_3DSTATE_VF_COMPONENT_PACKING_VertexElement11Enables_start 76 #define GFX9_3DSTATE_VF_COMPONENT_PACKING_VertexElement11Enables_start 76 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_COMPONENT_PACKING_VertexElement11Enables_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 76; case 120: return 76; case 110: return 76; case 90: return 76; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_COMPONENT_PACKING::Vertex Element 12 Enables */ #define GFX125_3DSTATE_VF_COMPONENT_PACKING_VertexElement12Enables_bits 4 #define GFX12_3DSTATE_VF_COMPONENT_PACKING_VertexElement12Enables_bits 4 #define GFX11_3DSTATE_VF_COMPONENT_PACKING_VertexElement12Enables_bits 4 #define GFX9_3DSTATE_VF_COMPONENT_PACKING_VertexElement12Enables_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_COMPONENT_PACKING_VertexElement12Enables_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_COMPONENT_PACKING_VertexElement12Enables_start 80 #define GFX12_3DSTATE_VF_COMPONENT_PACKING_VertexElement12Enables_start 80 #define GFX11_3DSTATE_VF_COMPONENT_PACKING_VertexElement12Enables_start 80 #define GFX9_3DSTATE_VF_COMPONENT_PACKING_VertexElement12Enables_start 80 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_COMPONENT_PACKING_VertexElement12Enables_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 80; case 120: return 80; case 110: return 80; case 90: return 80; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_COMPONENT_PACKING::Vertex Element 13 Enables */ #define GFX125_3DSTATE_VF_COMPONENT_PACKING_VertexElement13Enables_bits 4 #define GFX12_3DSTATE_VF_COMPONENT_PACKING_VertexElement13Enables_bits 4 #define GFX11_3DSTATE_VF_COMPONENT_PACKING_VertexElement13Enables_bits 4 #define GFX9_3DSTATE_VF_COMPONENT_PACKING_VertexElement13Enables_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_COMPONENT_PACKING_VertexElement13Enables_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_COMPONENT_PACKING_VertexElement13Enables_start 84 #define GFX12_3DSTATE_VF_COMPONENT_PACKING_VertexElement13Enables_start 84 #define GFX11_3DSTATE_VF_COMPONENT_PACKING_VertexElement13Enables_start 84 #define GFX9_3DSTATE_VF_COMPONENT_PACKING_VertexElement13Enables_start 84 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_COMPONENT_PACKING_VertexElement13Enables_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 84; case 120: return 84; case 110: return 84; case 90: return 84; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_COMPONENT_PACKING::Vertex Element 14 Enables */ #define GFX125_3DSTATE_VF_COMPONENT_PACKING_VertexElement14Enables_bits 4 #define GFX12_3DSTATE_VF_COMPONENT_PACKING_VertexElement14Enables_bits 4 #define GFX11_3DSTATE_VF_COMPONENT_PACKING_VertexElement14Enables_bits 4 #define GFX9_3DSTATE_VF_COMPONENT_PACKING_VertexElement14Enables_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_COMPONENT_PACKING_VertexElement14Enables_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_COMPONENT_PACKING_VertexElement14Enables_start 88 #define GFX12_3DSTATE_VF_COMPONENT_PACKING_VertexElement14Enables_start 88 #define GFX11_3DSTATE_VF_COMPONENT_PACKING_VertexElement14Enables_start 88 #define GFX9_3DSTATE_VF_COMPONENT_PACKING_VertexElement14Enables_start 88 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_COMPONENT_PACKING_VertexElement14Enables_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 88; case 120: return 88; case 110: return 88; case 90: return 88; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_COMPONENT_PACKING::Vertex Element 15 Enables */ #define GFX125_3DSTATE_VF_COMPONENT_PACKING_VertexElement15Enables_bits 4 #define GFX12_3DSTATE_VF_COMPONENT_PACKING_VertexElement15Enables_bits 4 #define GFX11_3DSTATE_VF_COMPONENT_PACKING_VertexElement15Enables_bits 4 #define GFX9_3DSTATE_VF_COMPONENT_PACKING_VertexElement15Enables_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_COMPONENT_PACKING_VertexElement15Enables_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_COMPONENT_PACKING_VertexElement15Enables_start 92 #define GFX12_3DSTATE_VF_COMPONENT_PACKING_VertexElement15Enables_start 92 #define GFX11_3DSTATE_VF_COMPONENT_PACKING_VertexElement15Enables_start 92 #define GFX9_3DSTATE_VF_COMPONENT_PACKING_VertexElement15Enables_start 92 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_COMPONENT_PACKING_VertexElement15Enables_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 92; case 120: return 92; case 110: return 92; case 90: return 92; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_COMPONENT_PACKING::Vertex Element 16 Enables */ #define GFX125_3DSTATE_VF_COMPONENT_PACKING_VertexElement16Enables_bits 4 #define GFX12_3DSTATE_VF_COMPONENT_PACKING_VertexElement16Enables_bits 4 #define GFX11_3DSTATE_VF_COMPONENT_PACKING_VertexElement16Enables_bits 4 #define GFX9_3DSTATE_VF_COMPONENT_PACKING_VertexElement16Enables_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_COMPONENT_PACKING_VertexElement16Enables_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_COMPONENT_PACKING_VertexElement16Enables_start 96 #define GFX12_3DSTATE_VF_COMPONENT_PACKING_VertexElement16Enables_start 96 #define GFX11_3DSTATE_VF_COMPONENT_PACKING_VertexElement16Enables_start 96 #define GFX9_3DSTATE_VF_COMPONENT_PACKING_VertexElement16Enables_start 96 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_COMPONENT_PACKING_VertexElement16Enables_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 96; case 120: return 96; case 110: return 96; case 90: return 96; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_COMPONENT_PACKING::Vertex Element 17 Enables */ #define GFX125_3DSTATE_VF_COMPONENT_PACKING_VertexElement17Enables_bits 4 #define GFX12_3DSTATE_VF_COMPONENT_PACKING_VertexElement17Enables_bits 4 #define GFX11_3DSTATE_VF_COMPONENT_PACKING_VertexElement17Enables_bits 4 #define GFX9_3DSTATE_VF_COMPONENT_PACKING_VertexElement17Enables_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_COMPONENT_PACKING_VertexElement17Enables_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_COMPONENT_PACKING_VertexElement17Enables_start 100 #define GFX12_3DSTATE_VF_COMPONENT_PACKING_VertexElement17Enables_start 100 #define GFX11_3DSTATE_VF_COMPONENT_PACKING_VertexElement17Enables_start 100 #define GFX9_3DSTATE_VF_COMPONENT_PACKING_VertexElement17Enables_start 100 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_COMPONENT_PACKING_VertexElement17Enables_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 100; case 120: return 100; case 110: return 100; case 90: return 100; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_COMPONENT_PACKING::Vertex Element 18 Enables */ #define GFX125_3DSTATE_VF_COMPONENT_PACKING_VertexElement18Enables_bits 4 #define GFX12_3DSTATE_VF_COMPONENT_PACKING_VertexElement18Enables_bits 4 #define GFX11_3DSTATE_VF_COMPONENT_PACKING_VertexElement18Enables_bits 4 #define GFX9_3DSTATE_VF_COMPONENT_PACKING_VertexElement18Enables_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_COMPONENT_PACKING_VertexElement18Enables_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_COMPONENT_PACKING_VertexElement18Enables_start 104 #define GFX12_3DSTATE_VF_COMPONENT_PACKING_VertexElement18Enables_start 104 #define GFX11_3DSTATE_VF_COMPONENT_PACKING_VertexElement18Enables_start 104 #define GFX9_3DSTATE_VF_COMPONENT_PACKING_VertexElement18Enables_start 104 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_COMPONENT_PACKING_VertexElement18Enables_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 104; case 120: return 104; case 110: return 104; case 90: return 104; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_COMPONENT_PACKING::Vertex Element 19 Enables */ #define GFX125_3DSTATE_VF_COMPONENT_PACKING_VertexElement19Enables_bits 4 #define GFX12_3DSTATE_VF_COMPONENT_PACKING_VertexElement19Enables_bits 4 #define GFX11_3DSTATE_VF_COMPONENT_PACKING_VertexElement19Enables_bits 4 #define GFX9_3DSTATE_VF_COMPONENT_PACKING_VertexElement19Enables_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_COMPONENT_PACKING_VertexElement19Enables_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_COMPONENT_PACKING_VertexElement19Enables_start 108 #define GFX12_3DSTATE_VF_COMPONENT_PACKING_VertexElement19Enables_start 108 #define GFX11_3DSTATE_VF_COMPONENT_PACKING_VertexElement19Enables_start 108 #define GFX9_3DSTATE_VF_COMPONENT_PACKING_VertexElement19Enables_start 108 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_COMPONENT_PACKING_VertexElement19Enables_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 108; case 120: return 108; case 110: return 108; case 90: return 108; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_COMPONENT_PACKING::Vertex Element 20 Enables */ #define GFX125_3DSTATE_VF_COMPONENT_PACKING_VertexElement20Enables_bits 4 #define GFX12_3DSTATE_VF_COMPONENT_PACKING_VertexElement20Enables_bits 4 #define GFX11_3DSTATE_VF_COMPONENT_PACKING_VertexElement20Enables_bits 4 #define GFX9_3DSTATE_VF_COMPONENT_PACKING_VertexElement20Enables_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_COMPONENT_PACKING_VertexElement20Enables_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_COMPONENT_PACKING_VertexElement20Enables_start 112 #define GFX12_3DSTATE_VF_COMPONENT_PACKING_VertexElement20Enables_start 112 #define GFX11_3DSTATE_VF_COMPONENT_PACKING_VertexElement20Enables_start 112 #define GFX9_3DSTATE_VF_COMPONENT_PACKING_VertexElement20Enables_start 112 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_COMPONENT_PACKING_VertexElement20Enables_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 112; case 120: return 112; case 110: return 112; case 90: return 112; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_COMPONENT_PACKING::Vertex Element 21 Enables */ #define GFX125_3DSTATE_VF_COMPONENT_PACKING_VertexElement21Enables_bits 4 #define GFX12_3DSTATE_VF_COMPONENT_PACKING_VertexElement21Enables_bits 4 #define GFX11_3DSTATE_VF_COMPONENT_PACKING_VertexElement21Enables_bits 4 #define GFX9_3DSTATE_VF_COMPONENT_PACKING_VertexElement21Enables_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_COMPONENT_PACKING_VertexElement21Enables_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_COMPONENT_PACKING_VertexElement21Enables_start 116 #define GFX12_3DSTATE_VF_COMPONENT_PACKING_VertexElement21Enables_start 116 #define GFX11_3DSTATE_VF_COMPONENT_PACKING_VertexElement21Enables_start 116 #define GFX9_3DSTATE_VF_COMPONENT_PACKING_VertexElement21Enables_start 116 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_COMPONENT_PACKING_VertexElement21Enables_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 116; case 120: return 116; case 110: return 116; case 90: return 116; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_COMPONENT_PACKING::Vertex Element 22 Enables */ #define GFX125_3DSTATE_VF_COMPONENT_PACKING_VertexElement22Enables_bits 4 #define GFX12_3DSTATE_VF_COMPONENT_PACKING_VertexElement22Enables_bits 4 #define GFX11_3DSTATE_VF_COMPONENT_PACKING_VertexElement22Enables_bits 4 #define GFX9_3DSTATE_VF_COMPONENT_PACKING_VertexElement22Enables_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_COMPONENT_PACKING_VertexElement22Enables_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_COMPONENT_PACKING_VertexElement22Enables_start 120 #define GFX12_3DSTATE_VF_COMPONENT_PACKING_VertexElement22Enables_start 120 #define GFX11_3DSTATE_VF_COMPONENT_PACKING_VertexElement22Enables_start 120 #define GFX9_3DSTATE_VF_COMPONENT_PACKING_VertexElement22Enables_start 120 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_COMPONENT_PACKING_VertexElement22Enables_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 120; case 120: return 120; case 110: return 120; case 90: return 120; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_COMPONENT_PACKING::Vertex Element 23 Enables */ #define GFX125_3DSTATE_VF_COMPONENT_PACKING_VertexElement23Enables_bits 4 #define GFX12_3DSTATE_VF_COMPONENT_PACKING_VertexElement23Enables_bits 4 #define GFX11_3DSTATE_VF_COMPONENT_PACKING_VertexElement23Enables_bits 4 #define GFX9_3DSTATE_VF_COMPONENT_PACKING_VertexElement23Enables_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_COMPONENT_PACKING_VertexElement23Enables_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_COMPONENT_PACKING_VertexElement23Enables_start 124 #define GFX12_3DSTATE_VF_COMPONENT_PACKING_VertexElement23Enables_start 124 #define GFX11_3DSTATE_VF_COMPONENT_PACKING_VertexElement23Enables_start 124 #define GFX9_3DSTATE_VF_COMPONENT_PACKING_VertexElement23Enables_start 124 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_COMPONENT_PACKING_VertexElement23Enables_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 124; case 120: return 124; case 110: return 124; case 90: return 124; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_COMPONENT_PACKING::Vertex Element 24 Enables */ #define GFX125_3DSTATE_VF_COMPONENT_PACKING_VertexElement24Enables_bits 4 #define GFX12_3DSTATE_VF_COMPONENT_PACKING_VertexElement24Enables_bits 4 #define GFX11_3DSTATE_VF_COMPONENT_PACKING_VertexElement24Enables_bits 4 #define GFX9_3DSTATE_VF_COMPONENT_PACKING_VertexElement24Enables_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_COMPONENT_PACKING_VertexElement24Enables_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_COMPONENT_PACKING_VertexElement24Enables_start 128 #define GFX12_3DSTATE_VF_COMPONENT_PACKING_VertexElement24Enables_start 128 #define GFX11_3DSTATE_VF_COMPONENT_PACKING_VertexElement24Enables_start 128 #define GFX9_3DSTATE_VF_COMPONENT_PACKING_VertexElement24Enables_start 128 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_COMPONENT_PACKING_VertexElement24Enables_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 128; case 120: return 128; case 110: return 128; case 90: return 128; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_COMPONENT_PACKING::Vertex Element 25 Enables */ #define GFX125_3DSTATE_VF_COMPONENT_PACKING_VertexElement25Enables_bits 4 #define GFX12_3DSTATE_VF_COMPONENT_PACKING_VertexElement25Enables_bits 4 #define GFX11_3DSTATE_VF_COMPONENT_PACKING_VertexElement25Enables_bits 4 #define GFX9_3DSTATE_VF_COMPONENT_PACKING_VertexElement25Enables_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_COMPONENT_PACKING_VertexElement25Enables_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_COMPONENT_PACKING_VertexElement25Enables_start 132 #define GFX12_3DSTATE_VF_COMPONENT_PACKING_VertexElement25Enables_start 132 #define GFX11_3DSTATE_VF_COMPONENT_PACKING_VertexElement25Enables_start 132 #define GFX9_3DSTATE_VF_COMPONENT_PACKING_VertexElement25Enables_start 132 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_COMPONENT_PACKING_VertexElement25Enables_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 132; case 120: return 132; case 110: return 132; case 90: return 132; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_COMPONENT_PACKING::Vertex Element 26 Enables */ #define GFX125_3DSTATE_VF_COMPONENT_PACKING_VertexElement26Enables_bits 4 #define GFX12_3DSTATE_VF_COMPONENT_PACKING_VertexElement26Enables_bits 4 #define GFX11_3DSTATE_VF_COMPONENT_PACKING_VertexElement26Enables_bits 4 #define GFX9_3DSTATE_VF_COMPONENT_PACKING_VertexElement26Enables_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_COMPONENT_PACKING_VertexElement26Enables_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_COMPONENT_PACKING_VertexElement26Enables_start 136 #define GFX12_3DSTATE_VF_COMPONENT_PACKING_VertexElement26Enables_start 136 #define GFX11_3DSTATE_VF_COMPONENT_PACKING_VertexElement26Enables_start 136 #define GFX9_3DSTATE_VF_COMPONENT_PACKING_VertexElement26Enables_start 136 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_COMPONENT_PACKING_VertexElement26Enables_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 136; case 120: return 136; case 110: return 136; case 90: return 136; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_COMPONENT_PACKING::Vertex Element 27 Enables */ #define GFX125_3DSTATE_VF_COMPONENT_PACKING_VertexElement27Enables_bits 4 #define GFX12_3DSTATE_VF_COMPONENT_PACKING_VertexElement27Enables_bits 4 #define GFX11_3DSTATE_VF_COMPONENT_PACKING_VertexElement27Enables_bits 4 #define GFX9_3DSTATE_VF_COMPONENT_PACKING_VertexElement27Enables_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_COMPONENT_PACKING_VertexElement27Enables_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_COMPONENT_PACKING_VertexElement27Enables_start 140 #define GFX12_3DSTATE_VF_COMPONENT_PACKING_VertexElement27Enables_start 140 #define GFX11_3DSTATE_VF_COMPONENT_PACKING_VertexElement27Enables_start 140 #define GFX9_3DSTATE_VF_COMPONENT_PACKING_VertexElement27Enables_start 140 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_COMPONENT_PACKING_VertexElement27Enables_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 140; case 120: return 140; case 110: return 140; case 90: return 140; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_COMPONENT_PACKING::Vertex Element 28 Enables */ #define GFX125_3DSTATE_VF_COMPONENT_PACKING_VertexElement28Enables_bits 4 #define GFX12_3DSTATE_VF_COMPONENT_PACKING_VertexElement28Enables_bits 4 #define GFX11_3DSTATE_VF_COMPONENT_PACKING_VertexElement28Enables_bits 4 #define GFX9_3DSTATE_VF_COMPONENT_PACKING_VertexElement28Enables_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_COMPONENT_PACKING_VertexElement28Enables_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_COMPONENT_PACKING_VertexElement28Enables_start 144 #define GFX12_3DSTATE_VF_COMPONENT_PACKING_VertexElement28Enables_start 144 #define GFX11_3DSTATE_VF_COMPONENT_PACKING_VertexElement28Enables_start 144 #define GFX9_3DSTATE_VF_COMPONENT_PACKING_VertexElement28Enables_start 144 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_COMPONENT_PACKING_VertexElement28Enables_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 144; case 120: return 144; case 110: return 144; case 90: return 144; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_COMPONENT_PACKING::Vertex Element 29 Enables */ #define GFX125_3DSTATE_VF_COMPONENT_PACKING_VertexElement29Enables_bits 4 #define GFX12_3DSTATE_VF_COMPONENT_PACKING_VertexElement29Enables_bits 4 #define GFX11_3DSTATE_VF_COMPONENT_PACKING_VertexElement29Enables_bits 4 #define GFX9_3DSTATE_VF_COMPONENT_PACKING_VertexElement29Enables_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_COMPONENT_PACKING_VertexElement29Enables_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_COMPONENT_PACKING_VertexElement29Enables_start 148 #define GFX12_3DSTATE_VF_COMPONENT_PACKING_VertexElement29Enables_start 148 #define GFX11_3DSTATE_VF_COMPONENT_PACKING_VertexElement29Enables_start 148 #define GFX9_3DSTATE_VF_COMPONENT_PACKING_VertexElement29Enables_start 148 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_COMPONENT_PACKING_VertexElement29Enables_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 148; case 120: return 148; case 110: return 148; case 90: return 148; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_COMPONENT_PACKING::Vertex Element 30 Enables */ #define GFX125_3DSTATE_VF_COMPONENT_PACKING_VertexElement30Enables_bits 4 #define GFX12_3DSTATE_VF_COMPONENT_PACKING_VertexElement30Enables_bits 4 #define GFX11_3DSTATE_VF_COMPONENT_PACKING_VertexElement30Enables_bits 4 #define GFX9_3DSTATE_VF_COMPONENT_PACKING_VertexElement30Enables_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_COMPONENT_PACKING_VertexElement30Enables_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_COMPONENT_PACKING_VertexElement30Enables_start 152 #define GFX12_3DSTATE_VF_COMPONENT_PACKING_VertexElement30Enables_start 152 #define GFX11_3DSTATE_VF_COMPONENT_PACKING_VertexElement30Enables_start 152 #define GFX9_3DSTATE_VF_COMPONENT_PACKING_VertexElement30Enables_start 152 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_COMPONENT_PACKING_VertexElement30Enables_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 152; case 120: return 152; case 110: return 152; case 90: return 152; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_COMPONENT_PACKING::Vertex Element 31 Enables */ #define GFX125_3DSTATE_VF_COMPONENT_PACKING_VertexElement31Enables_bits 4 #define GFX12_3DSTATE_VF_COMPONENT_PACKING_VertexElement31Enables_bits 4 #define GFX11_3DSTATE_VF_COMPONENT_PACKING_VertexElement31Enables_bits 4 #define GFX9_3DSTATE_VF_COMPONENT_PACKING_VertexElement31Enables_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_COMPONENT_PACKING_VertexElement31Enables_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_COMPONENT_PACKING_VertexElement31Enables_start 156 #define GFX12_3DSTATE_VF_COMPONENT_PACKING_VertexElement31Enables_start 156 #define GFX11_3DSTATE_VF_COMPONENT_PACKING_VertexElement31Enables_start 156 #define GFX9_3DSTATE_VF_COMPONENT_PACKING_VertexElement31Enables_start 156 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_COMPONENT_PACKING_VertexElement31Enables_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 156; case 120: return 156; case 110: return 156; case 90: return 156; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_INSTANCING */ #define GFX125_3DSTATE_VF_INSTANCING_length 3 #define GFX12_3DSTATE_VF_INSTANCING_length 3 #define GFX11_3DSTATE_VF_INSTANCING_length 3 #define GFX9_3DSTATE_VF_INSTANCING_length 3 #define GFX8_3DSTATE_VF_INSTANCING_length 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_INSTANCING_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_INSTANCING::3D Command Opcode */ #define GFX125_3DSTATE_VF_INSTANCING_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_VF_INSTANCING_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_VF_INSTANCING_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_VF_INSTANCING_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_VF_INSTANCING_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_INSTANCING_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_INSTANCING_3DCommandOpcode_start 24 #define GFX12_3DSTATE_VF_INSTANCING_3DCommandOpcode_start 24 #define GFX11_3DSTATE_VF_INSTANCING_3DCommandOpcode_start 24 #define GFX9_3DSTATE_VF_INSTANCING_3DCommandOpcode_start 24 #define GFX8_3DSTATE_VF_INSTANCING_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_INSTANCING_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_INSTANCING::3D Command Sub Opcode */ #define GFX125_3DSTATE_VF_INSTANCING_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_VF_INSTANCING_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_VF_INSTANCING_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_VF_INSTANCING_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_VF_INSTANCING_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_INSTANCING_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_INSTANCING_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_VF_INSTANCING_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_VF_INSTANCING_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_VF_INSTANCING_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_VF_INSTANCING_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_INSTANCING_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_INSTANCING::Command SubType */ #define GFX125_3DSTATE_VF_INSTANCING_CommandSubType_bits 2 #define GFX12_3DSTATE_VF_INSTANCING_CommandSubType_bits 2 #define GFX11_3DSTATE_VF_INSTANCING_CommandSubType_bits 2 #define GFX9_3DSTATE_VF_INSTANCING_CommandSubType_bits 2 #define GFX8_3DSTATE_VF_INSTANCING_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_INSTANCING_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_INSTANCING_CommandSubType_start 27 #define GFX12_3DSTATE_VF_INSTANCING_CommandSubType_start 27 #define GFX11_3DSTATE_VF_INSTANCING_CommandSubType_start 27 #define GFX9_3DSTATE_VF_INSTANCING_CommandSubType_start 27 #define GFX8_3DSTATE_VF_INSTANCING_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_INSTANCING_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_INSTANCING::Command Type */ #define GFX125_3DSTATE_VF_INSTANCING_CommandType_bits 3 #define GFX12_3DSTATE_VF_INSTANCING_CommandType_bits 3 #define GFX11_3DSTATE_VF_INSTANCING_CommandType_bits 3 #define GFX9_3DSTATE_VF_INSTANCING_CommandType_bits 3 #define GFX8_3DSTATE_VF_INSTANCING_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_INSTANCING_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_INSTANCING_CommandType_start 29 #define GFX12_3DSTATE_VF_INSTANCING_CommandType_start 29 #define GFX11_3DSTATE_VF_INSTANCING_CommandType_start 29 #define GFX9_3DSTATE_VF_INSTANCING_CommandType_start 29 #define GFX8_3DSTATE_VF_INSTANCING_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_INSTANCING_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_INSTANCING::DWord Length */ #define GFX125_3DSTATE_VF_INSTANCING_DWordLength_bits 8 #define GFX12_3DSTATE_VF_INSTANCING_DWordLength_bits 8 #define GFX11_3DSTATE_VF_INSTANCING_DWordLength_bits 8 #define GFX9_3DSTATE_VF_INSTANCING_DWordLength_bits 8 #define GFX8_3DSTATE_VF_INSTANCING_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_INSTANCING_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_INSTANCING_DWordLength_start 0 #define GFX12_3DSTATE_VF_INSTANCING_DWordLength_start 0 #define GFX11_3DSTATE_VF_INSTANCING_DWordLength_start 0 #define GFX9_3DSTATE_VF_INSTANCING_DWordLength_start 0 #define GFX8_3DSTATE_VF_INSTANCING_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_INSTANCING_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_INSTANCING::Instance Data Step Rate */ #define GFX125_3DSTATE_VF_INSTANCING_InstanceDataStepRate_bits 32 #define GFX12_3DSTATE_VF_INSTANCING_InstanceDataStepRate_bits 32 #define GFX11_3DSTATE_VF_INSTANCING_InstanceDataStepRate_bits 32 #define GFX9_3DSTATE_VF_INSTANCING_InstanceDataStepRate_bits 32 #define GFX8_3DSTATE_VF_INSTANCING_InstanceDataStepRate_bits 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_INSTANCING_InstanceDataStepRate_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_INSTANCING_InstanceDataStepRate_start 64 #define GFX12_3DSTATE_VF_INSTANCING_InstanceDataStepRate_start 64 #define GFX11_3DSTATE_VF_INSTANCING_InstanceDataStepRate_start 64 #define GFX9_3DSTATE_VF_INSTANCING_InstanceDataStepRate_start 64 #define GFX8_3DSTATE_VF_INSTANCING_InstanceDataStepRate_start 64 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_INSTANCING_InstanceDataStepRate_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 64; case 80: return 64; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_INSTANCING::Instancing Enable */ #define GFX125_3DSTATE_VF_INSTANCING_InstancingEnable_bits 1 #define GFX12_3DSTATE_VF_INSTANCING_InstancingEnable_bits 1 #define GFX11_3DSTATE_VF_INSTANCING_InstancingEnable_bits 1 #define GFX9_3DSTATE_VF_INSTANCING_InstancingEnable_bits 1 #define GFX8_3DSTATE_VF_INSTANCING_InstancingEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_INSTANCING_InstancingEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_INSTANCING_InstancingEnable_start 40 #define GFX12_3DSTATE_VF_INSTANCING_InstancingEnable_start 40 #define GFX11_3DSTATE_VF_INSTANCING_InstancingEnable_start 40 #define GFX9_3DSTATE_VF_INSTANCING_InstancingEnable_start 40 #define GFX8_3DSTATE_VF_INSTANCING_InstancingEnable_start 40 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_INSTANCING_InstancingEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 40; case 120: return 40; case 110: return 40; case 90: return 40; case 80: return 40; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_INSTANCING::Vertex Element Index */ #define GFX125_3DSTATE_VF_INSTANCING_VertexElementIndex_bits 6 #define GFX12_3DSTATE_VF_INSTANCING_VertexElementIndex_bits 6 #define GFX11_3DSTATE_VF_INSTANCING_VertexElementIndex_bits 6 #define GFX9_3DSTATE_VF_INSTANCING_VertexElementIndex_bits 6 #define GFX8_3DSTATE_VF_INSTANCING_VertexElementIndex_bits 6 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_INSTANCING_VertexElementIndex_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_INSTANCING_VertexElementIndex_start 32 #define GFX12_3DSTATE_VF_INSTANCING_VertexElementIndex_start 32 #define GFX11_3DSTATE_VF_INSTANCING_VertexElementIndex_start 32 #define GFX9_3DSTATE_VF_INSTANCING_VertexElementIndex_start 32 #define GFX8_3DSTATE_VF_INSTANCING_VertexElementIndex_start 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_INSTANCING_VertexElementIndex_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_SGVS */ #define GFX125_3DSTATE_VF_SGVS_length 2 #define GFX12_3DSTATE_VF_SGVS_length 2 #define GFX11_3DSTATE_VF_SGVS_length 2 #define GFX9_3DSTATE_VF_SGVS_length 2 #define GFX8_3DSTATE_VF_SGVS_length 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_SGVS_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_SGVS::3D Command Opcode */ #define GFX125_3DSTATE_VF_SGVS_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_VF_SGVS_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_VF_SGVS_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_VF_SGVS_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_VF_SGVS_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_SGVS_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_SGVS_3DCommandOpcode_start 24 #define GFX12_3DSTATE_VF_SGVS_3DCommandOpcode_start 24 #define GFX11_3DSTATE_VF_SGVS_3DCommandOpcode_start 24 #define GFX9_3DSTATE_VF_SGVS_3DCommandOpcode_start 24 #define GFX8_3DSTATE_VF_SGVS_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_SGVS_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_SGVS::3D Command Sub Opcode */ #define GFX125_3DSTATE_VF_SGVS_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_VF_SGVS_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_VF_SGVS_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_VF_SGVS_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_VF_SGVS_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_SGVS_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_SGVS_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_VF_SGVS_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_VF_SGVS_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_VF_SGVS_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_VF_SGVS_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_SGVS_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_SGVS::Command SubType */ #define GFX125_3DSTATE_VF_SGVS_CommandSubType_bits 2 #define GFX12_3DSTATE_VF_SGVS_CommandSubType_bits 2 #define GFX11_3DSTATE_VF_SGVS_CommandSubType_bits 2 #define GFX9_3DSTATE_VF_SGVS_CommandSubType_bits 2 #define GFX8_3DSTATE_VF_SGVS_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_SGVS_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_SGVS_CommandSubType_start 27 #define GFX12_3DSTATE_VF_SGVS_CommandSubType_start 27 #define GFX11_3DSTATE_VF_SGVS_CommandSubType_start 27 #define GFX9_3DSTATE_VF_SGVS_CommandSubType_start 27 #define GFX8_3DSTATE_VF_SGVS_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_SGVS_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_SGVS::Command Type */ #define GFX125_3DSTATE_VF_SGVS_CommandType_bits 3 #define GFX12_3DSTATE_VF_SGVS_CommandType_bits 3 #define GFX11_3DSTATE_VF_SGVS_CommandType_bits 3 #define GFX9_3DSTATE_VF_SGVS_CommandType_bits 3 #define GFX8_3DSTATE_VF_SGVS_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_SGVS_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_SGVS_CommandType_start 29 #define GFX12_3DSTATE_VF_SGVS_CommandType_start 29 #define GFX11_3DSTATE_VF_SGVS_CommandType_start 29 #define GFX9_3DSTATE_VF_SGVS_CommandType_start 29 #define GFX8_3DSTATE_VF_SGVS_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_SGVS_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_SGVS::DWord Length */ #define GFX125_3DSTATE_VF_SGVS_DWordLength_bits 8 #define GFX12_3DSTATE_VF_SGVS_DWordLength_bits 8 #define GFX11_3DSTATE_VF_SGVS_DWordLength_bits 8 #define GFX9_3DSTATE_VF_SGVS_DWordLength_bits 8 #define GFX8_3DSTATE_VF_SGVS_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_SGVS_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_SGVS_DWordLength_start 0 #define GFX12_3DSTATE_VF_SGVS_DWordLength_start 0 #define GFX11_3DSTATE_VF_SGVS_DWordLength_start 0 #define GFX9_3DSTATE_VF_SGVS_DWordLength_start 0 #define GFX8_3DSTATE_VF_SGVS_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_SGVS_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_SGVS::InstanceID Component Number */ #define GFX125_3DSTATE_VF_SGVS_InstanceIDComponentNumber_bits 2 #define GFX12_3DSTATE_VF_SGVS_InstanceIDComponentNumber_bits 2 #define GFX11_3DSTATE_VF_SGVS_InstanceIDComponentNumber_bits 2 #define GFX9_3DSTATE_VF_SGVS_InstanceIDComponentNumber_bits 2 #define GFX8_3DSTATE_VF_SGVS_InstanceIDComponentNumber_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_SGVS_InstanceIDComponentNumber_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_SGVS_InstanceIDComponentNumber_start 61 #define GFX12_3DSTATE_VF_SGVS_InstanceIDComponentNumber_start 61 #define GFX11_3DSTATE_VF_SGVS_InstanceIDComponentNumber_start 61 #define GFX9_3DSTATE_VF_SGVS_InstanceIDComponentNumber_start 61 #define GFX8_3DSTATE_VF_SGVS_InstanceIDComponentNumber_start 61 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_SGVS_InstanceIDComponentNumber_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 61; case 120: return 61; case 110: return 61; case 90: return 61; case 80: return 61; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_SGVS::InstanceID Element Offset */ #define GFX125_3DSTATE_VF_SGVS_InstanceIDElementOffset_bits 6 #define GFX12_3DSTATE_VF_SGVS_InstanceIDElementOffset_bits 6 #define GFX11_3DSTATE_VF_SGVS_InstanceIDElementOffset_bits 6 #define GFX9_3DSTATE_VF_SGVS_InstanceIDElementOffset_bits 6 #define GFX8_3DSTATE_VF_SGVS_InstanceIDElementOffset_bits 6 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_SGVS_InstanceIDElementOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_SGVS_InstanceIDElementOffset_start 48 #define GFX12_3DSTATE_VF_SGVS_InstanceIDElementOffset_start 48 #define GFX11_3DSTATE_VF_SGVS_InstanceIDElementOffset_start 48 #define GFX9_3DSTATE_VF_SGVS_InstanceIDElementOffset_start 48 #define GFX8_3DSTATE_VF_SGVS_InstanceIDElementOffset_start 48 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_SGVS_InstanceIDElementOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 48; case 120: return 48; case 110: return 48; case 90: return 48; case 80: return 48; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_SGVS::InstanceID Enable */ #define GFX125_3DSTATE_VF_SGVS_InstanceIDEnable_bits 1 #define GFX12_3DSTATE_VF_SGVS_InstanceIDEnable_bits 1 #define GFX11_3DSTATE_VF_SGVS_InstanceIDEnable_bits 1 #define GFX9_3DSTATE_VF_SGVS_InstanceIDEnable_bits 1 #define GFX8_3DSTATE_VF_SGVS_InstanceIDEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_SGVS_InstanceIDEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_SGVS_InstanceIDEnable_start 63 #define GFX12_3DSTATE_VF_SGVS_InstanceIDEnable_start 63 #define GFX11_3DSTATE_VF_SGVS_InstanceIDEnable_start 63 #define GFX9_3DSTATE_VF_SGVS_InstanceIDEnable_start 63 #define GFX8_3DSTATE_VF_SGVS_InstanceIDEnable_start 63 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_SGVS_InstanceIDEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 63; case 120: return 63; case 110: return 63; case 90: return 63; case 80: return 63; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_SGVS::VertexID Component Number */ #define GFX125_3DSTATE_VF_SGVS_VertexIDComponentNumber_bits 2 #define GFX12_3DSTATE_VF_SGVS_VertexIDComponentNumber_bits 2 #define GFX11_3DSTATE_VF_SGVS_VertexIDComponentNumber_bits 2 #define GFX9_3DSTATE_VF_SGVS_VertexIDComponentNumber_bits 2 #define GFX8_3DSTATE_VF_SGVS_VertexIDComponentNumber_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_SGVS_VertexIDComponentNumber_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_SGVS_VertexIDComponentNumber_start 45 #define GFX12_3DSTATE_VF_SGVS_VertexIDComponentNumber_start 45 #define GFX11_3DSTATE_VF_SGVS_VertexIDComponentNumber_start 45 #define GFX9_3DSTATE_VF_SGVS_VertexIDComponentNumber_start 45 #define GFX8_3DSTATE_VF_SGVS_VertexIDComponentNumber_start 45 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_SGVS_VertexIDComponentNumber_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 45; case 120: return 45; case 110: return 45; case 90: return 45; case 80: return 45; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_SGVS::VertexID Element Offset */ #define GFX125_3DSTATE_VF_SGVS_VertexIDElementOffset_bits 6 #define GFX12_3DSTATE_VF_SGVS_VertexIDElementOffset_bits 6 #define GFX11_3DSTATE_VF_SGVS_VertexIDElementOffset_bits 6 #define GFX9_3DSTATE_VF_SGVS_VertexIDElementOffset_bits 6 #define GFX8_3DSTATE_VF_SGVS_VertexIDElementOffset_bits 6 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_SGVS_VertexIDElementOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_SGVS_VertexIDElementOffset_start 32 #define GFX12_3DSTATE_VF_SGVS_VertexIDElementOffset_start 32 #define GFX11_3DSTATE_VF_SGVS_VertexIDElementOffset_start 32 #define GFX9_3DSTATE_VF_SGVS_VertexIDElementOffset_start 32 #define GFX8_3DSTATE_VF_SGVS_VertexIDElementOffset_start 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_SGVS_VertexIDElementOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_SGVS::VertexID Enable */ #define GFX125_3DSTATE_VF_SGVS_VertexIDEnable_bits 1 #define GFX12_3DSTATE_VF_SGVS_VertexIDEnable_bits 1 #define GFX11_3DSTATE_VF_SGVS_VertexIDEnable_bits 1 #define GFX9_3DSTATE_VF_SGVS_VertexIDEnable_bits 1 #define GFX8_3DSTATE_VF_SGVS_VertexIDEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_SGVS_VertexIDEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_SGVS_VertexIDEnable_start 47 #define GFX12_3DSTATE_VF_SGVS_VertexIDEnable_start 47 #define GFX11_3DSTATE_VF_SGVS_VertexIDEnable_start 47 #define GFX9_3DSTATE_VF_SGVS_VertexIDEnable_start 47 #define GFX8_3DSTATE_VF_SGVS_VertexIDEnable_start 47 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_SGVS_VertexIDEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 47; case 120: return 47; case 110: return 47; case 90: return 47; case 80: return 47; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_SGVS_2 */ #define GFX125_3DSTATE_VF_SGVS_2_length 3 #define GFX12_3DSTATE_VF_SGVS_2_length 3 #define GFX11_3DSTATE_VF_SGVS_2_length 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_SGVS_2_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_SGVS_2::3D Command Opcode */ #define GFX125_3DSTATE_VF_SGVS_2_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_VF_SGVS_2_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_VF_SGVS_2_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_SGVS_2_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_SGVS_2_3DCommandOpcode_start 24 #define GFX12_3DSTATE_VF_SGVS_2_3DCommandOpcode_start 24 #define GFX11_3DSTATE_VF_SGVS_2_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_SGVS_2_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_SGVS_2::3D Command Sub Opcode */ #define GFX125_3DSTATE_VF_SGVS_2_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_VF_SGVS_2_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_VF_SGVS_2_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_SGVS_2_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_SGVS_2_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_VF_SGVS_2_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_VF_SGVS_2_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_SGVS_2_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_SGVS_2::Command SubType */ #define GFX125_3DSTATE_VF_SGVS_2_CommandSubType_bits 2 #define GFX12_3DSTATE_VF_SGVS_2_CommandSubType_bits 2 #define GFX11_3DSTATE_VF_SGVS_2_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_SGVS_2_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_SGVS_2_CommandSubType_start 27 #define GFX12_3DSTATE_VF_SGVS_2_CommandSubType_start 27 #define GFX11_3DSTATE_VF_SGVS_2_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_SGVS_2_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_SGVS_2::Command Type */ #define GFX125_3DSTATE_VF_SGVS_2_CommandType_bits 3 #define GFX12_3DSTATE_VF_SGVS_2_CommandType_bits 3 #define GFX11_3DSTATE_VF_SGVS_2_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_SGVS_2_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_SGVS_2_CommandType_start 29 #define GFX12_3DSTATE_VF_SGVS_2_CommandType_start 29 #define GFX11_3DSTATE_VF_SGVS_2_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_SGVS_2_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_SGVS_2::DWord Length */ #define GFX125_3DSTATE_VF_SGVS_2_DWordLength_bits 8 #define GFX12_3DSTATE_VF_SGVS_2_DWordLength_bits 8 #define GFX11_3DSTATE_VF_SGVS_2_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_SGVS_2_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_SGVS_2_DWordLength_start 0 #define GFX12_3DSTATE_VF_SGVS_2_DWordLength_start 0 #define GFX11_3DSTATE_VF_SGVS_2_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_SGVS_2_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_SGVS_2::XP0 Component Number */ #define GFX125_3DSTATE_VF_SGVS_2_XP0ComponentNumber_bits 2 #define GFX12_3DSTATE_VF_SGVS_2_XP0ComponentNumber_bits 2 #define GFX11_3DSTATE_VF_SGVS_2_XP0ComponentNumber_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_SGVS_2_XP0ComponentNumber_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_SGVS_2_XP0ComponentNumber_start 45 #define GFX12_3DSTATE_VF_SGVS_2_XP0ComponentNumber_start 45 #define GFX11_3DSTATE_VF_SGVS_2_XP0ComponentNumber_start 45 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_SGVS_2_XP0ComponentNumber_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 45; case 120: return 45; case 110: return 45; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_SGVS_2::XP0 Element Offset */ #define GFX125_3DSTATE_VF_SGVS_2_XP0ElementOffset_bits 6 #define GFX12_3DSTATE_VF_SGVS_2_XP0ElementOffset_bits 6 #define GFX11_3DSTATE_VF_SGVS_2_XP0ElementOffset_bits 6 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_SGVS_2_XP0ElementOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_SGVS_2_XP0ElementOffset_start 32 #define GFX12_3DSTATE_VF_SGVS_2_XP0ElementOffset_start 32 #define GFX11_3DSTATE_VF_SGVS_2_XP0ElementOffset_start 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_SGVS_2_XP0ElementOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_SGVS_2::XP0 Enable */ #define GFX125_3DSTATE_VF_SGVS_2_XP0Enable_bits 1 #define GFX12_3DSTATE_VF_SGVS_2_XP0Enable_bits 1 #define GFX11_3DSTATE_VF_SGVS_2_XP0Enable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_SGVS_2_XP0Enable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_SGVS_2_XP0Enable_start 47 #define GFX12_3DSTATE_VF_SGVS_2_XP0Enable_start 47 #define GFX11_3DSTATE_VF_SGVS_2_XP0Enable_start 47 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_SGVS_2_XP0Enable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 47; case 120: return 47; case 110: return 47; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_SGVS_2::XP0 Source Select */ #define GFX125_3DSTATE_VF_SGVS_2_XP0SourceSelect_bits 1 #define GFX12_3DSTATE_VF_SGVS_2_XP0SourceSelect_bits 1 #define GFX11_3DSTATE_VF_SGVS_2_XP0SourceSelect_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_SGVS_2_XP0SourceSelect_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_SGVS_2_XP0SourceSelect_start 44 #define GFX12_3DSTATE_VF_SGVS_2_XP0SourceSelect_start 44 #define GFX11_3DSTATE_VF_SGVS_2_XP0SourceSelect_start 44 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_SGVS_2_XP0SourceSelect_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 44; case 120: return 44; case 110: return 44; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_SGVS_2::XP1 Component Number */ #define GFX125_3DSTATE_VF_SGVS_2_XP1ComponentNumber_bits 2 #define GFX12_3DSTATE_VF_SGVS_2_XP1ComponentNumber_bits 2 #define GFX11_3DSTATE_VF_SGVS_2_XP1ComponentNumber_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_SGVS_2_XP1ComponentNumber_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_SGVS_2_XP1ComponentNumber_start 61 #define GFX12_3DSTATE_VF_SGVS_2_XP1ComponentNumber_start 61 #define GFX11_3DSTATE_VF_SGVS_2_XP1ComponentNumber_start 61 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_SGVS_2_XP1ComponentNumber_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 61; case 120: return 61; case 110: return 61; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_SGVS_2::XP1 Element Offset */ #define GFX125_3DSTATE_VF_SGVS_2_XP1ElementOffset_bits 6 #define GFX12_3DSTATE_VF_SGVS_2_XP1ElementOffset_bits 6 #define GFX11_3DSTATE_VF_SGVS_2_XP1ElementOffset_bits 6 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_SGVS_2_XP1ElementOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_SGVS_2_XP1ElementOffset_start 48 #define GFX12_3DSTATE_VF_SGVS_2_XP1ElementOffset_start 48 #define GFX11_3DSTATE_VF_SGVS_2_XP1ElementOffset_start 48 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_SGVS_2_XP1ElementOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 48; case 120: return 48; case 110: return 48; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_SGVS_2::XP1 Enable */ #define GFX125_3DSTATE_VF_SGVS_2_XP1Enable_bits 1 #define GFX12_3DSTATE_VF_SGVS_2_XP1Enable_bits 1 #define GFX11_3DSTATE_VF_SGVS_2_XP1Enable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_SGVS_2_XP1Enable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_SGVS_2_XP1Enable_start 63 #define GFX12_3DSTATE_VF_SGVS_2_XP1Enable_start 63 #define GFX11_3DSTATE_VF_SGVS_2_XP1Enable_start 63 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_SGVS_2_XP1Enable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 63; case 120: return 63; case 110: return 63; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_SGVS_2::XP1 Source Select */ #define GFX125_3DSTATE_VF_SGVS_2_XP1SourceSelect_bits 1 #define GFX12_3DSTATE_VF_SGVS_2_XP1SourceSelect_bits 1 #define GFX11_3DSTATE_VF_SGVS_2_XP1SourceSelect_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_SGVS_2_XP1SourceSelect_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_SGVS_2_XP1SourceSelect_start 60 #define GFX12_3DSTATE_VF_SGVS_2_XP1SourceSelect_start 60 #define GFX11_3DSTATE_VF_SGVS_2_XP1SourceSelect_start 60 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_SGVS_2_XP1SourceSelect_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 60; case 120: return 60; case 110: return 60; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_SGVS_2::XP2 Component Number */ #define GFX125_3DSTATE_VF_SGVS_2_XP2ComponentNumber_bits 2 #define GFX12_3DSTATE_VF_SGVS_2_XP2ComponentNumber_bits 2 #define GFX11_3DSTATE_VF_SGVS_2_XP2ComponentNumber_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_SGVS_2_XP2ComponentNumber_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_SGVS_2_XP2ComponentNumber_start 77 #define GFX12_3DSTATE_VF_SGVS_2_XP2ComponentNumber_start 77 #define GFX11_3DSTATE_VF_SGVS_2_XP2ComponentNumber_start 77 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_SGVS_2_XP2ComponentNumber_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 77; case 120: return 77; case 110: return 77; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_SGVS_2::XP2 Element Offset */ #define GFX125_3DSTATE_VF_SGVS_2_XP2ElementOffset_bits 6 #define GFX12_3DSTATE_VF_SGVS_2_XP2ElementOffset_bits 6 #define GFX11_3DSTATE_VF_SGVS_2_XP2ElementOffset_bits 6 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_SGVS_2_XP2ElementOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_SGVS_2_XP2ElementOffset_start 64 #define GFX12_3DSTATE_VF_SGVS_2_XP2ElementOffset_start 64 #define GFX11_3DSTATE_VF_SGVS_2_XP2ElementOffset_start 64 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_SGVS_2_XP2ElementOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_SGVS_2::XP2 Enable */ #define GFX125_3DSTATE_VF_SGVS_2_XP2Enable_bits 1 #define GFX12_3DSTATE_VF_SGVS_2_XP2Enable_bits 1 #define GFX11_3DSTATE_VF_SGVS_2_XP2Enable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_SGVS_2_XP2Enable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_SGVS_2_XP2Enable_start 79 #define GFX12_3DSTATE_VF_SGVS_2_XP2Enable_start 79 #define GFX11_3DSTATE_VF_SGVS_2_XP2Enable_start 79 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_SGVS_2_XP2Enable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 79; case 120: return 79; case 110: return 79; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_STATISTICS */ #define GFX125_3DSTATE_VF_STATISTICS_length 1 #define GFX12_3DSTATE_VF_STATISTICS_length 1 #define GFX11_3DSTATE_VF_STATISTICS_length 1 #define GFX9_3DSTATE_VF_STATISTICS_length 1 #define GFX8_3DSTATE_VF_STATISTICS_length 1 #define GFX75_3DSTATE_VF_STATISTICS_length 1 #define GFX7_3DSTATE_VF_STATISTICS_length 1 #define GFX6_3DSTATE_VF_STATISTICS_length 1 #define GFX5_3DSTATE_VF_STATISTICS_length 1 #define GFX45_3DSTATE_VF_STATISTICS_length 1 #define GFX4_3DSTATE_VF_STATISTICS_length 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_STATISTICS_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_STATISTICS::3D Command Opcode */ #define GFX125_3DSTATE_VF_STATISTICS_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_VF_STATISTICS_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_VF_STATISTICS_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_VF_STATISTICS_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_VF_STATISTICS_3DCommandOpcode_bits 3 #define GFX75_3DSTATE_VF_STATISTICS_3DCommandOpcode_bits 3 #define GFX7_3DSTATE_VF_STATISTICS_3DCommandOpcode_bits 3 #define GFX6_3DSTATE_VF_STATISTICS_3DCommandOpcode_bits 3 #define GFX5_3DSTATE_VF_STATISTICS_3DCommandOpcode_bits 3 #define GFX45_3DSTATE_VF_STATISTICS_3DCommandOpcode_bits 3 #define GFX4_3DSTATE_VF_STATISTICS_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_STATISTICS_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_STATISTICS_3DCommandOpcode_start 24 #define GFX12_3DSTATE_VF_STATISTICS_3DCommandOpcode_start 24 #define GFX11_3DSTATE_VF_STATISTICS_3DCommandOpcode_start 24 #define GFX9_3DSTATE_VF_STATISTICS_3DCommandOpcode_start 24 #define GFX8_3DSTATE_VF_STATISTICS_3DCommandOpcode_start 24 #define GFX75_3DSTATE_VF_STATISTICS_3DCommandOpcode_start 24 #define GFX7_3DSTATE_VF_STATISTICS_3DCommandOpcode_start 24 #define GFX6_3DSTATE_VF_STATISTICS_3DCommandOpcode_start 24 #define GFX5_3DSTATE_VF_STATISTICS_3DCommandOpcode_start 24 #define GFX45_3DSTATE_VF_STATISTICS_3DCommandOpcode_start 24 #define GFX4_3DSTATE_VF_STATISTICS_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_STATISTICS_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 24; case 50: return 24; case 45: return 24; case 40: return 24; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_STATISTICS::3D Command Sub Opcode */ #define GFX125_3DSTATE_VF_STATISTICS_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_VF_STATISTICS_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_VF_STATISTICS_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_VF_STATISTICS_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_VF_STATISTICS_3DCommandSubOpcode_bits 8 #define GFX75_3DSTATE_VF_STATISTICS_3DCommandSubOpcode_bits 8 #define GFX7_3DSTATE_VF_STATISTICS_3DCommandSubOpcode_bits 8 #define GFX6_3DSTATE_VF_STATISTICS_3DCommandSubOpcode_bits 8 #define GFX5_3DSTATE_VF_STATISTICS_3DCommandSubOpcode_bits 8 #define GFX45_3DSTATE_VF_STATISTICS_3DCommandSubOpcode_bits 8 #define GFX4_3DSTATE_VF_STATISTICS_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_STATISTICS_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 8; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_STATISTICS_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_VF_STATISTICS_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_VF_STATISTICS_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_VF_STATISTICS_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_VF_STATISTICS_3DCommandSubOpcode_start 16 #define GFX75_3DSTATE_VF_STATISTICS_3DCommandSubOpcode_start 16 #define GFX7_3DSTATE_VF_STATISTICS_3DCommandSubOpcode_start 16 #define GFX6_3DSTATE_VF_STATISTICS_3DCommandSubOpcode_start 16 #define GFX5_3DSTATE_VF_STATISTICS_3DCommandSubOpcode_start 16 #define GFX45_3DSTATE_VF_STATISTICS_3DCommandSubOpcode_start 16 #define GFX4_3DSTATE_VF_STATISTICS_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_STATISTICS_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 16; case 50: return 16; case 45: return 16; case 40: return 16; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_STATISTICS::Command SubType */ #define GFX125_3DSTATE_VF_STATISTICS_CommandSubType_bits 2 #define GFX12_3DSTATE_VF_STATISTICS_CommandSubType_bits 2 #define GFX11_3DSTATE_VF_STATISTICS_CommandSubType_bits 2 #define GFX9_3DSTATE_VF_STATISTICS_CommandSubType_bits 2 #define GFX8_3DSTATE_VF_STATISTICS_CommandSubType_bits 2 #define GFX75_3DSTATE_VF_STATISTICS_CommandSubType_bits 2 #define GFX7_3DSTATE_VF_STATISTICS_CommandSubType_bits 2 #define GFX6_3DSTATE_VF_STATISTICS_CommandSubType_bits 2 #define GFX5_3DSTATE_VF_STATISTICS_CommandSubType_bits 2 #define GFX45_3DSTATE_VF_STATISTICS_CommandSubType_bits 2 #define GFX4_3DSTATE_VF_STATISTICS_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_STATISTICS_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 2; case 45: return 2; case 40: return 2; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_STATISTICS_CommandSubType_start 27 #define GFX12_3DSTATE_VF_STATISTICS_CommandSubType_start 27 #define GFX11_3DSTATE_VF_STATISTICS_CommandSubType_start 27 #define GFX9_3DSTATE_VF_STATISTICS_CommandSubType_start 27 #define GFX8_3DSTATE_VF_STATISTICS_CommandSubType_start 27 #define GFX75_3DSTATE_VF_STATISTICS_CommandSubType_start 27 #define GFX7_3DSTATE_VF_STATISTICS_CommandSubType_start 27 #define GFX6_3DSTATE_VF_STATISTICS_CommandSubType_start 27 #define GFX5_3DSTATE_VF_STATISTICS_CommandSubType_start 27 #define GFX45_3DSTATE_VF_STATISTICS_CommandSubType_start 27 #define GFX4_3DSTATE_VF_STATISTICS_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_STATISTICS_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 27; case 50: return 27; case 45: return 27; case 40: return 27; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_STATISTICS::Command Type */ #define GFX125_3DSTATE_VF_STATISTICS_CommandType_bits 3 #define GFX12_3DSTATE_VF_STATISTICS_CommandType_bits 3 #define GFX11_3DSTATE_VF_STATISTICS_CommandType_bits 3 #define GFX9_3DSTATE_VF_STATISTICS_CommandType_bits 3 #define GFX8_3DSTATE_VF_STATISTICS_CommandType_bits 3 #define GFX75_3DSTATE_VF_STATISTICS_CommandType_bits 3 #define GFX7_3DSTATE_VF_STATISTICS_CommandType_bits 3 #define GFX6_3DSTATE_VF_STATISTICS_CommandType_bits 3 #define GFX5_3DSTATE_VF_STATISTICS_CommandType_bits 3 #define GFX45_3DSTATE_VF_STATISTICS_CommandType_bits 3 #define GFX4_3DSTATE_VF_STATISTICS_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_STATISTICS_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_STATISTICS_CommandType_start 29 #define GFX12_3DSTATE_VF_STATISTICS_CommandType_start 29 #define GFX11_3DSTATE_VF_STATISTICS_CommandType_start 29 #define GFX9_3DSTATE_VF_STATISTICS_CommandType_start 29 #define GFX8_3DSTATE_VF_STATISTICS_CommandType_start 29 #define GFX75_3DSTATE_VF_STATISTICS_CommandType_start 29 #define GFX7_3DSTATE_VF_STATISTICS_CommandType_start 29 #define GFX6_3DSTATE_VF_STATISTICS_CommandType_start 29 #define GFX5_3DSTATE_VF_STATISTICS_CommandType_start 29 #define GFX45_3DSTATE_VF_STATISTICS_CommandType_start 29 #define GFX4_3DSTATE_VF_STATISTICS_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_STATISTICS_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 29; case 50: return 29; case 45: return 29; case 40: return 29; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_STATISTICS::Statistics Enable */ #define GFX125_3DSTATE_VF_STATISTICS_StatisticsEnable_bits 1 #define GFX12_3DSTATE_VF_STATISTICS_StatisticsEnable_bits 1 #define GFX11_3DSTATE_VF_STATISTICS_StatisticsEnable_bits 1 #define GFX9_3DSTATE_VF_STATISTICS_StatisticsEnable_bits 1 #define GFX8_3DSTATE_VF_STATISTICS_StatisticsEnable_bits 1 #define GFX75_3DSTATE_VF_STATISTICS_StatisticsEnable_bits 1 #define GFX7_3DSTATE_VF_STATISTICS_StatisticsEnable_bits 1 #define GFX6_3DSTATE_VF_STATISTICS_StatisticsEnable_bits 1 #define GFX5_3DSTATE_VF_STATISTICS_StatisticsEnable_bits 1 #define GFX45_3DSTATE_VF_STATISTICS_StatisticsEnable_bits 1 #define GFX4_3DSTATE_VF_STATISTICS_StatisticsEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_STATISTICS_StatisticsEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_STATISTICS_StatisticsEnable_start 0 #define GFX12_3DSTATE_VF_STATISTICS_StatisticsEnable_start 0 #define GFX11_3DSTATE_VF_STATISTICS_StatisticsEnable_start 0 #define GFX9_3DSTATE_VF_STATISTICS_StatisticsEnable_start 0 #define GFX8_3DSTATE_VF_STATISTICS_StatisticsEnable_start 0 #define GFX75_3DSTATE_VF_STATISTICS_StatisticsEnable_start 0 #define GFX7_3DSTATE_VF_STATISTICS_StatisticsEnable_start 0 #define GFX6_3DSTATE_VF_STATISTICS_StatisticsEnable_start 0 #define GFX5_3DSTATE_VF_STATISTICS_StatisticsEnable_start 0 #define GFX45_3DSTATE_VF_STATISTICS_StatisticsEnable_start 0 #define GFX4_3DSTATE_VF_STATISTICS_StatisticsEnable_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_STATISTICS_StatisticsEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_TOPOLOGY */ #define GFX125_3DSTATE_VF_TOPOLOGY_length 2 #define GFX12_3DSTATE_VF_TOPOLOGY_length 2 #define GFX11_3DSTATE_VF_TOPOLOGY_length 2 #define GFX9_3DSTATE_VF_TOPOLOGY_length 2 #define GFX8_3DSTATE_VF_TOPOLOGY_length 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_TOPOLOGY_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_TOPOLOGY::3D Command Opcode */ #define GFX125_3DSTATE_VF_TOPOLOGY_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_VF_TOPOLOGY_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_VF_TOPOLOGY_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_VF_TOPOLOGY_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_VF_TOPOLOGY_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_TOPOLOGY_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_TOPOLOGY_3DCommandOpcode_start 24 #define GFX12_3DSTATE_VF_TOPOLOGY_3DCommandOpcode_start 24 #define GFX11_3DSTATE_VF_TOPOLOGY_3DCommandOpcode_start 24 #define GFX9_3DSTATE_VF_TOPOLOGY_3DCommandOpcode_start 24 #define GFX8_3DSTATE_VF_TOPOLOGY_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_TOPOLOGY_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_TOPOLOGY::3D Command Sub Opcode */ #define GFX125_3DSTATE_VF_TOPOLOGY_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_VF_TOPOLOGY_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_VF_TOPOLOGY_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_VF_TOPOLOGY_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_VF_TOPOLOGY_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_TOPOLOGY_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_TOPOLOGY_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_VF_TOPOLOGY_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_VF_TOPOLOGY_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_VF_TOPOLOGY_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_VF_TOPOLOGY_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_TOPOLOGY_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_TOPOLOGY::Command SubType */ #define GFX125_3DSTATE_VF_TOPOLOGY_CommandSubType_bits 2 #define GFX12_3DSTATE_VF_TOPOLOGY_CommandSubType_bits 2 #define GFX11_3DSTATE_VF_TOPOLOGY_CommandSubType_bits 2 #define GFX9_3DSTATE_VF_TOPOLOGY_CommandSubType_bits 2 #define GFX8_3DSTATE_VF_TOPOLOGY_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_TOPOLOGY_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_TOPOLOGY_CommandSubType_start 27 #define GFX12_3DSTATE_VF_TOPOLOGY_CommandSubType_start 27 #define GFX11_3DSTATE_VF_TOPOLOGY_CommandSubType_start 27 #define GFX9_3DSTATE_VF_TOPOLOGY_CommandSubType_start 27 #define GFX8_3DSTATE_VF_TOPOLOGY_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_TOPOLOGY_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_TOPOLOGY::Command Type */ #define GFX125_3DSTATE_VF_TOPOLOGY_CommandType_bits 3 #define GFX12_3DSTATE_VF_TOPOLOGY_CommandType_bits 3 #define GFX11_3DSTATE_VF_TOPOLOGY_CommandType_bits 3 #define GFX9_3DSTATE_VF_TOPOLOGY_CommandType_bits 3 #define GFX8_3DSTATE_VF_TOPOLOGY_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_TOPOLOGY_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_TOPOLOGY_CommandType_start 29 #define GFX12_3DSTATE_VF_TOPOLOGY_CommandType_start 29 #define GFX11_3DSTATE_VF_TOPOLOGY_CommandType_start 29 #define GFX9_3DSTATE_VF_TOPOLOGY_CommandType_start 29 #define GFX8_3DSTATE_VF_TOPOLOGY_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_TOPOLOGY_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_TOPOLOGY::DWord Length */ #define GFX125_3DSTATE_VF_TOPOLOGY_DWordLength_bits 8 #define GFX12_3DSTATE_VF_TOPOLOGY_DWordLength_bits 8 #define GFX11_3DSTATE_VF_TOPOLOGY_DWordLength_bits 8 #define GFX9_3DSTATE_VF_TOPOLOGY_DWordLength_bits 8 #define GFX8_3DSTATE_VF_TOPOLOGY_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_TOPOLOGY_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_TOPOLOGY_DWordLength_start 0 #define GFX12_3DSTATE_VF_TOPOLOGY_DWordLength_start 0 #define GFX11_3DSTATE_VF_TOPOLOGY_DWordLength_start 0 #define GFX9_3DSTATE_VF_TOPOLOGY_DWordLength_start 0 #define GFX8_3DSTATE_VF_TOPOLOGY_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_TOPOLOGY_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VF_TOPOLOGY::Primitive Topology Type */ #define GFX125_3DSTATE_VF_TOPOLOGY_PrimitiveTopologyType_bits 6 #define GFX12_3DSTATE_VF_TOPOLOGY_PrimitiveTopologyType_bits 6 #define GFX11_3DSTATE_VF_TOPOLOGY_PrimitiveTopologyType_bits 6 #define GFX9_3DSTATE_VF_TOPOLOGY_PrimitiveTopologyType_bits 6 #define GFX8_3DSTATE_VF_TOPOLOGY_PrimitiveTopologyType_bits 6 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_TOPOLOGY_PrimitiveTopologyType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VF_TOPOLOGY_PrimitiveTopologyType_start 32 #define GFX12_3DSTATE_VF_TOPOLOGY_PrimitiveTopologyType_start 32 #define GFX11_3DSTATE_VF_TOPOLOGY_PrimitiveTopologyType_start 32 #define GFX9_3DSTATE_VF_TOPOLOGY_PrimitiveTopologyType_start 32 #define GFX8_3DSTATE_VF_TOPOLOGY_PrimitiveTopologyType_start 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VF_TOPOLOGY_PrimitiveTopologyType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VIEWPORT_STATE_POINTERS */ #define GFX6_3DSTATE_VIEWPORT_STATE_POINTERS_length 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VIEWPORT_STATE_POINTERS_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VIEWPORT_STATE_POINTERS::3D Command Opcode */ #define GFX6_3DSTATE_VIEWPORT_STATE_POINTERS_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VIEWPORT_STATE_POINTERS_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_VIEWPORT_STATE_POINTERS_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VIEWPORT_STATE_POINTERS_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 24; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VIEWPORT_STATE_POINTERS::3D Command Sub Opcode */ #define GFX6_3DSTATE_VIEWPORT_STATE_POINTERS_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VIEWPORT_STATE_POINTERS_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_VIEWPORT_STATE_POINTERS_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VIEWPORT_STATE_POINTERS_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 16; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VIEWPORT_STATE_POINTERS::CC Viewport State Change */ #define GFX6_3DSTATE_VIEWPORT_STATE_POINTERS_CCViewportStateChange_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VIEWPORT_STATE_POINTERS_CCViewportStateChange_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_VIEWPORT_STATE_POINTERS_CCViewportStateChange_start 12 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VIEWPORT_STATE_POINTERS_CCViewportStateChange_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 12; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VIEWPORT_STATE_POINTERS::CLIP Viewport State Change */ #define GFX6_3DSTATE_VIEWPORT_STATE_POINTERS_CLIPViewportStateChange_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VIEWPORT_STATE_POINTERS_CLIPViewportStateChange_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_VIEWPORT_STATE_POINTERS_CLIPViewportStateChange_start 10 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VIEWPORT_STATE_POINTERS_CLIPViewportStateChange_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 10; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VIEWPORT_STATE_POINTERS::Command SubType */ #define GFX6_3DSTATE_VIEWPORT_STATE_POINTERS_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VIEWPORT_STATE_POINTERS_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_VIEWPORT_STATE_POINTERS_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VIEWPORT_STATE_POINTERS_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 27; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VIEWPORT_STATE_POINTERS::Command Type */ #define GFX6_3DSTATE_VIEWPORT_STATE_POINTERS_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VIEWPORT_STATE_POINTERS_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_VIEWPORT_STATE_POINTERS_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VIEWPORT_STATE_POINTERS_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 29; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VIEWPORT_STATE_POINTERS::DWord Length */ #define GFX6_3DSTATE_VIEWPORT_STATE_POINTERS_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VIEWPORT_STATE_POINTERS_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_VIEWPORT_STATE_POINTERS_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VIEWPORT_STATE_POINTERS_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VIEWPORT_STATE_POINTERS::Pointer to CC_VIEWPORT */ #define GFX6_3DSTATE_VIEWPORT_STATE_POINTERS_PointertoCC_VIEWPORT_bits 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VIEWPORT_STATE_POINTERS_PointertoCC_VIEWPORT_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 27; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_VIEWPORT_STATE_POINTERS_PointertoCC_VIEWPORT_start 101 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VIEWPORT_STATE_POINTERS_PointertoCC_VIEWPORT_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 101; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VIEWPORT_STATE_POINTERS::Pointer to CLIP_VIEWPORT */ #define GFX6_3DSTATE_VIEWPORT_STATE_POINTERS_PointertoCLIP_VIEWPORT_bits 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VIEWPORT_STATE_POINTERS_PointertoCLIP_VIEWPORT_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 27; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_VIEWPORT_STATE_POINTERS_PointertoCLIP_VIEWPORT_start 37 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VIEWPORT_STATE_POINTERS_PointertoCLIP_VIEWPORT_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 37; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VIEWPORT_STATE_POINTERS::Pointer to SF_VIEWPORT */ #define GFX6_3DSTATE_VIEWPORT_STATE_POINTERS_PointertoSF_VIEWPORT_bits 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VIEWPORT_STATE_POINTERS_PointertoSF_VIEWPORT_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 27; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_VIEWPORT_STATE_POINTERS_PointertoSF_VIEWPORT_start 69 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VIEWPORT_STATE_POINTERS_PointertoSF_VIEWPORT_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 69; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VIEWPORT_STATE_POINTERS::SF Viewport State Change */ #define GFX6_3DSTATE_VIEWPORT_STATE_POINTERS_SFViewportStateChange_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VIEWPORT_STATE_POINTERS_SFViewportStateChange_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_VIEWPORT_STATE_POINTERS_SFViewportStateChange_start 11 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VIEWPORT_STATE_POINTERS_SFViewportStateChange_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 11; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VIEWPORT_STATE_POINTERS_CC */ #define GFX125_3DSTATE_VIEWPORT_STATE_POINTERS_CC_length 2 #define GFX12_3DSTATE_VIEWPORT_STATE_POINTERS_CC_length 2 #define GFX11_3DSTATE_VIEWPORT_STATE_POINTERS_CC_length 2 #define GFX9_3DSTATE_VIEWPORT_STATE_POINTERS_CC_length 2 #define GFX8_3DSTATE_VIEWPORT_STATE_POINTERS_CC_length 2 #define GFX75_3DSTATE_VIEWPORT_STATE_POINTERS_CC_length 2 #define GFX7_3DSTATE_VIEWPORT_STATE_POINTERS_CC_length 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VIEWPORT_STATE_POINTERS_CC_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VIEWPORT_STATE_POINTERS_CC::3D Command Opcode */ #define GFX125_3DSTATE_VIEWPORT_STATE_POINTERS_CC_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_VIEWPORT_STATE_POINTERS_CC_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_VIEWPORT_STATE_POINTERS_CC_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_VIEWPORT_STATE_POINTERS_CC_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_VIEWPORT_STATE_POINTERS_CC_3DCommandOpcode_bits 3 #define GFX75_3DSTATE_VIEWPORT_STATE_POINTERS_CC_3DCommandOpcode_bits 3 #define GFX7_3DSTATE_VIEWPORT_STATE_POINTERS_CC_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VIEWPORT_STATE_POINTERS_CC_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VIEWPORT_STATE_POINTERS_CC_3DCommandOpcode_start 24 #define GFX12_3DSTATE_VIEWPORT_STATE_POINTERS_CC_3DCommandOpcode_start 24 #define GFX11_3DSTATE_VIEWPORT_STATE_POINTERS_CC_3DCommandOpcode_start 24 #define GFX9_3DSTATE_VIEWPORT_STATE_POINTERS_CC_3DCommandOpcode_start 24 #define GFX8_3DSTATE_VIEWPORT_STATE_POINTERS_CC_3DCommandOpcode_start 24 #define GFX75_3DSTATE_VIEWPORT_STATE_POINTERS_CC_3DCommandOpcode_start 24 #define GFX7_3DSTATE_VIEWPORT_STATE_POINTERS_CC_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VIEWPORT_STATE_POINTERS_CC_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VIEWPORT_STATE_POINTERS_CC::3D Command Sub Opcode */ #define GFX125_3DSTATE_VIEWPORT_STATE_POINTERS_CC_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_VIEWPORT_STATE_POINTERS_CC_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_VIEWPORT_STATE_POINTERS_CC_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_VIEWPORT_STATE_POINTERS_CC_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_VIEWPORT_STATE_POINTERS_CC_3DCommandSubOpcode_bits 8 #define GFX75_3DSTATE_VIEWPORT_STATE_POINTERS_CC_3DCommandSubOpcode_bits 8 #define GFX7_3DSTATE_VIEWPORT_STATE_POINTERS_CC_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VIEWPORT_STATE_POINTERS_CC_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VIEWPORT_STATE_POINTERS_CC_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_VIEWPORT_STATE_POINTERS_CC_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_VIEWPORT_STATE_POINTERS_CC_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_VIEWPORT_STATE_POINTERS_CC_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_VIEWPORT_STATE_POINTERS_CC_3DCommandSubOpcode_start 16 #define GFX75_3DSTATE_VIEWPORT_STATE_POINTERS_CC_3DCommandSubOpcode_start 16 #define GFX7_3DSTATE_VIEWPORT_STATE_POINTERS_CC_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VIEWPORT_STATE_POINTERS_CC_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VIEWPORT_STATE_POINTERS_CC::CC Viewport Pointer */ #define GFX125_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CCViewportPointer_bits 27 #define GFX12_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CCViewportPointer_bits 27 #define GFX11_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CCViewportPointer_bits 27 #define GFX9_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CCViewportPointer_bits 27 #define GFX8_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CCViewportPointer_bits 27 #define GFX75_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CCViewportPointer_bits 27 #define GFX7_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CCViewportPointer_bits 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VIEWPORT_STATE_POINTERS_CC_CCViewportPointer_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CCViewportPointer_start 37 #define GFX12_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CCViewportPointer_start 37 #define GFX11_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CCViewportPointer_start 37 #define GFX9_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CCViewportPointer_start 37 #define GFX8_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CCViewportPointer_start 37 #define GFX75_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CCViewportPointer_start 37 #define GFX7_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CCViewportPointer_start 37 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VIEWPORT_STATE_POINTERS_CC_CCViewportPointer_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 37; case 120: return 37; case 110: return 37; case 90: return 37; case 80: return 37; case 75: return 37; case 70: return 37; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VIEWPORT_STATE_POINTERS_CC::Command SubType */ #define GFX125_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CommandSubType_bits 2 #define GFX12_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CommandSubType_bits 2 #define GFX11_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CommandSubType_bits 2 #define GFX9_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CommandSubType_bits 2 #define GFX8_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CommandSubType_bits 2 #define GFX75_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CommandSubType_bits 2 #define GFX7_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VIEWPORT_STATE_POINTERS_CC_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CommandSubType_start 27 #define GFX12_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CommandSubType_start 27 #define GFX11_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CommandSubType_start 27 #define GFX9_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CommandSubType_start 27 #define GFX8_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CommandSubType_start 27 #define GFX75_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CommandSubType_start 27 #define GFX7_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VIEWPORT_STATE_POINTERS_CC_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VIEWPORT_STATE_POINTERS_CC::Command Type */ #define GFX125_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CommandType_bits 3 #define GFX12_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CommandType_bits 3 #define GFX11_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CommandType_bits 3 #define GFX9_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CommandType_bits 3 #define GFX8_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CommandType_bits 3 #define GFX75_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CommandType_bits 3 #define GFX7_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VIEWPORT_STATE_POINTERS_CC_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CommandType_start 29 #define GFX12_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CommandType_start 29 #define GFX11_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CommandType_start 29 #define GFX9_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CommandType_start 29 #define GFX8_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CommandType_start 29 #define GFX75_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CommandType_start 29 #define GFX7_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VIEWPORT_STATE_POINTERS_CC_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VIEWPORT_STATE_POINTERS_CC::DWord Length */ #define GFX125_3DSTATE_VIEWPORT_STATE_POINTERS_CC_DWordLength_bits 8 #define GFX12_3DSTATE_VIEWPORT_STATE_POINTERS_CC_DWordLength_bits 8 #define GFX11_3DSTATE_VIEWPORT_STATE_POINTERS_CC_DWordLength_bits 8 #define GFX9_3DSTATE_VIEWPORT_STATE_POINTERS_CC_DWordLength_bits 8 #define GFX8_3DSTATE_VIEWPORT_STATE_POINTERS_CC_DWordLength_bits 8 #define GFX75_3DSTATE_VIEWPORT_STATE_POINTERS_CC_DWordLength_bits 8 #define GFX7_3DSTATE_VIEWPORT_STATE_POINTERS_CC_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VIEWPORT_STATE_POINTERS_CC_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VIEWPORT_STATE_POINTERS_CC_DWordLength_start 0 #define GFX12_3DSTATE_VIEWPORT_STATE_POINTERS_CC_DWordLength_start 0 #define GFX11_3DSTATE_VIEWPORT_STATE_POINTERS_CC_DWordLength_start 0 #define GFX9_3DSTATE_VIEWPORT_STATE_POINTERS_CC_DWordLength_start 0 #define GFX8_3DSTATE_VIEWPORT_STATE_POINTERS_CC_DWordLength_start 0 #define GFX75_3DSTATE_VIEWPORT_STATE_POINTERS_CC_DWordLength_start 0 #define GFX7_3DSTATE_VIEWPORT_STATE_POINTERS_CC_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VIEWPORT_STATE_POINTERS_CC_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP */ #define GFX125_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_length 2 #define GFX12_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_length 2 #define GFX11_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_length 2 #define GFX9_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_length 2 #define GFX8_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_length 2 #define GFX75_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_length 2 #define GFX7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_length 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP::3D Command Opcode */ #define GFX125_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_3DCommandOpcode_bits 3 #define GFX75_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_3DCommandOpcode_bits 3 #define GFX7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_3DCommandOpcode_start 24 #define GFX12_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_3DCommandOpcode_start 24 #define GFX11_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_3DCommandOpcode_start 24 #define GFX9_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_3DCommandOpcode_start 24 #define GFX8_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_3DCommandOpcode_start 24 #define GFX75_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_3DCommandOpcode_start 24 #define GFX7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP::3D Command Sub Opcode */ #define GFX125_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_3DCommandSubOpcode_bits 8 #define GFX75_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_3DCommandSubOpcode_bits 8 #define GFX7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_3DCommandSubOpcode_start 16 #define GFX75_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_3DCommandSubOpcode_start 16 #define GFX7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP::Command SubType */ #define GFX125_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_CommandSubType_bits 2 #define GFX12_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_CommandSubType_bits 2 #define GFX11_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_CommandSubType_bits 2 #define GFX9_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_CommandSubType_bits 2 #define GFX8_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_CommandSubType_bits 2 #define GFX75_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_CommandSubType_bits 2 #define GFX7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_CommandSubType_start 27 #define GFX12_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_CommandSubType_start 27 #define GFX11_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_CommandSubType_start 27 #define GFX9_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_CommandSubType_start 27 #define GFX8_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_CommandSubType_start 27 #define GFX75_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_CommandSubType_start 27 #define GFX7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP::Command Type */ #define GFX125_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_CommandType_bits 3 #define GFX12_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_CommandType_bits 3 #define GFX11_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_CommandType_bits 3 #define GFX9_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_CommandType_bits 3 #define GFX8_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_CommandType_bits 3 #define GFX75_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_CommandType_bits 3 #define GFX7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_CommandType_start 29 #define GFX12_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_CommandType_start 29 #define GFX11_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_CommandType_start 29 #define GFX9_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_CommandType_start 29 #define GFX8_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_CommandType_start 29 #define GFX75_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_CommandType_start 29 #define GFX7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP::DWord Length */ #define GFX125_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_DWordLength_bits 8 #define GFX12_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_DWordLength_bits 8 #define GFX11_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_DWordLength_bits 8 #define GFX9_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_DWordLength_bits 8 #define GFX8_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_DWordLength_bits 8 #define GFX75_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_DWordLength_bits 8 #define GFX7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_DWordLength_start 0 #define GFX12_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_DWordLength_start 0 #define GFX11_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_DWordLength_start 0 #define GFX9_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_DWordLength_start 0 #define GFX8_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_DWordLength_start 0 #define GFX75_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_DWordLength_start 0 #define GFX7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP::SF Clip Viewport Pointer */ #define GFX125_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_SFClipViewportPointer_bits 26 #define GFX12_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_SFClipViewportPointer_bits 26 #define GFX11_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_SFClipViewportPointer_bits 26 #define GFX9_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_SFClipViewportPointer_bits 26 #define GFX8_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_SFClipViewportPointer_bits 26 #define GFX75_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_SFClipViewportPointer_bits 26 #define GFX7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_SFClipViewportPointer_bits 26 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_SFClipViewportPointer_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 26; case 120: return 26; case 110: return 26; case 90: return 26; case 80: return 26; case 75: return 26; case 70: return 26; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_SFClipViewportPointer_start 38 #define GFX12_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_SFClipViewportPointer_start 38 #define GFX11_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_SFClipViewportPointer_start 38 #define GFX9_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_SFClipViewportPointer_start 38 #define GFX8_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_SFClipViewportPointer_start 38 #define GFX75_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_SFClipViewportPointer_start 38 #define GFX7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_SFClipViewportPointer_start 38 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_SFClipViewportPointer_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 38; case 120: return 38; case 110: return 38; case 90: return 38; case 80: return 38; case 75: return 38; case 70: return 38; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VS */ #define GFX125_3DSTATE_VS_length 9 #define GFX12_3DSTATE_VS_length 9 #define GFX11_3DSTATE_VS_length 9 #define GFX9_3DSTATE_VS_length 9 #define GFX8_3DSTATE_VS_length 9 #define GFX75_3DSTATE_VS_length 6 #define GFX7_3DSTATE_VS_length 6 #define GFX6_3DSTATE_VS_length 6 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VS_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 9; case 120: return 9; case 110: return 9; case 90: return 9; case 80: return 9; case 75: return 6; case 70: return 6; case 60: return 6; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VS::3D Command Opcode */ #define GFX125_3DSTATE_VS_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_VS_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_VS_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_VS_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_VS_3DCommandOpcode_bits 3 #define GFX75_3DSTATE_VS_3DCommandOpcode_bits 3 #define GFX7_3DSTATE_VS_3DCommandOpcode_bits 3 #define GFX6_3DSTATE_VS_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VS_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VS_3DCommandOpcode_start 24 #define GFX12_3DSTATE_VS_3DCommandOpcode_start 24 #define GFX11_3DSTATE_VS_3DCommandOpcode_start 24 #define GFX9_3DSTATE_VS_3DCommandOpcode_start 24 #define GFX8_3DSTATE_VS_3DCommandOpcode_start 24 #define GFX75_3DSTATE_VS_3DCommandOpcode_start 24 #define GFX7_3DSTATE_VS_3DCommandOpcode_start 24 #define GFX6_3DSTATE_VS_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VS_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 24; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VS::3D Command Sub Opcode */ #define GFX125_3DSTATE_VS_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_VS_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_VS_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_VS_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_VS_3DCommandSubOpcode_bits 8 #define GFX75_3DSTATE_VS_3DCommandSubOpcode_bits 8 #define GFX7_3DSTATE_VS_3DCommandSubOpcode_bits 8 #define GFX6_3DSTATE_VS_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VS_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VS_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_VS_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_VS_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_VS_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_VS_3DCommandSubOpcode_start 16 #define GFX75_3DSTATE_VS_3DCommandSubOpcode_start 16 #define GFX7_3DSTATE_VS_3DCommandSubOpcode_start 16 #define GFX6_3DSTATE_VS_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VS_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 16; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VS::Accesses UAV */ #define GFX125_3DSTATE_VS_AccessesUAV_bits 1 #define GFX12_3DSTATE_VS_AccessesUAV_bits 1 #define GFX11_3DSTATE_VS_AccessesUAV_bits 1 #define GFX9_3DSTATE_VS_AccessesUAV_bits 1 #define GFX8_3DSTATE_VS_AccessesUAV_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VS_AccessesUAV_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VS_AccessesUAV_start 108 #define GFX12_3DSTATE_VS_AccessesUAV_start 108 #define GFX11_3DSTATE_VS_AccessesUAV_start 108 #define GFX9_3DSTATE_VS_AccessesUAV_start 108 #define GFX8_3DSTATE_VS_AccessesUAV_start 108 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VS_AccessesUAV_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 108; case 120: return 108; case 110: return 108; case 90: return 108; case 80: return 108; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VS::Binding Table Entry Count */ #define GFX125_3DSTATE_VS_BindingTableEntryCount_bits 8 #define GFX12_3DSTATE_VS_BindingTableEntryCount_bits 8 #define GFX11_3DSTATE_VS_BindingTableEntryCount_bits 8 #define GFX9_3DSTATE_VS_BindingTableEntryCount_bits 8 #define GFX8_3DSTATE_VS_BindingTableEntryCount_bits 8 #define GFX75_3DSTATE_VS_BindingTableEntryCount_bits 8 #define GFX7_3DSTATE_VS_BindingTableEntryCount_bits 8 #define GFX6_3DSTATE_VS_BindingTableEntryCount_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VS_BindingTableEntryCount_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VS_BindingTableEntryCount_start 114 #define GFX12_3DSTATE_VS_BindingTableEntryCount_start 114 #define GFX11_3DSTATE_VS_BindingTableEntryCount_start 114 #define GFX9_3DSTATE_VS_BindingTableEntryCount_start 114 #define GFX8_3DSTATE_VS_BindingTableEntryCount_start 114 #define GFX75_3DSTATE_VS_BindingTableEntryCount_start 82 #define GFX7_3DSTATE_VS_BindingTableEntryCount_start 82 #define GFX6_3DSTATE_VS_BindingTableEntryCount_start 82 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VS_BindingTableEntryCount_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 114; case 120: return 114; case 110: return 114; case 90: return 114; case 80: return 114; case 75: return 82; case 70: return 82; case 60: return 82; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VS::Command SubType */ #define GFX125_3DSTATE_VS_CommandSubType_bits 2 #define GFX12_3DSTATE_VS_CommandSubType_bits 2 #define GFX11_3DSTATE_VS_CommandSubType_bits 2 #define GFX9_3DSTATE_VS_CommandSubType_bits 2 #define GFX8_3DSTATE_VS_CommandSubType_bits 2 #define GFX75_3DSTATE_VS_CommandSubType_bits 2 #define GFX7_3DSTATE_VS_CommandSubType_bits 2 #define GFX6_3DSTATE_VS_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VS_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VS_CommandSubType_start 27 #define GFX12_3DSTATE_VS_CommandSubType_start 27 #define GFX11_3DSTATE_VS_CommandSubType_start 27 #define GFX9_3DSTATE_VS_CommandSubType_start 27 #define GFX8_3DSTATE_VS_CommandSubType_start 27 #define GFX75_3DSTATE_VS_CommandSubType_start 27 #define GFX7_3DSTATE_VS_CommandSubType_start 27 #define GFX6_3DSTATE_VS_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VS_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 27; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VS::Command Type */ #define GFX125_3DSTATE_VS_CommandType_bits 3 #define GFX12_3DSTATE_VS_CommandType_bits 3 #define GFX11_3DSTATE_VS_CommandType_bits 3 #define GFX9_3DSTATE_VS_CommandType_bits 3 #define GFX8_3DSTATE_VS_CommandType_bits 3 #define GFX75_3DSTATE_VS_CommandType_bits 3 #define GFX7_3DSTATE_VS_CommandType_bits 3 #define GFX6_3DSTATE_VS_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VS_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VS_CommandType_start 29 #define GFX12_3DSTATE_VS_CommandType_start 29 #define GFX11_3DSTATE_VS_CommandType_start 29 #define GFX9_3DSTATE_VS_CommandType_start 29 #define GFX8_3DSTATE_VS_CommandType_start 29 #define GFX75_3DSTATE_VS_CommandType_start 29 #define GFX7_3DSTATE_VS_CommandType_start 29 #define GFX6_3DSTATE_VS_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VS_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 29; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VS::DWord Length */ #define GFX125_3DSTATE_VS_DWordLength_bits 8 #define GFX12_3DSTATE_VS_DWordLength_bits 8 #define GFX11_3DSTATE_VS_DWordLength_bits 8 #define GFX9_3DSTATE_VS_DWordLength_bits 8 #define GFX8_3DSTATE_VS_DWordLength_bits 8 #define GFX75_3DSTATE_VS_DWordLength_bits 8 #define GFX7_3DSTATE_VS_DWordLength_bits 8 #define GFX6_3DSTATE_VS_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VS_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VS_DWordLength_start 0 #define GFX12_3DSTATE_VS_DWordLength_start 0 #define GFX11_3DSTATE_VS_DWordLength_start 0 #define GFX9_3DSTATE_VS_DWordLength_start 0 #define GFX8_3DSTATE_VS_DWordLength_start 0 #define GFX75_3DSTATE_VS_DWordLength_start 0 #define GFX7_3DSTATE_VS_DWordLength_start 0 #define GFX6_3DSTATE_VS_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VS_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VS::Dispatch GRF Start Register For URB Data */ #define GFX125_3DSTATE_VS_DispatchGRFStartRegisterForURBData_bits 5 #define GFX12_3DSTATE_VS_DispatchGRFStartRegisterForURBData_bits 5 #define GFX11_3DSTATE_VS_DispatchGRFStartRegisterForURBData_bits 5 #define GFX9_3DSTATE_VS_DispatchGRFStartRegisterForURBData_bits 5 #define GFX8_3DSTATE_VS_DispatchGRFStartRegisterForURBData_bits 5 #define GFX75_3DSTATE_VS_DispatchGRFStartRegisterForURBData_bits 5 #define GFX7_3DSTATE_VS_DispatchGRFStartRegisterForURBData_bits 5 #define GFX6_3DSTATE_VS_DispatchGRFStartRegisterForURBData_bits 5 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VS_DispatchGRFStartRegisterForURBData_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 5; case 110: return 5; case 90: return 5; case 80: return 5; case 75: return 5; case 70: return 5; case 60: return 5; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VS_DispatchGRFStartRegisterForURBData_start 212 #define GFX12_3DSTATE_VS_DispatchGRFStartRegisterForURBData_start 212 #define GFX11_3DSTATE_VS_DispatchGRFStartRegisterForURBData_start 212 #define GFX9_3DSTATE_VS_DispatchGRFStartRegisterForURBData_start 212 #define GFX8_3DSTATE_VS_DispatchGRFStartRegisterForURBData_start 212 #define GFX75_3DSTATE_VS_DispatchGRFStartRegisterForURBData_start 148 #define GFX7_3DSTATE_VS_DispatchGRFStartRegisterForURBData_start 148 #define GFX6_3DSTATE_VS_DispatchGRFStartRegisterForURBData_start 148 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VS_DispatchGRFStartRegisterForURBData_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 212; case 120: return 212; case 110: return 212; case 90: return 212; case 80: return 212; case 75: return 148; case 70: return 148; case 60: return 148; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VS::Enable */ #define GFX125_3DSTATE_VS_Enable_bits 1 #define GFX12_3DSTATE_VS_Enable_bits 1 #define GFX11_3DSTATE_VS_Enable_bits 1 #define GFX9_3DSTATE_VS_Enable_bits 1 #define GFX8_3DSTATE_VS_Enable_bits 1 #define GFX75_3DSTATE_VS_Enable_bits 1 #define GFX7_3DSTATE_VS_Enable_bits 1 #define GFX6_3DSTATE_VS_Enable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VS_Enable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VS_Enable_start 224 #define GFX12_3DSTATE_VS_Enable_start 224 #define GFX11_3DSTATE_VS_Enable_start 224 #define GFX9_3DSTATE_VS_Enable_start 224 #define GFX8_3DSTATE_VS_Enable_start 224 #define GFX75_3DSTATE_VS_Enable_start 160 #define GFX7_3DSTATE_VS_Enable_start 160 #define GFX6_3DSTATE_VS_Enable_start 160 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VS_Enable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 224; case 120: return 224; case 110: return 224; case 90: return 224; case 80: return 224; case 75: return 160; case 70: return 160; case 60: return 160; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VS::Floating Point Mode */ #define GFX125_3DSTATE_VS_FloatingPointMode_bits 1 #define GFX12_3DSTATE_VS_FloatingPointMode_bits 1 #define GFX11_3DSTATE_VS_FloatingPointMode_bits 1 #define GFX9_3DSTATE_VS_FloatingPointMode_bits 1 #define GFX8_3DSTATE_VS_FloatingPointMode_bits 1 #define GFX75_3DSTATE_VS_FloatingPointMode_bits 1 #define GFX7_3DSTATE_VS_FloatingPointMode_bits 1 #define GFX6_3DSTATE_VS_FloatingPointMode_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VS_FloatingPointMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VS_FloatingPointMode_start 112 #define GFX12_3DSTATE_VS_FloatingPointMode_start 112 #define GFX11_3DSTATE_VS_FloatingPointMode_start 112 #define GFX9_3DSTATE_VS_FloatingPointMode_start 112 #define GFX8_3DSTATE_VS_FloatingPointMode_start 112 #define GFX75_3DSTATE_VS_FloatingPointMode_start 80 #define GFX7_3DSTATE_VS_FloatingPointMode_start 80 #define GFX6_3DSTATE_VS_FloatingPointMode_start 80 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VS_FloatingPointMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 112; case 120: return 112; case 110: return 112; case 90: return 112; case 80: return 112; case 75: return 80; case 70: return 80; case 60: return 80; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VS::Illegal Opcode Exception Enable */ #define GFX125_3DSTATE_VS_IllegalOpcodeExceptionEnable_bits 1 #define GFX12_3DSTATE_VS_IllegalOpcodeExceptionEnable_bits 1 #define GFX11_3DSTATE_VS_IllegalOpcodeExceptionEnable_bits 1 #define GFX9_3DSTATE_VS_IllegalOpcodeExceptionEnable_bits 1 #define GFX8_3DSTATE_VS_IllegalOpcodeExceptionEnable_bits 1 #define GFX75_3DSTATE_VS_IllegalOpcodeExceptionEnable_bits 1 #define GFX7_3DSTATE_VS_IllegalOpcodeExceptionEnable_bits 1 #define GFX6_3DSTATE_VS_IllegalOpcodeExceptionEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VS_IllegalOpcodeExceptionEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VS_IllegalOpcodeExceptionEnable_start 109 #define GFX12_3DSTATE_VS_IllegalOpcodeExceptionEnable_start 109 #define GFX11_3DSTATE_VS_IllegalOpcodeExceptionEnable_start 109 #define GFX9_3DSTATE_VS_IllegalOpcodeExceptionEnable_start 109 #define GFX8_3DSTATE_VS_IllegalOpcodeExceptionEnable_start 109 #define GFX75_3DSTATE_VS_IllegalOpcodeExceptionEnable_start 77 #define GFX7_3DSTATE_VS_IllegalOpcodeExceptionEnable_start 77 #define GFX6_3DSTATE_VS_IllegalOpcodeExceptionEnable_start 77 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VS_IllegalOpcodeExceptionEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 109; case 120: return 109; case 110: return 109; case 90: return 109; case 80: return 109; case 75: return 77; case 70: return 77; case 60: return 77; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VS::Kernel Start Pointer */ #define GFX125_3DSTATE_VS_KernelStartPointer_bits 58 #define GFX12_3DSTATE_VS_KernelStartPointer_bits 58 #define GFX11_3DSTATE_VS_KernelStartPointer_bits 58 #define GFX9_3DSTATE_VS_KernelStartPointer_bits 58 #define GFX8_3DSTATE_VS_KernelStartPointer_bits 58 #define GFX75_3DSTATE_VS_KernelStartPointer_bits 26 #define GFX7_3DSTATE_VS_KernelStartPointer_bits 26 #define GFX6_3DSTATE_VS_KernelStartPointer_bits 26 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VS_KernelStartPointer_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 58; case 120: return 58; case 110: return 58; case 90: return 58; case 80: return 58; case 75: return 26; case 70: return 26; case 60: return 26; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VS_KernelStartPointer_start 38 #define GFX12_3DSTATE_VS_KernelStartPointer_start 38 #define GFX11_3DSTATE_VS_KernelStartPointer_start 38 #define GFX9_3DSTATE_VS_KernelStartPointer_start 38 #define GFX8_3DSTATE_VS_KernelStartPointer_start 38 #define GFX75_3DSTATE_VS_KernelStartPointer_start 38 #define GFX7_3DSTATE_VS_KernelStartPointer_start 38 #define GFX6_3DSTATE_VS_KernelStartPointer_start 38 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VS_KernelStartPointer_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 38; case 120: return 38; case 110: return 38; case 90: return 38; case 80: return 38; case 75: return 38; case 70: return 38; case 60: return 38; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VS::Maximum Number of Threads */ #define GFX125_3DSTATE_VS_MaximumNumberofThreads_bits 10 #define GFX12_3DSTATE_VS_MaximumNumberofThreads_bits 10 #define GFX11_3DSTATE_VS_MaximumNumberofThreads_bits 10 #define GFX9_3DSTATE_VS_MaximumNumberofThreads_bits 9 #define GFX8_3DSTATE_VS_MaximumNumberofThreads_bits 9 #define GFX75_3DSTATE_VS_MaximumNumberofThreads_bits 9 #define GFX7_3DSTATE_VS_MaximumNumberofThreads_bits 7 #define GFX6_3DSTATE_VS_MaximumNumberofThreads_bits 7 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VS_MaximumNumberofThreads_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 10; case 120: return 10; case 110: return 10; case 90: return 9; case 80: return 9; case 75: return 9; case 70: return 7; case 60: return 7; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VS_MaximumNumberofThreads_start 246 #define GFX12_3DSTATE_VS_MaximumNumberofThreads_start 246 #define GFX11_3DSTATE_VS_MaximumNumberofThreads_start 246 #define GFX9_3DSTATE_VS_MaximumNumberofThreads_start 247 #define GFX8_3DSTATE_VS_MaximumNumberofThreads_start 247 #define GFX75_3DSTATE_VS_MaximumNumberofThreads_start 183 #define GFX7_3DSTATE_VS_MaximumNumberofThreads_start 185 #define GFX6_3DSTATE_VS_MaximumNumberofThreads_start 185 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VS_MaximumNumberofThreads_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 246; case 120: return 246; case 110: return 246; case 90: return 247; case 80: return 247; case 75: return 183; case 70: return 185; case 60: return 185; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VS::Per-Thread Scratch Space */ #define GFX12_3DSTATE_VS_PerThreadScratchSpace_bits 4 #define GFX11_3DSTATE_VS_PerThreadScratchSpace_bits 4 #define GFX9_3DSTATE_VS_PerThreadScratchSpace_bits 4 #define GFX8_3DSTATE_VS_PerThreadScratchSpace_bits 4 #define GFX75_3DSTATE_VS_PerThreadScratchSpace_bits 4 #define GFX7_3DSTATE_VS_PerThreadScratchSpace_bits 4 #define GFX6_3DSTATE_VS_PerThreadScratchSpace_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VS_PerThreadScratchSpace_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 4; case 70: return 4; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_3DSTATE_VS_PerThreadScratchSpace_start 128 #define GFX11_3DSTATE_VS_PerThreadScratchSpace_start 128 #define GFX9_3DSTATE_VS_PerThreadScratchSpace_start 128 #define GFX8_3DSTATE_VS_PerThreadScratchSpace_start 128 #define GFX75_3DSTATE_VS_PerThreadScratchSpace_start 96 #define GFX7_3DSTATE_VS_PerThreadScratchSpace_start 96 #define GFX6_3DSTATE_VS_PerThreadScratchSpace_start 96 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VS_PerThreadScratchSpace_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 128; case 110: return 128; case 90: return 128; case 80: return 128; case 75: return 96; case 70: return 96; case 60: return 96; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VS::SIMD8 Dispatch Enable */ #define GFX125_3DSTATE_VS_SIMD8DispatchEnable_bits 1 #define GFX12_3DSTATE_VS_SIMD8DispatchEnable_bits 1 #define GFX11_3DSTATE_VS_SIMD8DispatchEnable_bits 1 #define GFX9_3DSTATE_VS_SIMD8DispatchEnable_bits 1 #define GFX8_3DSTATE_VS_SIMD8DispatchEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VS_SIMD8DispatchEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VS_SIMD8DispatchEnable_start 226 #define GFX12_3DSTATE_VS_SIMD8DispatchEnable_start 226 #define GFX11_3DSTATE_VS_SIMD8DispatchEnable_start 226 #define GFX9_3DSTATE_VS_SIMD8DispatchEnable_start 226 #define GFX8_3DSTATE_VS_SIMD8DispatchEnable_start 226 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VS_SIMD8DispatchEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 226; case 120: return 226; case 110: return 226; case 90: return 226; case 80: return 226; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VS::SIMD8 Single Instance Dispatch Enable */ #define GFX125_3DSTATE_VS_SIMD8SingleInstanceDispatchEnable_bits 1 #define GFX12_3DSTATE_VS_SIMD8SingleInstanceDispatchEnable_bits 1 #define GFX11_3DSTATE_VS_SIMD8SingleInstanceDispatchEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VS_SIMD8SingleInstanceDispatchEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VS_SIMD8SingleInstanceDispatchEnable_start 233 #define GFX12_3DSTATE_VS_SIMD8SingleInstanceDispatchEnable_start 233 #define GFX11_3DSTATE_VS_SIMD8SingleInstanceDispatchEnable_start 233 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VS_SIMD8SingleInstanceDispatchEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 233; case 120: return 233; case 110: return 233; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VS::Sampler Count */ #define GFX125_3DSTATE_VS_SamplerCount_bits 3 #define GFX12_3DSTATE_VS_SamplerCount_bits 3 #define GFX11_3DSTATE_VS_SamplerCount_bits 3 #define GFX9_3DSTATE_VS_SamplerCount_bits 3 #define GFX8_3DSTATE_VS_SamplerCount_bits 3 #define GFX75_3DSTATE_VS_SamplerCount_bits 3 #define GFX7_3DSTATE_VS_SamplerCount_bits 3 #define GFX6_3DSTATE_VS_SamplerCount_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VS_SamplerCount_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VS_SamplerCount_start 123 #define GFX12_3DSTATE_VS_SamplerCount_start 123 #define GFX11_3DSTATE_VS_SamplerCount_start 123 #define GFX9_3DSTATE_VS_SamplerCount_start 123 #define GFX8_3DSTATE_VS_SamplerCount_start 123 #define GFX75_3DSTATE_VS_SamplerCount_start 91 #define GFX7_3DSTATE_VS_SamplerCount_start 91 #define GFX6_3DSTATE_VS_SamplerCount_start 91 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VS_SamplerCount_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 123; case 120: return 123; case 110: return 123; case 90: return 123; case 80: return 123; case 75: return 91; case 70: return 91; case 60: return 91; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VS::Scratch Space Base Pointer */ #define GFX12_3DSTATE_VS_ScratchSpaceBasePointer_bits 54 #define GFX11_3DSTATE_VS_ScratchSpaceBasePointer_bits 54 #define GFX9_3DSTATE_VS_ScratchSpaceBasePointer_bits 54 #define GFX8_3DSTATE_VS_ScratchSpaceBasePointer_bits 54 #define GFX75_3DSTATE_VS_ScratchSpaceBasePointer_bits 22 #define GFX7_3DSTATE_VS_ScratchSpaceBasePointer_bits 22 #define GFX6_3DSTATE_VS_ScratchSpaceBasePointer_bits 22 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VS_ScratchSpaceBasePointer_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 54; case 110: return 54; case 90: return 54; case 80: return 54; case 75: return 22; case 70: return 22; case 60: return 22; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_3DSTATE_VS_ScratchSpaceBasePointer_start 138 #define GFX11_3DSTATE_VS_ScratchSpaceBasePointer_start 138 #define GFX9_3DSTATE_VS_ScratchSpaceBasePointer_start 138 #define GFX8_3DSTATE_VS_ScratchSpaceBasePointer_start 138 #define GFX75_3DSTATE_VS_ScratchSpaceBasePointer_start 106 #define GFX7_3DSTATE_VS_ScratchSpaceBasePointer_start 106 #define GFX6_3DSTATE_VS_ScratchSpaceBasePointer_start 106 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VS_ScratchSpaceBasePointer_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 138; case 110: return 138; case 90: return 138; case 80: return 138; case 75: return 106; case 70: return 106; case 60: return 106; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VS::Scratch Space Buffer */ #define GFX125_3DSTATE_VS_ScratchSpaceBuffer_bits 22 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VS_ScratchSpaceBuffer_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 22; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VS_ScratchSpaceBuffer_start 138 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VS_ScratchSpaceBuffer_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 138; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VS::Single Vertex Dispatch */ #define GFX9_3DSTATE_VS_SingleVertexDispatch_bits 1 #define GFX8_3DSTATE_VS_SingleVertexDispatch_bits 1 #define GFX75_3DSTATE_VS_SingleVertexDispatch_bits 1 #define GFX7_3DSTATE_VS_SingleVertexDispatch_bits 1 #define GFX6_3DSTATE_VS_SingleVertexDispatch_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VS_SingleVertexDispatch_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_3DSTATE_VS_SingleVertexDispatch_start 127 #define GFX8_3DSTATE_VS_SingleVertexDispatch_start 127 #define GFX75_3DSTATE_VS_SingleVertexDispatch_start 95 #define GFX7_3DSTATE_VS_SingleVertexDispatch_start 95 #define GFX6_3DSTATE_VS_SingleVertexDispatch_start 95 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VS_SingleVertexDispatch_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 127; case 80: return 127; case 75: return 95; case 70: return 95; case 60: return 95; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VS::Software Exception Enable */ #define GFX125_3DSTATE_VS_SoftwareExceptionEnable_bits 1 #define GFX12_3DSTATE_VS_SoftwareExceptionEnable_bits 1 #define GFX11_3DSTATE_VS_SoftwareExceptionEnable_bits 1 #define GFX9_3DSTATE_VS_SoftwareExceptionEnable_bits 1 #define GFX8_3DSTATE_VS_SoftwareExceptionEnable_bits 1 #define GFX75_3DSTATE_VS_SoftwareExceptionEnable_bits 1 #define GFX7_3DSTATE_VS_SoftwareExceptionEnable_bits 1 #define GFX6_3DSTATE_VS_SoftwareExceptionEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VS_SoftwareExceptionEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VS_SoftwareExceptionEnable_start 103 #define GFX12_3DSTATE_VS_SoftwareExceptionEnable_start 103 #define GFX11_3DSTATE_VS_SoftwareExceptionEnable_start 103 #define GFX9_3DSTATE_VS_SoftwareExceptionEnable_start 103 #define GFX8_3DSTATE_VS_SoftwareExceptionEnable_start 103 #define GFX75_3DSTATE_VS_SoftwareExceptionEnable_start 71 #define GFX7_3DSTATE_VS_SoftwareExceptionEnable_start 71 #define GFX6_3DSTATE_VS_SoftwareExceptionEnable_start 71 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VS_SoftwareExceptionEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 103; case 120: return 103; case 110: return 103; case 90: return 103; case 80: return 103; case 75: return 71; case 70: return 71; case 60: return 71; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VS::Statistics Enable */ #define GFX125_3DSTATE_VS_StatisticsEnable_bits 1 #define GFX12_3DSTATE_VS_StatisticsEnable_bits 1 #define GFX11_3DSTATE_VS_StatisticsEnable_bits 1 #define GFX9_3DSTATE_VS_StatisticsEnable_bits 1 #define GFX8_3DSTATE_VS_StatisticsEnable_bits 1 #define GFX75_3DSTATE_VS_StatisticsEnable_bits 1 #define GFX7_3DSTATE_VS_StatisticsEnable_bits 1 #define GFX6_3DSTATE_VS_StatisticsEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VS_StatisticsEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VS_StatisticsEnable_start 234 #define GFX12_3DSTATE_VS_StatisticsEnable_start 234 #define GFX11_3DSTATE_VS_StatisticsEnable_start 234 #define GFX9_3DSTATE_VS_StatisticsEnable_start 234 #define GFX8_3DSTATE_VS_StatisticsEnable_start 234 #define GFX75_3DSTATE_VS_StatisticsEnable_start 170 #define GFX7_3DSTATE_VS_StatisticsEnable_start 170 #define GFX6_3DSTATE_VS_StatisticsEnable_start 170 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VS_StatisticsEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 234; case 120: return 234; case 110: return 234; case 90: return 234; case 80: return 234; case 75: return 170; case 70: return 170; case 60: return 170; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VS::Thread Dispatch Priority */ #define GFX125_3DSTATE_VS_ThreadDispatchPriority_bits 1 #define GFX12_3DSTATE_VS_ThreadDispatchPriority_bits 1 #define GFX11_3DSTATE_VS_ThreadDispatchPriority_bits 1 #define GFX9_3DSTATE_VS_ThreadDispatchPriority_bits 1 #define GFX8_3DSTATE_VS_ThreadDispatchPriority_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VS_ThreadDispatchPriority_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VS_ThreadDispatchPriority_start 113 #define GFX12_3DSTATE_VS_ThreadDispatchPriority_start 113 #define GFX11_3DSTATE_VS_ThreadDispatchPriority_start 113 #define GFX9_3DSTATE_VS_ThreadDispatchPriority_start 113 #define GFX8_3DSTATE_VS_ThreadDispatchPriority_start 113 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VS_ThreadDispatchPriority_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 113; case 120: return 113; case 110: return 113; case 90: return 113; case 80: return 113; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VS::Thread Priority */ #define GFX75_3DSTATE_VS_ThreadPriority_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VS_ThreadPriority_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_VS_ThreadPriority_start 81 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VS_ThreadPriority_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 81; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VS::User Clip Distance Clip Test Enable Bitmask */ #define GFX125_3DSTATE_VS_UserClipDistanceClipTestEnableBitmask_bits 8 #define GFX12_3DSTATE_VS_UserClipDistanceClipTestEnableBitmask_bits 8 #define GFX11_3DSTATE_VS_UserClipDistanceClipTestEnableBitmask_bits 8 #define GFX9_3DSTATE_VS_UserClipDistanceClipTestEnableBitmask_bits 8 #define GFX8_3DSTATE_VS_UserClipDistanceClipTestEnableBitmask_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VS_UserClipDistanceClipTestEnableBitmask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VS_UserClipDistanceClipTestEnableBitmask_start 264 #define GFX12_3DSTATE_VS_UserClipDistanceClipTestEnableBitmask_start 264 #define GFX11_3DSTATE_VS_UserClipDistanceClipTestEnableBitmask_start 264 #define GFX9_3DSTATE_VS_UserClipDistanceClipTestEnableBitmask_start 264 #define GFX8_3DSTATE_VS_UserClipDistanceClipTestEnableBitmask_start 264 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VS_UserClipDistanceClipTestEnableBitmask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 264; case 120: return 264; case 110: return 264; case 90: return 264; case 80: return 264; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VS::User Clip Distance Cull Test Enable Bitmask */ #define GFX125_3DSTATE_VS_UserClipDistanceCullTestEnableBitmask_bits 8 #define GFX12_3DSTATE_VS_UserClipDistanceCullTestEnableBitmask_bits 8 #define GFX11_3DSTATE_VS_UserClipDistanceCullTestEnableBitmask_bits 8 #define GFX9_3DSTATE_VS_UserClipDistanceCullTestEnableBitmask_bits 8 #define GFX8_3DSTATE_VS_UserClipDistanceCullTestEnableBitmask_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VS_UserClipDistanceCullTestEnableBitmask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VS_UserClipDistanceCullTestEnableBitmask_start 256 #define GFX12_3DSTATE_VS_UserClipDistanceCullTestEnableBitmask_start 256 #define GFX11_3DSTATE_VS_UserClipDistanceCullTestEnableBitmask_start 256 #define GFX9_3DSTATE_VS_UserClipDistanceCullTestEnableBitmask_start 256 #define GFX8_3DSTATE_VS_UserClipDistanceCullTestEnableBitmask_start 256 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VS_UserClipDistanceCullTestEnableBitmask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 256; case 120: return 256; case 110: return 256; case 90: return 256; case 80: return 256; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VS::VS accesses UAV */ #define GFX75_3DSTATE_VS_VSaccessesUAV_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VS_VSaccessesUAV_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_VS_VSaccessesUAV_start 76 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VS_VSaccessesUAV_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 76; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VS::Vector Mask Enable */ #define GFX125_3DSTATE_VS_VectorMaskEnable_bits 1 #define GFX12_3DSTATE_VS_VectorMaskEnable_bits 1 #define GFX11_3DSTATE_VS_VectorMaskEnable_bits 1 #define GFX9_3DSTATE_VS_VectorMaskEnable_bits 1 #define GFX8_3DSTATE_VS_VectorMaskEnable_bits 1 #define GFX75_3DSTATE_VS_VectorMaskEnable_bits 1 #define GFX7_3DSTATE_VS_VectorMaskEnable_bits 1 #define GFX6_3DSTATE_VS_VectorMaskEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VS_VectorMaskEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VS_VectorMaskEnable_start 126 #define GFX12_3DSTATE_VS_VectorMaskEnable_start 126 #define GFX11_3DSTATE_VS_VectorMaskEnable_start 126 #define GFX9_3DSTATE_VS_VectorMaskEnable_start 126 #define GFX8_3DSTATE_VS_VectorMaskEnable_start 126 #define GFX75_3DSTATE_VS_VectorMaskEnable_start 94 #define GFX7_3DSTATE_VS_VectorMaskEnable_start 94 #define GFX6_3DSTATE_VS_VectorMaskEnable_start 94 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VS_VectorMaskEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 126; case 120: return 126; case 110: return 126; case 90: return 126; case 80: return 126; case 75: return 94; case 70: return 94; case 60: return 94; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VS::Vertex Cache Disable */ #define GFX125_3DSTATE_VS_VertexCacheDisable_bits 1 #define GFX12_3DSTATE_VS_VertexCacheDisable_bits 1 #define GFX11_3DSTATE_VS_VertexCacheDisable_bits 1 #define GFX9_3DSTATE_VS_VertexCacheDisable_bits 1 #define GFX8_3DSTATE_VS_VertexCacheDisable_bits 1 #define GFX75_3DSTATE_VS_VertexCacheDisable_bits 1 #define GFX7_3DSTATE_VS_VertexCacheDisable_bits 1 #define GFX6_3DSTATE_VS_VertexCacheDisable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VS_VertexCacheDisable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VS_VertexCacheDisable_start 225 #define GFX12_3DSTATE_VS_VertexCacheDisable_start 225 #define GFX11_3DSTATE_VS_VertexCacheDisable_start 225 #define GFX9_3DSTATE_VS_VertexCacheDisable_start 225 #define GFX8_3DSTATE_VS_VertexCacheDisable_start 225 #define GFX75_3DSTATE_VS_VertexCacheDisable_start 161 #define GFX7_3DSTATE_VS_VertexCacheDisable_start 161 #define GFX6_3DSTATE_VS_VertexCacheDisable_start 161 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VS_VertexCacheDisable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 225; case 120: return 225; case 110: return 225; case 90: return 225; case 80: return 225; case 75: return 161; case 70: return 161; case 60: return 161; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VS::Vertex URB Entry Output Length */ #define GFX125_3DSTATE_VS_VertexURBEntryOutputLength_bits 5 #define GFX12_3DSTATE_VS_VertexURBEntryOutputLength_bits 5 #define GFX11_3DSTATE_VS_VertexURBEntryOutputLength_bits 5 #define GFX9_3DSTATE_VS_VertexURBEntryOutputLength_bits 5 #define GFX8_3DSTATE_VS_VertexURBEntryOutputLength_bits 5 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VS_VertexURBEntryOutputLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 5; case 110: return 5; case 90: return 5; case 80: return 5; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VS_VertexURBEntryOutputLength_start 272 #define GFX12_3DSTATE_VS_VertexURBEntryOutputLength_start 272 #define GFX11_3DSTATE_VS_VertexURBEntryOutputLength_start 272 #define GFX9_3DSTATE_VS_VertexURBEntryOutputLength_start 272 #define GFX8_3DSTATE_VS_VertexURBEntryOutputLength_start 272 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VS_VertexURBEntryOutputLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 272; case 120: return 272; case 110: return 272; case 90: return 272; case 80: return 272; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VS::Vertex URB Entry Output Read Offset */ #define GFX125_3DSTATE_VS_VertexURBEntryOutputReadOffset_bits 6 #define GFX12_3DSTATE_VS_VertexURBEntryOutputReadOffset_bits 6 #define GFX11_3DSTATE_VS_VertexURBEntryOutputReadOffset_bits 6 #define GFX9_3DSTATE_VS_VertexURBEntryOutputReadOffset_bits 6 #define GFX8_3DSTATE_VS_VertexURBEntryOutputReadOffset_bits 6 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VS_VertexURBEntryOutputReadOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VS_VertexURBEntryOutputReadOffset_start 277 #define GFX12_3DSTATE_VS_VertexURBEntryOutputReadOffset_start 277 #define GFX11_3DSTATE_VS_VertexURBEntryOutputReadOffset_start 277 #define GFX9_3DSTATE_VS_VertexURBEntryOutputReadOffset_start 277 #define GFX8_3DSTATE_VS_VertexURBEntryOutputReadOffset_start 277 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VS_VertexURBEntryOutputReadOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 277; case 120: return 277; case 110: return 277; case 90: return 277; case 80: return 277; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VS::Vertex URB Entry Read Length */ #define GFX125_3DSTATE_VS_VertexURBEntryReadLength_bits 6 #define GFX12_3DSTATE_VS_VertexURBEntryReadLength_bits 6 #define GFX11_3DSTATE_VS_VertexURBEntryReadLength_bits 6 #define GFX9_3DSTATE_VS_VertexURBEntryReadLength_bits 6 #define GFX8_3DSTATE_VS_VertexURBEntryReadLength_bits 6 #define GFX75_3DSTATE_VS_VertexURBEntryReadLength_bits 6 #define GFX7_3DSTATE_VS_VertexURBEntryReadLength_bits 6 #define GFX6_3DSTATE_VS_VertexURBEntryReadLength_bits 6 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VS_VertexURBEntryReadLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 6; case 60: return 6; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VS_VertexURBEntryReadLength_start 203 #define GFX12_3DSTATE_VS_VertexURBEntryReadLength_start 203 #define GFX11_3DSTATE_VS_VertexURBEntryReadLength_start 203 #define GFX9_3DSTATE_VS_VertexURBEntryReadLength_start 203 #define GFX8_3DSTATE_VS_VertexURBEntryReadLength_start 203 #define GFX75_3DSTATE_VS_VertexURBEntryReadLength_start 139 #define GFX7_3DSTATE_VS_VertexURBEntryReadLength_start 139 #define GFX6_3DSTATE_VS_VertexURBEntryReadLength_start 139 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VS_VertexURBEntryReadLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 203; case 120: return 203; case 110: return 203; case 90: return 203; case 80: return 203; case 75: return 139; case 70: return 139; case 60: return 139; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_VS::Vertex URB Entry Read Offset */ #define GFX125_3DSTATE_VS_VertexURBEntryReadOffset_bits 6 #define GFX12_3DSTATE_VS_VertexURBEntryReadOffset_bits 6 #define GFX11_3DSTATE_VS_VertexURBEntryReadOffset_bits 6 #define GFX9_3DSTATE_VS_VertexURBEntryReadOffset_bits 6 #define GFX8_3DSTATE_VS_VertexURBEntryReadOffset_bits 6 #define GFX75_3DSTATE_VS_VertexURBEntryReadOffset_bits 6 #define GFX7_3DSTATE_VS_VertexURBEntryReadOffset_bits 6 #define GFX6_3DSTATE_VS_VertexURBEntryReadOffset_bits 6 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VS_VertexURBEntryReadOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 6; case 60: return 6; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_VS_VertexURBEntryReadOffset_start 196 #define GFX12_3DSTATE_VS_VertexURBEntryReadOffset_start 196 #define GFX11_3DSTATE_VS_VertexURBEntryReadOffset_start 196 #define GFX9_3DSTATE_VS_VertexURBEntryReadOffset_start 196 #define GFX8_3DSTATE_VS_VertexURBEntryReadOffset_start 196 #define GFX75_3DSTATE_VS_VertexURBEntryReadOffset_start 132 #define GFX7_3DSTATE_VS_VertexURBEntryReadOffset_start 132 #define GFX6_3DSTATE_VS_VertexURBEntryReadOffset_start 132 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_VS_VertexURBEntryReadOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 196; case 120: return 196; case 110: return 196; case 90: return 196; case 80: return 196; case 75: return 132; case 70: return 132; case 60: return 132; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM */ #define GFX125_3DSTATE_WM_length 2 #define GFX12_3DSTATE_WM_length 2 #define GFX11_3DSTATE_WM_length 2 #define GFX9_3DSTATE_WM_length 2 #define GFX8_3DSTATE_WM_length 2 #define GFX75_3DSTATE_WM_length 3 #define GFX7_3DSTATE_WM_length 3 #define GFX6_3DSTATE_WM_length 9 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 3; case 70: return 3; case 60: return 9; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM::16 Pixel Dispatch Enable */ #define GFX6_3DSTATE_WM_16PixelDispatchEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_16PixelDispatchEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_WM_16PixelDispatchEnable_start 161 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_16PixelDispatchEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 161; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM::32 Pixel Dispatch Enable */ #define GFX6_3DSTATE_WM_32PixelDispatchEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_32PixelDispatchEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_WM_32PixelDispatchEnable_start 162 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_32PixelDispatchEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 162; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM::3D Command Opcode */ #define GFX125_3DSTATE_WM_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_WM_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_WM_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_WM_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_WM_3DCommandOpcode_bits 3 #define GFX75_3DSTATE_WM_3DCommandOpcode_bits 3 #define GFX7_3DSTATE_WM_3DCommandOpcode_bits 3 #define GFX6_3DSTATE_WM_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_3DCommandOpcode_start 24 #define GFX12_3DSTATE_WM_3DCommandOpcode_start 24 #define GFX11_3DSTATE_WM_3DCommandOpcode_start 24 #define GFX9_3DSTATE_WM_3DCommandOpcode_start 24 #define GFX8_3DSTATE_WM_3DCommandOpcode_start 24 #define GFX75_3DSTATE_WM_3DCommandOpcode_start 24 #define GFX7_3DSTATE_WM_3DCommandOpcode_start 24 #define GFX6_3DSTATE_WM_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 24; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM::3D Command Sub Opcode */ #define GFX125_3DSTATE_WM_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_WM_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_WM_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_WM_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_WM_3DCommandSubOpcode_bits 8 #define GFX75_3DSTATE_WM_3DCommandSubOpcode_bits 8 #define GFX7_3DSTATE_WM_3DCommandSubOpcode_bits 8 #define GFX6_3DSTATE_WM_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_WM_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_WM_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_WM_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_WM_3DCommandSubOpcode_start 16 #define GFX75_3DSTATE_WM_3DCommandSubOpcode_start 16 #define GFX7_3DSTATE_WM_3DCommandSubOpcode_start 16 #define GFX6_3DSTATE_WM_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 16; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM::8 Pixel Dispatch Enable */ #define GFX6_3DSTATE_WM_8PixelDispatchEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_8PixelDispatchEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_WM_8PixelDispatchEnable_start 160 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_8PixelDispatchEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 160; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM::Barycentric Interpolation Mode */ #define GFX125_3DSTATE_WM_BarycentricInterpolationMode_bits 6 #define GFX12_3DSTATE_WM_BarycentricInterpolationMode_bits 6 #define GFX11_3DSTATE_WM_BarycentricInterpolationMode_bits 6 #define GFX9_3DSTATE_WM_BarycentricInterpolationMode_bits 6 #define GFX8_3DSTATE_WM_BarycentricInterpolationMode_bits 6 #define GFX75_3DSTATE_WM_BarycentricInterpolationMode_bits 6 #define GFX7_3DSTATE_WM_BarycentricInterpolationMode_bits 6 #define GFX6_3DSTATE_WM_BarycentricInterpolationMode_bits 6 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_BarycentricInterpolationMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 6; case 60: return 6; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_BarycentricInterpolationMode_start 43 #define GFX12_3DSTATE_WM_BarycentricInterpolationMode_start 43 #define GFX11_3DSTATE_WM_BarycentricInterpolationMode_start 43 #define GFX9_3DSTATE_WM_BarycentricInterpolationMode_start 43 #define GFX8_3DSTATE_WM_BarycentricInterpolationMode_start 43 #define GFX75_3DSTATE_WM_BarycentricInterpolationMode_start 43 #define GFX7_3DSTATE_WM_BarycentricInterpolationMode_start 43 #define GFX6_3DSTATE_WM_BarycentricInterpolationMode_start 202 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_BarycentricInterpolationMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 43; case 120: return 43; case 110: return 43; case 90: return 43; case 80: return 43; case 75: return 43; case 70: return 43; case 60: return 202; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM::Binding Table Entry Count */ #define GFX6_3DSTATE_WM_BindingTableEntryCount_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_BindingTableEntryCount_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_WM_BindingTableEntryCount_start 82 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_BindingTableEntryCount_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 82; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM::Command SubType */ #define GFX125_3DSTATE_WM_CommandSubType_bits 2 #define GFX12_3DSTATE_WM_CommandSubType_bits 2 #define GFX11_3DSTATE_WM_CommandSubType_bits 2 #define GFX9_3DSTATE_WM_CommandSubType_bits 2 #define GFX8_3DSTATE_WM_CommandSubType_bits 2 #define GFX75_3DSTATE_WM_CommandSubType_bits 2 #define GFX7_3DSTATE_WM_CommandSubType_bits 2 #define GFX6_3DSTATE_WM_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_CommandSubType_start 27 #define GFX12_3DSTATE_WM_CommandSubType_start 27 #define GFX11_3DSTATE_WM_CommandSubType_start 27 #define GFX9_3DSTATE_WM_CommandSubType_start 27 #define GFX8_3DSTATE_WM_CommandSubType_start 27 #define GFX75_3DSTATE_WM_CommandSubType_start 27 #define GFX7_3DSTATE_WM_CommandSubType_start 27 #define GFX6_3DSTATE_WM_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 27; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM::Command Type */ #define GFX125_3DSTATE_WM_CommandType_bits 3 #define GFX12_3DSTATE_WM_CommandType_bits 3 #define GFX11_3DSTATE_WM_CommandType_bits 3 #define GFX9_3DSTATE_WM_CommandType_bits 3 #define GFX8_3DSTATE_WM_CommandType_bits 3 #define GFX75_3DSTATE_WM_CommandType_bits 3 #define GFX7_3DSTATE_WM_CommandType_bits 3 #define GFX6_3DSTATE_WM_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_CommandType_start 29 #define GFX12_3DSTATE_WM_CommandType_start 29 #define GFX11_3DSTATE_WM_CommandType_start 29 #define GFX9_3DSTATE_WM_CommandType_start 29 #define GFX8_3DSTATE_WM_CommandType_start 29 #define GFX75_3DSTATE_WM_CommandType_start 29 #define GFX7_3DSTATE_WM_CommandType_start 29 #define GFX6_3DSTATE_WM_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 29; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM::DWord Length */ #define GFX125_3DSTATE_WM_DWordLength_bits 8 #define GFX12_3DSTATE_WM_DWordLength_bits 8 #define GFX11_3DSTATE_WM_DWordLength_bits 8 #define GFX9_3DSTATE_WM_DWordLength_bits 8 #define GFX8_3DSTATE_WM_DWordLength_bits 8 #define GFX75_3DSTATE_WM_DWordLength_bits 8 #define GFX7_3DSTATE_WM_DWordLength_bits 8 #define GFX6_3DSTATE_WM_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_DWordLength_start 0 #define GFX12_3DSTATE_WM_DWordLength_start 0 #define GFX11_3DSTATE_WM_DWordLength_start 0 #define GFX9_3DSTATE_WM_DWordLength_start 0 #define GFX8_3DSTATE_WM_DWordLength_start 0 #define GFX75_3DSTATE_WM_DWordLength_start 0 #define GFX7_3DSTATE_WM_DWordLength_start 0 #define GFX6_3DSTATE_WM_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM::Depth Buffer Clear */ #define GFX75_3DSTATE_WM_DepthBufferClear_bits 1 #define GFX7_3DSTATE_WM_DepthBufferClear_bits 1 #define GFX6_3DSTATE_WM_DepthBufferClear_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_DepthBufferClear_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_WM_DepthBufferClear_start 62 #define GFX7_3DSTATE_WM_DepthBufferClear_start 62 #define GFX6_3DSTATE_WM_DepthBufferClear_start 158 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_DepthBufferClear_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 62; case 70: return 62; case 60: return 158; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM::Depth Buffer Resolve Enable */ #define GFX75_3DSTATE_WM_DepthBufferResolveEnable_bits 1 #define GFX7_3DSTATE_WM_DepthBufferResolveEnable_bits 1 #define GFX6_3DSTATE_WM_DepthBufferResolveEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_DepthBufferResolveEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_WM_DepthBufferResolveEnable_start 60 #define GFX7_3DSTATE_WM_DepthBufferResolveEnable_start 60 #define GFX6_3DSTATE_WM_DepthBufferResolveEnable_start 156 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_DepthBufferResolveEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 60; case 70: return 60; case 60: return 156; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM::Dispatch GRF Start Register For Constant/Setup Data 0 */ #define GFX6_3DSTATE_WM_DispatchGRFStartRegisterForConstantSetupData0_bits 7 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_DispatchGRFStartRegisterForConstantSetupData0_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 7; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_WM_DispatchGRFStartRegisterForConstantSetupData0_start 144 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_DispatchGRFStartRegisterForConstantSetupData0_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 144; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM::Dispatch GRF Start Register For Constant/Setup Data 1 */ #define GFX6_3DSTATE_WM_DispatchGRFStartRegisterForConstantSetupData1_bits 7 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_DispatchGRFStartRegisterForConstantSetupData1_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 7; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_WM_DispatchGRFStartRegisterForConstantSetupData1_start 136 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_DispatchGRFStartRegisterForConstantSetupData1_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 136; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM::Dispatch GRF Start Register For Constant/Setup Data 2 */ #define GFX6_3DSTATE_WM_DispatchGRFStartRegisterForConstantSetupData2_bits 7 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_DispatchGRFStartRegisterForConstantSetupData2_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 7; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_WM_DispatchGRFStartRegisterForConstantSetupData2_start 128 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_DispatchGRFStartRegisterForConstantSetupData2_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 128; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM::Dual Source Blend Enable */ #define GFX6_3DSTATE_WM_DualSourceBlendEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_DualSourceBlendEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_WM_DualSourceBlendEnable_start 167 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_DualSourceBlendEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 167; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM::Early Depth/Stencil Control */ #define GFX125_3DSTATE_WM_EarlyDepthStencilControl_bits 2 #define GFX12_3DSTATE_WM_EarlyDepthStencilControl_bits 2 #define GFX11_3DSTATE_WM_EarlyDepthStencilControl_bits 2 #define GFX9_3DSTATE_WM_EarlyDepthStencilControl_bits 2 #define GFX8_3DSTATE_WM_EarlyDepthStencilControl_bits 2 #define GFX75_3DSTATE_WM_EarlyDepthStencilControl_bits 2 #define GFX7_3DSTATE_WM_EarlyDepthStencilControl_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_EarlyDepthStencilControl_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_EarlyDepthStencilControl_start 53 #define GFX12_3DSTATE_WM_EarlyDepthStencilControl_start 53 #define GFX11_3DSTATE_WM_EarlyDepthStencilControl_start 53 #define GFX9_3DSTATE_WM_EarlyDepthStencilControl_start 53 #define GFX8_3DSTATE_WM_EarlyDepthStencilControl_start 53 #define GFX75_3DSTATE_WM_EarlyDepthStencilControl_start 53 #define GFX7_3DSTATE_WM_EarlyDepthStencilControl_start 53 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_EarlyDepthStencilControl_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 53; case 120: return 53; case 110: return 53; case 90: return 53; case 80: return 53; case 75: return 53; case 70: return 53; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM::Floating Point Mode */ #define GFX6_3DSTATE_WM_FloatingPointMode_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_FloatingPointMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_WM_FloatingPointMode_start 80 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_FloatingPointMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 80; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM::Force Kill Pixel Enable */ #define GFX125_3DSTATE_WM_ForceKillPixelEnable_bits 2 #define GFX12_3DSTATE_WM_ForceKillPixelEnable_bits 2 #define GFX11_3DSTATE_WM_ForceKillPixelEnable_bits 2 #define GFX9_3DSTATE_WM_ForceKillPixelEnable_bits 2 #define GFX8_3DSTATE_WM_ForceKillPixelEnable_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_ForceKillPixelEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_ForceKillPixelEnable_start 32 #define GFX12_3DSTATE_WM_ForceKillPixelEnable_start 32 #define GFX11_3DSTATE_WM_ForceKillPixelEnable_start 32 #define GFX9_3DSTATE_WM_ForceKillPixelEnable_start 32 #define GFX8_3DSTATE_WM_ForceKillPixelEnable_start 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_ForceKillPixelEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM::Force Thread Dispatch Enable */ #define GFX125_3DSTATE_WM_ForceThreadDispatchEnable_bits 2 #define GFX12_3DSTATE_WM_ForceThreadDispatchEnable_bits 2 #define GFX11_3DSTATE_WM_ForceThreadDispatchEnable_bits 2 #define GFX9_3DSTATE_WM_ForceThreadDispatchEnable_bits 2 #define GFX8_3DSTATE_WM_ForceThreadDispatchEnable_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_ForceThreadDispatchEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_ForceThreadDispatchEnable_start 51 #define GFX12_3DSTATE_WM_ForceThreadDispatchEnable_start 51 #define GFX11_3DSTATE_WM_ForceThreadDispatchEnable_start 51 #define GFX9_3DSTATE_WM_ForceThreadDispatchEnable_start 51 #define GFX8_3DSTATE_WM_ForceThreadDispatchEnable_start 51 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_ForceThreadDispatchEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 51; case 120: return 51; case 110: return 51; case 90: return 51; case 80: return 51; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM::Hierarchical Depth Buffer Resolve Enable */ #define GFX75_3DSTATE_WM_HierarchicalDepthBufferResolveEnable_bits 1 #define GFX7_3DSTATE_WM_HierarchicalDepthBufferResolveEnable_bits 1 #define GFX6_3DSTATE_WM_HierarchicalDepthBufferResolveEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_HierarchicalDepthBufferResolveEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_WM_HierarchicalDepthBufferResolveEnable_start 59 #define GFX7_3DSTATE_WM_HierarchicalDepthBufferResolveEnable_start 59 #define GFX6_3DSTATE_WM_HierarchicalDepthBufferResolveEnable_start 155 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_HierarchicalDepthBufferResolveEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 59; case 70: return 59; case 60: return 155; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM::Illegal Opcode Exception Enable */ #define GFX6_3DSTATE_WM_IllegalOpcodeExceptionEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_IllegalOpcodeExceptionEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_WM_IllegalOpcodeExceptionEnable_start 77 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_IllegalOpcodeExceptionEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 77; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM::Kernel Start Pointer 0 */ #define GFX6_3DSTATE_WM_KernelStartPointer0_bits 26 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_KernelStartPointer0_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 26; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_WM_KernelStartPointer0_start 38 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_KernelStartPointer0_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 38; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM::Kernel Start Pointer 1 */ #define GFX6_3DSTATE_WM_KernelStartPointer1_bits 26 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_KernelStartPointer1_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 26; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_WM_KernelStartPointer1_start 230 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_KernelStartPointer1_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 230; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM::Kernel Start Pointer 2 */ #define GFX6_3DSTATE_WM_KernelStartPointer2_bits 26 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_KernelStartPointer2_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 26; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_WM_KernelStartPointer2_start 262 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_KernelStartPointer2_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 262; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM::Legacy Depth Buffer Clear Enable */ #define GFX125_3DSTATE_WM_LegacyDepthBufferClearEnable_bits 1 #define GFX12_3DSTATE_WM_LegacyDepthBufferClearEnable_bits 1 #define GFX11_3DSTATE_WM_LegacyDepthBufferClearEnable_bits 1 #define GFX9_3DSTATE_WM_LegacyDepthBufferClearEnable_bits 1 #define GFX8_3DSTATE_WM_LegacyDepthBufferClearEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_LegacyDepthBufferClearEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_LegacyDepthBufferClearEnable_start 62 #define GFX12_3DSTATE_WM_LegacyDepthBufferClearEnable_start 62 #define GFX11_3DSTATE_WM_LegacyDepthBufferClearEnable_start 62 #define GFX9_3DSTATE_WM_LegacyDepthBufferClearEnable_start 62 #define GFX8_3DSTATE_WM_LegacyDepthBufferClearEnable_start 62 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_LegacyDepthBufferClearEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 62; case 120: return 62; case 110: return 62; case 90: return 62; case 80: return 62; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM::Legacy Depth Buffer Resolve Enable */ #define GFX125_3DSTATE_WM_LegacyDepthBufferResolveEnable_bits 1 #define GFX12_3DSTATE_WM_LegacyDepthBufferResolveEnable_bits 1 #define GFX11_3DSTATE_WM_LegacyDepthBufferResolveEnable_bits 1 #define GFX9_3DSTATE_WM_LegacyDepthBufferResolveEnable_bits 1 #define GFX8_3DSTATE_WM_LegacyDepthBufferResolveEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_LegacyDepthBufferResolveEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_LegacyDepthBufferResolveEnable_start 60 #define GFX12_3DSTATE_WM_LegacyDepthBufferResolveEnable_start 60 #define GFX11_3DSTATE_WM_LegacyDepthBufferResolveEnable_start 60 #define GFX9_3DSTATE_WM_LegacyDepthBufferResolveEnable_start 60 #define GFX8_3DSTATE_WM_LegacyDepthBufferResolveEnable_start 60 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_LegacyDepthBufferResolveEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 60; case 120: return 60; case 110: return 60; case 90: return 60; case 80: return 60; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM::Legacy Diamond Line Rasterization */ #define GFX125_3DSTATE_WM_LegacyDiamondLineRasterization_bits 1 #define GFX12_3DSTATE_WM_LegacyDiamondLineRasterization_bits 1 #define GFX11_3DSTATE_WM_LegacyDiamondLineRasterization_bits 1 #define GFX9_3DSTATE_WM_LegacyDiamondLineRasterization_bits 1 #define GFX8_3DSTATE_WM_LegacyDiamondLineRasterization_bits 1 #define GFX75_3DSTATE_WM_LegacyDiamondLineRasterization_bits 1 #define GFX7_3DSTATE_WM_LegacyDiamondLineRasterization_bits 1 #define GFX6_3DSTATE_WM_LegacyDiamondLineRasterization_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_LegacyDiamondLineRasterization_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_LegacyDiamondLineRasterization_start 58 #define GFX12_3DSTATE_WM_LegacyDiamondLineRasterization_start 58 #define GFX11_3DSTATE_WM_LegacyDiamondLineRasterization_start 58 #define GFX9_3DSTATE_WM_LegacyDiamondLineRasterization_start 58 #define GFX8_3DSTATE_WM_LegacyDiamondLineRasterization_start 58 #define GFX75_3DSTATE_WM_LegacyDiamondLineRasterization_start 58 #define GFX7_3DSTATE_WM_LegacyDiamondLineRasterization_start 58 #define GFX6_3DSTATE_WM_LegacyDiamondLineRasterization_start 183 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_LegacyDiamondLineRasterization_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 58; case 120: return 58; case 110: return 58; case 90: return 58; case 80: return 58; case 75: return 58; case 70: return 58; case 60: return 183; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM::Legacy Hierarchical Depth Buffer Resolve Enable */ #define GFX125_3DSTATE_WM_LegacyHierarchicalDepthBufferResolveEnable_bits 1 #define GFX12_3DSTATE_WM_LegacyHierarchicalDepthBufferResolveEnable_bits 1 #define GFX11_3DSTATE_WM_LegacyHierarchicalDepthBufferResolveEnable_bits 1 #define GFX9_3DSTATE_WM_LegacyHierarchicalDepthBufferResolveEnable_bits 1 #define GFX8_3DSTATE_WM_LegacyHierarchicalDepthBufferResolveEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_LegacyHierarchicalDepthBufferResolveEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_LegacyHierarchicalDepthBufferResolveEnable_start 59 #define GFX12_3DSTATE_WM_LegacyHierarchicalDepthBufferResolveEnable_start 59 #define GFX11_3DSTATE_WM_LegacyHierarchicalDepthBufferResolveEnable_start 59 #define GFX9_3DSTATE_WM_LegacyHierarchicalDepthBufferResolveEnable_start 59 #define GFX8_3DSTATE_WM_LegacyHierarchicalDepthBufferResolveEnable_start 59 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_LegacyHierarchicalDepthBufferResolveEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 59; case 120: return 59; case 110: return 59; case 90: return 59; case 80: return 59; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM::Line Antialiasing Region Width */ #define GFX125_3DSTATE_WM_LineAntialiasingRegionWidth_bits 2 #define GFX12_3DSTATE_WM_LineAntialiasingRegionWidth_bits 2 #define GFX11_3DSTATE_WM_LineAntialiasingRegionWidth_bits 2 #define GFX9_3DSTATE_WM_LineAntialiasingRegionWidth_bits 2 #define GFX8_3DSTATE_WM_LineAntialiasingRegionWidth_bits 2 #define GFX75_3DSTATE_WM_LineAntialiasingRegionWidth_bits 2 #define GFX7_3DSTATE_WM_LineAntialiasingRegionWidth_bits 2 #define GFX6_3DSTATE_WM_LineAntialiasingRegionWidth_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_LineAntialiasingRegionWidth_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_LineAntialiasingRegionWidth_start 38 #define GFX12_3DSTATE_WM_LineAntialiasingRegionWidth_start 38 #define GFX11_3DSTATE_WM_LineAntialiasingRegionWidth_start 38 #define GFX9_3DSTATE_WM_LineAntialiasingRegionWidth_start 38 #define GFX8_3DSTATE_WM_LineAntialiasingRegionWidth_start 38 #define GFX75_3DSTATE_WM_LineAntialiasingRegionWidth_start 38 #define GFX7_3DSTATE_WM_LineAntialiasingRegionWidth_start 38 #define GFX6_3DSTATE_WM_LineAntialiasingRegionWidth_start 174 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_LineAntialiasingRegionWidth_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 38; case 120: return 38; case 110: return 38; case 90: return 38; case 80: return 38; case 75: return 38; case 70: return 38; case 60: return 174; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM::Line End Cap Antialiasing Region Width */ #define GFX125_3DSTATE_WM_LineEndCapAntialiasingRegionWidth_bits 2 #define GFX12_3DSTATE_WM_LineEndCapAntialiasingRegionWidth_bits 2 #define GFX11_3DSTATE_WM_LineEndCapAntialiasingRegionWidth_bits 2 #define GFX9_3DSTATE_WM_LineEndCapAntialiasingRegionWidth_bits 2 #define GFX8_3DSTATE_WM_LineEndCapAntialiasingRegionWidth_bits 2 #define GFX75_3DSTATE_WM_LineEndCapAntialiasingRegionWidth_bits 2 #define GFX7_3DSTATE_WM_LineEndCapAntialiasingRegionWidth_bits 2 #define GFX6_3DSTATE_WM_LineEndCapAntialiasingRegionWidth_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_LineEndCapAntialiasingRegionWidth_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_LineEndCapAntialiasingRegionWidth_start 40 #define GFX12_3DSTATE_WM_LineEndCapAntialiasingRegionWidth_start 40 #define GFX11_3DSTATE_WM_LineEndCapAntialiasingRegionWidth_start 40 #define GFX9_3DSTATE_WM_LineEndCapAntialiasingRegionWidth_start 40 #define GFX8_3DSTATE_WM_LineEndCapAntialiasingRegionWidth_start 40 #define GFX75_3DSTATE_WM_LineEndCapAntialiasingRegionWidth_start 40 #define GFX7_3DSTATE_WM_LineEndCapAntialiasingRegionWidth_start 40 #define GFX6_3DSTATE_WM_LineEndCapAntialiasingRegionWidth_start 176 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_LineEndCapAntialiasingRegionWidth_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 40; case 120: return 40; case 110: return 40; case 90: return 40; case 80: return 40; case 75: return 40; case 70: return 40; case 60: return 176; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM::Line Stipple Enable */ #define GFX125_3DSTATE_WM_LineStippleEnable_bits 1 #define GFX12_3DSTATE_WM_LineStippleEnable_bits 1 #define GFX11_3DSTATE_WM_LineStippleEnable_bits 1 #define GFX9_3DSTATE_WM_LineStippleEnable_bits 1 #define GFX8_3DSTATE_WM_LineStippleEnable_bits 1 #define GFX75_3DSTATE_WM_LineStippleEnable_bits 1 #define GFX7_3DSTATE_WM_LineStippleEnable_bits 1 #define GFX6_3DSTATE_WM_LineStippleEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_LineStippleEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_LineStippleEnable_start 35 #define GFX12_3DSTATE_WM_LineStippleEnable_start 35 #define GFX11_3DSTATE_WM_LineStippleEnable_start 35 #define GFX9_3DSTATE_WM_LineStippleEnable_start 35 #define GFX8_3DSTATE_WM_LineStippleEnable_start 35 #define GFX75_3DSTATE_WM_LineStippleEnable_start 35 #define GFX7_3DSTATE_WM_LineStippleEnable_start 35 #define GFX6_3DSTATE_WM_LineStippleEnable_start 171 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_LineStippleEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 35; case 120: return 35; case 110: return 35; case 90: return 35; case 80: return 35; case 75: return 35; case 70: return 35; case 60: return 171; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM::MaskStack Exception Enable */ #define GFX6_3DSTATE_WM_MaskStackExceptionEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_MaskStackExceptionEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_WM_MaskStackExceptionEnable_start 75 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_MaskStackExceptionEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 75; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM::Maximum Number of Threads */ #define GFX6_3DSTATE_WM_MaximumNumberofThreads_bits 7 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_MaximumNumberofThreads_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 7; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_WM_MaximumNumberofThreads_start 185 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_MaximumNumberofThreads_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 185; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM::Multisample Dispatch Mode */ #define GFX75_3DSTATE_WM_MultisampleDispatchMode_bits 1 #define GFX7_3DSTATE_WM_MultisampleDispatchMode_bits 1 #define GFX6_3DSTATE_WM_MultisampleDispatchMode_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_MultisampleDispatchMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_WM_MultisampleDispatchMode_start 95 #define GFX7_3DSTATE_WM_MultisampleDispatchMode_start 95 #define GFX6_3DSTATE_WM_MultisampleDispatchMode_start 192 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_MultisampleDispatchMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 95; case 70: return 95; case 60: return 192; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM::Multisample Rasterization Mode */ #define GFX75_3DSTATE_WM_MultisampleRasterizationMode_bits 2 #define GFX7_3DSTATE_WM_MultisampleRasterizationMode_bits 2 #define GFX6_3DSTATE_WM_MultisampleRasterizationMode_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_MultisampleRasterizationMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_WM_MultisampleRasterizationMode_start 32 #define GFX7_3DSTATE_WM_MultisampleRasterizationMode_start 32 #define GFX6_3DSTATE_WM_MultisampleRasterizationMode_start 193 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_MultisampleRasterizationMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 32; case 70: return 32; case 60: return 193; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM::Number of SF Output Attributes */ #define GFX6_3DSTATE_WM_NumberofSFOutputAttributes_bits 6 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_NumberofSFOutputAttributes_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 6; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_WM_NumberofSFOutputAttributes_start 212 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_NumberofSFOutputAttributes_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 212; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM::PS UAV-only */ #define GFX75_3DSTATE_WM_PSUAVonly_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_PSUAVonly_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_WM_PSUAVonly_start 94 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_PSUAVonly_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 94; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM::Per Thread Scratch Space */ #define GFX6_3DSTATE_WM_PerThreadScratchSpace_bits 4 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_PerThreadScratchSpace_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_WM_PerThreadScratchSpace_start 96 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_PerThreadScratchSpace_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 96; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM::Pixel Shader Computed Depth */ #define GFX6_3DSTATE_WM_PixelShaderComputedDepth_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_PixelShaderComputedDepth_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_WM_PixelShaderComputedDepth_start 181 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_PixelShaderComputedDepth_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 181; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM::Pixel Shader Computed Depth Mode */ #define GFX75_3DSTATE_WM_PixelShaderComputedDepthMode_bits 2 #define GFX7_3DSTATE_WM_PixelShaderComputedDepthMode_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_PixelShaderComputedDepthMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_WM_PixelShaderComputedDepthMode_start 55 #define GFX7_3DSTATE_WM_PixelShaderComputedDepthMode_start 55 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_PixelShaderComputedDepthMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 55; case 70: return 55; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM::Pixel Shader Kills Pixel */ #define GFX75_3DSTATE_WM_PixelShaderKillsPixel_bits 1 #define GFX7_3DSTATE_WM_PixelShaderKillsPixel_bits 1 #define GFX6_3DSTATE_WM_PixelShaderKillsPixel_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_PixelShaderKillsPixel_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_WM_PixelShaderKillsPixel_start 57 #define GFX7_3DSTATE_WM_PixelShaderKillsPixel_start 57 #define GFX6_3DSTATE_WM_PixelShaderKillsPixel_start 182 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_PixelShaderKillsPixel_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 57; case 70: return 57; case 60: return 182; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM::Pixel Shader Uses Input Coverage Mask */ #define GFX75_3DSTATE_WM_PixelShaderUsesInputCoverageMask_bits 1 #define GFX7_3DSTATE_WM_PixelShaderUsesInputCoverageMask_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_PixelShaderUsesInputCoverageMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_WM_PixelShaderUsesInputCoverageMask_start 42 #define GFX7_3DSTATE_WM_PixelShaderUsesInputCoverageMask_start 42 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_PixelShaderUsesInputCoverageMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 42; case 70: return 42; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM::Pixel Shader Uses Source Depth */ #define GFX75_3DSTATE_WM_PixelShaderUsesSourceDepth_bits 1 #define GFX7_3DSTATE_WM_PixelShaderUsesSourceDepth_bits 1 #define GFX6_3DSTATE_WM_PixelShaderUsesSourceDepth_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_PixelShaderUsesSourceDepth_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_WM_PixelShaderUsesSourceDepth_start 52 #define GFX7_3DSTATE_WM_PixelShaderUsesSourceDepth_start 52 #define GFX6_3DSTATE_WM_PixelShaderUsesSourceDepth_start 180 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_PixelShaderUsesSourceDepth_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 52; case 70: return 52; case 60: return 180; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM::Pixel Shader Uses Source W */ #define GFX75_3DSTATE_WM_PixelShaderUsesSourceW_bits 1 #define GFX7_3DSTATE_WM_PixelShaderUsesSourceW_bits 1 #define GFX6_3DSTATE_WM_PixelShaderUsesSourceW_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_PixelShaderUsesSourceW_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_WM_PixelShaderUsesSourceW_start 51 #define GFX7_3DSTATE_WM_PixelShaderUsesSourceW_start 51 #define GFX6_3DSTATE_WM_PixelShaderUsesSourceW_start 168 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_PixelShaderUsesSourceW_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 51; case 70: return 51; case 60: return 168; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM::Point Rasterization Rule */ #define GFX125_3DSTATE_WM_PointRasterizationRule_bits 1 #define GFX12_3DSTATE_WM_PointRasterizationRule_bits 1 #define GFX11_3DSTATE_WM_PointRasterizationRule_bits 1 #define GFX9_3DSTATE_WM_PointRasterizationRule_bits 1 #define GFX8_3DSTATE_WM_PointRasterizationRule_bits 1 #define GFX75_3DSTATE_WM_PointRasterizationRule_bits 1 #define GFX7_3DSTATE_WM_PointRasterizationRule_bits 1 #define GFX6_3DSTATE_WM_PointRasterizationRule_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_PointRasterizationRule_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_PointRasterizationRule_start 34 #define GFX12_3DSTATE_WM_PointRasterizationRule_start 34 #define GFX11_3DSTATE_WM_PointRasterizationRule_start 34 #define GFX9_3DSTATE_WM_PointRasterizationRule_start 34 #define GFX8_3DSTATE_WM_PointRasterizationRule_start 34 #define GFX75_3DSTATE_WM_PointRasterizationRule_start 34 #define GFX7_3DSTATE_WM_PointRasterizationRule_start 34 #define GFX6_3DSTATE_WM_PointRasterizationRule_start 201 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_PointRasterizationRule_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 34; case 120: return 34; case 110: return 34; case 90: return 34; case 80: return 34; case 75: return 34; case 70: return 34; case 60: return 201; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM::Polygon Stipple Enable */ #define GFX125_3DSTATE_WM_PolygonStippleEnable_bits 1 #define GFX12_3DSTATE_WM_PolygonStippleEnable_bits 1 #define GFX11_3DSTATE_WM_PolygonStippleEnable_bits 1 #define GFX9_3DSTATE_WM_PolygonStippleEnable_bits 1 #define GFX8_3DSTATE_WM_PolygonStippleEnable_bits 1 #define GFX75_3DSTATE_WM_PolygonStippleEnable_bits 1 #define GFX7_3DSTATE_WM_PolygonStippleEnable_bits 1 #define GFX6_3DSTATE_WM_PolygonStippleEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_PolygonStippleEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_PolygonStippleEnable_start 36 #define GFX12_3DSTATE_WM_PolygonStippleEnable_start 36 #define GFX11_3DSTATE_WM_PolygonStippleEnable_start 36 #define GFX9_3DSTATE_WM_PolygonStippleEnable_start 36 #define GFX8_3DSTATE_WM_PolygonStippleEnable_start 36 #define GFX75_3DSTATE_WM_PolygonStippleEnable_start 36 #define GFX7_3DSTATE_WM_PolygonStippleEnable_start 36 #define GFX6_3DSTATE_WM_PolygonStippleEnable_start 173 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_PolygonStippleEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 36; case 120: return 36; case 110: return 36; case 90: return 36; case 80: return 36; case 75: return 36; case 70: return 36; case 60: return 173; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM::Position XY Offset Select */ #define GFX6_3DSTATE_WM_PositionXYOffsetSelect_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_PositionXYOffsetSelect_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_WM_PositionXYOffsetSelect_start 210 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_PositionXYOffsetSelect_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 210; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM::Position ZW Interpolation Mode */ #define GFX125_3DSTATE_WM_PositionZWInterpolationMode_bits 2 #define GFX12_3DSTATE_WM_PositionZWInterpolationMode_bits 2 #define GFX11_3DSTATE_WM_PositionZWInterpolationMode_bits 2 #define GFX9_3DSTATE_WM_PositionZWInterpolationMode_bits 2 #define GFX8_3DSTATE_WM_PositionZWInterpolationMode_bits 2 #define GFX75_3DSTATE_WM_PositionZWInterpolationMode_bits 2 #define GFX7_3DSTATE_WM_PositionZWInterpolationMode_bits 2 #define GFX6_3DSTATE_WM_PositionZWInterpolationMode_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_PositionZWInterpolationMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_PositionZWInterpolationMode_start 49 #define GFX12_3DSTATE_WM_PositionZWInterpolationMode_start 49 #define GFX11_3DSTATE_WM_PositionZWInterpolationMode_start 49 #define GFX9_3DSTATE_WM_PositionZWInterpolationMode_start 49 #define GFX8_3DSTATE_WM_PositionZWInterpolationMode_start 49 #define GFX75_3DSTATE_WM_PositionZWInterpolationMode_start 49 #define GFX7_3DSTATE_WM_PositionZWInterpolationMode_start 49 #define GFX6_3DSTATE_WM_PositionZWInterpolationMode_start 208 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_PositionZWInterpolationMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 49; case 120: return 49; case 110: return 49; case 90: return 49; case 80: return 49; case 75: return 49; case 70: return 49; case 60: return 208; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM::RT Independent Rasterization Enable */ #define GFX75_3DSTATE_WM_RTIndependentRasterizationEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_RTIndependentRasterizationEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_WM_RTIndependentRasterizationEnable_start 37 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_RTIndependentRasterizationEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 37; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM::Sampler Count */ #define GFX6_3DSTATE_WM_SamplerCount_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_SamplerCount_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_WM_SamplerCount_start 91 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_SamplerCount_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 91; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM::Scratch Space Base Pointer */ #define GFX6_3DSTATE_WM_ScratchSpaceBasePointer_bits 22 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_ScratchSpaceBasePointer_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 22; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_WM_ScratchSpaceBasePointer_start 106 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_ScratchSpaceBasePointer_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 106; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM::Single Program Flow */ #define GFX6_3DSTATE_WM_SingleProgramFlow_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_SingleProgramFlow_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_WM_SingleProgramFlow_start 95 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_SingleProgramFlow_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 95; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM::Software Exception Enable */ #define GFX6_3DSTATE_WM_SoftwareExceptionEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_SoftwareExceptionEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_WM_SoftwareExceptionEnable_start 71 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_SoftwareExceptionEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 71; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM::Statistics Enable */ #define GFX125_3DSTATE_WM_StatisticsEnable_bits 1 #define GFX12_3DSTATE_WM_StatisticsEnable_bits 1 #define GFX11_3DSTATE_WM_StatisticsEnable_bits 1 #define GFX9_3DSTATE_WM_StatisticsEnable_bits 1 #define GFX8_3DSTATE_WM_StatisticsEnable_bits 1 #define GFX75_3DSTATE_WM_StatisticsEnable_bits 1 #define GFX7_3DSTATE_WM_StatisticsEnable_bits 1 #define GFX6_3DSTATE_WM_StatisticsEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_StatisticsEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_StatisticsEnable_start 63 #define GFX12_3DSTATE_WM_StatisticsEnable_start 63 #define GFX11_3DSTATE_WM_StatisticsEnable_start 63 #define GFX9_3DSTATE_WM_StatisticsEnable_start 63 #define GFX8_3DSTATE_WM_StatisticsEnable_start 63 #define GFX75_3DSTATE_WM_StatisticsEnable_start 63 #define GFX7_3DSTATE_WM_StatisticsEnable_start 63 #define GFX6_3DSTATE_WM_StatisticsEnable_start 159 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_StatisticsEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 63; case 120: return 63; case 110: return 63; case 90: return 63; case 80: return 63; case 75: return 63; case 70: return 63; case 60: return 159; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM::Thread Dispatch Enable */ #define GFX75_3DSTATE_WM_ThreadDispatchEnable_bits 1 #define GFX7_3DSTATE_WM_ThreadDispatchEnable_bits 1 #define GFX6_3DSTATE_WM_ThreadDispatchEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_ThreadDispatchEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_3DSTATE_WM_ThreadDispatchEnable_start 61 #define GFX7_3DSTATE_WM_ThreadDispatchEnable_start 61 #define GFX6_3DSTATE_WM_ThreadDispatchEnable_start 179 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_ThreadDispatchEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 61; case 70: return 61; case 60: return 179; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM::Thread Priority */ #define GFX6_3DSTATE_WM_ThreadPriority_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_ThreadPriority_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_WM_ThreadPriority_start 81 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_ThreadPriority_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 81; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM::Vector Mask Enable */ #define GFX6_3DSTATE_WM_VectorMaskEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_VectorMaskEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_WM_VectorMaskEnable_start 94 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_VectorMaskEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 94; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM::oMask Present to RenderTarget */ #define GFX6_3DSTATE_WM_oMaskPresenttoRenderTarget_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_oMaskPresenttoRenderTarget_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_3DSTATE_WM_oMaskPresenttoRenderTarget_start 169 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_oMaskPresenttoRenderTarget_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 169; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM_CHROMAKEY */ #define GFX125_3DSTATE_WM_CHROMAKEY_length 2 #define GFX12_3DSTATE_WM_CHROMAKEY_length 2 #define GFX11_3DSTATE_WM_CHROMAKEY_length 2 #define GFX9_3DSTATE_WM_CHROMAKEY_length 2 #define GFX8_3DSTATE_WM_CHROMAKEY_length 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_CHROMAKEY_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM_CHROMAKEY::3D Command Opcode */ #define GFX125_3DSTATE_WM_CHROMAKEY_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_WM_CHROMAKEY_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_WM_CHROMAKEY_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_WM_CHROMAKEY_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_WM_CHROMAKEY_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_CHROMAKEY_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_CHROMAKEY_3DCommandOpcode_start 24 #define GFX12_3DSTATE_WM_CHROMAKEY_3DCommandOpcode_start 24 #define GFX11_3DSTATE_WM_CHROMAKEY_3DCommandOpcode_start 24 #define GFX9_3DSTATE_WM_CHROMAKEY_3DCommandOpcode_start 24 #define GFX8_3DSTATE_WM_CHROMAKEY_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_CHROMAKEY_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM_CHROMAKEY::3D Command Sub Opcode */ #define GFX125_3DSTATE_WM_CHROMAKEY_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_WM_CHROMAKEY_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_WM_CHROMAKEY_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_WM_CHROMAKEY_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_WM_CHROMAKEY_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_CHROMAKEY_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_CHROMAKEY_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_WM_CHROMAKEY_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_WM_CHROMAKEY_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_WM_CHROMAKEY_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_WM_CHROMAKEY_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_CHROMAKEY_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM_CHROMAKEY::ChromaKey Kill Enable */ #define GFX125_3DSTATE_WM_CHROMAKEY_ChromaKeyKillEnable_bits 1 #define GFX12_3DSTATE_WM_CHROMAKEY_ChromaKeyKillEnable_bits 1 #define GFX11_3DSTATE_WM_CHROMAKEY_ChromaKeyKillEnable_bits 1 #define GFX9_3DSTATE_WM_CHROMAKEY_ChromaKeyKillEnable_bits 1 #define GFX8_3DSTATE_WM_CHROMAKEY_ChromaKeyKillEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_CHROMAKEY_ChromaKeyKillEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_CHROMAKEY_ChromaKeyKillEnable_start 63 #define GFX12_3DSTATE_WM_CHROMAKEY_ChromaKeyKillEnable_start 63 #define GFX11_3DSTATE_WM_CHROMAKEY_ChromaKeyKillEnable_start 63 #define GFX9_3DSTATE_WM_CHROMAKEY_ChromaKeyKillEnable_start 63 #define GFX8_3DSTATE_WM_CHROMAKEY_ChromaKeyKillEnable_start 63 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_CHROMAKEY_ChromaKeyKillEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 63; case 120: return 63; case 110: return 63; case 90: return 63; case 80: return 63; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM_CHROMAKEY::Command SubType */ #define GFX125_3DSTATE_WM_CHROMAKEY_CommandSubType_bits 2 #define GFX12_3DSTATE_WM_CHROMAKEY_CommandSubType_bits 2 #define GFX11_3DSTATE_WM_CHROMAKEY_CommandSubType_bits 2 #define GFX9_3DSTATE_WM_CHROMAKEY_CommandSubType_bits 2 #define GFX8_3DSTATE_WM_CHROMAKEY_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_CHROMAKEY_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_CHROMAKEY_CommandSubType_start 27 #define GFX12_3DSTATE_WM_CHROMAKEY_CommandSubType_start 27 #define GFX11_3DSTATE_WM_CHROMAKEY_CommandSubType_start 27 #define GFX9_3DSTATE_WM_CHROMAKEY_CommandSubType_start 27 #define GFX8_3DSTATE_WM_CHROMAKEY_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_CHROMAKEY_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM_CHROMAKEY::Command Type */ #define GFX125_3DSTATE_WM_CHROMAKEY_CommandType_bits 3 #define GFX12_3DSTATE_WM_CHROMAKEY_CommandType_bits 3 #define GFX11_3DSTATE_WM_CHROMAKEY_CommandType_bits 3 #define GFX9_3DSTATE_WM_CHROMAKEY_CommandType_bits 3 #define GFX8_3DSTATE_WM_CHROMAKEY_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_CHROMAKEY_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_CHROMAKEY_CommandType_start 29 #define GFX12_3DSTATE_WM_CHROMAKEY_CommandType_start 29 #define GFX11_3DSTATE_WM_CHROMAKEY_CommandType_start 29 #define GFX9_3DSTATE_WM_CHROMAKEY_CommandType_start 29 #define GFX8_3DSTATE_WM_CHROMAKEY_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_CHROMAKEY_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM_CHROMAKEY::DWord Length */ #define GFX125_3DSTATE_WM_CHROMAKEY_DWordLength_bits 8 #define GFX12_3DSTATE_WM_CHROMAKEY_DWordLength_bits 8 #define GFX11_3DSTATE_WM_CHROMAKEY_DWordLength_bits 8 #define GFX9_3DSTATE_WM_CHROMAKEY_DWordLength_bits 8 #define GFX8_3DSTATE_WM_CHROMAKEY_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_CHROMAKEY_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_CHROMAKEY_DWordLength_start 0 #define GFX12_3DSTATE_WM_CHROMAKEY_DWordLength_start 0 #define GFX11_3DSTATE_WM_CHROMAKEY_DWordLength_start 0 #define GFX9_3DSTATE_WM_CHROMAKEY_DWordLength_start 0 #define GFX8_3DSTATE_WM_CHROMAKEY_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_CHROMAKEY_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM_DEPTH_STENCIL */ #define GFX125_3DSTATE_WM_DEPTH_STENCIL_length 4 #define GFX12_3DSTATE_WM_DEPTH_STENCIL_length 4 #define GFX11_3DSTATE_WM_DEPTH_STENCIL_length 4 #define GFX9_3DSTATE_WM_DEPTH_STENCIL_length 4 #define GFX8_3DSTATE_WM_DEPTH_STENCIL_length 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_DEPTH_STENCIL_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 3; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM_DEPTH_STENCIL::3D Command Opcode */ #define GFX125_3DSTATE_WM_DEPTH_STENCIL_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_WM_DEPTH_STENCIL_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_WM_DEPTH_STENCIL_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_WM_DEPTH_STENCIL_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_WM_DEPTH_STENCIL_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_DEPTH_STENCIL_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_DEPTH_STENCIL_3DCommandOpcode_start 24 #define GFX12_3DSTATE_WM_DEPTH_STENCIL_3DCommandOpcode_start 24 #define GFX11_3DSTATE_WM_DEPTH_STENCIL_3DCommandOpcode_start 24 #define GFX9_3DSTATE_WM_DEPTH_STENCIL_3DCommandOpcode_start 24 #define GFX8_3DSTATE_WM_DEPTH_STENCIL_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_DEPTH_STENCIL_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM_DEPTH_STENCIL::3D Command Sub Opcode */ #define GFX125_3DSTATE_WM_DEPTH_STENCIL_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_WM_DEPTH_STENCIL_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_WM_DEPTH_STENCIL_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_WM_DEPTH_STENCIL_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_WM_DEPTH_STENCIL_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_DEPTH_STENCIL_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_DEPTH_STENCIL_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_WM_DEPTH_STENCIL_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_WM_DEPTH_STENCIL_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_WM_DEPTH_STENCIL_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_WM_DEPTH_STENCIL_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_DEPTH_STENCIL_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM_DEPTH_STENCIL::Backface Stencil Fail Op */ #define GFX125_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilFailOp_bits 3 #define GFX12_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilFailOp_bits 3 #define GFX11_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilFailOp_bits 3 #define GFX9_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilFailOp_bits 3 #define GFX8_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilFailOp_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilFailOp_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilFailOp_start 49 #define GFX12_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilFailOp_start 49 #define GFX11_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilFailOp_start 49 #define GFX9_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilFailOp_start 49 #define GFX8_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilFailOp_start 49 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilFailOp_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 49; case 120: return 49; case 110: return 49; case 90: return 49; case 80: return 49; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM_DEPTH_STENCIL::Backface Stencil Pass Depth Fail Op */ #define GFX125_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilPassDepthFailOp_bits 3 #define GFX12_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilPassDepthFailOp_bits 3 #define GFX11_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilPassDepthFailOp_bits 3 #define GFX9_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilPassDepthFailOp_bits 3 #define GFX8_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilPassDepthFailOp_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilPassDepthFailOp_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilPassDepthFailOp_start 46 #define GFX12_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilPassDepthFailOp_start 46 #define GFX11_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilPassDepthFailOp_start 46 #define GFX9_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilPassDepthFailOp_start 46 #define GFX8_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilPassDepthFailOp_start 46 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilPassDepthFailOp_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 46; case 120: return 46; case 110: return 46; case 90: return 46; case 80: return 46; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM_DEPTH_STENCIL::Backface Stencil Pass Depth Pass Op */ #define GFX125_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilPassDepthPassOp_bits 3 #define GFX12_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilPassDepthPassOp_bits 3 #define GFX11_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilPassDepthPassOp_bits 3 #define GFX9_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilPassDepthPassOp_bits 3 #define GFX8_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilPassDepthPassOp_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilPassDepthPassOp_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilPassDepthPassOp_start 43 #define GFX12_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilPassDepthPassOp_start 43 #define GFX11_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilPassDepthPassOp_start 43 #define GFX9_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilPassDepthPassOp_start 43 #define GFX8_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilPassDepthPassOp_start 43 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilPassDepthPassOp_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 43; case 120: return 43; case 110: return 43; case 90: return 43; case 80: return 43; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM_DEPTH_STENCIL::Backface Stencil Reference Value */ #define GFX125_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilReferenceValue_bits 8 #define GFX12_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilReferenceValue_bits 8 #define GFX11_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilReferenceValue_bits 8 #define GFX9_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilReferenceValue_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilReferenceValue_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilReferenceValue_start 96 #define GFX12_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilReferenceValue_start 96 #define GFX11_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilReferenceValue_start 96 #define GFX9_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilReferenceValue_start 96 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilReferenceValue_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 96; case 120: return 96; case 110: return 96; case 90: return 96; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM_DEPTH_STENCIL::Backface Stencil Test Function */ #define GFX125_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilTestFunction_bits 3 #define GFX12_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilTestFunction_bits 3 #define GFX11_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilTestFunction_bits 3 #define GFX9_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilTestFunction_bits 3 #define GFX8_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilTestFunction_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilTestFunction_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilTestFunction_start 52 #define GFX12_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilTestFunction_start 52 #define GFX11_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilTestFunction_start 52 #define GFX9_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilTestFunction_start 52 #define GFX8_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilTestFunction_start 52 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilTestFunction_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 52; case 120: return 52; case 110: return 52; case 90: return 52; case 80: return 52; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM_DEPTH_STENCIL::Backface Stencil Test Mask */ #define GFX125_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilTestMask_bits 8 #define GFX12_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilTestMask_bits 8 #define GFX11_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilTestMask_bits 8 #define GFX9_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilTestMask_bits 8 #define GFX8_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilTestMask_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilTestMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilTestMask_start 72 #define GFX12_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilTestMask_start 72 #define GFX11_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilTestMask_start 72 #define GFX9_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilTestMask_start 72 #define GFX8_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilTestMask_start 72 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilTestMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 72; case 120: return 72; case 110: return 72; case 90: return 72; case 80: return 72; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM_DEPTH_STENCIL::Backface Stencil Write Mask */ #define GFX125_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilWriteMask_bits 8 #define GFX12_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilWriteMask_bits 8 #define GFX11_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilWriteMask_bits 8 #define GFX9_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilWriteMask_bits 8 #define GFX8_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilWriteMask_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilWriteMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilWriteMask_start 64 #define GFX12_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilWriteMask_start 64 #define GFX11_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilWriteMask_start 64 #define GFX9_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilWriteMask_start 64 #define GFX8_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilWriteMask_start 64 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilWriteMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 64; case 80: return 64; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM_DEPTH_STENCIL::Command SubType */ #define GFX125_3DSTATE_WM_DEPTH_STENCIL_CommandSubType_bits 2 #define GFX12_3DSTATE_WM_DEPTH_STENCIL_CommandSubType_bits 2 #define GFX11_3DSTATE_WM_DEPTH_STENCIL_CommandSubType_bits 2 #define GFX9_3DSTATE_WM_DEPTH_STENCIL_CommandSubType_bits 2 #define GFX8_3DSTATE_WM_DEPTH_STENCIL_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_DEPTH_STENCIL_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_DEPTH_STENCIL_CommandSubType_start 27 #define GFX12_3DSTATE_WM_DEPTH_STENCIL_CommandSubType_start 27 #define GFX11_3DSTATE_WM_DEPTH_STENCIL_CommandSubType_start 27 #define GFX9_3DSTATE_WM_DEPTH_STENCIL_CommandSubType_start 27 #define GFX8_3DSTATE_WM_DEPTH_STENCIL_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_DEPTH_STENCIL_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM_DEPTH_STENCIL::Command Type */ #define GFX125_3DSTATE_WM_DEPTH_STENCIL_CommandType_bits 3 #define GFX12_3DSTATE_WM_DEPTH_STENCIL_CommandType_bits 3 #define GFX11_3DSTATE_WM_DEPTH_STENCIL_CommandType_bits 3 #define GFX9_3DSTATE_WM_DEPTH_STENCIL_CommandType_bits 3 #define GFX8_3DSTATE_WM_DEPTH_STENCIL_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_DEPTH_STENCIL_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_DEPTH_STENCIL_CommandType_start 29 #define GFX12_3DSTATE_WM_DEPTH_STENCIL_CommandType_start 29 #define GFX11_3DSTATE_WM_DEPTH_STENCIL_CommandType_start 29 #define GFX9_3DSTATE_WM_DEPTH_STENCIL_CommandType_start 29 #define GFX8_3DSTATE_WM_DEPTH_STENCIL_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_DEPTH_STENCIL_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM_DEPTH_STENCIL::DWord Length */ #define GFX125_3DSTATE_WM_DEPTH_STENCIL_DWordLength_bits 8 #define GFX12_3DSTATE_WM_DEPTH_STENCIL_DWordLength_bits 8 #define GFX11_3DSTATE_WM_DEPTH_STENCIL_DWordLength_bits 8 #define GFX9_3DSTATE_WM_DEPTH_STENCIL_DWordLength_bits 8 #define GFX8_3DSTATE_WM_DEPTH_STENCIL_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_DEPTH_STENCIL_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_DEPTH_STENCIL_DWordLength_start 0 #define GFX12_3DSTATE_WM_DEPTH_STENCIL_DWordLength_start 0 #define GFX11_3DSTATE_WM_DEPTH_STENCIL_DWordLength_start 0 #define GFX9_3DSTATE_WM_DEPTH_STENCIL_DWordLength_start 0 #define GFX8_3DSTATE_WM_DEPTH_STENCIL_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_DEPTH_STENCIL_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM_DEPTH_STENCIL::Depth Buffer Write Enable */ #define GFX125_3DSTATE_WM_DEPTH_STENCIL_DepthBufferWriteEnable_bits 1 #define GFX12_3DSTATE_WM_DEPTH_STENCIL_DepthBufferWriteEnable_bits 1 #define GFX11_3DSTATE_WM_DEPTH_STENCIL_DepthBufferWriteEnable_bits 1 #define GFX9_3DSTATE_WM_DEPTH_STENCIL_DepthBufferWriteEnable_bits 1 #define GFX8_3DSTATE_WM_DEPTH_STENCIL_DepthBufferWriteEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_DEPTH_STENCIL_DepthBufferWriteEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_DEPTH_STENCIL_DepthBufferWriteEnable_start 32 #define GFX12_3DSTATE_WM_DEPTH_STENCIL_DepthBufferWriteEnable_start 32 #define GFX11_3DSTATE_WM_DEPTH_STENCIL_DepthBufferWriteEnable_start 32 #define GFX9_3DSTATE_WM_DEPTH_STENCIL_DepthBufferWriteEnable_start 32 #define GFX8_3DSTATE_WM_DEPTH_STENCIL_DepthBufferWriteEnable_start 32 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_DEPTH_STENCIL_DepthBufferWriteEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM_DEPTH_STENCIL::Depth State Modify Disable */ #define GFX125_3DSTATE_WM_DEPTH_STENCIL_DepthStateModifyDisable_bits 1 #define GFX12_3DSTATE_WM_DEPTH_STENCIL_DepthStateModifyDisable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_DEPTH_STENCIL_DepthStateModifyDisable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_DEPTH_STENCIL_DepthStateModifyDisable_start 12 #define GFX12_3DSTATE_WM_DEPTH_STENCIL_DepthStateModifyDisable_start 12 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_DEPTH_STENCIL_DepthStateModifyDisable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 12; case 120: return 12; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM_DEPTH_STENCIL::Depth Test Enable */ #define GFX125_3DSTATE_WM_DEPTH_STENCIL_DepthTestEnable_bits 1 #define GFX12_3DSTATE_WM_DEPTH_STENCIL_DepthTestEnable_bits 1 #define GFX11_3DSTATE_WM_DEPTH_STENCIL_DepthTestEnable_bits 1 #define GFX9_3DSTATE_WM_DEPTH_STENCIL_DepthTestEnable_bits 1 #define GFX8_3DSTATE_WM_DEPTH_STENCIL_DepthTestEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_DEPTH_STENCIL_DepthTestEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_DEPTH_STENCIL_DepthTestEnable_start 33 #define GFX12_3DSTATE_WM_DEPTH_STENCIL_DepthTestEnable_start 33 #define GFX11_3DSTATE_WM_DEPTH_STENCIL_DepthTestEnable_start 33 #define GFX9_3DSTATE_WM_DEPTH_STENCIL_DepthTestEnable_start 33 #define GFX8_3DSTATE_WM_DEPTH_STENCIL_DepthTestEnable_start 33 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_DEPTH_STENCIL_DepthTestEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 33; case 120: return 33; case 110: return 33; case 90: return 33; case 80: return 33; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM_DEPTH_STENCIL::Depth Test Function */ #define GFX125_3DSTATE_WM_DEPTH_STENCIL_DepthTestFunction_bits 3 #define GFX12_3DSTATE_WM_DEPTH_STENCIL_DepthTestFunction_bits 3 #define GFX11_3DSTATE_WM_DEPTH_STENCIL_DepthTestFunction_bits 3 #define GFX9_3DSTATE_WM_DEPTH_STENCIL_DepthTestFunction_bits 3 #define GFX8_3DSTATE_WM_DEPTH_STENCIL_DepthTestFunction_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_DEPTH_STENCIL_DepthTestFunction_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_DEPTH_STENCIL_DepthTestFunction_start 37 #define GFX12_3DSTATE_WM_DEPTH_STENCIL_DepthTestFunction_start 37 #define GFX11_3DSTATE_WM_DEPTH_STENCIL_DepthTestFunction_start 37 #define GFX9_3DSTATE_WM_DEPTH_STENCIL_DepthTestFunction_start 37 #define GFX8_3DSTATE_WM_DEPTH_STENCIL_DepthTestFunction_start 37 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_DEPTH_STENCIL_DepthTestFunction_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 37; case 120: return 37; case 110: return 37; case 90: return 37; case 80: return 37; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM_DEPTH_STENCIL::Double Sided Stencil Enable */ #define GFX125_3DSTATE_WM_DEPTH_STENCIL_DoubleSidedStencilEnable_bits 1 #define GFX12_3DSTATE_WM_DEPTH_STENCIL_DoubleSidedStencilEnable_bits 1 #define GFX11_3DSTATE_WM_DEPTH_STENCIL_DoubleSidedStencilEnable_bits 1 #define GFX9_3DSTATE_WM_DEPTH_STENCIL_DoubleSidedStencilEnable_bits 1 #define GFX8_3DSTATE_WM_DEPTH_STENCIL_DoubleSidedStencilEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_DEPTH_STENCIL_DoubleSidedStencilEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_DEPTH_STENCIL_DoubleSidedStencilEnable_start 36 #define GFX12_3DSTATE_WM_DEPTH_STENCIL_DoubleSidedStencilEnable_start 36 #define GFX11_3DSTATE_WM_DEPTH_STENCIL_DoubleSidedStencilEnable_start 36 #define GFX9_3DSTATE_WM_DEPTH_STENCIL_DoubleSidedStencilEnable_start 36 #define GFX8_3DSTATE_WM_DEPTH_STENCIL_DoubleSidedStencilEnable_start 36 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_DEPTH_STENCIL_DoubleSidedStencilEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 36; case 120: return 36; case 110: return 36; case 90: return 36; case 80: return 36; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM_DEPTH_STENCIL::Stencil Buffer Write Enable */ #define GFX125_3DSTATE_WM_DEPTH_STENCIL_StencilBufferWriteEnable_bits 1 #define GFX12_3DSTATE_WM_DEPTH_STENCIL_StencilBufferWriteEnable_bits 1 #define GFX11_3DSTATE_WM_DEPTH_STENCIL_StencilBufferWriteEnable_bits 1 #define GFX9_3DSTATE_WM_DEPTH_STENCIL_StencilBufferWriteEnable_bits 1 #define GFX8_3DSTATE_WM_DEPTH_STENCIL_StencilBufferWriteEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_DEPTH_STENCIL_StencilBufferWriteEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_DEPTH_STENCIL_StencilBufferWriteEnable_start 34 #define GFX12_3DSTATE_WM_DEPTH_STENCIL_StencilBufferWriteEnable_start 34 #define GFX11_3DSTATE_WM_DEPTH_STENCIL_StencilBufferWriteEnable_start 34 #define GFX9_3DSTATE_WM_DEPTH_STENCIL_StencilBufferWriteEnable_start 34 #define GFX8_3DSTATE_WM_DEPTH_STENCIL_StencilBufferWriteEnable_start 34 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_DEPTH_STENCIL_StencilBufferWriteEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 34; case 120: return 34; case 110: return 34; case 90: return 34; case 80: return 34; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM_DEPTH_STENCIL::Stencil Fail Op */ #define GFX125_3DSTATE_WM_DEPTH_STENCIL_StencilFailOp_bits 3 #define GFX12_3DSTATE_WM_DEPTH_STENCIL_StencilFailOp_bits 3 #define GFX11_3DSTATE_WM_DEPTH_STENCIL_StencilFailOp_bits 3 #define GFX9_3DSTATE_WM_DEPTH_STENCIL_StencilFailOp_bits 3 #define GFX8_3DSTATE_WM_DEPTH_STENCIL_StencilFailOp_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_DEPTH_STENCIL_StencilFailOp_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_DEPTH_STENCIL_StencilFailOp_start 61 #define GFX12_3DSTATE_WM_DEPTH_STENCIL_StencilFailOp_start 61 #define GFX11_3DSTATE_WM_DEPTH_STENCIL_StencilFailOp_start 61 #define GFX9_3DSTATE_WM_DEPTH_STENCIL_StencilFailOp_start 61 #define GFX8_3DSTATE_WM_DEPTH_STENCIL_StencilFailOp_start 61 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_DEPTH_STENCIL_StencilFailOp_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 61; case 120: return 61; case 110: return 61; case 90: return 61; case 80: return 61; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM_DEPTH_STENCIL::Stencil Pass Depth Fail Op */ #define GFX125_3DSTATE_WM_DEPTH_STENCIL_StencilPassDepthFailOp_bits 3 #define GFX12_3DSTATE_WM_DEPTH_STENCIL_StencilPassDepthFailOp_bits 3 #define GFX11_3DSTATE_WM_DEPTH_STENCIL_StencilPassDepthFailOp_bits 3 #define GFX9_3DSTATE_WM_DEPTH_STENCIL_StencilPassDepthFailOp_bits 3 #define GFX8_3DSTATE_WM_DEPTH_STENCIL_StencilPassDepthFailOp_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_DEPTH_STENCIL_StencilPassDepthFailOp_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_DEPTH_STENCIL_StencilPassDepthFailOp_start 58 #define GFX12_3DSTATE_WM_DEPTH_STENCIL_StencilPassDepthFailOp_start 58 #define GFX11_3DSTATE_WM_DEPTH_STENCIL_StencilPassDepthFailOp_start 58 #define GFX9_3DSTATE_WM_DEPTH_STENCIL_StencilPassDepthFailOp_start 58 #define GFX8_3DSTATE_WM_DEPTH_STENCIL_StencilPassDepthFailOp_start 58 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_DEPTH_STENCIL_StencilPassDepthFailOp_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 58; case 120: return 58; case 110: return 58; case 90: return 58; case 80: return 58; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM_DEPTH_STENCIL::Stencil Pass Depth Pass Op */ #define GFX125_3DSTATE_WM_DEPTH_STENCIL_StencilPassDepthPassOp_bits 3 #define GFX12_3DSTATE_WM_DEPTH_STENCIL_StencilPassDepthPassOp_bits 3 #define GFX11_3DSTATE_WM_DEPTH_STENCIL_StencilPassDepthPassOp_bits 3 #define GFX9_3DSTATE_WM_DEPTH_STENCIL_StencilPassDepthPassOp_bits 3 #define GFX8_3DSTATE_WM_DEPTH_STENCIL_StencilPassDepthPassOp_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_DEPTH_STENCIL_StencilPassDepthPassOp_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_DEPTH_STENCIL_StencilPassDepthPassOp_start 55 #define GFX12_3DSTATE_WM_DEPTH_STENCIL_StencilPassDepthPassOp_start 55 #define GFX11_3DSTATE_WM_DEPTH_STENCIL_StencilPassDepthPassOp_start 55 #define GFX9_3DSTATE_WM_DEPTH_STENCIL_StencilPassDepthPassOp_start 55 #define GFX8_3DSTATE_WM_DEPTH_STENCIL_StencilPassDepthPassOp_start 55 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_DEPTH_STENCIL_StencilPassDepthPassOp_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 55; case 120: return 55; case 110: return 55; case 90: return 55; case 80: return 55; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM_DEPTH_STENCIL::Stencil Reference Value */ #define GFX125_3DSTATE_WM_DEPTH_STENCIL_StencilReferenceValue_bits 8 #define GFX12_3DSTATE_WM_DEPTH_STENCIL_StencilReferenceValue_bits 8 #define GFX11_3DSTATE_WM_DEPTH_STENCIL_StencilReferenceValue_bits 8 #define GFX9_3DSTATE_WM_DEPTH_STENCIL_StencilReferenceValue_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_DEPTH_STENCIL_StencilReferenceValue_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_DEPTH_STENCIL_StencilReferenceValue_start 104 #define GFX12_3DSTATE_WM_DEPTH_STENCIL_StencilReferenceValue_start 104 #define GFX11_3DSTATE_WM_DEPTH_STENCIL_StencilReferenceValue_start 104 #define GFX9_3DSTATE_WM_DEPTH_STENCIL_StencilReferenceValue_start 104 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_DEPTH_STENCIL_StencilReferenceValue_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 104; case 120: return 104; case 110: return 104; case 90: return 104; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM_DEPTH_STENCIL::Stencil Reference Value Modify Disable */ #define GFX125_3DSTATE_WM_DEPTH_STENCIL_StencilReferenceValueModifyDisable_bits 1 #define GFX12_3DSTATE_WM_DEPTH_STENCIL_StencilReferenceValueModifyDisable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_DEPTH_STENCIL_StencilReferenceValueModifyDisable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_DEPTH_STENCIL_StencilReferenceValueModifyDisable_start 8 #define GFX12_3DSTATE_WM_DEPTH_STENCIL_StencilReferenceValueModifyDisable_start 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_DEPTH_STENCIL_StencilReferenceValueModifyDisable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM_DEPTH_STENCIL::Stencil State Modify Disable */ #define GFX125_3DSTATE_WM_DEPTH_STENCIL_StencilStateModifyDisable_bits 1 #define GFX12_3DSTATE_WM_DEPTH_STENCIL_StencilStateModifyDisable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_DEPTH_STENCIL_StencilStateModifyDisable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_DEPTH_STENCIL_StencilStateModifyDisable_start 11 #define GFX12_3DSTATE_WM_DEPTH_STENCIL_StencilStateModifyDisable_start 11 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_DEPTH_STENCIL_StencilStateModifyDisable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 11; case 120: return 11; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM_DEPTH_STENCIL::Stencil Test Enable */ #define GFX125_3DSTATE_WM_DEPTH_STENCIL_StencilTestEnable_bits 1 #define GFX12_3DSTATE_WM_DEPTH_STENCIL_StencilTestEnable_bits 1 #define GFX11_3DSTATE_WM_DEPTH_STENCIL_StencilTestEnable_bits 1 #define GFX9_3DSTATE_WM_DEPTH_STENCIL_StencilTestEnable_bits 1 #define GFX8_3DSTATE_WM_DEPTH_STENCIL_StencilTestEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_DEPTH_STENCIL_StencilTestEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_DEPTH_STENCIL_StencilTestEnable_start 35 #define GFX12_3DSTATE_WM_DEPTH_STENCIL_StencilTestEnable_start 35 #define GFX11_3DSTATE_WM_DEPTH_STENCIL_StencilTestEnable_start 35 #define GFX9_3DSTATE_WM_DEPTH_STENCIL_StencilTestEnable_start 35 #define GFX8_3DSTATE_WM_DEPTH_STENCIL_StencilTestEnable_start 35 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_DEPTH_STENCIL_StencilTestEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 35; case 120: return 35; case 110: return 35; case 90: return 35; case 80: return 35; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM_DEPTH_STENCIL::Stencil Test Function */ #define GFX125_3DSTATE_WM_DEPTH_STENCIL_StencilTestFunction_bits 3 #define GFX12_3DSTATE_WM_DEPTH_STENCIL_StencilTestFunction_bits 3 #define GFX11_3DSTATE_WM_DEPTH_STENCIL_StencilTestFunction_bits 3 #define GFX9_3DSTATE_WM_DEPTH_STENCIL_StencilTestFunction_bits 3 #define GFX8_3DSTATE_WM_DEPTH_STENCIL_StencilTestFunction_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_DEPTH_STENCIL_StencilTestFunction_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_DEPTH_STENCIL_StencilTestFunction_start 40 #define GFX12_3DSTATE_WM_DEPTH_STENCIL_StencilTestFunction_start 40 #define GFX11_3DSTATE_WM_DEPTH_STENCIL_StencilTestFunction_start 40 #define GFX9_3DSTATE_WM_DEPTH_STENCIL_StencilTestFunction_start 40 #define GFX8_3DSTATE_WM_DEPTH_STENCIL_StencilTestFunction_start 40 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_DEPTH_STENCIL_StencilTestFunction_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 40; case 120: return 40; case 110: return 40; case 90: return 40; case 80: return 40; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM_DEPTH_STENCIL::Stencil Test Mask */ #define GFX125_3DSTATE_WM_DEPTH_STENCIL_StencilTestMask_bits 8 #define GFX12_3DSTATE_WM_DEPTH_STENCIL_StencilTestMask_bits 8 #define GFX11_3DSTATE_WM_DEPTH_STENCIL_StencilTestMask_bits 8 #define GFX9_3DSTATE_WM_DEPTH_STENCIL_StencilTestMask_bits 8 #define GFX8_3DSTATE_WM_DEPTH_STENCIL_StencilTestMask_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_DEPTH_STENCIL_StencilTestMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_DEPTH_STENCIL_StencilTestMask_start 88 #define GFX12_3DSTATE_WM_DEPTH_STENCIL_StencilTestMask_start 88 #define GFX11_3DSTATE_WM_DEPTH_STENCIL_StencilTestMask_start 88 #define GFX9_3DSTATE_WM_DEPTH_STENCIL_StencilTestMask_start 88 #define GFX8_3DSTATE_WM_DEPTH_STENCIL_StencilTestMask_start 88 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_DEPTH_STENCIL_StencilTestMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 88; case 120: return 88; case 110: return 88; case 90: return 88; case 80: return 88; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM_DEPTH_STENCIL::Stencil Test Mask Modify Disable */ #define GFX125_3DSTATE_WM_DEPTH_STENCIL_StencilTestMaskModifyDisable_bits 1 #define GFX12_3DSTATE_WM_DEPTH_STENCIL_StencilTestMaskModifyDisable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_DEPTH_STENCIL_StencilTestMaskModifyDisable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_DEPTH_STENCIL_StencilTestMaskModifyDisable_start 9 #define GFX12_3DSTATE_WM_DEPTH_STENCIL_StencilTestMaskModifyDisable_start 9 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_DEPTH_STENCIL_StencilTestMaskModifyDisable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 9; case 120: return 9; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM_DEPTH_STENCIL::Stencil Write Mask */ #define GFX125_3DSTATE_WM_DEPTH_STENCIL_StencilWriteMask_bits 8 #define GFX12_3DSTATE_WM_DEPTH_STENCIL_StencilWriteMask_bits 8 #define GFX11_3DSTATE_WM_DEPTH_STENCIL_StencilWriteMask_bits 8 #define GFX9_3DSTATE_WM_DEPTH_STENCIL_StencilWriteMask_bits 8 #define GFX8_3DSTATE_WM_DEPTH_STENCIL_StencilWriteMask_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_DEPTH_STENCIL_StencilWriteMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_DEPTH_STENCIL_StencilWriteMask_start 80 #define GFX12_3DSTATE_WM_DEPTH_STENCIL_StencilWriteMask_start 80 #define GFX11_3DSTATE_WM_DEPTH_STENCIL_StencilWriteMask_start 80 #define GFX9_3DSTATE_WM_DEPTH_STENCIL_StencilWriteMask_start 80 #define GFX8_3DSTATE_WM_DEPTH_STENCIL_StencilWriteMask_start 80 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_DEPTH_STENCIL_StencilWriteMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 80; case 120: return 80; case 110: return 80; case 90: return 80; case 80: return 80; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM_DEPTH_STENCIL::Stencil Write Mask Modify Disable */ #define GFX125_3DSTATE_WM_DEPTH_STENCIL_StencilWriteMaskModifyDisable_bits 1 #define GFX12_3DSTATE_WM_DEPTH_STENCIL_StencilWriteMaskModifyDisable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_DEPTH_STENCIL_StencilWriteMaskModifyDisable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_DEPTH_STENCIL_StencilWriteMaskModifyDisable_start 10 #define GFX12_3DSTATE_WM_DEPTH_STENCIL_StencilWriteMaskModifyDisable_start 10 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_DEPTH_STENCIL_StencilWriteMaskModifyDisable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 10; case 120: return 10; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM_HZ_OP */ #define GFX125_3DSTATE_WM_HZ_OP_length 5 #define GFX12_3DSTATE_WM_HZ_OP_length 5 #define GFX11_3DSTATE_WM_HZ_OP_length 5 #define GFX9_3DSTATE_WM_HZ_OP_length 5 #define GFX8_3DSTATE_WM_HZ_OP_length 5 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_HZ_OP_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 5; case 110: return 5; case 90: return 5; case 80: return 5; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM_HZ_OP::3D Command Opcode */ #define GFX125_3DSTATE_WM_HZ_OP_3DCommandOpcode_bits 3 #define GFX12_3DSTATE_WM_HZ_OP_3DCommandOpcode_bits 3 #define GFX11_3DSTATE_WM_HZ_OP_3DCommandOpcode_bits 3 #define GFX9_3DSTATE_WM_HZ_OP_3DCommandOpcode_bits 3 #define GFX8_3DSTATE_WM_HZ_OP_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_HZ_OP_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_HZ_OP_3DCommandOpcode_start 24 #define GFX12_3DSTATE_WM_HZ_OP_3DCommandOpcode_start 24 #define GFX11_3DSTATE_WM_HZ_OP_3DCommandOpcode_start 24 #define GFX9_3DSTATE_WM_HZ_OP_3DCommandOpcode_start 24 #define GFX8_3DSTATE_WM_HZ_OP_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_HZ_OP_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM_HZ_OP::3D Command Sub Opcode */ #define GFX125_3DSTATE_WM_HZ_OP_3DCommandSubOpcode_bits 8 #define GFX12_3DSTATE_WM_HZ_OP_3DCommandSubOpcode_bits 8 #define GFX11_3DSTATE_WM_HZ_OP_3DCommandSubOpcode_bits 8 #define GFX9_3DSTATE_WM_HZ_OP_3DCommandSubOpcode_bits 8 #define GFX8_3DSTATE_WM_HZ_OP_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_HZ_OP_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_HZ_OP_3DCommandSubOpcode_start 16 #define GFX12_3DSTATE_WM_HZ_OP_3DCommandSubOpcode_start 16 #define GFX11_3DSTATE_WM_HZ_OP_3DCommandSubOpcode_start 16 #define GFX9_3DSTATE_WM_HZ_OP_3DCommandSubOpcode_start 16 #define GFX8_3DSTATE_WM_HZ_OP_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_HZ_OP_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM_HZ_OP::Clear Rectangle X Max */ #define GFX125_3DSTATE_WM_HZ_OP_ClearRectangleXMax_bits 16 #define GFX12_3DSTATE_WM_HZ_OP_ClearRectangleXMax_bits 16 #define GFX11_3DSTATE_WM_HZ_OP_ClearRectangleXMax_bits 16 #define GFX9_3DSTATE_WM_HZ_OP_ClearRectangleXMax_bits 16 #define GFX8_3DSTATE_WM_HZ_OP_ClearRectangleXMax_bits 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_HZ_OP_ClearRectangleXMax_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_HZ_OP_ClearRectangleXMax_start 96 #define GFX12_3DSTATE_WM_HZ_OP_ClearRectangleXMax_start 96 #define GFX11_3DSTATE_WM_HZ_OP_ClearRectangleXMax_start 96 #define GFX9_3DSTATE_WM_HZ_OP_ClearRectangleXMax_start 96 #define GFX8_3DSTATE_WM_HZ_OP_ClearRectangleXMax_start 96 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_HZ_OP_ClearRectangleXMax_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 96; case 120: return 96; case 110: return 96; case 90: return 96; case 80: return 96; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM_HZ_OP::Clear Rectangle X Min */ #define GFX125_3DSTATE_WM_HZ_OP_ClearRectangleXMin_bits 16 #define GFX12_3DSTATE_WM_HZ_OP_ClearRectangleXMin_bits 16 #define GFX11_3DSTATE_WM_HZ_OP_ClearRectangleXMin_bits 16 #define GFX9_3DSTATE_WM_HZ_OP_ClearRectangleXMin_bits 16 #define GFX8_3DSTATE_WM_HZ_OP_ClearRectangleXMin_bits 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_HZ_OP_ClearRectangleXMin_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_HZ_OP_ClearRectangleXMin_start 64 #define GFX12_3DSTATE_WM_HZ_OP_ClearRectangleXMin_start 64 #define GFX11_3DSTATE_WM_HZ_OP_ClearRectangleXMin_start 64 #define GFX9_3DSTATE_WM_HZ_OP_ClearRectangleXMin_start 64 #define GFX8_3DSTATE_WM_HZ_OP_ClearRectangleXMin_start 64 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_HZ_OP_ClearRectangleXMin_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 64; case 80: return 64; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM_HZ_OP::Clear Rectangle Y Max */ #define GFX125_3DSTATE_WM_HZ_OP_ClearRectangleYMax_bits 16 #define GFX12_3DSTATE_WM_HZ_OP_ClearRectangleYMax_bits 16 #define GFX11_3DSTATE_WM_HZ_OP_ClearRectangleYMax_bits 16 #define GFX9_3DSTATE_WM_HZ_OP_ClearRectangleYMax_bits 16 #define GFX8_3DSTATE_WM_HZ_OP_ClearRectangleYMax_bits 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_HZ_OP_ClearRectangleYMax_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_HZ_OP_ClearRectangleYMax_start 112 #define GFX12_3DSTATE_WM_HZ_OP_ClearRectangleYMax_start 112 #define GFX11_3DSTATE_WM_HZ_OP_ClearRectangleYMax_start 112 #define GFX9_3DSTATE_WM_HZ_OP_ClearRectangleYMax_start 112 #define GFX8_3DSTATE_WM_HZ_OP_ClearRectangleYMax_start 112 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_HZ_OP_ClearRectangleYMax_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 112; case 120: return 112; case 110: return 112; case 90: return 112; case 80: return 112; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM_HZ_OP::Clear Rectangle Y Min */ #define GFX125_3DSTATE_WM_HZ_OP_ClearRectangleYMin_bits 16 #define GFX12_3DSTATE_WM_HZ_OP_ClearRectangleYMin_bits 16 #define GFX11_3DSTATE_WM_HZ_OP_ClearRectangleYMin_bits 16 #define GFX9_3DSTATE_WM_HZ_OP_ClearRectangleYMin_bits 16 #define GFX8_3DSTATE_WM_HZ_OP_ClearRectangleYMin_bits 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_HZ_OP_ClearRectangleYMin_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_HZ_OP_ClearRectangleYMin_start 80 #define GFX12_3DSTATE_WM_HZ_OP_ClearRectangleYMin_start 80 #define GFX11_3DSTATE_WM_HZ_OP_ClearRectangleYMin_start 80 #define GFX9_3DSTATE_WM_HZ_OP_ClearRectangleYMin_start 80 #define GFX8_3DSTATE_WM_HZ_OP_ClearRectangleYMin_start 80 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_HZ_OP_ClearRectangleYMin_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 80; case 120: return 80; case 110: return 80; case 90: return 80; case 80: return 80; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM_HZ_OP::Command SubType */ #define GFX125_3DSTATE_WM_HZ_OP_CommandSubType_bits 2 #define GFX12_3DSTATE_WM_HZ_OP_CommandSubType_bits 2 #define GFX11_3DSTATE_WM_HZ_OP_CommandSubType_bits 2 #define GFX9_3DSTATE_WM_HZ_OP_CommandSubType_bits 2 #define GFX8_3DSTATE_WM_HZ_OP_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_HZ_OP_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_HZ_OP_CommandSubType_start 27 #define GFX12_3DSTATE_WM_HZ_OP_CommandSubType_start 27 #define GFX11_3DSTATE_WM_HZ_OP_CommandSubType_start 27 #define GFX9_3DSTATE_WM_HZ_OP_CommandSubType_start 27 #define GFX8_3DSTATE_WM_HZ_OP_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_HZ_OP_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM_HZ_OP::Command Type */ #define GFX125_3DSTATE_WM_HZ_OP_CommandType_bits 3 #define GFX12_3DSTATE_WM_HZ_OP_CommandType_bits 3 #define GFX11_3DSTATE_WM_HZ_OP_CommandType_bits 3 #define GFX9_3DSTATE_WM_HZ_OP_CommandType_bits 3 #define GFX8_3DSTATE_WM_HZ_OP_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_HZ_OP_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_HZ_OP_CommandType_start 29 #define GFX12_3DSTATE_WM_HZ_OP_CommandType_start 29 #define GFX11_3DSTATE_WM_HZ_OP_CommandType_start 29 #define GFX9_3DSTATE_WM_HZ_OP_CommandType_start 29 #define GFX8_3DSTATE_WM_HZ_OP_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_HZ_OP_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM_HZ_OP::DWord Length */ #define GFX125_3DSTATE_WM_HZ_OP_DWordLength_bits 8 #define GFX12_3DSTATE_WM_HZ_OP_DWordLength_bits 8 #define GFX11_3DSTATE_WM_HZ_OP_DWordLength_bits 8 #define GFX9_3DSTATE_WM_HZ_OP_DWordLength_bits 8 #define GFX8_3DSTATE_WM_HZ_OP_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_HZ_OP_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_HZ_OP_DWordLength_start 0 #define GFX12_3DSTATE_WM_HZ_OP_DWordLength_start 0 #define GFX11_3DSTATE_WM_HZ_OP_DWordLength_start 0 #define GFX9_3DSTATE_WM_HZ_OP_DWordLength_start 0 #define GFX8_3DSTATE_WM_HZ_OP_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_HZ_OP_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM_HZ_OP::Depth Buffer Clear Enable */ #define GFX125_3DSTATE_WM_HZ_OP_DepthBufferClearEnable_bits 1 #define GFX12_3DSTATE_WM_HZ_OP_DepthBufferClearEnable_bits 1 #define GFX11_3DSTATE_WM_HZ_OP_DepthBufferClearEnable_bits 1 #define GFX9_3DSTATE_WM_HZ_OP_DepthBufferClearEnable_bits 1 #define GFX8_3DSTATE_WM_HZ_OP_DepthBufferClearEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_HZ_OP_DepthBufferClearEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_HZ_OP_DepthBufferClearEnable_start 62 #define GFX12_3DSTATE_WM_HZ_OP_DepthBufferClearEnable_start 62 #define GFX11_3DSTATE_WM_HZ_OP_DepthBufferClearEnable_start 62 #define GFX9_3DSTATE_WM_HZ_OP_DepthBufferClearEnable_start 62 #define GFX8_3DSTATE_WM_HZ_OP_DepthBufferClearEnable_start 62 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_HZ_OP_DepthBufferClearEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 62; case 120: return 62; case 110: return 62; case 90: return 62; case 80: return 62; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM_HZ_OP::Depth Buffer Resolve Enable */ #define GFX125_3DSTATE_WM_HZ_OP_DepthBufferResolveEnable_bits 1 #define GFX12_3DSTATE_WM_HZ_OP_DepthBufferResolveEnable_bits 1 #define GFX11_3DSTATE_WM_HZ_OP_DepthBufferResolveEnable_bits 1 #define GFX9_3DSTATE_WM_HZ_OP_DepthBufferResolveEnable_bits 1 #define GFX8_3DSTATE_WM_HZ_OP_DepthBufferResolveEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_HZ_OP_DepthBufferResolveEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_HZ_OP_DepthBufferResolveEnable_start 60 #define GFX12_3DSTATE_WM_HZ_OP_DepthBufferResolveEnable_start 60 #define GFX11_3DSTATE_WM_HZ_OP_DepthBufferResolveEnable_start 60 #define GFX9_3DSTATE_WM_HZ_OP_DepthBufferResolveEnable_start 60 #define GFX8_3DSTATE_WM_HZ_OP_DepthBufferResolveEnable_start 60 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_HZ_OP_DepthBufferResolveEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 60; case 120: return 60; case 110: return 60; case 90: return 60; case 80: return 60; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM_HZ_OP::Full Surface Depth and Stencil Clear */ #define GFX125_3DSTATE_WM_HZ_OP_FullSurfaceDepthandStencilClear_bits 1 #define GFX12_3DSTATE_WM_HZ_OP_FullSurfaceDepthandStencilClear_bits 1 #define GFX11_3DSTATE_WM_HZ_OP_FullSurfaceDepthandStencilClear_bits 1 #define GFX9_3DSTATE_WM_HZ_OP_FullSurfaceDepthandStencilClear_bits 1 #define GFX8_3DSTATE_WM_HZ_OP_FullSurfaceDepthandStencilClear_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_HZ_OP_FullSurfaceDepthandStencilClear_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_HZ_OP_FullSurfaceDepthandStencilClear_start 57 #define GFX12_3DSTATE_WM_HZ_OP_FullSurfaceDepthandStencilClear_start 57 #define GFX11_3DSTATE_WM_HZ_OP_FullSurfaceDepthandStencilClear_start 57 #define GFX9_3DSTATE_WM_HZ_OP_FullSurfaceDepthandStencilClear_start 57 #define GFX8_3DSTATE_WM_HZ_OP_FullSurfaceDepthandStencilClear_start 57 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_HZ_OP_FullSurfaceDepthandStencilClear_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 57; case 120: return 57; case 110: return 57; case 90: return 57; case 80: return 57; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM_HZ_OP::Hierarchical Depth Buffer Resolve Enable */ #define GFX125_3DSTATE_WM_HZ_OP_HierarchicalDepthBufferResolveEnable_bits 1 #define GFX12_3DSTATE_WM_HZ_OP_HierarchicalDepthBufferResolveEnable_bits 1 #define GFX11_3DSTATE_WM_HZ_OP_HierarchicalDepthBufferResolveEnable_bits 1 #define GFX9_3DSTATE_WM_HZ_OP_HierarchicalDepthBufferResolveEnable_bits 1 #define GFX8_3DSTATE_WM_HZ_OP_HierarchicalDepthBufferResolveEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_HZ_OP_HierarchicalDepthBufferResolveEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_HZ_OP_HierarchicalDepthBufferResolveEnable_start 59 #define GFX12_3DSTATE_WM_HZ_OP_HierarchicalDepthBufferResolveEnable_start 59 #define GFX11_3DSTATE_WM_HZ_OP_HierarchicalDepthBufferResolveEnable_start 59 #define GFX9_3DSTATE_WM_HZ_OP_HierarchicalDepthBufferResolveEnable_start 59 #define GFX8_3DSTATE_WM_HZ_OP_HierarchicalDepthBufferResolveEnable_start 59 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_HZ_OP_HierarchicalDepthBufferResolveEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 59; case 120: return 59; case 110: return 59; case 90: return 59; case 80: return 59; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM_HZ_OP::Number of Multisamples */ #define GFX125_3DSTATE_WM_HZ_OP_NumberofMultisamples_bits 3 #define GFX12_3DSTATE_WM_HZ_OP_NumberofMultisamples_bits 3 #define GFX11_3DSTATE_WM_HZ_OP_NumberofMultisamples_bits 3 #define GFX9_3DSTATE_WM_HZ_OP_NumberofMultisamples_bits 3 #define GFX8_3DSTATE_WM_HZ_OP_NumberofMultisamples_bits 3 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_HZ_OP_NumberofMultisamples_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_HZ_OP_NumberofMultisamples_start 45 #define GFX12_3DSTATE_WM_HZ_OP_NumberofMultisamples_start 45 #define GFX11_3DSTATE_WM_HZ_OP_NumberofMultisamples_start 45 #define GFX9_3DSTATE_WM_HZ_OP_NumberofMultisamples_start 45 #define GFX8_3DSTATE_WM_HZ_OP_NumberofMultisamples_start 45 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_HZ_OP_NumberofMultisamples_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 45; case 120: return 45; case 110: return 45; case 90: return 45; case 80: return 45; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM_HZ_OP::Pixel Position Offset Enable */ #define GFX125_3DSTATE_WM_HZ_OP_PixelPositionOffsetEnable_bits 1 #define GFX12_3DSTATE_WM_HZ_OP_PixelPositionOffsetEnable_bits 1 #define GFX11_3DSTATE_WM_HZ_OP_PixelPositionOffsetEnable_bits 1 #define GFX9_3DSTATE_WM_HZ_OP_PixelPositionOffsetEnable_bits 1 #define GFX8_3DSTATE_WM_HZ_OP_PixelPositionOffsetEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_HZ_OP_PixelPositionOffsetEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_HZ_OP_PixelPositionOffsetEnable_start 58 #define GFX12_3DSTATE_WM_HZ_OP_PixelPositionOffsetEnable_start 58 #define GFX11_3DSTATE_WM_HZ_OP_PixelPositionOffsetEnable_start 58 #define GFX9_3DSTATE_WM_HZ_OP_PixelPositionOffsetEnable_start 58 #define GFX8_3DSTATE_WM_HZ_OP_PixelPositionOffsetEnable_start 58 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_HZ_OP_PixelPositionOffsetEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 58; case 120: return 58; case 110: return 58; case 90: return 58; case 80: return 58; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM_HZ_OP::Sample Mask */ #define GFX125_3DSTATE_WM_HZ_OP_SampleMask_bits 16 #define GFX12_3DSTATE_WM_HZ_OP_SampleMask_bits 16 #define GFX11_3DSTATE_WM_HZ_OP_SampleMask_bits 16 #define GFX9_3DSTATE_WM_HZ_OP_SampleMask_bits 16 #define GFX8_3DSTATE_WM_HZ_OP_SampleMask_bits 16 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_HZ_OP_SampleMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_HZ_OP_SampleMask_start 128 #define GFX12_3DSTATE_WM_HZ_OP_SampleMask_start 128 #define GFX11_3DSTATE_WM_HZ_OP_SampleMask_start 128 #define GFX9_3DSTATE_WM_HZ_OP_SampleMask_start 128 #define GFX8_3DSTATE_WM_HZ_OP_SampleMask_start 128 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_HZ_OP_SampleMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 128; case 120: return 128; case 110: return 128; case 90: return 128; case 80: return 128; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM_HZ_OP::Scissor Rectangle Enable */ #define GFX125_3DSTATE_WM_HZ_OP_ScissorRectangleEnable_bits 1 #define GFX12_3DSTATE_WM_HZ_OP_ScissorRectangleEnable_bits 1 #define GFX11_3DSTATE_WM_HZ_OP_ScissorRectangleEnable_bits 1 #define GFX9_3DSTATE_WM_HZ_OP_ScissorRectangleEnable_bits 1 #define GFX8_3DSTATE_WM_HZ_OP_ScissorRectangleEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_HZ_OP_ScissorRectangleEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_HZ_OP_ScissorRectangleEnable_start 61 #define GFX12_3DSTATE_WM_HZ_OP_ScissorRectangleEnable_start 61 #define GFX11_3DSTATE_WM_HZ_OP_ScissorRectangleEnable_start 61 #define GFX9_3DSTATE_WM_HZ_OP_ScissorRectangleEnable_start 61 #define GFX8_3DSTATE_WM_HZ_OP_ScissorRectangleEnable_start 61 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_HZ_OP_ScissorRectangleEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 61; case 120: return 61; case 110: return 61; case 90: return 61; case 80: return 61; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM_HZ_OP::Stencil Buffer Clear Enable */ #define GFX125_3DSTATE_WM_HZ_OP_StencilBufferClearEnable_bits 1 #define GFX12_3DSTATE_WM_HZ_OP_StencilBufferClearEnable_bits 1 #define GFX11_3DSTATE_WM_HZ_OP_StencilBufferClearEnable_bits 1 #define GFX9_3DSTATE_WM_HZ_OP_StencilBufferClearEnable_bits 1 #define GFX8_3DSTATE_WM_HZ_OP_StencilBufferClearEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_HZ_OP_StencilBufferClearEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_HZ_OP_StencilBufferClearEnable_start 63 #define GFX12_3DSTATE_WM_HZ_OP_StencilBufferClearEnable_start 63 #define GFX11_3DSTATE_WM_HZ_OP_StencilBufferClearEnable_start 63 #define GFX9_3DSTATE_WM_HZ_OP_StencilBufferClearEnable_start 63 #define GFX8_3DSTATE_WM_HZ_OP_StencilBufferClearEnable_start 63 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_HZ_OP_StencilBufferClearEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 63; case 120: return 63; case 110: return 63; case 90: return 63; case 80: return 63; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM_HZ_OP::Stencil Buffer Resolve Enable */ #define GFX125_3DSTATE_WM_HZ_OP_StencilBufferResolveEnable_bits 1 #define GFX12_3DSTATE_WM_HZ_OP_StencilBufferResolveEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_HZ_OP_StencilBufferResolveEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_HZ_OP_StencilBufferResolveEnable_start 56 #define GFX12_3DSTATE_WM_HZ_OP_StencilBufferResolveEnable_start 56 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_HZ_OP_StencilBufferResolveEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 56; case 120: return 56; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3DSTATE_WM_HZ_OP::Stencil Clear Value */ #define GFX125_3DSTATE_WM_HZ_OP_StencilClearValue_bits 8 #define GFX12_3DSTATE_WM_HZ_OP_StencilClearValue_bits 8 #define GFX11_3DSTATE_WM_HZ_OP_StencilClearValue_bits 8 #define GFX9_3DSTATE_WM_HZ_OP_StencilClearValue_bits 8 #define GFX8_3DSTATE_WM_HZ_OP_StencilClearValue_bits 8 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_HZ_OP_StencilClearValue_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_3DSTATE_WM_HZ_OP_StencilClearValue_start 48 #define GFX12_3DSTATE_WM_HZ_OP_StencilClearValue_start 48 #define GFX11_3DSTATE_WM_HZ_OP_StencilClearValue_start 48 #define GFX9_3DSTATE_WM_HZ_OP_StencilClearValue_start 48 #define GFX8_3DSTATE_WM_HZ_OP_StencilClearValue_start 48 static inline uint32_t ATTRIBUTE_PURE _3DSTATE_WM_HZ_OP_StencilClearValue_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 48; case 120: return 48; case 110: return 48; case 90: return 48; case 80: return 48; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3D_CHICKEN3 */ #define GFX12_3D_CHICKEN3_length 1 #define GFX11_3D_CHICKEN3_length 1 static inline uint32_t ATTRIBUTE_PURE _3D_CHICKEN3_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3D_CHICKEN3::AA Line Quality Fix */ #define GFX12_3D_CHICKEN3_AALineQualityFix_bits 1 #define GFX11_3D_CHICKEN3_AALineQualityFix_bits 1 static inline uint32_t ATTRIBUTE_PURE _3D_CHICKEN3_AALineQualityFix_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_3D_CHICKEN3_AALineQualityFix_start 5 #define GFX11_3D_CHICKEN3_AALineQualityFix_start 5 static inline uint32_t ATTRIBUTE_PURE _3D_CHICKEN3_AALineQualityFix_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 5; case 110: return 5; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* 3D_CHICKEN3::AA Line Quality Fix Mask */ #define GFX12_3D_CHICKEN3_AALineQualityFixMask_bits 1 #define GFX11_3D_CHICKEN3_AALineQualityFixMask_bits 1 static inline uint32_t ATTRIBUTE_PURE _3D_CHICKEN3_AALineQualityFixMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_3D_CHICKEN3_AALineQualityFixMask_start 21 #define GFX11_3D_CHICKEN3_AALineQualityFixMask_start 21 static inline uint32_t ATTRIBUTE_PURE _3D_CHICKEN3_AALineQualityFixMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 21; case 110: return 21; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* ACTHD_UDW */ #define GFX9_ACTHD_UDW_length 1 #define GFX8_ACTHD_UDW_length 1 static inline uint32_t ATTRIBUTE_PURE ACTHD_UDW_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* ACTHD_UDW::Head Pointer Upper DWORD */ #define GFX9_ACTHD_UDW_HeadPointerUpperDWORD_bits 16 #define GFX8_ACTHD_UDW_HeadPointerUpperDWORD_bits 16 static inline uint32_t ATTRIBUTE_PURE ACTHD_UDW_HeadPointerUpperDWORD_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 16; case 80: return 16; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_ACTHD_UDW_HeadPointerUpperDWORD_start 0 #define GFX8_ACTHD_UDW_HeadPointerUpperDWORD_start 0 static inline uint32_t ATTRIBUTE_PURE ACTHD_UDW_HeadPointerUpperDWORD_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* BCS_ACTHD_UDW */ #define GFX9_BCS_ACTHD_UDW_length 1 #define GFX8_BCS_ACTHD_UDW_length 1 static inline uint32_t ATTRIBUTE_PURE BCS_ACTHD_UDW_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* BCS_ACTHD_UDW::Head Pointer Upper DWORD */ #define GFX9_BCS_ACTHD_UDW_HeadPointerUpperDWORD_bits 16 #define GFX8_BCS_ACTHD_UDW_HeadPointerUpperDWORD_bits 16 static inline uint32_t ATTRIBUTE_PURE BCS_ACTHD_UDW_HeadPointerUpperDWORD_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 16; case 80: return 16; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_BCS_ACTHD_UDW_HeadPointerUpperDWORD_start 0 #define GFX8_BCS_ACTHD_UDW_HeadPointerUpperDWORD_start 0 static inline uint32_t ATTRIBUTE_PURE BCS_ACTHD_UDW_HeadPointerUpperDWORD_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* BCS_FAULT_REG */ #define GFX75_BCS_FAULT_REG_length 1 #define GFX7_BCS_FAULT_REG_length 1 #define GFX6_BCS_FAULT_REG_length 1 static inline uint32_t ATTRIBUTE_PURE BCS_FAULT_REG_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* BCS_FAULT_REG::Fault Type */ #define GFX75_BCS_FAULT_REG_FaultType_bits 2 #define GFX7_BCS_FAULT_REG_FaultType_bits 2 #define GFX6_BCS_FAULT_REG_FaultType_bits 2 static inline uint32_t ATTRIBUTE_PURE BCS_FAULT_REG_FaultType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_BCS_FAULT_REG_FaultType_start 1 #define GFX7_BCS_FAULT_REG_FaultType_start 1 #define GFX6_BCS_FAULT_REG_FaultType_start 1 static inline uint32_t ATTRIBUTE_PURE BCS_FAULT_REG_FaultType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* BCS_FAULT_REG::GTTSEL */ #define GFX75_BCS_FAULT_REG_GTTSEL_bits 1 #define GFX7_BCS_FAULT_REG_GTTSEL_bits 1 #define GFX6_BCS_FAULT_REG_GTTSEL_bits 1 static inline uint32_t ATTRIBUTE_PURE BCS_FAULT_REG_GTTSEL_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_BCS_FAULT_REG_GTTSEL_start 11 #define GFX7_BCS_FAULT_REG_GTTSEL_start 11 #define GFX6_BCS_FAULT_REG_GTTSEL_start 11 static inline uint32_t ATTRIBUTE_PURE BCS_FAULT_REG_GTTSEL_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 11; case 70: return 11; case 60: return 11; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* BCS_FAULT_REG::SRCID of Fault */ #define GFX75_BCS_FAULT_REG_SRCIDofFault_bits 8 #define GFX7_BCS_FAULT_REG_SRCIDofFault_bits 8 #define GFX6_BCS_FAULT_REG_SRCIDofFault_bits 8 static inline uint32_t ATTRIBUTE_PURE BCS_FAULT_REG_SRCIDofFault_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_BCS_FAULT_REG_SRCIDofFault_start 3 #define GFX7_BCS_FAULT_REG_SRCIDofFault_start 3 #define GFX6_BCS_FAULT_REG_SRCIDofFault_start 3 static inline uint32_t ATTRIBUTE_PURE BCS_FAULT_REG_SRCIDofFault_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* BCS_FAULT_REG::Valid Bit */ #define GFX75_BCS_FAULT_REG_ValidBit_bits 1 #define GFX7_BCS_FAULT_REG_ValidBit_bits 1 #define GFX6_BCS_FAULT_REG_ValidBit_bits 1 static inline uint32_t ATTRIBUTE_PURE BCS_FAULT_REG_ValidBit_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_BCS_FAULT_REG_ValidBit_start 0 #define GFX7_BCS_FAULT_REG_ValidBit_start 0 #define GFX6_BCS_FAULT_REG_ValidBit_start 0 static inline uint32_t ATTRIBUTE_PURE BCS_FAULT_REG_ValidBit_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* BCS_FAULT_REG::Virtual Address of Fault */ #define GFX75_BCS_FAULT_REG_VirtualAddressofFault_bits 20 #define GFX7_BCS_FAULT_REG_VirtualAddressofFault_bits 20 #define GFX6_BCS_FAULT_REG_VirtualAddressofFault_bits 20 static inline uint32_t ATTRIBUTE_PURE BCS_FAULT_REG_VirtualAddressofFault_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 20; case 70: return 20; case 60: return 20; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_BCS_FAULT_REG_VirtualAddressofFault_start 12 #define GFX7_BCS_FAULT_REG_VirtualAddressofFault_start 12 #define GFX6_BCS_FAULT_REG_VirtualAddressofFault_start 12 static inline uint32_t ATTRIBUTE_PURE BCS_FAULT_REG_VirtualAddressofFault_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 12; case 70: return 12; case 60: return 12; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* BCS_INSTDONE */ #define GFX125_BCS_INSTDONE_length 1 #define GFX12_BCS_INSTDONE_length 1 #define GFX11_BCS_INSTDONE_length 1 #define GFX9_BCS_INSTDONE_length 1 #define GFX8_BCS_INSTDONE_length 1 #define GFX75_BCS_INSTDONE_length 1 #define GFX7_BCS_INSTDONE_length 1 #define GFX6_BCS_INSTDONE_length 1 static inline uint32_t ATTRIBUTE_PURE BCS_INSTDONE_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* BCS_INSTDONE::BCS Done */ #define GFX125_BCS_INSTDONE_BCSDone_bits 1 #define GFX12_BCS_INSTDONE_BCSDone_bits 1 #define GFX11_BCS_INSTDONE_BCSDone_bits 1 #define GFX9_BCS_INSTDONE_BCSDone_bits 1 #define GFX8_BCS_INSTDONE_BCSDone_bits 1 #define GFX75_BCS_INSTDONE_BCSDone_bits 1 #define GFX7_BCS_INSTDONE_BCSDone_bits 1 #define GFX6_BCS_INSTDONE_BCSDone_bits 1 static inline uint32_t ATTRIBUTE_PURE BCS_INSTDONE_BCSDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_BCS_INSTDONE_BCSDone_start 3 #define GFX12_BCS_INSTDONE_BCSDone_start 3 #define GFX11_BCS_INSTDONE_BCSDone_start 3 #define GFX9_BCS_INSTDONE_BCSDone_start 3 #define GFX8_BCS_INSTDONE_BCSDone_start 3 #define GFX75_BCS_INSTDONE_BCSDone_start 3 #define GFX7_BCS_INSTDONE_BCSDone_start 3 #define GFX6_BCS_INSTDONE_BCSDone_start 3 static inline uint32_t ATTRIBUTE_PURE BCS_INSTDONE_BCSDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* BCS_INSTDONE::Blitter IDLE */ #define GFX125_BCS_INSTDONE_BlitterIDLE_bits 1 #define GFX12_BCS_INSTDONE_BlitterIDLE_bits 1 #define GFX11_BCS_INSTDONE_BlitterIDLE_bits 1 #define GFX9_BCS_INSTDONE_BlitterIDLE_bits 1 #define GFX8_BCS_INSTDONE_BlitterIDLE_bits 1 #define GFX75_BCS_INSTDONE_BlitterIDLE_bits 1 #define GFX7_BCS_INSTDONE_BlitterIDLE_bits 1 #define GFX6_BCS_INSTDONE_BlitterIDLE_bits 1 static inline uint32_t ATTRIBUTE_PURE BCS_INSTDONE_BlitterIDLE_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_BCS_INSTDONE_BlitterIDLE_start 1 #define GFX12_BCS_INSTDONE_BlitterIDLE_start 1 #define GFX11_BCS_INSTDONE_BlitterIDLE_start 1 #define GFX9_BCS_INSTDONE_BlitterIDLE_start 1 #define GFX8_BCS_INSTDONE_BlitterIDLE_start 1 #define GFX75_BCS_INSTDONE_BlitterIDLE_start 1 #define GFX7_BCS_INSTDONE_BlitterIDLE_start 1 #define GFX6_BCS_INSTDONE_BlitterIDLE_start 1 static inline uint32_t ATTRIBUTE_PURE BCS_INSTDONE_BlitterIDLE_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* BCS_INSTDONE::GAB IDLE */ #define GFX125_BCS_INSTDONE_GABIDLE_bits 1 #define GFX12_BCS_INSTDONE_GABIDLE_bits 1 #define GFX11_BCS_INSTDONE_GABIDLE_bits 1 #define GFX9_BCS_INSTDONE_GABIDLE_bits 1 #define GFX8_BCS_INSTDONE_GABIDLE_bits 1 #define GFX75_BCS_INSTDONE_GABIDLE_bits 1 #define GFX7_BCS_INSTDONE_GABIDLE_bits 1 #define GFX6_BCS_INSTDONE_GABIDLE_bits 1 static inline uint32_t ATTRIBUTE_PURE BCS_INSTDONE_GABIDLE_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_BCS_INSTDONE_GABIDLE_start 2 #define GFX12_BCS_INSTDONE_GABIDLE_start 2 #define GFX11_BCS_INSTDONE_GABIDLE_start 2 #define GFX9_BCS_INSTDONE_GABIDLE_start 2 #define GFX8_BCS_INSTDONE_GABIDLE_start 2 #define GFX75_BCS_INSTDONE_GABIDLE_start 2 #define GFX7_BCS_INSTDONE_GABIDLE_start 2 #define GFX6_BCS_INSTDONE_GABIDLE_start 2 static inline uint32_t ATTRIBUTE_PURE BCS_INSTDONE_GABIDLE_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* BCS_INSTDONE::Ring Enable */ #define GFX125_BCS_INSTDONE_RingEnable_bits 1 #define GFX12_BCS_INSTDONE_RingEnable_bits 1 #define GFX11_BCS_INSTDONE_RingEnable_bits 1 #define GFX9_BCS_INSTDONE_RingEnable_bits 1 #define GFX8_BCS_INSTDONE_RingEnable_bits 1 #define GFX75_BCS_INSTDONE_RingEnable_bits 1 #define GFX7_BCS_INSTDONE_RingEnable_bits 1 #define GFX6_BCS_INSTDONE_RingEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE BCS_INSTDONE_RingEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_BCS_INSTDONE_RingEnable_start 0 #define GFX12_BCS_INSTDONE_RingEnable_start 0 #define GFX11_BCS_INSTDONE_RingEnable_start 0 #define GFX9_BCS_INSTDONE_RingEnable_start 0 #define GFX8_BCS_INSTDONE_RingEnable_start 0 #define GFX75_BCS_INSTDONE_RingEnable_start 0 #define GFX7_BCS_INSTDONE_RingEnable_start 0 #define GFX6_BCS_INSTDONE_RingEnable_start 0 static inline uint32_t ATTRIBUTE_PURE BCS_INSTDONE_RingEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* BCS_RING_BUFFER_CTL */ #define GFX9_BCS_RING_BUFFER_CTL_length 1 #define GFX8_BCS_RING_BUFFER_CTL_length 1 #define GFX75_BCS_RING_BUFFER_CTL_length 1 #define GFX7_BCS_RING_BUFFER_CTL_length 1 #define GFX6_BCS_RING_BUFFER_CTL_length 1 static inline uint32_t ATTRIBUTE_PURE BCS_RING_BUFFER_CTL_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* BCS_RING_BUFFER_CTL::Automatic Report Head Pointer */ #define GFX9_BCS_RING_BUFFER_CTL_AutomaticReportHeadPointer_bits 2 #define GFX8_BCS_RING_BUFFER_CTL_AutomaticReportHeadPointer_bits 2 #define GFX75_BCS_RING_BUFFER_CTL_AutomaticReportHeadPointer_bits 2 #define GFX7_BCS_RING_BUFFER_CTL_AutomaticReportHeadPointer_bits 2 #define GFX6_BCS_RING_BUFFER_CTL_AutomaticReportHeadPointer_bits 2 static inline uint32_t ATTRIBUTE_PURE BCS_RING_BUFFER_CTL_AutomaticReportHeadPointer_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_BCS_RING_BUFFER_CTL_AutomaticReportHeadPointer_start 1 #define GFX8_BCS_RING_BUFFER_CTL_AutomaticReportHeadPointer_start 1 #define GFX75_BCS_RING_BUFFER_CTL_AutomaticReportHeadPointer_start 1 #define GFX7_BCS_RING_BUFFER_CTL_AutomaticReportHeadPointer_start 1 #define GFX6_BCS_RING_BUFFER_CTL_AutomaticReportHeadPointer_start 1 static inline uint32_t ATTRIBUTE_PURE BCS_RING_BUFFER_CTL_AutomaticReportHeadPointer_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* BCS_RING_BUFFER_CTL::Buffer Length (in pages - 1) */ #define GFX9_BCS_RING_BUFFER_CTL_BufferLengthinpages1_bits 9 #define GFX8_BCS_RING_BUFFER_CTL_BufferLengthinpages1_bits 9 #define GFX75_BCS_RING_BUFFER_CTL_BufferLengthinpages1_bits 9 #define GFX7_BCS_RING_BUFFER_CTL_BufferLengthinpages1_bits 9 #define GFX6_BCS_RING_BUFFER_CTL_BufferLengthinpages1_bits 9 static inline uint32_t ATTRIBUTE_PURE BCS_RING_BUFFER_CTL_BufferLengthinpages1_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 9; case 80: return 9; case 75: return 9; case 70: return 9; case 60: return 9; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_BCS_RING_BUFFER_CTL_BufferLengthinpages1_start 12 #define GFX8_BCS_RING_BUFFER_CTL_BufferLengthinpages1_start 12 #define GFX75_BCS_RING_BUFFER_CTL_BufferLengthinpages1_start 12 #define GFX7_BCS_RING_BUFFER_CTL_BufferLengthinpages1_start 12 #define GFX6_BCS_RING_BUFFER_CTL_BufferLengthinpages1_start 12 static inline uint32_t ATTRIBUTE_PURE BCS_RING_BUFFER_CTL_BufferLengthinpages1_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 12; case 80: return 12; case 75: return 12; case 70: return 12; case 60: return 12; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* BCS_RING_BUFFER_CTL::Disable Register Accesses */ #define GFX9_BCS_RING_BUFFER_CTL_DisableRegisterAccesses_bits 1 #define GFX8_BCS_RING_BUFFER_CTL_DisableRegisterAccesses_bits 1 #define GFX75_BCS_RING_BUFFER_CTL_DisableRegisterAccesses_bits 1 #define GFX7_BCS_RING_BUFFER_CTL_DisableRegisterAccesses_bits 1 #define GFX6_BCS_RING_BUFFER_CTL_DisableRegisterAccesses_bits 1 static inline uint32_t ATTRIBUTE_PURE BCS_RING_BUFFER_CTL_DisableRegisterAccesses_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_BCS_RING_BUFFER_CTL_DisableRegisterAccesses_start 8 #define GFX8_BCS_RING_BUFFER_CTL_DisableRegisterAccesses_start 8 #define GFX75_BCS_RING_BUFFER_CTL_DisableRegisterAccesses_start 8 #define GFX7_BCS_RING_BUFFER_CTL_DisableRegisterAccesses_start 8 #define GFX6_BCS_RING_BUFFER_CTL_DisableRegisterAccesses_start 8 static inline uint32_t ATTRIBUTE_PURE BCS_RING_BUFFER_CTL_DisableRegisterAccesses_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* BCS_RING_BUFFER_CTL::RBWait */ #define GFX9_BCS_RING_BUFFER_CTL_RBWait_bits 1 #define GFX8_BCS_RING_BUFFER_CTL_RBWait_bits 1 #define GFX75_BCS_RING_BUFFER_CTL_RBWait_bits 1 #define GFX7_BCS_RING_BUFFER_CTL_RBWait_bits 1 #define GFX6_BCS_RING_BUFFER_CTL_RBWait_bits 1 static inline uint32_t ATTRIBUTE_PURE BCS_RING_BUFFER_CTL_RBWait_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_BCS_RING_BUFFER_CTL_RBWait_start 11 #define GFX8_BCS_RING_BUFFER_CTL_RBWait_start 11 #define GFX75_BCS_RING_BUFFER_CTL_RBWait_start 11 #define GFX7_BCS_RING_BUFFER_CTL_RBWait_start 11 #define GFX6_BCS_RING_BUFFER_CTL_RBWait_start 11 static inline uint32_t ATTRIBUTE_PURE BCS_RING_BUFFER_CTL_RBWait_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 11; case 80: return 11; case 75: return 11; case 70: return 11; case 60: return 11; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* BCS_RING_BUFFER_CTL::Ring Buffer Enable */ #define GFX9_BCS_RING_BUFFER_CTL_RingBufferEnable_bits 1 #define GFX8_BCS_RING_BUFFER_CTL_RingBufferEnable_bits 1 #define GFX75_BCS_RING_BUFFER_CTL_RingBufferEnable_bits 1 #define GFX7_BCS_RING_BUFFER_CTL_RingBufferEnable_bits 1 #define GFX6_BCS_RING_BUFFER_CTL_RingBufferEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE BCS_RING_BUFFER_CTL_RingBufferEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_BCS_RING_BUFFER_CTL_RingBufferEnable_start 0 #define GFX8_BCS_RING_BUFFER_CTL_RingBufferEnable_start 0 #define GFX75_BCS_RING_BUFFER_CTL_RingBufferEnable_start 0 #define GFX7_BCS_RING_BUFFER_CTL_RingBufferEnable_start 0 #define GFX6_BCS_RING_BUFFER_CTL_RingBufferEnable_start 0 static inline uint32_t ATTRIBUTE_PURE BCS_RING_BUFFER_CTL_RingBufferEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* BCS_RING_BUFFER_CTL::Semaphore Wait */ #define GFX9_BCS_RING_BUFFER_CTL_SemaphoreWait_bits 1 #define GFX8_BCS_RING_BUFFER_CTL_SemaphoreWait_bits 1 #define GFX75_BCS_RING_BUFFER_CTL_SemaphoreWait_bits 1 #define GFX7_BCS_RING_BUFFER_CTL_SemaphoreWait_bits 1 #define GFX6_BCS_RING_BUFFER_CTL_SemaphoreWait_bits 1 static inline uint32_t ATTRIBUTE_PURE BCS_RING_BUFFER_CTL_SemaphoreWait_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_BCS_RING_BUFFER_CTL_SemaphoreWait_start 10 #define GFX8_BCS_RING_BUFFER_CTL_SemaphoreWait_start 10 #define GFX75_BCS_RING_BUFFER_CTL_SemaphoreWait_start 10 #define GFX7_BCS_RING_BUFFER_CTL_SemaphoreWait_start 10 #define GFX6_BCS_RING_BUFFER_CTL_SemaphoreWait_start 10 static inline uint32_t ATTRIBUTE_PURE BCS_RING_BUFFER_CTL_SemaphoreWait_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 10; case 80: return 10; case 75: return 10; case 70: return 10; case 60: return 10; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* BINDING_TABLE_EDIT_ENTRY */ #define GFX125_BINDING_TABLE_EDIT_ENTRY_length 1 #define GFX12_BINDING_TABLE_EDIT_ENTRY_length 1 #define GFX11_BINDING_TABLE_EDIT_ENTRY_length 1 #define GFX9_BINDING_TABLE_EDIT_ENTRY_length 1 #define GFX8_BINDING_TABLE_EDIT_ENTRY_length 1 #define GFX75_BINDING_TABLE_EDIT_ENTRY_length 1 static inline uint32_t ATTRIBUTE_PURE BINDING_TABLE_EDIT_ENTRY_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* BINDING_TABLE_EDIT_ENTRY::Binding Table Index */ #define GFX125_BINDING_TABLE_EDIT_ENTRY_BindingTableIndex_bits 8 #define GFX12_BINDING_TABLE_EDIT_ENTRY_BindingTableIndex_bits 8 #define GFX11_BINDING_TABLE_EDIT_ENTRY_BindingTableIndex_bits 8 #define GFX9_BINDING_TABLE_EDIT_ENTRY_BindingTableIndex_bits 8 #define GFX8_BINDING_TABLE_EDIT_ENTRY_BindingTableIndex_bits 8 #define GFX75_BINDING_TABLE_EDIT_ENTRY_BindingTableIndex_bits 8 static inline uint32_t ATTRIBUTE_PURE BINDING_TABLE_EDIT_ENTRY_BindingTableIndex_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_BINDING_TABLE_EDIT_ENTRY_BindingTableIndex_start 16 #define GFX12_BINDING_TABLE_EDIT_ENTRY_BindingTableIndex_start 16 #define GFX11_BINDING_TABLE_EDIT_ENTRY_BindingTableIndex_start 16 #define GFX9_BINDING_TABLE_EDIT_ENTRY_BindingTableIndex_start 16 #define GFX8_BINDING_TABLE_EDIT_ENTRY_BindingTableIndex_start 16 #define GFX75_BINDING_TABLE_EDIT_ENTRY_BindingTableIndex_start 16 static inline uint32_t ATTRIBUTE_PURE BINDING_TABLE_EDIT_ENTRY_BindingTableIndex_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* BINDING_TABLE_EDIT_ENTRY::Surface State Pointer */ #define GFX125_BINDING_TABLE_EDIT_ENTRY_SurfaceStatePointer_bits 16 #define GFX12_BINDING_TABLE_EDIT_ENTRY_SurfaceStatePointer_bits 16 #define GFX11_BINDING_TABLE_EDIT_ENTRY_SurfaceStatePointer_bits 16 #define GFX9_BINDING_TABLE_EDIT_ENTRY_SurfaceStatePointer_bits 16 #define GFX8_BINDING_TABLE_EDIT_ENTRY_SurfaceStatePointer_bits 16 #define GFX75_BINDING_TABLE_EDIT_ENTRY_SurfaceStatePointer_bits 16 static inline uint32_t ATTRIBUTE_PURE BINDING_TABLE_EDIT_ENTRY_SurfaceStatePointer_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_BINDING_TABLE_EDIT_ENTRY_SurfaceStatePointer_start 0 #define GFX12_BINDING_TABLE_EDIT_ENTRY_SurfaceStatePointer_start 0 #define GFX11_BINDING_TABLE_EDIT_ENTRY_SurfaceStatePointer_start 0 #define GFX9_BINDING_TABLE_EDIT_ENTRY_SurfaceStatePointer_start 0 #define GFX8_BINDING_TABLE_EDIT_ENTRY_SurfaceStatePointer_start 0 #define GFX75_BINDING_TABLE_EDIT_ENTRY_SurfaceStatePointer_start 0 static inline uint32_t ATTRIBUTE_PURE BINDING_TABLE_EDIT_ENTRY_SurfaceStatePointer_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* BINDING_TABLE_STATE */ #define GFX125_BINDING_TABLE_STATE_length 1 #define GFX12_BINDING_TABLE_STATE_length 1 #define GFX11_BINDING_TABLE_STATE_length 1 #define GFX9_BINDING_TABLE_STATE_length 1 #define GFX8_BINDING_TABLE_STATE_length 1 #define GFX75_BINDING_TABLE_STATE_length 1 #define GFX7_BINDING_TABLE_STATE_length 1 #define GFX6_BINDING_TABLE_STATE_length 1 static inline uint32_t ATTRIBUTE_PURE BINDING_TABLE_STATE_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* BINDING_TABLE_STATE::Surface State Pointer */ #define GFX125_BINDING_TABLE_STATE_SurfaceStatePointer_bits 26 #define GFX12_BINDING_TABLE_STATE_SurfaceStatePointer_bits 26 #define GFX11_BINDING_TABLE_STATE_SurfaceStatePointer_bits 26 #define GFX9_BINDING_TABLE_STATE_SurfaceStatePointer_bits 26 #define GFX8_BINDING_TABLE_STATE_SurfaceStatePointer_bits 26 #define GFX75_BINDING_TABLE_STATE_SurfaceStatePointer_bits 27 #define GFX7_BINDING_TABLE_STATE_SurfaceStatePointer_bits 27 #define GFX6_BINDING_TABLE_STATE_SurfaceStatePointer_bits 27 static inline uint32_t ATTRIBUTE_PURE BINDING_TABLE_STATE_SurfaceStatePointer_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 26; case 120: return 26; case 110: return 26; case 90: return 26; case 80: return 26; case 75: return 27; case 70: return 27; case 60: return 27; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_BINDING_TABLE_STATE_SurfaceStatePointer_start 6 #define GFX12_BINDING_TABLE_STATE_SurfaceStatePointer_start 6 #define GFX11_BINDING_TABLE_STATE_SurfaceStatePointer_start 6 #define GFX9_BINDING_TABLE_STATE_SurfaceStatePointer_start 6 #define GFX8_BINDING_TABLE_STATE_SurfaceStatePointer_start 6 #define GFX75_BINDING_TABLE_STATE_SurfaceStatePointer_start 5 #define GFX7_BINDING_TABLE_STATE_SurfaceStatePointer_start 5 #define GFX6_BINDING_TABLE_STATE_SurfaceStatePointer_start 5 static inline uint32_t ATTRIBUTE_PURE BINDING_TABLE_STATE_SurfaceStatePointer_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 5; case 70: return 5; case 60: return 5; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* BLEND_STATE */ #define GFX125_BLEND_STATE_length 1 #define GFX12_BLEND_STATE_length 1 #define GFX11_BLEND_STATE_length 1 #define GFX9_BLEND_STATE_length 1 #define GFX8_BLEND_STATE_length 1 #define GFX75_BLEND_STATE_length 0 #define GFX7_BLEND_STATE_length 0 #define GFX6_BLEND_STATE_length 0 static inline uint32_t ATTRIBUTE_PURE BLEND_STATE_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* BLEND_STATE::Alpha Test Enable */ #define GFX125_BLEND_STATE_AlphaTestEnable_bits 1 #define GFX12_BLEND_STATE_AlphaTestEnable_bits 1 #define GFX11_BLEND_STATE_AlphaTestEnable_bits 1 #define GFX9_BLEND_STATE_AlphaTestEnable_bits 1 #define GFX8_BLEND_STATE_AlphaTestEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE BLEND_STATE_AlphaTestEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_BLEND_STATE_AlphaTestEnable_start 27 #define GFX12_BLEND_STATE_AlphaTestEnable_start 27 #define GFX11_BLEND_STATE_AlphaTestEnable_start 27 #define GFX9_BLEND_STATE_AlphaTestEnable_start 27 #define GFX8_BLEND_STATE_AlphaTestEnable_start 27 static inline uint32_t ATTRIBUTE_PURE BLEND_STATE_AlphaTestEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* BLEND_STATE::Alpha Test Function */ #define GFX125_BLEND_STATE_AlphaTestFunction_bits 3 #define GFX12_BLEND_STATE_AlphaTestFunction_bits 3 #define GFX11_BLEND_STATE_AlphaTestFunction_bits 3 #define GFX9_BLEND_STATE_AlphaTestFunction_bits 3 #define GFX8_BLEND_STATE_AlphaTestFunction_bits 3 static inline uint32_t ATTRIBUTE_PURE BLEND_STATE_AlphaTestFunction_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_BLEND_STATE_AlphaTestFunction_start 24 #define GFX12_BLEND_STATE_AlphaTestFunction_start 24 #define GFX11_BLEND_STATE_AlphaTestFunction_start 24 #define GFX9_BLEND_STATE_AlphaTestFunction_start 24 #define GFX8_BLEND_STATE_AlphaTestFunction_start 24 static inline uint32_t ATTRIBUTE_PURE BLEND_STATE_AlphaTestFunction_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* BLEND_STATE::Alpha To Coverage Dither Enable */ #define GFX125_BLEND_STATE_AlphaToCoverageDitherEnable_bits 1 #define GFX12_BLEND_STATE_AlphaToCoverageDitherEnable_bits 1 #define GFX11_BLEND_STATE_AlphaToCoverageDitherEnable_bits 1 #define GFX9_BLEND_STATE_AlphaToCoverageDitherEnable_bits 1 #define GFX8_BLEND_STATE_AlphaToCoverageDitherEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE BLEND_STATE_AlphaToCoverageDitherEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_BLEND_STATE_AlphaToCoverageDitherEnable_start 28 #define GFX12_BLEND_STATE_AlphaToCoverageDitherEnable_start 28 #define GFX11_BLEND_STATE_AlphaToCoverageDitherEnable_start 28 #define GFX9_BLEND_STATE_AlphaToCoverageDitherEnable_start 28 #define GFX8_BLEND_STATE_AlphaToCoverageDitherEnable_start 28 static inline uint32_t ATTRIBUTE_PURE BLEND_STATE_AlphaToCoverageDitherEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 28; case 120: return 28; case 110: return 28; case 90: return 28; case 80: return 28; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* BLEND_STATE::Alpha To Coverage Enable */ #define GFX125_BLEND_STATE_AlphaToCoverageEnable_bits 1 #define GFX12_BLEND_STATE_AlphaToCoverageEnable_bits 1 #define GFX11_BLEND_STATE_AlphaToCoverageEnable_bits 1 #define GFX9_BLEND_STATE_AlphaToCoverageEnable_bits 1 #define GFX8_BLEND_STATE_AlphaToCoverageEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE BLEND_STATE_AlphaToCoverageEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_BLEND_STATE_AlphaToCoverageEnable_start 31 #define GFX12_BLEND_STATE_AlphaToCoverageEnable_start 31 #define GFX11_BLEND_STATE_AlphaToCoverageEnable_start 31 #define GFX9_BLEND_STATE_AlphaToCoverageEnable_start 31 #define GFX8_BLEND_STATE_AlphaToCoverageEnable_start 31 static inline uint32_t ATTRIBUTE_PURE BLEND_STATE_AlphaToCoverageEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 31; case 120: return 31; case 110: return 31; case 90: return 31; case 80: return 31; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* BLEND_STATE::Alpha To One Enable */ #define GFX125_BLEND_STATE_AlphaToOneEnable_bits 1 #define GFX12_BLEND_STATE_AlphaToOneEnable_bits 1 #define GFX11_BLEND_STATE_AlphaToOneEnable_bits 1 #define GFX9_BLEND_STATE_AlphaToOneEnable_bits 1 #define GFX8_BLEND_STATE_AlphaToOneEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE BLEND_STATE_AlphaToOneEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_BLEND_STATE_AlphaToOneEnable_start 29 #define GFX12_BLEND_STATE_AlphaToOneEnable_start 29 #define GFX11_BLEND_STATE_AlphaToOneEnable_start 29 #define GFX9_BLEND_STATE_AlphaToOneEnable_start 29 #define GFX8_BLEND_STATE_AlphaToOneEnable_start 29 static inline uint32_t ATTRIBUTE_PURE BLEND_STATE_AlphaToOneEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* BLEND_STATE::Color Dither Enable */ #define GFX125_BLEND_STATE_ColorDitherEnable_bits 1 #define GFX12_BLEND_STATE_ColorDitherEnable_bits 1 #define GFX11_BLEND_STATE_ColorDitherEnable_bits 1 #define GFX9_BLEND_STATE_ColorDitherEnable_bits 1 #define GFX8_BLEND_STATE_ColorDitherEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE BLEND_STATE_ColorDitherEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_BLEND_STATE_ColorDitherEnable_start 23 #define GFX12_BLEND_STATE_ColorDitherEnable_start 23 #define GFX11_BLEND_STATE_ColorDitherEnable_start 23 #define GFX9_BLEND_STATE_ColorDitherEnable_start 23 #define GFX8_BLEND_STATE_ColorDitherEnable_start 23 static inline uint32_t ATTRIBUTE_PURE BLEND_STATE_ColorDitherEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 23; case 120: return 23; case 110: return 23; case 90: return 23; case 80: return 23; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* BLEND_STATE::Independent Alpha Blend Enable */ #define GFX125_BLEND_STATE_IndependentAlphaBlendEnable_bits 1 #define GFX12_BLEND_STATE_IndependentAlphaBlendEnable_bits 1 #define GFX11_BLEND_STATE_IndependentAlphaBlendEnable_bits 1 #define GFX9_BLEND_STATE_IndependentAlphaBlendEnable_bits 1 #define GFX8_BLEND_STATE_IndependentAlphaBlendEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE BLEND_STATE_IndependentAlphaBlendEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_BLEND_STATE_IndependentAlphaBlendEnable_start 30 #define GFX12_BLEND_STATE_IndependentAlphaBlendEnable_start 30 #define GFX11_BLEND_STATE_IndependentAlphaBlendEnable_start 30 #define GFX9_BLEND_STATE_IndependentAlphaBlendEnable_start 30 #define GFX8_BLEND_STATE_IndependentAlphaBlendEnable_start 30 static inline uint32_t ATTRIBUTE_PURE BLEND_STATE_IndependentAlphaBlendEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 30; case 120: return 30; case 110: return 30; case 90: return 30; case 80: return 30; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* BLEND_STATE::X Dither Offset */ #define GFX125_BLEND_STATE_XDitherOffset_bits 2 #define GFX12_BLEND_STATE_XDitherOffset_bits 2 #define GFX11_BLEND_STATE_XDitherOffset_bits 2 #define GFX9_BLEND_STATE_XDitherOffset_bits 2 #define GFX8_BLEND_STATE_XDitherOffset_bits 2 static inline uint32_t ATTRIBUTE_PURE BLEND_STATE_XDitherOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_BLEND_STATE_XDitherOffset_start 21 #define GFX12_BLEND_STATE_XDitherOffset_start 21 #define GFX11_BLEND_STATE_XDitherOffset_start 21 #define GFX9_BLEND_STATE_XDitherOffset_start 21 #define GFX8_BLEND_STATE_XDitherOffset_start 21 static inline uint32_t ATTRIBUTE_PURE BLEND_STATE_XDitherOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 21; case 120: return 21; case 110: return 21; case 90: return 21; case 80: return 21; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* BLEND_STATE::Y Dither Offset */ #define GFX125_BLEND_STATE_YDitherOffset_bits 2 #define GFX12_BLEND_STATE_YDitherOffset_bits 2 #define GFX11_BLEND_STATE_YDitherOffset_bits 2 #define GFX9_BLEND_STATE_YDitherOffset_bits 2 #define GFX8_BLEND_STATE_YDitherOffset_bits 2 static inline uint32_t ATTRIBUTE_PURE BLEND_STATE_YDitherOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_BLEND_STATE_YDitherOffset_start 19 #define GFX12_BLEND_STATE_YDitherOffset_start 19 #define GFX11_BLEND_STATE_YDitherOffset_start 19 #define GFX9_BLEND_STATE_YDitherOffset_start 19 #define GFX8_BLEND_STATE_YDitherOffset_start 19 static inline uint32_t ATTRIBUTE_PURE BLEND_STATE_YDitherOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 19; case 120: return 19; case 110: return 19; case 90: return 19; case 80: return 19; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* BLEND_STATE_ENTRY */ #define GFX125_BLEND_STATE_ENTRY_length 2 #define GFX12_BLEND_STATE_ENTRY_length 2 #define GFX11_BLEND_STATE_ENTRY_length 2 #define GFX9_BLEND_STATE_ENTRY_length 2 #define GFX8_BLEND_STATE_ENTRY_length 2 #define GFX75_BLEND_STATE_ENTRY_length 2 #define GFX7_BLEND_STATE_ENTRY_length 2 #define GFX6_BLEND_STATE_ENTRY_length 2 static inline uint32_t ATTRIBUTE_PURE BLEND_STATE_ENTRY_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* BLEND_STATE_ENTRY::Alpha Blend Function */ #define GFX125_BLEND_STATE_ENTRY_AlphaBlendFunction_bits 3 #define GFX12_BLEND_STATE_ENTRY_AlphaBlendFunction_bits 3 #define GFX11_BLEND_STATE_ENTRY_AlphaBlendFunction_bits 3 #define GFX9_BLEND_STATE_ENTRY_AlphaBlendFunction_bits 3 #define GFX8_BLEND_STATE_ENTRY_AlphaBlendFunction_bits 3 #define GFX75_BLEND_STATE_ENTRY_AlphaBlendFunction_bits 3 #define GFX7_BLEND_STATE_ENTRY_AlphaBlendFunction_bits 3 #define GFX6_BLEND_STATE_ENTRY_AlphaBlendFunction_bits 3 static inline uint32_t ATTRIBUTE_PURE BLEND_STATE_ENTRY_AlphaBlendFunction_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_BLEND_STATE_ENTRY_AlphaBlendFunction_start 5 #define GFX12_BLEND_STATE_ENTRY_AlphaBlendFunction_start 5 #define GFX11_BLEND_STATE_ENTRY_AlphaBlendFunction_start 5 #define GFX9_BLEND_STATE_ENTRY_AlphaBlendFunction_start 5 #define GFX8_BLEND_STATE_ENTRY_AlphaBlendFunction_start 5 #define GFX75_BLEND_STATE_ENTRY_AlphaBlendFunction_start 26 #define GFX7_BLEND_STATE_ENTRY_AlphaBlendFunction_start 26 #define GFX6_BLEND_STATE_ENTRY_AlphaBlendFunction_start 26 static inline uint32_t ATTRIBUTE_PURE BLEND_STATE_ENTRY_AlphaBlendFunction_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 5; case 110: return 5; case 90: return 5; case 80: return 5; case 75: return 26; case 70: return 26; case 60: return 26; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* BLEND_STATE_ENTRY::Alpha Test Enable */ #define GFX75_BLEND_STATE_ENTRY_AlphaTestEnable_bits 1 #define GFX7_BLEND_STATE_ENTRY_AlphaTestEnable_bits 1 #define GFX6_BLEND_STATE_ENTRY_AlphaTestEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE BLEND_STATE_ENTRY_AlphaTestEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_BLEND_STATE_ENTRY_AlphaTestEnable_start 48 #define GFX7_BLEND_STATE_ENTRY_AlphaTestEnable_start 48 #define GFX6_BLEND_STATE_ENTRY_AlphaTestEnable_start 48 static inline uint32_t ATTRIBUTE_PURE BLEND_STATE_ENTRY_AlphaTestEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 48; case 70: return 48; case 60: return 48; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* BLEND_STATE_ENTRY::Alpha Test Function */ #define GFX75_BLEND_STATE_ENTRY_AlphaTestFunction_bits 3 #define GFX7_BLEND_STATE_ENTRY_AlphaTestFunction_bits 3 #define GFX6_BLEND_STATE_ENTRY_AlphaTestFunction_bits 3 static inline uint32_t ATTRIBUTE_PURE BLEND_STATE_ENTRY_AlphaTestFunction_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_BLEND_STATE_ENTRY_AlphaTestFunction_start 45 #define GFX7_BLEND_STATE_ENTRY_AlphaTestFunction_start 45 #define GFX6_BLEND_STATE_ENTRY_AlphaTestFunction_start 45 static inline uint32_t ATTRIBUTE_PURE BLEND_STATE_ENTRY_AlphaTestFunction_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 45; case 70: return 45; case 60: return 45; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* BLEND_STATE_ENTRY::AlphaToCoverage Dither Enable */ #define GFX75_BLEND_STATE_ENTRY_AlphaToCoverageDitherEnable_bits 1 #define GFX7_BLEND_STATE_ENTRY_AlphaToCoverageDitherEnable_bits 1 #define GFX6_BLEND_STATE_ENTRY_AlphaToCoverageDitherEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE BLEND_STATE_ENTRY_AlphaToCoverageDitherEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_BLEND_STATE_ENTRY_AlphaToCoverageDitherEnable_start 61 #define GFX7_BLEND_STATE_ENTRY_AlphaToCoverageDitherEnable_start 61 #define GFX6_BLEND_STATE_ENTRY_AlphaToCoverageDitherEnable_start 61 static inline uint32_t ATTRIBUTE_PURE BLEND_STATE_ENTRY_AlphaToCoverageDitherEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 61; case 70: return 61; case 60: return 61; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* BLEND_STATE_ENTRY::AlphaToCoverage Enable */ #define GFX75_BLEND_STATE_ENTRY_AlphaToCoverageEnable_bits 1 #define GFX7_BLEND_STATE_ENTRY_AlphaToCoverageEnable_bits 1 #define GFX6_BLEND_STATE_ENTRY_AlphaToCoverageEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE BLEND_STATE_ENTRY_AlphaToCoverageEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_BLEND_STATE_ENTRY_AlphaToCoverageEnable_start 63 #define GFX7_BLEND_STATE_ENTRY_AlphaToCoverageEnable_start 63 #define GFX6_BLEND_STATE_ENTRY_AlphaToCoverageEnable_start 63 static inline uint32_t ATTRIBUTE_PURE BLEND_STATE_ENTRY_AlphaToCoverageEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 63; case 70: return 63; case 60: return 63; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* BLEND_STATE_ENTRY::AlphaToOne Enable */ #define GFX75_BLEND_STATE_ENTRY_AlphaToOneEnable_bits 1 #define GFX7_BLEND_STATE_ENTRY_AlphaToOneEnable_bits 1 #define GFX6_BLEND_STATE_ENTRY_AlphaToOneEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE BLEND_STATE_ENTRY_AlphaToOneEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_BLEND_STATE_ENTRY_AlphaToOneEnable_start 62 #define GFX7_BLEND_STATE_ENTRY_AlphaToOneEnable_start 62 #define GFX6_BLEND_STATE_ENTRY_AlphaToOneEnable_start 62 static inline uint32_t ATTRIBUTE_PURE BLEND_STATE_ENTRY_AlphaToOneEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 62; case 70: return 62; case 60: return 62; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* BLEND_STATE_ENTRY::Color Blend Function */ #define GFX125_BLEND_STATE_ENTRY_ColorBlendFunction_bits 3 #define GFX12_BLEND_STATE_ENTRY_ColorBlendFunction_bits 3 #define GFX11_BLEND_STATE_ENTRY_ColorBlendFunction_bits 3 #define GFX9_BLEND_STATE_ENTRY_ColorBlendFunction_bits 3 #define GFX8_BLEND_STATE_ENTRY_ColorBlendFunction_bits 3 #define GFX75_BLEND_STATE_ENTRY_ColorBlendFunction_bits 3 #define GFX7_BLEND_STATE_ENTRY_ColorBlendFunction_bits 3 #define GFX6_BLEND_STATE_ENTRY_ColorBlendFunction_bits 3 static inline uint32_t ATTRIBUTE_PURE BLEND_STATE_ENTRY_ColorBlendFunction_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_BLEND_STATE_ENTRY_ColorBlendFunction_start 18 #define GFX12_BLEND_STATE_ENTRY_ColorBlendFunction_start 18 #define GFX11_BLEND_STATE_ENTRY_ColorBlendFunction_start 18 #define GFX9_BLEND_STATE_ENTRY_ColorBlendFunction_start 18 #define GFX8_BLEND_STATE_ENTRY_ColorBlendFunction_start 18 #define GFX75_BLEND_STATE_ENTRY_ColorBlendFunction_start 11 #define GFX7_BLEND_STATE_ENTRY_ColorBlendFunction_start 11 #define GFX6_BLEND_STATE_ENTRY_ColorBlendFunction_start 11 static inline uint32_t ATTRIBUTE_PURE BLEND_STATE_ENTRY_ColorBlendFunction_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 18; case 120: return 18; case 110: return 18; case 90: return 18; case 80: return 18; case 75: return 11; case 70: return 11; case 60: return 11; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* BLEND_STATE_ENTRY::Color Buffer Blend Enable */ #define GFX125_BLEND_STATE_ENTRY_ColorBufferBlendEnable_bits 1 #define GFX12_BLEND_STATE_ENTRY_ColorBufferBlendEnable_bits 1 #define GFX11_BLEND_STATE_ENTRY_ColorBufferBlendEnable_bits 1 #define GFX9_BLEND_STATE_ENTRY_ColorBufferBlendEnable_bits 1 #define GFX8_BLEND_STATE_ENTRY_ColorBufferBlendEnable_bits 1 #define GFX75_BLEND_STATE_ENTRY_ColorBufferBlendEnable_bits 1 #define GFX7_BLEND_STATE_ENTRY_ColorBufferBlendEnable_bits 1 #define GFX6_BLEND_STATE_ENTRY_ColorBufferBlendEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE BLEND_STATE_ENTRY_ColorBufferBlendEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_BLEND_STATE_ENTRY_ColorBufferBlendEnable_start 31 #define GFX12_BLEND_STATE_ENTRY_ColorBufferBlendEnable_start 31 #define GFX11_BLEND_STATE_ENTRY_ColorBufferBlendEnable_start 31 #define GFX9_BLEND_STATE_ENTRY_ColorBufferBlendEnable_start 31 #define GFX8_BLEND_STATE_ENTRY_ColorBufferBlendEnable_start 31 #define GFX75_BLEND_STATE_ENTRY_ColorBufferBlendEnable_start 31 #define GFX7_BLEND_STATE_ENTRY_ColorBufferBlendEnable_start 31 #define GFX6_BLEND_STATE_ENTRY_ColorBufferBlendEnable_start 31 static inline uint32_t ATTRIBUTE_PURE BLEND_STATE_ENTRY_ColorBufferBlendEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 31; case 120: return 31; case 110: return 31; case 90: return 31; case 80: return 31; case 75: return 31; case 70: return 31; case 60: return 31; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* BLEND_STATE_ENTRY::Color Clamp Range */ #define GFX125_BLEND_STATE_ENTRY_ColorClampRange_bits 2 #define GFX12_BLEND_STATE_ENTRY_ColorClampRange_bits 2 #define GFX11_BLEND_STATE_ENTRY_ColorClampRange_bits 2 #define GFX9_BLEND_STATE_ENTRY_ColorClampRange_bits 2 #define GFX8_BLEND_STATE_ENTRY_ColorClampRange_bits 2 #define GFX75_BLEND_STATE_ENTRY_ColorClampRange_bits 2 #define GFX7_BLEND_STATE_ENTRY_ColorClampRange_bits 2 #define GFX6_BLEND_STATE_ENTRY_ColorClampRange_bits 2 static inline uint32_t ATTRIBUTE_PURE BLEND_STATE_ENTRY_ColorClampRange_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_BLEND_STATE_ENTRY_ColorClampRange_start 34 #define GFX12_BLEND_STATE_ENTRY_ColorClampRange_start 34 #define GFX11_BLEND_STATE_ENTRY_ColorClampRange_start 34 #define GFX9_BLEND_STATE_ENTRY_ColorClampRange_start 34 #define GFX8_BLEND_STATE_ENTRY_ColorClampRange_start 34 #define GFX75_BLEND_STATE_ENTRY_ColorClampRange_start 34 #define GFX7_BLEND_STATE_ENTRY_ColorClampRange_start 34 #define GFX6_BLEND_STATE_ENTRY_ColorClampRange_start 34 static inline uint32_t ATTRIBUTE_PURE BLEND_STATE_ENTRY_ColorClampRange_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 34; case 120: return 34; case 110: return 34; case 90: return 34; case 80: return 34; case 75: return 34; case 70: return 34; case 60: return 34; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* BLEND_STATE_ENTRY::Color Dither Enable */ #define GFX75_BLEND_STATE_ENTRY_ColorDitherEnable_bits 1 #define GFX7_BLEND_STATE_ENTRY_ColorDitherEnable_bits 1 #define GFX6_BLEND_STATE_ENTRY_ColorDitherEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE BLEND_STATE_ENTRY_ColorDitherEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_BLEND_STATE_ENTRY_ColorDitherEnable_start 44 #define GFX7_BLEND_STATE_ENTRY_ColorDitherEnable_start 44 #define GFX6_BLEND_STATE_ENTRY_ColorDitherEnable_start 44 static inline uint32_t ATTRIBUTE_PURE BLEND_STATE_ENTRY_ColorDitherEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 44; case 70: return 44; case 60: return 44; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* BLEND_STATE_ENTRY::Destination Alpha Blend Factor */ #define GFX125_BLEND_STATE_ENTRY_DestinationAlphaBlendFactor_bits 5 #define GFX12_BLEND_STATE_ENTRY_DestinationAlphaBlendFactor_bits 5 #define GFX11_BLEND_STATE_ENTRY_DestinationAlphaBlendFactor_bits 5 #define GFX9_BLEND_STATE_ENTRY_DestinationAlphaBlendFactor_bits 5 #define GFX8_BLEND_STATE_ENTRY_DestinationAlphaBlendFactor_bits 5 #define GFX75_BLEND_STATE_ENTRY_DestinationAlphaBlendFactor_bits 5 #define GFX7_BLEND_STATE_ENTRY_DestinationAlphaBlendFactor_bits 5 #define GFX6_BLEND_STATE_ENTRY_DestinationAlphaBlendFactor_bits 5 static inline uint32_t ATTRIBUTE_PURE BLEND_STATE_ENTRY_DestinationAlphaBlendFactor_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 5; case 110: return 5; case 90: return 5; case 80: return 5; case 75: return 5; case 70: return 5; case 60: return 5; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_BLEND_STATE_ENTRY_DestinationAlphaBlendFactor_start 8 #define GFX12_BLEND_STATE_ENTRY_DestinationAlphaBlendFactor_start 8 #define GFX11_BLEND_STATE_ENTRY_DestinationAlphaBlendFactor_start 8 #define GFX9_BLEND_STATE_ENTRY_DestinationAlphaBlendFactor_start 8 #define GFX8_BLEND_STATE_ENTRY_DestinationAlphaBlendFactor_start 8 #define GFX75_BLEND_STATE_ENTRY_DestinationAlphaBlendFactor_start 15 #define GFX7_BLEND_STATE_ENTRY_DestinationAlphaBlendFactor_start 15 #define GFX6_BLEND_STATE_ENTRY_DestinationAlphaBlendFactor_start 15 static inline uint32_t ATTRIBUTE_PURE BLEND_STATE_ENTRY_DestinationAlphaBlendFactor_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 15; case 70: return 15; case 60: return 15; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* BLEND_STATE_ENTRY::Destination Blend Factor */ #define GFX125_BLEND_STATE_ENTRY_DestinationBlendFactor_bits 5 #define GFX12_BLEND_STATE_ENTRY_DestinationBlendFactor_bits 5 #define GFX11_BLEND_STATE_ENTRY_DestinationBlendFactor_bits 5 #define GFX9_BLEND_STATE_ENTRY_DestinationBlendFactor_bits 5 #define GFX8_BLEND_STATE_ENTRY_DestinationBlendFactor_bits 5 #define GFX75_BLEND_STATE_ENTRY_DestinationBlendFactor_bits 5 #define GFX7_BLEND_STATE_ENTRY_DestinationBlendFactor_bits 5 #define GFX6_BLEND_STATE_ENTRY_DestinationBlendFactor_bits 5 static inline uint32_t ATTRIBUTE_PURE BLEND_STATE_ENTRY_DestinationBlendFactor_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 5; case 110: return 5; case 90: return 5; case 80: return 5; case 75: return 5; case 70: return 5; case 60: return 5; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_BLEND_STATE_ENTRY_DestinationBlendFactor_start 21 #define GFX12_BLEND_STATE_ENTRY_DestinationBlendFactor_start 21 #define GFX11_BLEND_STATE_ENTRY_DestinationBlendFactor_start 21 #define GFX9_BLEND_STATE_ENTRY_DestinationBlendFactor_start 21 #define GFX8_BLEND_STATE_ENTRY_DestinationBlendFactor_start 21 #define GFX75_BLEND_STATE_ENTRY_DestinationBlendFactor_start 0 #define GFX7_BLEND_STATE_ENTRY_DestinationBlendFactor_start 0 #define GFX6_BLEND_STATE_ENTRY_DestinationBlendFactor_start 0 static inline uint32_t ATTRIBUTE_PURE BLEND_STATE_ENTRY_DestinationBlendFactor_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 21; case 120: return 21; case 110: return 21; case 90: return 21; case 80: return 21; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* BLEND_STATE_ENTRY::Independent Alpha Blend Enable */ #define GFX75_BLEND_STATE_ENTRY_IndependentAlphaBlendEnable_bits 1 #define GFX7_BLEND_STATE_ENTRY_IndependentAlphaBlendEnable_bits 1 #define GFX6_BLEND_STATE_ENTRY_IndependentAlphaBlendEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE BLEND_STATE_ENTRY_IndependentAlphaBlendEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_BLEND_STATE_ENTRY_IndependentAlphaBlendEnable_start 30 #define GFX7_BLEND_STATE_ENTRY_IndependentAlphaBlendEnable_start 30 #define GFX6_BLEND_STATE_ENTRY_IndependentAlphaBlendEnable_start 30 static inline uint32_t ATTRIBUTE_PURE BLEND_STATE_ENTRY_IndependentAlphaBlendEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 30; case 70: return 30; case 60: return 30; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* BLEND_STATE_ENTRY::Logic Op Enable */ #define GFX125_BLEND_STATE_ENTRY_LogicOpEnable_bits 1 #define GFX12_BLEND_STATE_ENTRY_LogicOpEnable_bits 1 #define GFX11_BLEND_STATE_ENTRY_LogicOpEnable_bits 1 #define GFX9_BLEND_STATE_ENTRY_LogicOpEnable_bits 1 #define GFX8_BLEND_STATE_ENTRY_LogicOpEnable_bits 1 #define GFX75_BLEND_STATE_ENTRY_LogicOpEnable_bits 1 #define GFX7_BLEND_STATE_ENTRY_LogicOpEnable_bits 1 #define GFX6_BLEND_STATE_ENTRY_LogicOpEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE BLEND_STATE_ENTRY_LogicOpEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_BLEND_STATE_ENTRY_LogicOpEnable_start 63 #define GFX12_BLEND_STATE_ENTRY_LogicOpEnable_start 63 #define GFX11_BLEND_STATE_ENTRY_LogicOpEnable_start 63 #define GFX9_BLEND_STATE_ENTRY_LogicOpEnable_start 63 #define GFX8_BLEND_STATE_ENTRY_LogicOpEnable_start 63 #define GFX75_BLEND_STATE_ENTRY_LogicOpEnable_start 54 #define GFX7_BLEND_STATE_ENTRY_LogicOpEnable_start 54 #define GFX6_BLEND_STATE_ENTRY_LogicOpEnable_start 54 static inline uint32_t ATTRIBUTE_PURE BLEND_STATE_ENTRY_LogicOpEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 63; case 120: return 63; case 110: return 63; case 90: return 63; case 80: return 63; case 75: return 54; case 70: return 54; case 60: return 54; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* BLEND_STATE_ENTRY::Logic Op Function */ #define GFX125_BLEND_STATE_ENTRY_LogicOpFunction_bits 4 #define GFX12_BLEND_STATE_ENTRY_LogicOpFunction_bits 4 #define GFX11_BLEND_STATE_ENTRY_LogicOpFunction_bits 4 #define GFX9_BLEND_STATE_ENTRY_LogicOpFunction_bits 4 #define GFX8_BLEND_STATE_ENTRY_LogicOpFunction_bits 4 #define GFX75_BLEND_STATE_ENTRY_LogicOpFunction_bits 4 #define GFX7_BLEND_STATE_ENTRY_LogicOpFunction_bits 4 #define GFX6_BLEND_STATE_ENTRY_LogicOpFunction_bits 4 static inline uint32_t ATTRIBUTE_PURE BLEND_STATE_ENTRY_LogicOpFunction_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 4; case 70: return 4; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_BLEND_STATE_ENTRY_LogicOpFunction_start 59 #define GFX12_BLEND_STATE_ENTRY_LogicOpFunction_start 59 #define GFX11_BLEND_STATE_ENTRY_LogicOpFunction_start 59 #define GFX9_BLEND_STATE_ENTRY_LogicOpFunction_start 59 #define GFX8_BLEND_STATE_ENTRY_LogicOpFunction_start 59 #define GFX75_BLEND_STATE_ENTRY_LogicOpFunction_start 50 #define GFX7_BLEND_STATE_ENTRY_LogicOpFunction_start 50 #define GFX6_BLEND_STATE_ENTRY_LogicOpFunction_start 50 static inline uint32_t ATTRIBUTE_PURE BLEND_STATE_ENTRY_LogicOpFunction_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 59; case 120: return 59; case 110: return 59; case 90: return 59; case 80: return 59; case 75: return 50; case 70: return 50; case 60: return 50; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* BLEND_STATE_ENTRY::Post-Blend Color Clamp Enable */ #define GFX125_BLEND_STATE_ENTRY_PostBlendColorClampEnable_bits 1 #define GFX12_BLEND_STATE_ENTRY_PostBlendColorClampEnable_bits 1 #define GFX11_BLEND_STATE_ENTRY_PostBlendColorClampEnable_bits 1 #define GFX9_BLEND_STATE_ENTRY_PostBlendColorClampEnable_bits 1 #define GFX8_BLEND_STATE_ENTRY_PostBlendColorClampEnable_bits 1 #define GFX75_BLEND_STATE_ENTRY_PostBlendColorClampEnable_bits 1 #define GFX7_BLEND_STATE_ENTRY_PostBlendColorClampEnable_bits 1 #define GFX6_BLEND_STATE_ENTRY_PostBlendColorClampEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE BLEND_STATE_ENTRY_PostBlendColorClampEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_BLEND_STATE_ENTRY_PostBlendColorClampEnable_start 32 #define GFX12_BLEND_STATE_ENTRY_PostBlendColorClampEnable_start 32 #define GFX11_BLEND_STATE_ENTRY_PostBlendColorClampEnable_start 32 #define GFX9_BLEND_STATE_ENTRY_PostBlendColorClampEnable_start 32 #define GFX8_BLEND_STATE_ENTRY_PostBlendColorClampEnable_start 32 #define GFX75_BLEND_STATE_ENTRY_PostBlendColorClampEnable_start 32 #define GFX7_BLEND_STATE_ENTRY_PostBlendColorClampEnable_start 32 #define GFX6_BLEND_STATE_ENTRY_PostBlendColorClampEnable_start 32 static inline uint32_t ATTRIBUTE_PURE BLEND_STATE_ENTRY_PostBlendColorClampEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 32; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* BLEND_STATE_ENTRY::Pre-Blend Color Clamp Enable */ #define GFX125_BLEND_STATE_ENTRY_PreBlendColorClampEnable_bits 1 #define GFX12_BLEND_STATE_ENTRY_PreBlendColorClampEnable_bits 1 #define GFX11_BLEND_STATE_ENTRY_PreBlendColorClampEnable_bits 1 #define GFX9_BLEND_STATE_ENTRY_PreBlendColorClampEnable_bits 1 #define GFX8_BLEND_STATE_ENTRY_PreBlendColorClampEnable_bits 1 #define GFX75_BLEND_STATE_ENTRY_PreBlendColorClampEnable_bits 1 #define GFX7_BLEND_STATE_ENTRY_PreBlendColorClampEnable_bits 1 #define GFX6_BLEND_STATE_ENTRY_PreBlendColorClampEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE BLEND_STATE_ENTRY_PreBlendColorClampEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_BLEND_STATE_ENTRY_PreBlendColorClampEnable_start 33 #define GFX12_BLEND_STATE_ENTRY_PreBlendColorClampEnable_start 33 #define GFX11_BLEND_STATE_ENTRY_PreBlendColorClampEnable_start 33 #define GFX9_BLEND_STATE_ENTRY_PreBlendColorClampEnable_start 33 #define GFX8_BLEND_STATE_ENTRY_PreBlendColorClampEnable_start 33 #define GFX75_BLEND_STATE_ENTRY_PreBlendColorClampEnable_start 33 #define GFX7_BLEND_STATE_ENTRY_PreBlendColorClampEnable_start 33 #define GFX6_BLEND_STATE_ENTRY_PreBlendColorClampEnable_start 33 static inline uint32_t ATTRIBUTE_PURE BLEND_STATE_ENTRY_PreBlendColorClampEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 33; case 120: return 33; case 110: return 33; case 90: return 33; case 80: return 33; case 75: return 33; case 70: return 33; case 60: return 33; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* BLEND_STATE_ENTRY::Pre-Blend Source Only Clamp Enable */ #define GFX125_BLEND_STATE_ENTRY_PreBlendSourceOnlyClampEnable_bits 1 #define GFX12_BLEND_STATE_ENTRY_PreBlendSourceOnlyClampEnable_bits 1 #define GFX11_BLEND_STATE_ENTRY_PreBlendSourceOnlyClampEnable_bits 1 #define GFX9_BLEND_STATE_ENTRY_PreBlendSourceOnlyClampEnable_bits 1 #define GFX8_BLEND_STATE_ENTRY_PreBlendSourceOnlyClampEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE BLEND_STATE_ENTRY_PreBlendSourceOnlyClampEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_BLEND_STATE_ENTRY_PreBlendSourceOnlyClampEnable_start 36 #define GFX12_BLEND_STATE_ENTRY_PreBlendSourceOnlyClampEnable_start 36 #define GFX11_BLEND_STATE_ENTRY_PreBlendSourceOnlyClampEnable_start 36 #define GFX9_BLEND_STATE_ENTRY_PreBlendSourceOnlyClampEnable_start 36 #define GFX8_BLEND_STATE_ENTRY_PreBlendSourceOnlyClampEnable_start 36 static inline uint32_t ATTRIBUTE_PURE BLEND_STATE_ENTRY_PreBlendSourceOnlyClampEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 36; case 120: return 36; case 110: return 36; case 90: return 36; case 80: return 36; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* BLEND_STATE_ENTRY::Source Alpha Blend Factor */ #define GFX125_BLEND_STATE_ENTRY_SourceAlphaBlendFactor_bits 5 #define GFX12_BLEND_STATE_ENTRY_SourceAlphaBlendFactor_bits 5 #define GFX11_BLEND_STATE_ENTRY_SourceAlphaBlendFactor_bits 5 #define GFX9_BLEND_STATE_ENTRY_SourceAlphaBlendFactor_bits 5 #define GFX8_BLEND_STATE_ENTRY_SourceAlphaBlendFactor_bits 5 #define GFX75_BLEND_STATE_ENTRY_SourceAlphaBlendFactor_bits 5 #define GFX7_BLEND_STATE_ENTRY_SourceAlphaBlendFactor_bits 5 #define GFX6_BLEND_STATE_ENTRY_SourceAlphaBlendFactor_bits 5 static inline uint32_t ATTRIBUTE_PURE BLEND_STATE_ENTRY_SourceAlphaBlendFactor_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 5; case 110: return 5; case 90: return 5; case 80: return 5; case 75: return 5; case 70: return 5; case 60: return 5; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_BLEND_STATE_ENTRY_SourceAlphaBlendFactor_start 13 #define GFX12_BLEND_STATE_ENTRY_SourceAlphaBlendFactor_start 13 #define GFX11_BLEND_STATE_ENTRY_SourceAlphaBlendFactor_start 13 #define GFX9_BLEND_STATE_ENTRY_SourceAlphaBlendFactor_start 13 #define GFX8_BLEND_STATE_ENTRY_SourceAlphaBlendFactor_start 13 #define GFX75_BLEND_STATE_ENTRY_SourceAlphaBlendFactor_start 20 #define GFX7_BLEND_STATE_ENTRY_SourceAlphaBlendFactor_start 20 #define GFX6_BLEND_STATE_ENTRY_SourceAlphaBlendFactor_start 20 static inline uint32_t ATTRIBUTE_PURE BLEND_STATE_ENTRY_SourceAlphaBlendFactor_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 13; case 120: return 13; case 110: return 13; case 90: return 13; case 80: return 13; case 75: return 20; case 70: return 20; case 60: return 20; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* BLEND_STATE_ENTRY::Source Blend Factor */ #define GFX125_BLEND_STATE_ENTRY_SourceBlendFactor_bits 5 #define GFX12_BLEND_STATE_ENTRY_SourceBlendFactor_bits 5 #define GFX11_BLEND_STATE_ENTRY_SourceBlendFactor_bits 5 #define GFX9_BLEND_STATE_ENTRY_SourceBlendFactor_bits 5 #define GFX8_BLEND_STATE_ENTRY_SourceBlendFactor_bits 5 #define GFX75_BLEND_STATE_ENTRY_SourceBlendFactor_bits 5 #define GFX7_BLEND_STATE_ENTRY_SourceBlendFactor_bits 5 #define GFX6_BLEND_STATE_ENTRY_SourceBlendFactor_bits 5 static inline uint32_t ATTRIBUTE_PURE BLEND_STATE_ENTRY_SourceBlendFactor_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 5; case 110: return 5; case 90: return 5; case 80: return 5; case 75: return 5; case 70: return 5; case 60: return 5; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_BLEND_STATE_ENTRY_SourceBlendFactor_start 26 #define GFX12_BLEND_STATE_ENTRY_SourceBlendFactor_start 26 #define GFX11_BLEND_STATE_ENTRY_SourceBlendFactor_start 26 #define GFX9_BLEND_STATE_ENTRY_SourceBlendFactor_start 26 #define GFX8_BLEND_STATE_ENTRY_SourceBlendFactor_start 26 #define GFX75_BLEND_STATE_ENTRY_SourceBlendFactor_start 5 #define GFX7_BLEND_STATE_ENTRY_SourceBlendFactor_start 5 #define GFX6_BLEND_STATE_ENTRY_SourceBlendFactor_start 5 static inline uint32_t ATTRIBUTE_PURE BLEND_STATE_ENTRY_SourceBlendFactor_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 26; case 120: return 26; case 110: return 26; case 90: return 26; case 80: return 26; case 75: return 5; case 70: return 5; case 60: return 5; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* BLEND_STATE_ENTRY::Write Disable Alpha */ #define GFX125_BLEND_STATE_ENTRY_WriteDisableAlpha_bits 1 #define GFX12_BLEND_STATE_ENTRY_WriteDisableAlpha_bits 1 #define GFX11_BLEND_STATE_ENTRY_WriteDisableAlpha_bits 1 #define GFX9_BLEND_STATE_ENTRY_WriteDisableAlpha_bits 1 #define GFX8_BLEND_STATE_ENTRY_WriteDisableAlpha_bits 1 #define GFX75_BLEND_STATE_ENTRY_WriteDisableAlpha_bits 1 #define GFX7_BLEND_STATE_ENTRY_WriteDisableAlpha_bits 1 #define GFX6_BLEND_STATE_ENTRY_WriteDisableAlpha_bits 1 static inline uint32_t ATTRIBUTE_PURE BLEND_STATE_ENTRY_WriteDisableAlpha_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_BLEND_STATE_ENTRY_WriteDisableAlpha_start 3 #define GFX12_BLEND_STATE_ENTRY_WriteDisableAlpha_start 3 #define GFX11_BLEND_STATE_ENTRY_WriteDisableAlpha_start 3 #define GFX9_BLEND_STATE_ENTRY_WriteDisableAlpha_start 3 #define GFX8_BLEND_STATE_ENTRY_WriteDisableAlpha_start 3 #define GFX75_BLEND_STATE_ENTRY_WriteDisableAlpha_start 59 #define GFX7_BLEND_STATE_ENTRY_WriteDisableAlpha_start 59 #define GFX6_BLEND_STATE_ENTRY_WriteDisableAlpha_start 59 static inline uint32_t ATTRIBUTE_PURE BLEND_STATE_ENTRY_WriteDisableAlpha_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 59; case 70: return 59; case 60: return 59; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* BLEND_STATE_ENTRY::Write Disable Blue */ #define GFX125_BLEND_STATE_ENTRY_WriteDisableBlue_bits 1 #define GFX12_BLEND_STATE_ENTRY_WriteDisableBlue_bits 1 #define GFX11_BLEND_STATE_ENTRY_WriteDisableBlue_bits 1 #define GFX9_BLEND_STATE_ENTRY_WriteDisableBlue_bits 1 #define GFX8_BLEND_STATE_ENTRY_WriteDisableBlue_bits 1 #define GFX75_BLEND_STATE_ENTRY_WriteDisableBlue_bits 1 #define GFX7_BLEND_STATE_ENTRY_WriteDisableBlue_bits 1 #define GFX6_BLEND_STATE_ENTRY_WriteDisableBlue_bits 1 static inline uint32_t ATTRIBUTE_PURE BLEND_STATE_ENTRY_WriteDisableBlue_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_BLEND_STATE_ENTRY_WriteDisableBlue_start 0 #define GFX12_BLEND_STATE_ENTRY_WriteDisableBlue_start 0 #define GFX11_BLEND_STATE_ENTRY_WriteDisableBlue_start 0 #define GFX9_BLEND_STATE_ENTRY_WriteDisableBlue_start 0 #define GFX8_BLEND_STATE_ENTRY_WriteDisableBlue_start 0 #define GFX75_BLEND_STATE_ENTRY_WriteDisableBlue_start 56 #define GFX7_BLEND_STATE_ENTRY_WriteDisableBlue_start 56 #define GFX6_BLEND_STATE_ENTRY_WriteDisableBlue_start 56 static inline uint32_t ATTRIBUTE_PURE BLEND_STATE_ENTRY_WriteDisableBlue_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 56; case 70: return 56; case 60: return 56; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* BLEND_STATE_ENTRY::Write Disable Green */ #define GFX125_BLEND_STATE_ENTRY_WriteDisableGreen_bits 1 #define GFX12_BLEND_STATE_ENTRY_WriteDisableGreen_bits 1 #define GFX11_BLEND_STATE_ENTRY_WriteDisableGreen_bits 1 #define GFX9_BLEND_STATE_ENTRY_WriteDisableGreen_bits 1 #define GFX8_BLEND_STATE_ENTRY_WriteDisableGreen_bits 1 #define GFX75_BLEND_STATE_ENTRY_WriteDisableGreen_bits 1 #define GFX7_BLEND_STATE_ENTRY_WriteDisableGreen_bits 1 #define GFX6_BLEND_STATE_ENTRY_WriteDisableGreen_bits 1 static inline uint32_t ATTRIBUTE_PURE BLEND_STATE_ENTRY_WriteDisableGreen_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_BLEND_STATE_ENTRY_WriteDisableGreen_start 1 #define GFX12_BLEND_STATE_ENTRY_WriteDisableGreen_start 1 #define GFX11_BLEND_STATE_ENTRY_WriteDisableGreen_start 1 #define GFX9_BLEND_STATE_ENTRY_WriteDisableGreen_start 1 #define GFX8_BLEND_STATE_ENTRY_WriteDisableGreen_start 1 #define GFX75_BLEND_STATE_ENTRY_WriteDisableGreen_start 57 #define GFX7_BLEND_STATE_ENTRY_WriteDisableGreen_start 57 #define GFX6_BLEND_STATE_ENTRY_WriteDisableGreen_start 57 static inline uint32_t ATTRIBUTE_PURE BLEND_STATE_ENTRY_WriteDisableGreen_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 57; case 70: return 57; case 60: return 57; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* BLEND_STATE_ENTRY::Write Disable Red */ #define GFX125_BLEND_STATE_ENTRY_WriteDisableRed_bits 1 #define GFX12_BLEND_STATE_ENTRY_WriteDisableRed_bits 1 #define GFX11_BLEND_STATE_ENTRY_WriteDisableRed_bits 1 #define GFX9_BLEND_STATE_ENTRY_WriteDisableRed_bits 1 #define GFX8_BLEND_STATE_ENTRY_WriteDisableRed_bits 1 #define GFX75_BLEND_STATE_ENTRY_WriteDisableRed_bits 1 #define GFX7_BLEND_STATE_ENTRY_WriteDisableRed_bits 1 #define GFX6_BLEND_STATE_ENTRY_WriteDisableRed_bits 1 static inline uint32_t ATTRIBUTE_PURE BLEND_STATE_ENTRY_WriteDisableRed_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_BLEND_STATE_ENTRY_WriteDisableRed_start 2 #define GFX12_BLEND_STATE_ENTRY_WriteDisableRed_start 2 #define GFX11_BLEND_STATE_ENTRY_WriteDisableRed_start 2 #define GFX9_BLEND_STATE_ENTRY_WriteDisableRed_start 2 #define GFX8_BLEND_STATE_ENTRY_WriteDisableRed_start 2 #define GFX75_BLEND_STATE_ENTRY_WriteDisableRed_start 58 #define GFX7_BLEND_STATE_ENTRY_WriteDisableRed_start 58 #define GFX6_BLEND_STATE_ENTRY_WriteDisableRed_start 58 static inline uint32_t ATTRIBUTE_PURE BLEND_STATE_ENTRY_WriteDisableRed_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 58; case 70: return 58; case 60: return 58; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* BLEND_STATE_ENTRY::X Dither Offset */ #define GFX75_BLEND_STATE_ENTRY_XDitherOffset_bits 2 #define GFX7_BLEND_STATE_ENTRY_XDitherOffset_bits 2 #define GFX6_BLEND_STATE_ENTRY_XDitherOffset_bits 2 static inline uint32_t ATTRIBUTE_PURE BLEND_STATE_ENTRY_XDitherOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_BLEND_STATE_ENTRY_XDitherOffset_start 42 #define GFX7_BLEND_STATE_ENTRY_XDitherOffset_start 42 #define GFX6_BLEND_STATE_ENTRY_XDitherOffset_start 42 static inline uint32_t ATTRIBUTE_PURE BLEND_STATE_ENTRY_XDitherOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 42; case 70: return 42; case 60: return 42; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* BLEND_STATE_ENTRY::Y Dither Offset */ #define GFX75_BLEND_STATE_ENTRY_YDitherOffset_bits 2 #define GFX7_BLEND_STATE_ENTRY_YDitherOffset_bits 2 #define GFX6_BLEND_STATE_ENTRY_YDitherOffset_bits 2 static inline uint32_t ATTRIBUTE_PURE BLEND_STATE_ENTRY_YDitherOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_BLEND_STATE_ENTRY_YDitherOffset_start 40 #define GFX7_BLEND_STATE_ENTRY_YDitherOffset_start 40 #define GFX6_BLEND_STATE_ENTRY_YDitherOffset_start 40 static inline uint32_t ATTRIBUTE_PURE BLEND_STATE_ENTRY_YDitherOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 40; case 70: return 40; case 60: return 40; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CACHE_MODE_0 */ #define GFX125_CACHE_MODE_0_length 1 #define GFX12_CACHE_MODE_0_length 1 #define GFX11_CACHE_MODE_0_length 1 #define GFX9_CACHE_MODE_0_length 1 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_0_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CACHE_MODE_0::Depth Related Cache Pipelined Flush Disable */ #define GFX125_CACHE_MODE_0_DepthRelatedCachePipelinedFlushDisable_bits 1 #define GFX12_CACHE_MODE_0_DepthRelatedCachePipelinedFlushDisable_bits 1 #define GFX11_CACHE_MODE_0_DepthRelatedCachePipelinedFlushDisable_bits 1 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_0_DepthRelatedCachePipelinedFlushDisable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CACHE_MODE_0_DepthRelatedCachePipelinedFlushDisable_start 8 #define GFX12_CACHE_MODE_0_DepthRelatedCachePipelinedFlushDisable_start 8 #define GFX11_CACHE_MODE_0_DepthRelatedCachePipelinedFlushDisable_start 8 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_0_DepthRelatedCachePipelinedFlushDisable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CACHE_MODE_0::Depth Related Cache Pipelined Flush Disable Mask */ #define GFX125_CACHE_MODE_0_DepthRelatedCachePipelinedFlushDisableMask_bits 1 #define GFX12_CACHE_MODE_0_DepthRelatedCachePipelinedFlushDisableMask_bits 1 #define GFX11_CACHE_MODE_0_DepthRelatedCachePipelinedFlushDisableMask_bits 1 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_0_DepthRelatedCachePipelinedFlushDisableMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CACHE_MODE_0_DepthRelatedCachePipelinedFlushDisableMask_start 24 #define GFX12_CACHE_MODE_0_DepthRelatedCachePipelinedFlushDisableMask_start 24 #define GFX11_CACHE_MODE_0_DepthRelatedCachePipelinedFlushDisableMask_start 24 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_0_DepthRelatedCachePipelinedFlushDisableMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CACHE_MODE_0::Disable Byte sharing for 3D TYF LOD1 surfaces for 32/64/128 bpp */ #define GFX125_CACHE_MODE_0_DisableBytesharingfor3DTYFLOD1surfacesfor3264128bpp_bits 1 #define GFX12_CACHE_MODE_0_DisableBytesharingfor3DTYFLOD1surfacesfor3264128bpp_bits 1 #define GFX11_CACHE_MODE_0_DisableBytesharingfor3DTYFLOD1surfacesfor3264128bpp_bits 1 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_0_DisableBytesharingfor3DTYFLOD1surfacesfor3264128bpp_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CACHE_MODE_0_DisableBytesharingfor3DTYFLOD1surfacesfor3264128bpp_start 0 #define GFX12_CACHE_MODE_0_DisableBytesharingfor3DTYFLOD1surfacesfor3264128bpp_start 0 #define GFX11_CACHE_MODE_0_DisableBytesharingfor3DTYFLOD1surfacesfor3264128bpp_start 0 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_0_DisableBytesharingfor3DTYFLOD1surfacesfor3264128bpp_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CACHE_MODE_0::Disable Byte sharing for 3D TYF LOD1 surfaces for 32/64/128 bpp Mask */ #define GFX125_CACHE_MODE_0_DisableBytesharingfor3DTYFLOD1surfacesfor3264128bppMask_bits 1 #define GFX12_CACHE_MODE_0_DisableBytesharingfor3DTYFLOD1surfacesfor3264128bppMask_bits 1 #define GFX11_CACHE_MODE_0_DisableBytesharingfor3DTYFLOD1surfacesfor3264128bppMask_bits 1 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_0_DisableBytesharingfor3DTYFLOD1surfacesfor3264128bppMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CACHE_MODE_0_DisableBytesharingfor3DTYFLOD1surfacesfor3264128bppMask_start 16 #define GFX12_CACHE_MODE_0_DisableBytesharingfor3DTYFLOD1surfacesfor3264128bppMask_start 16 #define GFX11_CACHE_MODE_0_DisableBytesharingfor3DTYFLOD1surfacesfor3264128bppMask_start 16 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_0_DisableBytesharingfor3DTYFLOD1surfacesfor3264128bppMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CACHE_MODE_0::Disable Repacking for Compression */ #define GFX125_CACHE_MODE_0_DisableRepackingforCompression_bits 1 #define GFX12_CACHE_MODE_0_DisableRepackingforCompression_bits 1 #define GFX11_CACHE_MODE_0_DisableRepackingforCompression_bits 1 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_0_DisableRepackingforCompression_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CACHE_MODE_0_DisableRepackingforCompression_start 15 #define GFX12_CACHE_MODE_0_DisableRepackingforCompression_start 15 #define GFX11_CACHE_MODE_0_DisableRepackingforCompression_start 15 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_0_DisableRepackingforCompression_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 15; case 120: return 15; case 110: return 15; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CACHE_MODE_0::Disable Repacking for Compression Mask */ #define GFX125_CACHE_MODE_0_DisableRepackingforCompressionMask_bits 1 #define GFX12_CACHE_MODE_0_DisableRepackingforCompressionMask_bits 1 #define GFX11_CACHE_MODE_0_DisableRepackingforCompressionMask_bits 1 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_0_DisableRepackingforCompressionMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CACHE_MODE_0_DisableRepackingforCompressionMask_start 31 #define GFX12_CACHE_MODE_0_DisableRepackingforCompressionMask_start 31 #define GFX11_CACHE_MODE_0_DisableRepackingforCompressionMask_start 31 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_0_DisableRepackingforCompressionMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 31; case 120: return 31; case 110: return 31; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CACHE_MODE_0::Disable clock gating in the pixel backend */ #define GFX125_CACHE_MODE_0_Disableclockgatinginthepixelbackend_bits 1 #define GFX12_CACHE_MODE_0_Disableclockgatinginthepixelbackend_bits 1 #define GFX11_CACHE_MODE_0_Disableclockgatinginthepixelbackend_bits 1 #define GFX9_CACHE_MODE_0_Disableclockgatinginthepixelbackend_bits 1 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_0_Disableclockgatinginthepixelbackend_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CACHE_MODE_0_Disableclockgatinginthepixelbackend_start 1 #define GFX12_CACHE_MODE_0_Disableclockgatinginthepixelbackend_start 1 #define GFX11_CACHE_MODE_0_Disableclockgatinginthepixelbackend_start 1 #define GFX9_CACHE_MODE_0_Disableclockgatinginthepixelbackend_start 1 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_0_Disableclockgatinginthepixelbackend_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CACHE_MODE_0::Disable clock gating in the pixel backend Mask */ #define GFX125_CACHE_MODE_0_DisableclockgatinginthepixelbackendMask_bits 1 #define GFX12_CACHE_MODE_0_DisableclockgatinginthepixelbackendMask_bits 1 #define GFX11_CACHE_MODE_0_DisableclockgatinginthepixelbackendMask_bits 1 #define GFX9_CACHE_MODE_0_DisableclockgatinginthepixelbackendMask_bits 1 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_0_DisableclockgatinginthepixelbackendMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CACHE_MODE_0_DisableclockgatinginthepixelbackendMask_start 17 #define GFX12_CACHE_MODE_0_DisableclockgatinginthepixelbackendMask_start 17 #define GFX11_CACHE_MODE_0_DisableclockgatinginthepixelbackendMask_start 17 #define GFX9_CACHE_MODE_0_DisableclockgatinginthepixelbackendMask_start 17 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_0_DisableclockgatinginthepixelbackendMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 17; case 120: return 17; case 110: return 17; case 90: return 17; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CACHE_MODE_0::Hierarchical Z Disable */ #define GFX125_CACHE_MODE_0_HierarchicalZDisable_bits 1 #define GFX12_CACHE_MODE_0_HierarchicalZDisable_bits 1 #define GFX11_CACHE_MODE_0_HierarchicalZDisable_bits 1 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_0_HierarchicalZDisable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CACHE_MODE_0_HierarchicalZDisable_start 3 #define GFX12_CACHE_MODE_0_HierarchicalZDisable_start 3 #define GFX11_CACHE_MODE_0_HierarchicalZDisable_start 3 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_0_HierarchicalZDisable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CACHE_MODE_0::Hierarchical Z Disable Mask */ #define GFX125_CACHE_MODE_0_HierarchicalZDisableMask_bits 1 #define GFX12_CACHE_MODE_0_HierarchicalZDisableMask_bits 1 #define GFX11_CACHE_MODE_0_HierarchicalZDisableMask_bits 1 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_0_HierarchicalZDisableMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CACHE_MODE_0_HierarchicalZDisableMask_start 19 #define GFX12_CACHE_MODE_0_HierarchicalZDisableMask_start 19 #define GFX11_CACHE_MODE_0_HierarchicalZDisableMask_start 19 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_0_HierarchicalZDisableMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 19; case 120: return 19; case 110: return 19; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CACHE_MODE_0::Hierarchical Z RAW Stall Optimization Disable */ #define GFX9_CACHE_MODE_0_HierarchicalZRAWStallOptimizationDisable_bits 1 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_0_HierarchicalZRAWStallOptimizationDisable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_CACHE_MODE_0_HierarchicalZRAWStallOptimizationDisable_start 2 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_0_HierarchicalZRAWStallOptimizationDisable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 2; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CACHE_MODE_0::Hierarchical Z RAW Stall Optimization Disable Mask */ #define GFX9_CACHE_MODE_0_HierarchicalZRAWStallOptimizationDisableMask_bits 1 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_0_HierarchicalZRAWStallOptimizationDisableMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_CACHE_MODE_0_HierarchicalZRAWStallOptimizationDisableMask_start 18 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_0_HierarchicalZRAWStallOptimizationDisableMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 18; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CACHE_MODE_0::MSAA Compression Plane Number Threshold for eLLC */ #define GFX125_CACHE_MODE_0_MSAACompressionPlaneNumberThresholdforeLLC_bits 3 #define GFX12_CACHE_MODE_0_MSAACompressionPlaneNumberThresholdforeLLC_bits 3 #define GFX11_CACHE_MODE_0_MSAACompressionPlaneNumberThresholdforeLLC_bits 3 #define GFX9_CACHE_MODE_0_MSAACompressionPlaneNumberThresholdforeLLC_bits 3 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_0_MSAACompressionPlaneNumberThresholdforeLLC_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CACHE_MODE_0_MSAACompressionPlaneNumberThresholdforeLLC_start 12 #define GFX12_CACHE_MODE_0_MSAACompressionPlaneNumberThresholdforeLLC_start 12 #define GFX11_CACHE_MODE_0_MSAACompressionPlaneNumberThresholdforeLLC_start 12 #define GFX9_CACHE_MODE_0_MSAACompressionPlaneNumberThresholdforeLLC_start 12 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_0_MSAACompressionPlaneNumberThresholdforeLLC_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 12; case 120: return 12; case 110: return 12; case 90: return 12; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CACHE_MODE_0::MSAA Compression Plane Number Threshold for eLLC Mask */ #define GFX125_CACHE_MODE_0_MSAACompressionPlaneNumberThresholdforeLLCMask_bits 3 #define GFX12_CACHE_MODE_0_MSAACompressionPlaneNumberThresholdforeLLCMask_bits 3 #define GFX11_CACHE_MODE_0_MSAACompressionPlaneNumberThresholdforeLLCMask_bits 3 #define GFX9_CACHE_MODE_0_MSAACompressionPlaneNumberThresholdforeLLCMask_bits 3 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_0_MSAACompressionPlaneNumberThresholdforeLLCMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CACHE_MODE_0_MSAACompressionPlaneNumberThresholdforeLLCMask_start 28 #define GFX12_CACHE_MODE_0_MSAACompressionPlaneNumberThresholdforeLLCMask_start 28 #define GFX11_CACHE_MODE_0_MSAACompressionPlaneNumberThresholdforeLLCMask_start 28 #define GFX9_CACHE_MODE_0_MSAACompressionPlaneNumberThresholdforeLLCMask_start 28 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_0_MSAACompressionPlaneNumberThresholdforeLLCMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 28; case 120: return 28; case 110: return 28; case 90: return 28; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CACHE_MODE_0::Null tile fix disable */ #define GFX9_CACHE_MODE_0_Nulltilefixdisable_bits 1 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_0_Nulltilefixdisable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_CACHE_MODE_0_Nulltilefixdisable_start 0 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_0_Nulltilefixdisable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CACHE_MODE_0::Null tile fix disable Mask */ #define GFX9_CACHE_MODE_0_NulltilefixdisableMask_bits 1 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_0_NulltilefixdisableMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_CACHE_MODE_0_NulltilefixdisableMask_start 16 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_0_NulltilefixdisableMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 16; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CACHE_MODE_0::RCC Eviction Policy */ #define GFX125_CACHE_MODE_0_RCCEvictionPolicy_bits 1 #define GFX12_CACHE_MODE_0_RCCEvictionPolicy_bits 1 #define GFX11_CACHE_MODE_0_RCCEvictionPolicy_bits 1 #define GFX9_CACHE_MODE_0_RCCEvictionPolicy_bits 1 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_0_RCCEvictionPolicy_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CACHE_MODE_0_RCCEvictionPolicy_start 4 #define GFX12_CACHE_MODE_0_RCCEvictionPolicy_start 4 #define GFX11_CACHE_MODE_0_RCCEvictionPolicy_start 4 #define GFX9_CACHE_MODE_0_RCCEvictionPolicy_start 4 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_0_RCCEvictionPolicy_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CACHE_MODE_0::RCC Eviction Policy Mask */ #define GFX125_CACHE_MODE_0_RCCEvictionPolicyMask_bits 1 #define GFX12_CACHE_MODE_0_RCCEvictionPolicyMask_bits 1 #define GFX11_CACHE_MODE_0_RCCEvictionPolicyMask_bits 1 #define GFX9_CACHE_MODE_0_RCCEvictionPolicyMask_bits 1 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_0_RCCEvictionPolicyMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CACHE_MODE_0_RCCEvictionPolicyMask_start 20 #define GFX12_CACHE_MODE_0_RCCEvictionPolicyMask_start 20 #define GFX11_CACHE_MODE_0_RCCEvictionPolicyMask_start 20 #define GFX9_CACHE_MODE_0_RCCEvictionPolicyMask_start 20 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_0_RCCEvictionPolicyMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 20; case 120: return 20; case 110: return 20; case 90: return 20; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CACHE_MODE_0::RCZ PMA Not-Promoted Allocation stall optimization Disable due to change in depth parameters */ #define GFX125_CACHE_MODE_0_RCZPMANotPromotedAllocationstalloptimizationDisableduetochangeindepthparameters_bits 1 #define GFX12_CACHE_MODE_0_RCZPMANotPromotedAllocationstalloptimizationDisableduetochangeindepthparameters_bits 1 #define GFX11_CACHE_MODE_0_RCZPMANotPromotedAllocationstalloptimizationDisableduetochangeindepthparameters_bits 1 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_0_RCZPMANotPromotedAllocationstalloptimizationDisableduetochangeindepthparameters_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CACHE_MODE_0_RCZPMANotPromotedAllocationstalloptimizationDisableduetochangeindepthparameters_start 10 #define GFX12_CACHE_MODE_0_RCZPMANotPromotedAllocationstalloptimizationDisableduetochangeindepthparameters_start 10 #define GFX11_CACHE_MODE_0_RCZPMANotPromotedAllocationstalloptimizationDisableduetochangeindepthparameters_start 10 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_0_RCZPMANotPromotedAllocationstalloptimizationDisableduetochangeindepthparameters_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 10; case 120: return 10; case 110: return 10; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CACHE_MODE_0::RCZ PMA Not-Promoted Allocation stall optimization Disable due to change in depth parameters Mask */ #define GFX125_CACHE_MODE_0_RCZPMANotPromotedAllocationstalloptimizationDisableduetochangeindepthparametersMask_bits 1 #define GFX12_CACHE_MODE_0_RCZPMANotPromotedAllocationstalloptimizationDisableduetochangeindepthparametersMask_bits 1 #define GFX11_CACHE_MODE_0_RCZPMANotPromotedAllocationstalloptimizationDisableduetochangeindepthparametersMask_bits 1 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_0_RCZPMANotPromotedAllocationstalloptimizationDisableduetochangeindepthparametersMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CACHE_MODE_0_RCZPMANotPromotedAllocationstalloptimizationDisableduetochangeindepthparametersMask_start 26 #define GFX12_CACHE_MODE_0_RCZPMANotPromotedAllocationstalloptimizationDisableduetochangeindepthparametersMask_start 26 #define GFX11_CACHE_MODE_0_RCZPMANotPromotedAllocationstalloptimizationDisableduetochangeindepthparametersMask_start 26 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_0_RCZPMANotPromotedAllocationstalloptimizationDisableduetochangeindepthparametersMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 26; case 120: return 26; case 110: return 26; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CACHE_MODE_0::STC PMA Optimization Disable */ #define GFX125_CACHE_MODE_0_STCPMAOptimizationDisable_bits 1 #define GFX12_CACHE_MODE_0_STCPMAOptimizationDisable_bits 1 #define GFX11_CACHE_MODE_0_STCPMAOptimizationDisable_bits 1 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_0_STCPMAOptimizationDisable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CACHE_MODE_0_STCPMAOptimizationDisable_start 5 #define GFX12_CACHE_MODE_0_STCPMAOptimizationDisable_start 5 #define GFX11_CACHE_MODE_0_STCPMAOptimizationDisable_start 5 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_0_STCPMAOptimizationDisable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 5; case 110: return 5; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CACHE_MODE_0::STC PMA Optimization Disable Mask */ #define GFX125_CACHE_MODE_0_STCPMAOptimizationDisableMask_bits 1 #define GFX12_CACHE_MODE_0_STCPMAOptimizationDisableMask_bits 1 #define GFX11_CACHE_MODE_0_STCPMAOptimizationDisableMask_bits 1 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_0_STCPMAOptimizationDisableMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CACHE_MODE_0_STCPMAOptimizationDisableMask_start 21 #define GFX12_CACHE_MODE_0_STCPMAOptimizationDisableMask_start 21 #define GFX11_CACHE_MODE_0_STCPMAOptimizationDisableMask_start 21 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_0_STCPMAOptimizationDisableMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 21; case 120: return 21; case 110: return 21; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CACHE_MODE_0::STC PMA Optimization Enable */ #define GFX9_CACHE_MODE_0_STCPMAOptimizationEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_0_STCPMAOptimizationEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_CACHE_MODE_0_STCPMAOptimizationEnable_start 5 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_0_STCPMAOptimizationEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 5; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CACHE_MODE_0::STC PMA Optimization Enable Mask */ #define GFX9_CACHE_MODE_0_STCPMAOptimizationEnableMask_bits 1 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_0_STCPMAOptimizationEnableMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_CACHE_MODE_0_STCPMAOptimizationEnableMask_start 21 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_0_STCPMAOptimizationEnableMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 21; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CACHE_MODE_0::STC Read-Hit Wonly Optimization Disable */ #define GFX125_CACHE_MODE_0_STCReadHitWonlyOptimizationDisable_bits 1 #define GFX12_CACHE_MODE_0_STCReadHitWonlyOptimizationDisable_bits 1 #define GFX11_CACHE_MODE_0_STCReadHitWonlyOptimizationDisable_bits 1 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_0_STCReadHitWonlyOptimizationDisable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CACHE_MODE_0_STCReadHitWonlyOptimizationDisable_start 6 #define GFX12_CACHE_MODE_0_STCReadHitWonlyOptimizationDisable_start 6 #define GFX11_CACHE_MODE_0_STCReadHitWonlyOptimizationDisable_start 6 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_0_STCReadHitWonlyOptimizationDisable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CACHE_MODE_0::STC Read-Hit Wonly Optimization Disable Mask */ #define GFX125_CACHE_MODE_0_STCReadHitWonlyOptimizationDisableMask_bits 1 #define GFX12_CACHE_MODE_0_STCReadHitWonlyOptimizationDisableMask_bits 1 #define GFX11_CACHE_MODE_0_STCReadHitWonlyOptimizationDisableMask_bits 1 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_0_STCReadHitWonlyOptimizationDisableMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CACHE_MODE_0_STCReadHitWonlyOptimizationDisableMask_start 22 #define GFX12_CACHE_MODE_0_STCReadHitWonlyOptimizationDisableMask_start 22 #define GFX11_CACHE_MODE_0_STCReadHitWonlyOptimizationDisableMask_start 22 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_0_STCReadHitWonlyOptimizationDisableMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 22; case 120: return 22; case 110: return 22; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CACHE_MODE_0::Sampler L2 Disable */ #define GFX9_CACHE_MODE_0_SamplerL2Disable_bits 1 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_0_SamplerL2Disable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_CACHE_MODE_0_SamplerL2Disable_start 15 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_0_SamplerL2Disable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 15; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CACHE_MODE_0::Sampler L2 Disable Mask */ #define GFX9_CACHE_MODE_0_SamplerL2DisableMask_bits 1 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_0_SamplerL2DisableMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_CACHE_MODE_0_SamplerL2DisableMask_start 31 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_0_SamplerL2DisableMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 31; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CACHE_MODE_0::Sampler L2 Request Arbitration */ #define GFX9_CACHE_MODE_0_SamplerL2RequestArbitration_bits 2 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_0_SamplerL2RequestArbitration_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 2; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_CACHE_MODE_0_SamplerL2RequestArbitration_start 6 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_0_SamplerL2RequestArbitration_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 6; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CACHE_MODE_0::Sampler L2 Request Arbitration Mask */ #define GFX9_CACHE_MODE_0_SamplerL2RequestArbitrationMask_bits 2 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_0_SamplerL2RequestArbitrationMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 2; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_CACHE_MODE_0_SamplerL2RequestArbitrationMask_start 22 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_0_SamplerL2RequestArbitrationMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 22; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CACHE_MODE_0::Sampler L2 TLB Prefetch Enable */ #define GFX125_CACHE_MODE_0_SamplerL2TLBPrefetchEnable_bits 1 #define GFX12_CACHE_MODE_0_SamplerL2TLBPrefetchEnable_bits 1 #define GFX11_CACHE_MODE_0_SamplerL2TLBPrefetchEnable_bits 1 #define GFX9_CACHE_MODE_0_SamplerL2TLBPrefetchEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_0_SamplerL2TLBPrefetchEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CACHE_MODE_0_SamplerL2TLBPrefetchEnable_start 9 #define GFX12_CACHE_MODE_0_SamplerL2TLBPrefetchEnable_start 9 #define GFX11_CACHE_MODE_0_SamplerL2TLBPrefetchEnable_start 9 #define GFX9_CACHE_MODE_0_SamplerL2TLBPrefetchEnable_start 9 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_0_SamplerL2TLBPrefetchEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 9; case 120: return 9; case 110: return 9; case 90: return 9; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CACHE_MODE_0::Sampler L2 TLB Prefetch Enable Mask */ #define GFX125_CACHE_MODE_0_SamplerL2TLBPrefetchEnableMask_bits 1 #define GFX12_CACHE_MODE_0_SamplerL2TLBPrefetchEnableMask_bits 1 #define GFX11_CACHE_MODE_0_SamplerL2TLBPrefetchEnableMask_bits 1 #define GFX9_CACHE_MODE_0_SamplerL2TLBPrefetchEnableMask_bits 1 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_0_SamplerL2TLBPrefetchEnableMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CACHE_MODE_0_SamplerL2TLBPrefetchEnableMask_start 25 #define GFX12_CACHE_MODE_0_SamplerL2TLBPrefetchEnableMask_start 25 #define GFX11_CACHE_MODE_0_SamplerL2TLBPrefetchEnableMask_start 25 #define GFX9_CACHE_MODE_0_SamplerL2TLBPrefetchEnableMask_start 25 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_0_SamplerL2TLBPrefetchEnableMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 25; case 120: return 25; case 110: return 25; case 90: return 25; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CACHE_MODE_0::Sampler Set Remapping for 3D Disable */ #define GFX9_CACHE_MODE_0_SamplerSetRemappingfor3DDisable_bits 1 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_0_SamplerSetRemappingfor3DDisable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_CACHE_MODE_0_SamplerSetRemappingfor3DDisable_start 11 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_0_SamplerSetRemappingfor3DDisable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 11; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CACHE_MODE_0::Sampler Set Remapping for 3D Disable Mask */ #define GFX9_CACHE_MODE_0_SamplerSetRemappingfor3DDisableMask_bits 1 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_0_SamplerSetRemappingfor3DDisableMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_CACHE_MODE_0_SamplerSetRemappingfor3DDisableMask_start 27 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_0_SamplerSetRemappingfor3DDisableMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 27; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CACHE_MODE_1 */ #define GFX125_CACHE_MODE_1_length 1 #define GFX12_CACHE_MODE_1_length 1 #define GFX11_CACHE_MODE_1_length 1 #define GFX9_CACHE_MODE_1_length 1 #define GFX8_CACHE_MODE_1_length 1 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_1_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CACHE_MODE_1::4X4 RCPFE-STC Optimization Disable */ #define GFX9_CACHE_MODE_1_4X4RCPFESTCOptimizationDisable_bits 1 #define GFX8_CACHE_MODE_1_4X4RCPFESTCOptimizationDisable_bits 1 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_1_4X4RCPFESTCOptimizationDisable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_CACHE_MODE_1_4X4RCPFESTCOptimizationDisable_start 6 #define GFX8_CACHE_MODE_1_4X4RCPFESTCOptimizationDisable_start 6 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_1_4X4RCPFESTCOptimizationDisable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 6; case 80: return 6; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CACHE_MODE_1::4X4 RCPFE-STC Optimization Disable Mask */ #define GFX9_CACHE_MODE_1_4X4RCPFESTCOptimizationDisableMask_bits 1 #define GFX8_CACHE_MODE_1_4X4RCPFESTCOptimizationDisableMask_bits 1 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_1_4X4RCPFESTCOptimizationDisableMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_CACHE_MODE_1_4X4RCPFESTCOptimizationDisableMask_start 22 #define GFX8_CACHE_MODE_1_4X4RCPFESTCOptimizationDisableMask_start 22 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_1_4X4RCPFESTCOptimizationDisableMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 22; case 80: return 22; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CACHE_MODE_1::Blend Optimization Fix Disable */ #define GFX125_CACHE_MODE_1_BlendOptimizationFixDisable_bits 1 #define GFX12_CACHE_MODE_1_BlendOptimizationFixDisable_bits 1 #define GFX11_CACHE_MODE_1_BlendOptimizationFixDisable_bits 1 #define GFX9_CACHE_MODE_1_BlendOptimizationFixDisable_bits 1 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_1_BlendOptimizationFixDisable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CACHE_MODE_1_BlendOptimizationFixDisable_start 14 #define GFX12_CACHE_MODE_1_BlendOptimizationFixDisable_start 14 #define GFX11_CACHE_MODE_1_BlendOptimizationFixDisable_start 14 #define GFX9_CACHE_MODE_1_BlendOptimizationFixDisable_start 14 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_1_BlendOptimizationFixDisable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 14; case 120: return 14; case 110: return 14; case 90: return 14; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CACHE_MODE_1::Blend Optimization Fix Disable Mask */ #define GFX125_CACHE_MODE_1_BlendOptimizationFixDisableMask_bits 1 #define GFX12_CACHE_MODE_1_BlendOptimizationFixDisableMask_bits 1 #define GFX11_CACHE_MODE_1_BlendOptimizationFixDisableMask_bits 1 #define GFX9_CACHE_MODE_1_BlendOptimizationFixDisableMask_bits 1 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_1_BlendOptimizationFixDisableMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CACHE_MODE_1_BlendOptimizationFixDisableMask_start 30 #define GFX12_CACHE_MODE_1_BlendOptimizationFixDisableMask_start 30 #define GFX11_CACHE_MODE_1_BlendOptimizationFixDisableMask_start 30 #define GFX9_CACHE_MODE_1_BlendOptimizationFixDisableMask_start 30 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_1_BlendOptimizationFixDisableMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 30; case 120: return 30; case 110: return 30; case 90: return 30; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CACHE_MODE_1::Color Compression Disable */ #define GFX125_CACHE_MODE_1_ColorCompressionDisable_bits 1 #define GFX12_CACHE_MODE_1_ColorCompressionDisable_bits 1 #define GFX11_CACHE_MODE_1_ColorCompressionDisable_bits 1 #define GFX9_CACHE_MODE_1_ColorCompressionDisable_bits 1 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_1_ColorCompressionDisable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CACHE_MODE_1_ColorCompressionDisable_start 15 #define GFX12_CACHE_MODE_1_ColorCompressionDisable_start 15 #define GFX11_CACHE_MODE_1_ColorCompressionDisable_start 15 #define GFX9_CACHE_MODE_1_ColorCompressionDisable_start 15 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_1_ColorCompressionDisable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 15; case 120: return 15; case 110: return 15; case 90: return 15; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CACHE_MODE_1::Color Compression Disable Mask */ #define GFX125_CACHE_MODE_1_ColorCompressionDisableMask_bits 1 #define GFX12_CACHE_MODE_1_ColorCompressionDisableMask_bits 1 #define GFX11_CACHE_MODE_1_ColorCompressionDisableMask_bits 1 #define GFX9_CACHE_MODE_1_ColorCompressionDisableMask_bits 1 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_1_ColorCompressionDisableMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CACHE_MODE_1_ColorCompressionDisableMask_start 31 #define GFX12_CACHE_MODE_1_ColorCompressionDisableMask_start 31 #define GFX11_CACHE_MODE_1_ColorCompressionDisableMask_start 31 #define GFX9_CACHE_MODE_1_ColorCompressionDisableMask_start 31 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_1_ColorCompressionDisableMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 31; case 120: return 31; case 110: return 31; case 90: return 31; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CACHE_MODE_1::Depth Read Hit Write-Only Optimization Disable */ #define GFX9_CACHE_MODE_1_DepthReadHitWriteOnlyOptimizationDisable_bits 1 #define GFX8_CACHE_MODE_1_DepthReadHitWriteOnlyOptimizationDisable_bits 1 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_1_DepthReadHitWriteOnlyOptimizationDisable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_CACHE_MODE_1_DepthReadHitWriteOnlyOptimizationDisable_start 3 #define GFX8_CACHE_MODE_1_DepthReadHitWriteOnlyOptimizationDisable_start 3 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_1_DepthReadHitWriteOnlyOptimizationDisable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 3; case 80: return 3; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CACHE_MODE_1::Depth Read Hit Write-Only Optimization Disable Mask */ #define GFX9_CACHE_MODE_1_DepthReadHitWriteOnlyOptimizationDisableMask_bits 1 #define GFX8_CACHE_MODE_1_DepthReadHitWriteOnlyOptimizationDisableMask_bits 1 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_1_DepthReadHitWriteOnlyOptimizationDisableMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_CACHE_MODE_1_DepthReadHitWriteOnlyOptimizationDisableMask_start 19 #define GFX8_CACHE_MODE_1_DepthReadHitWriteOnlyOptimizationDisableMask_start 19 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_1_DepthReadHitWriteOnlyOptimizationDisableMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 19; case 80: return 19; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CACHE_MODE_1::Float Blend Optimization Enable */ #define GFX9_CACHE_MODE_1_FloatBlendOptimizationEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_1_FloatBlendOptimizationEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_CACHE_MODE_1_FloatBlendOptimizationEnable_start 4 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_1_FloatBlendOptimizationEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CACHE_MODE_1::Float Blend Optimization Enable Mask */ #define GFX9_CACHE_MODE_1_FloatBlendOptimizationEnableMask_bits 1 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_1_FloatBlendOptimizationEnableMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_CACHE_MODE_1_FloatBlendOptimizationEnableMask_start 20 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_1_FloatBlendOptimizationEnableMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 20; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CACHE_MODE_1::HIZ Eviction Policy */ #define GFX9_CACHE_MODE_1_HIZEvictionPolicy_bits 1 #define GFX8_CACHE_MODE_1_HIZEvictionPolicy_bits 1 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_1_HIZEvictionPolicy_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_CACHE_MODE_1_HIZEvictionPolicy_start 12 #define GFX8_CACHE_MODE_1_HIZEvictionPolicy_start 12 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_1_HIZEvictionPolicy_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 12; case 80: return 12; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CACHE_MODE_1::HIZ Eviction Policy Mask */ #define GFX9_CACHE_MODE_1_HIZEvictionPolicyMask_bits 1 #define GFX8_CACHE_MODE_1_HIZEvictionPolicyMask_bits 1 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_1_HIZEvictionPolicyMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_CACHE_MODE_1_HIZEvictionPolicyMask_start 28 #define GFX8_CACHE_MODE_1_HIZEvictionPolicyMask_start 28 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_1_HIZEvictionPolicyMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 28; case 80: return 28; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CACHE_MODE_1::MCS Cache Disable */ #define GFX125_CACHE_MODE_1_MCSCacheDisable_bits 1 #define GFX12_CACHE_MODE_1_MCSCacheDisable_bits 1 #define GFX11_CACHE_MODE_1_MCSCacheDisable_bits 1 #define GFX9_CACHE_MODE_1_MCSCacheDisable_bits 1 #define GFX8_CACHE_MODE_1_MCSCacheDisable_bits 1 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_1_MCSCacheDisable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CACHE_MODE_1_MCSCacheDisable_start 5 #define GFX12_CACHE_MODE_1_MCSCacheDisable_start 5 #define GFX11_CACHE_MODE_1_MCSCacheDisable_start 5 #define GFX9_CACHE_MODE_1_MCSCacheDisable_start 5 #define GFX8_CACHE_MODE_1_MCSCacheDisable_start 5 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_1_MCSCacheDisable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 5; case 110: return 5; case 90: return 5; case 80: return 5; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CACHE_MODE_1::MCS Cache Disable Mask */ #define GFX125_CACHE_MODE_1_MCSCacheDisableMask_bits 1 #define GFX12_CACHE_MODE_1_MCSCacheDisableMask_bits 1 #define GFX11_CACHE_MODE_1_MCSCacheDisableMask_bits 1 #define GFX9_CACHE_MODE_1_MCSCacheDisableMask_bits 1 #define GFX8_CACHE_MODE_1_MCSCacheDisableMask_bits 1 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_1_MCSCacheDisableMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CACHE_MODE_1_MCSCacheDisableMask_start 21 #define GFX12_CACHE_MODE_1_MCSCacheDisableMask_start 21 #define GFX11_CACHE_MODE_1_MCSCacheDisableMask_start 21 #define GFX9_CACHE_MODE_1_MCSCacheDisableMask_start 21 #define GFX8_CACHE_MODE_1_MCSCacheDisableMask_start 21 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_1_MCSCacheDisableMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 21; case 120: return 21; case 110: return 21; case 90: return 21; case 80: return 21; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CACHE_MODE_1::MSC RAW Hazard Avoidance Bit */ #define GFX125_CACHE_MODE_1_MSCRAWHazardAvoidanceBit_bits 1 #define GFX12_CACHE_MODE_1_MSCRAWHazardAvoidanceBit_bits 1 #define GFX11_CACHE_MODE_1_MSCRAWHazardAvoidanceBit_bits 1 #define GFX9_CACHE_MODE_1_MSCRAWHazardAvoidanceBit_bits 1 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_1_MSCRAWHazardAvoidanceBit_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CACHE_MODE_1_MSCRAWHazardAvoidanceBit_start 9 #define GFX12_CACHE_MODE_1_MSCRAWHazardAvoidanceBit_start 9 #define GFX11_CACHE_MODE_1_MSCRAWHazardAvoidanceBit_start 9 #define GFX9_CACHE_MODE_1_MSCRAWHazardAvoidanceBit_start 9 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_1_MSCRAWHazardAvoidanceBit_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 9; case 120: return 9; case 110: return 9; case 90: return 9; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CACHE_MODE_1::MSC RAW Hazard Avoidance Bit Mask */ #define GFX125_CACHE_MODE_1_MSCRAWHazardAvoidanceBitMask_bits 1 #define GFX12_CACHE_MODE_1_MSCRAWHazardAvoidanceBitMask_bits 1 #define GFX11_CACHE_MODE_1_MSCRAWHazardAvoidanceBitMask_bits 1 #define GFX9_CACHE_MODE_1_MSCRAWHazardAvoidanceBitMask_bits 1 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_1_MSCRAWHazardAvoidanceBitMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CACHE_MODE_1_MSCRAWHazardAvoidanceBitMask_start 25 #define GFX12_CACHE_MODE_1_MSCRAWHazardAvoidanceBitMask_start 25 #define GFX11_CACHE_MODE_1_MSCRAWHazardAvoidanceBitMask_start 25 #define GFX9_CACHE_MODE_1_MSCRAWHazardAvoidanceBitMask_start 25 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_1_MSCRAWHazardAvoidanceBitMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 25; case 120: return 25; case 110: return 25; case 90: return 25; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CACHE_MODE_1::MSC Resolve Optimization Disable */ #define GFX8_CACHE_MODE_1_MSCResolveOptimizationDisable_bits 1 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_1_MSCResolveOptimizationDisable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX8_CACHE_MODE_1_MSCResolveOptimizationDisable_start 14 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_1_MSCResolveOptimizationDisable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 14; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CACHE_MODE_1::MSC Resolve Optimization Disable Mask */ #define GFX8_CACHE_MODE_1_MSCResolveOptimizationDisableMask_bits 1 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_1_MSCResolveOptimizationDisableMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX8_CACHE_MODE_1_MSCResolveOptimizationDisableMask_start 30 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_1_MSCResolveOptimizationDisableMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 30; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CACHE_MODE_1::NP Early Z Fails Disable */ #define GFX125_CACHE_MODE_1_NPEarlyZFailsDisable_bits 1 #define GFX12_CACHE_MODE_1_NPEarlyZFailsDisable_bits 1 #define GFX11_CACHE_MODE_1_NPEarlyZFailsDisable_bits 1 #define GFX9_CACHE_MODE_1_NPEarlyZFailsDisable_bits 1 #define GFX8_CACHE_MODE_1_NPEarlyZFailsDisable_bits 1 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_1_NPEarlyZFailsDisable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CACHE_MODE_1_NPEarlyZFailsDisable_start 13 #define GFX12_CACHE_MODE_1_NPEarlyZFailsDisable_start 13 #define GFX11_CACHE_MODE_1_NPEarlyZFailsDisable_start 13 #define GFX9_CACHE_MODE_1_NPEarlyZFailsDisable_start 13 #define GFX8_CACHE_MODE_1_NPEarlyZFailsDisable_start 13 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_1_NPEarlyZFailsDisable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 13; case 120: return 13; case 110: return 13; case 90: return 13; case 80: return 13; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CACHE_MODE_1::NP Early Z Fails Disable Mask */ #define GFX125_CACHE_MODE_1_NPEarlyZFailsDisableMask_bits 1 #define GFX12_CACHE_MODE_1_NPEarlyZFailsDisableMask_bits 1 #define GFX11_CACHE_MODE_1_NPEarlyZFailsDisableMask_bits 1 #define GFX9_CACHE_MODE_1_NPEarlyZFailsDisableMask_bits 1 #define GFX8_CACHE_MODE_1_NPEarlyZFailsDisableMask_bits 1 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_1_NPEarlyZFailsDisableMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CACHE_MODE_1_NPEarlyZFailsDisableMask_start 29 #define GFX12_CACHE_MODE_1_NPEarlyZFailsDisableMask_start 29 #define GFX11_CACHE_MODE_1_NPEarlyZFailsDisableMask_start 29 #define GFX9_CACHE_MODE_1_NPEarlyZFailsDisableMask_start 29 #define GFX8_CACHE_MODE_1_NPEarlyZFailsDisableMask_start 29 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_1_NPEarlyZFailsDisableMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CACHE_MODE_1::NP PMA Fix Enable */ #define GFX9_CACHE_MODE_1_NPPMAFixEnable_bits 1 #define GFX8_CACHE_MODE_1_NPPMAFixEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_1_NPPMAFixEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_CACHE_MODE_1_NPPMAFixEnable_start 11 #define GFX8_CACHE_MODE_1_NPPMAFixEnable_start 11 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_1_NPPMAFixEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 11; case 80: return 11; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CACHE_MODE_1::NP PMA Fix Enable Mask */ #define GFX9_CACHE_MODE_1_NPPMAFixEnableMask_bits 1 #define GFX8_CACHE_MODE_1_NPPMAFixEnableMask_bits 1 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_1_NPPMAFixEnableMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_CACHE_MODE_1_NPPMAFixEnableMask_start 27 #define GFX8_CACHE_MODE_1_NPPMAFixEnableMask_start 27 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_1_NPPMAFixEnableMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 27; case 80: return 27; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CACHE_MODE_1::Partial Resolve Disable In VC */ #define GFX125_CACHE_MODE_1_PartialResolveDisableInVC_bits 1 #define GFX12_CACHE_MODE_1_PartialResolveDisableInVC_bits 1 #define GFX11_CACHE_MODE_1_PartialResolveDisableInVC_bits 1 #define GFX9_CACHE_MODE_1_PartialResolveDisableInVC_bits 1 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_1_PartialResolveDisableInVC_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CACHE_MODE_1_PartialResolveDisableInVC_start 1 #define GFX12_CACHE_MODE_1_PartialResolveDisableInVC_start 1 #define GFX11_CACHE_MODE_1_PartialResolveDisableInVC_start 1 #define GFX9_CACHE_MODE_1_PartialResolveDisableInVC_start 1 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_1_PartialResolveDisableInVC_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CACHE_MODE_1::Partial Resolve Disable In VC Mask */ #define GFX125_CACHE_MODE_1_PartialResolveDisableInVCMask_bits 1 #define GFX12_CACHE_MODE_1_PartialResolveDisableInVCMask_bits 1 #define GFX11_CACHE_MODE_1_PartialResolveDisableInVCMask_bits 1 #define GFX9_CACHE_MODE_1_PartialResolveDisableInVCMask_bits 1 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_1_PartialResolveDisableInVCMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CACHE_MODE_1_PartialResolveDisableInVCMask_start 17 #define GFX12_CACHE_MODE_1_PartialResolveDisableInVCMask_start 17 #define GFX11_CACHE_MODE_1_PartialResolveDisableInVCMask_start 17 #define GFX9_CACHE_MODE_1_PartialResolveDisableInVCMask_start 17 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_1_PartialResolveDisableInVCMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 17; case 120: return 17; case 110: return 17; case 90: return 17; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CACHE_MODE_1::RCZ PMA Promoted 2 Not-Promoted Allocation stall optimization Disable */ #define GFX125_CACHE_MODE_1_RCZPMAPromoted2NotPromotedAllocationstalloptimizationDisable_bits 1 #define GFX12_CACHE_MODE_1_RCZPMAPromoted2NotPromotedAllocationstalloptimizationDisable_bits 1 #define GFX11_CACHE_MODE_1_RCZPMAPromoted2NotPromotedAllocationstalloptimizationDisable_bits 1 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_1_RCZPMAPromoted2NotPromotedAllocationstalloptimizationDisable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CACHE_MODE_1_RCZPMAPromoted2NotPromotedAllocationstalloptimizationDisable_start 3 #define GFX12_CACHE_MODE_1_RCZPMAPromoted2NotPromotedAllocationstalloptimizationDisable_start 3 #define GFX11_CACHE_MODE_1_RCZPMAPromoted2NotPromotedAllocationstalloptimizationDisable_start 3 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_1_RCZPMAPromoted2NotPromotedAllocationstalloptimizationDisable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CACHE_MODE_1::RCZ PMA Promoted 2 Not-Promoted Allocation stall optimization Disable Mask */ #define GFX125_CACHE_MODE_1_RCZPMAPromoted2NotPromotedAllocationstalloptimizationDisableMask_bits 1 #define GFX12_CACHE_MODE_1_RCZPMAPromoted2NotPromotedAllocationstalloptimizationDisableMask_bits 1 #define GFX11_CACHE_MODE_1_RCZPMAPromoted2NotPromotedAllocationstalloptimizationDisableMask_bits 1 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_1_RCZPMAPromoted2NotPromotedAllocationstalloptimizationDisableMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CACHE_MODE_1_RCZPMAPromoted2NotPromotedAllocationstalloptimizationDisableMask_start 19 #define GFX12_CACHE_MODE_1_RCZPMAPromoted2NotPromotedAllocationstalloptimizationDisableMask_start 19 #define GFX11_CACHE_MODE_1_RCZPMAPromoted2NotPromotedAllocationstalloptimizationDisableMask_start 19 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_1_RCZPMAPromoted2NotPromotedAllocationstalloptimizationDisableMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 19; case 120: return 19; case 110: return 19; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CACHE_MODE_1::RCZ Read after expansion control fix 2 */ #define GFX9_CACHE_MODE_1_RCZReadafterexpansioncontrolfix2_bits 1 #define GFX8_CACHE_MODE_1_RCZReadafterexpansioncontrolfix2_bits 1 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_1_RCZReadafterexpansioncontrolfix2_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_CACHE_MODE_1_RCZReadafterexpansioncontrolfix2_start 2 #define GFX8_CACHE_MODE_1_RCZReadafterexpansioncontrolfix2_start 2 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_1_RCZReadafterexpansioncontrolfix2_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 2; case 80: return 2; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CACHE_MODE_1::RCZ Read after expansion control fix 2 Mask */ #define GFX9_CACHE_MODE_1_RCZReadafterexpansioncontrolfix2Mask_bits 1 #define GFX8_CACHE_MODE_1_RCZReadafterexpansioncontrolfix2Mask_bits 1 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_1_RCZReadafterexpansioncontrolfix2Mask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_CACHE_MODE_1_RCZReadafterexpansioncontrolfix2Mask_start 18 #define GFX8_CACHE_MODE_1_RCZReadafterexpansioncontrolfix2Mask_start 18 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_1_RCZReadafterexpansioncontrolfix2Mask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 18; case 80: return 18; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CACHE_MODE_1::Sampler Cache Set XOR selection */ #define GFX9_CACHE_MODE_1_SamplerCacheSetXORselection_bits 2 #define GFX8_CACHE_MODE_1_SamplerCacheSetXORselection_bits 2 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_1_SamplerCacheSetXORselection_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 2; case 80: return 2; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_CACHE_MODE_1_SamplerCacheSetXORselection_start 7 #define GFX8_CACHE_MODE_1_SamplerCacheSetXORselection_start 7 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_1_SamplerCacheSetXORselection_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 7; case 80: return 7; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CACHE_MODE_1::Sampler Cache Set XOR selection Mask */ #define GFX9_CACHE_MODE_1_SamplerCacheSetXORselectionMask_bits 2 #define GFX8_CACHE_MODE_1_SamplerCacheSetXORselectionMask_bits 2 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_1_SamplerCacheSetXORselectionMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 2; case 80: return 2; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_CACHE_MODE_1_SamplerCacheSetXORselectionMask_start 23 #define GFX8_CACHE_MODE_1_SamplerCacheSetXORselectionMask_start 23 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_1_SamplerCacheSetXORselectionMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 23; case 80: return 23; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CACHE_MODE_SS */ #define GFX125_CACHE_MODE_SS_length 1 #define GFX12_CACHE_MODE_SS_length 1 #define GFX11_CACHE_MODE_SS_length 1 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_SS_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CACHE_MODE_SS::Float Blend Optimization Enable */ #define GFX125_CACHE_MODE_SS_FloatBlendOptimizationEnable_bits 1 #define GFX12_CACHE_MODE_SS_FloatBlendOptimizationEnable_bits 1 #define GFX11_CACHE_MODE_SS_FloatBlendOptimizationEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_SS_FloatBlendOptimizationEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CACHE_MODE_SS_FloatBlendOptimizationEnable_start 4 #define GFX12_CACHE_MODE_SS_FloatBlendOptimizationEnable_start 4 #define GFX11_CACHE_MODE_SS_FloatBlendOptimizationEnable_start 4 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_SS_FloatBlendOptimizationEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CACHE_MODE_SS::Float Blend Optimization Enable Mask */ #define GFX125_CACHE_MODE_SS_FloatBlendOptimizationEnableMask_bits 1 #define GFX12_CACHE_MODE_SS_FloatBlendOptimizationEnableMask_bits 1 #define GFX11_CACHE_MODE_SS_FloatBlendOptimizationEnableMask_bits 1 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_SS_FloatBlendOptimizationEnableMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CACHE_MODE_SS_FloatBlendOptimizationEnableMask_start 20 #define GFX12_CACHE_MODE_SS_FloatBlendOptimizationEnableMask_start 20 #define GFX11_CACHE_MODE_SS_FloatBlendOptimizationEnableMask_start 20 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_SS_FloatBlendOptimizationEnableMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 20; case 120: return 20; case 110: return 20; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CACHE_MODE_SS::Instruction Level 1 Cache Disable */ #define GFX125_CACHE_MODE_SS_InstructionLevel1CacheDisable_bits 1 #define GFX12_CACHE_MODE_SS_InstructionLevel1CacheDisable_bits 1 #define GFX11_CACHE_MODE_SS_InstructionLevel1CacheDisable_bits 1 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_SS_InstructionLevel1CacheDisable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CACHE_MODE_SS_InstructionLevel1CacheDisable_start 0 #define GFX12_CACHE_MODE_SS_InstructionLevel1CacheDisable_start 0 #define GFX11_CACHE_MODE_SS_InstructionLevel1CacheDisable_start 0 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_SS_InstructionLevel1CacheDisable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CACHE_MODE_SS::Instruction Level 1 Cache Disable Mask */ #define GFX125_CACHE_MODE_SS_InstructionLevel1CacheDisableMask_bits 1 #define GFX12_CACHE_MODE_SS_InstructionLevel1CacheDisableMask_bits 1 #define GFX11_CACHE_MODE_SS_InstructionLevel1CacheDisableMask_bits 1 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_SS_InstructionLevel1CacheDisableMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CACHE_MODE_SS_InstructionLevel1CacheDisableMask_start 16 #define GFX12_CACHE_MODE_SS_InstructionLevel1CacheDisableMask_start 16 #define GFX11_CACHE_MODE_SS_InstructionLevel1CacheDisableMask_start 16 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_SS_InstructionLevel1CacheDisableMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CACHE_MODE_SS::Instruction Level 1 Cache and In-Flight Queue Disable */ #define GFX125_CACHE_MODE_SS_InstructionLevel1CacheandInFlightQueueDisable_bits 1 #define GFX12_CACHE_MODE_SS_InstructionLevel1CacheandInFlightQueueDisable_bits 1 #define GFX11_CACHE_MODE_SS_InstructionLevel1CacheandInFlightQueueDisable_bits 1 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_SS_InstructionLevel1CacheandInFlightQueueDisable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CACHE_MODE_SS_InstructionLevel1CacheandInFlightQueueDisable_start 1 #define GFX12_CACHE_MODE_SS_InstructionLevel1CacheandInFlightQueueDisable_start 1 #define GFX11_CACHE_MODE_SS_InstructionLevel1CacheandInFlightQueueDisable_start 1 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_SS_InstructionLevel1CacheandInFlightQueueDisable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CACHE_MODE_SS::Instruction Level 1 Cache and In-Flight Queue Disable Mask */ #define GFX125_CACHE_MODE_SS_InstructionLevel1CacheandInFlightQueueDisableMask_bits 1 #define GFX12_CACHE_MODE_SS_InstructionLevel1CacheandInFlightQueueDisableMask_bits 1 #define GFX11_CACHE_MODE_SS_InstructionLevel1CacheandInFlightQueueDisableMask_bits 1 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_SS_InstructionLevel1CacheandInFlightQueueDisableMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CACHE_MODE_SS_InstructionLevel1CacheandInFlightQueueDisableMask_start 17 #define GFX12_CACHE_MODE_SS_InstructionLevel1CacheandInFlightQueueDisableMask_start 17 #define GFX11_CACHE_MODE_SS_InstructionLevel1CacheandInFlightQueueDisableMask_start 17 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_SS_InstructionLevel1CacheandInFlightQueueDisableMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 17; case 120: return 17; case 110: return 17; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CACHE_MODE_SS::Per Sample Blend Opt Disable */ #define GFX125_CACHE_MODE_SS_PerSampleBlendOptDisable_bits 1 #define GFX12_CACHE_MODE_SS_PerSampleBlendOptDisable_bits 1 #define GFX11_CACHE_MODE_SS_PerSampleBlendOptDisable_bits 1 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_SS_PerSampleBlendOptDisable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CACHE_MODE_SS_PerSampleBlendOptDisable_start 11 #define GFX12_CACHE_MODE_SS_PerSampleBlendOptDisable_start 11 #define GFX11_CACHE_MODE_SS_PerSampleBlendOptDisable_start 11 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_SS_PerSampleBlendOptDisable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 11; case 120: return 11; case 110: return 11; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CACHE_MODE_SS::Per Sample Blend Opt Disable Mask */ #define GFX125_CACHE_MODE_SS_PerSampleBlendOptDisableMask_bits 1 #define GFX12_CACHE_MODE_SS_PerSampleBlendOptDisableMask_bits 1 #define GFX11_CACHE_MODE_SS_PerSampleBlendOptDisableMask_bits 1 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_SS_PerSampleBlendOptDisableMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CACHE_MODE_SS_PerSampleBlendOptDisableMask_start 27 #define GFX12_CACHE_MODE_SS_PerSampleBlendOptDisableMask_start 27 #define GFX11_CACHE_MODE_SS_PerSampleBlendOptDisableMask_start 27 static inline uint32_t ATTRIBUTE_PURE CACHE_MODE_SS_PerSampleBlendOptDisableMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CC_VIEWPORT */ #define GFX125_CC_VIEWPORT_length 2 #define GFX12_CC_VIEWPORT_length 2 #define GFX11_CC_VIEWPORT_length 2 #define GFX9_CC_VIEWPORT_length 2 #define GFX8_CC_VIEWPORT_length 2 #define GFX75_CC_VIEWPORT_length 2 #define GFX7_CC_VIEWPORT_length 2 #define GFX6_CC_VIEWPORT_length 2 #define GFX5_CC_VIEWPORT_length 2 #define GFX45_CC_VIEWPORT_length 2 #define GFX4_CC_VIEWPORT_length 2 static inline uint32_t ATTRIBUTE_PURE CC_VIEWPORT_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 2; case 45: return 2; case 40: return 2; default: unreachable("Invalid hardware generation"); } } /* CC_VIEWPORT::Maximum Depth */ #define GFX125_CC_VIEWPORT_MaximumDepth_bits 32 #define GFX12_CC_VIEWPORT_MaximumDepth_bits 32 #define GFX11_CC_VIEWPORT_MaximumDepth_bits 32 #define GFX9_CC_VIEWPORT_MaximumDepth_bits 32 #define GFX8_CC_VIEWPORT_MaximumDepth_bits 32 #define GFX75_CC_VIEWPORT_MaximumDepth_bits 32 #define GFX7_CC_VIEWPORT_MaximumDepth_bits 32 #define GFX6_CC_VIEWPORT_MaximumDepth_bits 32 #define GFX5_CC_VIEWPORT_MaximumDepth_bits 32 #define GFX45_CC_VIEWPORT_MaximumDepth_bits 32 #define GFX4_CC_VIEWPORT_MaximumDepth_bits 32 static inline uint32_t ATTRIBUTE_PURE CC_VIEWPORT_MaximumDepth_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 32; case 50: return 32; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } #define GFX125_CC_VIEWPORT_MaximumDepth_start 32 #define GFX12_CC_VIEWPORT_MaximumDepth_start 32 #define GFX11_CC_VIEWPORT_MaximumDepth_start 32 #define GFX9_CC_VIEWPORT_MaximumDepth_start 32 #define GFX8_CC_VIEWPORT_MaximumDepth_start 32 #define GFX75_CC_VIEWPORT_MaximumDepth_start 32 #define GFX7_CC_VIEWPORT_MaximumDepth_start 32 #define GFX6_CC_VIEWPORT_MaximumDepth_start 32 #define GFX5_CC_VIEWPORT_MaximumDepth_start 32 #define GFX45_CC_VIEWPORT_MaximumDepth_start 32 #define GFX4_CC_VIEWPORT_MaximumDepth_start 32 static inline uint32_t ATTRIBUTE_PURE CC_VIEWPORT_MaximumDepth_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 32; case 50: return 32; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } /* CC_VIEWPORT::Minimum Depth */ #define GFX125_CC_VIEWPORT_MinimumDepth_bits 32 #define GFX12_CC_VIEWPORT_MinimumDepth_bits 32 #define GFX11_CC_VIEWPORT_MinimumDepth_bits 32 #define GFX9_CC_VIEWPORT_MinimumDepth_bits 32 #define GFX8_CC_VIEWPORT_MinimumDepth_bits 32 #define GFX75_CC_VIEWPORT_MinimumDepth_bits 32 #define GFX7_CC_VIEWPORT_MinimumDepth_bits 32 #define GFX6_CC_VIEWPORT_MinimumDepth_bits 32 #define GFX5_CC_VIEWPORT_MinimumDepth_bits 32 #define GFX45_CC_VIEWPORT_MinimumDepth_bits 32 #define GFX4_CC_VIEWPORT_MinimumDepth_bits 32 static inline uint32_t ATTRIBUTE_PURE CC_VIEWPORT_MinimumDepth_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 32; case 50: return 32; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } #define GFX125_CC_VIEWPORT_MinimumDepth_start 0 #define GFX12_CC_VIEWPORT_MinimumDepth_start 0 #define GFX11_CC_VIEWPORT_MinimumDepth_start 0 #define GFX9_CC_VIEWPORT_MinimumDepth_start 0 #define GFX8_CC_VIEWPORT_MinimumDepth_start 0 #define GFX75_CC_VIEWPORT_MinimumDepth_start 0 #define GFX7_CC_VIEWPORT_MinimumDepth_start 0 #define GFX6_CC_VIEWPORT_MinimumDepth_start 0 #define GFX5_CC_VIEWPORT_MinimumDepth_start 0 #define GFX45_CC_VIEWPORT_MinimumDepth_start 0 #define GFX4_CC_VIEWPORT_MinimumDepth_start 0 static inline uint32_t ATTRIBUTE_PURE CC_VIEWPORT_MinimumDepth_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CFE_STATE */ #define GFX125_CFE_STATE_length 6 static inline uint32_t ATTRIBUTE_PURE CFE_STATE_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CFE_STATE::CFE SubOpcode */ #define GFX125_CFE_STATE_CFESubOpcode_bits 6 static inline uint32_t ATTRIBUTE_PURE CFE_STATE_CFESubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CFE_STATE_CFESubOpcode_start 18 static inline uint32_t ATTRIBUTE_PURE CFE_STATE_CFESubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 18; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CFE_STATE::CFE SubOpcode Variant */ #define GFX125_CFE_STATE_CFESubOpcodeVariant_bits 2 static inline uint32_t ATTRIBUTE_PURE CFE_STATE_CFESubOpcodeVariant_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CFE_STATE_CFESubOpcodeVariant_start 16 static inline uint32_t ATTRIBUTE_PURE CFE_STATE_CFESubOpcodeVariant_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CFE_STATE::Command Type */ #define GFX125_CFE_STATE_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE CFE_STATE_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CFE_STATE_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE CFE_STATE_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CFE_STATE::Compute Command Opcode */ #define GFX125_CFE_STATE_ComputeCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE CFE_STATE_ComputeCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CFE_STATE_ComputeCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE CFE_STATE_ComputeCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CFE_STATE::DWord Length */ #define GFX125_CFE_STATE_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE CFE_STATE_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CFE_STATE_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE CFE_STATE_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CFE_STATE::Fused EU Dispatch */ #define GFX125_CFE_STATE_FusedEUDispatch_bits 1 static inline uint32_t ATTRIBUTE_PURE CFE_STATE_FusedEUDispatch_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CFE_STATE_FusedEUDispatch_start 102 static inline uint32_t ATTRIBUTE_PURE CFE_STATE_FusedEUDispatch_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 102; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CFE_STATE::Maximum Number of Threads */ #define GFX125_CFE_STATE_MaximumNumberofThreads_bits 16 static inline uint32_t ATTRIBUTE_PURE CFE_STATE_MaximumNumberofThreads_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CFE_STATE_MaximumNumberofThreads_start 112 static inline uint32_t ATTRIBUTE_PURE CFE_STATE_MaximumNumberofThreads_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 112; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CFE_STATE::Number of Walkers */ #define GFX125_CFE_STATE_NumberofWalkers_bits 3 static inline uint32_t ATTRIBUTE_PURE CFE_STATE_NumberofWalkers_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CFE_STATE_NumberofWalkers_start 99 static inline uint32_t ATTRIBUTE_PURE CFE_STATE_NumberofWalkers_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 99; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CFE_STATE::Over Dispatch Control */ #define GFX125_CFE_STATE_OverDispatchControl_bits 2 static inline uint32_t ATTRIBUTE_PURE CFE_STATE_OverDispatchControl_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CFE_STATE_OverDispatchControl_start 110 static inline uint32_t ATTRIBUTE_PURE CFE_STATE_OverDispatchControl_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 110; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CFE_STATE::Pipeline */ #define GFX125_CFE_STATE_Pipeline_bits 2 static inline uint32_t ATTRIBUTE_PURE CFE_STATE_Pipeline_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CFE_STATE_Pipeline_start 27 static inline uint32_t ATTRIBUTE_PURE CFE_STATE_Pipeline_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CFE_STATE::Scratch Space Buffer */ #define GFX125_CFE_STATE_ScratchSpaceBuffer_bits 22 static inline uint32_t ATTRIBUTE_PURE CFE_STATE_ScratchSpaceBuffer_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 22; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CFE_STATE_ScratchSpaceBuffer_start 42 static inline uint32_t ATTRIBUTE_PURE CFE_STATE_ScratchSpaceBuffer_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 42; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CFE_STATE::Single Slice Dispatch CCS Mode */ #define GFX125_CFE_STATE_SingleSliceDispatchCCSMode_bits 1 static inline uint32_t ATTRIBUTE_PURE CFE_STATE_SingleSliceDispatchCCSMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CFE_STATE_SingleSliceDispatchCCSMode_start 109 static inline uint32_t ATTRIBUTE_PURE CFE_STATE_SingleSliceDispatchCCSMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 109; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CHICKEN3 */ #define GFX75_CHICKEN3_length 1 static inline uint32_t ATTRIBUTE_PURE CHICKEN3_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CHICKEN3::L3 Atomic Disable */ #define GFX75_CHICKEN3_L3AtomicDisable_bits 1 static inline uint32_t ATTRIBUTE_PURE CHICKEN3_L3AtomicDisable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_CHICKEN3_L3AtomicDisable_start 6 static inline uint32_t ATTRIBUTE_PURE CHICKEN3_L3AtomicDisable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 6; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CHICKEN3::L3 Atomic Disable Mask */ #define GFX75_CHICKEN3_L3AtomicDisableMask_bits 1 static inline uint32_t ATTRIBUTE_PURE CHICKEN3_L3AtomicDisableMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_CHICKEN3_L3AtomicDisableMask_start 22 static inline uint32_t ATTRIBUTE_PURE CHICKEN3_L3AtomicDisableMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 22; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CHICKEN_RASTER_1 */ #define GFX125_CHICKEN_RASTER_1_length 1 static inline uint32_t ATTRIBUTE_PURE CHICKEN_RASTER_1_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CHICKEN_RASTER_1::AA Line Quality Fix */ #define GFX125_CHICKEN_RASTER_1_AALineQualityFix_bits 1 static inline uint32_t ATTRIBUTE_PURE CHICKEN_RASTER_1_AALineQualityFix_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CHICKEN_RASTER_1_AALineQualityFix_start 5 static inline uint32_t ATTRIBUTE_PURE CHICKEN_RASTER_1_AALineQualityFix_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CHICKEN_RASTER_1::AA Line Quality Fix Mask */ #define GFX125_CHICKEN_RASTER_1_AALineQualityFixMask_bits 1 static inline uint32_t ATTRIBUTE_PURE CHICKEN_RASTER_1_AALineQualityFixMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CHICKEN_RASTER_1_AALineQualityFixMask_start 21 static inline uint32_t ATTRIBUTE_PURE CHICKEN_RASTER_1_AALineQualityFixMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 21; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CHROMA_FILTER_COEFFICIENTS_ARRAY */ #define GFX125_CHROMA_FILTER_COEFFICIENTS_ARRAY_length 2 #define GFX12_CHROMA_FILTER_COEFFICIENTS_ARRAY_length 2 #define GFX11_CHROMA_FILTER_COEFFICIENTS_ARRAY_length 2 static inline uint32_t ATTRIBUTE_PURE CHROMA_FILTER_COEFFICIENTS_ARRAY_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CHROMA_FILTER_COEFFICIENTS_ARRAY::Table 1X Filter Coefficient[[n],2] */ #define GFX125_CHROMA_FILTER_COEFFICIENTS_ARRAY_Table1XFilterCoefficientn2_bits 8 #define GFX12_CHROMA_FILTER_COEFFICIENTS_ARRAY_Table1XFilterCoefficientn2_bits 8 #define GFX11_CHROMA_FILTER_COEFFICIENTS_ARRAY_Table1XFilterCoefficientn2_bits 8 static inline uint32_t ATTRIBUTE_PURE CHROMA_FILTER_COEFFICIENTS_ARRAY_Table1XFilterCoefficientn2_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CHROMA_FILTER_COEFFICIENTS_ARRAY_Table1XFilterCoefficientn2_start 0 #define GFX12_CHROMA_FILTER_COEFFICIENTS_ARRAY_Table1XFilterCoefficientn2_start 0 #define GFX11_CHROMA_FILTER_COEFFICIENTS_ARRAY_Table1XFilterCoefficientn2_start 0 static inline uint32_t ATTRIBUTE_PURE CHROMA_FILTER_COEFFICIENTS_ARRAY_Table1XFilterCoefficientn2_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CHROMA_FILTER_COEFFICIENTS_ARRAY::Table 1X Filter Coefficient[[n],3] */ #define GFX125_CHROMA_FILTER_COEFFICIENTS_ARRAY_Table1XFilterCoefficientn3_bits 8 #define GFX12_CHROMA_FILTER_COEFFICIENTS_ARRAY_Table1XFilterCoefficientn3_bits 8 #define GFX11_CHROMA_FILTER_COEFFICIENTS_ARRAY_Table1XFilterCoefficientn3_bits 8 static inline uint32_t ATTRIBUTE_PURE CHROMA_FILTER_COEFFICIENTS_ARRAY_Table1XFilterCoefficientn3_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CHROMA_FILTER_COEFFICIENTS_ARRAY_Table1XFilterCoefficientn3_start 16 #define GFX12_CHROMA_FILTER_COEFFICIENTS_ARRAY_Table1XFilterCoefficientn3_start 16 #define GFX11_CHROMA_FILTER_COEFFICIENTS_ARRAY_Table1XFilterCoefficientn3_start 16 static inline uint32_t ATTRIBUTE_PURE CHROMA_FILTER_COEFFICIENTS_ARRAY_Table1XFilterCoefficientn3_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CHROMA_FILTER_COEFFICIENTS_ARRAY::Table 1X Filter Coefficient[[n],4] */ #define GFX125_CHROMA_FILTER_COEFFICIENTS_ARRAY_Table1XFilterCoefficientn4_bits 8 #define GFX12_CHROMA_FILTER_COEFFICIENTS_ARRAY_Table1XFilterCoefficientn4_bits 8 #define GFX11_CHROMA_FILTER_COEFFICIENTS_ARRAY_Table1XFilterCoefficientn4_bits 8 static inline uint32_t ATTRIBUTE_PURE CHROMA_FILTER_COEFFICIENTS_ARRAY_Table1XFilterCoefficientn4_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CHROMA_FILTER_COEFFICIENTS_ARRAY_Table1XFilterCoefficientn4_start 32 #define GFX12_CHROMA_FILTER_COEFFICIENTS_ARRAY_Table1XFilterCoefficientn4_start 32 #define GFX11_CHROMA_FILTER_COEFFICIENTS_ARRAY_Table1XFilterCoefficientn4_start 32 static inline uint32_t ATTRIBUTE_PURE CHROMA_FILTER_COEFFICIENTS_ARRAY_Table1XFilterCoefficientn4_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CHROMA_FILTER_COEFFICIENTS_ARRAY::Table 1X Filter Coefficient[[n],5] */ #define GFX125_CHROMA_FILTER_COEFFICIENTS_ARRAY_Table1XFilterCoefficientn5_bits 8 #define GFX12_CHROMA_FILTER_COEFFICIENTS_ARRAY_Table1XFilterCoefficientn5_bits 8 #define GFX11_CHROMA_FILTER_COEFFICIENTS_ARRAY_Table1XFilterCoefficientn5_bits 8 static inline uint32_t ATTRIBUTE_PURE CHROMA_FILTER_COEFFICIENTS_ARRAY_Table1XFilterCoefficientn5_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CHROMA_FILTER_COEFFICIENTS_ARRAY_Table1XFilterCoefficientn5_start 48 #define GFX12_CHROMA_FILTER_COEFFICIENTS_ARRAY_Table1XFilterCoefficientn5_start 48 #define GFX11_CHROMA_FILTER_COEFFICIENTS_ARRAY_Table1XFilterCoefficientn5_start 48 static inline uint32_t ATTRIBUTE_PURE CHROMA_FILTER_COEFFICIENTS_ARRAY_Table1XFilterCoefficientn5_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 48; case 120: return 48; case 110: return 48; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CHROMA_FILTER_COEFFICIENTS_ARRAY::Table 1Y Filter Coefficient[[n],2] */ #define GFX125_CHROMA_FILTER_COEFFICIENTS_ARRAY_Table1YFilterCoefficientn2_bits 8 #define GFX12_CHROMA_FILTER_COEFFICIENTS_ARRAY_Table1YFilterCoefficientn2_bits 8 #define GFX11_CHROMA_FILTER_COEFFICIENTS_ARRAY_Table1YFilterCoefficientn2_bits 8 static inline uint32_t ATTRIBUTE_PURE CHROMA_FILTER_COEFFICIENTS_ARRAY_Table1YFilterCoefficientn2_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CHROMA_FILTER_COEFFICIENTS_ARRAY_Table1YFilterCoefficientn2_start 8 #define GFX12_CHROMA_FILTER_COEFFICIENTS_ARRAY_Table1YFilterCoefficientn2_start 8 #define GFX11_CHROMA_FILTER_COEFFICIENTS_ARRAY_Table1YFilterCoefficientn2_start 8 static inline uint32_t ATTRIBUTE_PURE CHROMA_FILTER_COEFFICIENTS_ARRAY_Table1YFilterCoefficientn2_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CHROMA_FILTER_COEFFICIENTS_ARRAY::Table 1Y Filter Coefficient[[n],3] */ #define GFX125_CHROMA_FILTER_COEFFICIENTS_ARRAY_Table1YFilterCoefficientn3_bits 8 #define GFX12_CHROMA_FILTER_COEFFICIENTS_ARRAY_Table1YFilterCoefficientn3_bits 8 #define GFX11_CHROMA_FILTER_COEFFICIENTS_ARRAY_Table1YFilterCoefficientn3_bits 8 static inline uint32_t ATTRIBUTE_PURE CHROMA_FILTER_COEFFICIENTS_ARRAY_Table1YFilterCoefficientn3_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CHROMA_FILTER_COEFFICIENTS_ARRAY_Table1YFilterCoefficientn3_start 24 #define GFX12_CHROMA_FILTER_COEFFICIENTS_ARRAY_Table1YFilterCoefficientn3_start 24 #define GFX11_CHROMA_FILTER_COEFFICIENTS_ARRAY_Table1YFilterCoefficientn3_start 24 static inline uint32_t ATTRIBUTE_PURE CHROMA_FILTER_COEFFICIENTS_ARRAY_Table1YFilterCoefficientn3_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CHROMA_FILTER_COEFFICIENTS_ARRAY::Table 1Y Filter Coefficient[[n],4] */ #define GFX125_CHROMA_FILTER_COEFFICIENTS_ARRAY_Table1YFilterCoefficientn4_bits 8 #define GFX12_CHROMA_FILTER_COEFFICIENTS_ARRAY_Table1YFilterCoefficientn4_bits 8 #define GFX11_CHROMA_FILTER_COEFFICIENTS_ARRAY_Table1YFilterCoefficientn4_bits 8 static inline uint32_t ATTRIBUTE_PURE CHROMA_FILTER_COEFFICIENTS_ARRAY_Table1YFilterCoefficientn4_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CHROMA_FILTER_COEFFICIENTS_ARRAY_Table1YFilterCoefficientn4_start 40 #define GFX12_CHROMA_FILTER_COEFFICIENTS_ARRAY_Table1YFilterCoefficientn4_start 40 #define GFX11_CHROMA_FILTER_COEFFICIENTS_ARRAY_Table1YFilterCoefficientn4_start 40 static inline uint32_t ATTRIBUTE_PURE CHROMA_FILTER_COEFFICIENTS_ARRAY_Table1YFilterCoefficientn4_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 40; case 120: return 40; case 110: return 40; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CHROMA_FILTER_COEFFICIENTS_ARRAY::Table 1Y Filter Coefficient[[n],5] */ #define GFX125_CHROMA_FILTER_COEFFICIENTS_ARRAY_Table1YFilterCoefficientn5_bits 8 #define GFX12_CHROMA_FILTER_COEFFICIENTS_ARRAY_Table1YFilterCoefficientn5_bits 8 #define GFX11_CHROMA_FILTER_COEFFICIENTS_ARRAY_Table1YFilterCoefficientn5_bits 8 static inline uint32_t ATTRIBUTE_PURE CHROMA_FILTER_COEFFICIENTS_ARRAY_Table1YFilterCoefficientn5_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CHROMA_FILTER_COEFFICIENTS_ARRAY_Table1YFilterCoefficientn5_start 56 #define GFX12_CHROMA_FILTER_COEFFICIENTS_ARRAY_Table1YFilterCoefficientn5_start 56 #define GFX11_CHROMA_FILTER_COEFFICIENTS_ARRAY_Table1YFilterCoefficientn5_start 56 static inline uint32_t ATTRIBUTE_PURE CHROMA_FILTER_COEFFICIENTS_ARRAY_Table1YFilterCoefficientn5_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 56; case 120: return 56; case 110: return 56; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CLEAR_COLOR */ #define GFX125_CLEAR_COLOR_length 8 #define GFX12_CLEAR_COLOR_length 8 #define GFX11_CLEAR_COLOR_length 8 static inline uint32_t ATTRIBUTE_PURE CLEAR_COLOR_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CLEAR_COLOR::Converted Clear Value Hi/Low */ #define GFX125_CLEAR_COLOR_ConvertedClearValueHiLow_bits 64 #define GFX12_CLEAR_COLOR_ConvertedClearValueHiLow_bits 64 #define GFX11_CLEAR_COLOR_ConvertedClearValueHiLow_bits 64 static inline uint32_t ATTRIBUTE_PURE CLEAR_COLOR_ConvertedClearValueHiLow_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CLEAR_COLOR_ConvertedClearValueHiLow_start 128 #define GFX12_CLEAR_COLOR_ConvertedClearValueHiLow_start 128 #define GFX11_CLEAR_COLOR_ConvertedClearValueHiLow_start 128 static inline uint32_t ATTRIBUTE_PURE CLEAR_COLOR_ConvertedClearValueHiLow_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 128; case 120: return 128; case 110: return 128; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CLEAR_COLOR::Raw Clear Color Alpha */ #define GFX125_CLEAR_COLOR_RawClearColorAlpha_bits 32 #define GFX12_CLEAR_COLOR_RawClearColorAlpha_bits 32 #define GFX11_CLEAR_COLOR_RawClearColorAlpha_bits 32 static inline uint32_t ATTRIBUTE_PURE CLEAR_COLOR_RawClearColorAlpha_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CLEAR_COLOR_RawClearColorAlpha_start 96 #define GFX12_CLEAR_COLOR_RawClearColorAlpha_start 96 #define GFX11_CLEAR_COLOR_RawClearColorAlpha_start 96 static inline uint32_t ATTRIBUTE_PURE CLEAR_COLOR_RawClearColorAlpha_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 96; case 120: return 96; case 110: return 96; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CLEAR_COLOR::Raw Clear Color Blue */ #define GFX125_CLEAR_COLOR_RawClearColorBlue_bits 32 #define GFX12_CLEAR_COLOR_RawClearColorBlue_bits 32 #define GFX11_CLEAR_COLOR_RawClearColorBlue_bits 32 static inline uint32_t ATTRIBUTE_PURE CLEAR_COLOR_RawClearColorBlue_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CLEAR_COLOR_RawClearColorBlue_start 64 #define GFX12_CLEAR_COLOR_RawClearColorBlue_start 64 #define GFX11_CLEAR_COLOR_RawClearColorBlue_start 64 static inline uint32_t ATTRIBUTE_PURE CLEAR_COLOR_RawClearColorBlue_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CLEAR_COLOR::Raw Clear Color Green */ #define GFX125_CLEAR_COLOR_RawClearColorGreen_bits 32 #define GFX12_CLEAR_COLOR_RawClearColorGreen_bits 32 #define GFX11_CLEAR_COLOR_RawClearColorGreen_bits 32 static inline uint32_t ATTRIBUTE_PURE CLEAR_COLOR_RawClearColorGreen_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CLEAR_COLOR_RawClearColorGreen_start 32 #define GFX12_CLEAR_COLOR_RawClearColorGreen_start 32 #define GFX11_CLEAR_COLOR_RawClearColorGreen_start 32 static inline uint32_t ATTRIBUTE_PURE CLEAR_COLOR_RawClearColorGreen_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CLEAR_COLOR::Raw Clear Color Red */ #define GFX125_CLEAR_COLOR_RawClearColorRed_bits 32 #define GFX12_CLEAR_COLOR_RawClearColorRed_bits 32 #define GFX11_CLEAR_COLOR_RawClearColorRed_bits 32 static inline uint32_t ATTRIBUTE_PURE CLEAR_COLOR_RawClearColorRed_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CLEAR_COLOR_RawClearColorRed_start 0 #define GFX12_CLEAR_COLOR_RawClearColorRed_start 0 #define GFX11_CLEAR_COLOR_RawClearColorRed_start 0 static inline uint32_t ATTRIBUTE_PURE CLEAR_COLOR_RawClearColorRed_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CLIP_STATE */ #define GFX5_CLIP_STATE_length 11 #define GFX45_CLIP_STATE_length 11 #define GFX4_CLIP_STATE_length 11 static inline uint32_t ATTRIBUTE_PURE CLIP_STATE_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 11; case 45: return 11; case 40: return 11; default: unreachable("Invalid hardware generation"); } } /* CLIP_STATE::API Mode */ #define GFX5_CLIP_STATE_APIMode_bits 1 #define GFX45_CLIP_STATE_APIMode_bits 1 #define GFX4_CLIP_STATE_APIMode_bits 1 static inline uint32_t ATTRIBUTE_PURE CLIP_STATE_APIMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_CLIP_STATE_APIMode_start 190 #define GFX45_CLIP_STATE_APIMode_start 190 #define GFX4_CLIP_STATE_APIMode_start 190 static inline uint32_t ATTRIBUTE_PURE CLIP_STATE_APIMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 190; case 45: return 190; case 40: return 190; default: unreachable("Invalid hardware generation"); } } /* CLIP_STATE::Binding Table Entry Count */ #define GFX5_CLIP_STATE_BindingTableEntryCount_bits 8 #define GFX45_CLIP_STATE_BindingTableEntryCount_bits 8 #define GFX4_CLIP_STATE_BindingTableEntryCount_bits 8 static inline uint32_t ATTRIBUTE_PURE CLIP_STATE_BindingTableEntryCount_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 8; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } #define GFX5_CLIP_STATE_BindingTableEntryCount_start 50 #define GFX45_CLIP_STATE_BindingTableEntryCount_start 50 #define GFX4_CLIP_STATE_BindingTableEntryCount_start 50 static inline uint32_t ATTRIBUTE_PURE CLIP_STATE_BindingTableEntryCount_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 50; case 45: return 50; case 40: return 50; default: unreachable("Invalid hardware generation"); } } /* CLIP_STATE::Clip Mode */ #define GFX5_CLIP_STATE_ClipMode_bits 3 #define GFX45_CLIP_STATE_ClipMode_bits 3 #define GFX4_CLIP_STATE_ClipMode_bits 3 static inline uint32_t ATTRIBUTE_PURE CLIP_STATE_ClipMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX5_CLIP_STATE_ClipMode_start 173 #define GFX45_CLIP_STATE_ClipMode_start 173 #define GFX4_CLIP_STATE_ClipMode_start 173 static inline uint32_t ATTRIBUTE_PURE CLIP_STATE_ClipMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 173; case 45: return 173; case 40: return 173; default: unreachable("Invalid hardware generation"); } } /* CLIP_STATE::Clipper Statistics Enable */ #define GFX45_CLIP_STATE_ClipperStatisticsEnable_bits 1 #define GFX4_CLIP_STATE_ClipperStatisticsEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE CLIP_STATE_ClipperStatisticsEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX45_CLIP_STATE_ClipperStatisticsEnable_start 138 #define GFX4_CLIP_STATE_ClipperStatisticsEnable_start 138 static inline uint32_t ATTRIBUTE_PURE CLIP_STATE_ClipperStatisticsEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 138; case 40: return 138; default: unreachable("Invalid hardware generation"); } } /* CLIP_STATE::Clipper Viewport State Pointer */ #define GFX5_CLIP_STATE_ClipperViewportStatePointer_bits 27 #define GFX45_CLIP_STATE_ClipperViewportStatePointer_bits 27 #define GFX4_CLIP_STATE_ClipperViewportStatePointer_bits 27 static inline uint32_t ATTRIBUTE_PURE CLIP_STATE_ClipperViewportStatePointer_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 27; case 45: return 27; case 40: return 27; default: unreachable("Invalid hardware generation"); } } #define GFX5_CLIP_STATE_ClipperViewportStatePointer_start 197 #define GFX45_CLIP_STATE_ClipperViewportStatePointer_start 197 #define GFX4_CLIP_STATE_ClipperViewportStatePointer_start 197 static inline uint32_t ATTRIBUTE_PURE CLIP_STATE_ClipperViewportStatePointer_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 197; case 45: return 197; case 40: return 197; default: unreachable("Invalid hardware generation"); } } /* CLIP_STATE::Constant URB Entry Read Length */ #define GFX5_CLIP_STATE_ConstantURBEntryReadLength_bits 6 #define GFX45_CLIP_STATE_ConstantURBEntryReadLength_bits 6 #define GFX4_CLIP_STATE_ConstantURBEntryReadLength_bits 6 static inline uint32_t ATTRIBUTE_PURE CLIP_STATE_ConstantURBEntryReadLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 6; case 45: return 6; case 40: return 6; default: unreachable("Invalid hardware generation"); } } #define GFX5_CLIP_STATE_ConstantURBEntryReadLength_start 121 #define GFX45_CLIP_STATE_ConstantURBEntryReadLength_start 121 #define GFX4_CLIP_STATE_ConstantURBEntryReadLength_start 121 static inline uint32_t ATTRIBUTE_PURE CLIP_STATE_ConstantURBEntryReadLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 121; case 45: return 121; case 40: return 121; default: unreachable("Invalid hardware generation"); } } /* CLIP_STATE::Constant URB Entry Read Offset */ #define GFX5_CLIP_STATE_ConstantURBEntryReadOffset_bits 6 #define GFX45_CLIP_STATE_ConstantURBEntryReadOffset_bits 6 #define GFX4_CLIP_STATE_ConstantURBEntryReadOffset_bits 6 static inline uint32_t ATTRIBUTE_PURE CLIP_STATE_ConstantURBEntryReadOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 6; case 45: return 6; case 40: return 6; default: unreachable("Invalid hardware generation"); } } #define GFX5_CLIP_STATE_ConstantURBEntryReadOffset_start 114 #define GFX45_CLIP_STATE_ConstantURBEntryReadOffset_start 114 #define GFX4_CLIP_STATE_ConstantURBEntryReadOffset_start 114 static inline uint32_t ATTRIBUTE_PURE CLIP_STATE_ConstantURBEntryReadOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 114; case 45: return 114; case 40: return 114; default: unreachable("Invalid hardware generation"); } } /* CLIP_STATE::Dispatch GRF Start Register For URB Data */ #define GFX5_CLIP_STATE_DispatchGRFStartRegisterForURBData_bits 4 #define GFX45_CLIP_STATE_DispatchGRFStartRegisterForURBData_bits 4 #define GFX4_CLIP_STATE_DispatchGRFStartRegisterForURBData_bits 4 static inline uint32_t ATTRIBUTE_PURE CLIP_STATE_DispatchGRFStartRegisterForURBData_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 4; case 45: return 4; case 40: return 4; default: unreachable("Invalid hardware generation"); } } #define GFX5_CLIP_STATE_DispatchGRFStartRegisterForURBData_start 96 #define GFX45_CLIP_STATE_DispatchGRFStartRegisterForURBData_start 96 #define GFX4_CLIP_STATE_DispatchGRFStartRegisterForURBData_start 96 static inline uint32_t ATTRIBUTE_PURE CLIP_STATE_DispatchGRFStartRegisterForURBData_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 96; case 45: return 96; case 40: return 96; default: unreachable("Invalid hardware generation"); } } /* CLIP_STATE::Floating Point Mode */ #define GFX5_CLIP_STATE_FloatingPointMode_bits 1 #define GFX45_CLIP_STATE_FloatingPointMode_bits 1 #define GFX4_CLIP_STATE_FloatingPointMode_bits 1 static inline uint32_t ATTRIBUTE_PURE CLIP_STATE_FloatingPointMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_CLIP_STATE_FloatingPointMode_start 48 #define GFX45_CLIP_STATE_FloatingPointMode_start 48 #define GFX4_CLIP_STATE_FloatingPointMode_start 48 static inline uint32_t ATTRIBUTE_PURE CLIP_STATE_FloatingPointMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 48; case 45: return 48; case 40: return 48; default: unreachable("Invalid hardware generation"); } } /* CLIP_STATE::GRF Register Count */ #define GFX5_CLIP_STATE_GRFRegisterCount_bits 3 #define GFX45_CLIP_STATE_GRFRegisterCount_bits 3 #define GFX4_CLIP_STATE_GRFRegisterCount_bits 3 static inline uint32_t ATTRIBUTE_PURE CLIP_STATE_GRFRegisterCount_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX5_CLIP_STATE_GRFRegisterCount_start 1 #define GFX45_CLIP_STATE_GRFRegisterCount_start 1 #define GFX4_CLIP_STATE_GRFRegisterCount_start 1 static inline uint32_t ATTRIBUTE_PURE CLIP_STATE_GRFRegisterCount_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } /* CLIP_STATE::GS Output Object Statistics Enable */ #define GFX45_CLIP_STATE_GSOutputObjectStatisticsEnable_bits 1 #define GFX4_CLIP_STATE_GSOutputObjectStatisticsEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE CLIP_STATE_GSOutputObjectStatisticsEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX45_CLIP_STATE_GSOutputObjectStatisticsEnable_start 138 #define GFX4_CLIP_STATE_GSOutputObjectStatisticsEnable_start 138 static inline uint32_t ATTRIBUTE_PURE CLIP_STATE_GSOutputObjectStatisticsEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 138; case 40: return 138; default: unreachable("Invalid hardware generation"); } } /* CLIP_STATE::Guardband ClipTest Enable */ #define GFX5_CLIP_STATE_GuardbandClipTestEnable_bits 1 #define GFX45_CLIP_STATE_GuardbandClipTestEnable_bits 1 #define GFX4_CLIP_STATE_GuardbandClipTestEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE CLIP_STATE_GuardbandClipTestEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_CLIP_STATE_GuardbandClipTestEnable_start 186 #define GFX45_CLIP_STATE_GuardbandClipTestEnable_start 186 #define GFX4_CLIP_STATE_GuardbandClipTestEnable_start 186 static inline uint32_t ATTRIBUTE_PURE CLIP_STATE_GuardbandClipTestEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 186; case 45: return 186; case 40: return 186; default: unreachable("Invalid hardware generation"); } } /* CLIP_STATE::Illegal Opcode Exception Enable */ #define GFX5_CLIP_STATE_IllegalOpcodeExceptionEnable_bits 1 #define GFX45_CLIP_STATE_IllegalOpcodeExceptionEnable_bits 1 #define GFX4_CLIP_STATE_IllegalOpcodeExceptionEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE CLIP_STATE_IllegalOpcodeExceptionEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_CLIP_STATE_IllegalOpcodeExceptionEnable_start 45 #define GFX45_CLIP_STATE_IllegalOpcodeExceptionEnable_start 45 #define GFX4_CLIP_STATE_IllegalOpcodeExceptionEnable_start 45 static inline uint32_t ATTRIBUTE_PURE CLIP_STATE_IllegalOpcodeExceptionEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 45; case 45: return 45; case 40: return 45; default: unreachable("Invalid hardware generation"); } } /* CLIP_STATE::Kernel Start Pointer */ #define GFX5_CLIP_STATE_KernelStartPointer_bits 26 #define GFX45_CLIP_STATE_KernelStartPointer_bits 26 #define GFX4_CLIP_STATE_KernelStartPointer_bits 26 static inline uint32_t ATTRIBUTE_PURE CLIP_STATE_KernelStartPointer_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 26; case 45: return 26; case 40: return 26; default: unreachable("Invalid hardware generation"); } } #define GFX5_CLIP_STATE_KernelStartPointer_start 6 #define GFX45_CLIP_STATE_KernelStartPointer_start 6 #define GFX4_CLIP_STATE_KernelStartPointer_start 6 static inline uint32_t ATTRIBUTE_PURE CLIP_STATE_KernelStartPointer_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 6; case 45: return 6; case 40: return 6; default: unreachable("Invalid hardware generation"); } } /* CLIP_STATE::Mask Stack Exception Enable */ #define GFX5_CLIP_STATE_MaskStackExceptionEnable_bits 1 #define GFX45_CLIP_STATE_MaskStackExceptionEnable_bits 1 #define GFX4_CLIP_STATE_MaskStackExceptionEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE CLIP_STATE_MaskStackExceptionEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_CLIP_STATE_MaskStackExceptionEnable_start 43 #define GFX45_CLIP_STATE_MaskStackExceptionEnable_start 43 #define GFX4_CLIP_STATE_MaskStackExceptionEnable_start 43 static inline uint32_t ATTRIBUTE_PURE CLIP_STATE_MaskStackExceptionEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 43; case 45: return 43; case 40: return 43; default: unreachable("Invalid hardware generation"); } } /* CLIP_STATE::Maximum Number of Threads */ #define GFX5_CLIP_STATE_MaximumNumberofThreads_bits 6 #define GFX45_CLIP_STATE_MaximumNumberofThreads_bits 6 #define GFX4_CLIP_STATE_MaximumNumberofThreads_bits 6 static inline uint32_t ATTRIBUTE_PURE CLIP_STATE_MaximumNumberofThreads_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 6; case 45: return 6; case 40: return 6; default: unreachable("Invalid hardware generation"); } } #define GFX5_CLIP_STATE_MaximumNumberofThreads_start 153 #define GFX45_CLIP_STATE_MaximumNumberofThreads_start 153 #define GFX4_CLIP_STATE_MaximumNumberofThreads_start 153 static inline uint32_t ATTRIBUTE_PURE CLIP_STATE_MaximumNumberofThreads_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 153; case 45: return 153; case 40: return 153; default: unreachable("Invalid hardware generation"); } } /* CLIP_STATE::Negative W ClipTest Enable */ #define GFX5_CLIP_STATE_NegativeWClipTestEnable_bits 1 #define GFX45_CLIP_STATE_NegativeWClipTestEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE CLIP_STATE_NegativeWClipTestEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX5_CLIP_STATE_NegativeWClipTestEnable_start 185 #define GFX45_CLIP_STATE_NegativeWClipTestEnable_start 185 static inline uint32_t ATTRIBUTE_PURE CLIP_STATE_NegativeWClipTestEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 185; case 45: return 185; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CLIP_STATE::Number of URB Entries */ #define GFX5_CLIP_STATE_NumberofURBEntries_bits 8 #define GFX45_CLIP_STATE_NumberofURBEntries_bits 8 #define GFX4_CLIP_STATE_NumberofURBEntries_bits 8 static inline uint32_t ATTRIBUTE_PURE CLIP_STATE_NumberofURBEntries_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 8; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } #define GFX5_CLIP_STATE_NumberofURBEntries_start 139 #define GFX45_CLIP_STATE_NumberofURBEntries_start 139 #define GFX4_CLIP_STATE_NumberofURBEntries_start 139 static inline uint32_t ATTRIBUTE_PURE CLIP_STATE_NumberofURBEntries_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 139; case 45: return 139; case 40: return 139; default: unreachable("Invalid hardware generation"); } } /* CLIP_STATE::Per-Thread Scratch Space */ #define GFX5_CLIP_STATE_PerThreadScratchSpace_bits 4 #define GFX45_CLIP_STATE_PerThreadScratchSpace_bits 4 #define GFX4_CLIP_STATE_PerThreadScratchSpace_bits 4 static inline uint32_t ATTRIBUTE_PURE CLIP_STATE_PerThreadScratchSpace_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 4; case 45: return 4; case 40: return 4; default: unreachable("Invalid hardware generation"); } } #define GFX5_CLIP_STATE_PerThreadScratchSpace_start 64 #define GFX45_CLIP_STATE_PerThreadScratchSpace_start 64 #define GFX4_CLIP_STATE_PerThreadScratchSpace_start 64 static inline uint32_t ATTRIBUTE_PURE CLIP_STATE_PerThreadScratchSpace_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 64; case 45: return 64; case 40: return 64; default: unreachable("Invalid hardware generation"); } } /* CLIP_STATE::Scratch Space Base Pointer */ #define GFX5_CLIP_STATE_ScratchSpaceBasePointer_bits 22 #define GFX45_CLIP_STATE_ScratchSpaceBasePointer_bits 22 #define GFX4_CLIP_STATE_ScratchSpaceBasePointer_bits 22 static inline uint32_t ATTRIBUTE_PURE CLIP_STATE_ScratchSpaceBasePointer_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 22; case 45: return 22; case 40: return 22; default: unreachable("Invalid hardware generation"); } } #define GFX5_CLIP_STATE_ScratchSpaceBasePointer_start 74 #define GFX45_CLIP_STATE_ScratchSpaceBasePointer_start 74 #define GFX4_CLIP_STATE_ScratchSpaceBasePointer_start 74 static inline uint32_t ATTRIBUTE_PURE CLIP_STATE_ScratchSpaceBasePointer_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 74; case 45: return 74; case 40: return 74; default: unreachable("Invalid hardware generation"); } } /* CLIP_STATE::Screen Space Viewport X Max */ #define GFX5_CLIP_STATE_ScreenSpaceViewportXMax_bits 32 #define GFX45_CLIP_STATE_ScreenSpaceViewportXMax_bits 32 #define GFX4_CLIP_STATE_ScreenSpaceViewportXMax_bits 32 static inline uint32_t ATTRIBUTE_PURE CLIP_STATE_ScreenSpaceViewportXMax_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 32; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } #define GFX5_CLIP_STATE_ScreenSpaceViewportXMax_start 256 #define GFX45_CLIP_STATE_ScreenSpaceViewportXMax_start 256 #define GFX4_CLIP_STATE_ScreenSpaceViewportXMax_start 256 static inline uint32_t ATTRIBUTE_PURE CLIP_STATE_ScreenSpaceViewportXMax_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 256; case 45: return 256; case 40: return 256; default: unreachable("Invalid hardware generation"); } } /* CLIP_STATE::Screen Space Viewport X Min */ #define GFX5_CLIP_STATE_ScreenSpaceViewportXMin_bits 32 #define GFX45_CLIP_STATE_ScreenSpaceViewportXMin_bits 32 #define GFX4_CLIP_STATE_ScreenSpaceViewportXMin_bits 32 static inline uint32_t ATTRIBUTE_PURE CLIP_STATE_ScreenSpaceViewportXMin_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 32; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } #define GFX5_CLIP_STATE_ScreenSpaceViewportXMin_start 224 #define GFX45_CLIP_STATE_ScreenSpaceViewportXMin_start 224 #define GFX4_CLIP_STATE_ScreenSpaceViewportXMin_start 224 static inline uint32_t ATTRIBUTE_PURE CLIP_STATE_ScreenSpaceViewportXMin_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 224; case 45: return 224; case 40: return 224; default: unreachable("Invalid hardware generation"); } } /* CLIP_STATE::Screen Space Viewport Y Max */ #define GFX5_CLIP_STATE_ScreenSpaceViewportYMax_bits 32 #define GFX45_CLIP_STATE_ScreenSpaceViewportYMax_bits 32 #define GFX4_CLIP_STATE_ScreenSpaceViewportYMax_bits 32 static inline uint32_t ATTRIBUTE_PURE CLIP_STATE_ScreenSpaceViewportYMax_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 32; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } #define GFX5_CLIP_STATE_ScreenSpaceViewportYMax_start 320 #define GFX45_CLIP_STATE_ScreenSpaceViewportYMax_start 320 #define GFX4_CLIP_STATE_ScreenSpaceViewportYMax_start 320 static inline uint32_t ATTRIBUTE_PURE CLIP_STATE_ScreenSpaceViewportYMax_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 320; case 45: return 320; case 40: return 320; default: unreachable("Invalid hardware generation"); } } /* CLIP_STATE::Screen Space Viewport Y Min */ #define GFX5_CLIP_STATE_ScreenSpaceViewportYMin_bits 32 #define GFX45_CLIP_STATE_ScreenSpaceViewportYMin_bits 32 #define GFX4_CLIP_STATE_ScreenSpaceViewportYMin_bits 32 static inline uint32_t ATTRIBUTE_PURE CLIP_STATE_ScreenSpaceViewportYMin_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 32; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } #define GFX5_CLIP_STATE_ScreenSpaceViewportYMin_start 288 #define GFX45_CLIP_STATE_ScreenSpaceViewportYMin_start 288 #define GFX4_CLIP_STATE_ScreenSpaceViewportYMin_start 288 static inline uint32_t ATTRIBUTE_PURE CLIP_STATE_ScreenSpaceViewportYMin_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 288; case 45: return 288; case 40: return 288; default: unreachable("Invalid hardware generation"); } } /* CLIP_STATE::Single Program Flow */ #define GFX5_CLIP_STATE_SingleProgramFlow_bits 1 #define GFX45_CLIP_STATE_SingleProgramFlow_bits 1 #define GFX4_CLIP_STATE_SingleProgramFlow_bits 1 static inline uint32_t ATTRIBUTE_PURE CLIP_STATE_SingleProgramFlow_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_CLIP_STATE_SingleProgramFlow_start 63 #define GFX45_CLIP_STATE_SingleProgramFlow_start 63 #define GFX4_CLIP_STATE_SingleProgramFlow_start 63 static inline uint32_t ATTRIBUTE_PURE CLIP_STATE_SingleProgramFlow_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 63; case 45: return 63; case 40: return 63; default: unreachable("Invalid hardware generation"); } } /* CLIP_STATE::Software Exception Enable */ #define GFX5_CLIP_STATE_SoftwareExceptionEnable_bits 1 #define GFX45_CLIP_STATE_SoftwareExceptionEnable_bits 1 #define GFX4_CLIP_STATE_SoftwareExceptionEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE CLIP_STATE_SoftwareExceptionEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_CLIP_STATE_SoftwareExceptionEnable_start 39 #define GFX45_CLIP_STATE_SoftwareExceptionEnable_start 39 #define GFX4_CLIP_STATE_SoftwareExceptionEnable_start 39 static inline uint32_t ATTRIBUTE_PURE CLIP_STATE_SoftwareExceptionEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 39; case 45: return 39; case 40: return 39; default: unreachable("Invalid hardware generation"); } } /* CLIP_STATE::Thread Priority */ #define GFX5_CLIP_STATE_ThreadPriority_bits 1 #define GFX45_CLIP_STATE_ThreadPriority_bits 1 #define GFX4_CLIP_STATE_ThreadPriority_bits 1 static inline uint32_t ATTRIBUTE_PURE CLIP_STATE_ThreadPriority_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_CLIP_STATE_ThreadPriority_start 49 #define GFX45_CLIP_STATE_ThreadPriority_start 49 #define GFX4_CLIP_STATE_ThreadPriority_start 49 static inline uint32_t ATTRIBUTE_PURE CLIP_STATE_ThreadPriority_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 49; case 45: return 49; case 40: return 49; default: unreachable("Invalid hardware generation"); } } /* CLIP_STATE::URB Entry Allocation Size */ #define GFX5_CLIP_STATE_URBEntryAllocationSize_bits 5 #define GFX45_CLIP_STATE_URBEntryAllocationSize_bits 5 #define GFX4_CLIP_STATE_URBEntryAllocationSize_bits 5 static inline uint32_t ATTRIBUTE_PURE CLIP_STATE_URBEntryAllocationSize_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 5; case 45: return 5; case 40: return 5; default: unreachable("Invalid hardware generation"); } } #define GFX5_CLIP_STATE_URBEntryAllocationSize_start 147 #define GFX45_CLIP_STATE_URBEntryAllocationSize_start 147 #define GFX4_CLIP_STATE_URBEntryAllocationSize_start 147 static inline uint32_t ATTRIBUTE_PURE CLIP_STATE_URBEntryAllocationSize_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 147; case 45: return 147; case 40: return 147; default: unreachable("Invalid hardware generation"); } } /* CLIP_STATE::UserClipDistance ClipTest Enable Bitmask */ #define GFX5_CLIP_STATE_UserClipDistanceClipTestEnableBitmask_bits 8 #define GFX45_CLIP_STATE_UserClipDistanceClipTestEnableBitmask_bits 8 #define GFX4_CLIP_STATE_UserClipDistanceClipTestEnableBitmask_bits 8 static inline uint32_t ATTRIBUTE_PURE CLIP_STATE_UserClipDistanceClipTestEnableBitmask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 8; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } #define GFX5_CLIP_STATE_UserClipDistanceClipTestEnableBitmask_start 176 #define GFX45_CLIP_STATE_UserClipDistanceClipTestEnableBitmask_start 176 #define GFX4_CLIP_STATE_UserClipDistanceClipTestEnableBitmask_start 176 static inline uint32_t ATTRIBUTE_PURE CLIP_STATE_UserClipDistanceClipTestEnableBitmask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 176; case 45: return 176; case 40: return 176; default: unreachable("Invalid hardware generation"); } } /* CLIP_STATE::UserClipFlags MustClip Enable */ #define GFX5_CLIP_STATE_UserClipFlagsMustClipEnable_bits 1 #define GFX45_CLIP_STATE_UserClipFlagsMustClipEnable_bits 1 #define GFX4_CLIP_STATE_UserClipFlagsMustClipEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE CLIP_STATE_UserClipFlagsMustClipEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_CLIP_STATE_UserClipFlagsMustClipEnable_start 184 #define GFX45_CLIP_STATE_UserClipFlagsMustClipEnable_start 184 #define GFX4_CLIP_STATE_UserClipFlagsMustClipEnable_start 184 static inline uint32_t ATTRIBUTE_PURE CLIP_STATE_UserClipFlagsMustClipEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 184; case 45: return 184; case 40: return 184; default: unreachable("Invalid hardware generation"); } } /* CLIP_STATE::Vertex Position Space */ #define GFX5_CLIP_STATE_VertexPositionSpace_bits 1 #define GFX45_CLIP_STATE_VertexPositionSpace_bits 1 #define GFX4_CLIP_STATE_VertexPositionSpace_bits 1 static inline uint32_t ATTRIBUTE_PURE CLIP_STATE_VertexPositionSpace_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_CLIP_STATE_VertexPositionSpace_start 189 #define GFX45_CLIP_STATE_VertexPositionSpace_start 189 #define GFX4_CLIP_STATE_VertexPositionSpace_start 189 static inline uint32_t ATTRIBUTE_PURE CLIP_STATE_VertexPositionSpace_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 189; case 45: return 189; case 40: return 189; default: unreachable("Invalid hardware generation"); } } /* CLIP_STATE::Vertex URB Entry Read Length */ #define GFX5_CLIP_STATE_VertexURBEntryReadLength_bits 6 #define GFX45_CLIP_STATE_VertexURBEntryReadLength_bits 6 #define GFX4_CLIP_STATE_VertexURBEntryReadLength_bits 6 static inline uint32_t ATTRIBUTE_PURE CLIP_STATE_VertexURBEntryReadLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 6; case 45: return 6; case 40: return 6; default: unreachable("Invalid hardware generation"); } } #define GFX5_CLIP_STATE_VertexURBEntryReadLength_start 107 #define GFX45_CLIP_STATE_VertexURBEntryReadLength_start 107 #define GFX4_CLIP_STATE_VertexURBEntryReadLength_start 107 static inline uint32_t ATTRIBUTE_PURE CLIP_STATE_VertexURBEntryReadLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 107; case 45: return 107; case 40: return 107; default: unreachable("Invalid hardware generation"); } } /* CLIP_STATE::Vertex URB Entry Read Offset */ #define GFX5_CLIP_STATE_VertexURBEntryReadOffset_bits 6 #define GFX45_CLIP_STATE_VertexURBEntryReadOffset_bits 6 #define GFX4_CLIP_STATE_VertexURBEntryReadOffset_bits 6 static inline uint32_t ATTRIBUTE_PURE CLIP_STATE_VertexURBEntryReadOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 6; case 45: return 6; case 40: return 6; default: unreachable("Invalid hardware generation"); } } #define GFX5_CLIP_STATE_VertexURBEntryReadOffset_start 100 #define GFX45_CLIP_STATE_VertexURBEntryReadOffset_start 100 #define GFX4_CLIP_STATE_VertexURBEntryReadOffset_start 100 static inline uint32_t ATTRIBUTE_PURE CLIP_STATE_VertexURBEntryReadOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 100; case 45: return 100; case 40: return 100; default: unreachable("Invalid hardware generation"); } } /* CLIP_STATE::Viewport XY ClipTest Enable */ #define GFX5_CLIP_STATE_ViewportXYClipTestEnable_bits 1 #define GFX45_CLIP_STATE_ViewportXYClipTestEnable_bits 1 #define GFX4_CLIP_STATE_ViewportXYClipTestEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE CLIP_STATE_ViewportXYClipTestEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_CLIP_STATE_ViewportXYClipTestEnable_start 188 #define GFX45_CLIP_STATE_ViewportXYClipTestEnable_start 188 #define GFX4_CLIP_STATE_ViewportXYClipTestEnable_start 188 static inline uint32_t ATTRIBUTE_PURE CLIP_STATE_ViewportXYClipTestEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 188; case 45: return 188; case 40: return 188; default: unreachable("Invalid hardware generation"); } } /* CLIP_STATE::Viewport Z ClipTest Enable */ #define GFX5_CLIP_STATE_ViewportZClipTestEnable_bits 1 #define GFX45_CLIP_STATE_ViewportZClipTestEnable_bits 1 #define GFX4_CLIP_STATE_ViewportZClipTestEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE CLIP_STATE_ViewportZClipTestEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_CLIP_STATE_ViewportZClipTestEnable_start 187 #define GFX45_CLIP_STATE_ViewportZClipTestEnable_start 187 #define GFX4_CLIP_STATE_ViewportZClipTestEnable_start 187 static inline uint32_t ATTRIBUTE_PURE CLIP_STATE_ViewportZClipTestEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 187; case 45: return 187; case 40: return 187; default: unreachable("Invalid hardware generation"); } } /* CLIP_VIEWPORT */ #define GFX6_CLIP_VIEWPORT_length 4 #define GFX5_CLIP_VIEWPORT_length 4 #define GFX45_CLIP_VIEWPORT_length 4 #define GFX4_CLIP_VIEWPORT_length 4 static inline uint32_t ATTRIBUTE_PURE CLIP_VIEWPORT_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 4; case 50: return 4; case 45: return 4; case 40: return 4; default: unreachable("Invalid hardware generation"); } } /* CLIP_VIEWPORT::XMax Clip Guardband */ #define GFX6_CLIP_VIEWPORT_XMaxClipGuardband_bits 32 #define GFX5_CLIP_VIEWPORT_XMaxClipGuardband_bits 32 #define GFX45_CLIP_VIEWPORT_XMaxClipGuardband_bits 32 #define GFX4_CLIP_VIEWPORT_XMaxClipGuardband_bits 32 static inline uint32_t ATTRIBUTE_PURE CLIP_VIEWPORT_XMaxClipGuardband_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 32; case 50: return 32; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } #define GFX6_CLIP_VIEWPORT_XMaxClipGuardband_start 32 #define GFX5_CLIP_VIEWPORT_XMaxClipGuardband_start 32 #define GFX45_CLIP_VIEWPORT_XMaxClipGuardband_start 32 #define GFX4_CLIP_VIEWPORT_XMaxClipGuardband_start 32 static inline uint32_t ATTRIBUTE_PURE CLIP_VIEWPORT_XMaxClipGuardband_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 32; case 50: return 32; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } /* CLIP_VIEWPORT::XMin Clip Guardband */ #define GFX6_CLIP_VIEWPORT_XMinClipGuardband_bits 32 #define GFX5_CLIP_VIEWPORT_XMinClipGuardband_bits 32 #define GFX45_CLIP_VIEWPORT_XMinClipGuardband_bits 32 #define GFX4_CLIP_VIEWPORT_XMinClipGuardband_bits 32 static inline uint32_t ATTRIBUTE_PURE CLIP_VIEWPORT_XMinClipGuardband_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 32; case 50: return 32; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } #define GFX6_CLIP_VIEWPORT_XMinClipGuardband_start 0 #define GFX5_CLIP_VIEWPORT_XMinClipGuardband_start 0 #define GFX45_CLIP_VIEWPORT_XMinClipGuardband_start 0 #define GFX4_CLIP_VIEWPORT_XMinClipGuardband_start 0 static inline uint32_t ATTRIBUTE_PURE CLIP_VIEWPORT_XMinClipGuardband_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CLIP_VIEWPORT::YMax Clip Guardband */ #define GFX6_CLIP_VIEWPORT_YMaxClipGuardband_bits 32 #define GFX5_CLIP_VIEWPORT_YMaxClipGuardband_bits 32 #define GFX45_CLIP_VIEWPORT_YMaxClipGuardband_bits 32 #define GFX4_CLIP_VIEWPORT_YMaxClipGuardband_bits 32 static inline uint32_t ATTRIBUTE_PURE CLIP_VIEWPORT_YMaxClipGuardband_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 32; case 50: return 32; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } #define GFX6_CLIP_VIEWPORT_YMaxClipGuardband_start 96 #define GFX5_CLIP_VIEWPORT_YMaxClipGuardband_start 96 #define GFX45_CLIP_VIEWPORT_YMaxClipGuardband_start 96 #define GFX4_CLIP_VIEWPORT_YMaxClipGuardband_start 96 static inline uint32_t ATTRIBUTE_PURE CLIP_VIEWPORT_YMaxClipGuardband_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 96; case 50: return 96; case 45: return 96; case 40: return 96; default: unreachable("Invalid hardware generation"); } } /* CLIP_VIEWPORT::YMin Clip Guardband */ #define GFX6_CLIP_VIEWPORT_YMinClipGuardband_bits 32 #define GFX5_CLIP_VIEWPORT_YMinClipGuardband_bits 32 #define GFX45_CLIP_VIEWPORT_YMinClipGuardband_bits 32 #define GFX4_CLIP_VIEWPORT_YMinClipGuardband_bits 32 static inline uint32_t ATTRIBUTE_PURE CLIP_VIEWPORT_YMinClipGuardband_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 32; case 50: return 32; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } #define GFX6_CLIP_VIEWPORT_YMinClipGuardband_start 64 #define GFX5_CLIP_VIEWPORT_YMinClipGuardband_start 64 #define GFX45_CLIP_VIEWPORT_YMinClipGuardband_start 64 #define GFX4_CLIP_VIEWPORT_YMinClipGuardband_start 64 static inline uint32_t ATTRIBUTE_PURE CLIP_VIEWPORT_YMinClipGuardband_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 64; case 50: return 64; case 45: return 64; case 40: return 64; default: unreachable("Invalid hardware generation"); } } /* CL_INVOCATION_COUNT */ #define GFX125_CL_INVOCATION_COUNT_length 2 #define GFX12_CL_INVOCATION_COUNT_length 2 #define GFX11_CL_INVOCATION_COUNT_length 2 #define GFX9_CL_INVOCATION_COUNT_length 2 #define GFX8_CL_INVOCATION_COUNT_length 2 #define GFX75_CL_INVOCATION_COUNT_length 2 #define GFX7_CL_INVOCATION_COUNT_length 2 static inline uint32_t ATTRIBUTE_PURE CL_INVOCATION_COUNT_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CL_INVOCATION_COUNT::CL Invocation Count Report */ #define GFX125_CL_INVOCATION_COUNT_CLInvocationCountReport_bits 64 #define GFX12_CL_INVOCATION_COUNT_CLInvocationCountReport_bits 64 #define GFX11_CL_INVOCATION_COUNT_CLInvocationCountReport_bits 64 #define GFX9_CL_INVOCATION_COUNT_CLInvocationCountReport_bits 64 #define GFX8_CL_INVOCATION_COUNT_CLInvocationCountReport_bits 64 #define GFX75_CL_INVOCATION_COUNT_CLInvocationCountReport_bits 64 #define GFX7_CL_INVOCATION_COUNT_CLInvocationCountReport_bits 64 static inline uint32_t ATTRIBUTE_PURE CL_INVOCATION_COUNT_CLInvocationCountReport_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 64; case 80: return 64; case 75: return 64; case 70: return 64; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CL_INVOCATION_COUNT_CLInvocationCountReport_start 0 #define GFX12_CL_INVOCATION_COUNT_CLInvocationCountReport_start 0 #define GFX11_CL_INVOCATION_COUNT_CLInvocationCountReport_start 0 #define GFX9_CL_INVOCATION_COUNT_CLInvocationCountReport_start 0 #define GFX8_CL_INVOCATION_COUNT_CLInvocationCountReport_start 0 #define GFX75_CL_INVOCATION_COUNT_CLInvocationCountReport_start 0 #define GFX7_CL_INVOCATION_COUNT_CLInvocationCountReport_start 0 static inline uint32_t ATTRIBUTE_PURE CL_INVOCATION_COUNT_CLInvocationCountReport_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CL_PRIMITIVES_COUNT */ #define GFX125_CL_PRIMITIVES_COUNT_length 2 #define GFX12_CL_PRIMITIVES_COUNT_length 2 #define GFX11_CL_PRIMITIVES_COUNT_length 2 #define GFX9_CL_PRIMITIVES_COUNT_length 2 #define GFX8_CL_PRIMITIVES_COUNT_length 2 #define GFX75_CL_PRIMITIVES_COUNT_length 2 #define GFX7_CL_PRIMITIVES_COUNT_length 2 static inline uint32_t ATTRIBUTE_PURE CL_PRIMITIVES_COUNT_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CL_PRIMITIVES_COUNT::CL Primitives Count Report */ #define GFX125_CL_PRIMITIVES_COUNT_CLPrimitivesCountReport_bits 64 #define GFX12_CL_PRIMITIVES_COUNT_CLPrimitivesCountReport_bits 64 #define GFX11_CL_PRIMITIVES_COUNT_CLPrimitivesCountReport_bits 64 #define GFX9_CL_PRIMITIVES_COUNT_CLPrimitivesCountReport_bits 64 #define GFX8_CL_PRIMITIVES_COUNT_CLPrimitivesCountReport_bits 64 #define GFX75_CL_PRIMITIVES_COUNT_CLPrimitivesCountReport_bits 64 #define GFX7_CL_PRIMITIVES_COUNT_CLPrimitivesCountReport_bits 64 static inline uint32_t ATTRIBUTE_PURE CL_PRIMITIVES_COUNT_CLPrimitivesCountReport_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 64; case 80: return 64; case 75: return 64; case 70: return 64; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CL_PRIMITIVES_COUNT_CLPrimitivesCountReport_start 0 #define GFX12_CL_PRIMITIVES_COUNT_CLPrimitivesCountReport_start 0 #define GFX11_CL_PRIMITIVES_COUNT_CLPrimitivesCountReport_start 0 #define GFX9_CL_PRIMITIVES_COUNT_CLPrimitivesCountReport_start 0 #define GFX8_CL_PRIMITIVES_COUNT_CLPrimitivesCountReport_start 0 #define GFX75_CL_PRIMITIVES_COUNT_CLPrimitivesCountReport_start 0 #define GFX7_CL_PRIMITIVES_COUNT_CLPrimitivesCountReport_start 0 static inline uint32_t ATTRIBUTE_PURE CL_PRIMITIVES_COUNT_CLPrimitivesCountReport_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* COLOR_CALC_STATE */ #define GFX125_COLOR_CALC_STATE_length 6 #define GFX12_COLOR_CALC_STATE_length 6 #define GFX11_COLOR_CALC_STATE_length 6 #define GFX9_COLOR_CALC_STATE_length 6 #define GFX8_COLOR_CALC_STATE_length 6 #define GFX75_COLOR_CALC_STATE_length 6 #define GFX7_COLOR_CALC_STATE_length 6 #define GFX6_COLOR_CALC_STATE_length 6 #define GFX5_COLOR_CALC_STATE_length 8 #define GFX45_COLOR_CALC_STATE_length 8 #define GFX4_COLOR_CALC_STATE_length 8 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 6; case 60: return 6; case 50: return 8; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } /* COLOR_CALC_STATE::Alpha Blend Function */ #define GFX5_COLOR_CALC_STATE_AlphaBlendFunction_bits 3 #define GFX45_COLOR_CALC_STATE_AlphaBlendFunction_bits 3 #define GFX4_COLOR_CALC_STATE_AlphaBlendFunction_bits 3 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_AlphaBlendFunction_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX5_COLOR_CALC_STATE_AlphaBlendFunction_start 172 #define GFX45_COLOR_CALC_STATE_AlphaBlendFunction_start 172 #define GFX4_COLOR_CALC_STATE_AlphaBlendFunction_start 172 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_AlphaBlendFunction_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 172; case 45: return 172; case 40: return 172; default: unreachable("Invalid hardware generation"); } } /* COLOR_CALC_STATE::Alpha Reference Value As FLOAT32 */ #define GFX125_COLOR_CALC_STATE_AlphaReferenceValueAsFLOAT32_bits 32 #define GFX12_COLOR_CALC_STATE_AlphaReferenceValueAsFLOAT32_bits 32 #define GFX11_COLOR_CALC_STATE_AlphaReferenceValueAsFLOAT32_bits 32 #define GFX9_COLOR_CALC_STATE_AlphaReferenceValueAsFLOAT32_bits 32 #define GFX8_COLOR_CALC_STATE_AlphaReferenceValueAsFLOAT32_bits 32 #define GFX75_COLOR_CALC_STATE_AlphaReferenceValueAsFLOAT32_bits 32 #define GFX7_COLOR_CALC_STATE_AlphaReferenceValueAsFLOAT32_bits 32 #define GFX6_COLOR_CALC_STATE_AlphaReferenceValueAsFLOAT32_bits 32 #define GFX5_COLOR_CALC_STATE_AlphaReferenceValueAsFLOAT32_bits 32 #define GFX45_COLOR_CALC_STATE_AlphaReferenceValueAsFLOAT32_bits 32 #define GFX4_COLOR_CALC_STATE_AlphaReferenceValueAsFLOAT32_bits 32 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_AlphaReferenceValueAsFLOAT32_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 32; case 50: return 32; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } #define GFX125_COLOR_CALC_STATE_AlphaReferenceValueAsFLOAT32_start 32 #define GFX12_COLOR_CALC_STATE_AlphaReferenceValueAsFLOAT32_start 32 #define GFX11_COLOR_CALC_STATE_AlphaReferenceValueAsFLOAT32_start 32 #define GFX9_COLOR_CALC_STATE_AlphaReferenceValueAsFLOAT32_start 32 #define GFX8_COLOR_CALC_STATE_AlphaReferenceValueAsFLOAT32_start 32 #define GFX75_COLOR_CALC_STATE_AlphaReferenceValueAsFLOAT32_start 32 #define GFX7_COLOR_CALC_STATE_AlphaReferenceValueAsFLOAT32_start 32 #define GFX6_COLOR_CALC_STATE_AlphaReferenceValueAsFLOAT32_start 32 #define GFX5_COLOR_CALC_STATE_AlphaReferenceValueAsFLOAT32_start 224 #define GFX45_COLOR_CALC_STATE_AlphaReferenceValueAsFLOAT32_start 224 #define GFX4_COLOR_CALC_STATE_AlphaReferenceValueAsFLOAT32_start 224 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_AlphaReferenceValueAsFLOAT32_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 32; case 50: return 224; case 45: return 224; case 40: return 224; default: unreachable("Invalid hardware generation"); } } /* COLOR_CALC_STATE::Alpha Reference Value As UNORM8 */ #define GFX125_COLOR_CALC_STATE_AlphaReferenceValueAsUNORM8_bits 32 #define GFX12_COLOR_CALC_STATE_AlphaReferenceValueAsUNORM8_bits 32 #define GFX11_COLOR_CALC_STATE_AlphaReferenceValueAsUNORM8_bits 32 #define GFX9_COLOR_CALC_STATE_AlphaReferenceValueAsUNORM8_bits 32 #define GFX8_COLOR_CALC_STATE_AlphaReferenceValueAsUNORM8_bits 32 #define GFX75_COLOR_CALC_STATE_AlphaReferenceValueAsUNORM8_bits 32 #define GFX7_COLOR_CALC_STATE_AlphaReferenceValueAsUNORM8_bits 32 #define GFX6_COLOR_CALC_STATE_AlphaReferenceValueAsUNORM8_bits 32 #define GFX5_COLOR_CALC_STATE_AlphaReferenceValueAsUNORM8_bits 32 #define GFX45_COLOR_CALC_STATE_AlphaReferenceValueAsUNORM8_bits 32 #define GFX4_COLOR_CALC_STATE_AlphaReferenceValueAsUNORM8_bits 32 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_AlphaReferenceValueAsUNORM8_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 32; case 50: return 32; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } #define GFX125_COLOR_CALC_STATE_AlphaReferenceValueAsUNORM8_start 32 #define GFX12_COLOR_CALC_STATE_AlphaReferenceValueAsUNORM8_start 32 #define GFX11_COLOR_CALC_STATE_AlphaReferenceValueAsUNORM8_start 32 #define GFX9_COLOR_CALC_STATE_AlphaReferenceValueAsUNORM8_start 32 #define GFX8_COLOR_CALC_STATE_AlphaReferenceValueAsUNORM8_start 32 #define GFX75_COLOR_CALC_STATE_AlphaReferenceValueAsUNORM8_start 32 #define GFX7_COLOR_CALC_STATE_AlphaReferenceValueAsUNORM8_start 32 #define GFX6_COLOR_CALC_STATE_AlphaReferenceValueAsUNORM8_start 32 #define GFX5_COLOR_CALC_STATE_AlphaReferenceValueAsUNORM8_start 224 #define GFX45_COLOR_CALC_STATE_AlphaReferenceValueAsUNORM8_start 224 #define GFX4_COLOR_CALC_STATE_AlphaReferenceValueAsUNORM8_start 224 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_AlphaReferenceValueAsUNORM8_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 32; case 50: return 224; case 45: return 224; case 40: return 224; default: unreachable("Invalid hardware generation"); } } /* COLOR_CALC_STATE::Alpha Test Enable */ #define GFX5_COLOR_CALC_STATE_AlphaTestEnable_bits 1 #define GFX45_COLOR_CALC_STATE_AlphaTestEnable_bits 1 #define GFX4_COLOR_CALC_STATE_AlphaTestEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_AlphaTestEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_COLOR_CALC_STATE_AlphaTestEnable_start 107 #define GFX45_COLOR_CALC_STATE_AlphaTestEnable_start 107 #define GFX4_COLOR_CALC_STATE_AlphaTestEnable_start 107 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_AlphaTestEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 107; case 45: return 107; case 40: return 107; default: unreachable("Invalid hardware generation"); } } /* COLOR_CALC_STATE::Alpha Test Format */ #define GFX125_COLOR_CALC_STATE_AlphaTestFormat_bits 1 #define GFX12_COLOR_CALC_STATE_AlphaTestFormat_bits 1 #define GFX11_COLOR_CALC_STATE_AlphaTestFormat_bits 1 #define GFX9_COLOR_CALC_STATE_AlphaTestFormat_bits 1 #define GFX8_COLOR_CALC_STATE_AlphaTestFormat_bits 1 #define GFX75_COLOR_CALC_STATE_AlphaTestFormat_bits 1 #define GFX7_COLOR_CALC_STATE_AlphaTestFormat_bits 1 #define GFX6_COLOR_CALC_STATE_AlphaTestFormat_bits 1 #define GFX5_COLOR_CALC_STATE_AlphaTestFormat_bits 1 #define GFX45_COLOR_CALC_STATE_AlphaTestFormat_bits 1 #define GFX4_COLOR_CALC_STATE_AlphaTestFormat_bits 1 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_AlphaTestFormat_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX125_COLOR_CALC_STATE_AlphaTestFormat_start 0 #define GFX12_COLOR_CALC_STATE_AlphaTestFormat_start 0 #define GFX11_COLOR_CALC_STATE_AlphaTestFormat_start 0 #define GFX9_COLOR_CALC_STATE_AlphaTestFormat_start 0 #define GFX8_COLOR_CALC_STATE_AlphaTestFormat_start 0 #define GFX75_COLOR_CALC_STATE_AlphaTestFormat_start 0 #define GFX7_COLOR_CALC_STATE_AlphaTestFormat_start 0 #define GFX6_COLOR_CALC_STATE_AlphaTestFormat_start 0 #define GFX5_COLOR_CALC_STATE_AlphaTestFormat_start 111 #define GFX45_COLOR_CALC_STATE_AlphaTestFormat_start 111 #define GFX4_COLOR_CALC_STATE_AlphaTestFormat_start 111 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_AlphaTestFormat_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 111; case 45: return 111; case 40: return 111; default: unreachable("Invalid hardware generation"); } } /* COLOR_CALC_STATE::Alpha Test Function */ #define GFX5_COLOR_CALC_STATE_AlphaTestFunction_bits 3 #define GFX45_COLOR_CALC_STATE_AlphaTestFunction_bits 3 #define GFX4_COLOR_CALC_STATE_AlphaTestFunction_bits 3 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_AlphaTestFunction_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX5_COLOR_CALC_STATE_AlphaTestFunction_start 104 #define GFX45_COLOR_CALC_STATE_AlphaTestFunction_start 104 #define GFX4_COLOR_CALC_STATE_AlphaTestFunction_start 104 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_AlphaTestFunction_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 104; case 45: return 104; case 40: return 104; default: unreachable("Invalid hardware generation"); } } /* COLOR_CALC_STATE::Backface Stencil Fail Op */ #define GFX5_COLOR_CALC_STATE_BackfaceStencilFailOp_bits 3 #define GFX45_COLOR_CALC_STATE_BackfaceStencilFailOp_bits 3 #define GFX4_COLOR_CALC_STATE_BackfaceStencilFailOp_bits 3 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_BackfaceStencilFailOp_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX5_COLOR_CALC_STATE_BackfaceStencilFailOp_start 9 #define GFX45_COLOR_CALC_STATE_BackfaceStencilFailOp_start 9 #define GFX4_COLOR_CALC_STATE_BackfaceStencilFailOp_start 9 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_BackfaceStencilFailOp_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 9; case 45: return 9; case 40: return 9; default: unreachable("Invalid hardware generation"); } } /* COLOR_CALC_STATE::Backface Stencil Pass Depth Fail Op */ #define GFX5_COLOR_CALC_STATE_BackfaceStencilPassDepthFailOp_bits 3 #define GFX45_COLOR_CALC_STATE_BackfaceStencilPassDepthFailOp_bits 3 #define GFX4_COLOR_CALC_STATE_BackfaceStencilPassDepthFailOp_bits 3 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_BackfaceStencilPassDepthFailOp_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX5_COLOR_CALC_STATE_BackfaceStencilPassDepthFailOp_start 6 #define GFX45_COLOR_CALC_STATE_BackfaceStencilPassDepthFailOp_start 6 #define GFX4_COLOR_CALC_STATE_BackfaceStencilPassDepthFailOp_start 6 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_BackfaceStencilPassDepthFailOp_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 6; case 45: return 6; case 40: return 6; default: unreachable("Invalid hardware generation"); } } /* COLOR_CALC_STATE::Backface Stencil Pass Depth Pass Op */ #define GFX5_COLOR_CALC_STATE_BackfaceStencilPassDepthPassOp_bits 3 #define GFX45_COLOR_CALC_STATE_BackfaceStencilPassDepthPassOp_bits 3 #define GFX4_COLOR_CALC_STATE_BackfaceStencilPassDepthPassOp_bits 3 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_BackfaceStencilPassDepthPassOp_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX5_COLOR_CALC_STATE_BackfaceStencilPassDepthPassOp_start 3 #define GFX45_COLOR_CALC_STATE_BackfaceStencilPassDepthPassOp_start 3 #define GFX4_COLOR_CALC_STATE_BackfaceStencilPassDepthPassOp_start 3 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_BackfaceStencilPassDepthPassOp_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } /* COLOR_CALC_STATE::Backface Stencil Reference Value */ #define GFX8_COLOR_CALC_STATE_BackfaceStencilReferenceValue_bits 8 #define GFX75_COLOR_CALC_STATE_BackfaceStencilReferenceValue_bits 8 #define GFX7_COLOR_CALC_STATE_BackfaceStencilReferenceValue_bits 8 #define GFX6_COLOR_CALC_STATE_BackfaceStencilReferenceValue_bits 8 #define GFX5_COLOR_CALC_STATE_BackfaceStencilReferenceValue_bits 8 #define GFX45_COLOR_CALC_STATE_BackfaceStencilReferenceValue_bits 8 #define GFX4_COLOR_CALC_STATE_BackfaceStencilReferenceValue_bits 8 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_BackfaceStencilReferenceValue_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 8; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } #define GFX8_COLOR_CALC_STATE_BackfaceStencilReferenceValue_start 16 #define GFX75_COLOR_CALC_STATE_BackfaceStencilReferenceValue_start 16 #define GFX7_COLOR_CALC_STATE_BackfaceStencilReferenceValue_start 16 #define GFX6_COLOR_CALC_STATE_BackfaceStencilReferenceValue_start 16 #define GFX5_COLOR_CALC_STATE_BackfaceStencilReferenceValue_start 32 #define GFX45_COLOR_CALC_STATE_BackfaceStencilReferenceValue_start 32 #define GFX4_COLOR_CALC_STATE_BackfaceStencilReferenceValue_start 32 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_BackfaceStencilReferenceValue_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 16; case 50: return 32; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } /* COLOR_CALC_STATE::Backface Stencil Test Function */ #define GFX5_COLOR_CALC_STATE_BackfaceStencilTestFunction_bits 3 #define GFX45_COLOR_CALC_STATE_BackfaceStencilTestFunction_bits 3 #define GFX4_COLOR_CALC_STATE_BackfaceStencilTestFunction_bits 3 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_BackfaceStencilTestFunction_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX5_COLOR_CALC_STATE_BackfaceStencilTestFunction_start 12 #define GFX45_COLOR_CALC_STATE_BackfaceStencilTestFunction_start 12 #define GFX4_COLOR_CALC_STATE_BackfaceStencilTestFunction_start 12 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_BackfaceStencilTestFunction_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 12; case 45: return 12; case 40: return 12; default: unreachable("Invalid hardware generation"); } } /* COLOR_CALC_STATE::Backface Stencil Test Mask */ #define GFX5_COLOR_CALC_STATE_BackfaceStencilTestMask_bits 8 #define GFX45_COLOR_CALC_STATE_BackfaceStencilTestMask_bits 8 #define GFX4_COLOR_CALC_STATE_BackfaceStencilTestMask_bits 8 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_BackfaceStencilTestMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 8; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } #define GFX5_COLOR_CALC_STATE_BackfaceStencilTestMask_start 88 #define GFX45_COLOR_CALC_STATE_BackfaceStencilTestMask_start 88 #define GFX4_COLOR_CALC_STATE_BackfaceStencilTestMask_start 88 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_BackfaceStencilTestMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 88; case 45: return 88; case 40: return 88; default: unreachable("Invalid hardware generation"); } } /* COLOR_CALC_STATE::Backface Stencil Write Mask */ #define GFX5_COLOR_CALC_STATE_BackfaceStencilWriteMask_bits 8 #define GFX45_COLOR_CALC_STATE_BackfaceStencilWriteMask_bits 8 #define GFX4_COLOR_CALC_STATE_BackfaceStencilWriteMask_bits 8 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_BackfaceStencilWriteMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 8; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } #define GFX5_COLOR_CALC_STATE_BackfaceStencilWriteMask_start 80 #define GFX45_COLOR_CALC_STATE_BackfaceStencilWriteMask_start 80 #define GFX4_COLOR_CALC_STATE_BackfaceStencilWriteMask_start 80 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_BackfaceStencilWriteMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 80; case 45: return 80; case 40: return 80; default: unreachable("Invalid hardware generation"); } } /* COLOR_CALC_STATE::Blend Constant Color Alpha */ #define GFX125_COLOR_CALC_STATE_BlendConstantColorAlpha_bits 32 #define GFX12_COLOR_CALC_STATE_BlendConstantColorAlpha_bits 32 #define GFX11_COLOR_CALC_STATE_BlendConstantColorAlpha_bits 32 #define GFX9_COLOR_CALC_STATE_BlendConstantColorAlpha_bits 32 #define GFX8_COLOR_CALC_STATE_BlendConstantColorAlpha_bits 32 #define GFX75_COLOR_CALC_STATE_BlendConstantColorAlpha_bits 32 #define GFX7_COLOR_CALC_STATE_BlendConstantColorAlpha_bits 32 #define GFX6_COLOR_CALC_STATE_BlendConstantColorAlpha_bits 32 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_BlendConstantColorAlpha_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 32; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_COLOR_CALC_STATE_BlendConstantColorAlpha_start 160 #define GFX12_COLOR_CALC_STATE_BlendConstantColorAlpha_start 160 #define GFX11_COLOR_CALC_STATE_BlendConstantColorAlpha_start 160 #define GFX9_COLOR_CALC_STATE_BlendConstantColorAlpha_start 160 #define GFX8_COLOR_CALC_STATE_BlendConstantColorAlpha_start 160 #define GFX75_COLOR_CALC_STATE_BlendConstantColorAlpha_start 160 #define GFX7_COLOR_CALC_STATE_BlendConstantColorAlpha_start 160 #define GFX6_COLOR_CALC_STATE_BlendConstantColorAlpha_start 160 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_BlendConstantColorAlpha_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 160; case 120: return 160; case 110: return 160; case 90: return 160; case 80: return 160; case 75: return 160; case 70: return 160; case 60: return 160; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* COLOR_CALC_STATE::Blend Constant Color Blue */ #define GFX125_COLOR_CALC_STATE_BlendConstantColorBlue_bits 32 #define GFX12_COLOR_CALC_STATE_BlendConstantColorBlue_bits 32 #define GFX11_COLOR_CALC_STATE_BlendConstantColorBlue_bits 32 #define GFX9_COLOR_CALC_STATE_BlendConstantColorBlue_bits 32 #define GFX8_COLOR_CALC_STATE_BlendConstantColorBlue_bits 32 #define GFX75_COLOR_CALC_STATE_BlendConstantColorBlue_bits 32 #define GFX7_COLOR_CALC_STATE_BlendConstantColorBlue_bits 32 #define GFX6_COLOR_CALC_STATE_BlendConstantColorBlue_bits 32 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_BlendConstantColorBlue_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 32; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_COLOR_CALC_STATE_BlendConstantColorBlue_start 128 #define GFX12_COLOR_CALC_STATE_BlendConstantColorBlue_start 128 #define GFX11_COLOR_CALC_STATE_BlendConstantColorBlue_start 128 #define GFX9_COLOR_CALC_STATE_BlendConstantColorBlue_start 128 #define GFX8_COLOR_CALC_STATE_BlendConstantColorBlue_start 128 #define GFX75_COLOR_CALC_STATE_BlendConstantColorBlue_start 128 #define GFX7_COLOR_CALC_STATE_BlendConstantColorBlue_start 128 #define GFX6_COLOR_CALC_STATE_BlendConstantColorBlue_start 128 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_BlendConstantColorBlue_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 128; case 120: return 128; case 110: return 128; case 90: return 128; case 80: return 128; case 75: return 128; case 70: return 128; case 60: return 128; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* COLOR_CALC_STATE::Blend Constant Color Green */ #define GFX125_COLOR_CALC_STATE_BlendConstantColorGreen_bits 32 #define GFX12_COLOR_CALC_STATE_BlendConstantColorGreen_bits 32 #define GFX11_COLOR_CALC_STATE_BlendConstantColorGreen_bits 32 #define GFX9_COLOR_CALC_STATE_BlendConstantColorGreen_bits 32 #define GFX8_COLOR_CALC_STATE_BlendConstantColorGreen_bits 32 #define GFX75_COLOR_CALC_STATE_BlendConstantColorGreen_bits 32 #define GFX7_COLOR_CALC_STATE_BlendConstantColorGreen_bits 32 #define GFX6_COLOR_CALC_STATE_BlendConstantColorGreen_bits 32 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_BlendConstantColorGreen_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 32; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_COLOR_CALC_STATE_BlendConstantColorGreen_start 96 #define GFX12_COLOR_CALC_STATE_BlendConstantColorGreen_start 96 #define GFX11_COLOR_CALC_STATE_BlendConstantColorGreen_start 96 #define GFX9_COLOR_CALC_STATE_BlendConstantColorGreen_start 96 #define GFX8_COLOR_CALC_STATE_BlendConstantColorGreen_start 96 #define GFX75_COLOR_CALC_STATE_BlendConstantColorGreen_start 96 #define GFX7_COLOR_CALC_STATE_BlendConstantColorGreen_start 96 #define GFX6_COLOR_CALC_STATE_BlendConstantColorGreen_start 96 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_BlendConstantColorGreen_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 96; case 120: return 96; case 110: return 96; case 90: return 96; case 80: return 96; case 75: return 96; case 70: return 96; case 60: return 96; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* COLOR_CALC_STATE::Blend Constant Color Red */ #define GFX125_COLOR_CALC_STATE_BlendConstantColorRed_bits 32 #define GFX12_COLOR_CALC_STATE_BlendConstantColorRed_bits 32 #define GFX11_COLOR_CALC_STATE_BlendConstantColorRed_bits 32 #define GFX9_COLOR_CALC_STATE_BlendConstantColorRed_bits 32 #define GFX8_COLOR_CALC_STATE_BlendConstantColorRed_bits 32 #define GFX75_COLOR_CALC_STATE_BlendConstantColorRed_bits 32 #define GFX7_COLOR_CALC_STATE_BlendConstantColorRed_bits 32 #define GFX6_COLOR_CALC_STATE_BlendConstantColorRed_bits 32 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_BlendConstantColorRed_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 32; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_COLOR_CALC_STATE_BlendConstantColorRed_start 64 #define GFX12_COLOR_CALC_STATE_BlendConstantColorRed_start 64 #define GFX11_COLOR_CALC_STATE_BlendConstantColorRed_start 64 #define GFX9_COLOR_CALC_STATE_BlendConstantColorRed_start 64 #define GFX8_COLOR_CALC_STATE_BlendConstantColorRed_start 64 #define GFX75_COLOR_CALC_STATE_BlendConstantColorRed_start 64 #define GFX7_COLOR_CALC_STATE_BlendConstantColorRed_start 64 #define GFX6_COLOR_CALC_STATE_BlendConstantColorRed_start 64 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_BlendConstantColorRed_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 64; case 80: return 64; case 75: return 64; case 70: return 64; case 60: return 64; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* COLOR_CALC_STATE::CC Viewport State Pointer */ #define GFX5_COLOR_CALC_STATE_CCViewportStatePointer_bits 27 #define GFX45_COLOR_CALC_STATE_CCViewportStatePointer_bits 27 #define GFX4_COLOR_CALC_STATE_CCViewportStatePointer_bits 27 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_CCViewportStatePointer_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 27; case 45: return 27; case 40: return 27; default: unreachable("Invalid hardware generation"); } } #define GFX5_COLOR_CALC_STATE_CCViewportStatePointer_start 133 #define GFX45_COLOR_CALC_STATE_CCViewportStatePointer_start 133 #define GFX4_COLOR_CALC_STATE_CCViewportStatePointer_start 133 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_CCViewportStatePointer_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 133; case 45: return 133; case 40: return 133; default: unreachable("Invalid hardware generation"); } } /* COLOR_CALC_STATE::Color Blend Function */ #define GFX5_COLOR_CALC_STATE_ColorBlendFunction_bits 3 #define GFX45_COLOR_CALC_STATE_ColorBlendFunction_bits 3 #define GFX4_COLOR_CALC_STATE_ColorBlendFunction_bits 3 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_ColorBlendFunction_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX5_COLOR_CALC_STATE_ColorBlendFunction_start 221 #define GFX45_COLOR_CALC_STATE_ColorBlendFunction_start 221 #define GFX4_COLOR_CALC_STATE_ColorBlendFunction_start 221 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_ColorBlendFunction_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 221; case 45: return 221; case 40: return 221; default: unreachable("Invalid hardware generation"); } } /* COLOR_CALC_STATE::Color Buffer Blend Enable */ #define GFX5_COLOR_CALC_STATE_ColorBufferBlendEnable_bits 1 #define GFX45_COLOR_CALC_STATE_ColorBufferBlendEnable_bits 1 #define GFX4_COLOR_CALC_STATE_ColorBufferBlendEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_ColorBufferBlendEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_COLOR_CALC_STATE_ColorBufferBlendEnable_start 108 #define GFX45_COLOR_CALC_STATE_ColorBufferBlendEnable_start 108 #define GFX4_COLOR_CALC_STATE_ColorBufferBlendEnable_start 108 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_ColorBufferBlendEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 108; case 45: return 108; case 40: return 108; default: unreachable("Invalid hardware generation"); } } /* COLOR_CALC_STATE::Color Clamp Range */ #define GFX5_COLOR_CALC_STATE_ColorClampRange_bits 2 #define GFX45_COLOR_CALC_STATE_ColorClampRange_bits 2 #define GFX4_COLOR_CALC_STATE_ColorClampRange_bits 2 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_ColorClampRange_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 2; case 45: return 2; case 40: return 2; default: unreachable("Invalid hardware generation"); } } #define GFX5_COLOR_CALC_STATE_ColorClampRange_start 194 #define GFX45_COLOR_CALC_STATE_ColorClampRange_start 194 #define GFX4_COLOR_CALC_STATE_ColorClampRange_start 194 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_ColorClampRange_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 194; case 45: return 194; case 40: return 194; default: unreachable("Invalid hardware generation"); } } /* COLOR_CALC_STATE::Color Dither Enable */ #define GFX5_COLOR_CALC_STATE_ColorDitherEnable_bits 1 #define GFX45_COLOR_CALC_STATE_ColorDitherEnable_bits 1 #define GFX4_COLOR_CALC_STATE_ColorDitherEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_ColorDitherEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_COLOR_CALC_STATE_ColorDitherEnable_start 191 #define GFX45_COLOR_CALC_STATE_ColorDitherEnable_start 191 #define GFX4_COLOR_CALC_STATE_ColorDitherEnable_start 191 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_ColorDitherEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 191; case 45: return 191; case 40: return 191; default: unreachable("Invalid hardware generation"); } } /* COLOR_CALC_STATE::Depth Buffer Write Enable */ #define GFX5_COLOR_CALC_STATE_DepthBufferWriteEnable_bits 1 #define GFX45_COLOR_CALC_STATE_DepthBufferWriteEnable_bits 1 #define GFX4_COLOR_CALC_STATE_DepthBufferWriteEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_DepthBufferWriteEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_COLOR_CALC_STATE_DepthBufferWriteEnable_start 75 #define GFX45_COLOR_CALC_STATE_DepthBufferWriteEnable_start 75 #define GFX4_COLOR_CALC_STATE_DepthBufferWriteEnable_start 75 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_DepthBufferWriteEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 75; case 45: return 75; case 40: return 75; default: unreachable("Invalid hardware generation"); } } /* COLOR_CALC_STATE::Depth Test Enable */ #define GFX5_COLOR_CALC_STATE_DepthTestEnable_bits 1 #define GFX45_COLOR_CALC_STATE_DepthTestEnable_bits 1 #define GFX4_COLOR_CALC_STATE_DepthTestEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_DepthTestEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_COLOR_CALC_STATE_DepthTestEnable_start 79 #define GFX45_COLOR_CALC_STATE_DepthTestEnable_start 79 #define GFX4_COLOR_CALC_STATE_DepthTestEnable_start 79 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_DepthTestEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 79; case 45: return 79; case 40: return 79; default: unreachable("Invalid hardware generation"); } } /* COLOR_CALC_STATE::Depth Test Function */ #define GFX5_COLOR_CALC_STATE_DepthTestFunction_bits 3 #define GFX45_COLOR_CALC_STATE_DepthTestFunction_bits 3 #define GFX4_COLOR_CALC_STATE_DepthTestFunction_bits 3 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_DepthTestFunction_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX5_COLOR_CALC_STATE_DepthTestFunction_start 76 #define GFX45_COLOR_CALC_STATE_DepthTestFunction_start 76 #define GFX4_COLOR_CALC_STATE_DepthTestFunction_start 76 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_DepthTestFunction_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 76; case 45: return 76; case 40: return 76; default: unreachable("Invalid hardware generation"); } } /* COLOR_CALC_STATE::Destination Alpha Blend Factor */ #define GFX5_COLOR_CALC_STATE_DestinationAlphaBlendFactor_bits 5 #define GFX45_COLOR_CALC_STATE_DestinationAlphaBlendFactor_bits 5 #define GFX4_COLOR_CALC_STATE_DestinationAlphaBlendFactor_bits 5 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_DestinationAlphaBlendFactor_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 5; case 45: return 5; case 40: return 5; default: unreachable("Invalid hardware generation"); } } #define GFX5_COLOR_CALC_STATE_DestinationAlphaBlendFactor_start 162 #define GFX45_COLOR_CALC_STATE_DestinationAlphaBlendFactor_start 162 #define GFX4_COLOR_CALC_STATE_DestinationAlphaBlendFactor_start 162 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_DestinationAlphaBlendFactor_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 162; case 45: return 162; case 40: return 162; default: unreachable("Invalid hardware generation"); } } /* COLOR_CALC_STATE::Destination Blend Factor */ #define GFX5_COLOR_CALC_STATE_DestinationBlendFactor_bits 5 #define GFX45_COLOR_CALC_STATE_DestinationBlendFactor_bits 5 #define GFX4_COLOR_CALC_STATE_DestinationBlendFactor_bits 5 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_DestinationBlendFactor_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 5; case 45: return 5; case 40: return 5; default: unreachable("Invalid hardware generation"); } } #define GFX5_COLOR_CALC_STATE_DestinationBlendFactor_start 211 #define GFX45_COLOR_CALC_STATE_DestinationBlendFactor_start 211 #define GFX4_COLOR_CALC_STATE_DestinationBlendFactor_start 211 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_DestinationBlendFactor_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 211; case 45: return 211; case 40: return 211; default: unreachable("Invalid hardware generation"); } } /* COLOR_CALC_STATE::Double Sided Stencil Enable */ #define GFX5_COLOR_CALC_STATE_DoubleSidedStencilEnable_bits 1 #define GFX45_COLOR_CALC_STATE_DoubleSidedStencilEnable_bits 1 #define GFX4_COLOR_CALC_STATE_DoubleSidedStencilEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_DoubleSidedStencilEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_COLOR_CALC_STATE_DoubleSidedStencilEnable_start 15 #define GFX45_COLOR_CALC_STATE_DoubleSidedStencilEnable_start 15 #define GFX4_COLOR_CALC_STATE_DoubleSidedStencilEnable_start 15 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_DoubleSidedStencilEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 15; case 45: return 15; case 40: return 15; default: unreachable("Invalid hardware generation"); } } /* COLOR_CALC_STATE::Independent Alpha Blend Enable */ #define GFX5_COLOR_CALC_STATE_IndependentAlphaBlendEnable_bits 1 #define GFX45_COLOR_CALC_STATE_IndependentAlphaBlendEnable_bits 1 #define GFX4_COLOR_CALC_STATE_IndependentAlphaBlendEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_IndependentAlphaBlendEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_COLOR_CALC_STATE_IndependentAlphaBlendEnable_start 109 #define GFX45_COLOR_CALC_STATE_IndependentAlphaBlendEnable_start 109 #define GFX4_COLOR_CALC_STATE_IndependentAlphaBlendEnable_start 109 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_IndependentAlphaBlendEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 109; case 45: return 109; case 40: return 109; default: unreachable("Invalid hardware generation"); } } /* COLOR_CALC_STATE::Logic Op Enable */ #define GFX5_COLOR_CALC_STATE_LogicOpEnable_bits 1 #define GFX45_COLOR_CALC_STATE_LogicOpEnable_bits 1 #define GFX4_COLOR_CALC_STATE_LogicOpEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_LogicOpEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_COLOR_CALC_STATE_LogicOpEnable_start 64 #define GFX45_COLOR_CALC_STATE_LogicOpEnable_start 64 #define GFX4_COLOR_CALC_STATE_LogicOpEnable_start 64 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_LogicOpEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 64; case 45: return 64; case 40: return 64; default: unreachable("Invalid hardware generation"); } } /* COLOR_CALC_STATE::Logic Op Function */ #define GFX5_COLOR_CALC_STATE_LogicOpFunction_bits 4 #define GFX45_COLOR_CALC_STATE_LogicOpFunction_bits 4 #define GFX4_COLOR_CALC_STATE_LogicOpFunction_bits 4 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_LogicOpFunction_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 4; case 45: return 4; case 40: return 4; default: unreachable("Invalid hardware generation"); } } #define GFX5_COLOR_CALC_STATE_LogicOpFunction_start 176 #define GFX45_COLOR_CALC_STATE_LogicOpFunction_start 176 #define GFX4_COLOR_CALC_STATE_LogicOpFunction_start 176 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_LogicOpFunction_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 176; case 45: return 176; case 40: return 176; default: unreachable("Invalid hardware generation"); } } /* COLOR_CALC_STATE::Post-Blend Color Clamp Enable */ #define GFX5_COLOR_CALC_STATE_PostBlendColorClampEnable_bits 1 #define GFX45_COLOR_CALC_STATE_PostBlendColorClampEnable_bits 1 #define GFX4_COLOR_CALC_STATE_PostBlendColorClampEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_PostBlendColorClampEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_COLOR_CALC_STATE_PostBlendColorClampEnable_start 192 #define GFX45_COLOR_CALC_STATE_PostBlendColorClampEnable_start 192 #define GFX4_COLOR_CALC_STATE_PostBlendColorClampEnable_start 192 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_PostBlendColorClampEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 192; case 45: return 192; case 40: return 192; default: unreachable("Invalid hardware generation"); } } /* COLOR_CALC_STATE::Pre-Blend Color Clamp Enable */ #define GFX5_COLOR_CALC_STATE_PreBlendColorClampEnable_bits 1 #define GFX45_COLOR_CALC_STATE_PreBlendColorClampEnable_bits 1 #define GFX4_COLOR_CALC_STATE_PreBlendColorClampEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_PreBlendColorClampEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_COLOR_CALC_STATE_PreBlendColorClampEnable_start 193 #define GFX45_COLOR_CALC_STATE_PreBlendColorClampEnable_start 193 #define GFX4_COLOR_CALC_STATE_PreBlendColorClampEnable_start 193 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_PreBlendColorClampEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 193; case 45: return 193; case 40: return 193; default: unreachable("Invalid hardware generation"); } } /* COLOR_CALC_STATE::Round Disable Function Disable */ #define GFX125_COLOR_CALC_STATE_RoundDisableFunctionDisable_bits 1 #define GFX12_COLOR_CALC_STATE_RoundDisableFunctionDisable_bits 1 #define GFX11_COLOR_CALC_STATE_RoundDisableFunctionDisable_bits 1 #define GFX9_COLOR_CALC_STATE_RoundDisableFunctionDisable_bits 1 #define GFX8_COLOR_CALC_STATE_RoundDisableFunctionDisable_bits 1 #define GFX75_COLOR_CALC_STATE_RoundDisableFunctionDisable_bits 1 #define GFX7_COLOR_CALC_STATE_RoundDisableFunctionDisable_bits 1 #define GFX6_COLOR_CALC_STATE_RoundDisableFunctionDisable_bits 1 #define GFX5_COLOR_CALC_STATE_RoundDisableFunctionDisable_bits 1 #define GFX45_COLOR_CALC_STATE_RoundDisableFunctionDisable_bits 1 #define GFX4_COLOR_CALC_STATE_RoundDisableFunctionDisable_bits 1 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_RoundDisableFunctionDisable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX125_COLOR_CALC_STATE_RoundDisableFunctionDisable_start 15 #define GFX12_COLOR_CALC_STATE_RoundDisableFunctionDisable_start 15 #define GFX11_COLOR_CALC_STATE_RoundDisableFunctionDisable_start 15 #define GFX9_COLOR_CALC_STATE_RoundDisableFunctionDisable_start 15 #define GFX8_COLOR_CALC_STATE_RoundDisableFunctionDisable_start 15 #define GFX75_COLOR_CALC_STATE_RoundDisableFunctionDisable_start 15 #define GFX7_COLOR_CALC_STATE_RoundDisableFunctionDisable_start 15 #define GFX6_COLOR_CALC_STATE_RoundDisableFunctionDisable_start 15 #define GFX5_COLOR_CALC_STATE_RoundDisableFunctionDisable_start 190 #define GFX45_COLOR_CALC_STATE_RoundDisableFunctionDisable_start 190 #define GFX4_COLOR_CALC_STATE_RoundDisableFunctionDisable_start 190 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_RoundDisableFunctionDisable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 15; case 120: return 15; case 110: return 15; case 90: return 15; case 80: return 15; case 75: return 15; case 70: return 15; case 60: return 15; case 50: return 190; case 45: return 190; case 40: return 190; default: unreachable("Invalid hardware generation"); } } /* COLOR_CALC_STATE::Source Alpha Blend Factor */ #define GFX5_COLOR_CALC_STATE_SourceAlphaBlendFactor_bits 5 #define GFX45_COLOR_CALC_STATE_SourceAlphaBlendFactor_bits 5 #define GFX4_COLOR_CALC_STATE_SourceAlphaBlendFactor_bits 5 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_SourceAlphaBlendFactor_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 5; case 45: return 5; case 40: return 5; default: unreachable("Invalid hardware generation"); } } #define GFX5_COLOR_CALC_STATE_SourceAlphaBlendFactor_start 167 #define GFX45_COLOR_CALC_STATE_SourceAlphaBlendFactor_start 167 #define GFX4_COLOR_CALC_STATE_SourceAlphaBlendFactor_start 167 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_SourceAlphaBlendFactor_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 167; case 45: return 167; case 40: return 167; default: unreachable("Invalid hardware generation"); } } /* COLOR_CALC_STATE::Source Blend Factor */ #define GFX5_COLOR_CALC_STATE_SourceBlendFactor_bits 5 #define GFX45_COLOR_CALC_STATE_SourceBlendFactor_bits 5 #define GFX4_COLOR_CALC_STATE_SourceBlendFactor_bits 5 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_SourceBlendFactor_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 5; case 45: return 5; case 40: return 5; default: unreachable("Invalid hardware generation"); } } #define GFX5_COLOR_CALC_STATE_SourceBlendFactor_start 216 #define GFX45_COLOR_CALC_STATE_SourceBlendFactor_start 216 #define GFX4_COLOR_CALC_STATE_SourceBlendFactor_start 216 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_SourceBlendFactor_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 216; case 45: return 216; case 40: return 216; default: unreachable("Invalid hardware generation"); } } /* COLOR_CALC_STATE::Statistics Enable */ #define GFX5_COLOR_CALC_STATE_StatisticsEnable_bits 1 #define GFX45_COLOR_CALC_STATE_StatisticsEnable_bits 1 #define GFX4_COLOR_CALC_STATE_StatisticsEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_StatisticsEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_COLOR_CALC_STATE_StatisticsEnable_start 175 #define GFX45_COLOR_CALC_STATE_StatisticsEnable_start 175 #define GFX4_COLOR_CALC_STATE_StatisticsEnable_start 175 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_StatisticsEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 175; case 45: return 175; case 40: return 175; default: unreachable("Invalid hardware generation"); } } /* COLOR_CALC_STATE::Stencil Buffer Write Enable */ #define GFX5_COLOR_CALC_STATE_StencilBufferWriteEnable_bits 1 #define GFX45_COLOR_CALC_STATE_StencilBufferWriteEnable_bits 1 #define GFX4_COLOR_CALC_STATE_StencilBufferWriteEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_StencilBufferWriteEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_COLOR_CALC_STATE_StencilBufferWriteEnable_start 18 #define GFX45_COLOR_CALC_STATE_StencilBufferWriteEnable_start 18 #define GFX4_COLOR_CALC_STATE_StencilBufferWriteEnable_start 18 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_StencilBufferWriteEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 18; case 45: return 18; case 40: return 18; default: unreachable("Invalid hardware generation"); } } /* COLOR_CALC_STATE::Stencil Fail Op */ #define GFX5_COLOR_CALC_STATE_StencilFailOp_bits 3 #define GFX45_COLOR_CALC_STATE_StencilFailOp_bits 3 #define GFX4_COLOR_CALC_STATE_StencilFailOp_bits 3 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_StencilFailOp_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX5_COLOR_CALC_STATE_StencilFailOp_start 25 #define GFX45_COLOR_CALC_STATE_StencilFailOp_start 25 #define GFX4_COLOR_CALC_STATE_StencilFailOp_start 25 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_StencilFailOp_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 25; case 45: return 25; case 40: return 25; default: unreachable("Invalid hardware generation"); } } /* COLOR_CALC_STATE::Stencil Pass Depth Fail Op */ #define GFX5_COLOR_CALC_STATE_StencilPassDepthFailOp_bits 3 #define GFX45_COLOR_CALC_STATE_StencilPassDepthFailOp_bits 3 #define GFX4_COLOR_CALC_STATE_StencilPassDepthFailOp_bits 3 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_StencilPassDepthFailOp_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX5_COLOR_CALC_STATE_StencilPassDepthFailOp_start 22 #define GFX45_COLOR_CALC_STATE_StencilPassDepthFailOp_start 22 #define GFX4_COLOR_CALC_STATE_StencilPassDepthFailOp_start 22 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_StencilPassDepthFailOp_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 22; case 45: return 22; case 40: return 22; default: unreachable("Invalid hardware generation"); } } /* COLOR_CALC_STATE::Stencil Pass Depth Pass Op */ #define GFX5_COLOR_CALC_STATE_StencilPassDepthPassOp_bits 3 #define GFX45_COLOR_CALC_STATE_StencilPassDepthPassOp_bits 3 #define GFX4_COLOR_CALC_STATE_StencilPassDepthPassOp_bits 3 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_StencilPassDepthPassOp_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX5_COLOR_CALC_STATE_StencilPassDepthPassOp_start 19 #define GFX45_COLOR_CALC_STATE_StencilPassDepthPassOp_start 19 #define GFX4_COLOR_CALC_STATE_StencilPassDepthPassOp_start 19 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_StencilPassDepthPassOp_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 19; case 45: return 19; case 40: return 19; default: unreachable("Invalid hardware generation"); } } /* COLOR_CALC_STATE::Stencil Reference Value */ #define GFX8_COLOR_CALC_STATE_StencilReferenceValue_bits 8 #define GFX75_COLOR_CALC_STATE_StencilReferenceValue_bits 8 #define GFX7_COLOR_CALC_STATE_StencilReferenceValue_bits 8 #define GFX6_COLOR_CALC_STATE_StencilReferenceValue_bits 8 #define GFX5_COLOR_CALC_STATE_StencilReferenceValue_bits 8 #define GFX45_COLOR_CALC_STATE_StencilReferenceValue_bits 8 #define GFX4_COLOR_CALC_STATE_StencilReferenceValue_bits 8 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_StencilReferenceValue_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 8; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } #define GFX8_COLOR_CALC_STATE_StencilReferenceValue_start 24 #define GFX75_COLOR_CALC_STATE_StencilReferenceValue_start 24 #define GFX7_COLOR_CALC_STATE_StencilReferenceValue_start 24 #define GFX6_COLOR_CALC_STATE_StencilReferenceValue_start 24 #define GFX5_COLOR_CALC_STATE_StencilReferenceValue_start 56 #define GFX45_COLOR_CALC_STATE_StencilReferenceValue_start 56 #define GFX4_COLOR_CALC_STATE_StencilReferenceValue_start 56 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_StencilReferenceValue_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 24; case 50: return 56; case 45: return 56; case 40: return 56; default: unreachable("Invalid hardware generation"); } } /* COLOR_CALC_STATE::Stencil Test Enable */ #define GFX5_COLOR_CALC_STATE_StencilTestEnable_bits 1 #define GFX45_COLOR_CALC_STATE_StencilTestEnable_bits 1 #define GFX4_COLOR_CALC_STATE_StencilTestEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_StencilTestEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_COLOR_CALC_STATE_StencilTestEnable_start 31 #define GFX45_COLOR_CALC_STATE_StencilTestEnable_start 31 #define GFX4_COLOR_CALC_STATE_StencilTestEnable_start 31 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_StencilTestEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 31; case 45: return 31; case 40: return 31; default: unreachable("Invalid hardware generation"); } } /* COLOR_CALC_STATE::Stencil Test Function */ #define GFX5_COLOR_CALC_STATE_StencilTestFunction_bits 3 #define GFX45_COLOR_CALC_STATE_StencilTestFunction_bits 3 #define GFX4_COLOR_CALC_STATE_StencilTestFunction_bits 3 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_StencilTestFunction_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX5_COLOR_CALC_STATE_StencilTestFunction_start 28 #define GFX45_COLOR_CALC_STATE_StencilTestFunction_start 28 #define GFX4_COLOR_CALC_STATE_StencilTestFunction_start 28 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_StencilTestFunction_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 28; case 45: return 28; case 40: return 28; default: unreachable("Invalid hardware generation"); } } /* COLOR_CALC_STATE::Stencil Test Mask */ #define GFX5_COLOR_CALC_STATE_StencilTestMask_bits 8 #define GFX45_COLOR_CALC_STATE_StencilTestMask_bits 8 #define GFX4_COLOR_CALC_STATE_StencilTestMask_bits 8 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_StencilTestMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 8; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } #define GFX5_COLOR_CALC_STATE_StencilTestMask_start 48 #define GFX45_COLOR_CALC_STATE_StencilTestMask_start 48 #define GFX4_COLOR_CALC_STATE_StencilTestMask_start 48 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_StencilTestMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 48; case 45: return 48; case 40: return 48; default: unreachable("Invalid hardware generation"); } } /* COLOR_CALC_STATE::Stencil Write Mask */ #define GFX5_COLOR_CALC_STATE_StencilWriteMask_bits 8 #define GFX45_COLOR_CALC_STATE_StencilWriteMask_bits 8 #define GFX4_COLOR_CALC_STATE_StencilWriteMask_bits 8 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_StencilWriteMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 8; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } #define GFX5_COLOR_CALC_STATE_StencilWriteMask_start 40 #define GFX45_COLOR_CALC_STATE_StencilWriteMask_start 40 #define GFX4_COLOR_CALC_STATE_StencilWriteMask_start 40 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_StencilWriteMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 40; case 45: return 40; case 40: return 40; default: unreachable("Invalid hardware generation"); } } /* COLOR_CALC_STATE::X Dither Offset */ #define GFX5_COLOR_CALC_STATE_XDitherOffset_bits 2 #define GFX45_COLOR_CALC_STATE_XDitherOffset_bits 2 #define GFX4_COLOR_CALC_STATE_XDitherOffset_bits 2 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_XDitherOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 2; case 45: return 2; case 40: return 2; default: unreachable("Invalid hardware generation"); } } #define GFX5_COLOR_CALC_STATE_XDitherOffset_start 209 #define GFX45_COLOR_CALC_STATE_XDitherOffset_start 209 #define GFX4_COLOR_CALC_STATE_XDitherOffset_start 209 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_XDitherOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 209; case 45: return 209; case 40: return 209; default: unreachable("Invalid hardware generation"); } } /* COLOR_CALC_STATE::Y Dither Offset */ #define GFX5_COLOR_CALC_STATE_YDitherOffset_bits 2 #define GFX45_COLOR_CALC_STATE_YDitherOffset_bits 2 #define GFX4_COLOR_CALC_STATE_YDitherOffset_bits 2 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_YDitherOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 2; case 45: return 2; case 40: return 2; default: unreachable("Invalid hardware generation"); } } #define GFX5_COLOR_CALC_STATE_YDitherOffset_start 207 #define GFX45_COLOR_CALC_STATE_YDitherOffset_start 207 #define GFX4_COLOR_CALC_STATE_YDitherOffset_start 207 static inline uint32_t ATTRIBUTE_PURE COLOR_CALC_STATE_YDitherOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 207; case 45: return 207; case 40: return 207; default: unreachable("Invalid hardware generation"); } } /* COMMON_SLICE_CHICKEN1 */ #define GFX125_COMMON_SLICE_CHICKEN1_length 1 #define GFX12_COMMON_SLICE_CHICKEN1_length 1 static inline uint32_t ATTRIBUTE_PURE COMMON_SLICE_CHICKEN1_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* COMMON_SLICE_CHICKEN1::HIZ Plane Optimization disable bit */ #define GFX125_COMMON_SLICE_CHICKEN1_HIZPlaneOptimizationdisablebit_bits 1 #define GFX12_COMMON_SLICE_CHICKEN1_HIZPlaneOptimizationdisablebit_bits 1 static inline uint32_t ATTRIBUTE_PURE COMMON_SLICE_CHICKEN1_HIZPlaneOptimizationdisablebit_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_COMMON_SLICE_CHICKEN1_HIZPlaneOptimizationdisablebit_start 9 #define GFX12_COMMON_SLICE_CHICKEN1_HIZPlaneOptimizationdisablebit_start 9 static inline uint32_t ATTRIBUTE_PURE COMMON_SLICE_CHICKEN1_HIZPlaneOptimizationdisablebit_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 9; case 120: return 9; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* COMMON_SLICE_CHICKEN1::HIZ Plane Optimization disable bit Mask */ #define GFX125_COMMON_SLICE_CHICKEN1_HIZPlaneOptimizationdisablebitMask_bits 1 #define GFX12_COMMON_SLICE_CHICKEN1_HIZPlaneOptimizationdisablebitMask_bits 1 static inline uint32_t ATTRIBUTE_PURE COMMON_SLICE_CHICKEN1_HIZPlaneOptimizationdisablebitMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_COMMON_SLICE_CHICKEN1_HIZPlaneOptimizationdisablebitMask_start 25 #define GFX12_COMMON_SLICE_CHICKEN1_HIZPlaneOptimizationdisablebitMask_start 25 static inline uint32_t ATTRIBUTE_PURE COMMON_SLICE_CHICKEN1_HIZPlaneOptimizationdisablebitMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 25; case 120: return 25; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* COMMON_SLICE_CHICKEN3 */ #define GFX125_COMMON_SLICE_CHICKEN3_length 1 #define GFX12_COMMON_SLICE_CHICKEN3_length 1 #define GFX11_COMMON_SLICE_CHICKEN3_length 1 static inline uint32_t ATTRIBUTE_PURE COMMON_SLICE_CHICKEN3_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* COMMON_SLICE_CHICKEN3::PS Thread Panic Dispatch */ #define GFX125_COMMON_SLICE_CHICKEN3_PSThreadPanicDispatch_bits 2 #define GFX12_COMMON_SLICE_CHICKEN3_PSThreadPanicDispatch_bits 2 #define GFX11_COMMON_SLICE_CHICKEN3_PSThreadPanicDispatch_bits 2 static inline uint32_t ATTRIBUTE_PURE COMMON_SLICE_CHICKEN3_PSThreadPanicDispatch_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_COMMON_SLICE_CHICKEN3_PSThreadPanicDispatch_start 6 #define GFX12_COMMON_SLICE_CHICKEN3_PSThreadPanicDispatch_start 6 #define GFX11_COMMON_SLICE_CHICKEN3_PSThreadPanicDispatch_start 6 static inline uint32_t ATTRIBUTE_PURE COMMON_SLICE_CHICKEN3_PSThreadPanicDispatch_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* COMMON_SLICE_CHICKEN3::PS Thread Panic Dispatch Mask */ #define GFX125_COMMON_SLICE_CHICKEN3_PSThreadPanicDispatchMask_bits 2 #define GFX12_COMMON_SLICE_CHICKEN3_PSThreadPanicDispatchMask_bits 2 #define GFX11_COMMON_SLICE_CHICKEN3_PSThreadPanicDispatchMask_bits 2 static inline uint32_t ATTRIBUTE_PURE COMMON_SLICE_CHICKEN3_PSThreadPanicDispatchMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_COMMON_SLICE_CHICKEN3_PSThreadPanicDispatchMask_start 22 #define GFX12_COMMON_SLICE_CHICKEN3_PSThreadPanicDispatchMask_start 22 #define GFX11_COMMON_SLICE_CHICKEN3_PSThreadPanicDispatchMask_start 22 static inline uint32_t ATTRIBUTE_PURE COMMON_SLICE_CHICKEN3_PSThreadPanicDispatchMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 22; case 120: return 22; case 110: return 22; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* COMMON_SLICE_CHICKEN4 */ #define GFX125_COMMON_SLICE_CHICKEN4_length 1 #define GFX12_COMMON_SLICE_CHICKEN4_length 1 #define GFX11_COMMON_SLICE_CHICKEN4_length 1 static inline uint32_t ATTRIBUTE_PURE COMMON_SLICE_CHICKEN4_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* COMMON_SLICE_CHICKEN4::Enable Hardware Filtering in WM */ #define GFX125_COMMON_SLICE_CHICKEN4_EnableHardwareFilteringinWM_bits 1 #define GFX12_COMMON_SLICE_CHICKEN4_EnableHardwareFilteringinWM_bits 1 #define GFX11_COMMON_SLICE_CHICKEN4_EnableHardwareFilteringinWM_bits 1 static inline uint32_t ATTRIBUTE_PURE COMMON_SLICE_CHICKEN4_EnableHardwareFilteringinWM_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_COMMON_SLICE_CHICKEN4_EnableHardwareFilteringinWM_start 5 #define GFX12_COMMON_SLICE_CHICKEN4_EnableHardwareFilteringinWM_start 5 #define GFX11_COMMON_SLICE_CHICKEN4_EnableHardwareFilteringinWM_start 5 static inline uint32_t ATTRIBUTE_PURE COMMON_SLICE_CHICKEN4_EnableHardwareFilteringinWM_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 5; case 110: return 5; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* COMMON_SLICE_CHICKEN4::Enable Hardware Filtering in WM Mask */ #define GFX125_COMMON_SLICE_CHICKEN4_EnableHardwareFilteringinWMMask_bits 1 #define GFX12_COMMON_SLICE_CHICKEN4_EnableHardwareFilteringinWMMask_bits 1 #define GFX11_COMMON_SLICE_CHICKEN4_EnableHardwareFilteringinWMMask_bits 1 static inline uint32_t ATTRIBUTE_PURE COMMON_SLICE_CHICKEN4_EnableHardwareFilteringinWMMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_COMMON_SLICE_CHICKEN4_EnableHardwareFilteringinWMMask_start 21 #define GFX12_COMMON_SLICE_CHICKEN4_EnableHardwareFilteringinWMMask_start 21 #define GFX11_COMMON_SLICE_CHICKEN4_EnableHardwareFilteringinWMMask_start 21 static inline uint32_t ATTRIBUTE_PURE COMMON_SLICE_CHICKEN4_EnableHardwareFilteringinWMMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 21; case 120: return 21; case 110: return 21; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* COMPUTE_WALKER */ #define GFX125_COMPUTE_WALKER_length 39 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 39; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* COMPUTE_WALKER::CFE SubOpcode */ #define GFX125_COMPUTE_WALKER_CFESubOpcode_bits 6 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_CFESubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_COMPUTE_WALKER_CFESubOpcode_start 18 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_CFESubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 18; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* COMPUTE_WALKER::CFE SubOpcode Variant */ #define GFX125_COMPUTE_WALKER_CFESubOpcodeVariant_bits 2 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_CFESubOpcodeVariant_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_COMPUTE_WALKER_CFESubOpcodeVariant_start 16 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_CFESubOpcodeVariant_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* COMPUTE_WALKER::Command Type */ #define GFX125_COMPUTE_WALKER_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_COMPUTE_WALKER_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* COMPUTE_WALKER::Compute Command Opcode */ #define GFX125_COMPUTE_WALKER_ComputeCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_ComputeCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_COMPUTE_WALKER_ComputeCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_ComputeCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* COMPUTE_WALKER::DWord Length */ #define GFX125_COMPUTE_WALKER_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_COMPUTE_WALKER_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* COMPUTE_WALKER::Emit Inline Parameter */ #define GFX125_COMPUTE_WALKER_EmitInlineParameter_bits 1 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_EmitInlineParameter_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_COMPUTE_WALKER_EmitInlineParameter_start 153 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_EmitInlineParameter_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 153; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* COMPUTE_WALKER::Emit Local */ #define GFX125_COMPUTE_WALKER_EmitLocal_bits 3 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_EmitLocal_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_COMPUTE_WALKER_EmitLocal_start 154 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_EmitLocal_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 154; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* COMPUTE_WALKER::Execution Mask */ #define GFX125_COMPUTE_WALKER_ExecutionMask_bits 32 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_ExecutionMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_COMPUTE_WALKER_ExecutionMask_start 160 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_ExecutionMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 160; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* COMPUTE_WALKER::Generate Local ID */ #define GFX125_COMPUTE_WALKER_GenerateLocalID_bits 1 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_GenerateLocalID_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_COMPUTE_WALKER_GenerateLocalID_start 157 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_GenerateLocalID_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 157; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* COMPUTE_WALKER::Indirect Data Length */ #define GFX125_COMPUTE_WALKER_IndirectDataLength_bits 17 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_IndirectDataLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 17; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_COMPUTE_WALKER_IndirectDataLength_start 64 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_IndirectDataLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* COMPUTE_WALKER::Indirect Data Start Address */ #define GFX125_COMPUTE_WALKER_IndirectDataStartAddress_bits 26 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_IndirectDataStartAddress_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 26; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_COMPUTE_WALKER_IndirectDataStartAddress_start 102 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_IndirectDataStartAddress_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 102; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* COMPUTE_WALKER::Indirect Parameter Enable */ #define GFX125_COMPUTE_WALKER_IndirectParameterEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_IndirectParameterEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_COMPUTE_WALKER_IndirectParameterEnable_start 10 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_IndirectParameterEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 10; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* COMPUTE_WALKER::Interface Descriptor */ #define GFX125_COMPUTE_WALKER_InterfaceDescriptor_bits 256 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_InterfaceDescriptor_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 256; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_COMPUTE_WALKER_InterfaceDescriptor_start 576 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_InterfaceDescriptor_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 576; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* COMPUTE_WALKER::L3 prefetch disable */ #define GFX125_COMPUTE_WALKER_L3prefetchdisable_bits 1 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_L3prefetchdisable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_COMPUTE_WALKER_L3prefetchdisable_start 81 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_L3prefetchdisable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 81; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* COMPUTE_WALKER::Local X Maximum */ #define GFX125_COMPUTE_WALKER_LocalXMaximum_bits 10 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_LocalXMaximum_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 10; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_COMPUTE_WALKER_LocalXMaximum_start 192 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_LocalXMaximum_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 192; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* COMPUTE_WALKER::Local Y Maximum */ #define GFX125_COMPUTE_WALKER_LocalYMaximum_bits 10 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_LocalYMaximum_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 10; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_COMPUTE_WALKER_LocalYMaximum_start 202 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_LocalYMaximum_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 202; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* COMPUTE_WALKER::Local Z Maximum */ #define GFX125_COMPUTE_WALKER_LocalZMaximum_bits 10 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_LocalZMaximum_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 10; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_COMPUTE_WALKER_LocalZMaximum_start 212 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_LocalZMaximum_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 212; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* COMPUTE_WALKER::Message SIMD */ #define GFX125_COMPUTE_WALKER_MessageSIMD_bits 2 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_MessageSIMD_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_COMPUTE_WALKER_MessageSIMD_start 145 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_MessageSIMD_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 145; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* COMPUTE_WALKER::Partition ID */ #define GFX125_COMPUTE_WALKER_PartitionID_bits 32 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_PartitionID_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_COMPUTE_WALKER_PartitionID_start 416 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_PartitionID_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 416; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* COMPUTE_WALKER::Partition Size */ #define GFX125_COMPUTE_WALKER_PartitionSize_bits 32 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_PartitionSize_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_COMPUTE_WALKER_PartitionSize_start 448 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_PartitionSize_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 448; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* COMPUTE_WALKER::Partition Type */ #define GFX125_COMPUTE_WALKER_PartitionType_bits 2 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_PartitionType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_COMPUTE_WALKER_PartitionType_start 94 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_PartitionType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 94; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* COMPUTE_WALKER::Pipeline */ #define GFX125_COMPUTE_WALKER_Pipeline_bits 2 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_Pipeline_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_COMPUTE_WALKER_Pipeline_start 27 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_Pipeline_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* COMPUTE_WALKER::Post Sync */ #define GFX125_COMPUTE_WALKER_PostSync_bits 160 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_PostSync_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 160; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_COMPUTE_WALKER_PostSync_start 832 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_PostSync_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 832; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* COMPUTE_WALKER::Predicate Enable */ #define GFX125_COMPUTE_WALKER_PredicateEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_PredicateEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_COMPUTE_WALKER_PredicateEnable_start 8 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_PredicateEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* COMPUTE_WALKER::Preempt X */ #define GFX125_COMPUTE_WALKER_PreemptX_bits 32 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_PreemptX_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_COMPUTE_WALKER_PreemptX_start 480 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_PreemptX_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 480; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* COMPUTE_WALKER::Preempt Y */ #define GFX125_COMPUTE_WALKER_PreemptY_bits 32 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_PreemptY_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_COMPUTE_WALKER_PreemptY_start 512 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_PreemptY_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 512; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* COMPUTE_WALKER::Preempt Z */ #define GFX125_COMPUTE_WALKER_PreemptZ_bits 32 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_PreemptZ_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_COMPUTE_WALKER_PreemptZ_start 544 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_PreemptZ_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 544; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* COMPUTE_WALKER::SIMD Size */ #define GFX125_COMPUTE_WALKER_SIMDSize_bits 2 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_SIMDSize_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_COMPUTE_WALKER_SIMDSize_start 158 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_SIMDSize_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 158; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* COMPUTE_WALKER::Systolic Mode Enable */ #define GFX125_COMPUTE_WALKER_SystolicModeEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_SystolicModeEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_COMPUTE_WALKER_SystolicModeEnable_start 14 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_SystolicModeEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 14; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* COMPUTE_WALKER::Thread Group ID Starting X */ #define GFX125_COMPUTE_WALKER_ThreadGroupIDStartingX_bits 32 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_ThreadGroupIDStartingX_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_COMPUTE_WALKER_ThreadGroupIDStartingX_start 320 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_ThreadGroupIDStartingX_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 320; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* COMPUTE_WALKER::Thread Group ID Starting Y */ #define GFX125_COMPUTE_WALKER_ThreadGroupIDStartingY_bits 32 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_ThreadGroupIDStartingY_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_COMPUTE_WALKER_ThreadGroupIDStartingY_start 352 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_ThreadGroupIDStartingY_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 352; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* COMPUTE_WALKER::Thread Group ID Starting Z */ #define GFX125_COMPUTE_WALKER_ThreadGroupIDStartingZ_bits 32 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_ThreadGroupIDStartingZ_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_COMPUTE_WALKER_ThreadGroupIDStartingZ_start 384 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_ThreadGroupIDStartingZ_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 384; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* COMPUTE_WALKER::Thread Group ID X Dimension */ #define GFX125_COMPUTE_WALKER_ThreadGroupIDXDimension_bits 32 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_ThreadGroupIDXDimension_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_COMPUTE_WALKER_ThreadGroupIDXDimension_start 224 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_ThreadGroupIDXDimension_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 224; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* COMPUTE_WALKER::Thread Group ID Y Dimension */ #define GFX125_COMPUTE_WALKER_ThreadGroupIDYDimension_bits 32 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_ThreadGroupIDYDimension_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_COMPUTE_WALKER_ThreadGroupIDYDimension_start 256 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_ThreadGroupIDYDimension_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 256; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* COMPUTE_WALKER::Thread Group ID Z Dimension */ #define GFX125_COMPUTE_WALKER_ThreadGroupIDZDimension_bits 32 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_ThreadGroupIDZDimension_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_COMPUTE_WALKER_ThreadGroupIDZDimension_start 288 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_ThreadGroupIDZDimension_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 288; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* COMPUTE_WALKER::Tile Layout */ #define GFX125_COMPUTE_WALKER_TileLayout_bits 3 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_TileLayout_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_COMPUTE_WALKER_TileLayout_start 147 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_TileLayout_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 147; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* COMPUTE_WALKER::Walk Order */ #define GFX125_COMPUTE_WALKER_WalkOrder_bits 3 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_WalkOrder_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_COMPUTE_WALKER_WalkOrder_start 150 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_WalkOrder_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 150; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* COMPUTE_WALKER::Workload Partition Enable */ #define GFX125_COMPUTE_WALKER_WorkloadPartitionEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_WorkloadPartitionEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_COMPUTE_WALKER_WorkloadPartitionEnable_start 9 static inline uint32_t ATTRIBUTE_PURE COMPUTE_WALKER_WorkloadPartitionEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 9; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CONSTANT_BUFFER */ #define GFX5_CONSTANT_BUFFER_length 2 #define GFX45_CONSTANT_BUFFER_length 2 #define GFX4_CONSTANT_BUFFER_length 2 static inline uint32_t ATTRIBUTE_PURE CONSTANT_BUFFER_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 2; case 45: return 2; case 40: return 2; default: unreachable("Invalid hardware generation"); } } /* CONSTANT_BUFFER::3D Command Opcode */ #define GFX5_CONSTANT_BUFFER_3DCommandOpcode_bits 3 #define GFX45_CONSTANT_BUFFER_3DCommandOpcode_bits 3 #define GFX4_CONSTANT_BUFFER_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE CONSTANT_BUFFER_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX5_CONSTANT_BUFFER_3DCommandOpcode_start 24 #define GFX45_CONSTANT_BUFFER_3DCommandOpcode_start 24 #define GFX4_CONSTANT_BUFFER_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE CONSTANT_BUFFER_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 24; case 45: return 24; case 40: return 24; default: unreachable("Invalid hardware generation"); } } /* CONSTANT_BUFFER::3D Command Sub Opcode */ #define GFX5_CONSTANT_BUFFER_3DCommandSubOpcode_bits 8 #define GFX45_CONSTANT_BUFFER_3DCommandSubOpcode_bits 8 #define GFX4_CONSTANT_BUFFER_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE CONSTANT_BUFFER_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 8; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } #define GFX5_CONSTANT_BUFFER_3DCommandSubOpcode_start 16 #define GFX45_CONSTANT_BUFFER_3DCommandSubOpcode_start 16 #define GFX4_CONSTANT_BUFFER_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE CONSTANT_BUFFER_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 16; case 45: return 16; case 40: return 16; default: unreachable("Invalid hardware generation"); } } /* CONSTANT_BUFFER::Buffer Length */ #define GFX5_CONSTANT_BUFFER_BufferLength_bits 6 #define GFX45_CONSTANT_BUFFER_BufferLength_bits 6 #define GFX4_CONSTANT_BUFFER_BufferLength_bits 6 static inline uint32_t ATTRIBUTE_PURE CONSTANT_BUFFER_BufferLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 6; case 45: return 6; case 40: return 6; default: unreachable("Invalid hardware generation"); } } #define GFX5_CONSTANT_BUFFER_BufferLength_start 32 #define GFX45_CONSTANT_BUFFER_BufferLength_start 32 #define GFX4_CONSTANT_BUFFER_BufferLength_start 32 static inline uint32_t ATTRIBUTE_PURE CONSTANT_BUFFER_BufferLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 32; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } /* CONSTANT_BUFFER::Buffer Starting Address */ #define GFX5_CONSTANT_BUFFER_BufferStartingAddress_bits 26 #define GFX45_CONSTANT_BUFFER_BufferStartingAddress_bits 26 #define GFX4_CONSTANT_BUFFER_BufferStartingAddress_bits 26 static inline uint32_t ATTRIBUTE_PURE CONSTANT_BUFFER_BufferStartingAddress_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 26; case 45: return 26; case 40: return 26; default: unreachable("Invalid hardware generation"); } } #define GFX5_CONSTANT_BUFFER_BufferStartingAddress_start 38 #define GFX45_CONSTANT_BUFFER_BufferStartingAddress_start 38 #define GFX4_CONSTANT_BUFFER_BufferStartingAddress_start 38 static inline uint32_t ATTRIBUTE_PURE CONSTANT_BUFFER_BufferStartingAddress_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 38; case 45: return 38; case 40: return 38; default: unreachable("Invalid hardware generation"); } } /* CONSTANT_BUFFER::Command SubType */ #define GFX5_CONSTANT_BUFFER_CommandSubType_bits 2 #define GFX45_CONSTANT_BUFFER_CommandSubType_bits 2 #define GFX4_CONSTANT_BUFFER_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE CONSTANT_BUFFER_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 2; case 45: return 2; case 40: return 2; default: unreachable("Invalid hardware generation"); } } #define GFX5_CONSTANT_BUFFER_CommandSubType_start 27 #define GFX45_CONSTANT_BUFFER_CommandSubType_start 27 #define GFX4_CONSTANT_BUFFER_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE CONSTANT_BUFFER_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 27; case 45: return 27; case 40: return 27; default: unreachable("Invalid hardware generation"); } } /* CONSTANT_BUFFER::Command Type */ #define GFX5_CONSTANT_BUFFER_CommandType_bits 3 #define GFX45_CONSTANT_BUFFER_CommandType_bits 3 #define GFX4_CONSTANT_BUFFER_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE CONSTANT_BUFFER_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX5_CONSTANT_BUFFER_CommandType_start 29 #define GFX45_CONSTANT_BUFFER_CommandType_start 29 #define GFX4_CONSTANT_BUFFER_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE CONSTANT_BUFFER_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 29; case 45: return 29; case 40: return 29; default: unreachable("Invalid hardware generation"); } } /* CONSTANT_BUFFER::DWord Length */ #define GFX5_CONSTANT_BUFFER_DWordLength_bits 8 #define GFX45_CONSTANT_BUFFER_DWordLength_bits 8 #define GFX4_CONSTANT_BUFFER_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE CONSTANT_BUFFER_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 8; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } #define GFX5_CONSTANT_BUFFER_DWordLength_start 0 #define GFX45_CONSTANT_BUFFER_DWordLength_start 0 #define GFX4_CONSTANT_BUFFER_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE CONSTANT_BUFFER_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CONSTANT_BUFFER::Valid */ #define GFX5_CONSTANT_BUFFER_Valid_bits 1 #define GFX45_CONSTANT_BUFFER_Valid_bits 1 #define GFX4_CONSTANT_BUFFER_Valid_bits 1 static inline uint32_t ATTRIBUTE_PURE CONSTANT_BUFFER_Valid_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_CONSTANT_BUFFER_Valid_start 8 #define GFX45_CONSTANT_BUFFER_Valid_start 8 #define GFX4_CONSTANT_BUFFER_Valid_start 8 static inline uint32_t ATTRIBUTE_PURE CONSTANT_BUFFER_Valid_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 8; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } /* CPS_STATE */ #define GFX125_CPS_STATE_length 8 #define GFX12_CPS_STATE_length 8 static inline uint32_t ATTRIBUTE_PURE CPS_STATE_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CPS_STATE::Aspect */ #define GFX125_CPS_STATE_Aspect_bits 32 #define GFX12_CPS_STATE_Aspect_bits 32 static inline uint32_t ATTRIBUTE_PURE CPS_STATE_Aspect_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CPS_STATE_Aspect_start 224 #define GFX12_CPS_STATE_Aspect_start 224 static inline uint32_t ATTRIBUTE_PURE CPS_STATE_Aspect_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 224; case 120: return 224; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CPS_STATE::Coarse Pixel Shading Mode */ #define GFX125_CPS_STATE_CoarsePixelShadingMode_bits 2 #define GFX12_CPS_STATE_CoarsePixelShadingMode_bits 2 static inline uint32_t ATTRIBUTE_PURE CPS_STATE_CoarsePixelShadingMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CPS_STATE_CoarsePixelShadingMode_start 12 #define GFX12_CPS_STATE_CoarsePixelShadingMode_start 12 static inline uint32_t ATTRIBUTE_PURE CPS_STATE_CoarsePixelShadingMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 12; case 120: return 12; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CPS_STATE::Max CP Size X */ #define GFX125_CPS_STATE_MaxCPSizeX_bits 11 #define GFX12_CPS_STATE_MaxCPSizeX_bits 11 static inline uint32_t ATTRIBUTE_PURE CPS_STATE_MaxCPSizeX_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 11; case 120: return 11; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CPS_STATE_MaxCPSizeX_start 32 #define GFX12_CPS_STATE_MaxCPSizeX_start 32 static inline uint32_t ATTRIBUTE_PURE CPS_STATE_MaxCPSizeX_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CPS_STATE::Max CP Size Y */ #define GFX125_CPS_STATE_MaxCPSizeY_bits 11 #define GFX12_CPS_STATE_MaxCPSizeY_bits 11 static inline uint32_t ATTRIBUTE_PURE CPS_STATE_MaxCPSizeY_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 11; case 120: return 11; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CPS_STATE_MaxCPSizeY_start 48 #define GFX12_CPS_STATE_MaxCPSizeY_start 48 static inline uint32_t ATTRIBUTE_PURE CPS_STATE_MaxCPSizeY_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 48; case 120: return 48; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CPS_STATE::Min CP Size X */ #define GFX125_CPS_STATE_MinCPSizeX_bits 11 #define GFX12_CPS_STATE_MinCPSizeX_bits 11 static inline uint32_t ATTRIBUTE_PURE CPS_STATE_MinCPSizeX_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 11; case 120: return 11; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CPS_STATE_MinCPSizeX_start 0 #define GFX12_CPS_STATE_MinCPSizeX_start 0 static inline uint32_t ATTRIBUTE_PURE CPS_STATE_MinCPSizeX_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CPS_STATE::Min CP Size Y */ #define GFX125_CPS_STATE_MinCPSizeY_bits 11 #define GFX12_CPS_STATE_MinCPSizeY_bits 11 static inline uint32_t ATTRIBUTE_PURE CPS_STATE_MinCPSizeY_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 11; case 120: return 11; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CPS_STATE_MinCPSizeY_start 16 #define GFX12_CPS_STATE_MinCPSizeY_start 16 static inline uint32_t ATTRIBUTE_PURE CPS_STATE_MinCPSizeY_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CPS_STATE::M x */ #define GFX125_CPS_STATE_Mx_bits 32 #define GFX12_CPS_STATE_Mx_bits 32 static inline uint32_t ATTRIBUTE_PURE CPS_STATE_Mx_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CPS_STATE_Mx_start 160 #define GFX12_CPS_STATE_Mx_start 160 static inline uint32_t ATTRIBUTE_PURE CPS_STATE_Mx_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 160; case 120: return 160; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CPS_STATE::M y */ #define GFX125_CPS_STATE_My_bits 32 #define GFX12_CPS_STATE_My_bits 32 static inline uint32_t ATTRIBUTE_PURE CPS_STATE_My_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CPS_STATE_My_start 128 #define GFX12_CPS_STATE_My_start 128 static inline uint32_t ATTRIBUTE_PURE CPS_STATE_My_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 128; case 120: return 128; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CPS_STATE::R min */ #define GFX125_CPS_STATE_Rmin_bits 32 #define GFX12_CPS_STATE_Rmin_bits 32 static inline uint32_t ATTRIBUTE_PURE CPS_STATE_Rmin_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CPS_STATE_Rmin_start 192 #define GFX12_CPS_STATE_Rmin_start 192 static inline uint32_t ATTRIBUTE_PURE CPS_STATE_Rmin_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 192; case 120: return 192; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CPS_STATE::Scale Axis */ #define GFX125_CPS_STATE_ScaleAxis_bits 1 #define GFX12_CPS_STATE_ScaleAxis_bits 1 static inline uint32_t ATTRIBUTE_PURE CPS_STATE_ScaleAxis_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CPS_STATE_ScaleAxis_start 14 #define GFX12_CPS_STATE_ScaleAxis_start 14 static inline uint32_t ATTRIBUTE_PURE CPS_STATE_ScaleAxis_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 14; case 120: return 14; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CPS_STATE::Statistics Enable */ #define GFX125_CPS_STATE_StatisticsEnable_bits 1 #define GFX12_CPS_STATE_StatisticsEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE CPS_STATE_StatisticsEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CPS_STATE_StatisticsEnable_start 11 #define GFX12_CPS_STATE_StatisticsEnable_start 11 static inline uint32_t ATTRIBUTE_PURE CPS_STATE_StatisticsEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 11; case 120: return 11; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CPS_STATE::X Focal */ #define GFX125_CPS_STATE_XFocal_bits 16 #define GFX12_CPS_STATE_XFocal_bits 16 static inline uint32_t ATTRIBUTE_PURE CPS_STATE_XFocal_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CPS_STATE_XFocal_start 96 #define GFX12_CPS_STATE_XFocal_start 96 static inline uint32_t ATTRIBUTE_PURE CPS_STATE_XFocal_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 96; case 120: return 96; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CPS_STATE::Y Focal */ #define GFX125_CPS_STATE_YFocal_bits 16 #define GFX12_CPS_STATE_YFocal_bits 16 static inline uint32_t ATTRIBUTE_PURE CPS_STATE_YFocal_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CPS_STATE_YFocal_start 64 #define GFX12_CPS_STATE_YFocal_start 64 static inline uint32_t ATTRIBUTE_PURE CPS_STATE_YFocal_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CS_CHICKEN1 */ #define GFX125_CS_CHICKEN1_length 1 #define GFX12_CS_CHICKEN1_length 1 #define GFX11_CS_CHICKEN1_length 1 #define GFX9_CS_CHICKEN1_length 1 static inline uint32_t ATTRIBUTE_PURE CS_CHICKEN1_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CS_CHICKEN1::Replay Mode */ #define GFX125_CS_CHICKEN1_ReplayMode_bits 1 #define GFX12_CS_CHICKEN1_ReplayMode_bits 1 #define GFX11_CS_CHICKEN1_ReplayMode_bits 1 #define GFX9_CS_CHICKEN1_ReplayMode_bits 1 static inline uint32_t ATTRIBUTE_PURE CS_CHICKEN1_ReplayMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CS_CHICKEN1_ReplayMode_start 0 #define GFX12_CS_CHICKEN1_ReplayMode_start 0 #define GFX11_CS_CHICKEN1_ReplayMode_start 0 #define GFX9_CS_CHICKEN1_ReplayMode_start 0 static inline uint32_t ATTRIBUTE_PURE CS_CHICKEN1_ReplayMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CS_CHICKEN1::Replay Mode Mask */ #define GFX125_CS_CHICKEN1_ReplayModeMask_bits 1 #define GFX12_CS_CHICKEN1_ReplayModeMask_bits 1 #define GFX11_CS_CHICKEN1_ReplayModeMask_bits 1 #define GFX9_CS_CHICKEN1_ReplayModeMask_bits 1 static inline uint32_t ATTRIBUTE_PURE CS_CHICKEN1_ReplayModeMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CS_CHICKEN1_ReplayModeMask_start 16 #define GFX12_CS_CHICKEN1_ReplayModeMask_start 16 #define GFX11_CS_CHICKEN1_ReplayModeMask_start 16 #define GFX9_CS_CHICKEN1_ReplayModeMask_start 16 static inline uint32_t ATTRIBUTE_PURE CS_CHICKEN1_ReplayModeMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CS_DEBUG_MODE2 */ #define GFX125_CS_DEBUG_MODE2_length 1 #define GFX12_CS_DEBUG_MODE2_length 1 #define GFX11_CS_DEBUG_MODE2_length 1 #define GFX9_CS_DEBUG_MODE2_length 1 static inline uint32_t ATTRIBUTE_PURE CS_DEBUG_MODE2_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CS_DEBUG_MODE2::3D Rendering Instruction Disable */ #define GFX125_CS_DEBUG_MODE2_3DRenderingInstructionDisable_bits 1 #define GFX12_CS_DEBUG_MODE2_3DRenderingInstructionDisable_bits 1 #define GFX11_CS_DEBUG_MODE2_3DRenderingInstructionDisable_bits 1 #define GFX9_CS_DEBUG_MODE2_3DRenderingInstructionDisable_bits 1 static inline uint32_t ATTRIBUTE_PURE CS_DEBUG_MODE2_3DRenderingInstructionDisable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CS_DEBUG_MODE2_3DRenderingInstructionDisable_start 0 #define GFX12_CS_DEBUG_MODE2_3DRenderingInstructionDisable_start 0 #define GFX11_CS_DEBUG_MODE2_3DRenderingInstructionDisable_start 0 #define GFX9_CS_DEBUG_MODE2_3DRenderingInstructionDisable_start 0 static inline uint32_t ATTRIBUTE_PURE CS_DEBUG_MODE2_3DRenderingInstructionDisable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CS_DEBUG_MODE2::3D Rendering Instruction Disable Mask */ #define GFX125_CS_DEBUG_MODE2_3DRenderingInstructionDisableMask_bits 1 #define GFX12_CS_DEBUG_MODE2_3DRenderingInstructionDisableMask_bits 1 #define GFX11_CS_DEBUG_MODE2_3DRenderingInstructionDisableMask_bits 1 #define GFX9_CS_DEBUG_MODE2_3DRenderingInstructionDisableMask_bits 1 static inline uint32_t ATTRIBUTE_PURE CS_DEBUG_MODE2_3DRenderingInstructionDisableMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CS_DEBUG_MODE2_3DRenderingInstructionDisableMask_start 16 #define GFX12_CS_DEBUG_MODE2_3DRenderingInstructionDisableMask_start 16 #define GFX11_CS_DEBUG_MODE2_3DRenderingInstructionDisableMask_start 16 #define GFX9_CS_DEBUG_MODE2_3DRenderingInstructionDisableMask_start 16 static inline uint32_t ATTRIBUTE_PURE CS_DEBUG_MODE2_3DRenderingInstructionDisableMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CS_DEBUG_MODE2::CONSTANT_BUFFER Address Offset Disable */ #define GFX125_CS_DEBUG_MODE2_CONSTANT_BUFFERAddressOffsetDisable_bits 1 #define GFX12_CS_DEBUG_MODE2_CONSTANT_BUFFERAddressOffsetDisable_bits 1 #define GFX11_CS_DEBUG_MODE2_CONSTANT_BUFFERAddressOffsetDisable_bits 1 #define GFX9_CS_DEBUG_MODE2_CONSTANT_BUFFERAddressOffsetDisable_bits 1 static inline uint32_t ATTRIBUTE_PURE CS_DEBUG_MODE2_CONSTANT_BUFFERAddressOffsetDisable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CS_DEBUG_MODE2_CONSTANT_BUFFERAddressOffsetDisable_start 4 #define GFX12_CS_DEBUG_MODE2_CONSTANT_BUFFERAddressOffsetDisable_start 4 #define GFX11_CS_DEBUG_MODE2_CONSTANT_BUFFERAddressOffsetDisable_start 4 #define GFX9_CS_DEBUG_MODE2_CONSTANT_BUFFERAddressOffsetDisable_start 4 static inline uint32_t ATTRIBUTE_PURE CS_DEBUG_MODE2_CONSTANT_BUFFERAddressOffsetDisable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CS_DEBUG_MODE2::CONSTANT_BUFFER Address Offset Disable Mask */ #define GFX125_CS_DEBUG_MODE2_CONSTANT_BUFFERAddressOffsetDisableMask_bits 1 #define GFX12_CS_DEBUG_MODE2_CONSTANT_BUFFERAddressOffsetDisableMask_bits 1 #define GFX11_CS_DEBUG_MODE2_CONSTANT_BUFFERAddressOffsetDisableMask_bits 1 #define GFX9_CS_DEBUG_MODE2_CONSTANT_BUFFERAddressOffsetDisableMask_bits 1 static inline uint32_t ATTRIBUTE_PURE CS_DEBUG_MODE2_CONSTANT_BUFFERAddressOffsetDisableMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CS_DEBUG_MODE2_CONSTANT_BUFFERAddressOffsetDisableMask_start 20 #define GFX12_CS_DEBUG_MODE2_CONSTANT_BUFFERAddressOffsetDisableMask_start 20 #define GFX11_CS_DEBUG_MODE2_CONSTANT_BUFFERAddressOffsetDisableMask_start 20 #define GFX9_CS_DEBUG_MODE2_CONSTANT_BUFFERAddressOffsetDisableMask_start 20 static inline uint32_t ATTRIBUTE_PURE CS_DEBUG_MODE2_CONSTANT_BUFFERAddressOffsetDisableMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 20; case 120: return 20; case 110: return 20; case 90: return 20; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CS_DEBUG_MODE2::Media Instruction Disable */ #define GFX125_CS_DEBUG_MODE2_MediaInstructionDisable_bits 1 #define GFX12_CS_DEBUG_MODE2_MediaInstructionDisable_bits 1 #define GFX11_CS_DEBUG_MODE2_MediaInstructionDisable_bits 1 #define GFX9_CS_DEBUG_MODE2_MediaInstructionDisable_bits 1 static inline uint32_t ATTRIBUTE_PURE CS_DEBUG_MODE2_MediaInstructionDisable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CS_DEBUG_MODE2_MediaInstructionDisable_start 1 #define GFX12_CS_DEBUG_MODE2_MediaInstructionDisable_start 1 #define GFX11_CS_DEBUG_MODE2_MediaInstructionDisable_start 1 #define GFX9_CS_DEBUG_MODE2_MediaInstructionDisable_start 1 static inline uint32_t ATTRIBUTE_PURE CS_DEBUG_MODE2_MediaInstructionDisable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CS_DEBUG_MODE2::Media Instruction Disable Mask */ #define GFX125_CS_DEBUG_MODE2_MediaInstructionDisableMask_bits 1 #define GFX12_CS_DEBUG_MODE2_MediaInstructionDisableMask_bits 1 #define GFX11_CS_DEBUG_MODE2_MediaInstructionDisableMask_bits 1 #define GFX9_CS_DEBUG_MODE2_MediaInstructionDisableMask_bits 1 static inline uint32_t ATTRIBUTE_PURE CS_DEBUG_MODE2_MediaInstructionDisableMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CS_DEBUG_MODE2_MediaInstructionDisableMask_start 17 #define GFX12_CS_DEBUG_MODE2_MediaInstructionDisableMask_start 17 #define GFX11_CS_DEBUG_MODE2_MediaInstructionDisableMask_start 17 #define GFX9_CS_DEBUG_MODE2_MediaInstructionDisableMask_start 17 static inline uint32_t ATTRIBUTE_PURE CS_DEBUG_MODE2_MediaInstructionDisableMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 17; case 120: return 17; case 110: return 17; case 90: return 17; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CS_INVOCATION_COUNT */ #define GFX125_CS_INVOCATION_COUNT_length 2 #define GFX12_CS_INVOCATION_COUNT_length 2 #define GFX11_CS_INVOCATION_COUNT_length 2 #define GFX9_CS_INVOCATION_COUNT_length 2 #define GFX8_CS_INVOCATION_COUNT_length 2 #define GFX75_CS_INVOCATION_COUNT_length 2 #define GFX7_CS_INVOCATION_COUNT_length 2 static inline uint32_t ATTRIBUTE_PURE CS_INVOCATION_COUNT_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CS_INVOCATION_COUNT::CS Invocation Count Report */ #define GFX125_CS_INVOCATION_COUNT_CSInvocationCountReport_bits 64 #define GFX12_CS_INVOCATION_COUNT_CSInvocationCountReport_bits 64 #define GFX11_CS_INVOCATION_COUNT_CSInvocationCountReport_bits 64 #define GFX9_CS_INVOCATION_COUNT_CSInvocationCountReport_bits 64 #define GFX8_CS_INVOCATION_COUNT_CSInvocationCountReport_bits 64 #define GFX75_CS_INVOCATION_COUNT_CSInvocationCountReport_bits 64 #define GFX7_CS_INVOCATION_COUNT_CSInvocationCountReport_bits 64 static inline uint32_t ATTRIBUTE_PURE CS_INVOCATION_COUNT_CSInvocationCountReport_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 64; case 80: return 64; case 75: return 64; case 70: return 64; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_CS_INVOCATION_COUNT_CSInvocationCountReport_start 0 #define GFX12_CS_INVOCATION_COUNT_CSInvocationCountReport_start 0 #define GFX11_CS_INVOCATION_COUNT_CSInvocationCountReport_start 0 #define GFX9_CS_INVOCATION_COUNT_CSInvocationCountReport_start 0 #define GFX8_CS_INVOCATION_COUNT_CSInvocationCountReport_start 0 #define GFX75_CS_INVOCATION_COUNT_CSInvocationCountReport_start 0 #define GFX7_CS_INVOCATION_COUNT_CSInvocationCountReport_start 0 static inline uint32_t ATTRIBUTE_PURE CS_INVOCATION_COUNT_CSInvocationCountReport_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CS_URB_STATE */ #define GFX5_CS_URB_STATE_length 2 #define GFX45_CS_URB_STATE_length 2 #define GFX4_CS_URB_STATE_length 2 static inline uint32_t ATTRIBUTE_PURE CS_URB_STATE_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 2; case 45: return 2; case 40: return 2; default: unreachable("Invalid hardware generation"); } } /* CS_URB_STATE::3D Command Opcode */ #define GFX5_CS_URB_STATE_3DCommandOpcode_bits 3 #define GFX45_CS_URB_STATE_3DCommandOpcode_bits 3 #define GFX4_CS_URB_STATE_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE CS_URB_STATE_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX5_CS_URB_STATE_3DCommandOpcode_start 24 #define GFX45_CS_URB_STATE_3DCommandOpcode_start 24 #define GFX4_CS_URB_STATE_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE CS_URB_STATE_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 24; case 45: return 24; case 40: return 24; default: unreachable("Invalid hardware generation"); } } /* CS_URB_STATE::3D Command Sub Opcode */ #define GFX5_CS_URB_STATE_3DCommandSubOpcode_bits 8 #define GFX45_CS_URB_STATE_3DCommandSubOpcode_bits 8 #define GFX4_CS_URB_STATE_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE CS_URB_STATE_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 8; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } #define GFX5_CS_URB_STATE_3DCommandSubOpcode_start 16 #define GFX45_CS_URB_STATE_3DCommandSubOpcode_start 16 #define GFX4_CS_URB_STATE_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE CS_URB_STATE_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 16; case 45: return 16; case 40: return 16; default: unreachable("Invalid hardware generation"); } } /* CS_URB_STATE::Command SubType */ #define GFX5_CS_URB_STATE_CommandSubType_bits 2 #define GFX45_CS_URB_STATE_CommandSubType_bits 2 #define GFX4_CS_URB_STATE_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE CS_URB_STATE_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 2; case 45: return 2; case 40: return 2; default: unreachable("Invalid hardware generation"); } } #define GFX5_CS_URB_STATE_CommandSubType_start 27 #define GFX45_CS_URB_STATE_CommandSubType_start 27 #define GFX4_CS_URB_STATE_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE CS_URB_STATE_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 27; case 45: return 27; case 40: return 27; default: unreachable("Invalid hardware generation"); } } /* CS_URB_STATE::Command Type */ #define GFX5_CS_URB_STATE_CommandType_bits 3 #define GFX45_CS_URB_STATE_CommandType_bits 3 #define GFX4_CS_URB_STATE_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE CS_URB_STATE_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX5_CS_URB_STATE_CommandType_start 29 #define GFX45_CS_URB_STATE_CommandType_start 29 #define GFX4_CS_URB_STATE_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE CS_URB_STATE_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 29; case 45: return 29; case 40: return 29; default: unreachable("Invalid hardware generation"); } } /* CS_URB_STATE::DWord Length */ #define GFX5_CS_URB_STATE_DWordLength_bits 8 #define GFX45_CS_URB_STATE_DWordLength_bits 8 #define GFX4_CS_URB_STATE_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE CS_URB_STATE_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 8; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } #define GFX5_CS_URB_STATE_DWordLength_start 0 #define GFX45_CS_URB_STATE_DWordLength_start 0 #define GFX4_CS_URB_STATE_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE CS_URB_STATE_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* CS_URB_STATE::Number of URB Entries */ #define GFX5_CS_URB_STATE_NumberofURBEntries_bits 3 #define GFX45_CS_URB_STATE_NumberofURBEntries_bits 3 #define GFX4_CS_URB_STATE_NumberofURBEntries_bits 3 static inline uint32_t ATTRIBUTE_PURE CS_URB_STATE_NumberofURBEntries_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX5_CS_URB_STATE_NumberofURBEntries_start 32 #define GFX45_CS_URB_STATE_NumberofURBEntries_start 32 #define GFX4_CS_URB_STATE_NumberofURBEntries_start 32 static inline uint32_t ATTRIBUTE_PURE CS_URB_STATE_NumberofURBEntries_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 32; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } /* CS_URB_STATE::URB Entry Allocation Size */ #define GFX5_CS_URB_STATE_URBEntryAllocationSize_bits 5 #define GFX45_CS_URB_STATE_URBEntryAllocationSize_bits 5 #define GFX4_CS_URB_STATE_URBEntryAllocationSize_bits 5 static inline uint32_t ATTRIBUTE_PURE CS_URB_STATE_URBEntryAllocationSize_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 5; case 45: return 5; case 40: return 5; default: unreachable("Invalid hardware generation"); } } #define GFX5_CS_URB_STATE_URBEntryAllocationSize_start 36 #define GFX45_CS_URB_STATE_URBEntryAllocationSize_start 36 #define GFX4_CS_URB_STATE_URBEntryAllocationSize_start 36 static inline uint32_t ATTRIBUTE_PURE CS_URB_STATE_URBEntryAllocationSize_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 36; case 45: return 36; case 40: return 36; default: unreachable("Invalid hardware generation"); } } /* DEPTH_STENCIL_STATE */ #define GFX75_DEPTH_STENCIL_STATE_length 3 #define GFX7_DEPTH_STENCIL_STATE_length 3 #define GFX6_DEPTH_STENCIL_STATE_length 3 static inline uint32_t ATTRIBUTE_PURE DEPTH_STENCIL_STATE_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* DEPTH_STENCIL_STATE::Backface Stencil Fail Op */ #define GFX75_DEPTH_STENCIL_STATE_BackfaceStencilFailOp_bits 3 #define GFX7_DEPTH_STENCIL_STATE_BackfaceStencilFailOp_bits 3 #define GFX6_DEPTH_STENCIL_STATE_BackfaceStencilFailOp_bits 3 static inline uint32_t ATTRIBUTE_PURE DEPTH_STENCIL_STATE_BackfaceStencilFailOp_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_DEPTH_STENCIL_STATE_BackfaceStencilFailOp_start 9 #define GFX7_DEPTH_STENCIL_STATE_BackfaceStencilFailOp_start 9 #define GFX6_DEPTH_STENCIL_STATE_BackfaceStencilFailOp_start 9 static inline uint32_t ATTRIBUTE_PURE DEPTH_STENCIL_STATE_BackfaceStencilFailOp_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 9; case 70: return 9; case 60: return 9; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* DEPTH_STENCIL_STATE::Backface Stencil Pass Depth Fail Op */ #define GFX75_DEPTH_STENCIL_STATE_BackfaceStencilPassDepthFailOp_bits 3 #define GFX7_DEPTH_STENCIL_STATE_BackfaceStencilPassDepthFailOp_bits 3 #define GFX6_DEPTH_STENCIL_STATE_BackfaceStencilPassDepthFailOp_bits 3 static inline uint32_t ATTRIBUTE_PURE DEPTH_STENCIL_STATE_BackfaceStencilPassDepthFailOp_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_DEPTH_STENCIL_STATE_BackfaceStencilPassDepthFailOp_start 6 #define GFX7_DEPTH_STENCIL_STATE_BackfaceStencilPassDepthFailOp_start 6 #define GFX6_DEPTH_STENCIL_STATE_BackfaceStencilPassDepthFailOp_start 6 static inline uint32_t ATTRIBUTE_PURE DEPTH_STENCIL_STATE_BackfaceStencilPassDepthFailOp_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 6; case 70: return 6; case 60: return 6; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* DEPTH_STENCIL_STATE::Backface Stencil Pass Depth Pass Op */ #define GFX75_DEPTH_STENCIL_STATE_BackfaceStencilPassDepthPassOp_bits 3 #define GFX7_DEPTH_STENCIL_STATE_BackfaceStencilPassDepthPassOp_bits 3 #define GFX6_DEPTH_STENCIL_STATE_BackfaceStencilPassDepthPassOp_bits 3 static inline uint32_t ATTRIBUTE_PURE DEPTH_STENCIL_STATE_BackfaceStencilPassDepthPassOp_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_DEPTH_STENCIL_STATE_BackfaceStencilPassDepthPassOp_start 3 #define GFX7_DEPTH_STENCIL_STATE_BackfaceStencilPassDepthPassOp_start 3 #define GFX6_DEPTH_STENCIL_STATE_BackfaceStencilPassDepthPassOp_start 3 static inline uint32_t ATTRIBUTE_PURE DEPTH_STENCIL_STATE_BackfaceStencilPassDepthPassOp_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* DEPTH_STENCIL_STATE::Backface Stencil Test Function */ #define GFX75_DEPTH_STENCIL_STATE_BackfaceStencilTestFunction_bits 3 #define GFX7_DEPTH_STENCIL_STATE_BackfaceStencilTestFunction_bits 3 #define GFX6_DEPTH_STENCIL_STATE_BackfaceStencilTestFunction_bits 3 static inline uint32_t ATTRIBUTE_PURE DEPTH_STENCIL_STATE_BackfaceStencilTestFunction_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_DEPTH_STENCIL_STATE_BackfaceStencilTestFunction_start 12 #define GFX7_DEPTH_STENCIL_STATE_BackfaceStencilTestFunction_start 12 #define GFX6_DEPTH_STENCIL_STATE_BackfaceStencilTestFunction_start 12 static inline uint32_t ATTRIBUTE_PURE DEPTH_STENCIL_STATE_BackfaceStencilTestFunction_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 12; case 70: return 12; case 60: return 12; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* DEPTH_STENCIL_STATE::Backface Stencil Test Mask */ #define GFX75_DEPTH_STENCIL_STATE_BackfaceStencilTestMask_bits 8 #define GFX7_DEPTH_STENCIL_STATE_BackfaceStencilTestMask_bits 8 #define GFX6_DEPTH_STENCIL_STATE_BackfaceStencilTestMask_bits 8 static inline uint32_t ATTRIBUTE_PURE DEPTH_STENCIL_STATE_BackfaceStencilTestMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_DEPTH_STENCIL_STATE_BackfaceStencilTestMask_start 40 #define GFX7_DEPTH_STENCIL_STATE_BackfaceStencilTestMask_start 40 #define GFX6_DEPTH_STENCIL_STATE_BackfaceStencilTestMask_start 40 static inline uint32_t ATTRIBUTE_PURE DEPTH_STENCIL_STATE_BackfaceStencilTestMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 40; case 70: return 40; case 60: return 40; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* DEPTH_STENCIL_STATE::Backface Stencil Write Mask */ #define GFX75_DEPTH_STENCIL_STATE_BackfaceStencilWriteMask_bits 8 #define GFX7_DEPTH_STENCIL_STATE_BackfaceStencilWriteMask_bits 8 #define GFX6_DEPTH_STENCIL_STATE_BackfaceStencilWriteMask_bits 8 static inline uint32_t ATTRIBUTE_PURE DEPTH_STENCIL_STATE_BackfaceStencilWriteMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_DEPTH_STENCIL_STATE_BackfaceStencilWriteMask_start 32 #define GFX7_DEPTH_STENCIL_STATE_BackfaceStencilWriteMask_start 32 #define GFX6_DEPTH_STENCIL_STATE_BackfaceStencilWriteMask_start 32 static inline uint32_t ATTRIBUTE_PURE DEPTH_STENCIL_STATE_BackfaceStencilWriteMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 32; case 70: return 32; case 60: return 32; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* DEPTH_STENCIL_STATE::Depth Buffer Write Enable */ #define GFX75_DEPTH_STENCIL_STATE_DepthBufferWriteEnable_bits 1 #define GFX7_DEPTH_STENCIL_STATE_DepthBufferWriteEnable_bits 1 #define GFX6_DEPTH_STENCIL_STATE_DepthBufferWriteEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE DEPTH_STENCIL_STATE_DepthBufferWriteEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_DEPTH_STENCIL_STATE_DepthBufferWriteEnable_start 90 #define GFX7_DEPTH_STENCIL_STATE_DepthBufferWriteEnable_start 90 #define GFX6_DEPTH_STENCIL_STATE_DepthBufferWriteEnable_start 90 static inline uint32_t ATTRIBUTE_PURE DEPTH_STENCIL_STATE_DepthBufferWriteEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 90; case 70: return 90; case 60: return 90; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* DEPTH_STENCIL_STATE::Depth Test Enable */ #define GFX75_DEPTH_STENCIL_STATE_DepthTestEnable_bits 1 #define GFX7_DEPTH_STENCIL_STATE_DepthTestEnable_bits 1 #define GFX6_DEPTH_STENCIL_STATE_DepthTestEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE DEPTH_STENCIL_STATE_DepthTestEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_DEPTH_STENCIL_STATE_DepthTestEnable_start 95 #define GFX7_DEPTH_STENCIL_STATE_DepthTestEnable_start 95 #define GFX6_DEPTH_STENCIL_STATE_DepthTestEnable_start 95 static inline uint32_t ATTRIBUTE_PURE DEPTH_STENCIL_STATE_DepthTestEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 95; case 70: return 95; case 60: return 95; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* DEPTH_STENCIL_STATE::Depth Test Function */ #define GFX75_DEPTH_STENCIL_STATE_DepthTestFunction_bits 3 #define GFX7_DEPTH_STENCIL_STATE_DepthTestFunction_bits 3 #define GFX6_DEPTH_STENCIL_STATE_DepthTestFunction_bits 3 static inline uint32_t ATTRIBUTE_PURE DEPTH_STENCIL_STATE_DepthTestFunction_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_DEPTH_STENCIL_STATE_DepthTestFunction_start 91 #define GFX7_DEPTH_STENCIL_STATE_DepthTestFunction_start 91 #define GFX6_DEPTH_STENCIL_STATE_DepthTestFunction_start 91 static inline uint32_t ATTRIBUTE_PURE DEPTH_STENCIL_STATE_DepthTestFunction_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 91; case 70: return 91; case 60: return 91; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* DEPTH_STENCIL_STATE::Double Sided Stencil Enable */ #define GFX75_DEPTH_STENCIL_STATE_DoubleSidedStencilEnable_bits 1 #define GFX7_DEPTH_STENCIL_STATE_DoubleSidedStencilEnable_bits 1 #define GFX6_DEPTH_STENCIL_STATE_DoubleSidedStencilEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE DEPTH_STENCIL_STATE_DoubleSidedStencilEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_DEPTH_STENCIL_STATE_DoubleSidedStencilEnable_start 15 #define GFX7_DEPTH_STENCIL_STATE_DoubleSidedStencilEnable_start 15 #define GFX6_DEPTH_STENCIL_STATE_DoubleSidedStencilEnable_start 15 static inline uint32_t ATTRIBUTE_PURE DEPTH_STENCIL_STATE_DoubleSidedStencilEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 15; case 70: return 15; case 60: return 15; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* DEPTH_STENCIL_STATE::Stencil Buffer Write Enable */ #define GFX75_DEPTH_STENCIL_STATE_StencilBufferWriteEnable_bits 1 #define GFX7_DEPTH_STENCIL_STATE_StencilBufferWriteEnable_bits 1 #define GFX6_DEPTH_STENCIL_STATE_StencilBufferWriteEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE DEPTH_STENCIL_STATE_StencilBufferWriteEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_DEPTH_STENCIL_STATE_StencilBufferWriteEnable_start 18 #define GFX7_DEPTH_STENCIL_STATE_StencilBufferWriteEnable_start 18 #define GFX6_DEPTH_STENCIL_STATE_StencilBufferWriteEnable_start 18 static inline uint32_t ATTRIBUTE_PURE DEPTH_STENCIL_STATE_StencilBufferWriteEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 18; case 70: return 18; case 60: return 18; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* DEPTH_STENCIL_STATE::Stencil Fail Op */ #define GFX75_DEPTH_STENCIL_STATE_StencilFailOp_bits 3 #define GFX7_DEPTH_STENCIL_STATE_StencilFailOp_bits 3 #define GFX6_DEPTH_STENCIL_STATE_StencilFailOp_bits 3 static inline uint32_t ATTRIBUTE_PURE DEPTH_STENCIL_STATE_StencilFailOp_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_DEPTH_STENCIL_STATE_StencilFailOp_start 25 #define GFX7_DEPTH_STENCIL_STATE_StencilFailOp_start 25 #define GFX6_DEPTH_STENCIL_STATE_StencilFailOp_start 25 static inline uint32_t ATTRIBUTE_PURE DEPTH_STENCIL_STATE_StencilFailOp_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 25; case 70: return 25; case 60: return 25; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* DEPTH_STENCIL_STATE::Stencil Pass Depth Fail Op */ #define GFX75_DEPTH_STENCIL_STATE_StencilPassDepthFailOp_bits 3 #define GFX7_DEPTH_STENCIL_STATE_StencilPassDepthFailOp_bits 3 #define GFX6_DEPTH_STENCIL_STATE_StencilPassDepthFailOp_bits 3 static inline uint32_t ATTRIBUTE_PURE DEPTH_STENCIL_STATE_StencilPassDepthFailOp_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_DEPTH_STENCIL_STATE_StencilPassDepthFailOp_start 22 #define GFX7_DEPTH_STENCIL_STATE_StencilPassDepthFailOp_start 22 #define GFX6_DEPTH_STENCIL_STATE_StencilPassDepthFailOp_start 22 static inline uint32_t ATTRIBUTE_PURE DEPTH_STENCIL_STATE_StencilPassDepthFailOp_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 22; case 70: return 22; case 60: return 22; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* DEPTH_STENCIL_STATE::Stencil Pass Depth Pass Op */ #define GFX75_DEPTH_STENCIL_STATE_StencilPassDepthPassOp_bits 3 #define GFX7_DEPTH_STENCIL_STATE_StencilPassDepthPassOp_bits 3 #define GFX6_DEPTH_STENCIL_STATE_StencilPassDepthPassOp_bits 3 static inline uint32_t ATTRIBUTE_PURE DEPTH_STENCIL_STATE_StencilPassDepthPassOp_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_DEPTH_STENCIL_STATE_StencilPassDepthPassOp_start 19 #define GFX7_DEPTH_STENCIL_STATE_StencilPassDepthPassOp_start 19 #define GFX6_DEPTH_STENCIL_STATE_StencilPassDepthPassOp_start 19 static inline uint32_t ATTRIBUTE_PURE DEPTH_STENCIL_STATE_StencilPassDepthPassOp_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 19; case 70: return 19; case 60: return 19; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* DEPTH_STENCIL_STATE::Stencil Test Enable */ #define GFX75_DEPTH_STENCIL_STATE_StencilTestEnable_bits 1 #define GFX7_DEPTH_STENCIL_STATE_StencilTestEnable_bits 1 #define GFX6_DEPTH_STENCIL_STATE_StencilTestEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE DEPTH_STENCIL_STATE_StencilTestEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_DEPTH_STENCIL_STATE_StencilTestEnable_start 31 #define GFX7_DEPTH_STENCIL_STATE_StencilTestEnable_start 31 #define GFX6_DEPTH_STENCIL_STATE_StencilTestEnable_start 31 static inline uint32_t ATTRIBUTE_PURE DEPTH_STENCIL_STATE_StencilTestEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 31; case 70: return 31; case 60: return 31; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* DEPTH_STENCIL_STATE::Stencil Test Function */ #define GFX75_DEPTH_STENCIL_STATE_StencilTestFunction_bits 3 #define GFX7_DEPTH_STENCIL_STATE_StencilTestFunction_bits 3 #define GFX6_DEPTH_STENCIL_STATE_StencilTestFunction_bits 3 static inline uint32_t ATTRIBUTE_PURE DEPTH_STENCIL_STATE_StencilTestFunction_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_DEPTH_STENCIL_STATE_StencilTestFunction_start 28 #define GFX7_DEPTH_STENCIL_STATE_StencilTestFunction_start 28 #define GFX6_DEPTH_STENCIL_STATE_StencilTestFunction_start 28 static inline uint32_t ATTRIBUTE_PURE DEPTH_STENCIL_STATE_StencilTestFunction_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 28; case 70: return 28; case 60: return 28; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* DEPTH_STENCIL_STATE::Stencil Test Mask */ #define GFX75_DEPTH_STENCIL_STATE_StencilTestMask_bits 8 #define GFX7_DEPTH_STENCIL_STATE_StencilTestMask_bits 8 #define GFX6_DEPTH_STENCIL_STATE_StencilTestMask_bits 8 static inline uint32_t ATTRIBUTE_PURE DEPTH_STENCIL_STATE_StencilTestMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_DEPTH_STENCIL_STATE_StencilTestMask_start 56 #define GFX7_DEPTH_STENCIL_STATE_StencilTestMask_start 56 #define GFX6_DEPTH_STENCIL_STATE_StencilTestMask_start 56 static inline uint32_t ATTRIBUTE_PURE DEPTH_STENCIL_STATE_StencilTestMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 56; case 70: return 56; case 60: return 56; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* DEPTH_STENCIL_STATE::Stencil Write Mask */ #define GFX75_DEPTH_STENCIL_STATE_StencilWriteMask_bits 8 #define GFX7_DEPTH_STENCIL_STATE_StencilWriteMask_bits 8 #define GFX6_DEPTH_STENCIL_STATE_StencilWriteMask_bits 8 static inline uint32_t ATTRIBUTE_PURE DEPTH_STENCIL_STATE_StencilWriteMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_DEPTH_STENCIL_STATE_StencilWriteMask_start 48 #define GFX7_DEPTH_STENCIL_STATE_StencilWriteMask_start 48 #define GFX6_DEPTH_STENCIL_STATE_StencilWriteMask_start 48 static inline uint32_t ATTRIBUTE_PURE DEPTH_STENCIL_STATE_StencilWriteMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 48; case 70: return 48; case 60: return 48; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* DS_INVOCATION_COUNT */ #define GFX125_DS_INVOCATION_COUNT_length 2 #define GFX12_DS_INVOCATION_COUNT_length 2 #define GFX11_DS_INVOCATION_COUNT_length 2 #define GFX9_DS_INVOCATION_COUNT_length 2 #define GFX8_DS_INVOCATION_COUNT_length 2 #define GFX75_DS_INVOCATION_COUNT_length 2 #define GFX7_DS_INVOCATION_COUNT_length 2 static inline uint32_t ATTRIBUTE_PURE DS_INVOCATION_COUNT_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* DS_INVOCATION_COUNT::DS Invocation Count Report */ #define GFX125_DS_INVOCATION_COUNT_DSInvocationCountReport_bits 64 #define GFX12_DS_INVOCATION_COUNT_DSInvocationCountReport_bits 64 #define GFX11_DS_INVOCATION_COUNT_DSInvocationCountReport_bits 64 #define GFX9_DS_INVOCATION_COUNT_DSInvocationCountReport_bits 64 #define GFX8_DS_INVOCATION_COUNT_DSInvocationCountReport_bits 64 #define GFX75_DS_INVOCATION_COUNT_DSInvocationCountReport_bits 64 #define GFX7_DS_INVOCATION_COUNT_DSInvocationCountReport_bits 64 static inline uint32_t ATTRIBUTE_PURE DS_INVOCATION_COUNT_DSInvocationCountReport_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 64; case 80: return 64; case 75: return 64; case 70: return 64; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_DS_INVOCATION_COUNT_DSInvocationCountReport_start 0 #define GFX12_DS_INVOCATION_COUNT_DSInvocationCountReport_start 0 #define GFX11_DS_INVOCATION_COUNT_DSInvocationCountReport_start 0 #define GFX9_DS_INVOCATION_COUNT_DSInvocationCountReport_start 0 #define GFX8_DS_INVOCATION_COUNT_DSInvocationCountReport_start 0 #define GFX75_DS_INVOCATION_COUNT_DSInvocationCountReport_start 0 #define GFX7_DS_INVOCATION_COUNT_DSInvocationCountReport_start 0 static inline uint32_t ATTRIBUTE_PURE DS_INVOCATION_COUNT_DSInvocationCountReport_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* ERR_INT */ #define GFX75_ERR_INT_length 1 #define GFX7_ERR_INT_length 1 static inline uint32_t ATTRIBUTE_PURE ERR_INT_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* ERR_INT::Cursor A GTT Fault Status */ #define GFX75_ERR_INT_CursorAGTTFaultStatus_bits 1 #define GFX7_ERR_INT_CursorAGTTFaultStatus_bits 1 static inline uint32_t ATTRIBUTE_PURE ERR_INT_CursorAGTTFaultStatus_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_ERR_INT_CursorAGTTFaultStatus_start 4 #define GFX7_ERR_INT_CursorAGTTFaultStatus_start 4 static inline uint32_t ATTRIBUTE_PURE ERR_INT_CursorAGTTFaultStatus_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 4; case 70: return 4; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* ERR_INT::Cursor B GTT Fault Status */ #define GFX75_ERR_INT_CursorBGTTFaultStatus_bits 1 #define GFX7_ERR_INT_CursorBGTTFaultStatus_bits 1 static inline uint32_t ATTRIBUTE_PURE ERR_INT_CursorBGTTFaultStatus_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_ERR_INT_CursorBGTTFaultStatus_start 5 #define GFX7_ERR_INT_CursorBGTTFaultStatus_start 5 static inline uint32_t ATTRIBUTE_PURE ERR_INT_CursorBGTTFaultStatus_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 5; case 70: return 5; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* ERR_INT::Invalid GTT page table entry */ #define GFX75_ERR_INT_InvalidGTTpagetableentry_bits 1 #define GFX7_ERR_INT_InvalidGTTpagetableentry_bits 1 static inline uint32_t ATTRIBUTE_PURE ERR_INT_InvalidGTTpagetableentry_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_ERR_INT_InvalidGTTpagetableentry_start 7 #define GFX7_ERR_INT_InvalidGTTpagetableentry_start 7 static inline uint32_t ATTRIBUTE_PURE ERR_INT_InvalidGTTpagetableentry_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 7; case 70: return 7; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* ERR_INT::Invalid page table entry data */ #define GFX75_ERR_INT_Invalidpagetableentrydata_bits 1 #define GFX7_ERR_INT_Invalidpagetableentrydata_bits 1 static inline uint32_t ATTRIBUTE_PURE ERR_INT_Invalidpagetableentrydata_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_ERR_INT_Invalidpagetableentrydata_start 6 #define GFX7_ERR_INT_Invalidpagetableentrydata_start 6 static inline uint32_t ATTRIBUTE_PURE ERR_INT_Invalidpagetableentrydata_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 6; case 70: return 6; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* ERR_INT::Primary A GTT Fault Status */ #define GFX75_ERR_INT_PrimaryAGTTFaultStatus_bits 1 #define GFX7_ERR_INT_PrimaryAGTTFaultStatus_bits 1 static inline uint32_t ATTRIBUTE_PURE ERR_INT_PrimaryAGTTFaultStatus_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_ERR_INT_PrimaryAGTTFaultStatus_start 0 #define GFX7_ERR_INT_PrimaryAGTTFaultStatus_start 0 static inline uint32_t ATTRIBUTE_PURE ERR_INT_PrimaryAGTTFaultStatus_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* ERR_INT::Primary B GTT Fault Status */ #define GFX75_ERR_INT_PrimaryBGTTFaultStatus_bits 1 #define GFX7_ERR_INT_PrimaryBGTTFaultStatus_bits 1 static inline uint32_t ATTRIBUTE_PURE ERR_INT_PrimaryBGTTFaultStatus_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_ERR_INT_PrimaryBGTTFaultStatus_start 1 #define GFX7_ERR_INT_PrimaryBGTTFaultStatus_start 1 static inline uint32_t ATTRIBUTE_PURE ERR_INT_PrimaryBGTTFaultStatus_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* ERR_INT::Sprite A GTT Fault Status */ #define GFX75_ERR_INT_SpriteAGTTFaultStatus_bits 1 #define GFX7_ERR_INT_SpriteAGTTFaultStatus_bits 1 static inline uint32_t ATTRIBUTE_PURE ERR_INT_SpriteAGTTFaultStatus_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_ERR_INT_SpriteAGTTFaultStatus_start 2 #define GFX7_ERR_INT_SpriteAGTTFaultStatus_start 2 static inline uint32_t ATTRIBUTE_PURE ERR_INT_SpriteAGTTFaultStatus_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* ERR_INT::Sprite B GTT Fault Status */ #define GFX75_ERR_INT_SpriteBGTTFaultStatus_bits 1 #define GFX7_ERR_INT_SpriteBGTTFaultStatus_bits 1 static inline uint32_t ATTRIBUTE_PURE ERR_INT_SpriteBGTTFaultStatus_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_ERR_INT_SpriteBGTTFaultStatus_start 3 #define GFX7_ERR_INT_SpriteBGTTFaultStatus_start 3 static inline uint32_t ATTRIBUTE_PURE ERR_INT_SpriteBGTTFaultStatus_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* EXECUTION_UNIT_EXTENDED_MESSAGE_DESCRIPTOR */ #define GFX125_EXECUTION_UNIT_EXTENDED_MESSAGE_DESCRIPTOR_length 1 #define GFX12_EXECUTION_UNIT_EXTENDED_MESSAGE_DESCRIPTOR_length 1 #define GFX11_EXECUTION_UNIT_EXTENDED_MESSAGE_DESCRIPTOR_length 1 #define GFX9_EXECUTION_UNIT_EXTENDED_MESSAGE_DESCRIPTOR_length 1 static inline uint32_t ATTRIBUTE_PURE EXECUTION_UNIT_EXTENDED_MESSAGE_DESCRIPTOR_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* EXECUTION_UNIT_EXTENDED_MESSAGE_DESCRIPTOR::End Of Thread */ #define GFX125_EXECUTION_UNIT_EXTENDED_MESSAGE_DESCRIPTOR_EndOfThread_bits 1 #define GFX12_EXECUTION_UNIT_EXTENDED_MESSAGE_DESCRIPTOR_EndOfThread_bits 1 #define GFX11_EXECUTION_UNIT_EXTENDED_MESSAGE_DESCRIPTOR_EndOfThread_bits 1 #define GFX9_EXECUTION_UNIT_EXTENDED_MESSAGE_DESCRIPTOR_EndOfThread_bits 1 static inline uint32_t ATTRIBUTE_PURE EXECUTION_UNIT_EXTENDED_MESSAGE_DESCRIPTOR_EndOfThread_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_EXECUTION_UNIT_EXTENDED_MESSAGE_DESCRIPTOR_EndOfThread_start 5 #define GFX12_EXECUTION_UNIT_EXTENDED_MESSAGE_DESCRIPTOR_EndOfThread_start 5 #define GFX11_EXECUTION_UNIT_EXTENDED_MESSAGE_DESCRIPTOR_EndOfThread_start 5 #define GFX9_EXECUTION_UNIT_EXTENDED_MESSAGE_DESCRIPTOR_EndOfThread_start 5 static inline uint32_t ATTRIBUTE_PURE EXECUTION_UNIT_EXTENDED_MESSAGE_DESCRIPTOR_EndOfThread_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 5; case 110: return 5; case 90: return 5; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* EXECUTION_UNIT_EXTENDED_MESSAGE_DESCRIPTOR::Extended Message Length */ #define GFX125_EXECUTION_UNIT_EXTENDED_MESSAGE_DESCRIPTOR_ExtendedMessageLength_bits 4 #define GFX12_EXECUTION_UNIT_EXTENDED_MESSAGE_DESCRIPTOR_ExtendedMessageLength_bits 4 #define GFX11_EXECUTION_UNIT_EXTENDED_MESSAGE_DESCRIPTOR_ExtendedMessageLength_bits 4 #define GFX9_EXECUTION_UNIT_EXTENDED_MESSAGE_DESCRIPTOR_ExtendedMessageLength_bits 4 static inline uint32_t ATTRIBUTE_PURE EXECUTION_UNIT_EXTENDED_MESSAGE_DESCRIPTOR_ExtendedMessageLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_EXECUTION_UNIT_EXTENDED_MESSAGE_DESCRIPTOR_ExtendedMessageLength_start 6 #define GFX12_EXECUTION_UNIT_EXTENDED_MESSAGE_DESCRIPTOR_ExtendedMessageLength_start 6 #define GFX11_EXECUTION_UNIT_EXTENDED_MESSAGE_DESCRIPTOR_ExtendedMessageLength_start 6 #define GFX9_EXECUTION_UNIT_EXTENDED_MESSAGE_DESCRIPTOR_ExtendedMessageLength_start 6 static inline uint32_t ATTRIBUTE_PURE EXECUTION_UNIT_EXTENDED_MESSAGE_DESCRIPTOR_ExtendedMessageLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* EXECUTION_UNIT_EXTENDED_MESSAGE_DESCRIPTOR::Target Function ID */ #define GFX125_EXECUTION_UNIT_EXTENDED_MESSAGE_DESCRIPTOR_TargetFunctionID_bits 4 #define GFX12_EXECUTION_UNIT_EXTENDED_MESSAGE_DESCRIPTOR_TargetFunctionID_bits 4 #define GFX11_EXECUTION_UNIT_EXTENDED_MESSAGE_DESCRIPTOR_TargetFunctionID_bits 4 #define GFX9_EXECUTION_UNIT_EXTENDED_MESSAGE_DESCRIPTOR_TargetFunctionID_bits 4 static inline uint32_t ATTRIBUTE_PURE EXECUTION_UNIT_EXTENDED_MESSAGE_DESCRIPTOR_TargetFunctionID_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_EXECUTION_UNIT_EXTENDED_MESSAGE_DESCRIPTOR_TargetFunctionID_start 0 #define GFX12_EXECUTION_UNIT_EXTENDED_MESSAGE_DESCRIPTOR_TargetFunctionID_start 0 #define GFX11_EXECUTION_UNIT_EXTENDED_MESSAGE_DESCRIPTOR_TargetFunctionID_start 0 #define GFX9_EXECUTION_UNIT_EXTENDED_MESSAGE_DESCRIPTOR_TargetFunctionID_start 0 static inline uint32_t ATTRIBUTE_PURE EXECUTION_UNIT_EXTENDED_MESSAGE_DESCRIPTOR_TargetFunctionID_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* FAULT_REG */ #define GFX9_FAULT_REG_length 1 #define GFX8_FAULT_REG_length 1 static inline uint32_t ATTRIBUTE_PURE FAULT_REG_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* FAULT_REG::Engine ID */ #define GFX9_FAULT_REG_EngineID_bits 3 #define GFX8_FAULT_REG_EngineID_bits 3 static inline uint32_t ATTRIBUTE_PURE FAULT_REG_EngineID_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 3; case 80: return 3; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_FAULT_REG_EngineID_start 12 #define GFX8_FAULT_REG_EngineID_start 12 static inline uint32_t ATTRIBUTE_PURE FAULT_REG_EngineID_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 12; case 80: return 12; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* FAULT_REG::Fault Type */ #define GFX9_FAULT_REG_FaultType_bits 2 #define GFX8_FAULT_REG_FaultType_bits 2 static inline uint32_t ATTRIBUTE_PURE FAULT_REG_FaultType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 2; case 80: return 2; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_FAULT_REG_FaultType_start 1 #define GFX8_FAULT_REG_FaultType_start 1 static inline uint32_t ATTRIBUTE_PURE FAULT_REG_FaultType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* FAULT_REG::GTTSEL */ #define GFX9_FAULT_REG_GTTSEL_bits 1 #define GFX8_FAULT_REG_GTTSEL_bits 1 static inline uint32_t ATTRIBUTE_PURE FAULT_REG_GTTSEL_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_FAULT_REG_GTTSEL_start 11 #define GFX8_FAULT_REG_GTTSEL_start 11 static inline uint32_t ATTRIBUTE_PURE FAULT_REG_GTTSEL_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 11; case 80: return 11; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* FAULT_REG::SRCID of Fault */ #define GFX9_FAULT_REG_SRCIDofFault_bits 8 #define GFX8_FAULT_REG_SRCIDofFault_bits 8 static inline uint32_t ATTRIBUTE_PURE FAULT_REG_SRCIDofFault_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 8; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_FAULT_REG_SRCIDofFault_start 3 #define GFX8_FAULT_REG_SRCIDofFault_start 3 static inline uint32_t ATTRIBUTE_PURE FAULT_REG_SRCIDofFault_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 3; case 80: return 3; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* FAULT_REG::Valid Bit */ #define GFX9_FAULT_REG_ValidBit_bits 1 #define GFX8_FAULT_REG_ValidBit_bits 1 static inline uint32_t ATTRIBUTE_PURE FAULT_REG_ValidBit_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_FAULT_REG_ValidBit_start 0 #define GFX8_FAULT_REG_ValidBit_start 0 static inline uint32_t ATTRIBUTE_PURE FAULT_REG_ValidBit_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* FILTER_COEFFICIENT */ #define GFX125_FILTER_COEFFICIENT_length 1 #define GFX12_FILTER_COEFFICIENT_length 1 #define GFX11_FILTER_COEFFICIENT_length 1 #define GFX9_FILTER_COEFFICIENT_length 1 #define GFX8_FILTER_COEFFICIENT_length 1 static inline uint32_t ATTRIBUTE_PURE FILTER_COEFFICIENT_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* FILTER_COEFFICIENT::Filter Coefficient */ #define GFX125_FILTER_COEFFICIENT_FilterCoefficient_bits 8 #define GFX12_FILTER_COEFFICIENT_FilterCoefficient_bits 8 #define GFX11_FILTER_COEFFICIENT_FilterCoefficient_bits 8 #define GFX9_FILTER_COEFFICIENT_FilterCoefficient_bits 8 #define GFX8_FILTER_COEFFICIENT_FilterCoefficient_bits 8 static inline uint32_t ATTRIBUTE_PURE FILTER_COEFFICIENT_FilterCoefficient_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_FILTER_COEFFICIENT_FilterCoefficient_start 0 #define GFX12_FILTER_COEFFICIENT_FilterCoefficient_start 0 #define GFX11_FILTER_COEFFICIENT_FilterCoefficient_start 0 #define GFX9_FILTER_COEFFICIENT_FilterCoefficient_start 0 #define GFX8_FILTER_COEFFICIENT_FilterCoefficient_start 0 static inline uint32_t ATTRIBUTE_PURE FILTER_COEFFICIENT_FilterCoefficient_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* FRAMEDELTAQP */ #define GFX125_FRAMEDELTAQP_length 2 #define GFX12_FRAMEDELTAQP_length 2 #define GFX11_FRAMEDELTAQP_length 2 #define GFX9_FRAMEDELTAQP_length 2 static inline uint32_t ATTRIBUTE_PURE FRAMEDELTAQP_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* FRAMEDELTAQPRANGE */ #define GFX125_FRAMEDELTAQPRANGE_length 2 #define GFX12_FRAMEDELTAQPRANGE_length 2 #define GFX11_FRAMEDELTAQPRANGE_length 2 #define GFX9_FRAMEDELTAQPRANGE_length 2 static inline uint32_t ATTRIBUTE_PURE FRAMEDELTAQPRANGE_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GATHER_CONSTANT_ENTRY */ #define GFX125_GATHER_CONSTANT_ENTRY_length 1 #define GFX12_GATHER_CONSTANT_ENTRY_length 1 #define GFX11_GATHER_CONSTANT_ENTRY_length 1 #define GFX9_GATHER_CONSTANT_ENTRY_length 1 #define GFX8_GATHER_CONSTANT_ENTRY_length 1 #define GFX75_GATHER_CONSTANT_ENTRY_length 1 static inline uint32_t ATTRIBUTE_PURE GATHER_CONSTANT_ENTRY_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GATHER_CONSTANT_ENTRY::Binding Table Index Offset */ #define GFX125_GATHER_CONSTANT_ENTRY_BindingTableIndexOffset_bits 4 #define GFX12_GATHER_CONSTANT_ENTRY_BindingTableIndexOffset_bits 4 #define GFX11_GATHER_CONSTANT_ENTRY_BindingTableIndexOffset_bits 4 #define GFX9_GATHER_CONSTANT_ENTRY_BindingTableIndexOffset_bits 4 #define GFX8_GATHER_CONSTANT_ENTRY_BindingTableIndexOffset_bits 4 #define GFX75_GATHER_CONSTANT_ENTRY_BindingTableIndexOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE GATHER_CONSTANT_ENTRY_BindingTableIndexOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 4; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_GATHER_CONSTANT_ENTRY_BindingTableIndexOffset_start 0 #define GFX12_GATHER_CONSTANT_ENTRY_BindingTableIndexOffset_start 0 #define GFX11_GATHER_CONSTANT_ENTRY_BindingTableIndexOffset_start 0 #define GFX9_GATHER_CONSTANT_ENTRY_BindingTableIndexOffset_start 0 #define GFX8_GATHER_CONSTANT_ENTRY_BindingTableIndexOffset_start 0 #define GFX75_GATHER_CONSTANT_ENTRY_BindingTableIndexOffset_start 0 static inline uint32_t ATTRIBUTE_PURE GATHER_CONSTANT_ENTRY_BindingTableIndexOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GATHER_CONSTANT_ENTRY::Channel Mask */ #define GFX125_GATHER_CONSTANT_ENTRY_ChannelMask_bits 4 #define GFX12_GATHER_CONSTANT_ENTRY_ChannelMask_bits 4 #define GFX11_GATHER_CONSTANT_ENTRY_ChannelMask_bits 4 #define GFX9_GATHER_CONSTANT_ENTRY_ChannelMask_bits 4 #define GFX8_GATHER_CONSTANT_ENTRY_ChannelMask_bits 4 #define GFX75_GATHER_CONSTANT_ENTRY_ChannelMask_bits 4 static inline uint32_t ATTRIBUTE_PURE GATHER_CONSTANT_ENTRY_ChannelMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 4; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_GATHER_CONSTANT_ENTRY_ChannelMask_start 4 #define GFX12_GATHER_CONSTANT_ENTRY_ChannelMask_start 4 #define GFX11_GATHER_CONSTANT_ENTRY_ChannelMask_start 4 #define GFX9_GATHER_CONSTANT_ENTRY_ChannelMask_start 4 #define GFX8_GATHER_CONSTANT_ENTRY_ChannelMask_start 4 #define GFX75_GATHER_CONSTANT_ENTRY_ChannelMask_start 4 static inline uint32_t ATTRIBUTE_PURE GATHER_CONSTANT_ENTRY_ChannelMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 4; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GATHER_CONSTANT_ENTRY::Constant Buffer Offset */ #define GFX125_GATHER_CONSTANT_ENTRY_ConstantBufferOffset_bits 8 #define GFX12_GATHER_CONSTANT_ENTRY_ConstantBufferOffset_bits 8 #define GFX11_GATHER_CONSTANT_ENTRY_ConstantBufferOffset_bits 8 #define GFX9_GATHER_CONSTANT_ENTRY_ConstantBufferOffset_bits 8 #define GFX8_GATHER_CONSTANT_ENTRY_ConstantBufferOffset_bits 8 #define GFX75_GATHER_CONSTANT_ENTRY_ConstantBufferOffset_bits 8 static inline uint32_t ATTRIBUTE_PURE GATHER_CONSTANT_ENTRY_ConstantBufferOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_GATHER_CONSTANT_ENTRY_ConstantBufferOffset_start 8 #define GFX12_GATHER_CONSTANT_ENTRY_ConstantBufferOffset_start 8 #define GFX11_GATHER_CONSTANT_ENTRY_ConstantBufferOffset_start 8 #define GFX9_GATHER_CONSTANT_ENTRY_ConstantBufferOffset_start 8 #define GFX8_GATHER_CONSTANT_ENTRY_ConstantBufferOffset_start 8 #define GFX75_GATHER_CONSTANT_ENTRY_ConstantBufferOffset_start 8 static inline uint32_t ATTRIBUTE_PURE GATHER_CONSTANT_ENTRY_ConstantBufferOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GFX_ARB_ERROR_RPT */ #define GFX9_GFX_ARB_ERROR_RPT_length 1 #define GFX8_GFX_ARB_ERROR_RPT_length 1 #define GFX75_GFX_ARB_ERROR_RPT_length 1 #define GFX7_GFX_ARB_ERROR_RPT_length 1 #define GFX6_GFX_ARB_ERROR_RPT_length 1 static inline uint32_t ATTRIBUTE_PURE GFX_ARB_ERROR_RPT_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GFX_ARB_ERROR_RPT::Context Page Fault Error */ #define GFX75_GFX_ARB_ERROR_RPT_ContextPageFaultError_bits 1 #define GFX7_GFX_ARB_ERROR_RPT_ContextPageFaultError_bits 1 #define GFX6_GFX_ARB_ERROR_RPT_ContextPageFaultError_bits 1 static inline uint32_t ATTRIBUTE_PURE GFX_ARB_ERROR_RPT_ContextPageFaultError_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_GFX_ARB_ERROR_RPT_ContextPageFaultError_start 1 #define GFX7_GFX_ARB_ERROR_RPT_ContextPageFaultError_start 1 #define GFX6_GFX_ARB_ERROR_RPT_ContextPageFaultError_start 1 static inline uint32_t ATTRIBUTE_PURE GFX_ARB_ERROR_RPT_ContextPageFaultError_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GFX_ARB_ERROR_RPT::Context Page VTD Translation Error */ #define GFX75_GFX_ARB_ERROR_RPT_ContextPageVTDTranslationError_bits 1 #define GFX7_GFX_ARB_ERROR_RPT_ContextPageVTDTranslationError_bits 1 #define GFX6_GFX_ARB_ERROR_RPT_ContextPageVTDTranslationError_bits 1 static inline uint32_t ATTRIBUTE_PURE GFX_ARB_ERROR_RPT_ContextPageVTDTranslationError_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_GFX_ARB_ERROR_RPT_ContextPageVTDTranslationError_start 5 #define GFX7_GFX_ARB_ERROR_RPT_ContextPageVTDTranslationError_start 5 #define GFX6_GFX_ARB_ERROR_RPT_ContextPageVTDTranslationError_start 5 static inline uint32_t ATTRIBUTE_PURE GFX_ARB_ERROR_RPT_ContextPageVTDTranslationError_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 5; case 70: return 5; case 60: return 5; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GFX_ARB_ERROR_RPT::Context Was Not Marked As Present When Doing DMA */ #define GFX9_GFX_ARB_ERROR_RPT_ContextWasNotMarkedAsPresentWhenDoingDMA_bits 1 #define GFX8_GFX_ARB_ERROR_RPT_ContextWasNotMarkedAsPresentWhenDoingDMA_bits 1 static inline uint32_t ATTRIBUTE_PURE GFX_ARB_ERROR_RPT_ContextWasNotMarkedAsPresentWhenDoingDMA_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_GFX_ARB_ERROR_RPT_ContextWasNotMarkedAsPresentWhenDoingDMA_start 15 #define GFX8_GFX_ARB_ERROR_RPT_ContextWasNotMarkedAsPresentWhenDoingDMA_start 15 static inline uint32_t ATTRIBUTE_PURE GFX_ARB_ERROR_RPT_ContextWasNotMarkedAsPresentWhenDoingDMA_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 15; case 80: return 15; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GFX_ARB_ERROR_RPT::GuC VTd translation Page Fault 2nd level (Undefined doorbell) */ #define GFX9_GFX_ARB_ERROR_RPT_GuCVTdtranslationPageFault2ndlevelUndefineddoorbell_bits 1 #define GFX8_GFX_ARB_ERROR_RPT_GuCVTdtranslationPageFault2ndlevelUndefineddoorbell_bits 1 static inline uint32_t ATTRIBUTE_PURE GFX_ARB_ERROR_RPT_GuCVTdtranslationPageFault2ndlevelUndefineddoorbell_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_GFX_ARB_ERROR_RPT_GuCVTdtranslationPageFault2ndlevelUndefineddoorbell_start 9 #define GFX8_GFX_ARB_ERROR_RPT_GuCVTdtranslationPageFault2ndlevelUndefineddoorbell_start 9 static inline uint32_t ATTRIBUTE_PURE GFX_ARB_ERROR_RPT_GuCVTdtranslationPageFault2ndlevelUndefineddoorbell_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 9; case 80: return 9; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GFX_ARB_ERROR_RPT::Hardware Status Page Fault Error */ #define GFX75_GFX_ARB_ERROR_RPT_HardwareStatusPageFaultError_bits 1 #define GFX7_GFX_ARB_ERROR_RPT_HardwareStatusPageFaultError_bits 1 #define GFX6_GFX_ARB_ERROR_RPT_HardwareStatusPageFaultError_bits 1 static inline uint32_t ATTRIBUTE_PURE GFX_ARB_ERROR_RPT_HardwareStatusPageFaultError_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_GFX_ARB_ERROR_RPT_HardwareStatusPageFaultError_start 3 #define GFX7_GFX_ARB_ERROR_RPT_HardwareStatusPageFaultError_start 3 #define GFX6_GFX_ARB_ERROR_RPT_HardwareStatusPageFaultError_start 3 static inline uint32_t ATTRIBUTE_PURE GFX_ARB_ERROR_RPT_HardwareStatusPageFaultError_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GFX_ARB_ERROR_RPT::Hardware Status Page VTD Translation Error */ #define GFX75_GFX_ARB_ERROR_RPT_HardwareStatusPageVTDTranslationError_bits 1 #define GFX7_GFX_ARB_ERROR_RPT_HardwareStatusPageVTDTranslationError_bits 1 #define GFX6_GFX_ARB_ERROR_RPT_HardwareStatusPageVTDTranslationError_bits 1 static inline uint32_t ATTRIBUTE_PURE GFX_ARB_ERROR_RPT_HardwareStatusPageVTDTranslationError_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_GFX_ARB_ERROR_RPT_HardwareStatusPageVTDTranslationError_start 7 #define GFX7_GFX_ARB_ERROR_RPT_HardwareStatusPageVTDTranslationError_start 7 #define GFX6_GFX_ARB_ERROR_RPT_HardwareStatusPageVTDTranslationError_start 7 static inline uint32_t ATTRIBUTE_PURE GFX_ARB_ERROR_RPT_HardwareStatusPageVTDTranslationError_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 7; case 70: return 7; case 60: return 7; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GFX_ARB_ERROR_RPT::Invalid Page Directory Entry Error */ #define GFX9_GFX_ARB_ERROR_RPT_InvalidPageDirectoryEntryError_bits 1 #define GFX8_GFX_ARB_ERROR_RPT_InvalidPageDirectoryEntryError_bits 1 static inline uint32_t ATTRIBUTE_PURE GFX_ARB_ERROR_RPT_InvalidPageDirectoryEntryError_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_GFX_ARB_ERROR_RPT_InvalidPageDirectoryEntryError_start 2 #define GFX8_GFX_ARB_ERROR_RPT_InvalidPageDirectoryEntryError_start 2 static inline uint32_t ATTRIBUTE_PURE GFX_ARB_ERROR_RPT_InvalidPageDirectoryEntryError_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 2; case 80: return 2; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GFX_ARB_ERROR_RPT::Invalid Page Directory entry error */ #define GFX75_GFX_ARB_ERROR_RPT_InvalidPageDirectoryentryerror_bits 1 #define GFX7_GFX_ARB_ERROR_RPT_InvalidPageDirectoryentryerror_bits 1 #define GFX6_GFX_ARB_ERROR_RPT_InvalidPageDirectoryentryerror_bits 1 static inline uint32_t ATTRIBUTE_PURE GFX_ARB_ERROR_RPT_InvalidPageDirectoryentryerror_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_GFX_ARB_ERROR_RPT_InvalidPageDirectoryentryerror_start 2 #define GFX7_GFX_ARB_ERROR_RPT_InvalidPageDirectoryentryerror_start 2 #define GFX6_GFX_ARB_ERROR_RPT_InvalidPageDirectoryentryerror_start 2 static inline uint32_t ATTRIBUTE_PURE GFX_ARB_ERROR_RPT_InvalidPageDirectoryentryerror_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GFX_ARB_ERROR_RPT::Non WB memory type for Advanced Context */ #define GFX9_GFX_ARB_ERROR_RPT_NonWBmemorytypeforAdvancedContext_bits 1 #define GFX8_GFX_ARB_ERROR_RPT_NonWBmemorytypeforAdvancedContext_bits 1 static inline uint32_t ATTRIBUTE_PURE GFX_ARB_ERROR_RPT_NonWBmemorytypeforAdvancedContext_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_GFX_ARB_ERROR_RPT_NonWBmemorytypeforAdvancedContext_start 10 #define GFX8_GFX_ARB_ERROR_RPT_NonWBmemorytypeforAdvancedContext_start 10 static inline uint32_t ATTRIBUTE_PURE GFX_ARB_ERROR_RPT_NonWBmemorytypeforAdvancedContext_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 10; case 80: return 10; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GFX_ARB_ERROR_RPT::PASID Boundary Violation */ #define GFX9_GFX_ARB_ERROR_RPT_PASIDBoundaryViolation_bits 1 #define GFX8_GFX_ARB_ERROR_RPT_PASIDBoundaryViolation_bits 1 static inline uint32_t ATTRIBUTE_PURE GFX_ARB_ERROR_RPT_PASIDBoundaryViolation_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_GFX_ARB_ERROR_RPT_PASIDBoundaryViolation_start 12 #define GFX8_GFX_ARB_ERROR_RPT_PASIDBoundaryViolation_start 12 static inline uint32_t ATTRIBUTE_PURE GFX_ARB_ERROR_RPT_PASIDBoundaryViolation_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 12; case 80: return 12; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GFX_ARB_ERROR_RPT::PASID Not Enabled */ #define GFX9_GFX_ARB_ERROR_RPT_PASIDNotEnabled_bits 1 #define GFX8_GFX_ARB_ERROR_RPT_PASIDNotEnabled_bits 1 static inline uint32_t ATTRIBUTE_PURE GFX_ARB_ERROR_RPT_PASIDNotEnabled_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_GFX_ARB_ERROR_RPT_PASIDNotEnabled_start 11 #define GFX8_GFX_ARB_ERROR_RPT_PASIDNotEnabled_start 11 static inline uint32_t ATTRIBUTE_PURE GFX_ARB_ERROR_RPT_PASIDNotEnabled_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 11; case 80: return 11; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GFX_ARB_ERROR_RPT::PASID Not Valid */ #define GFX9_GFX_ARB_ERROR_RPT_PASIDNotValid_bits 1 #define GFX8_GFX_ARB_ERROR_RPT_PASIDNotValid_bits 1 static inline uint32_t ATTRIBUTE_PURE GFX_ARB_ERROR_RPT_PASIDNotValid_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_GFX_ARB_ERROR_RPT_PASIDNotValid_start 13 #define GFX8_GFX_ARB_ERROR_RPT_PASIDNotValid_start 13 static inline uint32_t ATTRIBUTE_PURE GFX_ARB_ERROR_RPT_PASIDNotValid_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 13; case 80: return 13; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GFX_ARB_ERROR_RPT::PASID Was Zero For Untranslated Request */ #define GFX9_GFX_ARB_ERROR_RPT_PASIDWasZeroForUntranslatedRequest_bits 1 #define GFX8_GFX_ARB_ERROR_RPT_PASIDWasZeroForUntranslatedRequest_bits 1 static inline uint32_t ATTRIBUTE_PURE GFX_ARB_ERROR_RPT_PASIDWasZeroForUntranslatedRequest_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_GFX_ARB_ERROR_RPT_PASIDWasZeroForUntranslatedRequest_start 14 #define GFX8_GFX_ARB_ERROR_RPT_PASIDWasZeroForUntranslatedRequest_start 14 static inline uint32_t ATTRIBUTE_PURE GFX_ARB_ERROR_RPT_PASIDWasZeroForUntranslatedRequest_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 14; case 80: return 14; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GFX_ARB_ERROR_RPT::Page Directory Entry VTD Translation Error */ #define GFX9_GFX_ARB_ERROR_RPT_PageDirectoryEntryVTDTranslationError_bits 1 #define GFX8_GFX_ARB_ERROR_RPT_PageDirectoryEntryVTDTranslationError_bits 1 #define GFX75_GFX_ARB_ERROR_RPT_PageDirectoryEntryVTDTranslationError_bits 1 #define GFX7_GFX_ARB_ERROR_RPT_PageDirectoryEntryVTDTranslationError_bits 1 #define GFX6_GFX_ARB_ERROR_RPT_PageDirectoryEntryVTDTranslationError_bits 1 static inline uint32_t ATTRIBUTE_PURE GFX_ARB_ERROR_RPT_PageDirectoryEntryVTDTranslationError_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_GFX_ARB_ERROR_RPT_PageDirectoryEntryVTDTranslationError_start 6 #define GFX8_GFX_ARB_ERROR_RPT_PageDirectoryEntryVTDTranslationError_start 6 #define GFX75_GFX_ARB_ERROR_RPT_PageDirectoryEntryVTDTranslationError_start 6 #define GFX7_GFX_ARB_ERROR_RPT_PageDirectoryEntryVTDTranslationError_start 6 #define GFX6_GFX_ARB_ERROR_RPT_PageDirectoryEntryVTDTranslationError_start 6 static inline uint32_t ATTRIBUTE_PURE GFX_ARB_ERROR_RPT_PageDirectoryEntryVTDTranslationError_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 6; case 60: return 6; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GFX_ARB_ERROR_RPT::Pending Page Faults */ #define GFX75_GFX_ARB_ERROR_RPT_PendingPageFaults_bits 7 static inline uint32_t ATTRIBUTE_PURE GFX_ARB_ERROR_RPT_PendingPageFaults_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 7; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_GFX_ARB_ERROR_RPT_PendingPageFaults_start 9 static inline uint32_t ATTRIBUTE_PURE GFX_ARB_ERROR_RPT_PendingPageFaults_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 9; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GFX_ARB_ERROR_RPT::ROSTRM PAVP Invalid Physical Address */ #define GFX9_GFX_ARB_ERROR_RPT_ROSTRMPAVPInvalidPhysicalAddress_bits 1 #define GFX8_GFX_ARB_ERROR_RPT_ROSTRMPAVPInvalidPhysicalAddress_bits 1 static inline uint32_t ATTRIBUTE_PURE GFX_ARB_ERROR_RPT_ROSTRMPAVPInvalidPhysicalAddress_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_GFX_ARB_ERROR_RPT_ROSTRMPAVPInvalidPhysicalAddress_start 3 #define GFX8_GFX_ARB_ERROR_RPT_ROSTRMPAVPInvalidPhysicalAddress_start 3 static inline uint32_t ATTRIBUTE_PURE GFX_ARB_ERROR_RPT_ROSTRMPAVPInvalidPhysicalAddress_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 3; case 80: return 3; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GFX_ARB_ERROR_RPT::RSTRM PAVP Read Invalid */ #define GFX9_GFX_ARB_ERROR_RPT_RSTRMPAVPReadInvalid_bits 1 #define GFX8_GFX_ARB_ERROR_RPT_RSTRMPAVPReadInvalid_bits 1 static inline uint32_t ATTRIBUTE_PURE GFX_ARB_ERROR_RPT_RSTRMPAVPReadInvalid_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_GFX_ARB_ERROR_RPT_RSTRMPAVPReadInvalid_start 1 #define GFX8_GFX_ARB_ERROR_RPT_RSTRMPAVPReadInvalid_start 1 static inline uint32_t ATTRIBUTE_PURE GFX_ARB_ERROR_RPT_RSTRMPAVPReadInvalid_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GFX_ARB_ERROR_RPT::TLB Page Fault Error */ #define GFX9_GFX_ARB_ERROR_RPT_TLBPageFaultError_bits 1 #define GFX8_GFX_ARB_ERROR_RPT_TLBPageFaultError_bits 1 #define GFX75_GFX_ARB_ERROR_RPT_TLBPageFaultError_bits 1 #define GFX7_GFX_ARB_ERROR_RPT_TLBPageFaultError_bits 1 #define GFX6_GFX_ARB_ERROR_RPT_TLBPageFaultError_bits 1 static inline uint32_t ATTRIBUTE_PURE GFX_ARB_ERROR_RPT_TLBPageFaultError_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_GFX_ARB_ERROR_RPT_TLBPageFaultError_start 0 #define GFX8_GFX_ARB_ERROR_RPT_TLBPageFaultError_start 0 #define GFX75_GFX_ARB_ERROR_RPT_TLBPageFaultError_start 0 #define GFX7_GFX_ARB_ERROR_RPT_TLBPageFaultError_start 0 #define GFX6_GFX_ARB_ERROR_RPT_TLBPageFaultError_start 0 static inline uint32_t ATTRIBUTE_PURE GFX_ARB_ERROR_RPT_TLBPageFaultError_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GFX_ARB_ERROR_RPT::TLB Page VTD Translation Error */ #define GFX9_GFX_ARB_ERROR_RPT_TLBPageVTDTranslationError_bits 1 #define GFX8_GFX_ARB_ERROR_RPT_TLBPageVTDTranslationError_bits 1 #define GFX75_GFX_ARB_ERROR_RPT_TLBPageVTDTranslationError_bits 1 #define GFX7_GFX_ARB_ERROR_RPT_TLBPageVTDTranslationError_bits 1 #define GFX6_GFX_ARB_ERROR_RPT_TLBPageVTDTranslationError_bits 1 static inline uint32_t ATTRIBUTE_PURE GFX_ARB_ERROR_RPT_TLBPageVTDTranslationError_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_GFX_ARB_ERROR_RPT_TLBPageVTDTranslationError_start 4 #define GFX8_GFX_ARB_ERROR_RPT_TLBPageVTDTranslationError_start 4 #define GFX75_GFX_ARB_ERROR_RPT_TLBPageVTDTranslationError_start 4 #define GFX7_GFX_ARB_ERROR_RPT_TLBPageVTDTranslationError_start 4 #define GFX6_GFX_ARB_ERROR_RPT_TLBPageVTDTranslationError_start 4 static inline uint32_t ATTRIBUTE_PURE GFX_ARB_ERROR_RPT_TLBPageVTDTranslationError_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 4; case 80: return 4; case 75: return 4; case 70: return 4; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GFX_ARB_ERROR_RPT::Unloaded PD Error */ #define GFX9_GFX_ARB_ERROR_RPT_UnloadedPDError_bits 1 #define GFX8_GFX_ARB_ERROR_RPT_UnloadedPDError_bits 1 #define GFX75_GFX_ARB_ERROR_RPT_UnloadedPDError_bits 1 #define GFX7_GFX_ARB_ERROR_RPT_UnloadedPDError_bits 1 #define GFX6_GFX_ARB_ERROR_RPT_UnloadedPDError_bits 1 static inline uint32_t ATTRIBUTE_PURE GFX_ARB_ERROR_RPT_UnloadedPDError_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_GFX_ARB_ERROR_RPT_UnloadedPDError_start 8 #define GFX8_GFX_ARB_ERROR_RPT_UnloadedPDError_start 8 #define GFX75_GFX_ARB_ERROR_RPT_UnloadedPDError_start 8 #define GFX7_GFX_ARB_ERROR_RPT_UnloadedPDError_start 8 #define GFX6_GFX_ARB_ERROR_RPT_UnloadedPDError_start 8 static inline uint32_t ATTRIBUTE_PURE GFX_ARB_ERROR_RPT_UnloadedPDError_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GFX_ARB_ERROR_RPT::WRDP PAVP Invalid */ #define GFX9_GFX_ARB_ERROR_RPT_WRDPPAVPInvalid_bits 1 #define GFX8_GFX_ARB_ERROR_RPT_WRDPPAVPInvalid_bits 1 static inline uint32_t ATTRIBUTE_PURE GFX_ARB_ERROR_RPT_WRDPPAVPInvalid_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_GFX_ARB_ERROR_RPT_WRDPPAVPInvalid_start 5 #define GFX8_GFX_ARB_ERROR_RPT_WRDPPAVPInvalid_start 5 static inline uint32_t ATTRIBUTE_PURE GFX_ARB_ERROR_RPT_WRDPPAVPInvalid_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 5; case 80: return 5; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GFX_AUX_TABLE_BASE_ADDR */ #define GFX125_GFX_AUX_TABLE_BASE_ADDR_length 2 #define GFX12_GFX_AUX_TABLE_BASE_ADDR_length 2 static inline uint32_t ATTRIBUTE_PURE GFX_AUX_TABLE_BASE_ADDR_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GFX_AUX_TABLE_BASE_ADDR::Address */ #define GFX125_GFX_AUX_TABLE_BASE_ADDR_Address_bits 64 #define GFX12_GFX_AUX_TABLE_BASE_ADDR_Address_bits 64 static inline uint32_t ATTRIBUTE_PURE GFX_AUX_TABLE_BASE_ADDR_Address_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_GFX_AUX_TABLE_BASE_ADDR_Address_start 0 #define GFX12_GFX_AUX_TABLE_BASE_ADDR_Address_start 0 static inline uint32_t ATTRIBUTE_PURE GFX_AUX_TABLE_BASE_ADDR_Address_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GFX_CCS_AUX_INV */ #define GFX125_GFX_CCS_AUX_INV_length 1 #define GFX12_GFX_CCS_AUX_INV_length 1 static inline uint32_t ATTRIBUTE_PURE GFX_CCS_AUX_INV_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GFX_CCS_AUX_INV::Aux Inv */ #define GFX125_GFX_CCS_AUX_INV_AuxInv_bits 1 #define GFX12_GFX_CCS_AUX_INV_AuxInv_bits 1 static inline uint32_t ATTRIBUTE_PURE GFX_CCS_AUX_INV_AuxInv_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_GFX_CCS_AUX_INV_AuxInv_start 0 #define GFX12_GFX_CCS_AUX_INV_AuxInv_start 0 static inline uint32_t ATTRIBUTE_PURE GFX_CCS_AUX_INV_AuxInv_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GPGPU_CSR_BASE_ADDRESS */ #define GFX9_GPGPU_CSR_BASE_ADDRESS_length 3 #define GFX8_GPGPU_CSR_BASE_ADDRESS_length 3 #define GFX75_GPGPU_CSR_BASE_ADDRESS_length 2 static inline uint32_t ATTRIBUTE_PURE GPGPU_CSR_BASE_ADDRESS_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 3; case 80: return 3; case 75: return 2; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GPGPU_CSR_BASE_ADDRESS::3D Command Opcode */ #define GFX9_GPGPU_CSR_BASE_ADDRESS_3DCommandOpcode_bits 3 #define GFX8_GPGPU_CSR_BASE_ADDRESS_3DCommandOpcode_bits 3 #define GFX75_GPGPU_CSR_BASE_ADDRESS_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE GPGPU_CSR_BASE_ADDRESS_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_GPGPU_CSR_BASE_ADDRESS_3DCommandOpcode_start 24 #define GFX8_GPGPU_CSR_BASE_ADDRESS_3DCommandOpcode_start 24 #define GFX75_GPGPU_CSR_BASE_ADDRESS_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE GPGPU_CSR_BASE_ADDRESS_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GPGPU_CSR_BASE_ADDRESS::3D Command Sub Opcode */ #define GFX9_GPGPU_CSR_BASE_ADDRESS_3DCommandSubOpcode_bits 8 #define GFX8_GPGPU_CSR_BASE_ADDRESS_3DCommandSubOpcode_bits 8 #define GFX75_GPGPU_CSR_BASE_ADDRESS_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE GPGPU_CSR_BASE_ADDRESS_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_GPGPU_CSR_BASE_ADDRESS_3DCommandSubOpcode_start 16 #define GFX8_GPGPU_CSR_BASE_ADDRESS_3DCommandSubOpcode_start 16 #define GFX75_GPGPU_CSR_BASE_ADDRESS_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE GPGPU_CSR_BASE_ADDRESS_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GPGPU_CSR_BASE_ADDRESS::Command SubType */ #define GFX9_GPGPU_CSR_BASE_ADDRESS_CommandSubType_bits 2 #define GFX8_GPGPU_CSR_BASE_ADDRESS_CommandSubType_bits 2 #define GFX75_GPGPU_CSR_BASE_ADDRESS_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE GPGPU_CSR_BASE_ADDRESS_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_GPGPU_CSR_BASE_ADDRESS_CommandSubType_start 27 #define GFX8_GPGPU_CSR_BASE_ADDRESS_CommandSubType_start 27 #define GFX75_GPGPU_CSR_BASE_ADDRESS_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE GPGPU_CSR_BASE_ADDRESS_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GPGPU_CSR_BASE_ADDRESS::Command Type */ #define GFX9_GPGPU_CSR_BASE_ADDRESS_CommandType_bits 3 #define GFX8_GPGPU_CSR_BASE_ADDRESS_CommandType_bits 3 #define GFX75_GPGPU_CSR_BASE_ADDRESS_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE GPGPU_CSR_BASE_ADDRESS_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_GPGPU_CSR_BASE_ADDRESS_CommandType_start 29 #define GFX8_GPGPU_CSR_BASE_ADDRESS_CommandType_start 29 #define GFX75_GPGPU_CSR_BASE_ADDRESS_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE GPGPU_CSR_BASE_ADDRESS_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GPGPU_CSR_BASE_ADDRESS::DWord Length */ #define GFX9_GPGPU_CSR_BASE_ADDRESS_DWordLength_bits 8 #define GFX8_GPGPU_CSR_BASE_ADDRESS_DWordLength_bits 8 #define GFX75_GPGPU_CSR_BASE_ADDRESS_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE GPGPU_CSR_BASE_ADDRESS_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_GPGPU_CSR_BASE_ADDRESS_DWordLength_start 0 #define GFX8_GPGPU_CSR_BASE_ADDRESS_DWordLength_start 0 #define GFX75_GPGPU_CSR_BASE_ADDRESS_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE GPGPU_CSR_BASE_ADDRESS_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GPGPU_CSR_BASE_ADDRESS::GPGPU CSR Base Address */ #define GFX9_GPGPU_CSR_BASE_ADDRESS_GPGPUCSRBaseAddress_bits 52 #define GFX8_GPGPU_CSR_BASE_ADDRESS_GPGPUCSRBaseAddress_bits 52 #define GFX75_GPGPU_CSR_BASE_ADDRESS_GPGPUCSRBaseAddress_bits 20 static inline uint32_t ATTRIBUTE_PURE GPGPU_CSR_BASE_ADDRESS_GPGPUCSRBaseAddress_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 52; case 80: return 52; case 75: return 20; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_GPGPU_CSR_BASE_ADDRESS_GPGPUCSRBaseAddress_start 44 #define GFX8_GPGPU_CSR_BASE_ADDRESS_GPGPUCSRBaseAddress_start 44 #define GFX75_GPGPU_CSR_BASE_ADDRESS_GPGPUCSRBaseAddress_start 44 static inline uint32_t ATTRIBUTE_PURE GPGPU_CSR_BASE_ADDRESS_GPGPUCSRBaseAddress_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 44; case 80: return 44; case 75: return 44; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GPGPU_OBJECT */ #define GFX75_GPGPU_OBJECT_length 8 #define GFX7_GPGPU_OBJECT_length 8 static inline uint32_t ATTRIBUTE_PURE GPGPU_OBJECT_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GPGPU_OBJECT::Command Type */ #define GFX75_GPGPU_OBJECT_CommandType_bits 3 #define GFX7_GPGPU_OBJECT_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE GPGPU_OBJECT_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_GPGPU_OBJECT_CommandType_start 29 #define GFX7_GPGPU_OBJECT_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE GPGPU_OBJECT_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 29; case 70: return 29; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GPGPU_OBJECT::DWord Length */ #define GFX75_GPGPU_OBJECT_DWordLength_bits 8 #define GFX7_GPGPU_OBJECT_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE GPGPU_OBJECT_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_GPGPU_OBJECT_DWordLength_start 0 #define GFX7_GPGPU_OBJECT_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE GPGPU_OBJECT_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GPGPU_OBJECT::End of Thread Group */ #define GFX75_GPGPU_OBJECT_EndofThreadGroup_bits 1 #define GFX7_GPGPU_OBJECT_EndofThreadGroup_bits 1 static inline uint32_t ATTRIBUTE_PURE GPGPU_OBJECT_EndofThreadGroup_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_GPGPU_OBJECT_EndofThreadGroup_start 88 #define GFX7_GPGPU_OBJECT_EndofThreadGroup_start 88 static inline uint32_t ATTRIBUTE_PURE GPGPU_OBJECT_EndofThreadGroup_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 88; case 70: return 88; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GPGPU_OBJECT::Execution Mask */ #define GFX75_GPGPU_OBJECT_ExecutionMask_bits 32 #define GFX7_GPGPU_OBJECT_ExecutionMask_bits 32 static inline uint32_t ATTRIBUTE_PURE GPGPU_OBJECT_ExecutionMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 32; case 70: return 32; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_GPGPU_OBJECT_ExecutionMask_start 224 #define GFX7_GPGPU_OBJECT_ExecutionMask_start 224 static inline uint32_t ATTRIBUTE_PURE GPGPU_OBJECT_ExecutionMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 224; case 70: return 224; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GPGPU_OBJECT::Half-Slice Destination Select */ #define GFX75_GPGPU_OBJECT_HalfSliceDestinationSelect_bits 2 #define GFX7_GPGPU_OBJECT_HalfSliceDestinationSelect_bits 2 static inline uint32_t ATTRIBUTE_PURE GPGPU_OBJECT_HalfSliceDestinationSelect_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_GPGPU_OBJECT_HalfSliceDestinationSelect_start 81 #define GFX7_GPGPU_OBJECT_HalfSliceDestinationSelect_start 81 static inline uint32_t ATTRIBUTE_PURE GPGPU_OBJECT_HalfSliceDestinationSelect_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 81; case 70: return 81; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GPGPU_OBJECT::Indirect Data Length */ #define GFX75_GPGPU_OBJECT_IndirectDataLength_bits 17 #define GFX7_GPGPU_OBJECT_IndirectDataLength_bits 17 static inline uint32_t ATTRIBUTE_PURE GPGPU_OBJECT_IndirectDataLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 17; case 70: return 17; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_GPGPU_OBJECT_IndirectDataLength_start 64 #define GFX7_GPGPU_OBJECT_IndirectDataLength_start 64 static inline uint32_t ATTRIBUTE_PURE GPGPU_OBJECT_IndirectDataLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 64; case 70: return 64; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GPGPU_OBJECT::Indirect Data Start Address */ #define GFX75_GPGPU_OBJECT_IndirectDataStartAddress_bits 32 #define GFX7_GPGPU_OBJECT_IndirectDataStartAddress_bits 32 static inline uint32_t ATTRIBUTE_PURE GPGPU_OBJECT_IndirectDataStartAddress_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 32; case 70: return 32; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_GPGPU_OBJECT_IndirectDataStartAddress_start 96 #define GFX7_GPGPU_OBJECT_IndirectDataStartAddress_start 96 static inline uint32_t ATTRIBUTE_PURE GPGPU_OBJECT_IndirectDataStartAddress_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 96; case 70: return 96; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GPGPU_OBJECT::Interface Descriptor Offset */ #define GFX75_GPGPU_OBJECT_InterfaceDescriptorOffset_bits 6 #define GFX7_GPGPU_OBJECT_InterfaceDescriptorOffset_bits 5 static inline uint32_t ATTRIBUTE_PURE GPGPU_OBJECT_InterfaceDescriptorOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 6; case 70: return 5; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_GPGPU_OBJECT_InterfaceDescriptorOffset_start 32 #define GFX7_GPGPU_OBJECT_InterfaceDescriptorOffset_start 32 static inline uint32_t ATTRIBUTE_PURE GPGPU_OBJECT_InterfaceDescriptorOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 32; case 70: return 32; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GPGPU_OBJECT::Media Command Opcode */ #define GFX75_GPGPU_OBJECT_MediaCommandOpcode_bits 3 #define GFX7_GPGPU_OBJECT_MediaCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE GPGPU_OBJECT_MediaCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_GPGPU_OBJECT_MediaCommandOpcode_start 24 #define GFX7_GPGPU_OBJECT_MediaCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE GPGPU_OBJECT_MediaCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 24; case 70: return 24; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GPGPU_OBJECT::Pipeline */ #define GFX75_GPGPU_OBJECT_Pipeline_bits 2 #define GFX7_GPGPU_OBJECT_Pipeline_bits 2 static inline uint32_t ATTRIBUTE_PURE GPGPU_OBJECT_Pipeline_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_GPGPU_OBJECT_Pipeline_start 27 #define GFX7_GPGPU_OBJECT_Pipeline_start 27 static inline uint32_t ATTRIBUTE_PURE GPGPU_OBJECT_Pipeline_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 27; case 70: return 27; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GPGPU_OBJECT::Predicate Enable */ #define GFX75_GPGPU_OBJECT_PredicateEnable_bits 1 #define GFX7_GPGPU_OBJECT_PredicateEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE GPGPU_OBJECT_PredicateEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_GPGPU_OBJECT_PredicateEnable_start 8 #define GFX7_GPGPU_OBJECT_PredicateEnable_start 8 static inline uint32_t ATTRIBUTE_PURE GPGPU_OBJECT_PredicateEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GPGPU_OBJECT::Shared Local Memory Fixed Offset */ #define GFX75_GPGPU_OBJECT_SharedLocalMemoryFixedOffset_bits 1 #define GFX7_GPGPU_OBJECT_SharedLocalMemoryFixedOffset_bits 1 static inline uint32_t ATTRIBUTE_PURE GPGPU_OBJECT_SharedLocalMemoryFixedOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_GPGPU_OBJECT_SharedLocalMemoryFixedOffset_start 39 #define GFX7_GPGPU_OBJECT_SharedLocalMemoryFixedOffset_start 39 static inline uint32_t ATTRIBUTE_PURE GPGPU_OBJECT_SharedLocalMemoryFixedOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 39; case 70: return 39; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GPGPU_OBJECT::Shared Local Memory Offset */ #define GFX75_GPGPU_OBJECT_SharedLocalMemoryOffset_bits 4 #define GFX7_GPGPU_OBJECT_SharedLocalMemoryOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE GPGPU_OBJECT_SharedLocalMemoryOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 4; case 70: return 4; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_GPGPU_OBJECT_SharedLocalMemoryOffset_start 92 #define GFX7_GPGPU_OBJECT_SharedLocalMemoryOffset_start 92 static inline uint32_t ATTRIBUTE_PURE GPGPU_OBJECT_SharedLocalMemoryOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 92; case 70: return 92; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GPGPU_OBJECT::Slice Destination Select */ #define GFX75_GPGPU_OBJECT_SliceDestinationSelect_bits 1 static inline uint32_t ATTRIBUTE_PURE GPGPU_OBJECT_SliceDestinationSelect_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_GPGPU_OBJECT_SliceDestinationSelect_start 83 static inline uint32_t ATTRIBUTE_PURE GPGPU_OBJECT_SliceDestinationSelect_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 83; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GPGPU_OBJECT::SubOpcode */ #define GFX75_GPGPU_OBJECT_SubOpcode_bits 8 #define GFX7_GPGPU_OBJECT_SubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE GPGPU_OBJECT_SubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_GPGPU_OBJECT_SubOpcode_start 16 #define GFX7_GPGPU_OBJECT_SubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE GPGPU_OBJECT_SubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 16; case 70: return 16; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GPGPU_OBJECT::Thread Group ID X */ #define GFX75_GPGPU_OBJECT_ThreadGroupIDX_bits 32 #define GFX7_GPGPU_OBJECT_ThreadGroupIDX_bits 32 static inline uint32_t ATTRIBUTE_PURE GPGPU_OBJECT_ThreadGroupIDX_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 32; case 70: return 32; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_GPGPU_OBJECT_ThreadGroupIDX_start 128 #define GFX7_GPGPU_OBJECT_ThreadGroupIDX_start 128 static inline uint32_t ATTRIBUTE_PURE GPGPU_OBJECT_ThreadGroupIDX_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 128; case 70: return 128; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GPGPU_OBJECT::Thread Group ID Y */ #define GFX75_GPGPU_OBJECT_ThreadGroupIDY_bits 32 #define GFX7_GPGPU_OBJECT_ThreadGroupIDY_bits 32 static inline uint32_t ATTRIBUTE_PURE GPGPU_OBJECT_ThreadGroupIDY_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 32; case 70: return 32; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_GPGPU_OBJECT_ThreadGroupIDY_start 160 #define GFX7_GPGPU_OBJECT_ThreadGroupIDY_start 160 static inline uint32_t ATTRIBUTE_PURE GPGPU_OBJECT_ThreadGroupIDY_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 160; case 70: return 160; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GPGPU_OBJECT::Thread Group ID Z */ #define GFX75_GPGPU_OBJECT_ThreadGroupIDZ_bits 32 #define GFX7_GPGPU_OBJECT_ThreadGroupIDZ_bits 32 static inline uint32_t ATTRIBUTE_PURE GPGPU_OBJECT_ThreadGroupIDZ_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 32; case 70: return 32; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_GPGPU_OBJECT_ThreadGroupIDZ_start 192 #define GFX7_GPGPU_OBJECT_ThreadGroupIDZ_start 192 static inline uint32_t ATTRIBUTE_PURE GPGPU_OBJECT_ThreadGroupIDZ_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 192; case 70: return 192; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GPGPU_WALKER */ #define GFX12_GPGPU_WALKER_length 15 #define GFX11_GPGPU_WALKER_length 15 #define GFX9_GPGPU_WALKER_length 15 #define GFX8_GPGPU_WALKER_length 15 #define GFX75_GPGPU_WALKER_length 11 #define GFX7_GPGPU_WALKER_length 11 static inline uint32_t ATTRIBUTE_PURE GPGPU_WALKER_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 15; case 110: return 15; case 90: return 15; case 80: return 15; case 75: return 11; case 70: return 11; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GPGPU_WALKER::Bottom Execution Mask */ #define GFX12_GPGPU_WALKER_BottomExecutionMask_bits 32 #define GFX11_GPGPU_WALKER_BottomExecutionMask_bits 32 #define GFX9_GPGPU_WALKER_BottomExecutionMask_bits 32 #define GFX8_GPGPU_WALKER_BottomExecutionMask_bits 32 #define GFX75_GPGPU_WALKER_BottomExecutionMask_bits 32 #define GFX7_GPGPU_WALKER_BottomExecutionMask_bits 32 static inline uint32_t ATTRIBUTE_PURE GPGPU_WALKER_BottomExecutionMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_GPGPU_WALKER_BottomExecutionMask_start 448 #define GFX11_GPGPU_WALKER_BottomExecutionMask_start 448 #define GFX9_GPGPU_WALKER_BottomExecutionMask_start 448 #define GFX8_GPGPU_WALKER_BottomExecutionMask_start 448 #define GFX75_GPGPU_WALKER_BottomExecutionMask_start 320 #define GFX7_GPGPU_WALKER_BottomExecutionMask_start 320 static inline uint32_t ATTRIBUTE_PURE GPGPU_WALKER_BottomExecutionMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 448; case 110: return 448; case 90: return 448; case 80: return 448; case 75: return 320; case 70: return 320; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GPGPU_WALKER::Command Type */ #define GFX12_GPGPU_WALKER_CommandType_bits 3 #define GFX11_GPGPU_WALKER_CommandType_bits 3 #define GFX9_GPGPU_WALKER_CommandType_bits 3 #define GFX8_GPGPU_WALKER_CommandType_bits 3 #define GFX75_GPGPU_WALKER_CommandType_bits 3 #define GFX7_GPGPU_WALKER_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE GPGPU_WALKER_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_GPGPU_WALKER_CommandType_start 29 #define GFX11_GPGPU_WALKER_CommandType_start 29 #define GFX9_GPGPU_WALKER_CommandType_start 29 #define GFX8_GPGPU_WALKER_CommandType_start 29 #define GFX75_GPGPU_WALKER_CommandType_start 29 #define GFX7_GPGPU_WALKER_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE GPGPU_WALKER_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GPGPU_WALKER::DWord Length */ #define GFX12_GPGPU_WALKER_DWordLength_bits 8 #define GFX11_GPGPU_WALKER_DWordLength_bits 8 #define GFX9_GPGPU_WALKER_DWordLength_bits 8 #define GFX8_GPGPU_WALKER_DWordLength_bits 8 #define GFX75_GPGPU_WALKER_DWordLength_bits 8 #define GFX7_GPGPU_WALKER_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE GPGPU_WALKER_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_GPGPU_WALKER_DWordLength_start 0 #define GFX11_GPGPU_WALKER_DWordLength_start 0 #define GFX9_GPGPU_WALKER_DWordLength_start 0 #define GFX8_GPGPU_WALKER_DWordLength_start 0 #define GFX75_GPGPU_WALKER_DWordLength_start 0 #define GFX7_GPGPU_WALKER_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE GPGPU_WALKER_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GPGPU_WALKER::Indirect Data Length */ #define GFX12_GPGPU_WALKER_IndirectDataLength_bits 17 #define GFX11_GPGPU_WALKER_IndirectDataLength_bits 17 #define GFX9_GPGPU_WALKER_IndirectDataLength_bits 17 #define GFX8_GPGPU_WALKER_IndirectDataLength_bits 17 static inline uint32_t ATTRIBUTE_PURE GPGPU_WALKER_IndirectDataLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 17; case 110: return 17; case 90: return 17; case 80: return 17; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_GPGPU_WALKER_IndirectDataLength_start 64 #define GFX11_GPGPU_WALKER_IndirectDataLength_start 64 #define GFX9_GPGPU_WALKER_IndirectDataLength_start 64 #define GFX8_GPGPU_WALKER_IndirectDataLength_start 64 static inline uint32_t ATTRIBUTE_PURE GPGPU_WALKER_IndirectDataLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 64; case 110: return 64; case 90: return 64; case 80: return 64; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GPGPU_WALKER::Indirect Data Start Address */ #define GFX12_GPGPU_WALKER_IndirectDataStartAddress_bits 26 #define GFX11_GPGPU_WALKER_IndirectDataStartAddress_bits 26 #define GFX9_GPGPU_WALKER_IndirectDataStartAddress_bits 26 #define GFX8_GPGPU_WALKER_IndirectDataStartAddress_bits 26 static inline uint32_t ATTRIBUTE_PURE GPGPU_WALKER_IndirectDataStartAddress_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 26; case 110: return 26; case 90: return 26; case 80: return 26; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_GPGPU_WALKER_IndirectDataStartAddress_start 102 #define GFX11_GPGPU_WALKER_IndirectDataStartAddress_start 102 #define GFX9_GPGPU_WALKER_IndirectDataStartAddress_start 102 #define GFX8_GPGPU_WALKER_IndirectDataStartAddress_start 102 static inline uint32_t ATTRIBUTE_PURE GPGPU_WALKER_IndirectDataStartAddress_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 102; case 110: return 102; case 90: return 102; case 80: return 102; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GPGPU_WALKER::Indirect Parameter Enable */ #define GFX12_GPGPU_WALKER_IndirectParameterEnable_bits 1 #define GFX11_GPGPU_WALKER_IndirectParameterEnable_bits 1 #define GFX9_GPGPU_WALKER_IndirectParameterEnable_bits 1 #define GFX8_GPGPU_WALKER_IndirectParameterEnable_bits 1 #define GFX75_GPGPU_WALKER_IndirectParameterEnable_bits 1 #define GFX7_GPGPU_WALKER_IndirectParameterEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE GPGPU_WALKER_IndirectParameterEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_GPGPU_WALKER_IndirectParameterEnable_start 10 #define GFX11_GPGPU_WALKER_IndirectParameterEnable_start 10 #define GFX9_GPGPU_WALKER_IndirectParameterEnable_start 10 #define GFX8_GPGPU_WALKER_IndirectParameterEnable_start 10 #define GFX75_GPGPU_WALKER_IndirectParameterEnable_start 10 #define GFX7_GPGPU_WALKER_IndirectParameterEnable_start 10 static inline uint32_t ATTRIBUTE_PURE GPGPU_WALKER_IndirectParameterEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 10; case 110: return 10; case 90: return 10; case 80: return 10; case 75: return 10; case 70: return 10; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GPGPU_WALKER::Interface Descriptor Offset */ #define GFX12_GPGPU_WALKER_InterfaceDescriptorOffset_bits 6 #define GFX11_GPGPU_WALKER_InterfaceDescriptorOffset_bits 6 #define GFX9_GPGPU_WALKER_InterfaceDescriptorOffset_bits 6 #define GFX8_GPGPU_WALKER_InterfaceDescriptorOffset_bits 6 #define GFX75_GPGPU_WALKER_InterfaceDescriptorOffset_bits 6 #define GFX7_GPGPU_WALKER_InterfaceDescriptorOffset_bits 5 static inline uint32_t ATTRIBUTE_PURE GPGPU_WALKER_InterfaceDescriptorOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 5; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_GPGPU_WALKER_InterfaceDescriptorOffset_start 32 #define GFX11_GPGPU_WALKER_InterfaceDescriptorOffset_start 32 #define GFX9_GPGPU_WALKER_InterfaceDescriptorOffset_start 32 #define GFX8_GPGPU_WALKER_InterfaceDescriptorOffset_start 32 #define GFX75_GPGPU_WALKER_InterfaceDescriptorOffset_start 32 #define GFX7_GPGPU_WALKER_InterfaceDescriptorOffset_start 32 static inline uint32_t ATTRIBUTE_PURE GPGPU_WALKER_InterfaceDescriptorOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GPGPU_WALKER::Media Command Opcode */ #define GFX12_GPGPU_WALKER_MediaCommandOpcode_bits 3 #define GFX11_GPGPU_WALKER_MediaCommandOpcode_bits 3 #define GFX9_GPGPU_WALKER_MediaCommandOpcode_bits 3 #define GFX8_GPGPU_WALKER_MediaCommandOpcode_bits 3 #define GFX75_GPGPU_WALKER_MediaCommandOpcode_bits 3 #define GFX7_GPGPU_WALKER_MediaCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE GPGPU_WALKER_MediaCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_GPGPU_WALKER_MediaCommandOpcode_start 24 #define GFX11_GPGPU_WALKER_MediaCommandOpcode_start 24 #define GFX9_GPGPU_WALKER_MediaCommandOpcode_start 24 #define GFX8_GPGPU_WALKER_MediaCommandOpcode_start 24 #define GFX75_GPGPU_WALKER_MediaCommandOpcode_start 24 #define GFX7_GPGPU_WALKER_MediaCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE GPGPU_WALKER_MediaCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GPGPU_WALKER::Pipeline */ #define GFX12_GPGPU_WALKER_Pipeline_bits 2 #define GFX11_GPGPU_WALKER_Pipeline_bits 2 #define GFX9_GPGPU_WALKER_Pipeline_bits 2 #define GFX8_GPGPU_WALKER_Pipeline_bits 2 #define GFX75_GPGPU_WALKER_Pipeline_bits 2 #define GFX7_GPGPU_WALKER_Pipeline_bits 2 static inline uint32_t ATTRIBUTE_PURE GPGPU_WALKER_Pipeline_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_GPGPU_WALKER_Pipeline_start 27 #define GFX11_GPGPU_WALKER_Pipeline_start 27 #define GFX9_GPGPU_WALKER_Pipeline_start 27 #define GFX8_GPGPU_WALKER_Pipeline_start 27 #define GFX75_GPGPU_WALKER_Pipeline_start 27 #define GFX7_GPGPU_WALKER_Pipeline_start 27 static inline uint32_t ATTRIBUTE_PURE GPGPU_WALKER_Pipeline_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GPGPU_WALKER::Predicate Enable */ #define GFX12_GPGPU_WALKER_PredicateEnable_bits 1 #define GFX11_GPGPU_WALKER_PredicateEnable_bits 1 #define GFX9_GPGPU_WALKER_PredicateEnable_bits 1 #define GFX8_GPGPU_WALKER_PredicateEnable_bits 1 #define GFX75_GPGPU_WALKER_PredicateEnable_bits 1 #define GFX7_GPGPU_WALKER_PredicateEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE GPGPU_WALKER_PredicateEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_GPGPU_WALKER_PredicateEnable_start 8 #define GFX11_GPGPU_WALKER_PredicateEnable_start 8 #define GFX9_GPGPU_WALKER_PredicateEnable_start 8 #define GFX8_GPGPU_WALKER_PredicateEnable_start 8 #define GFX75_GPGPU_WALKER_PredicateEnable_start 8 #define GFX7_GPGPU_WALKER_PredicateEnable_start 8 static inline uint32_t ATTRIBUTE_PURE GPGPU_WALKER_PredicateEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GPGPU_WALKER::Right Execution Mask */ #define GFX12_GPGPU_WALKER_RightExecutionMask_bits 32 #define GFX11_GPGPU_WALKER_RightExecutionMask_bits 32 #define GFX9_GPGPU_WALKER_RightExecutionMask_bits 32 #define GFX8_GPGPU_WALKER_RightExecutionMask_bits 32 #define GFX75_GPGPU_WALKER_RightExecutionMask_bits 32 #define GFX7_GPGPU_WALKER_RightExecutionMask_bits 32 static inline uint32_t ATTRIBUTE_PURE GPGPU_WALKER_RightExecutionMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_GPGPU_WALKER_RightExecutionMask_start 416 #define GFX11_GPGPU_WALKER_RightExecutionMask_start 416 #define GFX9_GPGPU_WALKER_RightExecutionMask_start 416 #define GFX8_GPGPU_WALKER_RightExecutionMask_start 416 #define GFX75_GPGPU_WALKER_RightExecutionMask_start 288 #define GFX7_GPGPU_WALKER_RightExecutionMask_start 288 static inline uint32_t ATTRIBUTE_PURE GPGPU_WALKER_RightExecutionMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 416; case 110: return 416; case 90: return 416; case 80: return 416; case 75: return 288; case 70: return 288; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GPGPU_WALKER::SIMD Size */ #define GFX12_GPGPU_WALKER_SIMDSize_bits 2 #define GFX11_GPGPU_WALKER_SIMDSize_bits 2 #define GFX9_GPGPU_WALKER_SIMDSize_bits 2 #define GFX8_GPGPU_WALKER_SIMDSize_bits 2 #define GFX75_GPGPU_WALKER_SIMDSize_bits 2 #define GFX7_GPGPU_WALKER_SIMDSize_bits 2 static inline uint32_t ATTRIBUTE_PURE GPGPU_WALKER_SIMDSize_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_GPGPU_WALKER_SIMDSize_start 158 #define GFX11_GPGPU_WALKER_SIMDSize_start 158 #define GFX9_GPGPU_WALKER_SIMDSize_start 158 #define GFX8_GPGPU_WALKER_SIMDSize_start 158 #define GFX75_GPGPU_WALKER_SIMDSize_start 94 #define GFX7_GPGPU_WALKER_SIMDSize_start 94 static inline uint32_t ATTRIBUTE_PURE GPGPU_WALKER_SIMDSize_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 158; case 110: return 158; case 90: return 158; case 80: return 158; case 75: return 94; case 70: return 94; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GPGPU_WALKER::SubOpcode */ #define GFX12_GPGPU_WALKER_SubOpcode_bits 8 #define GFX11_GPGPU_WALKER_SubOpcode_bits 8 #define GFX9_GPGPU_WALKER_SubOpcode_bits 8 #define GFX8_GPGPU_WALKER_SubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE GPGPU_WALKER_SubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_GPGPU_WALKER_SubOpcode_start 16 #define GFX11_GPGPU_WALKER_SubOpcode_start 16 #define GFX9_GPGPU_WALKER_SubOpcode_start 16 #define GFX8_GPGPU_WALKER_SubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE GPGPU_WALKER_SubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GPGPU_WALKER::SubOpcode A */ #define GFX75_GPGPU_WALKER_SubOpcodeA_bits 8 #define GFX7_GPGPU_WALKER_SubOpcodeA_bits 8 static inline uint32_t ATTRIBUTE_PURE GPGPU_WALKER_SubOpcodeA_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_GPGPU_WALKER_SubOpcodeA_start 16 #define GFX7_GPGPU_WALKER_SubOpcodeA_start 16 static inline uint32_t ATTRIBUTE_PURE GPGPU_WALKER_SubOpcodeA_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 16; case 70: return 16; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GPGPU_WALKER::Thread Depth Counter Maximum */ #define GFX12_GPGPU_WALKER_ThreadDepthCounterMaximum_bits 6 #define GFX11_GPGPU_WALKER_ThreadDepthCounterMaximum_bits 6 #define GFX9_GPGPU_WALKER_ThreadDepthCounterMaximum_bits 6 #define GFX8_GPGPU_WALKER_ThreadDepthCounterMaximum_bits 6 #define GFX75_GPGPU_WALKER_ThreadDepthCounterMaximum_bits 6 #define GFX7_GPGPU_WALKER_ThreadDepthCounterMaximum_bits 6 static inline uint32_t ATTRIBUTE_PURE GPGPU_WALKER_ThreadDepthCounterMaximum_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 6; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_GPGPU_WALKER_ThreadDepthCounterMaximum_start 144 #define GFX11_GPGPU_WALKER_ThreadDepthCounterMaximum_start 144 #define GFX9_GPGPU_WALKER_ThreadDepthCounterMaximum_start 144 #define GFX8_GPGPU_WALKER_ThreadDepthCounterMaximum_start 144 #define GFX75_GPGPU_WALKER_ThreadDepthCounterMaximum_start 80 #define GFX7_GPGPU_WALKER_ThreadDepthCounterMaximum_start 80 static inline uint32_t ATTRIBUTE_PURE GPGPU_WALKER_ThreadDepthCounterMaximum_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 144; case 110: return 144; case 90: return 144; case 80: return 144; case 75: return 80; case 70: return 80; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GPGPU_WALKER::Thread Group ID Starting/Resume Z */ #define GFX12_GPGPU_WALKER_ThreadGroupIDStartingResumeZ_bits 32 #define GFX11_GPGPU_WALKER_ThreadGroupIDStartingResumeZ_bits 32 #define GFX9_GPGPU_WALKER_ThreadGroupIDStartingResumeZ_bits 32 #define GFX8_GPGPU_WALKER_ThreadGroupIDStartingResumeZ_bits 32 static inline uint32_t ATTRIBUTE_PURE GPGPU_WALKER_ThreadGroupIDStartingResumeZ_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_GPGPU_WALKER_ThreadGroupIDStartingResumeZ_start 352 #define GFX11_GPGPU_WALKER_ThreadGroupIDStartingResumeZ_start 352 #define GFX9_GPGPU_WALKER_ThreadGroupIDStartingResumeZ_start 352 #define GFX8_GPGPU_WALKER_ThreadGroupIDStartingResumeZ_start 352 static inline uint32_t ATTRIBUTE_PURE GPGPU_WALKER_ThreadGroupIDStartingResumeZ_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 352; case 110: return 352; case 90: return 352; case 80: return 352; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GPGPU_WALKER::Thread Group ID Starting X */ #define GFX12_GPGPU_WALKER_ThreadGroupIDStartingX_bits 32 #define GFX11_GPGPU_WALKER_ThreadGroupIDStartingX_bits 32 #define GFX9_GPGPU_WALKER_ThreadGroupIDStartingX_bits 32 #define GFX8_GPGPU_WALKER_ThreadGroupIDStartingX_bits 32 #define GFX75_GPGPU_WALKER_ThreadGroupIDStartingX_bits 32 #define GFX7_GPGPU_WALKER_ThreadGroupIDStartingX_bits 32 static inline uint32_t ATTRIBUTE_PURE GPGPU_WALKER_ThreadGroupIDStartingX_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_GPGPU_WALKER_ThreadGroupIDStartingX_start 160 #define GFX11_GPGPU_WALKER_ThreadGroupIDStartingX_start 160 #define GFX9_GPGPU_WALKER_ThreadGroupIDStartingX_start 160 #define GFX8_GPGPU_WALKER_ThreadGroupIDStartingX_start 160 #define GFX75_GPGPU_WALKER_ThreadGroupIDStartingX_start 96 #define GFX7_GPGPU_WALKER_ThreadGroupIDStartingX_start 96 static inline uint32_t ATTRIBUTE_PURE GPGPU_WALKER_ThreadGroupIDStartingX_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 160; case 110: return 160; case 90: return 160; case 80: return 160; case 75: return 96; case 70: return 96; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GPGPU_WALKER::Thread Group ID Starting Y */ #define GFX12_GPGPU_WALKER_ThreadGroupIDStartingY_bits 32 #define GFX11_GPGPU_WALKER_ThreadGroupIDStartingY_bits 32 #define GFX9_GPGPU_WALKER_ThreadGroupIDStartingY_bits 32 #define GFX8_GPGPU_WALKER_ThreadGroupIDStartingY_bits 32 #define GFX75_GPGPU_WALKER_ThreadGroupIDStartingY_bits 32 #define GFX7_GPGPU_WALKER_ThreadGroupIDStartingY_bits 32 static inline uint32_t ATTRIBUTE_PURE GPGPU_WALKER_ThreadGroupIDStartingY_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_GPGPU_WALKER_ThreadGroupIDStartingY_start 256 #define GFX11_GPGPU_WALKER_ThreadGroupIDStartingY_start 256 #define GFX9_GPGPU_WALKER_ThreadGroupIDStartingY_start 256 #define GFX8_GPGPU_WALKER_ThreadGroupIDStartingY_start 256 #define GFX75_GPGPU_WALKER_ThreadGroupIDStartingY_start 160 #define GFX7_GPGPU_WALKER_ThreadGroupIDStartingY_start 160 static inline uint32_t ATTRIBUTE_PURE GPGPU_WALKER_ThreadGroupIDStartingY_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 256; case 110: return 256; case 90: return 256; case 80: return 256; case 75: return 160; case 70: return 160; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GPGPU_WALKER::Thread Group ID Starting Z */ #define GFX75_GPGPU_WALKER_ThreadGroupIDStartingZ_bits 32 #define GFX7_GPGPU_WALKER_ThreadGroupIDStartingZ_bits 32 static inline uint32_t ATTRIBUTE_PURE GPGPU_WALKER_ThreadGroupIDStartingZ_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 32; case 70: return 32; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_GPGPU_WALKER_ThreadGroupIDStartingZ_start 224 #define GFX7_GPGPU_WALKER_ThreadGroupIDStartingZ_start 224 static inline uint32_t ATTRIBUTE_PURE GPGPU_WALKER_ThreadGroupIDStartingZ_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 224; case 70: return 224; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GPGPU_WALKER::Thread Group ID X Dimension */ #define GFX12_GPGPU_WALKER_ThreadGroupIDXDimension_bits 32 #define GFX11_GPGPU_WALKER_ThreadGroupIDXDimension_bits 32 #define GFX9_GPGPU_WALKER_ThreadGroupIDXDimension_bits 32 #define GFX8_GPGPU_WALKER_ThreadGroupIDXDimension_bits 32 #define GFX75_GPGPU_WALKER_ThreadGroupIDXDimension_bits 32 #define GFX7_GPGPU_WALKER_ThreadGroupIDXDimension_bits 32 static inline uint32_t ATTRIBUTE_PURE GPGPU_WALKER_ThreadGroupIDXDimension_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_GPGPU_WALKER_ThreadGroupIDXDimension_start 224 #define GFX11_GPGPU_WALKER_ThreadGroupIDXDimension_start 224 #define GFX9_GPGPU_WALKER_ThreadGroupIDXDimension_start 224 #define GFX8_GPGPU_WALKER_ThreadGroupIDXDimension_start 224 #define GFX75_GPGPU_WALKER_ThreadGroupIDXDimension_start 128 #define GFX7_GPGPU_WALKER_ThreadGroupIDXDimension_start 128 static inline uint32_t ATTRIBUTE_PURE GPGPU_WALKER_ThreadGroupIDXDimension_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 224; case 110: return 224; case 90: return 224; case 80: return 224; case 75: return 128; case 70: return 128; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GPGPU_WALKER::Thread Group ID Y Dimension */ #define GFX12_GPGPU_WALKER_ThreadGroupIDYDimension_bits 32 #define GFX11_GPGPU_WALKER_ThreadGroupIDYDimension_bits 32 #define GFX9_GPGPU_WALKER_ThreadGroupIDYDimension_bits 32 #define GFX8_GPGPU_WALKER_ThreadGroupIDYDimension_bits 32 #define GFX75_GPGPU_WALKER_ThreadGroupIDYDimension_bits 32 #define GFX7_GPGPU_WALKER_ThreadGroupIDYDimension_bits 32 static inline uint32_t ATTRIBUTE_PURE GPGPU_WALKER_ThreadGroupIDYDimension_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_GPGPU_WALKER_ThreadGroupIDYDimension_start 320 #define GFX11_GPGPU_WALKER_ThreadGroupIDYDimension_start 320 #define GFX9_GPGPU_WALKER_ThreadGroupIDYDimension_start 320 #define GFX8_GPGPU_WALKER_ThreadGroupIDYDimension_start 320 #define GFX75_GPGPU_WALKER_ThreadGroupIDYDimension_start 192 #define GFX7_GPGPU_WALKER_ThreadGroupIDYDimension_start 192 static inline uint32_t ATTRIBUTE_PURE GPGPU_WALKER_ThreadGroupIDYDimension_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 320; case 110: return 320; case 90: return 320; case 80: return 320; case 75: return 192; case 70: return 192; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GPGPU_WALKER::Thread Group ID Z Dimension */ #define GFX12_GPGPU_WALKER_ThreadGroupIDZDimension_bits 32 #define GFX11_GPGPU_WALKER_ThreadGroupIDZDimension_bits 32 #define GFX9_GPGPU_WALKER_ThreadGroupIDZDimension_bits 32 #define GFX8_GPGPU_WALKER_ThreadGroupIDZDimension_bits 32 #define GFX75_GPGPU_WALKER_ThreadGroupIDZDimension_bits 32 #define GFX7_GPGPU_WALKER_ThreadGroupIDZDimension_bits 32 static inline uint32_t ATTRIBUTE_PURE GPGPU_WALKER_ThreadGroupIDZDimension_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_GPGPU_WALKER_ThreadGroupIDZDimension_start 384 #define GFX11_GPGPU_WALKER_ThreadGroupIDZDimension_start 384 #define GFX9_GPGPU_WALKER_ThreadGroupIDZDimension_start 384 #define GFX8_GPGPU_WALKER_ThreadGroupIDZDimension_start 384 #define GFX75_GPGPU_WALKER_ThreadGroupIDZDimension_start 256 #define GFX7_GPGPU_WALKER_ThreadGroupIDZDimension_start 256 static inline uint32_t ATTRIBUTE_PURE GPGPU_WALKER_ThreadGroupIDZDimension_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 384; case 110: return 384; case 90: return 384; case 80: return 384; case 75: return 256; case 70: return 256; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GPGPU_WALKER::Thread Height Counter Maximum */ #define GFX12_GPGPU_WALKER_ThreadHeightCounterMaximum_bits 6 #define GFX11_GPGPU_WALKER_ThreadHeightCounterMaximum_bits 6 #define GFX9_GPGPU_WALKER_ThreadHeightCounterMaximum_bits 6 #define GFX8_GPGPU_WALKER_ThreadHeightCounterMaximum_bits 6 #define GFX75_GPGPU_WALKER_ThreadHeightCounterMaximum_bits 6 #define GFX7_GPGPU_WALKER_ThreadHeightCounterMaximum_bits 6 static inline uint32_t ATTRIBUTE_PURE GPGPU_WALKER_ThreadHeightCounterMaximum_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 6; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_GPGPU_WALKER_ThreadHeightCounterMaximum_start 136 #define GFX11_GPGPU_WALKER_ThreadHeightCounterMaximum_start 136 #define GFX9_GPGPU_WALKER_ThreadHeightCounterMaximum_start 136 #define GFX8_GPGPU_WALKER_ThreadHeightCounterMaximum_start 136 #define GFX75_GPGPU_WALKER_ThreadHeightCounterMaximum_start 72 #define GFX7_GPGPU_WALKER_ThreadHeightCounterMaximum_start 72 static inline uint32_t ATTRIBUTE_PURE GPGPU_WALKER_ThreadHeightCounterMaximum_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 136; case 110: return 136; case 90: return 136; case 80: return 136; case 75: return 72; case 70: return 72; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GPGPU_WALKER::Thread Width Counter Maximum */ #define GFX12_GPGPU_WALKER_ThreadWidthCounterMaximum_bits 6 #define GFX11_GPGPU_WALKER_ThreadWidthCounterMaximum_bits 6 #define GFX9_GPGPU_WALKER_ThreadWidthCounterMaximum_bits 6 #define GFX8_GPGPU_WALKER_ThreadWidthCounterMaximum_bits 6 #define GFX75_GPGPU_WALKER_ThreadWidthCounterMaximum_bits 6 #define GFX7_GPGPU_WALKER_ThreadWidthCounterMaximum_bits 6 static inline uint32_t ATTRIBUTE_PURE GPGPU_WALKER_ThreadWidthCounterMaximum_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 6; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_GPGPU_WALKER_ThreadWidthCounterMaximum_start 128 #define GFX11_GPGPU_WALKER_ThreadWidthCounterMaximum_start 128 #define GFX9_GPGPU_WALKER_ThreadWidthCounterMaximum_start 128 #define GFX8_GPGPU_WALKER_ThreadWidthCounterMaximum_start 128 #define GFX75_GPGPU_WALKER_ThreadWidthCounterMaximum_start 64 #define GFX7_GPGPU_WALKER_ThreadWidthCounterMaximum_start 64 static inline uint32_t ATTRIBUTE_PURE GPGPU_WALKER_ThreadWidthCounterMaximum_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 128; case 110: return 128; case 90: return 128; case 80: return 128; case 75: return 64; case 70: return 64; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GS_INVOCATION_COUNT */ #define GFX125_GS_INVOCATION_COUNT_length 2 #define GFX12_GS_INVOCATION_COUNT_length 2 #define GFX11_GS_INVOCATION_COUNT_length 2 #define GFX9_GS_INVOCATION_COUNT_length 2 #define GFX8_GS_INVOCATION_COUNT_length 2 #define GFX75_GS_INVOCATION_COUNT_length 2 #define GFX7_GS_INVOCATION_COUNT_length 2 static inline uint32_t ATTRIBUTE_PURE GS_INVOCATION_COUNT_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GS_INVOCATION_COUNT::GS Invocation Count Report */ #define GFX125_GS_INVOCATION_COUNT_GSInvocationCountReport_bits 64 #define GFX12_GS_INVOCATION_COUNT_GSInvocationCountReport_bits 64 #define GFX11_GS_INVOCATION_COUNT_GSInvocationCountReport_bits 64 #define GFX9_GS_INVOCATION_COUNT_GSInvocationCountReport_bits 64 #define GFX8_GS_INVOCATION_COUNT_GSInvocationCountReport_bits 64 #define GFX75_GS_INVOCATION_COUNT_GSInvocationCountReport_bits 64 #define GFX7_GS_INVOCATION_COUNT_GSInvocationCountReport_bits 64 static inline uint32_t ATTRIBUTE_PURE GS_INVOCATION_COUNT_GSInvocationCountReport_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 64; case 80: return 64; case 75: return 64; case 70: return 64; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_GS_INVOCATION_COUNT_GSInvocationCountReport_start 0 #define GFX12_GS_INVOCATION_COUNT_GSInvocationCountReport_start 0 #define GFX11_GS_INVOCATION_COUNT_GSInvocationCountReport_start 0 #define GFX9_GS_INVOCATION_COUNT_GSInvocationCountReport_start 0 #define GFX8_GS_INVOCATION_COUNT_GSInvocationCountReport_start 0 #define GFX75_GS_INVOCATION_COUNT_GSInvocationCountReport_start 0 #define GFX7_GS_INVOCATION_COUNT_GSInvocationCountReport_start 0 static inline uint32_t ATTRIBUTE_PURE GS_INVOCATION_COUNT_GSInvocationCountReport_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GS_PRIMITIVES_COUNT */ #define GFX125_GS_PRIMITIVES_COUNT_length 2 #define GFX12_GS_PRIMITIVES_COUNT_length 2 #define GFX11_GS_PRIMITIVES_COUNT_length 2 #define GFX9_GS_PRIMITIVES_COUNT_length 2 #define GFX8_GS_PRIMITIVES_COUNT_length 2 #define GFX75_GS_PRIMITIVES_COUNT_length 2 #define GFX7_GS_PRIMITIVES_COUNT_length 2 static inline uint32_t ATTRIBUTE_PURE GS_PRIMITIVES_COUNT_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GS_PRIMITIVES_COUNT::GS Primitives Count Report */ #define GFX125_GS_PRIMITIVES_COUNT_GSPrimitivesCountReport_bits 64 #define GFX12_GS_PRIMITIVES_COUNT_GSPrimitivesCountReport_bits 64 #define GFX11_GS_PRIMITIVES_COUNT_GSPrimitivesCountReport_bits 64 #define GFX9_GS_PRIMITIVES_COUNT_GSPrimitivesCountReport_bits 64 #define GFX8_GS_PRIMITIVES_COUNT_GSPrimitivesCountReport_bits 64 #define GFX75_GS_PRIMITIVES_COUNT_GSPrimitivesCountReport_bits 64 #define GFX7_GS_PRIMITIVES_COUNT_GSPrimitivesCountReport_bits 64 static inline uint32_t ATTRIBUTE_PURE GS_PRIMITIVES_COUNT_GSPrimitivesCountReport_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 64; case 80: return 64; case 75: return 64; case 70: return 64; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_GS_PRIMITIVES_COUNT_GSPrimitivesCountReport_start 0 #define GFX12_GS_PRIMITIVES_COUNT_GSPrimitivesCountReport_start 0 #define GFX11_GS_PRIMITIVES_COUNT_GSPrimitivesCountReport_start 0 #define GFX9_GS_PRIMITIVES_COUNT_GSPrimitivesCountReport_start 0 #define GFX8_GS_PRIMITIVES_COUNT_GSPrimitivesCountReport_start 0 #define GFX75_GS_PRIMITIVES_COUNT_GSPrimitivesCountReport_start 0 #define GFX7_GS_PRIMITIVES_COUNT_GSPrimitivesCountReport_start 0 static inline uint32_t ATTRIBUTE_PURE GS_PRIMITIVES_COUNT_GSPrimitivesCountReport_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GS_STATE */ #define GFX5_GS_STATE_length 7 #define GFX45_GS_STATE_length 7 #define GFX4_GS_STATE_length 7 static inline uint32_t ATTRIBUTE_PURE GS_STATE_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 7; case 45: return 7; case 40: return 7; default: unreachable("Invalid hardware generation"); } } /* GS_STATE::Binding Table Entry Count */ #define GFX5_GS_STATE_BindingTableEntryCount_bits 8 #define GFX45_GS_STATE_BindingTableEntryCount_bits 8 #define GFX4_GS_STATE_BindingTableEntryCount_bits 8 static inline uint32_t ATTRIBUTE_PURE GS_STATE_BindingTableEntryCount_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 8; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } #define GFX5_GS_STATE_BindingTableEntryCount_start 50 #define GFX45_GS_STATE_BindingTableEntryCount_start 50 #define GFX4_GS_STATE_BindingTableEntryCount_start 50 static inline uint32_t ATTRIBUTE_PURE GS_STATE_BindingTableEntryCount_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 50; case 45: return 50; case 40: return 50; default: unreachable("Invalid hardware generation"); } } /* GS_STATE::Constant URB Entry Read Length */ #define GFX5_GS_STATE_ConstantURBEntryReadLength_bits 6 #define GFX45_GS_STATE_ConstantURBEntryReadLength_bits 6 #define GFX4_GS_STATE_ConstantURBEntryReadLength_bits 6 static inline uint32_t ATTRIBUTE_PURE GS_STATE_ConstantURBEntryReadLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 6; case 45: return 6; case 40: return 6; default: unreachable("Invalid hardware generation"); } } #define GFX5_GS_STATE_ConstantURBEntryReadLength_start 121 #define GFX45_GS_STATE_ConstantURBEntryReadLength_start 121 #define GFX4_GS_STATE_ConstantURBEntryReadLength_start 121 static inline uint32_t ATTRIBUTE_PURE GS_STATE_ConstantURBEntryReadLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 121; case 45: return 121; case 40: return 121; default: unreachable("Invalid hardware generation"); } } /* GS_STATE::Constant URB Entry Read Offset */ #define GFX5_GS_STATE_ConstantURBEntryReadOffset_bits 6 #define GFX45_GS_STATE_ConstantURBEntryReadOffset_bits 6 #define GFX4_GS_STATE_ConstantURBEntryReadOffset_bits 6 static inline uint32_t ATTRIBUTE_PURE GS_STATE_ConstantURBEntryReadOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 6; case 45: return 6; case 40: return 6; default: unreachable("Invalid hardware generation"); } } #define GFX5_GS_STATE_ConstantURBEntryReadOffset_start 114 #define GFX45_GS_STATE_ConstantURBEntryReadOffset_start 114 #define GFX4_GS_STATE_ConstantURBEntryReadOffset_start 114 static inline uint32_t ATTRIBUTE_PURE GS_STATE_ConstantURBEntryReadOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 114; case 45: return 114; case 40: return 114; default: unreachable("Invalid hardware generation"); } } /* GS_STATE::Discard Adjacency */ #define GFX45_GS_STATE_DiscardAdjacency_bits 1 #define GFX4_GS_STATE_DiscardAdjacency_bits 1 static inline uint32_t ATTRIBUTE_PURE GS_STATE_DiscardAdjacency_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX45_GS_STATE_DiscardAdjacency_start 221 #define GFX4_GS_STATE_DiscardAdjacency_start 221 static inline uint32_t ATTRIBUTE_PURE GS_STATE_DiscardAdjacency_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 221; case 40: return 221; default: unreachable("Invalid hardware generation"); } } /* GS_STATE::Dispatch GRF Start Register For URB Data */ #define GFX5_GS_STATE_DispatchGRFStartRegisterForURBData_bits 4 #define GFX45_GS_STATE_DispatchGRFStartRegisterForURBData_bits 4 #define GFX4_GS_STATE_DispatchGRFStartRegisterForURBData_bits 4 static inline uint32_t ATTRIBUTE_PURE GS_STATE_DispatchGRFStartRegisterForURBData_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 4; case 45: return 4; case 40: return 4; default: unreachable("Invalid hardware generation"); } } #define GFX5_GS_STATE_DispatchGRFStartRegisterForURBData_start 96 #define GFX45_GS_STATE_DispatchGRFStartRegisterForURBData_start 96 #define GFX4_GS_STATE_DispatchGRFStartRegisterForURBData_start 96 static inline uint32_t ATTRIBUTE_PURE GS_STATE_DispatchGRFStartRegisterForURBData_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 96; case 45: return 96; case 40: return 96; default: unreachable("Invalid hardware generation"); } } /* GS_STATE::Floating Point Mode */ #define GFX5_GS_STATE_FloatingPointMode_bits 1 #define GFX45_GS_STATE_FloatingPointMode_bits 1 #define GFX4_GS_STATE_FloatingPointMode_bits 1 static inline uint32_t ATTRIBUTE_PURE GS_STATE_FloatingPointMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_GS_STATE_FloatingPointMode_start 48 #define GFX45_GS_STATE_FloatingPointMode_start 48 #define GFX4_GS_STATE_FloatingPointMode_start 48 static inline uint32_t ATTRIBUTE_PURE GS_STATE_FloatingPointMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 48; case 45: return 48; case 40: return 48; default: unreachable("Invalid hardware generation"); } } /* GS_STATE::GRF Register Count */ #define GFX5_GS_STATE_GRFRegisterCount_bits 3 #define GFX45_GS_STATE_GRFRegisterCount_bits 3 #define GFX4_GS_STATE_GRFRegisterCount_bits 3 static inline uint32_t ATTRIBUTE_PURE GS_STATE_GRFRegisterCount_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX5_GS_STATE_GRFRegisterCount_start 1 #define GFX45_GS_STATE_GRFRegisterCount_start 1 #define GFX4_GS_STATE_GRFRegisterCount_start 1 static inline uint32_t ATTRIBUTE_PURE GS_STATE_GRFRegisterCount_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } /* GS_STATE::GS Statistics Enable */ #define GFX5_GS_STATE_GSStatisticsEnable_bits 1 #define GFX45_GS_STATE_GSStatisticsEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE GS_STATE_GSStatisticsEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX5_GS_STATE_GSStatisticsEnable_start 138 #define GFX45_GS_STATE_GSStatisticsEnable_start 138 static inline uint32_t ATTRIBUTE_PURE GS_STATE_GSStatisticsEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 138; case 45: return 138; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GS_STATE::Illegal Opcode Exception Enable */ #define GFX5_GS_STATE_IllegalOpcodeExceptionEnable_bits 1 #define GFX45_GS_STATE_IllegalOpcodeExceptionEnable_bits 1 #define GFX4_GS_STATE_IllegalOpcodeExceptionEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE GS_STATE_IllegalOpcodeExceptionEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_GS_STATE_IllegalOpcodeExceptionEnable_start 45 #define GFX45_GS_STATE_IllegalOpcodeExceptionEnable_start 45 #define GFX4_GS_STATE_IllegalOpcodeExceptionEnable_start 45 static inline uint32_t ATTRIBUTE_PURE GS_STATE_IllegalOpcodeExceptionEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 45; case 45: return 45; case 40: return 45; default: unreachable("Invalid hardware generation"); } } /* GS_STATE::Kernel Start Pointer */ #define GFX5_GS_STATE_KernelStartPointer_bits 26 #define GFX45_GS_STATE_KernelStartPointer_bits 26 #define GFX4_GS_STATE_KernelStartPointer_bits 26 static inline uint32_t ATTRIBUTE_PURE GS_STATE_KernelStartPointer_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 26; case 45: return 26; case 40: return 26; default: unreachable("Invalid hardware generation"); } } #define GFX5_GS_STATE_KernelStartPointer_start 6 #define GFX45_GS_STATE_KernelStartPointer_start 6 #define GFX4_GS_STATE_KernelStartPointer_start 6 static inline uint32_t ATTRIBUTE_PURE GS_STATE_KernelStartPointer_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 6; case 45: return 6; case 40: return 6; default: unreachable("Invalid hardware generation"); } } /* GS_STATE::Mask Stack Exception Enable */ #define GFX5_GS_STATE_MaskStackExceptionEnable_bits 1 #define GFX45_GS_STATE_MaskStackExceptionEnable_bits 1 #define GFX4_GS_STATE_MaskStackExceptionEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE GS_STATE_MaskStackExceptionEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_GS_STATE_MaskStackExceptionEnable_start 43 #define GFX45_GS_STATE_MaskStackExceptionEnable_start 43 #define GFX4_GS_STATE_MaskStackExceptionEnable_start 43 static inline uint32_t ATTRIBUTE_PURE GS_STATE_MaskStackExceptionEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 43; case 45: return 43; case 40: return 43; default: unreachable("Invalid hardware generation"); } } /* GS_STATE::Maximum Number of Threads */ #define GFX5_GS_STATE_MaximumNumberofThreads_bits 6 #define GFX45_GS_STATE_MaximumNumberofThreads_bits 6 #define GFX4_GS_STATE_MaximumNumberofThreads_bits 6 static inline uint32_t ATTRIBUTE_PURE GS_STATE_MaximumNumberofThreads_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 6; case 45: return 6; case 40: return 6; default: unreachable("Invalid hardware generation"); } } #define GFX5_GS_STATE_MaximumNumberofThreads_start 153 #define GFX45_GS_STATE_MaximumNumberofThreads_start 153 #define GFX4_GS_STATE_MaximumNumberofThreads_start 153 static inline uint32_t ATTRIBUTE_PURE GS_STATE_MaximumNumberofThreads_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 153; case 45: return 153; case 40: return 153; default: unreachable("Invalid hardware generation"); } } /* GS_STATE::Maximum VPIndex */ #define GFX5_GS_STATE_MaximumVPIndex_bits 4 #define GFX45_GS_STATE_MaximumVPIndex_bits 4 #define GFX4_GS_STATE_MaximumVPIndex_bits 4 static inline uint32_t ATTRIBUTE_PURE GS_STATE_MaximumVPIndex_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 4; case 45: return 4; case 40: return 4; default: unreachable("Invalid hardware generation"); } } #define GFX5_GS_STATE_MaximumVPIndex_start 192 #define GFX45_GS_STATE_MaximumVPIndex_start 192 #define GFX4_GS_STATE_MaximumVPIndex_start 192 static inline uint32_t ATTRIBUTE_PURE GS_STATE_MaximumVPIndex_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 192; case 45: return 192; case 40: return 192; default: unreachable("Invalid hardware generation"); } } /* GS_STATE::Number of URB Entries */ #define GFX5_GS_STATE_NumberofURBEntries_bits 8 #define GFX45_GS_STATE_NumberofURBEntries_bits 8 #define GFX4_GS_STATE_NumberofURBEntries_bits 8 static inline uint32_t ATTRIBUTE_PURE GS_STATE_NumberofURBEntries_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 8; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } #define GFX5_GS_STATE_NumberofURBEntries_start 139 #define GFX45_GS_STATE_NumberofURBEntries_start 139 #define GFX4_GS_STATE_NumberofURBEntries_start 139 static inline uint32_t ATTRIBUTE_PURE GS_STATE_NumberofURBEntries_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 139; case 45: return 139; case 40: return 139; default: unreachable("Invalid hardware generation"); } } /* GS_STATE::Per-Thread Scratch Space */ #define GFX5_GS_STATE_PerThreadScratchSpace_bits 4 #define GFX45_GS_STATE_PerThreadScratchSpace_bits 4 #define GFX4_GS_STATE_PerThreadScratchSpace_bits 4 static inline uint32_t ATTRIBUTE_PURE GS_STATE_PerThreadScratchSpace_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 4; case 45: return 4; case 40: return 4; default: unreachable("Invalid hardware generation"); } } #define GFX5_GS_STATE_PerThreadScratchSpace_start 64 #define GFX45_GS_STATE_PerThreadScratchSpace_start 64 #define GFX4_GS_STATE_PerThreadScratchSpace_start 64 static inline uint32_t ATTRIBUTE_PURE GS_STATE_PerThreadScratchSpace_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 64; case 45: return 64; case 40: return 64; default: unreachable("Invalid hardware generation"); } } /* GS_STATE::Rendering Enable */ #define GFX45_GS_STATE_RenderingEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE GS_STATE_RenderingEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 1; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX45_GS_STATE_RenderingEnable_start 136 static inline uint32_t ATTRIBUTE_PURE GS_STATE_RenderingEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 136; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GS_STATE::Rendering Enabled */ #define GFX5_GS_STATE_RenderingEnabled_bits 1 static inline uint32_t ATTRIBUTE_PURE GS_STATE_RenderingEnabled_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX5_GS_STATE_RenderingEnabled_start 136 static inline uint32_t ATTRIBUTE_PURE GS_STATE_RenderingEnabled_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 136; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GS_STATE::Reorder Enable */ #define GFX5_GS_STATE_ReorderEnable_bits 1 #define GFX45_GS_STATE_ReorderEnable_bits 1 #define GFX4_GS_STATE_ReorderEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE GS_STATE_ReorderEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_GS_STATE_ReorderEnable_start 222 #define GFX45_GS_STATE_ReorderEnable_start 222 #define GFX4_GS_STATE_ReorderEnable_start 222 static inline uint32_t ATTRIBUTE_PURE GS_STATE_ReorderEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 222; case 45: return 222; case 40: return 222; default: unreachable("Invalid hardware generation"); } } /* GS_STATE::SO Statistics Enable */ #define GFX5_GS_STATE_SOStatisticsEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE GS_STATE_SOStatisticsEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX5_GS_STATE_SOStatisticsEnable_start 137 static inline uint32_t ATTRIBUTE_PURE GS_STATE_SOStatisticsEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 137; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GS_STATE::Sampler Count */ #define GFX5_GS_STATE_SamplerCount_bits 3 #define GFX45_GS_STATE_SamplerCount_bits 3 #define GFX4_GS_STATE_SamplerCount_bits 3 static inline uint32_t ATTRIBUTE_PURE GS_STATE_SamplerCount_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX5_GS_STATE_SamplerCount_start 160 #define GFX45_GS_STATE_SamplerCount_start 160 #define GFX4_GS_STATE_SamplerCount_start 160 static inline uint32_t ATTRIBUTE_PURE GS_STATE_SamplerCount_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 160; case 45: return 160; case 40: return 160; default: unreachable("Invalid hardware generation"); } } /* GS_STATE::Sampler State Pointer */ #define GFX5_GS_STATE_SamplerStatePointer_bits 27 #define GFX45_GS_STATE_SamplerStatePointer_bits 27 #define GFX4_GS_STATE_SamplerStatePointer_bits 27 static inline uint32_t ATTRIBUTE_PURE GS_STATE_SamplerStatePointer_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 27; case 45: return 27; case 40: return 27; default: unreachable("Invalid hardware generation"); } } #define GFX5_GS_STATE_SamplerStatePointer_start 165 #define GFX45_GS_STATE_SamplerStatePointer_start 165 #define GFX4_GS_STATE_SamplerStatePointer_start 165 static inline uint32_t ATTRIBUTE_PURE GS_STATE_SamplerStatePointer_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 165; case 45: return 165; case 40: return 165; default: unreachable("Invalid hardware generation"); } } /* GS_STATE::Scratch Space Base Pointer */ #define GFX5_GS_STATE_ScratchSpaceBasePointer_bits 22 #define GFX45_GS_STATE_ScratchSpaceBasePointer_bits 22 #define GFX4_GS_STATE_ScratchSpaceBasePointer_bits 22 static inline uint32_t ATTRIBUTE_PURE GS_STATE_ScratchSpaceBasePointer_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 22; case 45: return 22; case 40: return 22; default: unreachable("Invalid hardware generation"); } } #define GFX5_GS_STATE_ScratchSpaceBasePointer_start 74 #define GFX45_GS_STATE_ScratchSpaceBasePointer_start 74 #define GFX4_GS_STATE_ScratchSpaceBasePointer_start 74 static inline uint32_t ATTRIBUTE_PURE GS_STATE_ScratchSpaceBasePointer_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 74; case 45: return 74; case 40: return 74; default: unreachable("Invalid hardware generation"); } } /* GS_STATE::Single Program Flow */ #define GFX5_GS_STATE_SingleProgramFlow_bits 1 #define GFX45_GS_STATE_SingleProgramFlow_bits 1 #define GFX4_GS_STATE_SingleProgramFlow_bits 1 static inline uint32_t ATTRIBUTE_PURE GS_STATE_SingleProgramFlow_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_GS_STATE_SingleProgramFlow_start 63 #define GFX45_GS_STATE_SingleProgramFlow_start 63 #define GFX4_GS_STATE_SingleProgramFlow_start 63 static inline uint32_t ATTRIBUTE_PURE GS_STATE_SingleProgramFlow_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 63; case 45: return 63; case 40: return 63; default: unreachable("Invalid hardware generation"); } } /* GS_STATE::Software Exception Enable */ #define GFX5_GS_STATE_SoftwareExceptionEnable_bits 1 #define GFX45_GS_STATE_SoftwareExceptionEnable_bits 1 #define GFX4_GS_STATE_SoftwareExceptionEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE GS_STATE_SoftwareExceptionEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_GS_STATE_SoftwareExceptionEnable_start 39 #define GFX45_GS_STATE_SoftwareExceptionEnable_start 39 #define GFX4_GS_STATE_SoftwareExceptionEnable_start 39 static inline uint32_t ATTRIBUTE_PURE GS_STATE_SoftwareExceptionEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 39; case 45: return 39; case 40: return 39; default: unreachable("Invalid hardware generation"); } } /* GS_STATE::URB Entry Allocation Size */ #define GFX5_GS_STATE_URBEntryAllocationSize_bits 5 #define GFX45_GS_STATE_URBEntryAllocationSize_bits 5 #define GFX4_GS_STATE_URBEntryAllocationSize_bits 5 static inline uint32_t ATTRIBUTE_PURE GS_STATE_URBEntryAllocationSize_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 5; case 45: return 5; case 40: return 5; default: unreachable("Invalid hardware generation"); } } #define GFX5_GS_STATE_URBEntryAllocationSize_start 147 #define GFX45_GS_STATE_URBEntryAllocationSize_start 147 #define GFX4_GS_STATE_URBEntryAllocationSize_start 147 static inline uint32_t ATTRIBUTE_PURE GS_STATE_URBEntryAllocationSize_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 147; case 45: return 147; case 40: return 147; default: unreachable("Invalid hardware generation"); } } /* GS_STATE::Vertex URB Entry Read Length */ #define GFX5_GS_STATE_VertexURBEntryReadLength_bits 6 #define GFX45_GS_STATE_VertexURBEntryReadLength_bits 6 #define GFX4_GS_STATE_VertexURBEntryReadLength_bits 6 static inline uint32_t ATTRIBUTE_PURE GS_STATE_VertexURBEntryReadLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 6; case 45: return 6; case 40: return 6; default: unreachable("Invalid hardware generation"); } } #define GFX5_GS_STATE_VertexURBEntryReadLength_start 107 #define GFX45_GS_STATE_VertexURBEntryReadLength_start 107 #define GFX4_GS_STATE_VertexURBEntryReadLength_start 107 static inline uint32_t ATTRIBUTE_PURE GS_STATE_VertexURBEntryReadLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 107; case 45: return 107; case 40: return 107; default: unreachable("Invalid hardware generation"); } } /* GS_STATE::Vertex URB Entry Read Offset */ #define GFX5_GS_STATE_VertexURBEntryReadOffset_bits 6 #define GFX45_GS_STATE_VertexURBEntryReadOffset_bits 6 #define GFX4_GS_STATE_VertexURBEntryReadOffset_bits 6 static inline uint32_t ATTRIBUTE_PURE GS_STATE_VertexURBEntryReadOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 6; case 45: return 6; case 40: return 6; default: unreachable("Invalid hardware generation"); } } #define GFX5_GS_STATE_VertexURBEntryReadOffset_start 100 #define GFX45_GS_STATE_VertexURBEntryReadOffset_start 100 #define GFX4_GS_STATE_VertexURBEntryReadOffset_start 100 static inline uint32_t ATTRIBUTE_PURE GS_STATE_VertexURBEntryReadOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 100; case 45: return 100; case 40: return 100; default: unreachable("Invalid hardware generation"); } } /* GT_MODE */ #define GFX12_GT_MODE_length 1 #define GFX11_GT_MODE_length 1 #define GFX9_GT_MODE_length 1 static inline uint32_t ATTRIBUTE_PURE GT_MODE_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GT_MODE::Binding Table Alignment */ #define GFX12_GT_MODE_BindingTableAlignment_bits 1 #define GFX11_GT_MODE_BindingTableAlignment_bits 1 static inline uint32_t ATTRIBUTE_PURE GT_MODE_BindingTableAlignment_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_GT_MODE_BindingTableAlignment_start 10 #define GFX11_GT_MODE_BindingTableAlignment_start 10 static inline uint32_t ATTRIBUTE_PURE GT_MODE_BindingTableAlignment_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 10; case 110: return 10; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GT_MODE::Binding Table Alignment Mask */ #define GFX12_GT_MODE_BindingTableAlignmentMask_bits 1 #define GFX11_GT_MODE_BindingTableAlignmentMask_bits 1 static inline uint32_t ATTRIBUTE_PURE GT_MODE_BindingTableAlignmentMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_GT_MODE_BindingTableAlignmentMask_start 26 #define GFX11_GT_MODE_BindingTableAlignmentMask_start 26 static inline uint32_t ATTRIBUTE_PURE GT_MODE_BindingTableAlignmentMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 26; case 110: return 26; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GT_MODE::Slice Hashing */ #define GFX9_GT_MODE_SliceHashing_bits 2 static inline uint32_t ATTRIBUTE_PURE GT_MODE_SliceHashing_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 2; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_GT_MODE_SliceHashing_start 11 static inline uint32_t ATTRIBUTE_PURE GT_MODE_SliceHashing_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 11; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GT_MODE::Slice Hashing Mask */ #define GFX9_GT_MODE_SliceHashingMask_bits 2 static inline uint32_t ATTRIBUTE_PURE GT_MODE_SliceHashingMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 2; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_GT_MODE_SliceHashingMask_start 27 static inline uint32_t ATTRIBUTE_PURE GT_MODE_SliceHashingMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 27; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GT_MODE::Subslice Hashing */ #define GFX9_GT_MODE_SubsliceHashing_bits 2 static inline uint32_t ATTRIBUTE_PURE GT_MODE_SubsliceHashing_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 2; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_GT_MODE_SubsliceHashing_start 8 static inline uint32_t ATTRIBUTE_PURE GT_MODE_SubsliceHashing_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* GT_MODE::Subslice Hashing Mask */ #define GFX9_GT_MODE_SubsliceHashingMask_bits 2 static inline uint32_t ATTRIBUTE_PURE GT_MODE_SubsliceHashingMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 2; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_GT_MODE_SubsliceHashingMask_start 24 static inline uint32_t ATTRIBUTE_PURE GT_MODE_SubsliceHashingMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 24; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* HALF_SLICE_CHICKEN7 */ #define GFX125_HALF_SLICE_CHICKEN7_length 1 #define GFX12_HALF_SLICE_CHICKEN7_length 1 #define GFX11_HALF_SLICE_CHICKEN7_length 1 static inline uint32_t ATTRIBUTE_PURE HALF_SLICE_CHICKEN7_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* HALF_SLICE_CHICKEN7::Enabled Texel Offset Precision Fix */ #define GFX125_HALF_SLICE_CHICKEN7_EnabledTexelOffsetPrecisionFix_bits 1 #define GFX12_HALF_SLICE_CHICKEN7_EnabledTexelOffsetPrecisionFix_bits 1 #define GFX11_HALF_SLICE_CHICKEN7_EnabledTexelOffsetPrecisionFix_bits 1 static inline uint32_t ATTRIBUTE_PURE HALF_SLICE_CHICKEN7_EnabledTexelOffsetPrecisionFix_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_HALF_SLICE_CHICKEN7_EnabledTexelOffsetPrecisionFix_start 1 #define GFX12_HALF_SLICE_CHICKEN7_EnabledTexelOffsetPrecisionFix_start 1 #define GFX11_HALF_SLICE_CHICKEN7_EnabledTexelOffsetPrecisionFix_start 1 static inline uint32_t ATTRIBUTE_PURE HALF_SLICE_CHICKEN7_EnabledTexelOffsetPrecisionFix_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* HALF_SLICE_CHICKEN7::Enabled Texel Offset Precision Fix Mask */ #define GFX125_HALF_SLICE_CHICKEN7_EnabledTexelOffsetPrecisionFixMask_bits 1 #define GFX12_HALF_SLICE_CHICKEN7_EnabledTexelOffsetPrecisionFixMask_bits 1 #define GFX11_HALF_SLICE_CHICKEN7_EnabledTexelOffsetPrecisionFixMask_bits 1 static inline uint32_t ATTRIBUTE_PURE HALF_SLICE_CHICKEN7_EnabledTexelOffsetPrecisionFixMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_HALF_SLICE_CHICKEN7_EnabledTexelOffsetPrecisionFixMask_start 17 #define GFX12_HALF_SLICE_CHICKEN7_EnabledTexelOffsetPrecisionFixMask_start 17 #define GFX11_HALF_SLICE_CHICKEN7_EnabledTexelOffsetPrecisionFixMask_start 17 static inline uint32_t ATTRIBUTE_PURE HALF_SLICE_CHICKEN7_EnabledTexelOffsetPrecisionFixMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 17; case 120: return 17; case 110: return 17; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* HCP_PAK_INSERT_OBJECT_INDIRECT_PAYLOAD */ #define GFX125_HCP_PAK_INSERT_OBJECT_INDIRECT_PAYLOAD_length 4 #define GFX12_HCP_PAK_INSERT_OBJECT_INDIRECT_PAYLOAD_length 4 #define GFX11_HCP_PAK_INSERT_OBJECT_INDIRECT_PAYLOAD_length 4 #define GFX9_HCP_PAK_INSERT_OBJECT_INDIRECT_PAYLOAD_length 4 static inline uint32_t ATTRIBUTE_PURE HCP_PAK_INSERT_OBJECT_INDIRECT_PAYLOAD_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* HCP_PAK_INSERT_OBJECT_INDIRECT_PAYLOAD::Indirect Payload Base Address */ #define GFX125_HCP_PAK_INSERT_OBJECT_INDIRECT_PAYLOAD_IndirectPayloadBaseAddress_bits 64 #define GFX12_HCP_PAK_INSERT_OBJECT_INDIRECT_PAYLOAD_IndirectPayloadBaseAddress_bits 64 #define GFX11_HCP_PAK_INSERT_OBJECT_INDIRECT_PAYLOAD_IndirectPayloadBaseAddress_bits 64 #define GFX9_HCP_PAK_INSERT_OBJECT_INDIRECT_PAYLOAD_IndirectPayloadBaseAddress_bits 64 static inline uint32_t ATTRIBUTE_PURE HCP_PAK_INSERT_OBJECT_INDIRECT_PAYLOAD_IndirectPayloadBaseAddress_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 64; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_HCP_PAK_INSERT_OBJECT_INDIRECT_PAYLOAD_IndirectPayloadBaseAddress_start 32 #define GFX12_HCP_PAK_INSERT_OBJECT_INDIRECT_PAYLOAD_IndirectPayloadBaseAddress_start 32 #define GFX11_HCP_PAK_INSERT_OBJECT_INDIRECT_PAYLOAD_IndirectPayloadBaseAddress_start 32 #define GFX9_HCP_PAK_INSERT_OBJECT_INDIRECT_PAYLOAD_IndirectPayloadBaseAddress_start 32 static inline uint32_t ATTRIBUTE_PURE HCP_PAK_INSERT_OBJECT_INDIRECT_PAYLOAD_IndirectPayloadBaseAddress_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* HCP_PAK_INSERT_OBJECT_INDIRECT_PAYLOAD::Indirect Payload Base Address2 */ #define GFX125_HCP_PAK_INSERT_OBJECT_INDIRECT_PAYLOAD_IndirectPayloadBaseAddress2_bits 32 #define GFX12_HCP_PAK_INSERT_OBJECT_INDIRECT_PAYLOAD_IndirectPayloadBaseAddress2_bits 32 #define GFX11_HCP_PAK_INSERT_OBJECT_INDIRECT_PAYLOAD_IndirectPayloadBaseAddress2_bits 32 #define GFX9_HCP_PAK_INSERT_OBJECT_INDIRECT_PAYLOAD_IndirectPayloadBaseAddress2_bits 32 static inline uint32_t ATTRIBUTE_PURE HCP_PAK_INSERT_OBJECT_INDIRECT_PAYLOAD_IndirectPayloadBaseAddress2_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_HCP_PAK_INSERT_OBJECT_INDIRECT_PAYLOAD_IndirectPayloadBaseAddress2_start 96 #define GFX12_HCP_PAK_INSERT_OBJECT_INDIRECT_PAYLOAD_IndirectPayloadBaseAddress2_start 96 #define GFX11_HCP_PAK_INSERT_OBJECT_INDIRECT_PAYLOAD_IndirectPayloadBaseAddress2_start 96 #define GFX9_HCP_PAK_INSERT_OBJECT_INDIRECT_PAYLOAD_IndirectPayloadBaseAddress2_start 96 static inline uint32_t ATTRIBUTE_PURE HCP_PAK_INSERT_OBJECT_INDIRECT_PAYLOAD_IndirectPayloadBaseAddress2_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 96; case 120: return 96; case 110: return 96; case 90: return 96; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* HCP_PAK_INSERT_OBJECT_INDIRECT_PAYLOAD::Indirect Payload Data Size in bits */ #define GFX125_HCP_PAK_INSERT_OBJECT_INDIRECT_PAYLOAD_IndirectPayloadDataSizeinbits_bits 32 #define GFX12_HCP_PAK_INSERT_OBJECT_INDIRECT_PAYLOAD_IndirectPayloadDataSizeinbits_bits 32 #define GFX11_HCP_PAK_INSERT_OBJECT_INDIRECT_PAYLOAD_IndirectPayloadDataSizeinbits_bits 32 #define GFX9_HCP_PAK_INSERT_OBJECT_INDIRECT_PAYLOAD_IndirectPayloadDataSizeinbits_bits 32 static inline uint32_t ATTRIBUTE_PURE HCP_PAK_INSERT_OBJECT_INDIRECT_PAYLOAD_IndirectPayloadDataSizeinbits_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_HCP_PAK_INSERT_OBJECT_INDIRECT_PAYLOAD_IndirectPayloadDataSizeinbits_start 0 #define GFX12_HCP_PAK_INSERT_OBJECT_INDIRECT_PAYLOAD_IndirectPayloadDataSizeinbits_start 0 #define GFX11_HCP_PAK_INSERT_OBJECT_INDIRECT_PAYLOAD_IndirectPayloadDataSizeinbits_start 0 #define GFX9_HCP_PAK_INSERT_OBJECT_INDIRECT_PAYLOAD_IndirectPayloadDataSizeinbits_start 0 static inline uint32_t ATTRIBUTE_PURE HCP_PAK_INSERT_OBJECT_INDIRECT_PAYLOAD_IndirectPayloadDataSizeinbits_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* HCP_REF_LIST_ENTRY */ #define GFX125_HCP_REF_LIST_ENTRY_length 1 #define GFX12_HCP_REF_LIST_ENTRY_length 1 #define GFX11_HCP_REF_LIST_ENTRY_length 1 #define GFX9_HCP_REF_LIST_ENTRY_length 1 static inline uint32_t ATTRIBUTE_PURE HCP_REF_LIST_ENTRY_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* HCP_REF_LIST_ENTRY::Chroma Weighted Prediction */ #define GFX125_HCP_REF_LIST_ENTRY_ChromaWeightedPrediction_bits 1 #define GFX12_HCP_REF_LIST_ENTRY_ChromaWeightedPrediction_bits 1 #define GFX11_HCP_REF_LIST_ENTRY_ChromaWeightedPrediction_bits 1 #define GFX9_HCP_REF_LIST_ENTRY_ChromaWeightedPrediction_bits 1 static inline uint32_t ATTRIBUTE_PURE HCP_REF_LIST_ENTRY_ChromaWeightedPrediction_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_HCP_REF_LIST_ENTRY_ChromaWeightedPrediction_start 11 #define GFX12_HCP_REF_LIST_ENTRY_ChromaWeightedPrediction_start 11 #define GFX11_HCP_REF_LIST_ENTRY_ChromaWeightedPrediction_start 11 #define GFX9_HCP_REF_LIST_ENTRY_ChromaWeightedPrediction_start 11 static inline uint32_t ATTRIBUTE_PURE HCP_REF_LIST_ENTRY_ChromaWeightedPrediction_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 11; case 120: return 11; case 110: return 11; case 90: return 11; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* HCP_REF_LIST_ENTRY::Field Pic */ #define GFX125_HCP_REF_LIST_ENTRY_FieldPic_bits 1 #define GFX12_HCP_REF_LIST_ENTRY_FieldPic_bits 1 #define GFX11_HCP_REF_LIST_ENTRY_FieldPic_bits 1 #define GFX9_HCP_REF_LIST_ENTRY_FieldPic_bits 1 static inline uint32_t ATTRIBUTE_PURE HCP_REF_LIST_ENTRY_FieldPic_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_HCP_REF_LIST_ENTRY_FieldPic_start 14 #define GFX12_HCP_REF_LIST_ENTRY_FieldPic_start 14 #define GFX11_HCP_REF_LIST_ENTRY_FieldPic_start 14 #define GFX9_HCP_REF_LIST_ENTRY_FieldPic_start 14 static inline uint32_t ATTRIBUTE_PURE HCP_REF_LIST_ENTRY_FieldPic_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 14; case 120: return 14; case 110: return 14; case 90: return 14; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* HCP_REF_LIST_ENTRY::List Entry */ #define GFX125_HCP_REF_LIST_ENTRY_ListEntry_bits 3 #define GFX12_HCP_REF_LIST_ENTRY_ListEntry_bits 3 #define GFX11_HCP_REF_LIST_ENTRY_ListEntry_bits 3 #define GFX9_HCP_REF_LIST_ENTRY_ListEntry_bits 3 static inline uint32_t ATTRIBUTE_PURE HCP_REF_LIST_ENTRY_ListEntry_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_HCP_REF_LIST_ENTRY_ListEntry_start 8 #define GFX12_HCP_REF_LIST_ENTRY_ListEntry_start 8 #define GFX11_HCP_REF_LIST_ENTRY_ListEntry_start 8 #define GFX9_HCP_REF_LIST_ENTRY_ListEntry_start 8 static inline uint32_t ATTRIBUTE_PURE HCP_REF_LIST_ENTRY_ListEntry_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* HCP_REF_LIST_ENTRY::Long Term Reference */ #define GFX125_HCP_REF_LIST_ENTRY_LongTermReference_bits 1 #define GFX12_HCP_REF_LIST_ENTRY_LongTermReference_bits 1 #define GFX11_HCP_REF_LIST_ENTRY_LongTermReference_bits 1 #define GFX9_HCP_REF_LIST_ENTRY_LongTermReference_bits 1 static inline uint32_t ATTRIBUTE_PURE HCP_REF_LIST_ENTRY_LongTermReference_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_HCP_REF_LIST_ENTRY_LongTermReference_start 13 #define GFX12_HCP_REF_LIST_ENTRY_LongTermReference_start 13 #define GFX11_HCP_REF_LIST_ENTRY_LongTermReference_start 13 #define GFX9_HCP_REF_LIST_ENTRY_LongTermReference_start 13 static inline uint32_t ATTRIBUTE_PURE HCP_REF_LIST_ENTRY_LongTermReference_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 13; case 120: return 13; case 110: return 13; case 90: return 13; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* HCP_REF_LIST_ENTRY::Luma Weighted Prediction */ #define GFX125_HCP_REF_LIST_ENTRY_LumaWeightedPrediction_bits 1 #define GFX12_HCP_REF_LIST_ENTRY_LumaWeightedPrediction_bits 1 #define GFX11_HCP_REF_LIST_ENTRY_LumaWeightedPrediction_bits 1 #define GFX9_HCP_REF_LIST_ENTRY_LumaWeightedPrediction_bits 1 static inline uint32_t ATTRIBUTE_PURE HCP_REF_LIST_ENTRY_LumaWeightedPrediction_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_HCP_REF_LIST_ENTRY_LumaWeightedPrediction_start 12 #define GFX12_HCP_REF_LIST_ENTRY_LumaWeightedPrediction_start 12 #define GFX11_HCP_REF_LIST_ENTRY_LumaWeightedPrediction_start 12 #define GFX9_HCP_REF_LIST_ENTRY_LumaWeightedPrediction_start 12 static inline uint32_t ATTRIBUTE_PURE HCP_REF_LIST_ENTRY_LumaWeightedPrediction_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 12; case 120: return 12; case 110: return 12; case 90: return 12; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* HCP_REF_LIST_ENTRY::Reference Picture tb Value */ #define GFX125_HCP_REF_LIST_ENTRY_ReferencePicturetbValue_bits 8 #define GFX12_HCP_REF_LIST_ENTRY_ReferencePicturetbValue_bits 8 #define GFX11_HCP_REF_LIST_ENTRY_ReferencePicturetbValue_bits 8 #define GFX9_HCP_REF_LIST_ENTRY_ReferencePicturetbValue_bits 8 static inline uint32_t ATTRIBUTE_PURE HCP_REF_LIST_ENTRY_ReferencePicturetbValue_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_HCP_REF_LIST_ENTRY_ReferencePicturetbValue_start 0 #define GFX12_HCP_REF_LIST_ENTRY_ReferencePicturetbValue_start 0 #define GFX11_HCP_REF_LIST_ENTRY_ReferencePicturetbValue_start 0 #define GFX9_HCP_REF_LIST_ENTRY_ReferencePicturetbValue_start 0 static inline uint32_t ATTRIBUTE_PURE HCP_REF_LIST_ENTRY_ReferencePicturetbValue_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* HCP_REF_LIST_ENTRY::Top Field */ #define GFX125_HCP_REF_LIST_ENTRY_TopField_bits 1 #define GFX12_HCP_REF_LIST_ENTRY_TopField_bits 1 #define GFX11_HCP_REF_LIST_ENTRY_TopField_bits 1 #define GFX9_HCP_REF_LIST_ENTRY_TopField_bits 1 static inline uint32_t ATTRIBUTE_PURE HCP_REF_LIST_ENTRY_TopField_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_HCP_REF_LIST_ENTRY_TopField_start 15 #define GFX12_HCP_REF_LIST_ENTRY_TopField_start 15 #define GFX11_HCP_REF_LIST_ENTRY_TopField_start 15 #define GFX9_HCP_REF_LIST_ENTRY_TopField_start 15 static inline uint32_t ATTRIBUTE_PURE HCP_REF_LIST_ENTRY_TopField_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 15; case 120: return 15; case 110: return 15; case 90: return 15; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* HCP_TILE_POSITION_IN_CTB */ #define GFX125_HCP_TILE_POSITION_IN_CTB_length 1 #define GFX12_HCP_TILE_POSITION_IN_CTB_length 1 #define GFX11_HCP_TILE_POSITION_IN_CTB_length 1 #define GFX9_HCP_TILE_POSITION_IN_CTB_length 1 static inline uint32_t ATTRIBUTE_PURE HCP_TILE_POSITION_IN_CTB_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* HCP_TILE_POSITION_IN_CTB::CtbPos0+i */ #define GFX125_HCP_TILE_POSITION_IN_CTB_CtbPos0i_bits 8 #define GFX12_HCP_TILE_POSITION_IN_CTB_CtbPos0i_bits 8 #define GFX11_HCP_TILE_POSITION_IN_CTB_CtbPos0i_bits 8 #define GFX9_HCP_TILE_POSITION_IN_CTB_CtbPos0i_bits 8 static inline uint32_t ATTRIBUTE_PURE HCP_TILE_POSITION_IN_CTB_CtbPos0i_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_HCP_TILE_POSITION_IN_CTB_CtbPos0i_start 0 #define GFX12_HCP_TILE_POSITION_IN_CTB_CtbPos0i_start 0 #define GFX11_HCP_TILE_POSITION_IN_CTB_CtbPos0i_start 0 #define GFX9_HCP_TILE_POSITION_IN_CTB_CtbPos0i_start 0 static inline uint32_t ATTRIBUTE_PURE HCP_TILE_POSITION_IN_CTB_CtbPos0i_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* HCP_TILE_POSITION_IN_CTB::CtbPos1+i */ #define GFX125_HCP_TILE_POSITION_IN_CTB_CtbPos1i_bits 8 #define GFX12_HCP_TILE_POSITION_IN_CTB_CtbPos1i_bits 8 #define GFX11_HCP_TILE_POSITION_IN_CTB_CtbPos1i_bits 8 #define GFX9_HCP_TILE_POSITION_IN_CTB_CtbPos1i_bits 8 static inline uint32_t ATTRIBUTE_PURE HCP_TILE_POSITION_IN_CTB_CtbPos1i_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_HCP_TILE_POSITION_IN_CTB_CtbPos1i_start 8 #define GFX12_HCP_TILE_POSITION_IN_CTB_CtbPos1i_start 8 #define GFX11_HCP_TILE_POSITION_IN_CTB_CtbPos1i_start 8 #define GFX9_HCP_TILE_POSITION_IN_CTB_CtbPos1i_start 8 static inline uint32_t ATTRIBUTE_PURE HCP_TILE_POSITION_IN_CTB_CtbPos1i_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* HCP_TILE_POSITION_IN_CTB::CtbPos2+i */ #define GFX125_HCP_TILE_POSITION_IN_CTB_CtbPos2i_bits 8 #define GFX12_HCP_TILE_POSITION_IN_CTB_CtbPos2i_bits 8 #define GFX11_HCP_TILE_POSITION_IN_CTB_CtbPos2i_bits 8 #define GFX9_HCP_TILE_POSITION_IN_CTB_CtbPos2i_bits 8 static inline uint32_t ATTRIBUTE_PURE HCP_TILE_POSITION_IN_CTB_CtbPos2i_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_HCP_TILE_POSITION_IN_CTB_CtbPos2i_start 16 #define GFX12_HCP_TILE_POSITION_IN_CTB_CtbPos2i_start 16 #define GFX11_HCP_TILE_POSITION_IN_CTB_CtbPos2i_start 16 #define GFX9_HCP_TILE_POSITION_IN_CTB_CtbPos2i_start 16 static inline uint32_t ATTRIBUTE_PURE HCP_TILE_POSITION_IN_CTB_CtbPos2i_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* HCP_TILE_POSITION_IN_CTB::CtbPos3+i */ #define GFX125_HCP_TILE_POSITION_IN_CTB_CtbPos3i_bits 8 #define GFX12_HCP_TILE_POSITION_IN_CTB_CtbPos3i_bits 8 #define GFX11_HCP_TILE_POSITION_IN_CTB_CtbPos3i_bits 8 #define GFX9_HCP_TILE_POSITION_IN_CTB_CtbPos3i_bits 8 static inline uint32_t ATTRIBUTE_PURE HCP_TILE_POSITION_IN_CTB_CtbPos3i_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_HCP_TILE_POSITION_IN_CTB_CtbPos3i_start 24 #define GFX12_HCP_TILE_POSITION_IN_CTB_CtbPos3i_start 24 #define GFX11_HCP_TILE_POSITION_IN_CTB_CtbPos3i_start 24 #define GFX9_HCP_TILE_POSITION_IN_CTB_CtbPos3i_start 24 static inline uint32_t ATTRIBUTE_PURE HCP_TILE_POSITION_IN_CTB_CtbPos3i_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* HCP_TILE_POSITION_IN_CTB_MSB */ #define GFX125_HCP_TILE_POSITION_IN_CTB_MSB_length 2 #define GFX12_HCP_TILE_POSITION_IN_CTB_MSB_length 2 #define GFX11_HCP_TILE_POSITION_IN_CTB_MSB_length 2 static inline uint32_t ATTRIBUTE_PURE HCP_TILE_POSITION_IN_CTB_MSB_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* HCP_WEIGHTOFFSET_CHROMA_ENTRY */ #define GFX125_HCP_WEIGHTOFFSET_CHROMA_ENTRY_length 1 #define GFX12_HCP_WEIGHTOFFSET_CHROMA_ENTRY_length 1 #define GFX11_HCP_WEIGHTOFFSET_CHROMA_ENTRY_length 1 #define GFX9_HCP_WEIGHTOFFSET_CHROMA_ENTRY_length 1 static inline uint32_t ATTRIBUTE_PURE HCP_WEIGHTOFFSET_CHROMA_ENTRY_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* HCP_WEIGHTOFFSET_CHROMA_ENTRY::Chroma Offset LX[0] */ #define GFX125_HCP_WEIGHTOFFSET_CHROMA_ENTRY_ChromaOffsetLX0_bits 8 #define GFX12_HCP_WEIGHTOFFSET_CHROMA_ENTRY_ChromaOffsetLX0_bits 8 #define GFX11_HCP_WEIGHTOFFSET_CHROMA_ENTRY_ChromaOffsetLX0_bits 8 #define GFX9_HCP_WEIGHTOFFSET_CHROMA_ENTRY_ChromaOffsetLX0_bits 8 static inline uint32_t ATTRIBUTE_PURE HCP_WEIGHTOFFSET_CHROMA_ENTRY_ChromaOffsetLX0_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_HCP_WEIGHTOFFSET_CHROMA_ENTRY_ChromaOffsetLX0_start 8 #define GFX12_HCP_WEIGHTOFFSET_CHROMA_ENTRY_ChromaOffsetLX0_start 8 #define GFX11_HCP_WEIGHTOFFSET_CHROMA_ENTRY_ChromaOffsetLX0_start 8 #define GFX9_HCP_WEIGHTOFFSET_CHROMA_ENTRY_ChromaOffsetLX0_start 8 static inline uint32_t ATTRIBUTE_PURE HCP_WEIGHTOFFSET_CHROMA_ENTRY_ChromaOffsetLX0_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* HCP_WEIGHTOFFSET_CHROMA_ENTRY::Chroma Offset LX[1] */ #define GFX125_HCP_WEIGHTOFFSET_CHROMA_ENTRY_ChromaOffsetLX1_bits 8 #define GFX12_HCP_WEIGHTOFFSET_CHROMA_ENTRY_ChromaOffsetLX1_bits 8 #define GFX11_HCP_WEIGHTOFFSET_CHROMA_ENTRY_ChromaOffsetLX1_bits 8 #define GFX9_HCP_WEIGHTOFFSET_CHROMA_ENTRY_ChromaOffsetLX1_bits 8 static inline uint32_t ATTRIBUTE_PURE HCP_WEIGHTOFFSET_CHROMA_ENTRY_ChromaOffsetLX1_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_HCP_WEIGHTOFFSET_CHROMA_ENTRY_ChromaOffsetLX1_start 24 #define GFX12_HCP_WEIGHTOFFSET_CHROMA_ENTRY_ChromaOffsetLX1_start 24 #define GFX11_HCP_WEIGHTOFFSET_CHROMA_ENTRY_ChromaOffsetLX1_start 24 #define GFX9_HCP_WEIGHTOFFSET_CHROMA_ENTRY_ChromaOffsetLX1_start 24 static inline uint32_t ATTRIBUTE_PURE HCP_WEIGHTOFFSET_CHROMA_ENTRY_ChromaOffsetLX1_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* HCP_WEIGHTOFFSET_CHROMA_ENTRY::Delta Chroma Weight LX[0] */ #define GFX125_HCP_WEIGHTOFFSET_CHROMA_ENTRY_DeltaChromaWeightLX0_bits 8 #define GFX12_HCP_WEIGHTOFFSET_CHROMA_ENTRY_DeltaChromaWeightLX0_bits 8 #define GFX11_HCP_WEIGHTOFFSET_CHROMA_ENTRY_DeltaChromaWeightLX0_bits 8 #define GFX9_HCP_WEIGHTOFFSET_CHROMA_ENTRY_DeltaChromaWeightLX0_bits 8 static inline uint32_t ATTRIBUTE_PURE HCP_WEIGHTOFFSET_CHROMA_ENTRY_DeltaChromaWeightLX0_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_HCP_WEIGHTOFFSET_CHROMA_ENTRY_DeltaChromaWeightLX0_start 0 #define GFX12_HCP_WEIGHTOFFSET_CHROMA_ENTRY_DeltaChromaWeightLX0_start 0 #define GFX11_HCP_WEIGHTOFFSET_CHROMA_ENTRY_DeltaChromaWeightLX0_start 0 #define GFX9_HCP_WEIGHTOFFSET_CHROMA_ENTRY_DeltaChromaWeightLX0_start 0 static inline uint32_t ATTRIBUTE_PURE HCP_WEIGHTOFFSET_CHROMA_ENTRY_DeltaChromaWeightLX0_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* HCP_WEIGHTOFFSET_CHROMA_ENTRY::Delta Chroma Weight LX[1] */ #define GFX125_HCP_WEIGHTOFFSET_CHROMA_ENTRY_DeltaChromaWeightLX1_bits 8 #define GFX12_HCP_WEIGHTOFFSET_CHROMA_ENTRY_DeltaChromaWeightLX1_bits 8 #define GFX11_HCP_WEIGHTOFFSET_CHROMA_ENTRY_DeltaChromaWeightLX1_bits 8 #define GFX9_HCP_WEIGHTOFFSET_CHROMA_ENTRY_DeltaChromaWeightLX1_bits 8 static inline uint32_t ATTRIBUTE_PURE HCP_WEIGHTOFFSET_CHROMA_ENTRY_DeltaChromaWeightLX1_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_HCP_WEIGHTOFFSET_CHROMA_ENTRY_DeltaChromaWeightLX1_start 16 #define GFX12_HCP_WEIGHTOFFSET_CHROMA_ENTRY_DeltaChromaWeightLX1_start 16 #define GFX11_HCP_WEIGHTOFFSET_CHROMA_ENTRY_DeltaChromaWeightLX1_start 16 #define GFX9_HCP_WEIGHTOFFSET_CHROMA_ENTRY_DeltaChromaWeightLX1_start 16 static inline uint32_t ATTRIBUTE_PURE HCP_WEIGHTOFFSET_CHROMA_ENTRY_DeltaChromaWeightLX1_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* HCP_WEIGHTOFFSET_CHROMA_EXT_ENTRY */ #define GFX125_HCP_WEIGHTOFFSET_CHROMA_EXT_ENTRY_length 1 #define GFX12_HCP_WEIGHTOFFSET_CHROMA_EXT_ENTRY_length 1 #define GFX11_HCP_WEIGHTOFFSET_CHROMA_EXT_ENTRY_length 1 static inline uint32_t ATTRIBUTE_PURE HCP_WEIGHTOFFSET_CHROMA_EXT_ENTRY_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* HCP_WEIGHTOFFSET_CHROMA_EXT_ENTRY::Chroma Offset LX[0] MSByte [i] */ #define GFX125_HCP_WEIGHTOFFSET_CHROMA_EXT_ENTRY_ChromaOffsetLX0MSBytei_bits 8 #define GFX12_HCP_WEIGHTOFFSET_CHROMA_EXT_ENTRY_ChromaOffsetLX0MSBytei_bits 8 #define GFX11_HCP_WEIGHTOFFSET_CHROMA_EXT_ENTRY_ChromaOffsetLX0MSBytei_bits 8 static inline uint32_t ATTRIBUTE_PURE HCP_WEIGHTOFFSET_CHROMA_EXT_ENTRY_ChromaOffsetLX0MSBytei_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_HCP_WEIGHTOFFSET_CHROMA_EXT_ENTRY_ChromaOffsetLX0MSBytei_start 0 #define GFX12_HCP_WEIGHTOFFSET_CHROMA_EXT_ENTRY_ChromaOffsetLX0MSBytei_start 0 #define GFX11_HCP_WEIGHTOFFSET_CHROMA_EXT_ENTRY_ChromaOffsetLX0MSBytei_start 0 static inline uint32_t ATTRIBUTE_PURE HCP_WEIGHTOFFSET_CHROMA_EXT_ENTRY_ChromaOffsetLX0MSBytei_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* HCP_WEIGHTOFFSET_CHROMA_EXT_ENTRY::Chroma Offset LX[0] MSByte [i+1] */ #define GFX125_HCP_WEIGHTOFFSET_CHROMA_EXT_ENTRY_ChromaOffsetLX0MSBytei1_bits 8 #define GFX12_HCP_WEIGHTOFFSET_CHROMA_EXT_ENTRY_ChromaOffsetLX0MSBytei1_bits 8 #define GFX11_HCP_WEIGHTOFFSET_CHROMA_EXT_ENTRY_ChromaOffsetLX0MSBytei1_bits 8 static inline uint32_t ATTRIBUTE_PURE HCP_WEIGHTOFFSET_CHROMA_EXT_ENTRY_ChromaOffsetLX0MSBytei1_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_HCP_WEIGHTOFFSET_CHROMA_EXT_ENTRY_ChromaOffsetLX0MSBytei1_start 8 #define GFX12_HCP_WEIGHTOFFSET_CHROMA_EXT_ENTRY_ChromaOffsetLX0MSBytei1_start 8 #define GFX11_HCP_WEIGHTOFFSET_CHROMA_EXT_ENTRY_ChromaOffsetLX0MSBytei1_start 8 static inline uint32_t ATTRIBUTE_PURE HCP_WEIGHTOFFSET_CHROMA_EXT_ENTRY_ChromaOffsetLX0MSBytei1_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* HCP_WEIGHTOFFSET_CHROMA_EXT_ENTRY::Chroma Offset LX[1] MSByte [i] */ #define GFX125_HCP_WEIGHTOFFSET_CHROMA_EXT_ENTRY_ChromaOffsetLX1MSBytei_bits 8 #define GFX12_HCP_WEIGHTOFFSET_CHROMA_EXT_ENTRY_ChromaOffsetLX1MSBytei_bits 8 #define GFX11_HCP_WEIGHTOFFSET_CHROMA_EXT_ENTRY_ChromaOffsetLX1MSBytei_bits 8 static inline uint32_t ATTRIBUTE_PURE HCP_WEIGHTOFFSET_CHROMA_EXT_ENTRY_ChromaOffsetLX1MSBytei_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_HCP_WEIGHTOFFSET_CHROMA_EXT_ENTRY_ChromaOffsetLX1MSBytei_start 16 #define GFX12_HCP_WEIGHTOFFSET_CHROMA_EXT_ENTRY_ChromaOffsetLX1MSBytei_start 16 #define GFX11_HCP_WEIGHTOFFSET_CHROMA_EXT_ENTRY_ChromaOffsetLX1MSBytei_start 16 static inline uint32_t ATTRIBUTE_PURE HCP_WEIGHTOFFSET_CHROMA_EXT_ENTRY_ChromaOffsetLX1MSBytei_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* HCP_WEIGHTOFFSET_CHROMA_EXT_ENTRY::Chroma Offset LX[1] MSByte [i+1] */ #define GFX125_HCP_WEIGHTOFFSET_CHROMA_EXT_ENTRY_ChromaOffsetLX1MSBytei1_bits 8 #define GFX12_HCP_WEIGHTOFFSET_CHROMA_EXT_ENTRY_ChromaOffsetLX1MSBytei1_bits 8 #define GFX11_HCP_WEIGHTOFFSET_CHROMA_EXT_ENTRY_ChromaOffsetLX1MSBytei1_bits 8 static inline uint32_t ATTRIBUTE_PURE HCP_WEIGHTOFFSET_CHROMA_EXT_ENTRY_ChromaOffsetLX1MSBytei1_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_HCP_WEIGHTOFFSET_CHROMA_EXT_ENTRY_ChromaOffsetLX1MSBytei1_start 24 #define GFX12_HCP_WEIGHTOFFSET_CHROMA_EXT_ENTRY_ChromaOffsetLX1MSBytei1_start 24 #define GFX11_HCP_WEIGHTOFFSET_CHROMA_EXT_ENTRY_ChromaOffsetLX1MSBytei1_start 24 static inline uint32_t ATTRIBUTE_PURE HCP_WEIGHTOFFSET_CHROMA_EXT_ENTRY_ChromaOffsetLX1MSBytei1_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* HCP_WEIGHTOFFSET_LUMA_ENTRY */ #define GFX125_HCP_WEIGHTOFFSET_LUMA_ENTRY_length 1 #define GFX12_HCP_WEIGHTOFFSET_LUMA_ENTRY_length 1 #define GFX11_HCP_WEIGHTOFFSET_LUMA_ENTRY_length 1 #define GFX9_HCP_WEIGHTOFFSET_LUMA_ENTRY_length 1 static inline uint32_t ATTRIBUTE_PURE HCP_WEIGHTOFFSET_LUMA_ENTRY_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* HCP_WEIGHTOFFSET_LUMA_ENTRY::Delta Luma Weight LX */ #define GFX125_HCP_WEIGHTOFFSET_LUMA_ENTRY_DeltaLumaWeightLX_bits 8 #define GFX12_HCP_WEIGHTOFFSET_LUMA_ENTRY_DeltaLumaWeightLX_bits 8 #define GFX11_HCP_WEIGHTOFFSET_LUMA_ENTRY_DeltaLumaWeightLX_bits 8 #define GFX9_HCP_WEIGHTOFFSET_LUMA_ENTRY_DeltaLumaWeightLX_bits 8 static inline uint32_t ATTRIBUTE_PURE HCP_WEIGHTOFFSET_LUMA_ENTRY_DeltaLumaWeightLX_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_HCP_WEIGHTOFFSET_LUMA_ENTRY_DeltaLumaWeightLX_start 0 #define GFX12_HCP_WEIGHTOFFSET_LUMA_ENTRY_DeltaLumaWeightLX_start 0 #define GFX11_HCP_WEIGHTOFFSET_LUMA_ENTRY_DeltaLumaWeightLX_start 0 #define GFX9_HCP_WEIGHTOFFSET_LUMA_ENTRY_DeltaLumaWeightLX_start 0 static inline uint32_t ATTRIBUTE_PURE HCP_WEIGHTOFFSET_LUMA_ENTRY_DeltaLumaWeightLX_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* HCP_WEIGHTOFFSET_LUMA_ENTRY::Luma Offset LX */ #define GFX125_HCP_WEIGHTOFFSET_LUMA_ENTRY_LumaOffsetLX_bits 8 #define GFX12_HCP_WEIGHTOFFSET_LUMA_ENTRY_LumaOffsetLX_bits 8 #define GFX11_HCP_WEIGHTOFFSET_LUMA_ENTRY_LumaOffsetLX_bits 8 #define GFX9_HCP_WEIGHTOFFSET_LUMA_ENTRY_LumaOffsetLX_bits 8 static inline uint32_t ATTRIBUTE_PURE HCP_WEIGHTOFFSET_LUMA_ENTRY_LumaOffsetLX_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_HCP_WEIGHTOFFSET_LUMA_ENTRY_LumaOffsetLX_start 8 #define GFX12_HCP_WEIGHTOFFSET_LUMA_ENTRY_LumaOffsetLX_start 8 #define GFX11_HCP_WEIGHTOFFSET_LUMA_ENTRY_LumaOffsetLX_start 8 #define GFX9_HCP_WEIGHTOFFSET_LUMA_ENTRY_LumaOffsetLX_start 8 static inline uint32_t ATTRIBUTE_PURE HCP_WEIGHTOFFSET_LUMA_ENTRY_LumaOffsetLX_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* HCP_WEIGHTOFFSET_LUMA_ENTRY::Luma Offset LX MSByte */ #define GFX125_HCP_WEIGHTOFFSET_LUMA_ENTRY_LumaOffsetLXMSByte_bits 8 #define GFX12_HCP_WEIGHTOFFSET_LUMA_ENTRY_LumaOffsetLXMSByte_bits 8 #define GFX11_HCP_WEIGHTOFFSET_LUMA_ENTRY_LumaOffsetLXMSByte_bits 8 static inline uint32_t ATTRIBUTE_PURE HCP_WEIGHTOFFSET_LUMA_ENTRY_LumaOffsetLXMSByte_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_HCP_WEIGHTOFFSET_LUMA_ENTRY_LumaOffsetLXMSByte_start 24 #define GFX12_HCP_WEIGHTOFFSET_LUMA_ENTRY_LumaOffsetLXMSByte_start 24 #define GFX11_HCP_WEIGHTOFFSET_LUMA_ENTRY_LumaOffsetLXMSByte_start 24 static inline uint32_t ATTRIBUTE_PURE HCP_WEIGHTOFFSET_LUMA_ENTRY_LumaOffsetLXMSByte_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* HEVC_ARBITRATION_PRIORITY */ #define GFX125_HEVC_ARBITRATION_PRIORITY_length 1 #define GFX12_HEVC_ARBITRATION_PRIORITY_length 1 #define GFX11_HEVC_ARBITRATION_PRIORITY_length 1 #define GFX9_HEVC_ARBITRATION_PRIORITY_length 1 static inline uint32_t ATTRIBUTE_PURE HEVC_ARBITRATION_PRIORITY_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* HEVC_ARBITRATION_PRIORITY::Priority */ #define GFX125_HEVC_ARBITRATION_PRIORITY_Priority_bits 2 #define GFX12_HEVC_ARBITRATION_PRIORITY_Priority_bits 2 #define GFX11_HEVC_ARBITRATION_PRIORITY_Priority_bits 2 #define GFX9_HEVC_ARBITRATION_PRIORITY_Priority_bits 2 static inline uint32_t ATTRIBUTE_PURE HEVC_ARBITRATION_PRIORITY_Priority_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_HEVC_ARBITRATION_PRIORITY_Priority_start 0 #define GFX12_HEVC_ARBITRATION_PRIORITY_Priority_start 0 #define GFX11_HEVC_ARBITRATION_PRIORITY_Priority_start 0 #define GFX9_HEVC_ARBITRATION_PRIORITY_Priority_start 0 static inline uint32_t ATTRIBUTE_PURE HEVC_ARBITRATION_PRIORITY_Priority_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* HEVC_VP9_RDOQ_LAMBDA_FIELDS */ #define GFX125_HEVC_VP9_RDOQ_LAMBDA_FIELDS_length 1 #define GFX12_HEVC_VP9_RDOQ_LAMBDA_FIELDS_length 1 #define GFX11_HEVC_VP9_RDOQ_LAMBDA_FIELDS_length 1 #define GFX9_HEVC_VP9_RDOQ_LAMBDA_FIELDS_length 1 static inline uint32_t ATTRIBUTE_PURE HEVC_VP9_RDOQ_LAMBDA_FIELDS_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* HEVC_VP9_RDOQ_LAMBDA_FIELDS::Lambda Value 0 */ #define GFX125_HEVC_VP9_RDOQ_LAMBDA_FIELDS_LambdaValue0_bits 16 #define GFX12_HEVC_VP9_RDOQ_LAMBDA_FIELDS_LambdaValue0_bits 16 #define GFX11_HEVC_VP9_RDOQ_LAMBDA_FIELDS_LambdaValue0_bits 16 #define GFX9_HEVC_VP9_RDOQ_LAMBDA_FIELDS_LambdaValue0_bits 16 static inline uint32_t ATTRIBUTE_PURE HEVC_VP9_RDOQ_LAMBDA_FIELDS_LambdaValue0_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_HEVC_VP9_RDOQ_LAMBDA_FIELDS_LambdaValue0_start 0 #define GFX12_HEVC_VP9_RDOQ_LAMBDA_FIELDS_LambdaValue0_start 0 #define GFX11_HEVC_VP9_RDOQ_LAMBDA_FIELDS_LambdaValue0_start 0 #define GFX9_HEVC_VP9_RDOQ_LAMBDA_FIELDS_LambdaValue0_start 0 static inline uint32_t ATTRIBUTE_PURE HEVC_VP9_RDOQ_LAMBDA_FIELDS_LambdaValue0_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* HEVC_VP9_RDOQ_LAMBDA_FIELDS::Lambda Value 1 */ #define GFX125_HEVC_VP9_RDOQ_LAMBDA_FIELDS_LambdaValue1_bits 16 #define GFX12_HEVC_VP9_RDOQ_LAMBDA_FIELDS_LambdaValue1_bits 16 #define GFX11_HEVC_VP9_RDOQ_LAMBDA_FIELDS_LambdaValue1_bits 16 #define GFX9_HEVC_VP9_RDOQ_LAMBDA_FIELDS_LambdaValue1_bits 16 static inline uint32_t ATTRIBUTE_PURE HEVC_VP9_RDOQ_LAMBDA_FIELDS_LambdaValue1_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_HEVC_VP9_RDOQ_LAMBDA_FIELDS_LambdaValue1_start 16 #define GFX12_HEVC_VP9_RDOQ_LAMBDA_FIELDS_LambdaValue1_start 16 #define GFX11_HEVC_VP9_RDOQ_LAMBDA_FIELDS_LambdaValue1_start 16 #define GFX9_HEVC_VP9_RDOQ_LAMBDA_FIELDS_LambdaValue1_start 16 static inline uint32_t ATTRIBUTE_PURE HEVC_VP9_RDOQ_LAMBDA_FIELDS_LambdaValue1_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* HIZ_CHICKEN */ #define GFX125_HIZ_CHICKEN_length 1 #define GFX12_HIZ_CHICKEN_length 1 static inline uint32_t ATTRIBUTE_PURE HIZ_CHICKEN_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* HIZ_CHICKEN::HZ Depth Test LE/GE Optimization Disable */ #define GFX125_HIZ_CHICKEN_HZDepthTestLEGEOptimizationDisable_bits 1 #define GFX12_HIZ_CHICKEN_HZDepthTestLEGEOptimizationDisable_bits 1 static inline uint32_t ATTRIBUTE_PURE HIZ_CHICKEN_HZDepthTestLEGEOptimizationDisable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_HIZ_CHICKEN_HZDepthTestLEGEOptimizationDisable_start 13 #define GFX12_HIZ_CHICKEN_HZDepthTestLEGEOptimizationDisable_start 13 static inline uint32_t ATTRIBUTE_PURE HIZ_CHICKEN_HZDepthTestLEGEOptimizationDisable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 13; case 120: return 13; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* HIZ_CHICKEN::HZ Depth Test LE/GE Optimization Disable Mask */ #define GFX125_HIZ_CHICKEN_HZDepthTestLEGEOptimizationDisableMask_bits 1 #define GFX12_HIZ_CHICKEN_HZDepthTestLEGEOptimizationDisableMask_bits 1 static inline uint32_t ATTRIBUTE_PURE HIZ_CHICKEN_HZDepthTestLEGEOptimizationDisableMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_HIZ_CHICKEN_HZDepthTestLEGEOptimizationDisableMask_start 29 #define GFX12_HIZ_CHICKEN_HZDepthTestLEGEOptimizationDisableMask_start 29 static inline uint32_t ATTRIBUTE_PURE HIZ_CHICKEN_HZDepthTestLEGEOptimizationDisableMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* HS_INVOCATION_COUNT */ #define GFX125_HS_INVOCATION_COUNT_length 2 #define GFX12_HS_INVOCATION_COUNT_length 2 #define GFX11_HS_INVOCATION_COUNT_length 2 #define GFX9_HS_INVOCATION_COUNT_length 2 #define GFX8_HS_INVOCATION_COUNT_length 2 #define GFX75_HS_INVOCATION_COUNT_length 2 #define GFX7_HS_INVOCATION_COUNT_length 2 static inline uint32_t ATTRIBUTE_PURE HS_INVOCATION_COUNT_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* HS_INVOCATION_COUNT::HS Invocation Count Report */ #define GFX125_HS_INVOCATION_COUNT_HSInvocationCountReport_bits 64 #define GFX12_HS_INVOCATION_COUNT_HSInvocationCountReport_bits 64 #define GFX11_HS_INVOCATION_COUNT_HSInvocationCountReport_bits 64 #define GFX9_HS_INVOCATION_COUNT_HSInvocationCountReport_bits 64 #define GFX8_HS_INVOCATION_COUNT_HSInvocationCountReport_bits 64 #define GFX75_HS_INVOCATION_COUNT_HSInvocationCountReport_bits 64 #define GFX7_HS_INVOCATION_COUNT_HSInvocationCountReport_bits 64 static inline uint32_t ATTRIBUTE_PURE HS_INVOCATION_COUNT_HSInvocationCountReport_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 64; case 80: return 64; case 75: return 64; case 70: return 64; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_HS_INVOCATION_COUNT_HSInvocationCountReport_start 0 #define GFX12_HS_INVOCATION_COUNT_HSInvocationCountReport_start 0 #define GFX11_HS_INVOCATION_COUNT_HSInvocationCountReport_start 0 #define GFX9_HS_INVOCATION_COUNT_HSInvocationCountReport_start 0 #define GFX8_HS_INVOCATION_COUNT_HSInvocationCountReport_start 0 #define GFX75_HS_INVOCATION_COUNT_HSInvocationCountReport_start 0 #define GFX7_HS_INVOCATION_COUNT_HSInvocationCountReport_start 0 static inline uint32_t ATTRIBUTE_PURE HS_INVOCATION_COUNT_HSInvocationCountReport_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* HUC_VIRTUAL_ADDR_REGION */ #define GFX125_HUC_VIRTUAL_ADDR_REGION_length 3 #define GFX12_HUC_VIRTUAL_ADDR_REGION_length 3 #define GFX11_HUC_VIRTUAL_ADDR_REGION_length 3 #define GFX9_HUC_VIRTUAL_ADDR_REGION_length 3 static inline uint32_t ATTRIBUTE_PURE HUC_VIRTUAL_ADDR_REGION_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* HUC_VIRTUAL_ADDR_REGION::Address */ #define GFX125_HUC_VIRTUAL_ADDR_REGION_Address_bits 64 #define GFX12_HUC_VIRTUAL_ADDR_REGION_Address_bits 64 #define GFX11_HUC_VIRTUAL_ADDR_REGION_Address_bits 64 #define GFX9_HUC_VIRTUAL_ADDR_REGION_Address_bits 64 static inline uint32_t ATTRIBUTE_PURE HUC_VIRTUAL_ADDR_REGION_Address_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 64; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_HUC_VIRTUAL_ADDR_REGION_Address_start 0 #define GFX12_HUC_VIRTUAL_ADDR_REGION_Address_start 0 #define GFX11_HUC_VIRTUAL_ADDR_REGION_Address_start 0 #define GFX9_HUC_VIRTUAL_ADDR_REGION_Address_start 0 static inline uint32_t ATTRIBUTE_PURE HUC_VIRTUAL_ADDR_REGION_Address_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* HUC_VIRTUAL_ADDR_REGION::Memory Address Attributes */ #define GFX125_HUC_VIRTUAL_ADDR_REGION_MemoryAddressAttributes_bits 32 #define GFX12_HUC_VIRTUAL_ADDR_REGION_MemoryAddressAttributes_bits 32 #define GFX11_HUC_VIRTUAL_ADDR_REGION_MemoryAddressAttributes_bits 32 #define GFX9_HUC_VIRTUAL_ADDR_REGION_MemoryAddressAttributes_bits 32 static inline uint32_t ATTRIBUTE_PURE HUC_VIRTUAL_ADDR_REGION_MemoryAddressAttributes_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_HUC_VIRTUAL_ADDR_REGION_MemoryAddressAttributes_start 64 #define GFX12_HUC_VIRTUAL_ADDR_REGION_MemoryAddressAttributes_start 64 #define GFX11_HUC_VIRTUAL_ADDR_REGION_MemoryAddressAttributes_start 64 #define GFX9_HUC_VIRTUAL_ADDR_REGION_MemoryAddressAttributes_start 64 static inline uint32_t ATTRIBUTE_PURE HUC_VIRTUAL_ADDR_REGION_MemoryAddressAttributes_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 64; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* IA_PRIMITIVES_COUNT */ #define GFX125_IA_PRIMITIVES_COUNT_length 2 #define GFX12_IA_PRIMITIVES_COUNT_length 2 #define GFX11_IA_PRIMITIVES_COUNT_length 2 #define GFX9_IA_PRIMITIVES_COUNT_length 2 #define GFX8_IA_PRIMITIVES_COUNT_length 2 #define GFX75_IA_PRIMITIVES_COUNT_length 2 #define GFX7_IA_PRIMITIVES_COUNT_length 2 static inline uint32_t ATTRIBUTE_PURE IA_PRIMITIVES_COUNT_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* IA_PRIMITIVES_COUNT::IA Primitives Count Report */ #define GFX125_IA_PRIMITIVES_COUNT_IAPrimitivesCountReport_bits 64 #define GFX12_IA_PRIMITIVES_COUNT_IAPrimitivesCountReport_bits 64 #define GFX11_IA_PRIMITIVES_COUNT_IAPrimitivesCountReport_bits 64 #define GFX9_IA_PRIMITIVES_COUNT_IAPrimitivesCountReport_bits 64 #define GFX8_IA_PRIMITIVES_COUNT_IAPrimitivesCountReport_bits 64 #define GFX75_IA_PRIMITIVES_COUNT_IAPrimitivesCountReport_bits 64 #define GFX7_IA_PRIMITIVES_COUNT_IAPrimitivesCountReport_bits 64 static inline uint32_t ATTRIBUTE_PURE IA_PRIMITIVES_COUNT_IAPrimitivesCountReport_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 64; case 80: return 64; case 75: return 64; case 70: return 64; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_IA_PRIMITIVES_COUNT_IAPrimitivesCountReport_start 0 #define GFX12_IA_PRIMITIVES_COUNT_IAPrimitivesCountReport_start 0 #define GFX11_IA_PRIMITIVES_COUNT_IAPrimitivesCountReport_start 0 #define GFX9_IA_PRIMITIVES_COUNT_IAPrimitivesCountReport_start 0 #define GFX8_IA_PRIMITIVES_COUNT_IAPrimitivesCountReport_start 0 #define GFX75_IA_PRIMITIVES_COUNT_IAPrimitivesCountReport_start 0 #define GFX7_IA_PRIMITIVES_COUNT_IAPrimitivesCountReport_start 0 static inline uint32_t ATTRIBUTE_PURE IA_PRIMITIVES_COUNT_IAPrimitivesCountReport_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* IA_VERTICES_COUNT */ #define GFX125_IA_VERTICES_COUNT_length 2 #define GFX12_IA_VERTICES_COUNT_length 2 #define GFX11_IA_VERTICES_COUNT_length 2 #define GFX9_IA_VERTICES_COUNT_length 2 #define GFX8_IA_VERTICES_COUNT_length 2 #define GFX75_IA_VERTICES_COUNT_length 2 #define GFX7_IA_VERTICES_COUNT_length 2 static inline uint32_t ATTRIBUTE_PURE IA_VERTICES_COUNT_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* IA_VERTICES_COUNT::IA Vertices Count Report */ #define GFX125_IA_VERTICES_COUNT_IAVerticesCountReport_bits 64 #define GFX12_IA_VERTICES_COUNT_IAVerticesCountReport_bits 64 #define GFX11_IA_VERTICES_COUNT_IAVerticesCountReport_bits 64 #define GFX9_IA_VERTICES_COUNT_IAVerticesCountReport_bits 64 #define GFX8_IA_VERTICES_COUNT_IAVerticesCountReport_bits 64 #define GFX75_IA_VERTICES_COUNT_IAVerticesCountReport_bits 64 #define GFX7_IA_VERTICES_COUNT_IAVerticesCountReport_bits 64 static inline uint32_t ATTRIBUTE_PURE IA_VERTICES_COUNT_IAVerticesCountReport_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 64; case 80: return 64; case 75: return 64; case 70: return 64; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_IA_VERTICES_COUNT_IAVerticesCountReport_start 0 #define GFX12_IA_VERTICES_COUNT_IAVerticesCountReport_start 0 #define GFX11_IA_VERTICES_COUNT_IAVerticesCountReport_start 0 #define GFX9_IA_VERTICES_COUNT_IAVerticesCountReport_start 0 #define GFX8_IA_VERTICES_COUNT_IAVerticesCountReport_start 0 #define GFX75_IA_VERTICES_COUNT_IAVerticesCountReport_start 0 #define GFX7_IA_VERTICES_COUNT_IAVerticesCountReport_start 0 static inline uint32_t ATTRIBUTE_PURE IA_VERTICES_COUNT_IAVerticesCountReport_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* IMAGE_STATE_COST */ #define GFX125_IMAGE_STATE_COST_length 2 #define GFX12_IMAGE_STATE_COST_length 2 #define GFX11_IMAGE_STATE_COST_length 2 static inline uint32_t ATTRIBUTE_PURE IMAGE_STATE_COST_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* IMAGE_STATE_COST::MV 0 Cost */ #define GFX125_IMAGE_STATE_COST_MV0Cost_bits 8 #define GFX12_IMAGE_STATE_COST_MV0Cost_bits 8 #define GFX11_IMAGE_STATE_COST_MV0Cost_bits 8 static inline uint32_t ATTRIBUTE_PURE IMAGE_STATE_COST_MV0Cost_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_IMAGE_STATE_COST_MV0Cost_start 0 #define GFX12_IMAGE_STATE_COST_MV0Cost_start 0 #define GFX11_IMAGE_STATE_COST_MV0Cost_start 0 static inline uint32_t ATTRIBUTE_PURE IMAGE_STATE_COST_MV0Cost_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* IMAGE_STATE_COST::MV 1 Cost */ #define GFX125_IMAGE_STATE_COST_MV1Cost_bits 8 #define GFX12_IMAGE_STATE_COST_MV1Cost_bits 8 #define GFX11_IMAGE_STATE_COST_MV1Cost_bits 8 static inline uint32_t ATTRIBUTE_PURE IMAGE_STATE_COST_MV1Cost_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_IMAGE_STATE_COST_MV1Cost_start 8 #define GFX12_IMAGE_STATE_COST_MV1Cost_start 8 #define GFX11_IMAGE_STATE_COST_MV1Cost_start 8 static inline uint32_t ATTRIBUTE_PURE IMAGE_STATE_COST_MV1Cost_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* IMAGE_STATE_COST::MV 2 Cost */ #define GFX125_IMAGE_STATE_COST_MV2Cost_bits 8 #define GFX12_IMAGE_STATE_COST_MV2Cost_bits 8 #define GFX11_IMAGE_STATE_COST_MV2Cost_bits 8 static inline uint32_t ATTRIBUTE_PURE IMAGE_STATE_COST_MV2Cost_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_IMAGE_STATE_COST_MV2Cost_start 16 #define GFX12_IMAGE_STATE_COST_MV2Cost_start 16 #define GFX11_IMAGE_STATE_COST_MV2Cost_start 16 static inline uint32_t ATTRIBUTE_PURE IMAGE_STATE_COST_MV2Cost_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* IMAGE_STATE_COST::MV 3 Cost */ #define GFX125_IMAGE_STATE_COST_MV3Cost_bits 8 #define GFX12_IMAGE_STATE_COST_MV3Cost_bits 8 #define GFX11_IMAGE_STATE_COST_MV3Cost_bits 8 static inline uint32_t ATTRIBUTE_PURE IMAGE_STATE_COST_MV3Cost_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_IMAGE_STATE_COST_MV3Cost_start 24 #define GFX12_IMAGE_STATE_COST_MV3Cost_start 24 #define GFX11_IMAGE_STATE_COST_MV3Cost_start 24 static inline uint32_t ATTRIBUTE_PURE IMAGE_STATE_COST_MV3Cost_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* IMAGE_STATE_COST::MV 4 Cost */ #define GFX125_IMAGE_STATE_COST_MV4Cost_bits 8 #define GFX12_IMAGE_STATE_COST_MV4Cost_bits 8 #define GFX11_IMAGE_STATE_COST_MV4Cost_bits 8 static inline uint32_t ATTRIBUTE_PURE IMAGE_STATE_COST_MV4Cost_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_IMAGE_STATE_COST_MV4Cost_start 32 #define GFX12_IMAGE_STATE_COST_MV4Cost_start 32 #define GFX11_IMAGE_STATE_COST_MV4Cost_start 32 static inline uint32_t ATTRIBUTE_PURE IMAGE_STATE_COST_MV4Cost_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* IMAGE_STATE_COST::MV 5 Cost */ #define GFX125_IMAGE_STATE_COST_MV5Cost_bits 8 #define GFX12_IMAGE_STATE_COST_MV5Cost_bits 8 #define GFX11_IMAGE_STATE_COST_MV5Cost_bits 8 static inline uint32_t ATTRIBUTE_PURE IMAGE_STATE_COST_MV5Cost_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_IMAGE_STATE_COST_MV5Cost_start 40 #define GFX12_IMAGE_STATE_COST_MV5Cost_start 40 #define GFX11_IMAGE_STATE_COST_MV5Cost_start 40 static inline uint32_t ATTRIBUTE_PURE IMAGE_STATE_COST_MV5Cost_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 40; case 120: return 40; case 110: return 40; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* IMAGE_STATE_COST::MV 6 Cost */ #define GFX125_IMAGE_STATE_COST_MV6Cost_bits 8 #define GFX12_IMAGE_STATE_COST_MV6Cost_bits 8 #define GFX11_IMAGE_STATE_COST_MV6Cost_bits 8 static inline uint32_t ATTRIBUTE_PURE IMAGE_STATE_COST_MV6Cost_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_IMAGE_STATE_COST_MV6Cost_start 48 #define GFX12_IMAGE_STATE_COST_MV6Cost_start 48 #define GFX11_IMAGE_STATE_COST_MV6Cost_start 48 static inline uint32_t ATTRIBUTE_PURE IMAGE_STATE_COST_MV6Cost_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 48; case 120: return 48; case 110: return 48; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* IMAGE_STATE_COST::MV 7 Cost */ #define GFX125_IMAGE_STATE_COST_MV7Cost_bits 8 #define GFX12_IMAGE_STATE_COST_MV7Cost_bits 8 #define GFX11_IMAGE_STATE_COST_MV7Cost_bits 8 static inline uint32_t ATTRIBUTE_PURE IMAGE_STATE_COST_MV7Cost_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_IMAGE_STATE_COST_MV7Cost_start 56 #define GFX12_IMAGE_STATE_COST_MV7Cost_start 56 #define GFX11_IMAGE_STATE_COST_MV7Cost_start 56 static inline uint32_t ATTRIBUTE_PURE IMAGE_STATE_COST_MV7Cost_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 56; case 120: return 56; case 110: return 56; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT */ #define GFX125_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_length 3 #define GFX12_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_length 3 #define GFX11_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_length 3 #define GFX9_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_length 3 #define GFX8_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_length 3 #define GFX75_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_length 3 #define GFX7_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_length 2 static inline uint32_t ATTRIBUTE_PURE INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT::BSD Premature Complete Error Handling */ #define GFX125_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_BSDPrematureCompleteErrorHandling_bits 1 #define GFX12_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_BSDPrematureCompleteErrorHandling_bits 1 #define GFX11_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_BSDPrematureCompleteErrorHandling_bits 1 #define GFX9_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_BSDPrematureCompleteErrorHandling_bits 1 #define GFX8_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_BSDPrematureCompleteErrorHandling_bits 1 #define GFX75_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_BSDPrematureCompleteErrorHandling_bits 1 #define GFX7_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_BSDPrematureCompleteErrorHandling_bits 1 static inline uint32_t ATTRIBUTE_PURE INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_BSDPrematureCompleteErrorHandling_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_BSDPrematureCompleteErrorHandling_start 14 #define GFX12_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_BSDPrematureCompleteErrorHandling_start 14 #define GFX11_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_BSDPrematureCompleteErrorHandling_start 14 #define GFX9_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_BSDPrematureCompleteErrorHandling_start 14 #define GFX8_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_BSDPrematureCompleteErrorHandling_start 14 #define GFX75_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_BSDPrematureCompleteErrorHandling_start 14 #define GFX7_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_BSDPrematureCompleteErrorHandling_start 14 static inline uint32_t ATTRIBUTE_PURE INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_BSDPrematureCompleteErrorHandling_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 14; case 120: return 14; case 110: return 14; case 90: return 14; case 80: return 14; case 75: return 14; case 70: return 14; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT::B Slice Concealment Mode */ #define GFX125_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_BSliceConcealmentMode_bits 1 #define GFX12_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_BSliceConcealmentMode_bits 1 #define GFX11_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_BSliceConcealmentMode_bits 1 #define GFX9_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_BSliceConcealmentMode_bits 1 #define GFX8_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_BSliceConcealmentMode_bits 1 #define GFX75_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_BSliceConcealmentMode_bits 1 static inline uint32_t ATTRIBUTE_PURE INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_BSliceConcealmentMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_BSliceConcealmentMode_start 79 #define GFX12_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_BSliceConcealmentMode_start 79 #define GFX11_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_BSliceConcealmentMode_start 79 #define GFX9_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_BSliceConcealmentMode_start 79 #define GFX8_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_BSliceConcealmentMode_start 79 #define GFX75_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_BSliceConcealmentMode_start 79 static inline uint32_t ATTRIBUTE_PURE INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_BSliceConcealmentMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 79; case 120: return 79; case 110: return 79; case 90: return 79; case 80: return 79; case 75: return 79; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT::B Slice Inter Direct Type Concealment Mode */ #define GFX125_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_BSliceInterDirectTypeConcealmentMode_bits 2 #define GFX12_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_BSliceInterDirectTypeConcealmentMode_bits 2 #define GFX11_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_BSliceInterDirectTypeConcealmentMode_bits 2 #define GFX9_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_BSliceInterDirectTypeConcealmentMode_bits 2 #define GFX8_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_BSliceInterDirectTypeConcealmentMode_bits 2 #define GFX75_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_BSliceInterDirectTypeConcealmentMode_bits 2 static inline uint32_t ATTRIBUTE_PURE INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_BSliceInterDirectTypeConcealmentMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_BSliceInterDirectTypeConcealmentMode_start 76 #define GFX12_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_BSliceInterDirectTypeConcealmentMode_start 76 #define GFX11_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_BSliceInterDirectTypeConcealmentMode_start 76 #define GFX9_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_BSliceInterDirectTypeConcealmentMode_start 76 #define GFX8_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_BSliceInterDirectTypeConcealmentMode_start 76 #define GFX75_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_BSliceInterDirectTypeConcealmentMode_start 76 static inline uint32_t ATTRIBUTE_PURE INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_BSliceInterDirectTypeConcealmentMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 76; case 120: return 76; case 110: return 76; case 90: return 76; case 80: return 76; case 75: return 76; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT::B Slice Spatial Inter Concealment Mode */ #define GFX125_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_BSliceSpatialInterConcealmentMode_bits 3 #define GFX12_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_BSliceSpatialInterConcealmentMode_bits 3 #define GFX11_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_BSliceSpatialInterConcealmentMode_bits 3 #define GFX9_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_BSliceSpatialInterConcealmentMode_bits 3 #define GFX8_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_BSliceSpatialInterConcealmentMode_bits 3 #define GFX75_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_BSliceSpatialInterConcealmentMode_bits 3 static inline uint32_t ATTRIBUTE_PURE INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_BSliceSpatialInterConcealmentMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_BSliceSpatialInterConcealmentMode_start 72 #define GFX12_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_BSliceSpatialInterConcealmentMode_start 72 #define GFX11_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_BSliceSpatialInterConcealmentMode_start 72 #define GFX9_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_BSliceSpatialInterConcealmentMode_start 72 #define GFX8_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_BSliceSpatialInterConcealmentMode_start 72 #define GFX75_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_BSliceSpatialInterConcealmentMode_start 72 static inline uint32_t ATTRIBUTE_PURE INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_BSliceSpatialInterConcealmentMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 72; case 120: return 72; case 110: return 72; case 90: return 72; case 80: return 72; case 75: return 72; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT::B Slice Temporal Inter Concealment Mode */ #define GFX125_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_BSliceTemporalInterConcealmentMode_bits 3 #define GFX12_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_BSliceTemporalInterConcealmentMode_bits 3 #define GFX11_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_BSliceTemporalInterConcealmentMode_bits 3 #define GFX9_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_BSliceTemporalInterConcealmentMode_bits 3 #define GFX8_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_BSliceTemporalInterConcealmentMode_bits 3 #define GFX75_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_BSliceTemporalInterConcealmentMode_bits 3 static inline uint32_t ATTRIBUTE_PURE INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_BSliceTemporalInterConcealmentMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_BSliceTemporalInterConcealmentMode_start 68 #define GFX12_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_BSliceTemporalInterConcealmentMode_start 68 #define GFX11_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_BSliceTemporalInterConcealmentMode_start 68 #define GFX9_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_BSliceTemporalInterConcealmentMode_start 68 #define GFX8_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_BSliceTemporalInterConcealmentMode_start 68 #define GFX75_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_BSliceTemporalInterConcealmentMode_start 68 static inline uint32_t ATTRIBUTE_PURE INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_BSliceTemporalInterConcealmentMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 68; case 120: return 68; case 110: return 68; case 90: return 68; case 80: return 68; case 75: return 68; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT::Concealment Method */ #define GFX125_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_ConcealmentMethod_bits 1 #define GFX12_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_ConcealmentMethod_bits 1 #define GFX11_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_ConcealmentMethod_bits 1 #define GFX9_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_ConcealmentMethod_bits 1 #define GFX8_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_ConcealmentMethod_bits 1 #define GFX75_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_ConcealmentMethod_bits 1 #define GFX7_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_ConcealmentMethod_bits 1 static inline uint32_t ATTRIBUTE_PURE INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_ConcealmentMethod_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_ConcealmentMethod_start 31 #define GFX12_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_ConcealmentMethod_start 31 #define GFX11_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_ConcealmentMethod_start 31 #define GFX9_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_ConcealmentMethod_start 31 #define GFX8_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_ConcealmentMethod_start 31 #define GFX75_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_ConcealmentMethod_start 31 #define GFX7_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_ConcealmentMethod_start 31 static inline uint32_t ATTRIBUTE_PURE INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_ConcealmentMethod_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 31; case 120: return 31; case 110: return 31; case 90: return 31; case 80: return 31; case 75: return 31; case 70: return 31; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT::Concealment Picture ID */ #define GFX125_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_ConcealmentPictureID_bits 6 #define GFX12_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_ConcealmentPictureID_bits 6 #define GFX11_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_ConcealmentPictureID_bits 6 #define GFX9_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_ConcealmentPictureID_bits 6 #define GFX8_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_ConcealmentPictureID_bits 6 #define GFX75_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_ConcealmentPictureID_bits 6 #define GFX7_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_ConcealmentPictureID_bits 6 static inline uint32_t ATTRIBUTE_PURE INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_ConcealmentPictureID_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 6; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_ConcealmentPictureID_start 16 #define GFX12_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_ConcealmentPictureID_start 16 #define GFX11_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_ConcealmentPictureID_start 16 #define GFX9_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_ConcealmentPictureID_start 16 #define GFX8_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_ConcealmentPictureID_start 16 #define GFX75_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_ConcealmentPictureID_start 16 #define GFX7_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_ConcealmentPictureID_start 16 static inline uint32_t ATTRIBUTE_PURE INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_ConcealmentPictureID_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT::Concealment Reference Picture + Field Bit */ #define GFX125_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_ConcealmentReferencePictureFieldBit_bits 6 #define GFX12_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_ConcealmentReferencePictureFieldBit_bits 6 #define GFX11_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_ConcealmentReferencePictureFieldBit_bits 6 #define GFX9_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_ConcealmentReferencePictureFieldBit_bits 6 #define GFX8_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_ConcealmentReferencePictureFieldBit_bits 6 #define GFX75_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_ConcealmentReferencePictureFieldBit_bits 6 static inline uint32_t ATTRIBUTE_PURE INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_ConcealmentReferencePictureFieldBit_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_ConcealmentReferencePictureFieldBit_start 88 #define GFX12_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_ConcealmentReferencePictureFieldBit_start 88 #define GFX11_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_ConcealmentReferencePictureFieldBit_start 88 #define GFX9_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_ConcealmentReferencePictureFieldBit_start 88 #define GFX8_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_ConcealmentReferencePictureFieldBit_start 88 #define GFX75_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_ConcealmentReferencePictureFieldBit_start 88 static inline uint32_t ATTRIBUTE_PURE INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_ConcealmentReferencePictureFieldBit_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 88; case 120: return 88; case 110: return 88; case 90: return 88; case 80: return 88; case 75: return 88; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT::Emulation Prevention Byte Present */ #define GFX125_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_EmulationPreventionBytePresent_bits 1 #define GFX12_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_EmulationPreventionBytePresent_bits 1 #define GFX11_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_EmulationPreventionBytePresent_bits 1 #define GFX9_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_EmulationPreventionBytePresent_bits 1 #define GFX8_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_EmulationPreventionBytePresent_bits 1 #define GFX75_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_EmulationPreventionBytePresent_bits 1 #define GFX7_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_EmulationPreventionBytePresent_bits 1 static inline uint32_t ATTRIBUTE_PURE INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_EmulationPreventionBytePresent_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_EmulationPreventionBytePresent_start 36 #define GFX12_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_EmulationPreventionBytePresent_start 36 #define GFX11_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_EmulationPreventionBytePresent_start 36 #define GFX9_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_EmulationPreventionBytePresent_start 36 #define GFX8_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_EmulationPreventionBytePresent_start 36 #define GFX75_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_EmulationPreventionBytePresent_start 36 #define GFX7_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_EmulationPreventionBytePresent_start 36 static inline uint32_t ATTRIBUTE_PURE INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_EmulationPreventionBytePresent_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 36; case 120: return 36; case 110: return 36; case 90: return 36; case 80: return 36; case 75: return 36; case 70: return 36; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT::Entropy Error Handling */ #define GFX125_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_EntropyErrorHandling_bits 1 #define GFX12_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_EntropyErrorHandling_bits 1 #define GFX11_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_EntropyErrorHandling_bits 1 #define GFX9_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_EntropyErrorHandling_bits 1 #define GFX8_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_EntropyErrorHandling_bits 1 #define GFX75_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_EntropyErrorHandling_bits 1 #define GFX7_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_EntropyErrorHandling_bits 1 static inline uint32_t ATTRIBUTE_PURE INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_EntropyErrorHandling_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_EntropyErrorHandling_start 10 #define GFX12_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_EntropyErrorHandling_start 10 #define GFX11_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_EntropyErrorHandling_start 10 #define GFX9_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_EntropyErrorHandling_start 10 #define GFX8_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_EntropyErrorHandling_start 10 #define GFX75_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_EntropyErrorHandling_start 10 #define GFX7_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_EntropyErrorHandling_start 10 static inline uint32_t ATTRIBUTE_PURE INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_EntropyErrorHandling_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 10; case 120: return 10; case 110: return 10; case 90: return 10; case 80: return 10; case 75: return 10; case 70: return 10; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT::First MB Bit Offset */ #define GFX125_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_FirstMBBitOffset_bits 3 #define GFX12_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_FirstMBBitOffset_bits 3 #define GFX11_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_FirstMBBitOffset_bits 3 #define GFX9_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_FirstMBBitOffset_bits 3 #define GFX8_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_FirstMBBitOffset_bits 3 #define GFX75_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_FirstMBBitOffset_bits 3 #define GFX7_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_FirstMBBitOffset_bits 3 static inline uint32_t ATTRIBUTE_PURE INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_FirstMBBitOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_FirstMBBitOffset_start 32 #define GFX12_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_FirstMBBitOffset_start 32 #define GFX11_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_FirstMBBitOffset_start 32 #define GFX9_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_FirstMBBitOffset_start 32 #define GFX8_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_FirstMBBitOffset_start 32 #define GFX75_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_FirstMBBitOffset_start 32 #define GFX7_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_FirstMBBitOffset_start 32 static inline uint32_t ATTRIBUTE_PURE INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_FirstMBBitOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT::First MB Byte Offset of Slice Data or Slice Header */ #define GFX125_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_FirstMBByteOffsetofSliceDataorSliceHeader_bits 16 #define GFX12_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_FirstMBByteOffsetofSliceDataorSliceHeader_bits 16 #define GFX11_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_FirstMBByteOffsetofSliceDataorSliceHeader_bits 16 #define GFX9_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_FirstMBByteOffsetofSliceDataorSliceHeader_bits 16 #define GFX8_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_FirstMBByteOffsetofSliceDataorSliceHeader_bits 16 #define GFX75_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_FirstMBByteOffsetofSliceDataorSliceHeader_bits 16 #define GFX7_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_FirstMBByteOffsetofSliceDataorSliceHeader_bits 16 static inline uint32_t ATTRIBUTE_PURE INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_FirstMBByteOffsetofSliceDataorSliceHeader_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_FirstMBByteOffsetofSliceDataorSliceHeader_start 48 #define GFX12_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_FirstMBByteOffsetofSliceDataorSliceHeader_start 48 #define GFX11_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_FirstMBByteOffsetofSliceDataorSliceHeader_start 48 #define GFX9_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_FirstMBByteOffsetofSliceDataorSliceHeader_start 48 #define GFX8_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_FirstMBByteOffsetofSliceDataorSliceHeader_start 48 #define GFX75_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_FirstMBByteOffsetofSliceDataorSliceHeader_start 48 #define GFX7_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_FirstMBByteOffsetofSliceDataorSliceHeader_start 48 static inline uint32_t ATTRIBUTE_PURE INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_FirstMBByteOffsetofSliceDataorSliceHeader_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 48; case 120: return 48; case 110: return 48; case 90: return 48; case 80: return 48; case 75: return 48; case 70: return 48; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT::Fix Prev MB Skipped */ #define GFX125_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_FixPrevMBSkipped_bits 1 #define GFX12_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_FixPrevMBSkipped_bits 1 #define GFX11_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_FixPrevMBSkipped_bits 1 #define GFX9_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_FixPrevMBSkipped_bits 1 #define GFX8_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_FixPrevMBSkipped_bits 1 #define GFX75_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_FixPrevMBSkipped_bits 1 #define GFX7_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_FixPrevMBSkipped_bits 1 static inline uint32_t ATTRIBUTE_PURE INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_FixPrevMBSkipped_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_FixPrevMBSkipped_start 39 #define GFX12_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_FixPrevMBSkipped_start 39 #define GFX11_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_FixPrevMBSkipped_start 39 #define GFX9_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_FixPrevMBSkipped_start 39 #define GFX8_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_FixPrevMBSkipped_start 39 #define GFX75_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_FixPrevMBSkipped_start 39 #define GFX7_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_FixPrevMBSkipped_start 39 static inline uint32_t ATTRIBUTE_PURE INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_FixPrevMBSkipped_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 39; case 120: return 39; case 110: return 39; case 90: return 39; case 80: return 39; case 75: return 39; case 70: return 39; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT::I Slice Concealment Mode */ #define GFX125_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_ISliceConcealmentMode_bits 1 #define GFX12_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_ISliceConcealmentMode_bits 1 #define GFX11_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_ISliceConcealmentMode_bits 1 #define GFX9_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_ISliceConcealmentMode_bits 1 #define GFX8_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_ISliceConcealmentMode_bits 1 #define GFX75_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_ISliceConcealmentMode_bits 1 static inline uint32_t ATTRIBUTE_PURE INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_ISliceConcealmentMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_ISliceConcealmentMode_start 95 #define GFX12_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_ISliceConcealmentMode_start 95 #define GFX11_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_ISliceConcealmentMode_start 95 #define GFX9_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_ISliceConcealmentMode_start 95 #define GFX8_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_ISliceConcealmentMode_start 95 #define GFX75_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_ISliceConcealmentMode_start 95 static inline uint32_t ATTRIBUTE_PURE INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_ISliceConcealmentMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 95; case 120: return 95; case 110: return 95; case 90: return 95; case 80: return 95; case 75: return 95; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT::Init Current MB Number */ #define GFX125_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_InitCurrentMBNumber_bits 1 #define GFX12_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_InitCurrentMBNumber_bits 1 #define GFX11_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_InitCurrentMBNumber_bits 1 #define GFX9_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_InitCurrentMBNumber_bits 1 #define GFX8_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_InitCurrentMBNumber_bits 1 #define GFX75_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_InitCurrentMBNumber_bits 1 #define GFX7_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_InitCurrentMBNumber_bits 1 static inline uint32_t ATTRIBUTE_PURE INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_InitCurrentMBNumber_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_InitCurrentMBNumber_start 30 #define GFX12_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_InitCurrentMBNumber_start 30 #define GFX11_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_InitCurrentMBNumber_start 30 #define GFX9_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_InitCurrentMBNumber_start 30 #define GFX8_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_InitCurrentMBNumber_start 30 #define GFX75_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_InitCurrentMBNumber_start 30 #define GFX7_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_InitCurrentMBNumber_start 30 static inline uint32_t ATTRIBUTE_PURE INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_InitCurrentMBNumber_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 30; case 120: return 30; case 110: return 30; case 90: return 30; case 80: return 30; case 75: return 30; case 70: return 30; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT::Intra 8x8/4x4 Prediction Error Concealment Control */ #define GFX125_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_Intra8x84x4PredictionErrorConcealmentControl_bits 1 #define GFX12_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_Intra8x84x4PredictionErrorConcealmentControl_bits 1 #define GFX11_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_Intra8x84x4PredictionErrorConcealmentControl_bits 1 #define GFX9_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_Intra8x84x4PredictionErrorConcealmentControl_bits 1 #define GFX8_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_Intra8x84x4PredictionErrorConcealmentControl_bits 1 #define GFX75_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_Intra8x84x4PredictionErrorConcealmentControl_bits 1 static inline uint32_t ATTRIBUTE_PURE INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_Intra8x84x4PredictionErrorConcealmentControl_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_Intra8x84x4PredictionErrorConcealmentControl_start 65 #define GFX12_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_Intra8x84x4PredictionErrorConcealmentControl_start 65 #define GFX11_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_Intra8x84x4PredictionErrorConcealmentControl_start 65 #define GFX9_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_Intra8x84x4PredictionErrorConcealmentControl_start 65 #define GFX8_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_Intra8x84x4PredictionErrorConcealmentControl_start 65 #define GFX75_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_Intra8x84x4PredictionErrorConcealmentControl_start 65 static inline uint32_t ATTRIBUTE_PURE INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_Intra8x84x4PredictionErrorConcealmentControl_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 65; case 120: return 65; case 110: return 65; case 90: return 65; case 80: return 65; case 75: return 65; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT::Intra PredMode (4x4/8x8 Luma) Error Control */ #define GFX125_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_IntraPredMode4x48x8LumaErrorControl_bits 1 #define GFX12_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_IntraPredMode4x48x8LumaErrorControl_bits 1 #define GFX11_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_IntraPredMode4x48x8LumaErrorControl_bits 1 #define GFX9_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_IntraPredMode4x48x8LumaErrorControl_bits 1 #define GFX8_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_IntraPredMode4x48x8LumaErrorControl_bits 1 #define GFX75_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_IntraPredMode4x48x8LumaErrorControl_bits 1 static inline uint32_t ATTRIBUTE_PURE INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_IntraPredMode4x48x8LumaErrorControl_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_IntraPredMode4x48x8LumaErrorControl_start 29 #define GFX12_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_IntraPredMode4x48x8LumaErrorControl_start 29 #define GFX11_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_IntraPredMode4x48x8LumaErrorControl_start 29 #define GFX9_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_IntraPredMode4x48x8LumaErrorControl_start 29 #define GFX8_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_IntraPredMode4x48x8LumaErrorControl_start 29 #define GFX75_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_IntraPredMode4x48x8LumaErrorControl_start 29 static inline uint32_t ATTRIBUTE_PURE INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_IntraPredMode4x48x8LumaErrorControl_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT::Intra Prediction Error Control */ #define GFX125_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_IntraPredictionErrorControl_bits 1 #define GFX12_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_IntraPredictionErrorControl_bits 1 #define GFX11_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_IntraPredictionErrorControl_bits 1 #define GFX9_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_IntraPredictionErrorControl_bits 1 #define GFX8_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_IntraPredictionErrorControl_bits 1 #define GFX75_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_IntraPredictionErrorControl_bits 1 static inline uint32_t ATTRIBUTE_PURE INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_IntraPredictionErrorControl_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_IntraPredictionErrorControl_start 64 #define GFX12_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_IntraPredictionErrorControl_start 64 #define GFX11_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_IntraPredictionErrorControl_start 64 #define GFX9_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_IntraPredictionErrorControl_start 64 #define GFX8_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_IntraPredictionErrorControl_start 64 #define GFX75_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_IntraPredictionErrorControl_start 64 static inline uint32_t ATTRIBUTE_PURE INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_IntraPredictionErrorControl_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 64; case 80: return 64; case 75: return 64; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT::Last Slice */ #define GFX125_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_LastSlice_bits 1 #define GFX12_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_LastSlice_bits 1 #define GFX11_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_LastSlice_bits 1 #define GFX9_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_LastSlice_bits 1 #define GFX8_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_LastSlice_bits 1 #define GFX75_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_LastSlice_bits 1 #define GFX7_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_LastSlice_bits 1 static inline uint32_t ATTRIBUTE_PURE INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_LastSlice_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_LastSlice_start 35 #define GFX12_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_LastSlice_start 35 #define GFX11_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_LastSlice_start 35 #define GFX9_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_LastSlice_start 35 #define GFX8_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_LastSlice_start 35 #define GFX75_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_LastSlice_start 35 #define GFX7_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_LastSlice_start 35 static inline uint32_t ATTRIBUTE_PURE INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_LastSlice_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 35; case 120: return 35; case 110: return 35; case 90: return 35; case 80: return 35; case 75: return 35; case 70: return 35; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT::MB Error Concealment B Spatial Motion Vectors Override Disable */ #define GFX125_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBSpatialMotionVectorsOverrideDisable_bits 1 #define GFX12_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBSpatialMotionVectorsOverrideDisable_bits 1 #define GFX11_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBSpatialMotionVectorsOverrideDisable_bits 1 #define GFX9_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBSpatialMotionVectorsOverrideDisable_bits 1 #define GFX8_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBSpatialMotionVectorsOverrideDisable_bits 1 #define GFX75_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBSpatialMotionVectorsOverrideDisable_bits 1 #define GFX7_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBSpatialMotionVectorsOverrideDisable_bits 1 static inline uint32_t ATTRIBUTE_PURE INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBSpatialMotionVectorsOverrideDisable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBSpatialMotionVectorsOverrideDisable_start 4 #define GFX12_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBSpatialMotionVectorsOverrideDisable_start 4 #define GFX11_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBSpatialMotionVectorsOverrideDisable_start 4 #define GFX9_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBSpatialMotionVectorsOverrideDisable_start 4 #define GFX8_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBSpatialMotionVectorsOverrideDisable_start 4 #define GFX75_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBSpatialMotionVectorsOverrideDisable_start 4 #define GFX7_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBSpatialMotionVectorsOverrideDisable_start 4 static inline uint32_t ATTRIBUTE_PURE INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBSpatialMotionVectorsOverrideDisable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 4; case 70: return 4; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT::MB Error Concealment B Spatial Prediction Mode */ #define GFX125_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBSpatialPredictionMode_bits 2 #define GFX12_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBSpatialPredictionMode_bits 2 #define GFX11_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBSpatialPredictionMode_bits 2 #define GFX9_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBSpatialPredictionMode_bits 2 #define GFX8_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBSpatialPredictionMode_bits 2 #define GFX75_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBSpatialPredictionMode_bits 2 #define GFX7_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBSpatialPredictionMode_bits 2 static inline uint32_t ATTRIBUTE_PURE INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBSpatialPredictionMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBSpatialPredictionMode_start 6 #define GFX12_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBSpatialPredictionMode_start 6 #define GFX11_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBSpatialPredictionMode_start 6 #define GFX9_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBSpatialPredictionMode_start 6 #define GFX8_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBSpatialPredictionMode_start 6 #define GFX75_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBSpatialPredictionMode_start 6 #define GFX7_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBSpatialPredictionMode_start 6 static inline uint32_t ATTRIBUTE_PURE INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBSpatialPredictionMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 6; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT::MB Error Concealment B Spatial Reference Index Override Disable */ #define GFX7_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBSpatialReferenceIndexOverrideDisable_bits 1 static inline uint32_t ATTRIBUTE_PURE INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBSpatialReferenceIndexOverrideDisable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX7_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBSpatialReferenceIndexOverrideDisable_start 5 static inline uint32_t ATTRIBUTE_PURE INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBSpatialReferenceIndexOverrideDisable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 5; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT::MB Error Concealment B Spatial Weight Prediction Disable */ #define GFX125_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBSpatialWeightPredictionDisable_bits 1 #define GFX12_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBSpatialWeightPredictionDisable_bits 1 #define GFX11_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBSpatialWeightPredictionDisable_bits 1 #define GFX9_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBSpatialWeightPredictionDisable_bits 1 #define GFX8_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBSpatialWeightPredictionDisable_bits 1 #define GFX75_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBSpatialWeightPredictionDisable_bits 1 #define GFX7_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBSpatialWeightPredictionDisable_bits 1 static inline uint32_t ATTRIBUTE_PURE INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBSpatialWeightPredictionDisable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBSpatialWeightPredictionDisable_start 3 #define GFX12_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBSpatialWeightPredictionDisable_start 3 #define GFX11_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBSpatialWeightPredictionDisable_start 3 #define GFX9_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBSpatialWeightPredictionDisable_start 3 #define GFX8_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBSpatialWeightPredictionDisable_start 3 #define GFX75_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBSpatialWeightPredictionDisable_start 3 #define GFX7_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBSpatialWeightPredictionDisable_start 3 static inline uint32_t ATTRIBUTE_PURE INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBSpatialWeightPredictionDisable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT::MB Error Concealment B Temporal Motion Vectors Override Enable */ #define GFX125_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBTemporalMotionVectorsOverrideEnable_bits 1 #define GFX12_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBTemporalMotionVectorsOverrideEnable_bits 1 #define GFX11_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBTemporalMotionVectorsOverrideEnable_bits 1 #define GFX9_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBTemporalMotionVectorsOverrideEnable_bits 1 #define GFX8_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBTemporalMotionVectorsOverrideEnable_bits 1 #define GFX75_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBTemporalMotionVectorsOverrideEnable_bits 1 #define GFX7_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBTemporalMotionVectorsOverrideEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBTemporalMotionVectorsOverrideEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBTemporalMotionVectorsOverrideEnable_start 25 #define GFX12_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBTemporalMotionVectorsOverrideEnable_start 25 #define GFX11_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBTemporalMotionVectorsOverrideEnable_start 25 #define GFX9_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBTemporalMotionVectorsOverrideEnable_start 25 #define GFX8_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBTemporalMotionVectorsOverrideEnable_start 25 #define GFX75_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBTemporalMotionVectorsOverrideEnable_start 25 #define GFX7_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBTemporalMotionVectorsOverrideEnable_start 25 static inline uint32_t ATTRIBUTE_PURE INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBTemporalMotionVectorsOverrideEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 25; case 120: return 25; case 110: return 25; case 90: return 25; case 80: return 25; case 75: return 25; case 70: return 25; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT::MB Error Concealment B Temporal Prediction Mode */ #define GFX125_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBTemporalPredictionMode_bits 2 #define GFX12_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBTemporalPredictionMode_bits 2 #define GFX11_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBTemporalPredictionMode_bits 2 #define GFX9_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBTemporalPredictionMode_bits 2 #define GFX8_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBTemporalPredictionMode_bits 2 #define GFX75_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBTemporalPredictionMode_bits 2 #define GFX7_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBTemporalPredictionMode_bits 2 static inline uint32_t ATTRIBUTE_PURE INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBTemporalPredictionMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBTemporalPredictionMode_start 27 #define GFX12_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBTemporalPredictionMode_start 27 #define GFX11_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBTemporalPredictionMode_start 27 #define GFX9_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBTemporalPredictionMode_start 27 #define GFX8_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBTemporalPredictionMode_start 27 #define GFX75_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBTemporalPredictionMode_start 27 #define GFX7_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBTemporalPredictionMode_start 27 static inline uint32_t ATTRIBUTE_PURE INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBTemporalPredictionMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT::MB Error Concealment B Temporal Reference Index Override Enable */ #define GFX7_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBTemporalReferenceIndexOverrideEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBTemporalReferenceIndexOverrideEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX7_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBTemporalReferenceIndexOverrideEnable_start 26 static inline uint32_t ATTRIBUTE_PURE INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBTemporalReferenceIndexOverrideEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 26; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT::MB Error Concealment B Temporal Weight Prediction Disable */ #define GFX125_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBTemporalWeightPredictionDisable_bits 1 #define GFX12_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBTemporalWeightPredictionDisable_bits 1 #define GFX11_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBTemporalWeightPredictionDisable_bits 1 #define GFX9_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBTemporalWeightPredictionDisable_bits 1 #define GFX8_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBTemporalWeightPredictionDisable_bits 1 #define GFX75_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBTemporalWeightPredictionDisable_bits 1 #define GFX7_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBTemporalWeightPredictionDisable_bits 1 static inline uint32_t ATTRIBUTE_PURE INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBTemporalWeightPredictionDisable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBTemporalWeightPredictionDisable_start 24 #define GFX12_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBTemporalWeightPredictionDisable_start 24 #define GFX11_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBTemporalWeightPredictionDisable_start 24 #define GFX9_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBTemporalWeightPredictionDisable_start 24 #define GFX8_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBTemporalWeightPredictionDisable_start 24 #define GFX75_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBTemporalWeightPredictionDisable_start 24 #define GFX7_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBTemporalWeightPredictionDisable_start 24 static inline uint32_t ATTRIBUTE_PURE INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentBTemporalWeightPredictionDisable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT::MB Error Concealment P Slice Motion Vectors Override Disable */ #define GFX125_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentPSliceMotionVectorsOverrideDisable_bits 1 #define GFX12_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentPSliceMotionVectorsOverrideDisable_bits 1 #define GFX11_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentPSliceMotionVectorsOverrideDisable_bits 1 #define GFX9_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentPSliceMotionVectorsOverrideDisable_bits 1 #define GFX8_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentPSliceMotionVectorsOverrideDisable_bits 1 #define GFX75_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentPSliceMotionVectorsOverrideDisable_bits 1 #define GFX7_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentPSliceMotionVectorsOverrideDisable_bits 1 static inline uint32_t ATTRIBUTE_PURE INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentPSliceMotionVectorsOverrideDisable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentPSliceMotionVectorsOverrideDisable_start 1 #define GFX12_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentPSliceMotionVectorsOverrideDisable_start 1 #define GFX11_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentPSliceMotionVectorsOverrideDisable_start 1 #define GFX9_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentPSliceMotionVectorsOverrideDisable_start 1 #define GFX8_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentPSliceMotionVectorsOverrideDisable_start 1 #define GFX75_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentPSliceMotionVectorsOverrideDisable_start 1 #define GFX7_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentPSliceMotionVectorsOverrideDisable_start 1 static inline uint32_t ATTRIBUTE_PURE INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentPSliceMotionVectorsOverrideDisable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT::MB Error Concealment P Slice Reference Index Override Disable */ #define GFX7_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentPSliceReferenceIndexOverrideDisable_bits 1 static inline uint32_t ATTRIBUTE_PURE INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentPSliceReferenceIndexOverrideDisable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX7_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentPSliceReferenceIndexOverrideDisable_start 2 static inline uint32_t ATTRIBUTE_PURE INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentPSliceReferenceIndexOverrideDisable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT::MB Error Concealment P Slice Weight Prediction Disable */ #define GFX125_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentPSliceWeightPredictionDisable_bits 1 #define GFX12_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentPSliceWeightPredictionDisable_bits 1 #define GFX11_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentPSliceWeightPredictionDisable_bits 1 #define GFX9_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentPSliceWeightPredictionDisable_bits 1 #define GFX8_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentPSliceWeightPredictionDisable_bits 1 #define GFX75_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentPSliceWeightPredictionDisable_bits 1 #define GFX7_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentPSliceWeightPredictionDisable_bits 1 static inline uint32_t ATTRIBUTE_PURE INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentPSliceWeightPredictionDisable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentPSliceWeightPredictionDisable_start 0 #define GFX12_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentPSliceWeightPredictionDisable_start 0 #define GFX11_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentPSliceWeightPredictionDisable_start 0 #define GFX9_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentPSliceWeightPredictionDisable_start 0 #define GFX8_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentPSliceWeightPredictionDisable_start 0 #define GFX75_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentPSliceWeightPredictionDisable_start 0 #define GFX7_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentPSliceWeightPredictionDisable_start 0 static inline uint32_t ATTRIBUTE_PURE INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBErrorConcealmentPSliceWeightPredictionDisable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT::MB Header Error Handling */ #define GFX125_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBHeaderErrorHandling_bits 1 #define GFX12_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBHeaderErrorHandling_bits 1 #define GFX11_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBHeaderErrorHandling_bits 1 #define GFX9_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBHeaderErrorHandling_bits 1 #define GFX8_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBHeaderErrorHandling_bits 1 #define GFX75_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBHeaderErrorHandling_bits 1 #define GFX7_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBHeaderErrorHandling_bits 1 static inline uint32_t ATTRIBUTE_PURE INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBHeaderErrorHandling_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBHeaderErrorHandling_start 8 #define GFX12_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBHeaderErrorHandling_start 8 #define GFX11_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBHeaderErrorHandling_start 8 #define GFX9_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBHeaderErrorHandling_start 8 #define GFX8_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBHeaderErrorHandling_start 8 #define GFX75_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBHeaderErrorHandling_start 8 #define GFX7_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBHeaderErrorHandling_start 8 static inline uint32_t ATTRIBUTE_PURE INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MBHeaderErrorHandling_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT::MPR Error Handling */ #define GFX125_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MPRErrorHandling_bits 1 #define GFX12_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MPRErrorHandling_bits 1 #define GFX11_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MPRErrorHandling_bits 1 #define GFX9_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MPRErrorHandling_bits 1 #define GFX8_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MPRErrorHandling_bits 1 #define GFX75_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MPRErrorHandling_bits 1 #define GFX7_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MPRErrorHandling_bits 1 static inline uint32_t ATTRIBUTE_PURE INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MPRErrorHandling_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MPRErrorHandling_start 12 #define GFX12_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MPRErrorHandling_start 12 #define GFX11_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MPRErrorHandling_start 12 #define GFX9_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MPRErrorHandling_start 12 #define GFX8_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MPRErrorHandling_start 12 #define GFX75_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MPRErrorHandling_start 12 #define GFX7_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MPRErrorHandling_start 12 static inline uint32_t ATTRIBUTE_PURE INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_MPRErrorHandling_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 12; case 120: return 12; case 110: return 12; case 90: return 12; case 80: return 12; case 75: return 12; case 70: return 12; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT::P Slice Concealment Mode */ #define GFX125_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_PSliceConcealmentMode_bits 1 #define GFX12_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_PSliceConcealmentMode_bits 1 #define GFX11_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_PSliceConcealmentMode_bits 1 #define GFX9_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_PSliceConcealmentMode_bits 1 #define GFX8_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_PSliceConcealmentMode_bits 1 #define GFX75_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_PSliceConcealmentMode_bits 1 static inline uint32_t ATTRIBUTE_PURE INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_PSliceConcealmentMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_PSliceConcealmentMode_start 87 #define GFX12_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_PSliceConcealmentMode_start 87 #define GFX11_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_PSliceConcealmentMode_start 87 #define GFX9_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_PSliceConcealmentMode_start 87 #define GFX8_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_PSliceConcealmentMode_start 87 #define GFX75_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_PSliceConcealmentMode_start 87 static inline uint32_t ATTRIBUTE_PURE INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_PSliceConcealmentMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 87; case 120: return 87; case 110: return 87; case 90: return 87; case 80: return 87; case 75: return 87; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT::P Slice Inter Concealment Mode */ #define GFX125_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_PSliceInterConcealmentMode_bits 3 #define GFX12_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_PSliceInterConcealmentMode_bits 3 #define GFX11_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_PSliceInterConcealmentMode_bits 3 #define GFX9_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_PSliceInterConcealmentMode_bits 3 #define GFX8_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_PSliceInterConcealmentMode_bits 3 #define GFX75_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_PSliceInterConcealmentMode_bits 3 static inline uint32_t ATTRIBUTE_PURE INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_PSliceInterConcealmentMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_PSliceInterConcealmentMode_start 80 #define GFX12_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_PSliceInterConcealmentMode_start 80 #define GFX11_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_PSliceInterConcealmentMode_start 80 #define GFX9_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_PSliceInterConcealmentMode_start 80 #define GFX8_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_PSliceInterConcealmentMode_start 80 #define GFX75_INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_PSliceInterConcealmentMode_start 80 static inline uint32_t ATTRIBUTE_PURE INLINE_DATA_DESCRIPTION_FOR_MFD_AVC_BSD_OBJECT_PSliceInterConcealmentMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 80; case 120: return 80; case 110: return 80; case 90: return 80; case 80: return 80; case 75: return 80; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_1 */ #define GFX125_INSTDONE_1_length 1 #define GFX12_INSTDONE_1_length 1 #define GFX11_INSTDONE_1_length 1 #define GFX9_INSTDONE_1_length 1 #define GFX8_INSTDONE_1_length 1 #define GFX75_INSTDONE_1_length 1 #define GFX7_INSTDONE_1_length 1 #define GFX6_INSTDONE_1_length 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_1::AVS Done */ #define GFX6_INSTDONE_1_AVSDone_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_AVSDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_INSTDONE_1_AVSDone_start 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_AVSDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_1::CL Done */ #define GFX125_INSTDONE_1_CLDone_bits 1 #define GFX12_INSTDONE_1_CLDone_bits 1 #define GFX11_INSTDONE_1_CLDone_bits 1 #define GFX9_INSTDONE_1_CLDone_bits 1 #define GFX8_INSTDONE_1_CLDone_bits 1 #define GFX75_INSTDONE_1_CLDone_bits 1 #define GFX7_INSTDONE_1_CLDone_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_CLDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INSTDONE_1_CLDone_start 8 #define GFX12_INSTDONE_1_CLDone_start 8 #define GFX11_INSTDONE_1_CLDone_start 8 #define GFX9_INSTDONE_1_CLDone_start 8 #define GFX8_INSTDONE_1_CLDone_start 8 #define GFX75_INSTDONE_1_CLDone_start 8 #define GFX7_INSTDONE_1_CLDone_start 8 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_CLDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_1::CS Done */ #define GFX125_INSTDONE_1_CSDone_bits 1 #define GFX12_INSTDONE_1_CSDone_bits 1 #define GFX11_INSTDONE_1_CSDone_bits 1 #define GFX9_INSTDONE_1_CSDone_bits 1 #define GFX8_INSTDONE_1_CSDone_bits 1 #define GFX75_INSTDONE_1_CSDone_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_CSDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INSTDONE_1_CSDone_start 21 #define GFX12_INSTDONE_1_CSDone_start 21 #define GFX11_INSTDONE_1_CSDone_start 21 #define GFX9_INSTDONE_1_CSDone_start 21 #define GFX8_INSTDONE_1_CSDone_start 21 #define GFX75_INSTDONE_1_CSDone_start 21 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_CSDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 21; case 120: return 21; case 110: return 21; case 90: return 21; case 80: return 21; case 75: return 21; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_1::DS Done */ #define GFX125_INSTDONE_1_DSDone_bits 1 #define GFX12_INSTDONE_1_DSDone_bits 1 #define GFX11_INSTDONE_1_DSDone_bits 1 #define GFX9_INSTDONE_1_DSDone_bits 1 #define GFX8_INSTDONE_1_DSDone_bits 1 #define GFX75_INSTDONE_1_DSDone_bits 1 #define GFX7_INSTDONE_1_DSDone_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_DSDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INSTDONE_1_DSDone_start 5 #define GFX12_INSTDONE_1_DSDone_start 5 #define GFX11_INSTDONE_1_DSDone_start 5 #define GFX9_INSTDONE_1_DSDone_start 5 #define GFX8_INSTDONE_1_DSDone_start 5 #define GFX75_INSTDONE_1_DSDone_start 5 #define GFX7_INSTDONE_1_DSDone_start 5 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_DSDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 5; case 110: return 5; case 90: return 5; case 80: return 5; case 75: return 5; case 70: return 5; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_1::EU00 Done */ #define GFX6_INSTDONE_1_EU00Done_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_EU00Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_INSTDONE_1_EU00Done_start 16 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_EU00Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 16; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_1::EU01 Done */ #define GFX6_INSTDONE_1_EU01Done_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_EU01Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_INSTDONE_1_EU01Done_start 17 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_EU01Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 17; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_1::EU02 Done */ #define GFX6_INSTDONE_1_EU02Done_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_EU02Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_INSTDONE_1_EU02Done_start 18 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_EU02Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 18; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_1::EU10 Done */ #define GFX6_INSTDONE_1_EU10Done_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_EU10Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_INSTDONE_1_EU10Done_start 20 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_EU10Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 20; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_1::EU11 Done */ #define GFX6_INSTDONE_1_EU11Done_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_EU11Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_INSTDONE_1_EU11Done_start 21 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_EU11Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 21; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_1::EU12 Done */ #define GFX6_INSTDONE_1_EU12Done_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_EU12Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_INSTDONE_1_EU12Done_start 22 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_EU12Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 22; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_1::EU20 Done */ #define GFX6_INSTDONE_1_EU20Done_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_EU20Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_INSTDONE_1_EU20Done_start 24 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_EU20Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 24; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_1::EU21 Done */ #define GFX6_INSTDONE_1_EU21Done_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_EU21Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_INSTDONE_1_EU21Done_start 25 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_EU21Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 25; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_1::EU22 Done */ #define GFX6_INSTDONE_1_EU22Done_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_EU22Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_INSTDONE_1_EU22Done_start 26 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_EU22Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 26; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_1::EU30 Done */ #define GFX6_INSTDONE_1_EU30Done_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_EU30Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_INSTDONE_1_EU30Done_start 28 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_EU30Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 28; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_1::EU31 Done */ #define GFX6_INSTDONE_1_EU31Done_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_EU31Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_INSTDONE_1_EU31Done_start 29 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_EU31Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 29; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_1::EU32 Done */ #define GFX6_INSTDONE_1_EU32Done_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_EU32Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_INSTDONE_1_EU32Done_start 30 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_EU32Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 30; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_1::GAFM Done */ #define GFX125_INSTDONE_1_GAFMDone_bits 1 #define GFX12_INSTDONE_1_GAFMDone_bits 1 #define GFX11_INSTDONE_1_GAFMDone_bits 1 #define GFX9_INSTDONE_1_GAFMDone_bits 1 #define GFX8_INSTDONE_1_GAFMDone_bits 1 #define GFX75_INSTDONE_1_GAFMDone_bits 1 #define GFX7_INSTDONE_1_GAFMDone_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_GAFMDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INSTDONE_1_GAFMDone_start 18 #define GFX12_INSTDONE_1_GAFMDone_start 18 #define GFX11_INSTDONE_1_GAFMDone_start 18 #define GFX9_INSTDONE_1_GAFMDone_start 18 #define GFX8_INSTDONE_1_GAFMDone_start 18 #define GFX75_INSTDONE_1_GAFMDone_start 18 #define GFX7_INSTDONE_1_GAFMDone_start 18 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_GAFMDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 18; case 120: return 18; case 110: return 18; case 90: return 18; case 80: return 18; case 75: return 18; case 70: return 18; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_1::GAFS Done */ #define GFX125_INSTDONE_1_GAFSDone_bits 1 #define GFX12_INSTDONE_1_GAFSDone_bits 1 #define GFX11_INSTDONE_1_GAFSDone_bits 1 #define GFX9_INSTDONE_1_GAFSDone_bits 1 #define GFX8_INSTDONE_1_GAFSDone_bits 1 #define GFX75_INSTDONE_1_GAFSDone_bits 1 #define GFX7_INSTDONE_1_GAFSDone_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_GAFSDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INSTDONE_1_GAFSDone_start 15 #define GFX12_INSTDONE_1_GAFSDone_start 15 #define GFX11_INSTDONE_1_GAFSDone_start 15 #define GFX9_INSTDONE_1_GAFSDone_start 15 #define GFX8_INSTDONE_1_GAFSDone_start 15 #define GFX75_INSTDONE_1_GAFSDone_start 15 #define GFX7_INSTDONE_1_GAFSDone_start 15 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_GAFSDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 15; case 120: return 15; case 110: return 15; case 90: return 15; case 80: return 15; case 75: return 15; case 70: return 15; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_1::GAM Done */ #define GFX125_INSTDONE_1_GAMDone_bits 1 #define GFX12_INSTDONE_1_GAMDone_bits 1 #define GFX11_INSTDONE_1_GAMDone_bits 1 #define GFX9_INSTDONE_1_GAMDone_bits 1 #define GFX8_INSTDONE_1_GAMDone_bits 1 #define GFX75_INSTDONE_1_GAMDone_bits 1 #define GFX7_INSTDONE_1_GAMDone_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_GAMDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INSTDONE_1_GAMDone_start 19 #define GFX12_INSTDONE_1_GAMDone_start 19 #define GFX11_INSTDONE_1_GAMDone_start 19 #define GFX9_INSTDONE_1_GAMDone_start 19 #define GFX8_INSTDONE_1_GAMDone_start 19 #define GFX75_INSTDONE_1_GAMDone_start 19 #define GFX7_INSTDONE_1_GAMDone_start 19 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_GAMDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 19; case 120: return 19; case 110: return 19; case 90: return 19; case 80: return 19; case 75: return 19; case 70: return 19; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_1::GS Done */ #define GFX125_INSTDONE_1_GSDone_bits 1 #define GFX12_INSTDONE_1_GSDone_bits 1 #define GFX11_INSTDONE_1_GSDone_bits 1 #define GFX9_INSTDONE_1_GSDone_bits 1 #define GFX8_INSTDONE_1_GSDone_bits 1 #define GFX75_INSTDONE_1_GSDone_bits 1 #define GFX7_INSTDONE_1_GSDone_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_GSDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INSTDONE_1_GSDone_start 6 #define GFX12_INSTDONE_1_GSDone_start 6 #define GFX11_INSTDONE_1_GSDone_start 6 #define GFX9_INSTDONE_1_GSDone_start 6 #define GFX8_INSTDONE_1_GSDone_start 6 #define GFX75_INSTDONE_1_GSDone_start 6 #define GFX7_INSTDONE_1_GSDone_start 6 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_GSDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 6; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_1::GW Done */ #define GFX6_INSTDONE_1_GWDone_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_GWDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_INSTDONE_1_GWDone_start 3 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_GWDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_1::HIZ Done */ #define GFX6_INSTDONE_1_HIZDone_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_HIZDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_INSTDONE_1_HIZDone_start 2 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_HIZDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_1::HS Done */ #define GFX125_INSTDONE_1_HSDone_bits 1 #define GFX12_INSTDONE_1_HSDone_bits 1 #define GFX11_INSTDONE_1_HSDone_bits 1 #define GFX9_INSTDONE_1_HSDone_bits 1 #define GFX8_INSTDONE_1_HSDone_bits 1 #define GFX75_INSTDONE_1_HSDone_bits 1 #define GFX7_INSTDONE_1_HSDone_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_HSDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INSTDONE_1_HSDone_start 3 #define GFX12_INSTDONE_1_HSDone_start 3 #define GFX11_INSTDONE_1_HSDone_start 3 #define GFX9_INSTDONE_1_HSDone_start 3 #define GFX8_INSTDONE_1_HSDone_start 3 #define GFX75_INSTDONE_1_HSDone_start 3 #define GFX7_INSTDONE_1_HSDone_start 3 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_HSDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_1::IC0 Done */ #define GFX6_INSTDONE_1_IC0Done_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_IC0Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_INSTDONE_1_IC0Done_start 12 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_IC0Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 12; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_1::IC1 Done */ #define GFX6_INSTDONE_1_IC1Done_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_IC1Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_INSTDONE_1_IC1Done_start 13 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_IC1Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 13; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_1::IC2 Done */ #define GFX6_INSTDONE_1_IC2Done_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_IC2Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_INSTDONE_1_IC2Done_start 14 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_IC2Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 14; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_1::IC3 Done */ #define GFX6_INSTDONE_1_IC3Done_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_IC3Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_INSTDONE_1_IC3Done_start 15 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_IC3Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 15; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_1::IEF Done */ #define GFX6_INSTDONE_1_IEFDone_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_IEFDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_INSTDONE_1_IEFDone_start 8 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_IEFDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_1::ISC1/0 Done */ #define GFX6_INSTDONE_1_ISC10Done_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_ISC10Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_INSTDONE_1_ISC10Done_start 11 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_ISC10Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 11; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_1::ISC2/3 Done */ #define GFX6_INSTDONE_1_ISC23Done_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_ISC23Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_INSTDONE_1_ISC23Done_start 10 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_ISC23Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 10; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_1::MA0 Done */ #define GFX6_INSTDONE_1_MA0Done_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_MA0Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_INSTDONE_1_MA0Done_start 19 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_MA0Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 19; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_1::MA1 Done */ #define GFX6_INSTDONE_1_MA1Done_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_MA1Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_INSTDONE_1_MA1Done_start 23 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_MA1Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 23; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_1::MA2 Done */ #define GFX6_INSTDONE_1_MA2Done_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_MA2Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_INSTDONE_1_MA2Done_start 27 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_MA2Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 27; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_1::MA3 Done */ #define GFX6_INSTDONE_1_MA3Done_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_MA3Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_INSTDONE_1_MA3Done_start 31 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_MA3Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 31; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_1::PRB0 Ring Enable */ #define GFX125_INSTDONE_1_PRB0RingEnable_bits 1 #define GFX12_INSTDONE_1_PRB0RingEnable_bits 1 #define GFX11_INSTDONE_1_PRB0RingEnable_bits 1 #define GFX9_INSTDONE_1_PRB0RingEnable_bits 1 #define GFX8_INSTDONE_1_PRB0RingEnable_bits 1 #define GFX75_INSTDONE_1_PRB0RingEnable_bits 1 #define GFX7_INSTDONE_1_PRB0RingEnable_bits 1 #define GFX6_INSTDONE_1_PRB0RingEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_PRB0RingEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INSTDONE_1_PRB0RingEnable_start 0 #define GFX12_INSTDONE_1_PRB0RingEnable_start 0 #define GFX11_INSTDONE_1_PRB0RingEnable_start 0 #define GFX9_INSTDONE_1_PRB0RingEnable_start 0 #define GFX8_INSTDONE_1_PRB0RingEnable_start 0 #define GFX75_INSTDONE_1_PRB0RingEnable_start 0 #define GFX7_INSTDONE_1_PRB0RingEnable_start 0 #define GFX6_INSTDONE_1_PRB0RingEnable_start 0 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_PRB0RingEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_1::RCCFBC CS Done */ #define GFX125_INSTDONE_1_RCCFBCCSDone_bits 1 #define GFX12_INSTDONE_1_RCCFBCCSDone_bits 1 #define GFX11_INSTDONE_1_RCCFBCCSDone_bits 1 #define GFX9_INSTDONE_1_RCCFBCCSDone_bits 1 #define GFX8_INSTDONE_1_RCCFBCCSDone_bits 1 #define GFX75_INSTDONE_1_RCCFBCCSDone_bits 1 #define GFX7_INSTDONE_1_RCCFBCCSDone_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_RCCFBCCSDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INSTDONE_1_RCCFBCCSDone_start 23 #define GFX12_INSTDONE_1_RCCFBCCSDone_start 23 #define GFX11_INSTDONE_1_RCCFBCCSDone_start 23 #define GFX9_INSTDONE_1_RCCFBCCSDone_start 23 #define GFX8_INSTDONE_1_RCCFBCCSDone_start 23 #define GFX75_INSTDONE_1_RCCFBCCSDone_start 23 #define GFX7_INSTDONE_1_RCCFBCCSDone_start 23 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_RCCFBCCSDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 23; case 120: return 23; case 110: return 23; case 90: return 23; case 80: return 23; case 75: return 23; case 70: return 23; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_1::RS Done */ #define GFX125_INSTDONE_1_RSDone_bits 1 #define GFX12_INSTDONE_1_RSDone_bits 1 #define GFX11_INSTDONE_1_RSDone_bits 1 #define GFX9_INSTDONE_1_RSDone_bits 1 #define GFX8_INSTDONE_1_RSDone_bits 1 #define GFX75_INSTDONE_1_RSDone_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_RSDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INSTDONE_1_RSDone_start 20 #define GFX12_INSTDONE_1_RSDone_start 20 #define GFX11_INSTDONE_1_RSDone_start 20 #define GFX9_INSTDONE_1_RSDone_start 20 #define GFX8_INSTDONE_1_RSDone_start 20 #define GFX75_INSTDONE_1_RSDone_start 20 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_RSDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 20; case 120: return 20; case 110: return 20; case 90: return 20; case 80: return 20; case 75: return 20; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_1::SDE Done */ #define GFX125_INSTDONE_1_SDEDone_bits 1 #define GFX12_INSTDONE_1_SDEDone_bits 1 #define GFX11_INSTDONE_1_SDEDone_bits 1 #define GFX9_INSTDONE_1_SDEDone_bits 1 #define GFX8_INSTDONE_1_SDEDone_bits 1 #define GFX75_INSTDONE_1_SDEDone_bits 1 #define GFX7_INSTDONE_1_SDEDone_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_SDEDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INSTDONE_1_SDEDone_start 22 #define GFX12_INSTDONE_1_SDEDone_start 22 #define GFX11_INSTDONE_1_SDEDone_start 22 #define GFX9_INSTDONE_1_SDEDone_start 22 #define GFX8_INSTDONE_1_SDEDone_start 22 #define GFX75_INSTDONE_1_SDEDone_start 22 #define GFX7_INSTDONE_1_SDEDone_start 22 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_SDEDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 22; case 120: return 22; case 110: return 22; case 90: return 22; case 80: return 22; case 75: return 22; case 70: return 22; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_1::SF Done */ #define GFX125_INSTDONE_1_SFDone_bits 1 #define GFX12_INSTDONE_1_SFDone_bits 1 #define GFX11_INSTDONE_1_SFDone_bits 1 #define GFX9_INSTDONE_1_SFDone_bits 1 #define GFX8_INSTDONE_1_SFDone_bits 1 #define GFX75_INSTDONE_1_SFDone_bits 1 #define GFX7_INSTDONE_1_SFDone_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_SFDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INSTDONE_1_SFDone_start 9 #define GFX12_INSTDONE_1_SFDone_start 9 #define GFX11_INSTDONE_1_SFDone_start 9 #define GFX9_INSTDONE_1_SFDone_start 9 #define GFX8_INSTDONE_1_SFDone_start 9 #define GFX75_INSTDONE_1_SFDone_start 9 #define GFX7_INSTDONE_1_SFDone_start 9 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_SFDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 9; case 120: return 9; case 110: return 9; case 90: return 9; case 80: return 9; case 75: return 9; case 70: return 9; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_1::SOL Done */ #define GFX125_INSTDONE_1_SOLDone_bits 1 #define GFX12_INSTDONE_1_SOLDone_bits 1 #define GFX11_INSTDONE_1_SOLDone_bits 1 #define GFX9_INSTDONE_1_SOLDone_bits 1 #define GFX8_INSTDONE_1_SOLDone_bits 1 #define GFX75_INSTDONE_1_SOLDone_bits 1 #define GFX7_INSTDONE_1_SOLDone_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_SOLDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INSTDONE_1_SOLDone_start 7 #define GFX12_INSTDONE_1_SOLDone_start 7 #define GFX11_INSTDONE_1_SOLDone_start 7 #define GFX9_INSTDONE_1_SOLDone_start 7 #define GFX8_INSTDONE_1_SOLDone_start 7 #define GFX75_INSTDONE_1_SOLDone_start 7 #define GFX7_INSTDONE_1_SOLDone_start 7 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_SOLDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 7; case 120: return 7; case 110: return 7; case 90: return 7; case 80: return 7; case 75: return 7; case 70: return 7; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_1::SVG Done */ #define GFX125_INSTDONE_1_SVGDone_bits 1 #define GFX12_INSTDONE_1_SVGDone_bits 1 #define GFX11_INSTDONE_1_SVGDone_bits 1 #define GFX9_INSTDONE_1_SVGDone_bits 1 #define GFX8_INSTDONE_1_SVGDone_bits 1 #define GFX75_INSTDONE_1_SVGDone_bits 1 #define GFX7_INSTDONE_1_SVGDone_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_SVGDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INSTDONE_1_SVGDone_start 14 #define GFX12_INSTDONE_1_SVGDone_start 14 #define GFX11_INSTDONE_1_SVGDone_start 14 #define GFX9_INSTDONE_1_SVGDone_start 14 #define GFX8_INSTDONE_1_SVGDone_start 14 #define GFX75_INSTDONE_1_SVGDone_start 14 #define GFX7_INSTDONE_1_SVGDone_start 14 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_SVGDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 14; case 120: return 14; case 110: return 14; case 90: return 14; case 80: return 14; case 75: return 14; case 70: return 14; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_1::TD Done */ #define GFX6_INSTDONE_1_TDDone_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_TDDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_INSTDONE_1_TDDone_start 6 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_TDDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 6; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_1::TDG0 Done */ #define GFX125_INSTDONE_1_TDG0Done_bits 1 #define GFX12_INSTDONE_1_TDG0Done_bits 1 #define GFX11_INSTDONE_1_TDG0Done_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_TDG0Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INSTDONE_1_TDG0Done_start 12 #define GFX12_INSTDONE_1_TDG0Done_start 12 #define GFX11_INSTDONE_1_TDG0Done_start 12 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_TDG0Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 12; case 120: return 12; case 110: return 12; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_1::TDG1 Done */ #define GFX125_INSTDONE_1_TDG1Done_bits 1 #define GFX12_INSTDONE_1_TDG1Done_bits 1 #define GFX11_INSTDONE_1_TDG1Done_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_TDG1Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INSTDONE_1_TDG1Done_start 11 #define GFX12_INSTDONE_1_TDG1Done_start 11 #define GFX11_INSTDONE_1_TDG1Done_start 11 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_TDG1Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 11; case 120: return 11; case 110: return 11; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_1::TDG Done */ #define GFX9_INSTDONE_1_TDGDone_bits 1 #define GFX8_INSTDONE_1_TDGDone_bits 1 #define GFX75_INSTDONE_1_TDGDone_bits 1 #define GFX7_INSTDONE_1_TDGDone_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_TDGDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_INSTDONE_1_TDGDone_start 12 #define GFX8_INSTDONE_1_TDGDone_start 12 #define GFX75_INSTDONE_1_TDGDone_start 12 #define GFX7_INSTDONE_1_TDGDone_start 12 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_TDGDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 12; case 80: return 12; case 75: return 12; case 70: return 12; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_1::TE Done */ #define GFX125_INSTDONE_1_TEDone_bits 1 #define GFX12_INSTDONE_1_TEDone_bits 1 #define GFX11_INSTDONE_1_TEDone_bits 1 #define GFX9_INSTDONE_1_TEDone_bits 1 #define GFX8_INSTDONE_1_TEDone_bits 1 #define GFX75_INSTDONE_1_TEDone_bits 1 #define GFX7_INSTDONE_1_TEDone_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_TEDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INSTDONE_1_TEDone_start 4 #define GFX12_INSTDONE_1_TEDone_start 4 #define GFX11_INSTDONE_1_TEDone_start 4 #define GFX9_INSTDONE_1_TEDone_start 4 #define GFX8_INSTDONE_1_TEDone_start 4 #define GFX75_INSTDONE_1_TEDone_start 4 #define GFX7_INSTDONE_1_TEDone_start 4 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_TEDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 4; case 70: return 4; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_1::TS Done */ #define GFX6_INSTDONE_1_TSDone_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_TSDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_INSTDONE_1_TSDone_start 4 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_TSDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_1::TSG0 Done */ #define GFX125_INSTDONE_1_TSG0Done_bits 1 #define GFX12_INSTDONE_1_TSG0Done_bits 1 #define GFX11_INSTDONE_1_TSG0Done_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_TSG0Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INSTDONE_1_TSG0Done_start 17 #define GFX12_INSTDONE_1_TSG0Done_start 17 #define GFX11_INSTDONE_1_TSG0Done_start 17 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_TSG0Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 17; case 120: return 17; case 110: return 17; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_1::TSG1 Done */ #define GFX125_INSTDONE_1_TSG1Done_bits 1 #define GFX12_INSTDONE_1_TSG1Done_bits 1 #define GFX11_INSTDONE_1_TSG1Done_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_TSG1Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INSTDONE_1_TSG1Done_start 24 #define GFX12_INSTDONE_1_TSG1Done_start 24 #define GFX11_INSTDONE_1_TSG1Done_start 24 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_TSG1Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_1::TSG Done */ #define GFX9_INSTDONE_1_TSGDone_bits 1 #define GFX8_INSTDONE_1_TSGDone_bits 1 #define GFX75_INSTDONE_1_TSGDone_bits 1 #define GFX7_INSTDONE_1_TSGDone_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_TSGDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_INSTDONE_1_TSGDone_start 17 #define GFX8_INSTDONE_1_TSGDone_start 17 #define GFX75_INSTDONE_1_TSGDone_start 17 #define GFX7_INSTDONE_1_TSGDone_start 17 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_TSGDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 17; case 80: return 17; case 75: return 17; case 70: return 17; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_1::URBM Done */ #define GFX125_INSTDONE_1_URBMDone_bits 1 #define GFX12_INSTDONE_1_URBMDone_bits 1 #define GFX11_INSTDONE_1_URBMDone_bits 1 #define GFX9_INSTDONE_1_URBMDone_bits 1 #define GFX8_INSTDONE_1_URBMDone_bits 1 #define GFX75_INSTDONE_1_URBMDone_bits 1 #define GFX7_INSTDONE_1_URBMDone_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_URBMDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INSTDONE_1_URBMDone_start 13 #define GFX12_INSTDONE_1_URBMDone_start 13 #define GFX11_INSTDONE_1_URBMDone_start 13 #define GFX9_INSTDONE_1_URBMDone_start 13 #define GFX8_INSTDONE_1_URBMDone_start 13 #define GFX75_INSTDONE_1_URBMDone_start 13 #define GFX7_INSTDONE_1_URBMDone_start 13 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_URBMDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 13; case 120: return 13; case 110: return 13; case 90: return 13; case 80: return 13; case 75: return 13; case 70: return 13; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_1::VFE Done */ #define GFX125_INSTDONE_1_VFEDone_bits 1 #define GFX12_INSTDONE_1_VFEDone_bits 1 #define GFX11_INSTDONE_1_VFEDone_bits 1 #define GFX9_INSTDONE_1_VFEDone_bits 1 #define GFX8_INSTDONE_1_VFEDone_bits 1 #define GFX75_INSTDONE_1_VFEDone_bits 1 #define GFX7_INSTDONE_1_VFEDone_bits 1 #define GFX6_INSTDONE_1_VFEDone_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_VFEDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INSTDONE_1_VFEDone_start 16 #define GFX12_INSTDONE_1_VFEDone_start 16 #define GFX11_INSTDONE_1_VFEDone_start 16 #define GFX9_INSTDONE_1_VFEDone_start 16 #define GFX8_INSTDONE_1_VFEDone_start 16 #define GFX75_INSTDONE_1_VFEDone_start 16 #define GFX7_INSTDONE_1_VFEDone_start 16 #define GFX6_INSTDONE_1_VFEDone_start 7 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_VFEDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 7; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_1::VFG Done */ #define GFX125_INSTDONE_1_VFGDone_bits 1 #define GFX12_INSTDONE_1_VFGDone_bits 1 #define GFX11_INSTDONE_1_VFGDone_bits 1 #define GFX9_INSTDONE_1_VFGDone_bits 1 #define GFX8_INSTDONE_1_VFGDone_bits 1 #define GFX75_INSTDONE_1_VFGDone_bits 1 #define GFX7_INSTDONE_1_VFGDone_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_VFGDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INSTDONE_1_VFGDone_start 1 #define GFX12_INSTDONE_1_VFGDone_start 1 #define GFX11_INSTDONE_1_VFGDone_start 1 #define GFX9_INSTDONE_1_VFGDone_start 1 #define GFX8_INSTDONE_1_VFGDone_start 1 #define GFX75_INSTDONE_1_VFGDone_start 1 #define GFX7_INSTDONE_1_VFGDone_start 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_VFGDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_1::VSC Done */ #define GFX6_INSTDONE_1_VSCDone_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_VSCDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_INSTDONE_1_VSCDone_start 9 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_VSCDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 9; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_1::VS Done */ #define GFX125_INSTDONE_1_VSDone_bits 1 #define GFX12_INSTDONE_1_VSDone_bits 1 #define GFX11_INSTDONE_1_VSDone_bits 1 #define GFX9_INSTDONE_1_VSDone_bits 1 #define GFX8_INSTDONE_1_VSDone_bits 1 #define GFX75_INSTDONE_1_VSDone_bits 1 #define GFX7_INSTDONE_1_VSDone_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_VSDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INSTDONE_1_VSDone_start 2 #define GFX12_INSTDONE_1_VSDone_start 2 #define GFX11_INSTDONE_1_VSDone_start 2 #define GFX9_INSTDONE_1_VSDone_start 2 #define GFX8_INSTDONE_1_VSDone_start 2 #define GFX75_INSTDONE_1_VSDone_start 2 #define GFX7_INSTDONE_1_VSDone_start 2 static inline uint32_t ATTRIBUTE_PURE INSTDONE_1_VSDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_2 */ #define GFX6_INSTDONE_2_length 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_2_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_2::CL Done */ #define GFX6_INSTDONE_2_CLDone_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_2_CLDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_INSTDONE_2_CLDone_start 3 static inline uint32_t ATTRIBUTE_PURE INSTDONE_2_CLDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_2::CS Done */ #define GFX6_INSTDONE_2_CSDone_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_2_CSDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_INSTDONE_2_CSDone_start 30 static inline uint32_t ATTRIBUTE_PURE INSTDONE_2_CSDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 30; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_2::DAP Done */ #define GFX6_INSTDONE_2_DAPDone_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_2_DAPDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_INSTDONE_2_DAPDone_start 19 static inline uint32_t ATTRIBUTE_PURE INSTDONE_2_DAPDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 19; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_2::DG Done */ #define GFX6_INSTDONE_2_DGDone_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_2_DGDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_INSTDONE_2_DGDone_start 9 static inline uint32_t ATTRIBUTE_PURE INSTDONE_2_DGDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 9; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_2::DM Done */ #define GFX6_INSTDONE_2_DMDone_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_2_DMDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_INSTDONE_2_DMDone_start 11 static inline uint32_t ATTRIBUTE_PURE INSTDONE_2_DMDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 11; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_2::FL Done */ #define GFX6_INSTDONE_2_FLDone_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_2_FLDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_INSTDONE_2_FLDone_start 13 static inline uint32_t ATTRIBUTE_PURE INSTDONE_2_FLDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 13; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_2::FT Done */ #define GFX6_INSTDONE_2_FTDone_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_2_FTDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_INSTDONE_2_FTDone_start 10 static inline uint32_t ATTRIBUTE_PURE INSTDONE_2_FTDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 10; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_2::GAM Done */ #define GFX6_INSTDONE_2_GAMDone_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_2_GAMDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_INSTDONE_2_GAMDone_start 31 static inline uint32_t ATTRIBUTE_PURE INSTDONE_2_GAMDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 31; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_2::GS Done */ #define GFX6_INSTDONE_2_GSDone_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_2_GSDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_INSTDONE_2_GSDone_start 2 static inline uint32_t ATTRIBUTE_PURE INSTDONE_2_GSDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_2::ISC Done */ #define GFX6_INSTDONE_2_ISCDone_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_2_ISCDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_INSTDONE_2_ISCDone_start 25 static inline uint32_t ATTRIBUTE_PURE INSTDONE_2_ISCDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 25; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_2::IZ Done */ #define GFX6_INSTDONE_2_IZDone_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_2_IZDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_INSTDONE_2_IZDone_start 17 static inline uint32_t ATTRIBUTE_PURE INSTDONE_2_IZDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 17; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_2::MT Done */ #define GFX6_INSTDONE_2_MTDone_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_2_MTDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_INSTDONE_2_MTDone_start 24 static inline uint32_t ATTRIBUTE_PURE INSTDONE_2_MTDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 24; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_2::PL Done */ #define GFX6_INSTDONE_2_PLDone_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_2_PLDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_INSTDONE_2_PLDone_start 6 static inline uint32_t ATTRIBUTE_PURE INSTDONE_2_PLDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 6; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_2::PSD Done */ #define GFX6_INSTDONE_2_PSDDone_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_2_PSDDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_INSTDONE_2_PSDDone_start 18 static inline uint32_t ATTRIBUTE_PURE INSTDONE_2_PSDDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 18; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_2::QC Done */ #define GFX6_INSTDONE_2_QCDone_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_2_QCDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_INSTDONE_2_QCDone_start 14 static inline uint32_t ATTRIBUTE_PURE INSTDONE_2_QCDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 14; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_2::RCC Done */ #define GFX6_INSTDONE_2_RCCDone_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_2_RCCDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_INSTDONE_2_RCCDone_start 27 static inline uint32_t ATTRIBUTE_PURE INSTDONE_2_RCCDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 27; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_2::RCPBE Done */ #define GFX6_INSTDONE_2_RCPBEDone_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_2_RCPBEDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_INSTDONE_2_RCPBEDone_start 22 static inline uint32_t ATTRIBUTE_PURE INSTDONE_2_RCPBEDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 22; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_2::RCPFE Done */ #define GFX6_INSTDONE_2_RCPFEDone_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_2_RCPFEDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_INSTDONE_2_RCPFEDone_start 23 static inline uint32_t ATTRIBUTE_PURE INSTDONE_2_RCPFEDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 23; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_2::RCZ Done */ #define GFX6_INSTDONE_2_RCZDone_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_2_RCZDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_INSTDONE_2_RCZDone_start 20 static inline uint32_t ATTRIBUTE_PURE INSTDONE_2_RCZDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 20; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_2::SC Done */ #define GFX6_INSTDONE_2_SCDone_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_2_SCDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_INSTDONE_2_SCDone_start 12 static inline uint32_t ATTRIBUTE_PURE INSTDONE_2_SCDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 12; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_2::SF Done */ #define GFX6_INSTDONE_2_SFDone_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_2_SFDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_INSTDONE_2_SFDone_start 4 static inline uint32_t ATTRIBUTE_PURE INSTDONE_2_SFDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_2::SI Done */ #define GFX6_INSTDONE_2_SIDone_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_2_SIDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_INSTDONE_2_SIDone_start 8 static inline uint32_t ATTRIBUTE_PURE INSTDONE_2_SIDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_2::SO Done */ #define GFX6_INSTDONE_2_SODone_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_2_SODone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_INSTDONE_2_SODone_start 7 static inline uint32_t ATTRIBUTE_PURE INSTDONE_2_SODone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 7; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_2::SVG Done */ #define GFX6_INSTDONE_2_SVGDone_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_2_SVGDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_INSTDONE_2_SVGDone_start 26 static inline uint32_t ATTRIBUTE_PURE INSTDONE_2_SVGDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 26; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_2::SVRW Done */ #define GFX6_INSTDONE_2_SVRWDone_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_2_SVRWDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_INSTDONE_2_SVRWDone_start 28 static inline uint32_t ATTRIBUTE_PURE INSTDONE_2_SVRWDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 28; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_2::SVSM Done */ #define GFX6_INSTDONE_2_SVSMDone_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_2_SVSMDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_INSTDONE_2_SVSMDone_start 15 static inline uint32_t ATTRIBUTE_PURE INSTDONE_2_SVSMDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 15; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_2::VDI Done */ #define GFX6_INSTDONE_2_VDIDone_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_2_VDIDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_INSTDONE_2_VDIDone_start 21 static inline uint32_t ATTRIBUTE_PURE INSTDONE_2_VDIDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 21; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_2::VF Done */ #define GFX6_INSTDONE_2_VFDone_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_2_VFDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_INSTDONE_2_VFDone_start 0 static inline uint32_t ATTRIBUTE_PURE INSTDONE_2_VFDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_2::VME Done */ #define GFX6_INSTDONE_2_VMEDone_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_2_VMEDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_INSTDONE_2_VMEDone_start 5 static inline uint32_t ATTRIBUTE_PURE INSTDONE_2_VMEDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 5; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_2::VS0 Done */ #define GFX6_INSTDONE_2_VS0Done_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_2_VS0Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_INSTDONE_2_VS0Done_start 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_2_VS0Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_2::WMBE Done */ #define GFX6_INSTDONE_2_WMBEDone_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_2_WMBEDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_INSTDONE_2_WMBEDone_start 29 static inline uint32_t ATTRIBUTE_PURE INSTDONE_2_WMBEDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 29; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_2::WMFE Done */ #define GFX6_INSTDONE_2_WMFEDone_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_2_WMFEDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_INSTDONE_2_WMFEDone_start 16 static inline uint32_t ATTRIBUTE_PURE INSTDONE_2_WMFEDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 16; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_GEOM */ #define GFX125_INSTDONE_GEOM_length 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_GEOM_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_GEOM::CL Done */ #define GFX125_INSTDONE_GEOM_CLDone_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_GEOM_CLDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INSTDONE_GEOM_CLDone_start 8 static inline uint32_t ATTRIBUTE_PURE INSTDONE_GEOM_CLDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_GEOM::DS Done */ #define GFX125_INSTDONE_GEOM_DSDone_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_GEOM_DSDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INSTDONE_GEOM_DSDone_start 5 static inline uint32_t ATTRIBUTE_PURE INSTDONE_GEOM_DSDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_GEOM::GS Done */ #define GFX125_INSTDONE_GEOM_GSDone_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_GEOM_GSDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INSTDONE_GEOM_GSDone_start 6 static inline uint32_t ATTRIBUTE_PURE INSTDONE_GEOM_GSDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_GEOM::HS Done */ #define GFX125_INSTDONE_GEOM_HSDone_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_GEOM_HSDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INSTDONE_GEOM_HSDone_start 3 static inline uint32_t ATTRIBUTE_PURE INSTDONE_GEOM_HSDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_GEOM::SDE Done */ #define GFX125_INSTDONE_GEOM_SDEDone_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_GEOM_SDEDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INSTDONE_GEOM_SDEDone_start 22 static inline uint32_t ATTRIBUTE_PURE INSTDONE_GEOM_SDEDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 22; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_GEOM::SF Done */ #define GFX125_INSTDONE_GEOM_SFDone_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_GEOM_SFDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INSTDONE_GEOM_SFDone_start 9 static inline uint32_t ATTRIBUTE_PURE INSTDONE_GEOM_SFDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 9; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_GEOM::SOL Done */ #define GFX125_INSTDONE_GEOM_SOLDone_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_GEOM_SOLDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INSTDONE_GEOM_SOLDone_start 7 static inline uint32_t ATTRIBUTE_PURE INSTDONE_GEOM_SOLDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 7; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_GEOM::SVG Done */ #define GFX125_INSTDONE_GEOM_SVGDone_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_GEOM_SVGDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INSTDONE_GEOM_SVGDone_start 14 static inline uint32_t ATTRIBUTE_PURE INSTDONE_GEOM_SVGDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 14; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_GEOM::TDG1 Done */ #define GFX125_INSTDONE_GEOM_TDG1Done_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_GEOM_TDG1Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INSTDONE_GEOM_TDG1Done_start 11 static inline uint32_t ATTRIBUTE_PURE INSTDONE_GEOM_TDG1Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 11; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_GEOM::TE Done */ #define GFX125_INSTDONE_GEOM_TEDone_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_GEOM_TEDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INSTDONE_GEOM_TEDone_start 4 static inline uint32_t ATTRIBUTE_PURE INSTDONE_GEOM_TEDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_GEOM::TSG0 Done */ #define GFX125_INSTDONE_GEOM_TSG0Done_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_GEOM_TSG0Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INSTDONE_GEOM_TSG0Done_start 17 static inline uint32_t ATTRIBUTE_PURE INSTDONE_GEOM_TSG0Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 17; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_GEOM::URBM Done */ #define GFX125_INSTDONE_GEOM_URBMDone_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_GEOM_URBMDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INSTDONE_GEOM_URBMDone_start 13 static inline uint32_t ATTRIBUTE_PURE INSTDONE_GEOM_URBMDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 13; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_GEOM::VFL Done */ #define GFX125_INSTDONE_GEOM_VFLDone_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_GEOM_VFLDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INSTDONE_GEOM_VFLDone_start 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_GEOM_VFLDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTDONE_GEOM::VS Done */ #define GFX125_INSTDONE_GEOM_VSDone_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTDONE_GEOM_VSDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INSTDONE_GEOM_VSDone_start 2 static inline uint32_t ATTRIBUTE_PURE INSTDONE_GEOM_VSDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTPM */ #define GFX8_INSTPM_length 1 #define GFX75_INSTPM_length 1 #define GFX7_INSTPM_length 1 #define GFX6_INSTPM_length 1 static inline uint32_t ATTRIBUTE_PURE INSTPM_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTPM::3D Rendering Instruction Disable */ #define GFX8_INSTPM_3DRenderingInstructionDisable_bits 1 #define GFX75_INSTPM_3DRenderingInstructionDisable_bits 1 #define GFX7_INSTPM_3DRenderingInstructionDisable_bits 1 #define GFX6_INSTPM_3DRenderingInstructionDisable_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTPM_3DRenderingInstructionDisable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX8_INSTPM_3DRenderingInstructionDisable_start 2 #define GFX75_INSTPM_3DRenderingInstructionDisable_start 2 #define GFX7_INSTPM_3DRenderingInstructionDisable_start 2 #define GFX6_INSTPM_3DRenderingInstructionDisable_start 2 static inline uint32_t ATTRIBUTE_PURE INSTPM_3DRenderingInstructionDisable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTPM::3D Rendering Instruction Disable Mask */ #define GFX8_INSTPM_3DRenderingInstructionDisableMask_bits 1 #define GFX75_INSTPM_3DRenderingInstructionDisableMask_bits 1 #define GFX7_INSTPM_3DRenderingInstructionDisableMask_bits 1 #define GFX6_INSTPM_3DRenderingInstructionDisableMask_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTPM_3DRenderingInstructionDisableMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX8_INSTPM_3DRenderingInstructionDisableMask_start 18 #define GFX75_INSTPM_3DRenderingInstructionDisableMask_start 18 #define GFX7_INSTPM_3DRenderingInstructionDisableMask_start 18 #define GFX6_INSTPM_3DRenderingInstructionDisableMask_start 18 static inline uint32_t ATTRIBUTE_PURE INSTPM_3DRenderingInstructionDisableMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 18; case 75: return 18; case 70: return 18; case 60: return 18; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTPM::3D State Instruction Disable */ #define GFX8_INSTPM_3DStateInstructionDisable_bits 1 #define GFX75_INSTPM_3DStateInstructionDisable_bits 1 #define GFX7_INSTPM_3DStateInstructionDisable_bits 1 #define GFX6_INSTPM_3DStateInstructionDisable_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTPM_3DStateInstructionDisable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX8_INSTPM_3DStateInstructionDisable_start 1 #define GFX75_INSTPM_3DStateInstructionDisable_start 1 #define GFX7_INSTPM_3DStateInstructionDisable_start 1 #define GFX6_INSTPM_3DStateInstructionDisable_start 1 static inline uint32_t ATTRIBUTE_PURE INSTPM_3DStateInstructionDisable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTPM::3D State Instruction Disable Mask */ #define GFX8_INSTPM_3DStateInstructionDisableMask_bits 1 #define GFX75_INSTPM_3DStateInstructionDisableMask_bits 1 #define GFX7_INSTPM_3DStateInstructionDisableMask_bits 1 #define GFX6_INSTPM_3DStateInstructionDisableMask_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTPM_3DStateInstructionDisableMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX8_INSTPM_3DStateInstructionDisableMask_start 17 #define GFX75_INSTPM_3DStateInstructionDisableMask_start 17 #define GFX7_INSTPM_3DStateInstructionDisableMask_start 17 #define GFX6_INSTPM_3DStateInstructionDisableMask_start 17 static inline uint32_t ATTRIBUTE_PURE INSTPM_3DStateInstructionDisableMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 17; case 75: return 17; case 70: return 17; case 60: return 17; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTPM::CONSTANT_BUFFER Address Offset Disable */ #define GFX8_INSTPM_CONSTANT_BUFFERAddressOffsetDisable_bits 1 #define GFX75_INSTPM_CONSTANT_BUFFERAddressOffsetDisable_bits 1 #define GFX7_INSTPM_CONSTANT_BUFFERAddressOffsetDisable_bits 1 #define GFX6_INSTPM_CONSTANT_BUFFERAddressOffsetDisable_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTPM_CONSTANT_BUFFERAddressOffsetDisable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX8_INSTPM_CONSTANT_BUFFERAddressOffsetDisable_start 6 #define GFX75_INSTPM_CONSTANT_BUFFERAddressOffsetDisable_start 6 #define GFX7_INSTPM_CONSTANT_BUFFERAddressOffsetDisable_start 6 #define GFX6_INSTPM_CONSTANT_BUFFERAddressOffsetDisable_start 6 static inline uint32_t ATTRIBUTE_PURE INSTPM_CONSTANT_BUFFERAddressOffsetDisable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 6; case 75: return 6; case 70: return 6; case 60: return 6; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTPM::CONSTANT_BUFFER Address Offset Disable Mask */ #define GFX8_INSTPM_CONSTANT_BUFFERAddressOffsetDisableMask_bits 1 #define GFX75_INSTPM_CONSTANT_BUFFERAddressOffsetDisableMask_bits 1 #define GFX7_INSTPM_CONSTANT_BUFFERAddressOffsetDisableMask_bits 1 #define GFX6_INSTPM_CONSTANT_BUFFERAddressOffsetDisableMask_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTPM_CONSTANT_BUFFERAddressOffsetDisableMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX8_INSTPM_CONSTANT_BUFFERAddressOffsetDisableMask_start 22 #define GFX75_INSTPM_CONSTANT_BUFFERAddressOffsetDisableMask_start 22 #define GFX7_INSTPM_CONSTANT_BUFFERAddressOffsetDisableMask_start 22 #define GFX6_INSTPM_CONSTANT_BUFFERAddressOffsetDisableMask_start 22 static inline uint32_t ATTRIBUTE_PURE INSTPM_CONSTANT_BUFFERAddressOffsetDisableMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 22; case 75: return 22; case 70: return 22; case 60: return 22; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTPM::Media Instruction Disable */ #define GFX8_INSTPM_MediaInstructionDisable_bits 1 #define GFX75_INSTPM_MediaInstructionDisable_bits 1 #define GFX7_INSTPM_MediaInstructionDisable_bits 1 #define GFX6_INSTPM_MediaInstructionDisable_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTPM_MediaInstructionDisable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX8_INSTPM_MediaInstructionDisable_start 3 #define GFX75_INSTPM_MediaInstructionDisable_start 3 #define GFX7_INSTPM_MediaInstructionDisable_start 3 #define GFX6_INSTPM_MediaInstructionDisable_start 3 static inline uint32_t ATTRIBUTE_PURE INSTPM_MediaInstructionDisable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INSTPM::Media Instruction Disable Mask */ #define GFX8_INSTPM_MediaInstructionDisableMask_bits 1 #define GFX75_INSTPM_MediaInstructionDisableMask_bits 1 #define GFX7_INSTPM_MediaInstructionDisableMask_bits 1 #define GFX6_INSTPM_MediaInstructionDisableMask_bits 1 static inline uint32_t ATTRIBUTE_PURE INSTPM_MediaInstructionDisableMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX8_INSTPM_MediaInstructionDisableMask_start 19 #define GFX75_INSTPM_MediaInstructionDisableMask_start 19 #define GFX7_INSTPM_MediaInstructionDisableMask_start 19 #define GFX6_INSTPM_MediaInstructionDisableMask_start 19 static inline uint32_t ATTRIBUTE_PURE INSTPM_MediaInstructionDisableMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 19; case 75: return 19; case 70: return 19; case 60: return 19; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INTERFACE_DESCRIPTOR_DATA */ #define GFX125_INTERFACE_DESCRIPTOR_DATA_length 8 #define GFX12_INTERFACE_DESCRIPTOR_DATA_length 8 #define GFX11_INTERFACE_DESCRIPTOR_DATA_length 8 #define GFX9_INTERFACE_DESCRIPTOR_DATA_length 8 #define GFX8_INTERFACE_DESCRIPTOR_DATA_length 8 #define GFX75_INTERFACE_DESCRIPTOR_DATA_length 8 #define GFX7_INTERFACE_DESCRIPTOR_DATA_length 8 #define GFX6_INTERFACE_DESCRIPTOR_DATA_length 8 static inline uint32_t ATTRIBUTE_PURE INTERFACE_DESCRIPTOR_DATA_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INTERFACE_DESCRIPTOR_DATA::BTD Mode */ #define GFX125_INTERFACE_DESCRIPTOR_DATA_BTDMode_bits 1 static inline uint32_t ATTRIBUTE_PURE INTERFACE_DESCRIPTOR_DATA_BTDMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INTERFACE_DESCRIPTOR_DATA_BTDMode_start 191 static inline uint32_t ATTRIBUTE_PURE INTERFACE_DESCRIPTOR_DATA_BTDMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 191; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INTERFACE_DESCRIPTOR_DATA::Barrier Enable */ #define GFX125_INTERFACE_DESCRIPTOR_DATA_BarrierEnable_bits 1 #define GFX12_INTERFACE_DESCRIPTOR_DATA_BarrierEnable_bits 1 #define GFX11_INTERFACE_DESCRIPTOR_DATA_BarrierEnable_bits 1 #define GFX9_INTERFACE_DESCRIPTOR_DATA_BarrierEnable_bits 1 #define GFX8_INTERFACE_DESCRIPTOR_DATA_BarrierEnable_bits 1 #define GFX75_INTERFACE_DESCRIPTOR_DATA_BarrierEnable_bits 1 #define GFX7_INTERFACE_DESCRIPTOR_DATA_BarrierEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE INTERFACE_DESCRIPTOR_DATA_BarrierEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INTERFACE_DESCRIPTOR_DATA_BarrierEnable_start 181 #define GFX12_INTERFACE_DESCRIPTOR_DATA_BarrierEnable_start 213 #define GFX11_INTERFACE_DESCRIPTOR_DATA_BarrierEnable_start 213 #define GFX9_INTERFACE_DESCRIPTOR_DATA_BarrierEnable_start 213 #define GFX8_INTERFACE_DESCRIPTOR_DATA_BarrierEnable_start 213 #define GFX75_INTERFACE_DESCRIPTOR_DATA_BarrierEnable_start 181 #define GFX7_INTERFACE_DESCRIPTOR_DATA_BarrierEnable_start 181 static inline uint32_t ATTRIBUTE_PURE INTERFACE_DESCRIPTOR_DATA_BarrierEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 181; case 120: return 213; case 110: return 213; case 90: return 213; case 80: return 213; case 75: return 181; case 70: return 181; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INTERFACE_DESCRIPTOR_DATA::Barrier ID */ #define GFX6_INTERFACE_DESCRIPTOR_DATA_BarrierID_bits 4 static inline uint32_t ATTRIBUTE_PURE INTERFACE_DESCRIPTOR_DATA_BarrierID_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_INTERFACE_DESCRIPTOR_DATA_BarrierID_start 160 static inline uint32_t ATTRIBUTE_PURE INTERFACE_DESCRIPTOR_DATA_BarrierID_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 160; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INTERFACE_DESCRIPTOR_DATA::Barrier Return Byte */ #define GFX6_INTERFACE_DESCRIPTOR_DATA_BarrierReturnByte_bits 8 static inline uint32_t ATTRIBUTE_PURE INTERFACE_DESCRIPTOR_DATA_BarrierReturnByte_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_INTERFACE_DESCRIPTOR_DATA_BarrierReturnByte_start 168 static inline uint32_t ATTRIBUTE_PURE INTERFACE_DESCRIPTOR_DATA_BarrierReturnByte_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 168; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INTERFACE_DESCRIPTOR_DATA::Barrier Return GRF Offset */ #define GFX6_INTERFACE_DESCRIPTOR_DATA_BarrierReturnGRFOffset_bits 8 static inline uint32_t ATTRIBUTE_PURE INTERFACE_DESCRIPTOR_DATA_BarrierReturnGRFOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_INTERFACE_DESCRIPTOR_DATA_BarrierReturnGRFOffset_start 184 static inline uint32_t ATTRIBUTE_PURE INTERFACE_DESCRIPTOR_DATA_BarrierReturnGRFOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 184; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INTERFACE_DESCRIPTOR_DATA::Binding Table Entry Count */ #define GFX125_INTERFACE_DESCRIPTOR_DATA_BindingTableEntryCount_bits 5 #define GFX12_INTERFACE_DESCRIPTOR_DATA_BindingTableEntryCount_bits 5 #define GFX11_INTERFACE_DESCRIPTOR_DATA_BindingTableEntryCount_bits 5 #define GFX9_INTERFACE_DESCRIPTOR_DATA_BindingTableEntryCount_bits 5 #define GFX8_INTERFACE_DESCRIPTOR_DATA_BindingTableEntryCount_bits 5 #define GFX75_INTERFACE_DESCRIPTOR_DATA_BindingTableEntryCount_bits 5 #define GFX7_INTERFACE_DESCRIPTOR_DATA_BindingTableEntryCount_bits 5 #define GFX6_INTERFACE_DESCRIPTOR_DATA_BindingTableEntryCount_bits 5 static inline uint32_t ATTRIBUTE_PURE INTERFACE_DESCRIPTOR_DATA_BindingTableEntryCount_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 5; case 110: return 5; case 90: return 5; case 80: return 5; case 75: return 5; case 70: return 5; case 60: return 5; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INTERFACE_DESCRIPTOR_DATA_BindingTableEntryCount_start 128 #define GFX12_INTERFACE_DESCRIPTOR_DATA_BindingTableEntryCount_start 128 #define GFX11_INTERFACE_DESCRIPTOR_DATA_BindingTableEntryCount_start 128 #define GFX9_INTERFACE_DESCRIPTOR_DATA_BindingTableEntryCount_start 128 #define GFX8_INTERFACE_DESCRIPTOR_DATA_BindingTableEntryCount_start 128 #define GFX75_INTERFACE_DESCRIPTOR_DATA_BindingTableEntryCount_start 96 #define GFX7_INTERFACE_DESCRIPTOR_DATA_BindingTableEntryCount_start 96 #define GFX6_INTERFACE_DESCRIPTOR_DATA_BindingTableEntryCount_start 96 static inline uint32_t ATTRIBUTE_PURE INTERFACE_DESCRIPTOR_DATA_BindingTableEntryCount_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 128; case 120: return 128; case 110: return 128; case 90: return 128; case 80: return 128; case 75: return 96; case 70: return 96; case 60: return 96; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INTERFACE_DESCRIPTOR_DATA::Binding Table Pointer */ #define GFX125_INTERFACE_DESCRIPTOR_DATA_BindingTablePointer_bits 16 #define GFX12_INTERFACE_DESCRIPTOR_DATA_BindingTablePointer_bits 11 #define GFX11_INTERFACE_DESCRIPTOR_DATA_BindingTablePointer_bits 11 #define GFX9_INTERFACE_DESCRIPTOR_DATA_BindingTablePointer_bits 11 #define GFX8_INTERFACE_DESCRIPTOR_DATA_BindingTablePointer_bits 11 #define GFX75_INTERFACE_DESCRIPTOR_DATA_BindingTablePointer_bits 11 #define GFX7_INTERFACE_DESCRIPTOR_DATA_BindingTablePointer_bits 11 #define GFX6_INTERFACE_DESCRIPTOR_DATA_BindingTablePointer_bits 27 static inline uint32_t ATTRIBUTE_PURE INTERFACE_DESCRIPTOR_DATA_BindingTablePointer_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 11; case 110: return 11; case 90: return 11; case 80: return 11; case 75: return 11; case 70: return 11; case 60: return 27; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INTERFACE_DESCRIPTOR_DATA_BindingTablePointer_start 133 #define GFX12_INTERFACE_DESCRIPTOR_DATA_BindingTablePointer_start 133 #define GFX11_INTERFACE_DESCRIPTOR_DATA_BindingTablePointer_start 133 #define GFX9_INTERFACE_DESCRIPTOR_DATA_BindingTablePointer_start 133 #define GFX8_INTERFACE_DESCRIPTOR_DATA_BindingTablePointer_start 133 #define GFX75_INTERFACE_DESCRIPTOR_DATA_BindingTablePointer_start 101 #define GFX7_INTERFACE_DESCRIPTOR_DATA_BindingTablePointer_start 101 #define GFX6_INTERFACE_DESCRIPTOR_DATA_BindingTablePointer_start 101 static inline uint32_t ATTRIBUTE_PURE INTERFACE_DESCRIPTOR_DATA_BindingTablePointer_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 133; case 120: return 133; case 110: return 133; case 90: return 133; case 80: return 133; case 75: return 101; case 70: return 101; case 60: return 101; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INTERFACE_DESCRIPTOR_DATA::Constant URB Entry Read Length */ #define GFX12_INTERFACE_DESCRIPTOR_DATA_ConstantURBEntryReadLength_bits 16 #define GFX11_INTERFACE_DESCRIPTOR_DATA_ConstantURBEntryReadLength_bits 16 #define GFX9_INTERFACE_DESCRIPTOR_DATA_ConstantURBEntryReadLength_bits 16 #define GFX8_INTERFACE_DESCRIPTOR_DATA_ConstantURBEntryReadLength_bits 16 #define GFX75_INTERFACE_DESCRIPTOR_DATA_ConstantURBEntryReadLength_bits 16 #define GFX7_INTERFACE_DESCRIPTOR_DATA_ConstantURBEntryReadLength_bits 16 #define GFX6_INTERFACE_DESCRIPTOR_DATA_ConstantURBEntryReadLength_bits 16 static inline uint32_t ATTRIBUTE_PURE INTERFACE_DESCRIPTOR_DATA_ConstantURBEntryReadLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 16; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_INTERFACE_DESCRIPTOR_DATA_ConstantURBEntryReadLength_start 176 #define GFX11_INTERFACE_DESCRIPTOR_DATA_ConstantURBEntryReadLength_start 176 #define GFX9_INTERFACE_DESCRIPTOR_DATA_ConstantURBEntryReadLength_start 176 #define GFX8_INTERFACE_DESCRIPTOR_DATA_ConstantURBEntryReadLength_start 176 #define GFX75_INTERFACE_DESCRIPTOR_DATA_ConstantURBEntryReadLength_start 144 #define GFX7_INTERFACE_DESCRIPTOR_DATA_ConstantURBEntryReadLength_start 144 #define GFX6_INTERFACE_DESCRIPTOR_DATA_ConstantURBEntryReadLength_start 144 static inline uint32_t ATTRIBUTE_PURE INTERFACE_DESCRIPTOR_DATA_ConstantURBEntryReadLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 176; case 110: return 176; case 90: return 176; case 80: return 176; case 75: return 144; case 70: return 144; case 60: return 144; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INTERFACE_DESCRIPTOR_DATA::Constant URB Entry Read Offset */ #define GFX12_INTERFACE_DESCRIPTOR_DATA_ConstantURBEntryReadOffset_bits 16 #define GFX11_INTERFACE_DESCRIPTOR_DATA_ConstantURBEntryReadOffset_bits 16 #define GFX9_INTERFACE_DESCRIPTOR_DATA_ConstantURBEntryReadOffset_bits 16 #define GFX8_INTERFACE_DESCRIPTOR_DATA_ConstantURBEntryReadOffset_bits 16 #define GFX7_INTERFACE_DESCRIPTOR_DATA_ConstantURBEntryReadOffset_bits 16 #define GFX6_INTERFACE_DESCRIPTOR_DATA_ConstantURBEntryReadOffset_bits 16 static inline uint32_t ATTRIBUTE_PURE INTERFACE_DESCRIPTOR_DATA_ConstantURBEntryReadOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 0; case 70: return 16; case 60: return 16; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_INTERFACE_DESCRIPTOR_DATA_ConstantURBEntryReadOffset_start 160 #define GFX11_INTERFACE_DESCRIPTOR_DATA_ConstantURBEntryReadOffset_start 160 #define GFX9_INTERFACE_DESCRIPTOR_DATA_ConstantURBEntryReadOffset_start 160 #define GFX8_INTERFACE_DESCRIPTOR_DATA_ConstantURBEntryReadOffset_start 160 #define GFX7_INTERFACE_DESCRIPTOR_DATA_ConstantURBEntryReadOffset_start 128 #define GFX6_INTERFACE_DESCRIPTOR_DATA_ConstantURBEntryReadOffset_start 128 static inline uint32_t ATTRIBUTE_PURE INTERFACE_DESCRIPTOR_DATA_ConstantURBEntryReadOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 160; case 110: return 160; case 90: return 160; case 80: return 160; case 75: return 0; case 70: return 128; case 60: return 128; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INTERFACE_DESCRIPTOR_DATA::Cross-Thread Constant Data Read Length */ #define GFX12_INTERFACE_DESCRIPTOR_DATA_CrossThreadConstantDataReadLength_bits 8 #define GFX11_INTERFACE_DESCRIPTOR_DATA_CrossThreadConstantDataReadLength_bits 8 #define GFX9_INTERFACE_DESCRIPTOR_DATA_CrossThreadConstantDataReadLength_bits 8 #define GFX8_INTERFACE_DESCRIPTOR_DATA_CrossThreadConstantDataReadLength_bits 8 #define GFX75_INTERFACE_DESCRIPTOR_DATA_CrossThreadConstantDataReadLength_bits 8 static inline uint32_t ATTRIBUTE_PURE INTERFACE_DESCRIPTOR_DATA_CrossThreadConstantDataReadLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_INTERFACE_DESCRIPTOR_DATA_CrossThreadConstantDataReadLength_start 224 #define GFX11_INTERFACE_DESCRIPTOR_DATA_CrossThreadConstantDataReadLength_start 224 #define GFX9_INTERFACE_DESCRIPTOR_DATA_CrossThreadConstantDataReadLength_start 224 #define GFX8_INTERFACE_DESCRIPTOR_DATA_CrossThreadConstantDataReadLength_start 224 #define GFX75_INTERFACE_DESCRIPTOR_DATA_CrossThreadConstantDataReadLength_start 192 static inline uint32_t ATTRIBUTE_PURE INTERFACE_DESCRIPTOR_DATA_CrossThreadConstantDataReadLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 224; case 110: return 224; case 90: return 224; case 80: return 224; case 75: return 192; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INTERFACE_DESCRIPTOR_DATA::Denorm Mode */ #define GFX125_INTERFACE_DESCRIPTOR_DATA_DenormMode_bits 1 #define GFX12_INTERFACE_DESCRIPTOR_DATA_DenormMode_bits 1 #define GFX11_INTERFACE_DESCRIPTOR_DATA_DenormMode_bits 1 #define GFX9_INTERFACE_DESCRIPTOR_DATA_DenormMode_bits 1 #define GFX8_INTERFACE_DESCRIPTOR_DATA_DenormMode_bits 1 static inline uint32_t ATTRIBUTE_PURE INTERFACE_DESCRIPTOR_DATA_DenormMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INTERFACE_DESCRIPTOR_DATA_DenormMode_start 83 #define GFX12_INTERFACE_DESCRIPTOR_DATA_DenormMode_start 83 #define GFX11_INTERFACE_DESCRIPTOR_DATA_DenormMode_start 83 #define GFX9_INTERFACE_DESCRIPTOR_DATA_DenormMode_start 83 #define GFX8_INTERFACE_DESCRIPTOR_DATA_DenormMode_start 83 static inline uint32_t ATTRIBUTE_PURE INTERFACE_DESCRIPTOR_DATA_DenormMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 83; case 120: return 83; case 110: return 83; case 90: return 83; case 80: return 83; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INTERFACE_DESCRIPTOR_DATA::Floating Point Mode */ #define GFX125_INTERFACE_DESCRIPTOR_DATA_FloatingPointMode_bits 1 #define GFX12_INTERFACE_DESCRIPTOR_DATA_FloatingPointMode_bits 1 #define GFX11_INTERFACE_DESCRIPTOR_DATA_FloatingPointMode_bits 1 #define GFX9_INTERFACE_DESCRIPTOR_DATA_FloatingPointMode_bits 1 #define GFX8_INTERFACE_DESCRIPTOR_DATA_FloatingPointMode_bits 1 #define GFX75_INTERFACE_DESCRIPTOR_DATA_FloatingPointMode_bits 1 #define GFX7_INTERFACE_DESCRIPTOR_DATA_FloatingPointMode_bits 1 #define GFX6_INTERFACE_DESCRIPTOR_DATA_FloatingPointMode_bits 1 static inline uint32_t ATTRIBUTE_PURE INTERFACE_DESCRIPTOR_DATA_FloatingPointMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INTERFACE_DESCRIPTOR_DATA_FloatingPointMode_start 80 #define GFX12_INTERFACE_DESCRIPTOR_DATA_FloatingPointMode_start 80 #define GFX11_INTERFACE_DESCRIPTOR_DATA_FloatingPointMode_start 80 #define GFX9_INTERFACE_DESCRIPTOR_DATA_FloatingPointMode_start 80 #define GFX8_INTERFACE_DESCRIPTOR_DATA_FloatingPointMode_start 80 #define GFX75_INTERFACE_DESCRIPTOR_DATA_FloatingPointMode_start 48 #define GFX7_INTERFACE_DESCRIPTOR_DATA_FloatingPointMode_start 48 #define GFX6_INTERFACE_DESCRIPTOR_DATA_FloatingPointMode_start 48 static inline uint32_t ATTRIBUTE_PURE INTERFACE_DESCRIPTOR_DATA_FloatingPointMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 80; case 120: return 80; case 110: return 80; case 90: return 80; case 80: return 80; case 75: return 48; case 70: return 48; case 60: return 48; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INTERFACE_DESCRIPTOR_DATA::Global Barrier Enable */ #define GFX12_INTERFACE_DESCRIPTOR_DATA_GlobalBarrierEnable_bits 1 #define GFX11_INTERFACE_DESCRIPTOR_DATA_GlobalBarrierEnable_bits 1 #define GFX9_INTERFACE_DESCRIPTOR_DATA_GlobalBarrierEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE INTERFACE_DESCRIPTOR_DATA_GlobalBarrierEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_INTERFACE_DESCRIPTOR_DATA_GlobalBarrierEnable_start 207 #define GFX11_INTERFACE_DESCRIPTOR_DATA_GlobalBarrierEnable_start 207 #define GFX9_INTERFACE_DESCRIPTOR_DATA_GlobalBarrierEnable_start 207 static inline uint32_t ATTRIBUTE_PURE INTERFACE_DESCRIPTOR_DATA_GlobalBarrierEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 207; case 110: return 207; case 90: return 207; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INTERFACE_DESCRIPTOR_DATA::Illegal Opcode Exception Enable */ #define GFX125_INTERFACE_DESCRIPTOR_DATA_IllegalOpcodeExceptionEnable_bits 1 #define GFX12_INTERFACE_DESCRIPTOR_DATA_IllegalOpcodeExceptionEnable_bits 1 #define GFX11_INTERFACE_DESCRIPTOR_DATA_IllegalOpcodeExceptionEnable_bits 1 #define GFX9_INTERFACE_DESCRIPTOR_DATA_IllegalOpcodeExceptionEnable_bits 1 #define GFX8_INTERFACE_DESCRIPTOR_DATA_IllegalOpcodeExceptionEnable_bits 1 #define GFX75_INTERFACE_DESCRIPTOR_DATA_IllegalOpcodeExceptionEnable_bits 1 #define GFX7_INTERFACE_DESCRIPTOR_DATA_IllegalOpcodeExceptionEnable_bits 1 #define GFX6_INTERFACE_DESCRIPTOR_DATA_IllegalOpcodeExceptionEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE INTERFACE_DESCRIPTOR_DATA_IllegalOpcodeExceptionEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INTERFACE_DESCRIPTOR_DATA_IllegalOpcodeExceptionEnable_start 77 #define GFX12_INTERFACE_DESCRIPTOR_DATA_IllegalOpcodeExceptionEnable_start 77 #define GFX11_INTERFACE_DESCRIPTOR_DATA_IllegalOpcodeExceptionEnable_start 77 #define GFX9_INTERFACE_DESCRIPTOR_DATA_IllegalOpcodeExceptionEnable_start 77 #define GFX8_INTERFACE_DESCRIPTOR_DATA_IllegalOpcodeExceptionEnable_start 77 #define GFX75_INTERFACE_DESCRIPTOR_DATA_IllegalOpcodeExceptionEnable_start 45 #define GFX7_INTERFACE_DESCRIPTOR_DATA_IllegalOpcodeExceptionEnable_start 45 #define GFX6_INTERFACE_DESCRIPTOR_DATA_IllegalOpcodeExceptionEnable_start 45 static inline uint32_t ATTRIBUTE_PURE INTERFACE_DESCRIPTOR_DATA_IllegalOpcodeExceptionEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 77; case 120: return 77; case 110: return 77; case 90: return 77; case 80: return 77; case 75: return 45; case 70: return 45; case 60: return 45; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INTERFACE_DESCRIPTOR_DATA::Kernel Start Pointer */ #define GFX125_INTERFACE_DESCRIPTOR_DATA_KernelStartPointer_bits 26 #define GFX12_INTERFACE_DESCRIPTOR_DATA_KernelStartPointer_bits 42 #define GFX11_INTERFACE_DESCRIPTOR_DATA_KernelStartPointer_bits 42 #define GFX9_INTERFACE_DESCRIPTOR_DATA_KernelStartPointer_bits 42 #define GFX8_INTERFACE_DESCRIPTOR_DATA_KernelStartPointer_bits 42 #define GFX75_INTERFACE_DESCRIPTOR_DATA_KernelStartPointer_bits 26 #define GFX7_INTERFACE_DESCRIPTOR_DATA_KernelStartPointer_bits 26 #define GFX6_INTERFACE_DESCRIPTOR_DATA_KernelStartPointer_bits 26 static inline uint32_t ATTRIBUTE_PURE INTERFACE_DESCRIPTOR_DATA_KernelStartPointer_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 26; case 120: return 42; case 110: return 42; case 90: return 42; case 80: return 42; case 75: return 26; case 70: return 26; case 60: return 26; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INTERFACE_DESCRIPTOR_DATA_KernelStartPointer_start 6 #define GFX12_INTERFACE_DESCRIPTOR_DATA_KernelStartPointer_start 6 #define GFX11_INTERFACE_DESCRIPTOR_DATA_KernelStartPointer_start 6 #define GFX9_INTERFACE_DESCRIPTOR_DATA_KernelStartPointer_start 6 #define GFX8_INTERFACE_DESCRIPTOR_DATA_KernelStartPointer_start 6 #define GFX75_INTERFACE_DESCRIPTOR_DATA_KernelStartPointer_start 6 #define GFX7_INTERFACE_DESCRIPTOR_DATA_KernelStartPointer_start 6 #define GFX6_INTERFACE_DESCRIPTOR_DATA_KernelStartPointer_start 6 static inline uint32_t ATTRIBUTE_PURE INTERFACE_DESCRIPTOR_DATA_KernelStartPointer_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 6; case 60: return 6; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INTERFACE_DESCRIPTOR_DATA::Mask Stack Exception Enable */ #define GFX125_INTERFACE_DESCRIPTOR_DATA_MaskStackExceptionEnable_bits 1 #define GFX12_INTERFACE_DESCRIPTOR_DATA_MaskStackExceptionEnable_bits 1 #define GFX11_INTERFACE_DESCRIPTOR_DATA_MaskStackExceptionEnable_bits 1 #define GFX9_INTERFACE_DESCRIPTOR_DATA_MaskStackExceptionEnable_bits 1 #define GFX8_INTERFACE_DESCRIPTOR_DATA_MaskStackExceptionEnable_bits 1 #define GFX75_INTERFACE_DESCRIPTOR_DATA_MaskStackExceptionEnable_bits 1 #define GFX7_INTERFACE_DESCRIPTOR_DATA_MaskStackExceptionEnable_bits 1 #define GFX6_INTERFACE_DESCRIPTOR_DATA_MaskStackExceptionEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE INTERFACE_DESCRIPTOR_DATA_MaskStackExceptionEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INTERFACE_DESCRIPTOR_DATA_MaskStackExceptionEnable_start 75 #define GFX12_INTERFACE_DESCRIPTOR_DATA_MaskStackExceptionEnable_start 75 #define GFX11_INTERFACE_DESCRIPTOR_DATA_MaskStackExceptionEnable_start 75 #define GFX9_INTERFACE_DESCRIPTOR_DATA_MaskStackExceptionEnable_start 75 #define GFX8_INTERFACE_DESCRIPTOR_DATA_MaskStackExceptionEnable_start 75 #define GFX75_INTERFACE_DESCRIPTOR_DATA_MaskStackExceptionEnable_start 43 #define GFX7_INTERFACE_DESCRIPTOR_DATA_MaskStackExceptionEnable_start 43 #define GFX6_INTERFACE_DESCRIPTOR_DATA_MaskStackExceptionEnable_start 43 static inline uint32_t ATTRIBUTE_PURE INTERFACE_DESCRIPTOR_DATA_MaskStackExceptionEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 75; case 120: return 75; case 110: return 75; case 90: return 75; case 80: return 75; case 75: return 43; case 70: return 43; case 60: return 43; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INTERFACE_DESCRIPTOR_DATA::Number Of Barriers */ #define GFX125_INTERFACE_DESCRIPTOR_DATA_NumberOfBarriers_bits 3 static inline uint32_t ATTRIBUTE_PURE INTERFACE_DESCRIPTOR_DATA_NumberOfBarriers_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INTERFACE_DESCRIPTOR_DATA_NumberOfBarriers_start 188 static inline uint32_t ATTRIBUTE_PURE INTERFACE_DESCRIPTOR_DATA_NumberOfBarriers_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 188; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INTERFACE_DESCRIPTOR_DATA::Number of Threads in GPGPU Thread Group */ #define GFX125_INTERFACE_DESCRIPTOR_DATA_NumberofThreadsinGPGPUThreadGroup_bits 10 #define GFX12_INTERFACE_DESCRIPTOR_DATA_NumberofThreadsinGPGPUThreadGroup_bits 10 #define GFX11_INTERFACE_DESCRIPTOR_DATA_NumberofThreadsinGPGPUThreadGroup_bits 10 #define GFX9_INTERFACE_DESCRIPTOR_DATA_NumberofThreadsinGPGPUThreadGroup_bits 10 #define GFX8_INTERFACE_DESCRIPTOR_DATA_NumberofThreadsinGPGPUThreadGroup_bits 10 #define GFX75_INTERFACE_DESCRIPTOR_DATA_NumberofThreadsinGPGPUThreadGroup_bits 8 #define GFX7_INTERFACE_DESCRIPTOR_DATA_NumberofThreadsinGPGPUThreadGroup_bits 8 static inline uint32_t ATTRIBUTE_PURE INTERFACE_DESCRIPTOR_DATA_NumberofThreadsinGPGPUThreadGroup_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 10; case 120: return 10; case 110: return 10; case 90: return 10; case 80: return 10; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INTERFACE_DESCRIPTOR_DATA_NumberofThreadsinGPGPUThreadGroup_start 160 #define GFX12_INTERFACE_DESCRIPTOR_DATA_NumberofThreadsinGPGPUThreadGroup_start 192 #define GFX11_INTERFACE_DESCRIPTOR_DATA_NumberofThreadsinGPGPUThreadGroup_start 192 #define GFX9_INTERFACE_DESCRIPTOR_DATA_NumberofThreadsinGPGPUThreadGroup_start 192 #define GFX8_INTERFACE_DESCRIPTOR_DATA_NumberofThreadsinGPGPUThreadGroup_start 192 #define GFX75_INTERFACE_DESCRIPTOR_DATA_NumberofThreadsinGPGPUThreadGroup_start 160 #define GFX7_INTERFACE_DESCRIPTOR_DATA_NumberofThreadsinGPGPUThreadGroup_start 160 static inline uint32_t ATTRIBUTE_PURE INTERFACE_DESCRIPTOR_DATA_NumberofThreadsinGPGPUThreadGroup_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 160; case 120: return 192; case 110: return 192; case 90: return 192; case 80: return 192; case 75: return 160; case 70: return 160; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INTERFACE_DESCRIPTOR_DATA::Rounding Mode */ #define GFX125_INTERFACE_DESCRIPTOR_DATA_RoundingMode_bits 2 #define GFX12_INTERFACE_DESCRIPTOR_DATA_RoundingMode_bits 2 #define GFX11_INTERFACE_DESCRIPTOR_DATA_RoundingMode_bits 2 #define GFX9_INTERFACE_DESCRIPTOR_DATA_RoundingMode_bits 2 #define GFX8_INTERFACE_DESCRIPTOR_DATA_RoundingMode_bits 2 #define GFX75_INTERFACE_DESCRIPTOR_DATA_RoundingMode_bits 2 #define GFX7_INTERFACE_DESCRIPTOR_DATA_RoundingMode_bits 2 static inline uint32_t ATTRIBUTE_PURE INTERFACE_DESCRIPTOR_DATA_RoundingMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INTERFACE_DESCRIPTOR_DATA_RoundingMode_start 182 #define GFX12_INTERFACE_DESCRIPTOR_DATA_RoundingMode_start 214 #define GFX11_INTERFACE_DESCRIPTOR_DATA_RoundingMode_start 214 #define GFX9_INTERFACE_DESCRIPTOR_DATA_RoundingMode_start 214 #define GFX8_INTERFACE_DESCRIPTOR_DATA_RoundingMode_start 214 #define GFX75_INTERFACE_DESCRIPTOR_DATA_RoundingMode_start 182 #define GFX7_INTERFACE_DESCRIPTOR_DATA_RoundingMode_start 182 static inline uint32_t ATTRIBUTE_PURE INTERFACE_DESCRIPTOR_DATA_RoundingMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 182; case 120: return 214; case 110: return 214; case 90: return 214; case 80: return 214; case 75: return 182; case 70: return 182; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INTERFACE_DESCRIPTOR_DATA::Sampler Count */ #define GFX125_INTERFACE_DESCRIPTOR_DATA_SamplerCount_bits 3 #define GFX12_INTERFACE_DESCRIPTOR_DATA_SamplerCount_bits 3 #define GFX11_INTERFACE_DESCRIPTOR_DATA_SamplerCount_bits 3 #define GFX9_INTERFACE_DESCRIPTOR_DATA_SamplerCount_bits 3 #define GFX8_INTERFACE_DESCRIPTOR_DATA_SamplerCount_bits 3 #define GFX75_INTERFACE_DESCRIPTOR_DATA_SamplerCount_bits 3 #define GFX7_INTERFACE_DESCRIPTOR_DATA_SamplerCount_bits 3 #define GFX6_INTERFACE_DESCRIPTOR_DATA_SamplerCount_bits 3 static inline uint32_t ATTRIBUTE_PURE INTERFACE_DESCRIPTOR_DATA_SamplerCount_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INTERFACE_DESCRIPTOR_DATA_SamplerCount_start 98 #define GFX12_INTERFACE_DESCRIPTOR_DATA_SamplerCount_start 98 #define GFX11_INTERFACE_DESCRIPTOR_DATA_SamplerCount_start 98 #define GFX9_INTERFACE_DESCRIPTOR_DATA_SamplerCount_start 98 #define GFX8_INTERFACE_DESCRIPTOR_DATA_SamplerCount_start 98 #define GFX75_INTERFACE_DESCRIPTOR_DATA_SamplerCount_start 66 #define GFX7_INTERFACE_DESCRIPTOR_DATA_SamplerCount_start 66 #define GFX6_INTERFACE_DESCRIPTOR_DATA_SamplerCount_start 66 static inline uint32_t ATTRIBUTE_PURE INTERFACE_DESCRIPTOR_DATA_SamplerCount_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 98; case 120: return 98; case 110: return 98; case 90: return 98; case 80: return 98; case 75: return 66; case 70: return 66; case 60: return 66; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INTERFACE_DESCRIPTOR_DATA::Sampler State Pointer */ #define GFX125_INTERFACE_DESCRIPTOR_DATA_SamplerStatePointer_bits 27 #define GFX12_INTERFACE_DESCRIPTOR_DATA_SamplerStatePointer_bits 27 #define GFX11_INTERFACE_DESCRIPTOR_DATA_SamplerStatePointer_bits 27 #define GFX9_INTERFACE_DESCRIPTOR_DATA_SamplerStatePointer_bits 27 #define GFX8_INTERFACE_DESCRIPTOR_DATA_SamplerStatePointer_bits 27 #define GFX75_INTERFACE_DESCRIPTOR_DATA_SamplerStatePointer_bits 27 #define GFX7_INTERFACE_DESCRIPTOR_DATA_SamplerStatePointer_bits 27 #define GFX6_INTERFACE_DESCRIPTOR_DATA_SamplerStatePointer_bits 27 static inline uint32_t ATTRIBUTE_PURE INTERFACE_DESCRIPTOR_DATA_SamplerStatePointer_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 27; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INTERFACE_DESCRIPTOR_DATA_SamplerStatePointer_start 101 #define GFX12_INTERFACE_DESCRIPTOR_DATA_SamplerStatePointer_start 101 #define GFX11_INTERFACE_DESCRIPTOR_DATA_SamplerStatePointer_start 101 #define GFX9_INTERFACE_DESCRIPTOR_DATA_SamplerStatePointer_start 101 #define GFX8_INTERFACE_DESCRIPTOR_DATA_SamplerStatePointer_start 101 #define GFX75_INTERFACE_DESCRIPTOR_DATA_SamplerStatePointer_start 69 #define GFX7_INTERFACE_DESCRIPTOR_DATA_SamplerStatePointer_start 69 #define GFX6_INTERFACE_DESCRIPTOR_DATA_SamplerStatePointer_start 69 static inline uint32_t ATTRIBUTE_PURE INTERFACE_DESCRIPTOR_DATA_SamplerStatePointer_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 101; case 120: return 101; case 110: return 101; case 90: return 101; case 80: return 101; case 75: return 69; case 70: return 69; case 60: return 69; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INTERFACE_DESCRIPTOR_DATA::Shared Local Memory Size */ #define GFX125_INTERFACE_DESCRIPTOR_DATA_SharedLocalMemorySize_bits 5 #define GFX12_INTERFACE_DESCRIPTOR_DATA_SharedLocalMemorySize_bits 5 #define GFX11_INTERFACE_DESCRIPTOR_DATA_SharedLocalMemorySize_bits 5 #define GFX9_INTERFACE_DESCRIPTOR_DATA_SharedLocalMemorySize_bits 5 #define GFX8_INTERFACE_DESCRIPTOR_DATA_SharedLocalMemorySize_bits 5 #define GFX75_INTERFACE_DESCRIPTOR_DATA_SharedLocalMemorySize_bits 5 #define GFX7_INTERFACE_DESCRIPTOR_DATA_SharedLocalMemorySize_bits 5 static inline uint32_t ATTRIBUTE_PURE INTERFACE_DESCRIPTOR_DATA_SharedLocalMemorySize_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 5; case 110: return 5; case 90: return 5; case 80: return 5; case 75: return 5; case 70: return 5; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INTERFACE_DESCRIPTOR_DATA_SharedLocalMemorySize_start 176 #define GFX12_INTERFACE_DESCRIPTOR_DATA_SharedLocalMemorySize_start 208 #define GFX11_INTERFACE_DESCRIPTOR_DATA_SharedLocalMemorySize_start 208 #define GFX9_INTERFACE_DESCRIPTOR_DATA_SharedLocalMemorySize_start 208 #define GFX8_INTERFACE_DESCRIPTOR_DATA_SharedLocalMemorySize_start 208 #define GFX75_INTERFACE_DESCRIPTOR_DATA_SharedLocalMemorySize_start 176 #define GFX7_INTERFACE_DESCRIPTOR_DATA_SharedLocalMemorySize_start 176 static inline uint32_t ATTRIBUTE_PURE INTERFACE_DESCRIPTOR_DATA_SharedLocalMemorySize_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 176; case 120: return 208; case 110: return 208; case 90: return 208; case 80: return 208; case 75: return 176; case 70: return 176; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INTERFACE_DESCRIPTOR_DATA::Single Program Flow */ #define GFX125_INTERFACE_DESCRIPTOR_DATA_SingleProgramFlow_bits 1 #define GFX12_INTERFACE_DESCRIPTOR_DATA_SingleProgramFlow_bits 1 #define GFX11_INTERFACE_DESCRIPTOR_DATA_SingleProgramFlow_bits 1 #define GFX9_INTERFACE_DESCRIPTOR_DATA_SingleProgramFlow_bits 1 #define GFX8_INTERFACE_DESCRIPTOR_DATA_SingleProgramFlow_bits 1 #define GFX75_INTERFACE_DESCRIPTOR_DATA_SingleProgramFlow_bits 1 #define GFX7_INTERFACE_DESCRIPTOR_DATA_SingleProgramFlow_bits 1 #define GFX6_INTERFACE_DESCRIPTOR_DATA_SingleProgramFlow_bits 1 static inline uint32_t ATTRIBUTE_PURE INTERFACE_DESCRIPTOR_DATA_SingleProgramFlow_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INTERFACE_DESCRIPTOR_DATA_SingleProgramFlow_start 82 #define GFX12_INTERFACE_DESCRIPTOR_DATA_SingleProgramFlow_start 82 #define GFX11_INTERFACE_DESCRIPTOR_DATA_SingleProgramFlow_start 82 #define GFX9_INTERFACE_DESCRIPTOR_DATA_SingleProgramFlow_start 82 #define GFX8_INTERFACE_DESCRIPTOR_DATA_SingleProgramFlow_start 82 #define GFX75_INTERFACE_DESCRIPTOR_DATA_SingleProgramFlow_start 50 #define GFX7_INTERFACE_DESCRIPTOR_DATA_SingleProgramFlow_start 50 #define GFX6_INTERFACE_DESCRIPTOR_DATA_SingleProgramFlow_start 50 static inline uint32_t ATTRIBUTE_PURE INTERFACE_DESCRIPTOR_DATA_SingleProgramFlow_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 82; case 120: return 82; case 110: return 82; case 90: return 82; case 80: return 82; case 75: return 50; case 70: return 50; case 60: return 50; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INTERFACE_DESCRIPTOR_DATA::Software Exception Enable */ #define GFX125_INTERFACE_DESCRIPTOR_DATA_SoftwareExceptionEnable_bits 1 #define GFX12_INTERFACE_DESCRIPTOR_DATA_SoftwareExceptionEnable_bits 1 #define GFX11_INTERFACE_DESCRIPTOR_DATA_SoftwareExceptionEnable_bits 1 #define GFX9_INTERFACE_DESCRIPTOR_DATA_SoftwareExceptionEnable_bits 1 #define GFX8_INTERFACE_DESCRIPTOR_DATA_SoftwareExceptionEnable_bits 1 #define GFX75_INTERFACE_DESCRIPTOR_DATA_SoftwareExceptionEnable_bits 1 #define GFX7_INTERFACE_DESCRIPTOR_DATA_SoftwareExceptionEnable_bits 1 #define GFX6_INTERFACE_DESCRIPTOR_DATA_SoftwareExceptionEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE INTERFACE_DESCRIPTOR_DATA_SoftwareExceptionEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INTERFACE_DESCRIPTOR_DATA_SoftwareExceptionEnable_start 71 #define GFX12_INTERFACE_DESCRIPTOR_DATA_SoftwareExceptionEnable_start 71 #define GFX11_INTERFACE_DESCRIPTOR_DATA_SoftwareExceptionEnable_start 71 #define GFX9_INTERFACE_DESCRIPTOR_DATA_SoftwareExceptionEnable_start 71 #define GFX8_INTERFACE_DESCRIPTOR_DATA_SoftwareExceptionEnable_start 71 #define GFX75_INTERFACE_DESCRIPTOR_DATA_SoftwareExceptionEnable_start 39 #define GFX7_INTERFACE_DESCRIPTOR_DATA_SoftwareExceptionEnable_start 39 #define GFX6_INTERFACE_DESCRIPTOR_DATA_SoftwareExceptionEnable_start 39 static inline uint32_t ATTRIBUTE_PURE INTERFACE_DESCRIPTOR_DATA_SoftwareExceptionEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 71; case 120: return 71; case 110: return 71; case 90: return 71; case 80: return 71; case 75: return 39; case 70: return 39; case 60: return 39; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INTERFACE_DESCRIPTOR_DATA::Thread Preemption Disable */ #define GFX125_INTERFACE_DESCRIPTOR_DATA_ThreadPreemptionDisable_bits 1 #define GFX12_INTERFACE_DESCRIPTOR_DATA_ThreadPreemptionDisable_bits 1 static inline uint32_t ATTRIBUTE_PURE INTERFACE_DESCRIPTOR_DATA_ThreadPreemptionDisable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INTERFACE_DESCRIPTOR_DATA_ThreadPreemptionDisable_start 84 #define GFX12_INTERFACE_DESCRIPTOR_DATA_ThreadPreemptionDisable_start 84 static inline uint32_t ATTRIBUTE_PURE INTERFACE_DESCRIPTOR_DATA_ThreadPreemptionDisable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 84; case 120: return 84; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INTERFACE_DESCRIPTOR_DATA::Thread Priority */ #define GFX12_INTERFACE_DESCRIPTOR_DATA_ThreadPriority_bits 1 #define GFX11_INTERFACE_DESCRIPTOR_DATA_ThreadPriority_bits 1 #define GFX9_INTERFACE_DESCRIPTOR_DATA_ThreadPriority_bits 1 #define GFX8_INTERFACE_DESCRIPTOR_DATA_ThreadPriority_bits 1 #define GFX75_INTERFACE_DESCRIPTOR_DATA_ThreadPriority_bits 1 #define GFX7_INTERFACE_DESCRIPTOR_DATA_ThreadPriority_bits 1 #define GFX6_INTERFACE_DESCRIPTOR_DATA_ThreadPriority_bits 1 static inline uint32_t ATTRIBUTE_PURE INTERFACE_DESCRIPTOR_DATA_ThreadPriority_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_INTERFACE_DESCRIPTOR_DATA_ThreadPriority_start 81 #define GFX11_INTERFACE_DESCRIPTOR_DATA_ThreadPriority_start 81 #define GFX9_INTERFACE_DESCRIPTOR_DATA_ThreadPriority_start 81 #define GFX8_INTERFACE_DESCRIPTOR_DATA_ThreadPriority_start 81 #define GFX75_INTERFACE_DESCRIPTOR_DATA_ThreadPriority_start 49 #define GFX7_INTERFACE_DESCRIPTOR_DATA_ThreadPriority_start 49 #define GFX6_INTERFACE_DESCRIPTOR_DATA_ThreadPriority_start 49 static inline uint32_t ATTRIBUTE_PURE INTERFACE_DESCRIPTOR_DATA_ThreadPriority_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 81; case 110: return 81; case 90: return 81; case 80: return 81; case 75: return 49; case 70: return 49; case 60: return 49; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* INTERFACE_DESCRIPTOR_DATA::Thread group dispatch size */ #define GFX125_INTERFACE_DESCRIPTOR_DATA_Threadgroupdispatchsize_bits 1 static inline uint32_t ATTRIBUTE_PURE INTERFACE_DESCRIPTOR_DATA_Threadgroupdispatchsize_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_INTERFACE_DESCRIPTOR_DATA_Threadgroupdispatchsize_start 187 static inline uint32_t ATTRIBUTE_PURE INTERFACE_DESCRIPTOR_DATA_Threadgroupdispatchsize_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 187; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* L3ALLOC */ #define GFX125_L3ALLOC_length 1 #define GFX12_L3ALLOC_length 1 static inline uint32_t ATTRIBUTE_PURE L3ALLOC_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* L3ALLOC::All Allocation */ #define GFX125_L3ALLOC_AllAllocation_bits 7 #define GFX12_L3ALLOC_AllAllocation_bits 7 static inline uint32_t ATTRIBUTE_PURE L3ALLOC_AllAllocation_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 7; case 120: return 7; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_L3ALLOC_AllAllocation_start 25 #define GFX12_L3ALLOC_AllAllocation_start 25 static inline uint32_t ATTRIBUTE_PURE L3ALLOC_AllAllocation_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 25; case 120: return 25; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* L3ALLOC::Allocation Error */ #define GFX125_L3ALLOC_AllocationError_bits 1 #define GFX12_L3ALLOC_AllocationError_bits 1 static inline uint32_t ATTRIBUTE_PURE L3ALLOC_AllocationError_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_L3ALLOC_AllocationError_start 0 #define GFX12_L3ALLOC_AllocationError_start 0 static inline uint32_t ATTRIBUTE_PURE L3ALLOC_AllocationError_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* L3ALLOC::DC Allocation */ #define GFX125_L3ALLOC_DCAllocation_bits 7 #define GFX12_L3ALLOC_DCAllocation_bits 7 static inline uint32_t ATTRIBUTE_PURE L3ALLOC_DCAllocation_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 7; case 120: return 7; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_L3ALLOC_DCAllocation_start 18 #define GFX12_L3ALLOC_DCAllocation_start 18 static inline uint32_t ATTRIBUTE_PURE L3ALLOC_DCAllocation_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 18; case 120: return 18; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* L3ALLOC::L3 Full Way Allocation Enable */ #define GFX125_L3ALLOC_L3FullWayAllocationEnable_bits 1 #define GFX12_L3ALLOC_L3FullWayAllocationEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE L3ALLOC_L3FullWayAllocationEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_L3ALLOC_L3FullWayAllocationEnable_start 9 #define GFX12_L3ALLOC_L3FullWayAllocationEnable_start 9 static inline uint32_t ATTRIBUTE_PURE L3ALLOC_L3FullWayAllocationEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 9; case 120: return 9; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* L3ALLOC::RO Allocation */ #define GFX125_L3ALLOC_ROAllocation_bits 7 #define GFX12_L3ALLOC_ROAllocation_bits 7 static inline uint32_t ATTRIBUTE_PURE L3ALLOC_ROAllocation_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 7; case 120: return 7; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_L3ALLOC_ROAllocation_start 11 #define GFX12_L3ALLOC_ROAllocation_start 11 static inline uint32_t ATTRIBUTE_PURE L3ALLOC_ROAllocation_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 11; case 120: return 11; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* L3ALLOC::URB Allocation */ #define GFX125_L3ALLOC_URBAllocation_bits 7 #define GFX12_L3ALLOC_URBAllocation_bits 7 static inline uint32_t ATTRIBUTE_PURE L3ALLOC_URBAllocation_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 7; case 120: return 7; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_L3ALLOC_URBAllocation_start 1 #define GFX12_L3ALLOC_URBAllocation_start 1 static inline uint32_t ATTRIBUTE_PURE L3ALLOC_URBAllocation_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* L3CNTLREG */ #define GFX11_L3CNTLREG_length 1 #define GFX9_L3CNTLREG_length 1 #define GFX8_L3CNTLREG_length 1 static inline uint32_t ATTRIBUTE_PURE L3CNTLREG_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* L3CNTLREG::All Allocation */ #define GFX11_L3CNTLREG_AllAllocation_bits 7 #define GFX9_L3CNTLREG_AllAllocation_bits 7 #define GFX8_L3CNTLREG_AllAllocation_bits 7 static inline uint32_t ATTRIBUTE_PURE L3CNTLREG_AllAllocation_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 7; case 90: return 7; case 80: return 7; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX11_L3CNTLREG_AllAllocation_start 25 #define GFX9_L3CNTLREG_AllAllocation_start 25 #define GFX8_L3CNTLREG_AllAllocation_start 25 static inline uint32_t ATTRIBUTE_PURE L3CNTLREG_AllAllocation_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 25; case 90: return 25; case 80: return 25; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* L3CNTLREG::DC Allocation */ #define GFX11_L3CNTLREG_DCAllocation_bits 7 #define GFX9_L3CNTLREG_DCAllocation_bits 7 #define GFX8_L3CNTLREG_DCAllocation_bits 7 static inline uint32_t ATTRIBUTE_PURE L3CNTLREG_DCAllocation_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 7; case 90: return 7; case 80: return 7; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX11_L3CNTLREG_DCAllocation_start 18 #define GFX9_L3CNTLREG_DCAllocation_start 18 #define GFX8_L3CNTLREG_DCAllocation_start 18 static inline uint32_t ATTRIBUTE_PURE L3CNTLREG_DCAllocation_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 18; case 90: return 18; case 80: return 18; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* L3CNTLREG::Error Detection Behavior Control */ #define GFX11_L3CNTLREG_ErrorDetectionBehaviorControl_bits 1 static inline uint32_t ATTRIBUTE_PURE L3CNTLREG_ErrorDetectionBehaviorControl_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX11_L3CNTLREG_ErrorDetectionBehaviorControl_start 9 static inline uint32_t ATTRIBUTE_PURE L3CNTLREG_ErrorDetectionBehaviorControl_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 9; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* L3CNTLREG::RO Allocation */ #define GFX11_L3CNTLREG_ROAllocation_bits 7 #define GFX9_L3CNTLREG_ROAllocation_bits 7 #define GFX8_L3CNTLREG_ROAllocation_bits 7 static inline uint32_t ATTRIBUTE_PURE L3CNTLREG_ROAllocation_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 7; case 90: return 7; case 80: return 7; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX11_L3CNTLREG_ROAllocation_start 11 #define GFX9_L3CNTLREG_ROAllocation_start 11 #define GFX8_L3CNTLREG_ROAllocation_start 11 static inline uint32_t ATTRIBUTE_PURE L3CNTLREG_ROAllocation_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 11; case 90: return 11; case 80: return 11; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* L3CNTLREG::SLM Enable */ #define GFX9_L3CNTLREG_SLMEnable_bits 1 #define GFX8_L3CNTLREG_SLMEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE L3CNTLREG_SLMEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_L3CNTLREG_SLMEnable_start 0 #define GFX8_L3CNTLREG_SLMEnable_start 0 static inline uint32_t ATTRIBUTE_PURE L3CNTLREG_SLMEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* L3CNTLREG::URB Allocation */ #define GFX11_L3CNTLREG_URBAllocation_bits 7 #define GFX9_L3CNTLREG_URBAllocation_bits 7 #define GFX8_L3CNTLREG_URBAllocation_bits 7 static inline uint32_t ATTRIBUTE_PURE L3CNTLREG_URBAllocation_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 7; case 90: return 7; case 80: return 7; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX11_L3CNTLREG_URBAllocation_start 1 #define GFX9_L3CNTLREG_URBAllocation_start 1 #define GFX8_L3CNTLREG_URBAllocation_start 1 static inline uint32_t ATTRIBUTE_PURE L3CNTLREG_URBAllocation_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* L3CNTLREG::Use Full Ways */ #define GFX11_L3CNTLREG_UseFullWays_bits 1 static inline uint32_t ATTRIBUTE_PURE L3CNTLREG_UseFullWays_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX11_L3CNTLREG_UseFullWays_start 10 static inline uint32_t ATTRIBUTE_PURE L3CNTLREG_UseFullWays_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 10; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* L3CNTLREG2 */ #define GFX75_L3CNTLREG2_length 1 #define GFX7_L3CNTLREG2_length 1 static inline uint32_t ATTRIBUTE_PURE L3CNTLREG2_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* L3CNTLREG2::ALL Allocation */ #define GFX7_L3CNTLREG2_ALLAllocation_bits 6 static inline uint32_t ATTRIBUTE_PURE L3CNTLREG2_ALLAllocation_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 6; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX7_L3CNTLREG2_ALLAllocation_start 8 static inline uint32_t ATTRIBUTE_PURE L3CNTLREG2_ALLAllocation_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* L3CNTLREG2::DC Allocation */ #define GFX75_L3CNTLREG2_DCAllocation_bits 6 #define GFX7_L3CNTLREG2_DCAllocation_bits 6 static inline uint32_t ATTRIBUTE_PURE L3CNTLREG2_DCAllocation_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 6; case 70: return 6; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_L3CNTLREG2_DCAllocation_start 21 #define GFX7_L3CNTLREG2_DCAllocation_start 21 static inline uint32_t ATTRIBUTE_PURE L3CNTLREG2_DCAllocation_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 21; case 70: return 21; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* L3CNTLREG2::DC Low Bandwidth */ #define GFX75_L3CNTLREG2_DCLowBandwidth_bits 1 #define GFX7_L3CNTLREG2_DCLowBandwidth_bits 1 static inline uint32_t ATTRIBUTE_PURE L3CNTLREG2_DCLowBandwidth_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_L3CNTLREG2_DCLowBandwidth_start 27 #define GFX7_L3CNTLREG2_DCLowBandwidth_start 27 static inline uint32_t ATTRIBUTE_PURE L3CNTLREG2_DCLowBandwidth_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 27; case 70: return 27; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* L3CNTLREG2::RO Allocation */ #define GFX75_L3CNTLREG2_ROAllocation_bits 6 #define GFX7_L3CNTLREG2_ROAllocation_bits 6 static inline uint32_t ATTRIBUTE_PURE L3CNTLREG2_ROAllocation_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 6; case 70: return 6; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_L3CNTLREG2_ROAllocation_start 14 #define GFX7_L3CNTLREG2_ROAllocation_start 14 static inline uint32_t ATTRIBUTE_PURE L3CNTLREG2_ROAllocation_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 14; case 70: return 14; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* L3CNTLREG2::RO Low Bandwidth */ #define GFX75_L3CNTLREG2_ROLowBandwidth_bits 1 #define GFX7_L3CNTLREG2_ROLowBandwidth_bits 1 static inline uint32_t ATTRIBUTE_PURE L3CNTLREG2_ROLowBandwidth_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_L3CNTLREG2_ROLowBandwidth_start 20 #define GFX7_L3CNTLREG2_ROLowBandwidth_start 20 static inline uint32_t ATTRIBUTE_PURE L3CNTLREG2_ROLowBandwidth_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 20; case 70: return 20; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* L3CNTLREG2::SLM Enable */ #define GFX75_L3CNTLREG2_SLMEnable_bits 1 #define GFX7_L3CNTLREG2_SLMEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE L3CNTLREG2_SLMEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_L3CNTLREG2_SLMEnable_start 0 #define GFX7_L3CNTLREG2_SLMEnable_start 0 static inline uint32_t ATTRIBUTE_PURE L3CNTLREG2_SLMEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* L3CNTLREG2::URB Allocation */ #define GFX75_L3CNTLREG2_URBAllocation_bits 6 #define GFX7_L3CNTLREG2_URBAllocation_bits 6 static inline uint32_t ATTRIBUTE_PURE L3CNTLREG2_URBAllocation_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 6; case 70: return 6; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_L3CNTLREG2_URBAllocation_start 1 #define GFX7_L3CNTLREG2_URBAllocation_start 1 static inline uint32_t ATTRIBUTE_PURE L3CNTLREG2_URBAllocation_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* L3CNTLREG2::URB Low Bandwidth */ #define GFX75_L3CNTLREG2_URBLowBandwidth_bits 1 #define GFX7_L3CNTLREG2_URBLowBandwidth_bits 1 static inline uint32_t ATTRIBUTE_PURE L3CNTLREG2_URBLowBandwidth_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_L3CNTLREG2_URBLowBandwidth_start 7 #define GFX7_L3CNTLREG2_URBLowBandwidth_start 7 static inline uint32_t ATTRIBUTE_PURE L3CNTLREG2_URBLowBandwidth_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 7; case 70: return 7; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* L3CNTLREG3 */ #define GFX75_L3CNTLREG3_length 1 #define GFX7_L3CNTLREG3_length 1 static inline uint32_t ATTRIBUTE_PURE L3CNTLREG3_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* L3CNTLREG3::C Allocation */ #define GFX75_L3CNTLREG3_CAllocation_bits 6 #define GFX7_L3CNTLREG3_CAllocation_bits 6 static inline uint32_t ATTRIBUTE_PURE L3CNTLREG3_CAllocation_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 6; case 70: return 6; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_L3CNTLREG3_CAllocation_start 8 #define GFX7_L3CNTLREG3_CAllocation_start 8 static inline uint32_t ATTRIBUTE_PURE L3CNTLREG3_CAllocation_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* L3CNTLREG3::C Low Bandwidth */ #define GFX75_L3CNTLREG3_CLowBandwidth_bits 1 #define GFX7_L3CNTLREG3_CLowBandwidth_bits 1 static inline uint32_t ATTRIBUTE_PURE L3CNTLREG3_CLowBandwidth_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_L3CNTLREG3_CLowBandwidth_start 14 #define GFX7_L3CNTLREG3_CLowBandwidth_start 14 static inline uint32_t ATTRIBUTE_PURE L3CNTLREG3_CLowBandwidth_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 14; case 70: return 14; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* L3CNTLREG3::IS Allocation */ #define GFX75_L3CNTLREG3_ISAllocation_bits 6 #define GFX7_L3CNTLREG3_ISAllocation_bits 6 static inline uint32_t ATTRIBUTE_PURE L3CNTLREG3_ISAllocation_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 6; case 70: return 6; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_L3CNTLREG3_ISAllocation_start 1 #define GFX7_L3CNTLREG3_ISAllocation_start 1 static inline uint32_t ATTRIBUTE_PURE L3CNTLREG3_ISAllocation_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* L3CNTLREG3::IS Low Bandwidth */ #define GFX75_L3CNTLREG3_ISLowBandwidth_bits 1 #define GFX7_L3CNTLREG3_ISLowBandwidth_bits 1 static inline uint32_t ATTRIBUTE_PURE L3CNTLREG3_ISLowBandwidth_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_L3CNTLREG3_ISLowBandwidth_start 7 #define GFX7_L3CNTLREG3_ISLowBandwidth_start 7 static inline uint32_t ATTRIBUTE_PURE L3CNTLREG3_ISLowBandwidth_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 7; case 70: return 7; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* L3CNTLREG3::T Allocation */ #define GFX75_L3CNTLREG3_TAllocation_bits 6 #define GFX7_L3CNTLREG3_TAllocation_bits 6 static inline uint32_t ATTRIBUTE_PURE L3CNTLREG3_TAllocation_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 6; case 70: return 6; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_L3CNTLREG3_TAllocation_start 15 #define GFX7_L3CNTLREG3_TAllocation_start 15 static inline uint32_t ATTRIBUTE_PURE L3CNTLREG3_TAllocation_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 15; case 70: return 15; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* L3CNTLREG3::T Low Bandwidth */ #define GFX75_L3CNTLREG3_TLowBandwidth_bits 1 #define GFX7_L3CNTLREG3_TLowBandwidth_bits 1 static inline uint32_t ATTRIBUTE_PURE L3CNTLREG3_TLowBandwidth_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_L3CNTLREG3_TLowBandwidth_start 21 #define GFX7_L3CNTLREG3_TLowBandwidth_start 21 static inline uint32_t ATTRIBUTE_PURE L3CNTLREG3_TLowBandwidth_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 21; case 70: return 21; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* L3SQCREG1 */ #define GFX75_L3SQCREG1_length 1 #define GFX7_L3SQCREG1_length 1 static inline uint32_t ATTRIBUTE_PURE L3SQCREG1_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* L3SQCREG1::Convert C_UC */ #define GFX75_L3SQCREG1_ConvertC_UC_bits 1 #define GFX7_L3SQCREG1_ConvertC_UC_bits 1 static inline uint32_t ATTRIBUTE_PURE L3SQCREG1_ConvertC_UC_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_L3SQCREG1_ConvertC_UC_start 26 #define GFX7_L3SQCREG1_ConvertC_UC_start 26 static inline uint32_t ATTRIBUTE_PURE L3SQCREG1_ConvertC_UC_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 26; case 70: return 26; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* L3SQCREG1::Convert DC_UC */ #define GFX75_L3SQCREG1_ConvertDC_UC_bits 1 #define GFX7_L3SQCREG1_ConvertDC_UC_bits 1 static inline uint32_t ATTRIBUTE_PURE L3SQCREG1_ConvertDC_UC_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_L3SQCREG1_ConvertDC_UC_start 24 #define GFX7_L3SQCREG1_ConvertDC_UC_start 24 static inline uint32_t ATTRIBUTE_PURE L3SQCREG1_ConvertDC_UC_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 24; case 70: return 24; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* L3SQCREG1::Convert IS_UC */ #define GFX75_L3SQCREG1_ConvertIS_UC_bits 1 #define GFX7_L3SQCREG1_ConvertIS_UC_bits 1 static inline uint32_t ATTRIBUTE_PURE L3SQCREG1_ConvertIS_UC_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_L3SQCREG1_ConvertIS_UC_start 25 #define GFX7_L3SQCREG1_ConvertIS_UC_start 25 static inline uint32_t ATTRIBUTE_PURE L3SQCREG1_ConvertIS_UC_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 25; case 70: return 25; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* L3SQCREG1::Convert T_UC */ #define GFX75_L3SQCREG1_ConvertT_UC_bits 1 #define GFX7_L3SQCREG1_ConvertT_UC_bits 1 static inline uint32_t ATTRIBUTE_PURE L3SQCREG1_ConvertT_UC_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_L3SQCREG1_ConvertT_UC_start 27 #define GFX7_L3SQCREG1_ConvertT_UC_start 27 static inline uint32_t ATTRIBUTE_PURE L3SQCREG1_ConvertT_UC_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 27; case 70: return 27; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* L3SQCREG1::L3SQ General Priority Credit Initialization */ #define GFX75_L3SQCREG1_L3SQGeneralPriorityCreditInitialization_bits 5 #define GFX7_L3SQCREG1_L3SQGeneralPriorityCreditInitialization_bits 4 static inline uint32_t ATTRIBUTE_PURE L3SQCREG1_L3SQGeneralPriorityCreditInitialization_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 5; case 70: return 4; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_L3SQCREG1_L3SQGeneralPriorityCreditInitialization_start 19 #define GFX7_L3SQCREG1_L3SQGeneralPriorityCreditInitialization_start 20 static inline uint32_t ATTRIBUTE_PURE L3SQCREG1_L3SQGeneralPriorityCreditInitialization_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 19; case 70: return 20; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* L3SQCREG1::L3SQ High Priority Credit Initialization */ #define GFX75_L3SQCREG1_L3SQHighPriorityCreditInitialization_bits 5 #define GFX7_L3SQCREG1_L3SQHighPriorityCreditInitialization_bits 4 static inline uint32_t ATTRIBUTE_PURE L3SQCREG1_L3SQHighPriorityCreditInitialization_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 5; case 70: return 4; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_L3SQCREG1_L3SQHighPriorityCreditInitialization_start 14 #define GFX7_L3SQCREG1_L3SQHighPriorityCreditInitialization_start 16 static inline uint32_t ATTRIBUTE_PURE L3SQCREG1_L3SQHighPriorityCreditInitialization_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 14; case 70: return 16; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* LUMA_FILTER_COEFFICIENTS_ARRAY */ #define GFX125_LUMA_FILTER_COEFFICIENTS_ARRAY_length 4 #define GFX12_LUMA_FILTER_COEFFICIENTS_ARRAY_length 4 #define GFX11_LUMA_FILTER_COEFFICIENTS_ARRAY_length 4 static inline uint32_t ATTRIBUTE_PURE LUMA_FILTER_COEFFICIENTS_ARRAY_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* LUMA_FILTER_COEFFICIENTS_ARRAY::Table 0X Filter Coefficient[[n],0] */ #define GFX125_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0XFilterCoefficientn0_bits 8 #define GFX12_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0XFilterCoefficientn0_bits 8 #define GFX11_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0XFilterCoefficientn0_bits 8 static inline uint32_t ATTRIBUTE_PURE LUMA_FILTER_COEFFICIENTS_ARRAY_Table0XFilterCoefficientn0_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0XFilterCoefficientn0_start 0 #define GFX12_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0XFilterCoefficientn0_start 0 #define GFX11_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0XFilterCoefficientn0_start 0 static inline uint32_t ATTRIBUTE_PURE LUMA_FILTER_COEFFICIENTS_ARRAY_Table0XFilterCoefficientn0_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* LUMA_FILTER_COEFFICIENTS_ARRAY::Table 0X Filter Coefficient[[n],1] */ #define GFX125_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0XFilterCoefficientn1_bits 8 #define GFX12_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0XFilterCoefficientn1_bits 8 #define GFX11_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0XFilterCoefficientn1_bits 8 static inline uint32_t ATTRIBUTE_PURE LUMA_FILTER_COEFFICIENTS_ARRAY_Table0XFilterCoefficientn1_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0XFilterCoefficientn1_start 16 #define GFX12_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0XFilterCoefficientn1_start 16 #define GFX11_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0XFilterCoefficientn1_start 16 static inline uint32_t ATTRIBUTE_PURE LUMA_FILTER_COEFFICIENTS_ARRAY_Table0XFilterCoefficientn1_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* LUMA_FILTER_COEFFICIENTS_ARRAY::Table 0X Filter Coefficient[[n],2] */ #define GFX125_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0XFilterCoefficientn2_bits 8 #define GFX12_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0XFilterCoefficientn2_bits 8 #define GFX11_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0XFilterCoefficientn2_bits 8 static inline uint32_t ATTRIBUTE_PURE LUMA_FILTER_COEFFICIENTS_ARRAY_Table0XFilterCoefficientn2_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0XFilterCoefficientn2_start 32 #define GFX12_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0XFilterCoefficientn2_start 32 #define GFX11_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0XFilterCoefficientn2_start 32 static inline uint32_t ATTRIBUTE_PURE LUMA_FILTER_COEFFICIENTS_ARRAY_Table0XFilterCoefficientn2_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* LUMA_FILTER_COEFFICIENTS_ARRAY::Table 0X Filter Coefficient[[n],3] */ #define GFX125_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0XFilterCoefficientn3_bits 8 #define GFX12_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0XFilterCoefficientn3_bits 8 #define GFX11_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0XFilterCoefficientn3_bits 8 static inline uint32_t ATTRIBUTE_PURE LUMA_FILTER_COEFFICIENTS_ARRAY_Table0XFilterCoefficientn3_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0XFilterCoefficientn3_start 48 #define GFX12_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0XFilterCoefficientn3_start 48 #define GFX11_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0XFilterCoefficientn3_start 48 static inline uint32_t ATTRIBUTE_PURE LUMA_FILTER_COEFFICIENTS_ARRAY_Table0XFilterCoefficientn3_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 48; case 120: return 48; case 110: return 48; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* LUMA_FILTER_COEFFICIENTS_ARRAY::Table 0X Filter Coefficient[[n],4] */ #define GFX125_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0XFilterCoefficientn4_bits 8 #define GFX12_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0XFilterCoefficientn4_bits 8 #define GFX11_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0XFilterCoefficientn4_bits 8 static inline uint32_t ATTRIBUTE_PURE LUMA_FILTER_COEFFICIENTS_ARRAY_Table0XFilterCoefficientn4_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0XFilterCoefficientn4_start 64 #define GFX12_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0XFilterCoefficientn4_start 64 #define GFX11_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0XFilterCoefficientn4_start 64 static inline uint32_t ATTRIBUTE_PURE LUMA_FILTER_COEFFICIENTS_ARRAY_Table0XFilterCoefficientn4_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* LUMA_FILTER_COEFFICIENTS_ARRAY::Table 0X Filter Coefficient[[n],5] */ #define GFX125_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0XFilterCoefficientn5_bits 8 #define GFX12_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0XFilterCoefficientn5_bits 8 #define GFX11_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0XFilterCoefficientn5_bits 8 static inline uint32_t ATTRIBUTE_PURE LUMA_FILTER_COEFFICIENTS_ARRAY_Table0XFilterCoefficientn5_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0XFilterCoefficientn5_start 80 #define GFX12_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0XFilterCoefficientn5_start 80 #define GFX11_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0XFilterCoefficientn5_start 80 static inline uint32_t ATTRIBUTE_PURE LUMA_FILTER_COEFFICIENTS_ARRAY_Table0XFilterCoefficientn5_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 80; case 120: return 80; case 110: return 80; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* LUMA_FILTER_COEFFICIENTS_ARRAY::Table 0X Filter Coefficient[[n],6] */ #define GFX125_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0XFilterCoefficientn6_bits 8 #define GFX12_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0XFilterCoefficientn6_bits 8 #define GFX11_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0XFilterCoefficientn6_bits 8 static inline uint32_t ATTRIBUTE_PURE LUMA_FILTER_COEFFICIENTS_ARRAY_Table0XFilterCoefficientn6_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0XFilterCoefficientn6_start 96 #define GFX12_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0XFilterCoefficientn6_start 96 #define GFX11_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0XFilterCoefficientn6_start 96 static inline uint32_t ATTRIBUTE_PURE LUMA_FILTER_COEFFICIENTS_ARRAY_Table0XFilterCoefficientn6_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 96; case 120: return 96; case 110: return 96; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* LUMA_FILTER_COEFFICIENTS_ARRAY::Table 0X Filter Coefficient[[n],7] */ #define GFX125_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0XFilterCoefficientn7_bits 8 #define GFX12_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0XFilterCoefficientn7_bits 8 #define GFX11_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0XFilterCoefficientn7_bits 8 static inline uint32_t ATTRIBUTE_PURE LUMA_FILTER_COEFFICIENTS_ARRAY_Table0XFilterCoefficientn7_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0XFilterCoefficientn7_start 112 #define GFX12_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0XFilterCoefficientn7_start 112 #define GFX11_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0XFilterCoefficientn7_start 112 static inline uint32_t ATTRIBUTE_PURE LUMA_FILTER_COEFFICIENTS_ARRAY_Table0XFilterCoefficientn7_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 112; case 120: return 112; case 110: return 112; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* LUMA_FILTER_COEFFICIENTS_ARRAY::Table 0Y Filter Coefficient[[n],0] */ #define GFX125_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0YFilterCoefficientn0_bits 8 #define GFX12_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0YFilterCoefficientn0_bits 8 #define GFX11_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0YFilterCoefficientn0_bits 8 static inline uint32_t ATTRIBUTE_PURE LUMA_FILTER_COEFFICIENTS_ARRAY_Table0YFilterCoefficientn0_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0YFilterCoefficientn0_start 8 #define GFX12_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0YFilterCoefficientn0_start 8 #define GFX11_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0YFilterCoefficientn0_start 8 static inline uint32_t ATTRIBUTE_PURE LUMA_FILTER_COEFFICIENTS_ARRAY_Table0YFilterCoefficientn0_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* LUMA_FILTER_COEFFICIENTS_ARRAY::Table 0Y Filter Coefficient[[n],1] */ #define GFX125_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0YFilterCoefficientn1_bits 8 #define GFX12_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0YFilterCoefficientn1_bits 8 #define GFX11_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0YFilterCoefficientn1_bits 8 static inline uint32_t ATTRIBUTE_PURE LUMA_FILTER_COEFFICIENTS_ARRAY_Table0YFilterCoefficientn1_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0YFilterCoefficientn1_start 24 #define GFX12_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0YFilterCoefficientn1_start 24 #define GFX11_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0YFilterCoefficientn1_start 24 static inline uint32_t ATTRIBUTE_PURE LUMA_FILTER_COEFFICIENTS_ARRAY_Table0YFilterCoefficientn1_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* LUMA_FILTER_COEFFICIENTS_ARRAY::Table 0Y Filter Coefficient[[n],2] */ #define GFX125_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0YFilterCoefficientn2_bits 8 #define GFX12_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0YFilterCoefficientn2_bits 8 #define GFX11_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0YFilterCoefficientn2_bits 8 static inline uint32_t ATTRIBUTE_PURE LUMA_FILTER_COEFFICIENTS_ARRAY_Table0YFilterCoefficientn2_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0YFilterCoefficientn2_start 40 #define GFX12_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0YFilterCoefficientn2_start 40 #define GFX11_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0YFilterCoefficientn2_start 40 static inline uint32_t ATTRIBUTE_PURE LUMA_FILTER_COEFFICIENTS_ARRAY_Table0YFilterCoefficientn2_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 40; case 120: return 40; case 110: return 40; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* LUMA_FILTER_COEFFICIENTS_ARRAY::Table 0Y Filter Coefficient[[n],3] */ #define GFX125_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0YFilterCoefficientn3_bits 8 #define GFX12_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0YFilterCoefficientn3_bits 8 #define GFX11_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0YFilterCoefficientn3_bits 8 static inline uint32_t ATTRIBUTE_PURE LUMA_FILTER_COEFFICIENTS_ARRAY_Table0YFilterCoefficientn3_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0YFilterCoefficientn3_start 56 #define GFX12_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0YFilterCoefficientn3_start 56 #define GFX11_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0YFilterCoefficientn3_start 56 static inline uint32_t ATTRIBUTE_PURE LUMA_FILTER_COEFFICIENTS_ARRAY_Table0YFilterCoefficientn3_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 56; case 120: return 56; case 110: return 56; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* LUMA_FILTER_COEFFICIENTS_ARRAY::Table 0Y Filter Coefficient[[n],4] */ #define GFX125_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0YFilterCoefficientn4_bits 8 #define GFX12_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0YFilterCoefficientn4_bits 8 #define GFX11_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0YFilterCoefficientn4_bits 8 static inline uint32_t ATTRIBUTE_PURE LUMA_FILTER_COEFFICIENTS_ARRAY_Table0YFilterCoefficientn4_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0YFilterCoefficientn4_start 72 #define GFX12_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0YFilterCoefficientn4_start 72 #define GFX11_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0YFilterCoefficientn4_start 72 static inline uint32_t ATTRIBUTE_PURE LUMA_FILTER_COEFFICIENTS_ARRAY_Table0YFilterCoefficientn4_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 72; case 120: return 72; case 110: return 72; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* LUMA_FILTER_COEFFICIENTS_ARRAY::Table 0Y Filter Coefficient[[n],5] */ #define GFX125_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0YFilterCoefficientn5_bits 8 #define GFX12_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0YFilterCoefficientn5_bits 8 #define GFX11_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0YFilterCoefficientn5_bits 8 static inline uint32_t ATTRIBUTE_PURE LUMA_FILTER_COEFFICIENTS_ARRAY_Table0YFilterCoefficientn5_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0YFilterCoefficientn5_start 88 #define GFX12_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0YFilterCoefficientn5_start 88 #define GFX11_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0YFilterCoefficientn5_start 88 static inline uint32_t ATTRIBUTE_PURE LUMA_FILTER_COEFFICIENTS_ARRAY_Table0YFilterCoefficientn5_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 88; case 120: return 88; case 110: return 88; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* LUMA_FILTER_COEFFICIENTS_ARRAY::Table 0Y Filter Coefficient[[n],6] */ #define GFX125_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0YFilterCoefficientn6_bits 8 #define GFX12_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0YFilterCoefficientn6_bits 8 #define GFX11_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0YFilterCoefficientn6_bits 8 static inline uint32_t ATTRIBUTE_PURE LUMA_FILTER_COEFFICIENTS_ARRAY_Table0YFilterCoefficientn6_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0YFilterCoefficientn6_start 104 #define GFX12_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0YFilterCoefficientn6_start 104 #define GFX11_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0YFilterCoefficientn6_start 104 static inline uint32_t ATTRIBUTE_PURE LUMA_FILTER_COEFFICIENTS_ARRAY_Table0YFilterCoefficientn6_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 104; case 120: return 104; case 110: return 104; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* LUMA_FILTER_COEFFICIENTS_ARRAY::Table 0Y Filter Coefficient[[n],7] */ #define GFX125_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0YFilterCoefficientn7_bits 8 #define GFX12_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0YFilterCoefficientn7_bits 8 #define GFX11_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0YFilterCoefficientn7_bits 8 static inline uint32_t ATTRIBUTE_PURE LUMA_FILTER_COEFFICIENTS_ARRAY_Table0YFilterCoefficientn7_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0YFilterCoefficientn7_start 120 #define GFX12_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0YFilterCoefficientn7_start 120 #define GFX11_LUMA_FILTER_COEFFICIENTS_ARRAY_Table0YFilterCoefficientn7_start 120 static inline uint32_t ATTRIBUTE_PURE LUMA_FILTER_COEFFICIENTS_ARRAY_Table0YFilterCoefficientn7_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 120; case 120: return 120; case 110: return 120; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_CURBE_LOAD */ #define GFX12_MEDIA_CURBE_LOAD_length 4 #define GFX11_MEDIA_CURBE_LOAD_length 4 #define GFX9_MEDIA_CURBE_LOAD_length 4 #define GFX8_MEDIA_CURBE_LOAD_length 4 #define GFX75_MEDIA_CURBE_LOAD_length 4 #define GFX7_MEDIA_CURBE_LOAD_length 4 #define GFX6_MEDIA_CURBE_LOAD_length 4 static inline uint32_t ATTRIBUTE_PURE MEDIA_CURBE_LOAD_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 4; case 70: return 4; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_CURBE_LOAD::CURBE Data Start Address */ #define GFX12_MEDIA_CURBE_LOAD_CURBEDataStartAddress_bits 32 #define GFX11_MEDIA_CURBE_LOAD_CURBEDataStartAddress_bits 32 #define GFX9_MEDIA_CURBE_LOAD_CURBEDataStartAddress_bits 32 #define GFX8_MEDIA_CURBE_LOAD_CURBEDataStartAddress_bits 32 #define GFX75_MEDIA_CURBE_LOAD_CURBEDataStartAddress_bits 32 #define GFX7_MEDIA_CURBE_LOAD_CURBEDataStartAddress_bits 32 #define GFX6_MEDIA_CURBE_LOAD_CURBEDataStartAddress_bits 32 static inline uint32_t ATTRIBUTE_PURE MEDIA_CURBE_LOAD_CURBEDataStartAddress_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 32; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_CURBE_LOAD_CURBEDataStartAddress_start 96 #define GFX11_MEDIA_CURBE_LOAD_CURBEDataStartAddress_start 96 #define GFX9_MEDIA_CURBE_LOAD_CURBEDataStartAddress_start 96 #define GFX8_MEDIA_CURBE_LOAD_CURBEDataStartAddress_start 96 #define GFX75_MEDIA_CURBE_LOAD_CURBEDataStartAddress_start 96 #define GFX7_MEDIA_CURBE_LOAD_CURBEDataStartAddress_start 96 #define GFX6_MEDIA_CURBE_LOAD_CURBEDataStartAddress_start 96 static inline uint32_t ATTRIBUTE_PURE MEDIA_CURBE_LOAD_CURBEDataStartAddress_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 96; case 110: return 96; case 90: return 96; case 80: return 96; case 75: return 96; case 70: return 96; case 60: return 96; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_CURBE_LOAD::CURBE Total Data Length */ #define GFX12_MEDIA_CURBE_LOAD_CURBETotalDataLength_bits 17 #define GFX11_MEDIA_CURBE_LOAD_CURBETotalDataLength_bits 17 #define GFX9_MEDIA_CURBE_LOAD_CURBETotalDataLength_bits 17 #define GFX8_MEDIA_CURBE_LOAD_CURBETotalDataLength_bits 17 #define GFX75_MEDIA_CURBE_LOAD_CURBETotalDataLength_bits 17 #define GFX7_MEDIA_CURBE_LOAD_CURBETotalDataLength_bits 17 #define GFX6_MEDIA_CURBE_LOAD_CURBETotalDataLength_bits 17 static inline uint32_t ATTRIBUTE_PURE MEDIA_CURBE_LOAD_CURBETotalDataLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 17; case 110: return 17; case 90: return 17; case 80: return 17; case 75: return 17; case 70: return 17; case 60: return 17; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_CURBE_LOAD_CURBETotalDataLength_start 64 #define GFX11_MEDIA_CURBE_LOAD_CURBETotalDataLength_start 64 #define GFX9_MEDIA_CURBE_LOAD_CURBETotalDataLength_start 64 #define GFX8_MEDIA_CURBE_LOAD_CURBETotalDataLength_start 64 #define GFX75_MEDIA_CURBE_LOAD_CURBETotalDataLength_start 64 #define GFX7_MEDIA_CURBE_LOAD_CURBETotalDataLength_start 64 #define GFX6_MEDIA_CURBE_LOAD_CURBETotalDataLength_start 64 static inline uint32_t ATTRIBUTE_PURE MEDIA_CURBE_LOAD_CURBETotalDataLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 64; case 110: return 64; case 90: return 64; case 80: return 64; case 75: return 64; case 70: return 64; case 60: return 64; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_CURBE_LOAD::Command Type */ #define GFX12_MEDIA_CURBE_LOAD_CommandType_bits 3 #define GFX11_MEDIA_CURBE_LOAD_CommandType_bits 3 #define GFX9_MEDIA_CURBE_LOAD_CommandType_bits 3 #define GFX8_MEDIA_CURBE_LOAD_CommandType_bits 3 #define GFX75_MEDIA_CURBE_LOAD_CommandType_bits 3 #define GFX7_MEDIA_CURBE_LOAD_CommandType_bits 3 #define GFX6_MEDIA_CURBE_LOAD_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE MEDIA_CURBE_LOAD_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_CURBE_LOAD_CommandType_start 29 #define GFX11_MEDIA_CURBE_LOAD_CommandType_start 29 #define GFX9_MEDIA_CURBE_LOAD_CommandType_start 29 #define GFX8_MEDIA_CURBE_LOAD_CommandType_start 29 #define GFX75_MEDIA_CURBE_LOAD_CommandType_start 29 #define GFX7_MEDIA_CURBE_LOAD_CommandType_start 29 #define GFX6_MEDIA_CURBE_LOAD_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE MEDIA_CURBE_LOAD_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 29; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_CURBE_LOAD::DWord Length */ #define GFX12_MEDIA_CURBE_LOAD_DWordLength_bits 16 #define GFX11_MEDIA_CURBE_LOAD_DWordLength_bits 16 #define GFX9_MEDIA_CURBE_LOAD_DWordLength_bits 16 #define GFX8_MEDIA_CURBE_LOAD_DWordLength_bits 16 #define GFX75_MEDIA_CURBE_LOAD_DWordLength_bits 16 #define GFX7_MEDIA_CURBE_LOAD_DWordLength_bits 16 #define GFX6_MEDIA_CURBE_LOAD_DWordLength_bits 16 static inline uint32_t ATTRIBUTE_PURE MEDIA_CURBE_LOAD_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 16; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_CURBE_LOAD_DWordLength_start 0 #define GFX11_MEDIA_CURBE_LOAD_DWordLength_start 0 #define GFX9_MEDIA_CURBE_LOAD_DWordLength_start 0 #define GFX8_MEDIA_CURBE_LOAD_DWordLength_start 0 #define GFX75_MEDIA_CURBE_LOAD_DWordLength_start 0 #define GFX7_MEDIA_CURBE_LOAD_DWordLength_start 0 #define GFX6_MEDIA_CURBE_LOAD_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE MEDIA_CURBE_LOAD_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_CURBE_LOAD::Media Command Opcode */ #define GFX12_MEDIA_CURBE_LOAD_MediaCommandOpcode_bits 3 #define GFX11_MEDIA_CURBE_LOAD_MediaCommandOpcode_bits 3 #define GFX9_MEDIA_CURBE_LOAD_MediaCommandOpcode_bits 3 #define GFX8_MEDIA_CURBE_LOAD_MediaCommandOpcode_bits 3 #define GFX75_MEDIA_CURBE_LOAD_MediaCommandOpcode_bits 3 #define GFX7_MEDIA_CURBE_LOAD_MediaCommandOpcode_bits 3 #define GFX6_MEDIA_CURBE_LOAD_MediaCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE MEDIA_CURBE_LOAD_MediaCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_CURBE_LOAD_MediaCommandOpcode_start 24 #define GFX11_MEDIA_CURBE_LOAD_MediaCommandOpcode_start 24 #define GFX9_MEDIA_CURBE_LOAD_MediaCommandOpcode_start 24 #define GFX8_MEDIA_CURBE_LOAD_MediaCommandOpcode_start 24 #define GFX75_MEDIA_CURBE_LOAD_MediaCommandOpcode_start 24 #define GFX7_MEDIA_CURBE_LOAD_MediaCommandOpcode_start 24 #define GFX6_MEDIA_CURBE_LOAD_MediaCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE MEDIA_CURBE_LOAD_MediaCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 24; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_CURBE_LOAD::Pipeline */ #define GFX12_MEDIA_CURBE_LOAD_Pipeline_bits 2 #define GFX11_MEDIA_CURBE_LOAD_Pipeline_bits 2 #define GFX9_MEDIA_CURBE_LOAD_Pipeline_bits 2 #define GFX8_MEDIA_CURBE_LOAD_Pipeline_bits 2 #define GFX75_MEDIA_CURBE_LOAD_Pipeline_bits 2 #define GFX7_MEDIA_CURBE_LOAD_Pipeline_bits 2 #define GFX6_MEDIA_CURBE_LOAD_Pipeline_bits 2 static inline uint32_t ATTRIBUTE_PURE MEDIA_CURBE_LOAD_Pipeline_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_CURBE_LOAD_Pipeline_start 27 #define GFX11_MEDIA_CURBE_LOAD_Pipeline_start 27 #define GFX9_MEDIA_CURBE_LOAD_Pipeline_start 27 #define GFX8_MEDIA_CURBE_LOAD_Pipeline_start 27 #define GFX75_MEDIA_CURBE_LOAD_Pipeline_start 27 #define GFX7_MEDIA_CURBE_LOAD_Pipeline_start 27 #define GFX6_MEDIA_CURBE_LOAD_Pipeline_start 27 static inline uint32_t ATTRIBUTE_PURE MEDIA_CURBE_LOAD_Pipeline_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 27; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_CURBE_LOAD::SubOpcode */ #define GFX12_MEDIA_CURBE_LOAD_SubOpcode_bits 8 #define GFX11_MEDIA_CURBE_LOAD_SubOpcode_bits 8 #define GFX9_MEDIA_CURBE_LOAD_SubOpcode_bits 8 #define GFX8_MEDIA_CURBE_LOAD_SubOpcode_bits 8 #define GFX75_MEDIA_CURBE_LOAD_SubOpcode_bits 8 #define GFX7_MEDIA_CURBE_LOAD_SubOpcode_bits 8 #define GFX6_MEDIA_CURBE_LOAD_SubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE MEDIA_CURBE_LOAD_SubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_CURBE_LOAD_SubOpcode_start 16 #define GFX11_MEDIA_CURBE_LOAD_SubOpcode_start 16 #define GFX9_MEDIA_CURBE_LOAD_SubOpcode_start 16 #define GFX8_MEDIA_CURBE_LOAD_SubOpcode_start 16 #define GFX75_MEDIA_CURBE_LOAD_SubOpcode_start 16 #define GFX7_MEDIA_CURBE_LOAD_SubOpcode_start 16 #define GFX6_MEDIA_CURBE_LOAD_SubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE MEDIA_CURBE_LOAD_SubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 16; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_GATEWAY_STATE */ #define GFX6_MEDIA_GATEWAY_STATE_length 2 static inline uint32_t ATTRIBUTE_PURE MEDIA_GATEWAY_STATE_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_GATEWAY_STATE::Barrier.Byte */ #define GFX6_MEDIA_GATEWAY_STATE_BarrierByte_bits 8 static inline uint32_t ATTRIBUTE_PURE MEDIA_GATEWAY_STATE_BarrierByte_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_MEDIA_GATEWAY_STATE_BarrierByte_start 40 static inline uint32_t ATTRIBUTE_PURE MEDIA_GATEWAY_STATE_BarrierByte_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 40; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_GATEWAY_STATE::BarrierID */ #define GFX6_MEDIA_GATEWAY_STATE_BarrierID_bits 8 static inline uint32_t ATTRIBUTE_PURE MEDIA_GATEWAY_STATE_BarrierID_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_MEDIA_GATEWAY_STATE_BarrierID_start 48 static inline uint32_t ATTRIBUTE_PURE MEDIA_GATEWAY_STATE_BarrierID_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 48; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_GATEWAY_STATE::Barrier.ThreadCount */ #define GFX6_MEDIA_GATEWAY_STATE_BarrierThreadCount_bits 8 static inline uint32_t ATTRIBUTE_PURE MEDIA_GATEWAY_STATE_BarrierThreadCount_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_MEDIA_GATEWAY_STATE_BarrierThreadCount_start 32 static inline uint32_t ATTRIBUTE_PURE MEDIA_GATEWAY_STATE_BarrierThreadCount_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 32; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_GATEWAY_STATE::Command Type */ #define GFX6_MEDIA_GATEWAY_STATE_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE MEDIA_GATEWAY_STATE_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_MEDIA_GATEWAY_STATE_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE MEDIA_GATEWAY_STATE_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 29; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_GATEWAY_STATE::DWord Length */ #define GFX6_MEDIA_GATEWAY_STATE_DWordLength_bits 16 static inline uint32_t ATTRIBUTE_PURE MEDIA_GATEWAY_STATE_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 16; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_MEDIA_GATEWAY_STATE_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE MEDIA_GATEWAY_STATE_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_GATEWAY_STATE::Media Command Opcode */ #define GFX6_MEDIA_GATEWAY_STATE_MediaCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE MEDIA_GATEWAY_STATE_MediaCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_MEDIA_GATEWAY_STATE_MediaCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE MEDIA_GATEWAY_STATE_MediaCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 24; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_GATEWAY_STATE::Pipeline */ #define GFX6_MEDIA_GATEWAY_STATE_Pipeline_bits 2 static inline uint32_t ATTRIBUTE_PURE MEDIA_GATEWAY_STATE_Pipeline_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_MEDIA_GATEWAY_STATE_Pipeline_start 27 static inline uint32_t ATTRIBUTE_PURE MEDIA_GATEWAY_STATE_Pipeline_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 27; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_GATEWAY_STATE::SubOpcode */ #define GFX6_MEDIA_GATEWAY_STATE_SubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE MEDIA_GATEWAY_STATE_SubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_MEDIA_GATEWAY_STATE_SubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE MEDIA_GATEWAY_STATE_SubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 16; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_INTERFACE_DESCRIPTOR_LOAD */ #define GFX12_MEDIA_INTERFACE_DESCRIPTOR_LOAD_length 4 #define GFX11_MEDIA_INTERFACE_DESCRIPTOR_LOAD_length 4 #define GFX9_MEDIA_INTERFACE_DESCRIPTOR_LOAD_length 4 #define GFX8_MEDIA_INTERFACE_DESCRIPTOR_LOAD_length 4 #define GFX75_MEDIA_INTERFACE_DESCRIPTOR_LOAD_length 4 #define GFX7_MEDIA_INTERFACE_DESCRIPTOR_LOAD_length 4 #define GFX6_MEDIA_INTERFACE_DESCRIPTOR_LOAD_length 4 static inline uint32_t ATTRIBUTE_PURE MEDIA_INTERFACE_DESCRIPTOR_LOAD_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 4; case 70: return 4; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_INTERFACE_DESCRIPTOR_LOAD::Command Type */ #define GFX12_MEDIA_INTERFACE_DESCRIPTOR_LOAD_CommandType_bits 3 #define GFX11_MEDIA_INTERFACE_DESCRIPTOR_LOAD_CommandType_bits 3 #define GFX9_MEDIA_INTERFACE_DESCRIPTOR_LOAD_CommandType_bits 3 #define GFX8_MEDIA_INTERFACE_DESCRIPTOR_LOAD_CommandType_bits 3 #define GFX75_MEDIA_INTERFACE_DESCRIPTOR_LOAD_CommandType_bits 3 #define GFX7_MEDIA_INTERFACE_DESCRIPTOR_LOAD_CommandType_bits 3 #define GFX6_MEDIA_INTERFACE_DESCRIPTOR_LOAD_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE MEDIA_INTERFACE_DESCRIPTOR_LOAD_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_INTERFACE_DESCRIPTOR_LOAD_CommandType_start 29 #define GFX11_MEDIA_INTERFACE_DESCRIPTOR_LOAD_CommandType_start 29 #define GFX9_MEDIA_INTERFACE_DESCRIPTOR_LOAD_CommandType_start 29 #define GFX8_MEDIA_INTERFACE_DESCRIPTOR_LOAD_CommandType_start 29 #define GFX75_MEDIA_INTERFACE_DESCRIPTOR_LOAD_CommandType_start 29 #define GFX7_MEDIA_INTERFACE_DESCRIPTOR_LOAD_CommandType_start 29 #define GFX6_MEDIA_INTERFACE_DESCRIPTOR_LOAD_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE MEDIA_INTERFACE_DESCRIPTOR_LOAD_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 29; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_INTERFACE_DESCRIPTOR_LOAD::DWord Length */ #define GFX12_MEDIA_INTERFACE_DESCRIPTOR_LOAD_DWordLength_bits 16 #define GFX11_MEDIA_INTERFACE_DESCRIPTOR_LOAD_DWordLength_bits 16 #define GFX9_MEDIA_INTERFACE_DESCRIPTOR_LOAD_DWordLength_bits 16 #define GFX8_MEDIA_INTERFACE_DESCRIPTOR_LOAD_DWordLength_bits 16 #define GFX75_MEDIA_INTERFACE_DESCRIPTOR_LOAD_DWordLength_bits 16 #define GFX7_MEDIA_INTERFACE_DESCRIPTOR_LOAD_DWordLength_bits 16 #define GFX6_MEDIA_INTERFACE_DESCRIPTOR_LOAD_DWordLength_bits 16 static inline uint32_t ATTRIBUTE_PURE MEDIA_INTERFACE_DESCRIPTOR_LOAD_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 16; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_INTERFACE_DESCRIPTOR_LOAD_DWordLength_start 0 #define GFX11_MEDIA_INTERFACE_DESCRIPTOR_LOAD_DWordLength_start 0 #define GFX9_MEDIA_INTERFACE_DESCRIPTOR_LOAD_DWordLength_start 0 #define GFX8_MEDIA_INTERFACE_DESCRIPTOR_LOAD_DWordLength_start 0 #define GFX75_MEDIA_INTERFACE_DESCRIPTOR_LOAD_DWordLength_start 0 #define GFX7_MEDIA_INTERFACE_DESCRIPTOR_LOAD_DWordLength_start 0 #define GFX6_MEDIA_INTERFACE_DESCRIPTOR_LOAD_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE MEDIA_INTERFACE_DESCRIPTOR_LOAD_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_INTERFACE_DESCRIPTOR_LOAD::Interface Descriptor Data Start Address */ #define GFX12_MEDIA_INTERFACE_DESCRIPTOR_LOAD_InterfaceDescriptorDataStartAddress_bits 32 #define GFX11_MEDIA_INTERFACE_DESCRIPTOR_LOAD_InterfaceDescriptorDataStartAddress_bits 32 #define GFX9_MEDIA_INTERFACE_DESCRIPTOR_LOAD_InterfaceDescriptorDataStartAddress_bits 32 #define GFX8_MEDIA_INTERFACE_DESCRIPTOR_LOAD_InterfaceDescriptorDataStartAddress_bits 32 #define GFX75_MEDIA_INTERFACE_DESCRIPTOR_LOAD_InterfaceDescriptorDataStartAddress_bits 32 #define GFX7_MEDIA_INTERFACE_DESCRIPTOR_LOAD_InterfaceDescriptorDataStartAddress_bits 32 #define GFX6_MEDIA_INTERFACE_DESCRIPTOR_LOAD_InterfaceDescriptorDataStartAddress_bits 32 static inline uint32_t ATTRIBUTE_PURE MEDIA_INTERFACE_DESCRIPTOR_LOAD_InterfaceDescriptorDataStartAddress_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 32; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_INTERFACE_DESCRIPTOR_LOAD_InterfaceDescriptorDataStartAddress_start 96 #define GFX11_MEDIA_INTERFACE_DESCRIPTOR_LOAD_InterfaceDescriptorDataStartAddress_start 96 #define GFX9_MEDIA_INTERFACE_DESCRIPTOR_LOAD_InterfaceDescriptorDataStartAddress_start 96 #define GFX8_MEDIA_INTERFACE_DESCRIPTOR_LOAD_InterfaceDescriptorDataStartAddress_start 96 #define GFX75_MEDIA_INTERFACE_DESCRIPTOR_LOAD_InterfaceDescriptorDataStartAddress_start 96 #define GFX7_MEDIA_INTERFACE_DESCRIPTOR_LOAD_InterfaceDescriptorDataStartAddress_start 96 #define GFX6_MEDIA_INTERFACE_DESCRIPTOR_LOAD_InterfaceDescriptorDataStartAddress_start 96 static inline uint32_t ATTRIBUTE_PURE MEDIA_INTERFACE_DESCRIPTOR_LOAD_InterfaceDescriptorDataStartAddress_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 96; case 110: return 96; case 90: return 96; case 80: return 96; case 75: return 96; case 70: return 96; case 60: return 96; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_INTERFACE_DESCRIPTOR_LOAD::Interface Descriptor Total Length */ #define GFX12_MEDIA_INTERFACE_DESCRIPTOR_LOAD_InterfaceDescriptorTotalLength_bits 17 #define GFX11_MEDIA_INTERFACE_DESCRIPTOR_LOAD_InterfaceDescriptorTotalLength_bits 17 #define GFX9_MEDIA_INTERFACE_DESCRIPTOR_LOAD_InterfaceDescriptorTotalLength_bits 17 #define GFX8_MEDIA_INTERFACE_DESCRIPTOR_LOAD_InterfaceDescriptorTotalLength_bits 17 #define GFX75_MEDIA_INTERFACE_DESCRIPTOR_LOAD_InterfaceDescriptorTotalLength_bits 17 #define GFX7_MEDIA_INTERFACE_DESCRIPTOR_LOAD_InterfaceDescriptorTotalLength_bits 17 #define GFX6_MEDIA_INTERFACE_DESCRIPTOR_LOAD_InterfaceDescriptorTotalLength_bits 17 static inline uint32_t ATTRIBUTE_PURE MEDIA_INTERFACE_DESCRIPTOR_LOAD_InterfaceDescriptorTotalLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 17; case 110: return 17; case 90: return 17; case 80: return 17; case 75: return 17; case 70: return 17; case 60: return 17; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_INTERFACE_DESCRIPTOR_LOAD_InterfaceDescriptorTotalLength_start 64 #define GFX11_MEDIA_INTERFACE_DESCRIPTOR_LOAD_InterfaceDescriptorTotalLength_start 64 #define GFX9_MEDIA_INTERFACE_DESCRIPTOR_LOAD_InterfaceDescriptorTotalLength_start 64 #define GFX8_MEDIA_INTERFACE_DESCRIPTOR_LOAD_InterfaceDescriptorTotalLength_start 64 #define GFX75_MEDIA_INTERFACE_DESCRIPTOR_LOAD_InterfaceDescriptorTotalLength_start 64 #define GFX7_MEDIA_INTERFACE_DESCRIPTOR_LOAD_InterfaceDescriptorTotalLength_start 64 #define GFX6_MEDIA_INTERFACE_DESCRIPTOR_LOAD_InterfaceDescriptorTotalLength_start 64 static inline uint32_t ATTRIBUTE_PURE MEDIA_INTERFACE_DESCRIPTOR_LOAD_InterfaceDescriptorTotalLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 64; case 110: return 64; case 90: return 64; case 80: return 64; case 75: return 64; case 70: return 64; case 60: return 64; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_INTERFACE_DESCRIPTOR_LOAD::Media Command Opcode */ #define GFX12_MEDIA_INTERFACE_DESCRIPTOR_LOAD_MediaCommandOpcode_bits 3 #define GFX11_MEDIA_INTERFACE_DESCRIPTOR_LOAD_MediaCommandOpcode_bits 3 #define GFX9_MEDIA_INTERFACE_DESCRIPTOR_LOAD_MediaCommandOpcode_bits 3 #define GFX8_MEDIA_INTERFACE_DESCRIPTOR_LOAD_MediaCommandOpcode_bits 3 #define GFX75_MEDIA_INTERFACE_DESCRIPTOR_LOAD_MediaCommandOpcode_bits 3 #define GFX7_MEDIA_INTERFACE_DESCRIPTOR_LOAD_MediaCommandOpcode_bits 3 #define GFX6_MEDIA_INTERFACE_DESCRIPTOR_LOAD_MediaCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE MEDIA_INTERFACE_DESCRIPTOR_LOAD_MediaCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_INTERFACE_DESCRIPTOR_LOAD_MediaCommandOpcode_start 24 #define GFX11_MEDIA_INTERFACE_DESCRIPTOR_LOAD_MediaCommandOpcode_start 24 #define GFX9_MEDIA_INTERFACE_DESCRIPTOR_LOAD_MediaCommandOpcode_start 24 #define GFX8_MEDIA_INTERFACE_DESCRIPTOR_LOAD_MediaCommandOpcode_start 24 #define GFX75_MEDIA_INTERFACE_DESCRIPTOR_LOAD_MediaCommandOpcode_start 24 #define GFX7_MEDIA_INTERFACE_DESCRIPTOR_LOAD_MediaCommandOpcode_start 24 #define GFX6_MEDIA_INTERFACE_DESCRIPTOR_LOAD_MediaCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE MEDIA_INTERFACE_DESCRIPTOR_LOAD_MediaCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 24; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_INTERFACE_DESCRIPTOR_LOAD::Pipeline */ #define GFX12_MEDIA_INTERFACE_DESCRIPTOR_LOAD_Pipeline_bits 2 #define GFX11_MEDIA_INTERFACE_DESCRIPTOR_LOAD_Pipeline_bits 2 #define GFX9_MEDIA_INTERFACE_DESCRIPTOR_LOAD_Pipeline_bits 2 #define GFX8_MEDIA_INTERFACE_DESCRIPTOR_LOAD_Pipeline_bits 2 #define GFX75_MEDIA_INTERFACE_DESCRIPTOR_LOAD_Pipeline_bits 2 #define GFX7_MEDIA_INTERFACE_DESCRIPTOR_LOAD_Pipeline_bits 2 #define GFX6_MEDIA_INTERFACE_DESCRIPTOR_LOAD_Pipeline_bits 2 static inline uint32_t ATTRIBUTE_PURE MEDIA_INTERFACE_DESCRIPTOR_LOAD_Pipeline_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_INTERFACE_DESCRIPTOR_LOAD_Pipeline_start 27 #define GFX11_MEDIA_INTERFACE_DESCRIPTOR_LOAD_Pipeline_start 27 #define GFX9_MEDIA_INTERFACE_DESCRIPTOR_LOAD_Pipeline_start 27 #define GFX8_MEDIA_INTERFACE_DESCRIPTOR_LOAD_Pipeline_start 27 #define GFX75_MEDIA_INTERFACE_DESCRIPTOR_LOAD_Pipeline_start 27 #define GFX7_MEDIA_INTERFACE_DESCRIPTOR_LOAD_Pipeline_start 27 #define GFX6_MEDIA_INTERFACE_DESCRIPTOR_LOAD_Pipeline_start 27 static inline uint32_t ATTRIBUTE_PURE MEDIA_INTERFACE_DESCRIPTOR_LOAD_Pipeline_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 27; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_INTERFACE_DESCRIPTOR_LOAD::SubOpcode */ #define GFX12_MEDIA_INTERFACE_DESCRIPTOR_LOAD_SubOpcode_bits 8 #define GFX11_MEDIA_INTERFACE_DESCRIPTOR_LOAD_SubOpcode_bits 8 #define GFX9_MEDIA_INTERFACE_DESCRIPTOR_LOAD_SubOpcode_bits 8 #define GFX8_MEDIA_INTERFACE_DESCRIPTOR_LOAD_SubOpcode_bits 8 #define GFX75_MEDIA_INTERFACE_DESCRIPTOR_LOAD_SubOpcode_bits 8 #define GFX7_MEDIA_INTERFACE_DESCRIPTOR_LOAD_SubOpcode_bits 8 #define GFX6_MEDIA_INTERFACE_DESCRIPTOR_LOAD_SubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE MEDIA_INTERFACE_DESCRIPTOR_LOAD_SubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_INTERFACE_DESCRIPTOR_LOAD_SubOpcode_start 16 #define GFX11_MEDIA_INTERFACE_DESCRIPTOR_LOAD_SubOpcode_start 16 #define GFX9_MEDIA_INTERFACE_DESCRIPTOR_LOAD_SubOpcode_start 16 #define GFX8_MEDIA_INTERFACE_DESCRIPTOR_LOAD_SubOpcode_start 16 #define GFX75_MEDIA_INTERFACE_DESCRIPTOR_LOAD_SubOpcode_start 16 #define GFX7_MEDIA_INTERFACE_DESCRIPTOR_LOAD_SubOpcode_start 16 #define GFX6_MEDIA_INTERFACE_DESCRIPTOR_LOAD_SubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE MEDIA_INTERFACE_DESCRIPTOR_LOAD_SubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 16; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT */ /* MEDIA_OBJECT::Block Color */ #define GFX12_MEDIA_OBJECT_BlockColor_bits 8 #define GFX11_MEDIA_OBJECT_BlockColor_bits 8 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_BlockColor_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 8; case 110: return 8; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_OBJECT_BlockColor_start 176 #define GFX11_MEDIA_OBJECT_BlockColor_start 176 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_BlockColor_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 176; case 110: return 176; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT::Children Present */ #define GFX12_MEDIA_OBJECT_ChildrenPresent_bits 1 #define GFX11_MEDIA_OBJECT_ChildrenPresent_bits 1 #define GFX9_MEDIA_OBJECT_ChildrenPresent_bits 1 #define GFX8_MEDIA_OBJECT_ChildrenPresent_bits 1 #define GFX75_MEDIA_OBJECT_ChildrenPresent_bits 1 #define GFX7_MEDIA_OBJECT_ChildrenPresent_bits 1 #define GFX6_MEDIA_OBJECT_ChildrenPresent_bits 1 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_ChildrenPresent_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_OBJECT_ChildrenPresent_start 95 #define GFX11_MEDIA_OBJECT_ChildrenPresent_start 95 #define GFX9_MEDIA_OBJECT_ChildrenPresent_start 95 #define GFX8_MEDIA_OBJECT_ChildrenPresent_start 95 #define GFX75_MEDIA_OBJECT_ChildrenPresent_start 95 #define GFX7_MEDIA_OBJECT_ChildrenPresent_start 95 #define GFX6_MEDIA_OBJECT_ChildrenPresent_start 95 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_ChildrenPresent_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 95; case 110: return 95; case 90: return 95; case 80: return 95; case 75: return 95; case 70: return 95; case 60: return 95; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT::Command Type */ #define GFX12_MEDIA_OBJECT_CommandType_bits 3 #define GFX11_MEDIA_OBJECT_CommandType_bits 3 #define GFX9_MEDIA_OBJECT_CommandType_bits 3 #define GFX8_MEDIA_OBJECT_CommandType_bits 3 #define GFX75_MEDIA_OBJECT_CommandType_bits 3 #define GFX7_MEDIA_OBJECT_CommandType_bits 3 #define GFX6_MEDIA_OBJECT_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_OBJECT_CommandType_start 29 #define GFX11_MEDIA_OBJECT_CommandType_start 29 #define GFX9_MEDIA_OBJECT_CommandType_start 29 #define GFX8_MEDIA_OBJECT_CommandType_start 29 #define GFX75_MEDIA_OBJECT_CommandType_start 29 #define GFX7_MEDIA_OBJECT_CommandType_start 29 #define GFX6_MEDIA_OBJECT_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 29; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT::DWord Length */ #define GFX12_MEDIA_OBJECT_DWordLength_bits 15 #define GFX11_MEDIA_OBJECT_DWordLength_bits 15 #define GFX9_MEDIA_OBJECT_DWordLength_bits 16 #define GFX8_MEDIA_OBJECT_DWordLength_bits 16 #define GFX75_MEDIA_OBJECT_DWordLength_bits 16 #define GFX7_MEDIA_OBJECT_DWordLength_bits 16 #define GFX6_MEDIA_OBJECT_DWordLength_bits 16 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 15; case 110: return 15; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 16; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_OBJECT_DWordLength_start 0 #define GFX11_MEDIA_OBJECT_DWordLength_start 0 #define GFX9_MEDIA_OBJECT_DWordLength_start 0 #define GFX8_MEDIA_OBJECT_DWordLength_start 0 #define GFX75_MEDIA_OBJECT_DWordLength_start 0 #define GFX7_MEDIA_OBJECT_DWordLength_start 0 #define GFX6_MEDIA_OBJECT_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT::Force Destination */ #define GFX12_MEDIA_OBJECT_ForceDestination_bits 1 #define GFX11_MEDIA_OBJECT_ForceDestination_bits 1 #define GFX9_MEDIA_OBJECT_ForceDestination_bits 1 #define GFX8_MEDIA_OBJECT_ForceDestination_bits 1 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_ForceDestination_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_OBJECT_ForceDestination_start 86 #define GFX11_MEDIA_OBJECT_ForceDestination_start 86 #define GFX9_MEDIA_OBJECT_ForceDestination_start 86 #define GFX8_MEDIA_OBJECT_ForceDestination_start 86 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_ForceDestination_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 86; case 110: return 86; case 90: return 86; case 80: return 86; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT::Half-Slice Destination Select */ #define GFX75_MEDIA_OBJECT_HalfSliceDestinationSelect_bits 2 #define GFX7_MEDIA_OBJECT_HalfSliceDestinationSelect_bits 2 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_HalfSliceDestinationSelect_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_MEDIA_OBJECT_HalfSliceDestinationSelect_start 81 #define GFX7_MEDIA_OBJECT_HalfSliceDestinationSelect_start 81 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_HalfSliceDestinationSelect_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 81; case 70: return 81; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT::Indirect Data Length */ #define GFX12_MEDIA_OBJECT_IndirectDataLength_bits 17 #define GFX11_MEDIA_OBJECT_IndirectDataLength_bits 17 #define GFX9_MEDIA_OBJECT_IndirectDataLength_bits 17 #define GFX8_MEDIA_OBJECT_IndirectDataLength_bits 17 #define GFX75_MEDIA_OBJECT_IndirectDataLength_bits 17 #define GFX7_MEDIA_OBJECT_IndirectDataLength_bits 17 #define GFX6_MEDIA_OBJECT_IndirectDataLength_bits 17 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_IndirectDataLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 17; case 110: return 17; case 90: return 17; case 80: return 17; case 75: return 17; case 70: return 17; case 60: return 17; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_OBJECT_IndirectDataLength_start 64 #define GFX11_MEDIA_OBJECT_IndirectDataLength_start 64 #define GFX9_MEDIA_OBJECT_IndirectDataLength_start 64 #define GFX8_MEDIA_OBJECT_IndirectDataLength_start 64 #define GFX75_MEDIA_OBJECT_IndirectDataLength_start 64 #define GFX7_MEDIA_OBJECT_IndirectDataLength_start 64 #define GFX6_MEDIA_OBJECT_IndirectDataLength_start 64 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_IndirectDataLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 64; case 110: return 64; case 90: return 64; case 80: return 64; case 75: return 64; case 70: return 64; case 60: return 64; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT::Indirect Data Start Address */ #define GFX12_MEDIA_OBJECT_IndirectDataStartAddress_bits 32 #define GFX11_MEDIA_OBJECT_IndirectDataStartAddress_bits 32 #define GFX9_MEDIA_OBJECT_IndirectDataStartAddress_bits 32 #define GFX8_MEDIA_OBJECT_IndirectDataStartAddress_bits 32 #define GFX75_MEDIA_OBJECT_IndirectDataStartAddress_bits 32 #define GFX7_MEDIA_OBJECT_IndirectDataStartAddress_bits 32 #define GFX6_MEDIA_OBJECT_IndirectDataStartAddress_bits 32 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_IndirectDataStartAddress_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 32; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_OBJECT_IndirectDataStartAddress_start 96 #define GFX11_MEDIA_OBJECT_IndirectDataStartAddress_start 96 #define GFX9_MEDIA_OBJECT_IndirectDataStartAddress_start 96 #define GFX8_MEDIA_OBJECT_IndirectDataStartAddress_start 96 #define GFX75_MEDIA_OBJECT_IndirectDataStartAddress_start 96 #define GFX7_MEDIA_OBJECT_IndirectDataStartAddress_start 96 #define GFX6_MEDIA_OBJECT_IndirectDataStartAddress_start 96 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_IndirectDataStartAddress_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 96; case 110: return 96; case 90: return 96; case 80: return 96; case 75: return 96; case 70: return 96; case 60: return 96; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT::Interface Descriptor Offset */ #define GFX12_MEDIA_OBJECT_InterfaceDescriptorOffset_bits 6 #define GFX11_MEDIA_OBJECT_InterfaceDescriptorOffset_bits 6 #define GFX9_MEDIA_OBJECT_InterfaceDescriptorOffset_bits 6 #define GFX8_MEDIA_OBJECT_InterfaceDescriptorOffset_bits 6 #define GFX75_MEDIA_OBJECT_InterfaceDescriptorOffset_bits 6 #define GFX7_MEDIA_OBJECT_InterfaceDescriptorOffset_bits 5 #define GFX6_MEDIA_OBJECT_InterfaceDescriptorOffset_bits 5 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_InterfaceDescriptorOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 5; case 60: return 5; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_OBJECT_InterfaceDescriptorOffset_start 32 #define GFX11_MEDIA_OBJECT_InterfaceDescriptorOffset_start 32 #define GFX9_MEDIA_OBJECT_InterfaceDescriptorOffset_start 32 #define GFX8_MEDIA_OBJECT_InterfaceDescriptorOffset_start 32 #define GFX75_MEDIA_OBJECT_InterfaceDescriptorOffset_start 32 #define GFX7_MEDIA_OBJECT_InterfaceDescriptorOffset_start 32 #define GFX6_MEDIA_OBJECT_InterfaceDescriptorOffset_start 32 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_InterfaceDescriptorOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 32; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT::Media Command Opcode */ #define GFX12_MEDIA_OBJECT_MediaCommandOpcode_bits 3 #define GFX11_MEDIA_OBJECT_MediaCommandOpcode_bits 3 #define GFX9_MEDIA_OBJECT_MediaCommandOpcode_bits 3 #define GFX8_MEDIA_OBJECT_MediaCommandOpcode_bits 3 #define GFX75_MEDIA_OBJECT_MediaCommandOpcode_bits 3 #define GFX7_MEDIA_OBJECT_MediaCommandOpcode_bits 3 #define GFX6_MEDIA_OBJECT_MediaCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_MediaCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_OBJECT_MediaCommandOpcode_start 24 #define GFX11_MEDIA_OBJECT_MediaCommandOpcode_start 24 #define GFX9_MEDIA_OBJECT_MediaCommandOpcode_start 24 #define GFX8_MEDIA_OBJECT_MediaCommandOpcode_start 24 #define GFX75_MEDIA_OBJECT_MediaCommandOpcode_start 24 #define GFX7_MEDIA_OBJECT_MediaCommandOpcode_start 24 #define GFX6_MEDIA_OBJECT_MediaCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_MediaCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 24; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT::Media Command Pipeline */ #define GFX12_MEDIA_OBJECT_MediaCommandPipeline_bits 2 #define GFX11_MEDIA_OBJECT_MediaCommandPipeline_bits 2 #define GFX9_MEDIA_OBJECT_MediaCommandPipeline_bits 2 #define GFX8_MEDIA_OBJECT_MediaCommandPipeline_bits 2 #define GFX75_MEDIA_OBJECT_MediaCommandPipeline_bits 2 #define GFX7_MEDIA_OBJECT_MediaCommandPipeline_bits 2 #define GFX6_MEDIA_OBJECT_MediaCommandPipeline_bits 2 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_MediaCommandPipeline_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_OBJECT_MediaCommandPipeline_start 27 #define GFX11_MEDIA_OBJECT_MediaCommandPipeline_start 27 #define GFX9_MEDIA_OBJECT_MediaCommandPipeline_start 27 #define GFX8_MEDIA_OBJECT_MediaCommandPipeline_start 27 #define GFX75_MEDIA_OBJECT_MediaCommandPipeline_start 27 #define GFX7_MEDIA_OBJECT_MediaCommandPipeline_start 27 #define GFX6_MEDIA_OBJECT_MediaCommandPipeline_start 27 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_MediaCommandPipeline_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 27; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT::Media Command Sub-Opcode */ #define GFX12_MEDIA_OBJECT_MediaCommandSubOpcode_bits 8 #define GFX11_MEDIA_OBJECT_MediaCommandSubOpcode_bits 8 #define GFX9_MEDIA_OBJECT_MediaCommandSubOpcode_bits 8 #define GFX8_MEDIA_OBJECT_MediaCommandSubOpcode_bits 8 #define GFX75_MEDIA_OBJECT_MediaCommandSubOpcode_bits 8 #define GFX7_MEDIA_OBJECT_MediaCommandSubOpcode_bits 8 #define GFX6_MEDIA_OBJECT_MediaCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_MediaCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_OBJECT_MediaCommandSubOpcode_start 16 #define GFX11_MEDIA_OBJECT_MediaCommandSubOpcode_start 16 #define GFX9_MEDIA_OBJECT_MediaCommandSubOpcode_start 16 #define GFX8_MEDIA_OBJECT_MediaCommandSubOpcode_start 16 #define GFX75_MEDIA_OBJECT_MediaCommandSubOpcode_start 16 #define GFX7_MEDIA_OBJECT_MediaCommandSubOpcode_start 16 #define GFX6_MEDIA_OBJECT_MediaCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_MediaCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 16; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT::Scoreboard Color */ #define GFX9_MEDIA_OBJECT_ScoreboardColor_bits 4 #define GFX8_MEDIA_OBJECT_ScoreboardColor_bits 4 #define GFX75_MEDIA_OBJECT_ScoreboardColor_bits 4 #define GFX7_MEDIA_OBJECT_ScoreboardColor_bits 4 #define GFX6_MEDIA_OBJECT_ScoreboardColor_bits 4 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_ScoreboardColor_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 4; case 80: return 4; case 75: return 4; case 70: return 4; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_MEDIA_OBJECT_ScoreboardColor_start 176 #define GFX8_MEDIA_OBJECT_ScoreboardColor_start 176 #define GFX75_MEDIA_OBJECT_ScoreboardColor_start 176 #define GFX7_MEDIA_OBJECT_ScoreboardColor_start 176 #define GFX6_MEDIA_OBJECT_ScoreboardColor_start 176 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_ScoreboardColor_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 176; case 80: return 176; case 75: return 176; case 70: return 176; case 60: return 176; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT::Scoreboard Mask */ #define GFX9_MEDIA_OBJECT_ScoreboardMask_bits 8 #define GFX8_MEDIA_OBJECT_ScoreboardMask_bits 8 #define GFX75_MEDIA_OBJECT_ScoreboardMask_bits 8 #define GFX7_MEDIA_OBJECT_ScoreboardMask_bits 8 #define GFX6_MEDIA_OBJECT_ScoreboardMask_bits 8 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_ScoreboardMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_MEDIA_OBJECT_ScoreboardMask_start 160 #define GFX8_MEDIA_OBJECT_ScoreboardMask_start 160 #define GFX75_MEDIA_OBJECT_ScoreboardMask_start 160 #define GFX7_MEDIA_OBJECT_ScoreboardMask_start 160 #define GFX6_MEDIA_OBJECT_ScoreboardMask_start 160 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_ScoreboardMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 160; case 80: return 160; case 75: return 160; case 70: return 160; case 60: return 160; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT::Scoreboard X */ #define GFX9_MEDIA_OBJECT_ScoreboardX_bits 9 #define GFX8_MEDIA_OBJECT_ScoreboardX_bits 9 #define GFX75_MEDIA_OBJECT_ScoreboardX_bits 9 #define GFX7_MEDIA_OBJECT_ScoreboardX_bits 9 #define GFX6_MEDIA_OBJECT_ScoreboardX_bits 9 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_ScoreboardX_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 9; case 80: return 9; case 75: return 9; case 70: return 9; case 60: return 9; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_MEDIA_OBJECT_ScoreboardX_start 128 #define GFX8_MEDIA_OBJECT_ScoreboardX_start 128 #define GFX75_MEDIA_OBJECT_ScoreboardX_start 128 #define GFX7_MEDIA_OBJECT_ScoreboardX_start 128 #define GFX6_MEDIA_OBJECT_ScoreboardX_start 128 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_ScoreboardX_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 128; case 80: return 128; case 75: return 128; case 70: return 128; case 60: return 128; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT::Scoredboard Y */ #define GFX9_MEDIA_OBJECT_ScoredboardY_bits 9 #define GFX8_MEDIA_OBJECT_ScoredboardY_bits 9 #define GFX75_MEDIA_OBJECT_ScoredboardY_bits 9 #define GFX7_MEDIA_OBJECT_ScoredboardY_bits 9 #define GFX6_MEDIA_OBJECT_ScoredboardY_bits 9 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_ScoredboardY_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 9; case 80: return 9; case 75: return 9; case 70: return 9; case 60: return 9; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_MEDIA_OBJECT_ScoredboardY_start 144 #define GFX8_MEDIA_OBJECT_ScoredboardY_start 144 #define GFX75_MEDIA_OBJECT_ScoredboardY_start 144 #define GFX7_MEDIA_OBJECT_ScoredboardY_start 144 #define GFX6_MEDIA_OBJECT_ScoredboardY_start 144 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_ScoredboardY_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 144; case 80: return 144; case 75: return 144; case 70: return 144; case 60: return 144; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT::Slice Destination Select */ #define GFX12_MEDIA_OBJECT_SliceDestinationSelect_bits 2 #define GFX11_MEDIA_OBJECT_SliceDestinationSelect_bits 2 #define GFX9_MEDIA_OBJECT_SliceDestinationSelect_bits 2 #define GFX8_MEDIA_OBJECT_SliceDestinationSelect_bits 2 #define GFX75_MEDIA_OBJECT_SliceDestinationSelect_bits 1 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_SliceDestinationSelect_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_OBJECT_SliceDestinationSelect_start 83 #define GFX11_MEDIA_OBJECT_SliceDestinationSelect_start 83 #define GFX9_MEDIA_OBJECT_SliceDestinationSelect_start 83 #define GFX8_MEDIA_OBJECT_SliceDestinationSelect_start 83 #define GFX75_MEDIA_OBJECT_SliceDestinationSelect_start 83 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_SliceDestinationSelect_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 83; case 110: return 83; case 90: return 83; case 80: return 83; case 75: return 83; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT::Slice Destination Select MSBs */ #define GFX12_MEDIA_OBJECT_SliceDestinationSelectMSBs_bits 2 #define GFX11_MEDIA_OBJECT_SliceDestinationSelectMSBs_bits 2 #define GFX9_MEDIA_OBJECT_SliceDestinationSelectMSBs_bits 2 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_SliceDestinationSelectMSBs_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_OBJECT_SliceDestinationSelectMSBs_start 89 #define GFX11_MEDIA_OBJECT_SliceDestinationSelectMSBs_start 89 #define GFX9_MEDIA_OBJECT_SliceDestinationSelectMSBs_start 89 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_SliceDestinationSelectMSBs_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 89; case 110: return 89; case 90: return 89; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT::SubSlice Destination Select */ #define GFX12_MEDIA_OBJECT_SubSliceDestinationSelect_bits 2 #define GFX11_MEDIA_OBJECT_SubSliceDestinationSelect_bits 2 #define GFX9_MEDIA_OBJECT_SubSliceDestinationSelect_bits 2 #define GFX8_MEDIA_OBJECT_SubSliceDestinationSelect_bits 2 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_SubSliceDestinationSelect_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_OBJECT_SubSliceDestinationSelect_start 81 #define GFX11_MEDIA_OBJECT_SubSliceDestinationSelect_start 81 #define GFX9_MEDIA_OBJECT_SubSliceDestinationSelect_start 81 #define GFX8_MEDIA_OBJECT_SubSliceDestinationSelect_start 81 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_SubSliceDestinationSelect_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 81; case 110: return 81; case 90: return 81; case 80: return 81; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT::Thread Synchronization */ #define GFX12_MEDIA_OBJECT_ThreadSynchronization_bits 1 #define GFX11_MEDIA_OBJECT_ThreadSynchronization_bits 1 #define GFX9_MEDIA_OBJECT_ThreadSynchronization_bits 1 #define GFX8_MEDIA_OBJECT_ThreadSynchronization_bits 1 #define GFX75_MEDIA_OBJECT_ThreadSynchronization_bits 1 #define GFX7_MEDIA_OBJECT_ThreadSynchronization_bits 1 #define GFX6_MEDIA_OBJECT_ThreadSynchronization_bits 1 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_ThreadSynchronization_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_OBJECT_ThreadSynchronization_start 88 #define GFX11_MEDIA_OBJECT_ThreadSynchronization_start 88 #define GFX9_MEDIA_OBJECT_ThreadSynchronization_start 88 #define GFX8_MEDIA_OBJECT_ThreadSynchronization_start 88 #define GFX75_MEDIA_OBJECT_ThreadSynchronization_start 88 #define GFX7_MEDIA_OBJECT_ThreadSynchronization_start 88 #define GFX6_MEDIA_OBJECT_ThreadSynchronization_start 88 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_ThreadSynchronization_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 88; case 110: return 88; case 90: return 88; case 80: return 88; case 75: return 88; case 70: return 88; case 60: return 88; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT::Use Scoreboard */ #define GFX9_MEDIA_OBJECT_UseScoreboard_bits 1 #define GFX8_MEDIA_OBJECT_UseScoreboard_bits 1 #define GFX75_MEDIA_OBJECT_UseScoreboard_bits 1 #define GFX7_MEDIA_OBJECT_UseScoreboard_bits 1 #define GFX6_MEDIA_OBJECT_UseScoreboard_bits 1 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_UseScoreboard_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_MEDIA_OBJECT_UseScoreboard_start 85 #define GFX8_MEDIA_OBJECT_UseScoreboard_start 85 #define GFX75_MEDIA_OBJECT_UseScoreboard_start 85 #define GFX7_MEDIA_OBJECT_UseScoreboard_start 85 #define GFX6_MEDIA_OBJECT_UseScoreboard_start 85 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_UseScoreboard_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 85; case 80: return 85; case 75: return 85; case 70: return 85; case 60: return 85; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT::X Position */ #define GFX12_MEDIA_OBJECT_XPosition_bits 9 #define GFX11_MEDIA_OBJECT_XPosition_bits 9 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_XPosition_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 9; case 110: return 9; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_OBJECT_XPosition_start 128 #define GFX11_MEDIA_OBJECT_XPosition_start 128 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_XPosition_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 128; case 110: return 128; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT::Y Position */ #define GFX12_MEDIA_OBJECT_YPosition_bits 9 #define GFX11_MEDIA_OBJECT_YPosition_bits 9 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_YPosition_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 9; case 110: return 9; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_OBJECT_YPosition_start 144 #define GFX11_MEDIA_OBJECT_YPosition_start 144 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_YPosition_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 144; case 110: return 144; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT_GRPID */ /* MEDIA_OBJECT_GRPID::Block Color */ #define GFX12_MEDIA_OBJECT_GRPID_BlockColor_bits 8 #define GFX11_MEDIA_OBJECT_GRPID_BlockColor_bits 8 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_GRPID_BlockColor_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 8; case 110: return 8; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_OBJECT_GRPID_BlockColor_start 176 #define GFX11_MEDIA_OBJECT_GRPID_BlockColor_start 176 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_GRPID_BlockColor_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 176; case 110: return 176; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT_GRPID::Command Type */ #define GFX12_MEDIA_OBJECT_GRPID_CommandType_bits 3 #define GFX11_MEDIA_OBJECT_GRPID_CommandType_bits 3 #define GFX9_MEDIA_OBJECT_GRPID_CommandType_bits 3 #define GFX8_MEDIA_OBJECT_GRPID_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_GRPID_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_OBJECT_GRPID_CommandType_start 29 #define GFX11_MEDIA_OBJECT_GRPID_CommandType_start 29 #define GFX9_MEDIA_OBJECT_GRPID_CommandType_start 29 #define GFX8_MEDIA_OBJECT_GRPID_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_GRPID_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT_GRPID::DWord Length */ #define GFX12_MEDIA_OBJECT_GRPID_DWordLength_bits 16 #define GFX11_MEDIA_OBJECT_GRPID_DWordLength_bits 16 #define GFX9_MEDIA_OBJECT_GRPID_DWordLength_bits 16 #define GFX8_MEDIA_OBJECT_GRPID_DWordLength_bits 16 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_GRPID_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_OBJECT_GRPID_DWordLength_start 0 #define GFX11_MEDIA_OBJECT_GRPID_DWordLength_start 0 #define GFX9_MEDIA_OBJECT_GRPID_DWordLength_start 0 #define GFX8_MEDIA_OBJECT_GRPID_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_GRPID_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT_GRPID::End of Thread Group */ #define GFX12_MEDIA_OBJECT_GRPID_EndofThreadGroup_bits 1 #define GFX11_MEDIA_OBJECT_GRPID_EndofThreadGroup_bits 1 #define GFX9_MEDIA_OBJECT_GRPID_EndofThreadGroup_bits 1 #define GFX8_MEDIA_OBJECT_GRPID_EndofThreadGroup_bits 1 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_GRPID_EndofThreadGroup_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_OBJECT_GRPID_EndofThreadGroup_start 87 #define GFX11_MEDIA_OBJECT_GRPID_EndofThreadGroup_start 87 #define GFX9_MEDIA_OBJECT_GRPID_EndofThreadGroup_start 87 #define GFX8_MEDIA_OBJECT_GRPID_EndofThreadGroup_start 87 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_GRPID_EndofThreadGroup_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 87; case 110: return 87; case 90: return 87; case 80: return 87; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT_GRPID::Force Destination */ #define GFX9_MEDIA_OBJECT_GRPID_ForceDestination_bits 1 #define GFX8_MEDIA_OBJECT_GRPID_ForceDestination_bits 1 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_GRPID_ForceDestination_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_MEDIA_OBJECT_GRPID_ForceDestination_start 86 #define GFX8_MEDIA_OBJECT_GRPID_ForceDestination_start 86 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_GRPID_ForceDestination_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 86; case 80: return 86; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT_GRPID::GroupID */ #define GFX12_MEDIA_OBJECT_GRPID_GroupID_bits 32 #define GFX11_MEDIA_OBJECT_GRPID_GroupID_bits 32 #define GFX9_MEDIA_OBJECT_GRPID_GroupID_bits 32 #define GFX8_MEDIA_OBJECT_GRPID_GroupID_bits 32 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_GRPID_GroupID_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_OBJECT_GRPID_GroupID_start 192 #define GFX11_MEDIA_OBJECT_GRPID_GroupID_start 192 #define GFX9_MEDIA_OBJECT_GRPID_GroupID_start 192 #define GFX8_MEDIA_OBJECT_GRPID_GroupID_start 192 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_GRPID_GroupID_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 192; case 110: return 192; case 90: return 192; case 80: return 192; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT_GRPID::Indirect Data Length */ #define GFX12_MEDIA_OBJECT_GRPID_IndirectDataLength_bits 17 #define GFX11_MEDIA_OBJECT_GRPID_IndirectDataLength_bits 17 #define GFX9_MEDIA_OBJECT_GRPID_IndirectDataLength_bits 17 #define GFX8_MEDIA_OBJECT_GRPID_IndirectDataLength_bits 17 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_GRPID_IndirectDataLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 17; case 110: return 17; case 90: return 17; case 80: return 17; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_OBJECT_GRPID_IndirectDataLength_start 64 #define GFX11_MEDIA_OBJECT_GRPID_IndirectDataLength_start 64 #define GFX9_MEDIA_OBJECT_GRPID_IndirectDataLength_start 64 #define GFX8_MEDIA_OBJECT_GRPID_IndirectDataLength_start 64 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_GRPID_IndirectDataLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 64; case 110: return 64; case 90: return 64; case 80: return 64; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT_GRPID::Indirect Data Start Address */ #define GFX12_MEDIA_OBJECT_GRPID_IndirectDataStartAddress_bits 32 #define GFX11_MEDIA_OBJECT_GRPID_IndirectDataStartAddress_bits 32 #define GFX9_MEDIA_OBJECT_GRPID_IndirectDataStartAddress_bits 32 #define GFX8_MEDIA_OBJECT_GRPID_IndirectDataStartAddress_bits 32 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_GRPID_IndirectDataStartAddress_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_OBJECT_GRPID_IndirectDataStartAddress_start 96 #define GFX11_MEDIA_OBJECT_GRPID_IndirectDataStartAddress_start 96 #define GFX9_MEDIA_OBJECT_GRPID_IndirectDataStartAddress_start 96 #define GFX8_MEDIA_OBJECT_GRPID_IndirectDataStartAddress_start 96 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_GRPID_IndirectDataStartAddress_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 96; case 110: return 96; case 90: return 96; case 80: return 96; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT_GRPID::Interface Descriptor Offset */ #define GFX12_MEDIA_OBJECT_GRPID_InterfaceDescriptorOffset_bits 6 #define GFX11_MEDIA_OBJECT_GRPID_InterfaceDescriptorOffset_bits 6 #define GFX9_MEDIA_OBJECT_GRPID_InterfaceDescriptorOffset_bits 6 #define GFX8_MEDIA_OBJECT_GRPID_InterfaceDescriptorOffset_bits 6 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_GRPID_InterfaceDescriptorOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_OBJECT_GRPID_InterfaceDescriptorOffset_start 32 #define GFX11_MEDIA_OBJECT_GRPID_InterfaceDescriptorOffset_start 32 #define GFX9_MEDIA_OBJECT_GRPID_InterfaceDescriptorOffset_start 32 #define GFX8_MEDIA_OBJECT_GRPID_InterfaceDescriptorOffset_start 32 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_GRPID_InterfaceDescriptorOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT_GRPID::Media Command Opcode */ #define GFX12_MEDIA_OBJECT_GRPID_MediaCommandOpcode_bits 3 #define GFX11_MEDIA_OBJECT_GRPID_MediaCommandOpcode_bits 3 #define GFX9_MEDIA_OBJECT_GRPID_MediaCommandOpcode_bits 3 #define GFX8_MEDIA_OBJECT_GRPID_MediaCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_GRPID_MediaCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_OBJECT_GRPID_MediaCommandOpcode_start 24 #define GFX11_MEDIA_OBJECT_GRPID_MediaCommandOpcode_start 24 #define GFX9_MEDIA_OBJECT_GRPID_MediaCommandOpcode_start 24 #define GFX8_MEDIA_OBJECT_GRPID_MediaCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_GRPID_MediaCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT_GRPID::Media Command Pipeline */ #define GFX12_MEDIA_OBJECT_GRPID_MediaCommandPipeline_bits 2 #define GFX11_MEDIA_OBJECT_GRPID_MediaCommandPipeline_bits 2 #define GFX9_MEDIA_OBJECT_GRPID_MediaCommandPipeline_bits 2 #define GFX8_MEDIA_OBJECT_GRPID_MediaCommandPipeline_bits 2 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_GRPID_MediaCommandPipeline_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_OBJECT_GRPID_MediaCommandPipeline_start 27 #define GFX11_MEDIA_OBJECT_GRPID_MediaCommandPipeline_start 27 #define GFX9_MEDIA_OBJECT_GRPID_MediaCommandPipeline_start 27 #define GFX8_MEDIA_OBJECT_GRPID_MediaCommandPipeline_start 27 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_GRPID_MediaCommandPipeline_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT_GRPID::Media Command Sub-Opcode */ #define GFX12_MEDIA_OBJECT_GRPID_MediaCommandSubOpcode_bits 8 #define GFX11_MEDIA_OBJECT_GRPID_MediaCommandSubOpcode_bits 8 #define GFX9_MEDIA_OBJECT_GRPID_MediaCommandSubOpcode_bits 8 #define GFX8_MEDIA_OBJECT_GRPID_MediaCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_GRPID_MediaCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_OBJECT_GRPID_MediaCommandSubOpcode_start 16 #define GFX11_MEDIA_OBJECT_GRPID_MediaCommandSubOpcode_start 16 #define GFX9_MEDIA_OBJECT_GRPID_MediaCommandSubOpcode_start 16 #define GFX8_MEDIA_OBJECT_GRPID_MediaCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_GRPID_MediaCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT_GRPID::Scoreboard Color */ #define GFX9_MEDIA_OBJECT_GRPID_ScoreboardColor_bits 4 #define GFX8_MEDIA_OBJECT_GRPID_ScoreboardColor_bits 4 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_GRPID_ScoreboardColor_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 4; case 80: return 4; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_MEDIA_OBJECT_GRPID_ScoreboardColor_start 176 #define GFX8_MEDIA_OBJECT_GRPID_ScoreboardColor_start 176 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_GRPID_ScoreboardColor_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 176; case 80: return 176; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT_GRPID::Scoreboard Mask */ #define GFX9_MEDIA_OBJECT_GRPID_ScoreboardMask_bits 8 #define GFX8_MEDIA_OBJECT_GRPID_ScoreboardMask_bits 8 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_GRPID_ScoreboardMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 8; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_MEDIA_OBJECT_GRPID_ScoreboardMask_start 160 #define GFX8_MEDIA_OBJECT_GRPID_ScoreboardMask_start 160 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_GRPID_ScoreboardMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 160; case 80: return 160; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT_GRPID::Scoreboard X */ #define GFX9_MEDIA_OBJECT_GRPID_ScoreboardX_bits 9 #define GFX8_MEDIA_OBJECT_GRPID_ScoreboardX_bits 9 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_GRPID_ScoreboardX_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 9; case 80: return 9; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_MEDIA_OBJECT_GRPID_ScoreboardX_start 128 #define GFX8_MEDIA_OBJECT_GRPID_ScoreboardX_start 128 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_GRPID_ScoreboardX_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 128; case 80: return 128; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT_GRPID::Scoreboard Y */ #define GFX9_MEDIA_OBJECT_GRPID_ScoreboardY_bits 9 #define GFX8_MEDIA_OBJECT_GRPID_ScoreboardY_bits 9 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_GRPID_ScoreboardY_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 9; case 80: return 9; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_MEDIA_OBJECT_GRPID_ScoreboardY_start 144 #define GFX8_MEDIA_OBJECT_GRPID_ScoreboardY_start 144 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_GRPID_ScoreboardY_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 144; case 80: return 144; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT_GRPID::Slice Destination Select */ #define GFX9_MEDIA_OBJECT_GRPID_SliceDestinationSelect_bits 2 #define GFX8_MEDIA_OBJECT_GRPID_SliceDestinationSelect_bits 2 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_GRPID_SliceDestinationSelect_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 2; case 80: return 2; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_MEDIA_OBJECT_GRPID_SliceDestinationSelect_start 83 #define GFX8_MEDIA_OBJECT_GRPID_SliceDestinationSelect_start 83 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_GRPID_SliceDestinationSelect_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 83; case 80: return 83; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT_GRPID::Slice Destination Select MSB */ #define GFX9_MEDIA_OBJECT_GRPID_SliceDestinationSelectMSB_bits 1 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_GRPID_SliceDestinationSelectMSB_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_MEDIA_OBJECT_GRPID_SliceDestinationSelectMSB_start 88 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_GRPID_SliceDestinationSelectMSB_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 88; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT_GRPID::SubSlice Destination Select */ #define GFX9_MEDIA_OBJECT_GRPID_SubSliceDestinationSelect_bits 2 #define GFX8_MEDIA_OBJECT_GRPID_SubSliceDestinationSelect_bits 2 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_GRPID_SubSliceDestinationSelect_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 2; case 80: return 2; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_MEDIA_OBJECT_GRPID_SubSliceDestinationSelect_start 81 #define GFX8_MEDIA_OBJECT_GRPID_SubSliceDestinationSelect_start 81 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_GRPID_SubSliceDestinationSelect_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 81; case 80: return 81; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT_GRPID::Use Scoreboard */ #define GFX9_MEDIA_OBJECT_GRPID_UseScoreboard_bits 1 #define GFX8_MEDIA_OBJECT_GRPID_UseScoreboard_bits 1 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_GRPID_UseScoreboard_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_MEDIA_OBJECT_GRPID_UseScoreboard_start 85 #define GFX8_MEDIA_OBJECT_GRPID_UseScoreboard_start 85 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_GRPID_UseScoreboard_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 85; case 80: return 85; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT_GRPID::X Position */ #define GFX12_MEDIA_OBJECT_GRPID_XPosition_bits 9 #define GFX11_MEDIA_OBJECT_GRPID_XPosition_bits 9 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_GRPID_XPosition_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 9; case 110: return 9; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_OBJECT_GRPID_XPosition_start 128 #define GFX11_MEDIA_OBJECT_GRPID_XPosition_start 128 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_GRPID_XPosition_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 128; case 110: return 128; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT_GRPID::Y Position */ #define GFX12_MEDIA_OBJECT_GRPID_YPosition_bits 9 #define GFX11_MEDIA_OBJECT_GRPID_YPosition_bits 9 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_GRPID_YPosition_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 9; case 110: return 9; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_OBJECT_GRPID_YPosition_start 144 #define GFX11_MEDIA_OBJECT_GRPID_YPosition_start 144 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_GRPID_YPosition_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 144; case 110: return 144; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT_PRT */ #define GFX12_MEDIA_OBJECT_PRT_length 16 #define GFX11_MEDIA_OBJECT_PRT_length 16 #define GFX9_MEDIA_OBJECT_PRT_length 16 #define GFX8_MEDIA_OBJECT_PRT_length 16 #define GFX75_MEDIA_OBJECT_PRT_length 16 #define GFX7_MEDIA_OBJECT_PRT_length 16 #define GFX6_MEDIA_OBJECT_PRT_length 16 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_PRT_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 16; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT_PRT::Children Present */ #define GFX12_MEDIA_OBJECT_PRT_ChildrenPresent_bits 1 #define GFX11_MEDIA_OBJECT_PRT_ChildrenPresent_bits 1 #define GFX9_MEDIA_OBJECT_PRT_ChildrenPresent_bits 1 #define GFX8_MEDIA_OBJECT_PRT_ChildrenPresent_bits 1 #define GFX75_MEDIA_OBJECT_PRT_ChildrenPresent_bits 1 #define GFX7_MEDIA_OBJECT_PRT_ChildrenPresent_bits 1 #define GFX6_MEDIA_OBJECT_PRT_ChildrenPresent_bits 1 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_PRT_ChildrenPresent_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_OBJECT_PRT_ChildrenPresent_start 95 #define GFX11_MEDIA_OBJECT_PRT_ChildrenPresent_start 95 #define GFX9_MEDIA_OBJECT_PRT_ChildrenPresent_start 95 #define GFX8_MEDIA_OBJECT_PRT_ChildrenPresent_start 95 #define GFX75_MEDIA_OBJECT_PRT_ChildrenPresent_start 95 #define GFX7_MEDIA_OBJECT_PRT_ChildrenPresent_start 95 #define GFX6_MEDIA_OBJECT_PRT_ChildrenPresent_start 95 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_PRT_ChildrenPresent_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 95; case 110: return 95; case 90: return 95; case 80: return 95; case 75: return 95; case 70: return 95; case 60: return 95; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT_PRT::Command Type */ #define GFX12_MEDIA_OBJECT_PRT_CommandType_bits 3 #define GFX11_MEDIA_OBJECT_PRT_CommandType_bits 3 #define GFX9_MEDIA_OBJECT_PRT_CommandType_bits 3 #define GFX8_MEDIA_OBJECT_PRT_CommandType_bits 3 #define GFX75_MEDIA_OBJECT_PRT_CommandType_bits 3 #define GFX7_MEDIA_OBJECT_PRT_CommandType_bits 3 #define GFX6_MEDIA_OBJECT_PRT_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_PRT_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_OBJECT_PRT_CommandType_start 29 #define GFX11_MEDIA_OBJECT_PRT_CommandType_start 29 #define GFX9_MEDIA_OBJECT_PRT_CommandType_start 29 #define GFX8_MEDIA_OBJECT_PRT_CommandType_start 29 #define GFX75_MEDIA_OBJECT_PRT_CommandType_start 29 #define GFX7_MEDIA_OBJECT_PRT_CommandType_start 29 #define GFX6_MEDIA_OBJECT_PRT_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_PRT_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 29; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT_PRT::DWord Length */ #define GFX12_MEDIA_OBJECT_PRT_DWordLength_bits 15 #define GFX11_MEDIA_OBJECT_PRT_DWordLength_bits 15 #define GFX9_MEDIA_OBJECT_PRT_DWordLength_bits 16 #define GFX8_MEDIA_OBJECT_PRT_DWordLength_bits 16 #define GFX75_MEDIA_OBJECT_PRT_DWordLength_bits 16 #define GFX7_MEDIA_OBJECT_PRT_DWordLength_bits 16 #define GFX6_MEDIA_OBJECT_PRT_DWordLength_bits 16 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_PRT_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 15; case 110: return 15; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 16; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_OBJECT_PRT_DWordLength_start 0 #define GFX11_MEDIA_OBJECT_PRT_DWordLength_start 0 #define GFX9_MEDIA_OBJECT_PRT_DWordLength_start 0 #define GFX8_MEDIA_OBJECT_PRT_DWordLength_start 0 #define GFX75_MEDIA_OBJECT_PRT_DWordLength_start 0 #define GFX7_MEDIA_OBJECT_PRT_DWordLength_start 0 #define GFX6_MEDIA_OBJECT_PRT_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_PRT_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT_PRT::Interface Descriptor Offset */ #define GFX12_MEDIA_OBJECT_PRT_InterfaceDescriptorOffset_bits 6 #define GFX11_MEDIA_OBJECT_PRT_InterfaceDescriptorOffset_bits 6 #define GFX9_MEDIA_OBJECT_PRT_InterfaceDescriptorOffset_bits 6 #define GFX8_MEDIA_OBJECT_PRT_InterfaceDescriptorOffset_bits 6 #define GFX75_MEDIA_OBJECT_PRT_InterfaceDescriptorOffset_bits 6 #define GFX7_MEDIA_OBJECT_PRT_InterfaceDescriptorOffset_bits 5 #define GFX6_MEDIA_OBJECT_PRT_InterfaceDescriptorOffset_bits 5 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_PRT_InterfaceDescriptorOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 5; case 60: return 5; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_OBJECT_PRT_InterfaceDescriptorOffset_start 32 #define GFX11_MEDIA_OBJECT_PRT_InterfaceDescriptorOffset_start 32 #define GFX9_MEDIA_OBJECT_PRT_InterfaceDescriptorOffset_start 32 #define GFX8_MEDIA_OBJECT_PRT_InterfaceDescriptorOffset_start 32 #define GFX75_MEDIA_OBJECT_PRT_InterfaceDescriptorOffset_start 32 #define GFX7_MEDIA_OBJECT_PRT_InterfaceDescriptorOffset_start 32 #define GFX6_MEDIA_OBJECT_PRT_InterfaceDescriptorOffset_start 32 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_PRT_InterfaceDescriptorOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 32; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT_PRT::Media Command Opcode */ #define GFX12_MEDIA_OBJECT_PRT_MediaCommandOpcode_bits 3 #define GFX11_MEDIA_OBJECT_PRT_MediaCommandOpcode_bits 3 #define GFX9_MEDIA_OBJECT_PRT_MediaCommandOpcode_bits 3 #define GFX8_MEDIA_OBJECT_PRT_MediaCommandOpcode_bits 3 #define GFX75_MEDIA_OBJECT_PRT_MediaCommandOpcode_bits 3 #define GFX7_MEDIA_OBJECT_PRT_MediaCommandOpcode_bits 3 #define GFX6_MEDIA_OBJECT_PRT_MediaCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_PRT_MediaCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_OBJECT_PRT_MediaCommandOpcode_start 24 #define GFX11_MEDIA_OBJECT_PRT_MediaCommandOpcode_start 24 #define GFX9_MEDIA_OBJECT_PRT_MediaCommandOpcode_start 24 #define GFX8_MEDIA_OBJECT_PRT_MediaCommandOpcode_start 24 #define GFX75_MEDIA_OBJECT_PRT_MediaCommandOpcode_start 24 #define GFX7_MEDIA_OBJECT_PRT_MediaCommandOpcode_start 24 #define GFX6_MEDIA_OBJECT_PRT_MediaCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_PRT_MediaCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 24; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT_PRT::PRT_Fence Needed */ #define GFX12_MEDIA_OBJECT_PRT_PRT_FenceNeeded_bits 1 #define GFX11_MEDIA_OBJECT_PRT_PRT_FenceNeeded_bits 1 #define GFX9_MEDIA_OBJECT_PRT_PRT_FenceNeeded_bits 1 #define GFX8_MEDIA_OBJECT_PRT_PRT_FenceNeeded_bits 1 #define GFX75_MEDIA_OBJECT_PRT_PRT_FenceNeeded_bits 1 #define GFX7_MEDIA_OBJECT_PRT_PRT_FenceNeeded_bits 1 #define GFX6_MEDIA_OBJECT_PRT_PRT_FenceNeeded_bits 1 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_PRT_PRT_FenceNeeded_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_OBJECT_PRT_PRT_FenceNeeded_start 87 #define GFX11_MEDIA_OBJECT_PRT_PRT_FenceNeeded_start 87 #define GFX9_MEDIA_OBJECT_PRT_PRT_FenceNeeded_start 87 #define GFX8_MEDIA_OBJECT_PRT_PRT_FenceNeeded_start 87 #define GFX75_MEDIA_OBJECT_PRT_PRT_FenceNeeded_start 87 #define GFX7_MEDIA_OBJECT_PRT_PRT_FenceNeeded_start 87 #define GFX6_MEDIA_OBJECT_PRT_PRT_FenceNeeded_start 87 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_PRT_PRT_FenceNeeded_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 87; case 110: return 87; case 90: return 87; case 80: return 87; case 75: return 87; case 70: return 87; case 60: return 87; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT_PRT::PRT_FenceType */ #define GFX12_MEDIA_OBJECT_PRT_PRT_FenceType_bits 1 #define GFX11_MEDIA_OBJECT_PRT_PRT_FenceType_bits 1 #define GFX9_MEDIA_OBJECT_PRT_PRT_FenceType_bits 1 #define GFX8_MEDIA_OBJECT_PRT_PRT_FenceType_bits 1 #define GFX75_MEDIA_OBJECT_PRT_PRT_FenceType_bits 1 #define GFX7_MEDIA_OBJECT_PRT_PRT_FenceType_bits 1 #define GFX6_MEDIA_OBJECT_PRT_PRT_FenceType_bits 1 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_PRT_PRT_FenceType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_OBJECT_PRT_PRT_FenceType_start 86 #define GFX11_MEDIA_OBJECT_PRT_PRT_FenceType_start 86 #define GFX9_MEDIA_OBJECT_PRT_PRT_FenceType_start 86 #define GFX8_MEDIA_OBJECT_PRT_PRT_FenceType_start 86 #define GFX75_MEDIA_OBJECT_PRT_PRT_FenceType_start 86 #define GFX7_MEDIA_OBJECT_PRT_PRT_FenceType_start 86 #define GFX6_MEDIA_OBJECT_PRT_PRT_FenceType_start 86 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_PRT_PRT_FenceType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 86; case 110: return 86; case 90: return 86; case 80: return 86; case 75: return 86; case 70: return 86; case 60: return 86; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT_PRT::Pipeline */ #define GFX12_MEDIA_OBJECT_PRT_Pipeline_bits 2 #define GFX11_MEDIA_OBJECT_PRT_Pipeline_bits 2 #define GFX9_MEDIA_OBJECT_PRT_Pipeline_bits 2 #define GFX8_MEDIA_OBJECT_PRT_Pipeline_bits 2 #define GFX75_MEDIA_OBJECT_PRT_Pipeline_bits 2 #define GFX7_MEDIA_OBJECT_PRT_Pipeline_bits 2 #define GFX6_MEDIA_OBJECT_PRT_Pipeline_bits 2 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_PRT_Pipeline_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_OBJECT_PRT_Pipeline_start 27 #define GFX11_MEDIA_OBJECT_PRT_Pipeline_start 27 #define GFX9_MEDIA_OBJECT_PRT_Pipeline_start 27 #define GFX8_MEDIA_OBJECT_PRT_Pipeline_start 27 #define GFX75_MEDIA_OBJECT_PRT_Pipeline_start 27 #define GFX7_MEDIA_OBJECT_PRT_Pipeline_start 27 #define GFX6_MEDIA_OBJECT_PRT_Pipeline_start 27 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_PRT_Pipeline_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 27; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT_PRT::SubOpcode */ #define GFX12_MEDIA_OBJECT_PRT_SubOpcode_bits 8 #define GFX11_MEDIA_OBJECT_PRT_SubOpcode_bits 8 #define GFX9_MEDIA_OBJECT_PRT_SubOpcode_bits 8 #define GFX8_MEDIA_OBJECT_PRT_SubOpcode_bits 8 #define GFX75_MEDIA_OBJECT_PRT_SubOpcode_bits 8 #define GFX7_MEDIA_OBJECT_PRT_SubOpcode_bits 8 #define GFX6_MEDIA_OBJECT_PRT_SubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_PRT_SubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_OBJECT_PRT_SubOpcode_start 16 #define GFX11_MEDIA_OBJECT_PRT_SubOpcode_start 16 #define GFX9_MEDIA_OBJECT_PRT_SubOpcode_start 16 #define GFX8_MEDIA_OBJECT_PRT_SubOpcode_start 16 #define GFX75_MEDIA_OBJECT_PRT_SubOpcode_start 16 #define GFX7_MEDIA_OBJECT_PRT_SubOpcode_start 16 #define GFX6_MEDIA_OBJECT_PRT_SubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_PRT_SubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 16; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT_WALKER */ /* MEDIA_OBJECT_WALKER::Block Resolution X */ #define GFX12_MEDIA_OBJECT_WALKER_BlockResolutionX_bits 11 #define GFX11_MEDIA_OBJECT_WALKER_BlockResolutionX_bits 11 #define GFX9_MEDIA_OBJECT_WALKER_BlockResolutionX_bits 11 #define GFX8_MEDIA_OBJECT_WALKER_BlockResolutionX_bits 9 #define GFX75_MEDIA_OBJECT_WALKER_BlockResolutionX_bits 9 #define GFX7_MEDIA_OBJECT_WALKER_BlockResolutionX_bits 9 #define GFX6_MEDIA_OBJECT_WALKER_BlockResolutionX_bits 9 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_BlockResolutionX_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 11; case 110: return 11; case 90: return 11; case 80: return 9; case 75: return 9; case 70: return 9; case 60: return 9; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_OBJECT_WALKER_BlockResolutionX_start 256 #define GFX11_MEDIA_OBJECT_WALKER_BlockResolutionX_start 256 #define GFX9_MEDIA_OBJECT_WALKER_BlockResolutionX_start 256 #define GFX8_MEDIA_OBJECT_WALKER_BlockResolutionX_start 256 #define GFX75_MEDIA_OBJECT_WALKER_BlockResolutionX_start 256 #define GFX7_MEDIA_OBJECT_WALKER_BlockResolutionX_start 256 #define GFX6_MEDIA_OBJECT_WALKER_BlockResolutionX_start 256 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_BlockResolutionX_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 256; case 110: return 256; case 90: return 256; case 80: return 256; case 75: return 256; case 70: return 256; case 60: return 256; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT_WALKER::Block Resolution Y */ #define GFX12_MEDIA_OBJECT_WALKER_BlockResolutionY_bits 11 #define GFX11_MEDIA_OBJECT_WALKER_BlockResolutionY_bits 11 #define GFX9_MEDIA_OBJECT_WALKER_BlockResolutionY_bits 11 #define GFX8_MEDIA_OBJECT_WALKER_BlockResolutionY_bits 9 #define GFX75_MEDIA_OBJECT_WALKER_BlockResolutionY_bits 9 #define GFX7_MEDIA_OBJECT_WALKER_BlockResolutionY_bits 9 #define GFX6_MEDIA_OBJECT_WALKER_BlockResolutionY_bits 9 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_BlockResolutionY_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 11; case 110: return 11; case 90: return 11; case 80: return 9; case 75: return 9; case 70: return 9; case 60: return 9; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_OBJECT_WALKER_BlockResolutionY_start 272 #define GFX11_MEDIA_OBJECT_WALKER_BlockResolutionY_start 272 #define GFX9_MEDIA_OBJECT_WALKER_BlockResolutionY_start 272 #define GFX8_MEDIA_OBJECT_WALKER_BlockResolutionY_start 272 #define GFX75_MEDIA_OBJECT_WALKER_BlockResolutionY_start 272 #define GFX7_MEDIA_OBJECT_WALKER_BlockResolutionY_start 272 #define GFX6_MEDIA_OBJECT_WALKER_BlockResolutionY_start 272 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_BlockResolutionY_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 272; case 110: return 272; case 90: return 272; case 80: return 272; case 75: return 272; case 70: return 272; case 60: return 272; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT_WALKER::Children Present */ #define GFX8_MEDIA_OBJECT_WALKER_ChildrenPresent_bits 1 #define GFX75_MEDIA_OBJECT_WALKER_ChildrenPresent_bits 1 #define GFX7_MEDIA_OBJECT_WALKER_ChildrenPresent_bits 1 #define GFX6_MEDIA_OBJECT_WALKER_ChildrenPresent_bits 1 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_ChildrenPresent_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX8_MEDIA_OBJECT_WALKER_ChildrenPresent_start 95 #define GFX75_MEDIA_OBJECT_WALKER_ChildrenPresent_start 95 #define GFX7_MEDIA_OBJECT_WALKER_ChildrenPresent_start 95 #define GFX6_MEDIA_OBJECT_WALKER_ChildrenPresent_start 95 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_ChildrenPresent_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 95; case 75: return 95; case 70: return 95; case 60: return 95; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT_WALKER::Color Count Minus One */ #define GFX12_MEDIA_OBJECT_WALKER_ColorCountMinusOne_bits 8 #define GFX11_MEDIA_OBJECT_WALKER_ColorCountMinusOne_bits 8 #define GFX9_MEDIA_OBJECT_WALKER_ColorCountMinusOne_bits 4 #define GFX8_MEDIA_OBJECT_WALKER_ColorCountMinusOne_bits 4 #define GFX75_MEDIA_OBJECT_WALKER_ColorCountMinusOne_bits 4 #define GFX7_MEDIA_OBJECT_WALKER_ColorCountMinusOne_bits 4 #define GFX6_MEDIA_OBJECT_WALKER_ColorCountMinusOne_bits 4 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_ColorCountMinusOne_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 8; case 110: return 8; case 90: return 4; case 80: return 4; case 75: return 4; case 70: return 4; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_OBJECT_WALKER_ColorCountMinusOne_start 216 #define GFX11_MEDIA_OBJECT_WALKER_ColorCountMinusOne_start 216 #define GFX9_MEDIA_OBJECT_WALKER_ColorCountMinusOne_start 216 #define GFX8_MEDIA_OBJECT_WALKER_ColorCountMinusOne_start 216 #define GFX75_MEDIA_OBJECT_WALKER_ColorCountMinusOne_start 216 #define GFX7_MEDIA_OBJECT_WALKER_ColorCountMinusOne_start 216 #define GFX6_MEDIA_OBJECT_WALKER_ColorCountMinusOne_start 216 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_ColorCountMinusOne_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 216; case 110: return 216; case 90: return 216; case 80: return 216; case 75: return 216; case 70: return 216; case 60: return 216; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT_WALKER::Command Type */ #define GFX12_MEDIA_OBJECT_WALKER_CommandType_bits 3 #define GFX11_MEDIA_OBJECT_WALKER_CommandType_bits 3 #define GFX9_MEDIA_OBJECT_WALKER_CommandType_bits 3 #define GFX8_MEDIA_OBJECT_WALKER_CommandType_bits 3 #define GFX75_MEDIA_OBJECT_WALKER_CommandType_bits 3 #define GFX7_MEDIA_OBJECT_WALKER_CommandType_bits 3 #define GFX6_MEDIA_OBJECT_WALKER_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_OBJECT_WALKER_CommandType_start 29 #define GFX11_MEDIA_OBJECT_WALKER_CommandType_start 29 #define GFX9_MEDIA_OBJECT_WALKER_CommandType_start 29 #define GFX8_MEDIA_OBJECT_WALKER_CommandType_start 29 #define GFX75_MEDIA_OBJECT_WALKER_CommandType_start 29 #define GFX7_MEDIA_OBJECT_WALKER_CommandType_start 29 #define GFX6_MEDIA_OBJECT_WALKER_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 29; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT_WALKER::DWord Length */ #define GFX12_MEDIA_OBJECT_WALKER_DWordLength_bits 15 #define GFX11_MEDIA_OBJECT_WALKER_DWordLength_bits 15 #define GFX9_MEDIA_OBJECT_WALKER_DWordLength_bits 16 #define GFX8_MEDIA_OBJECT_WALKER_DWordLength_bits 16 #define GFX75_MEDIA_OBJECT_WALKER_DWordLength_bits 16 #define GFX7_MEDIA_OBJECT_WALKER_DWordLength_bits 16 #define GFX6_MEDIA_OBJECT_WALKER_DWordLength_bits 16 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 15; case 110: return 15; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 16; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_OBJECT_WALKER_DWordLength_start 0 #define GFX11_MEDIA_OBJECT_WALKER_DWordLength_start 0 #define GFX9_MEDIA_OBJECT_WALKER_DWordLength_start 0 #define GFX8_MEDIA_OBJECT_WALKER_DWordLength_start 0 #define GFX75_MEDIA_OBJECT_WALKER_DWordLength_start 0 #define GFX7_MEDIA_OBJECT_WALKER_DWordLength_start 0 #define GFX6_MEDIA_OBJECT_WALKER_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT_WALKER::Dual Mode */ #define GFX75_MEDIA_OBJECT_WALKER_DualMode_bits 1 #define GFX7_MEDIA_OBJECT_WALKER_DualMode_bits 1 #define GFX6_MEDIA_OBJECT_WALKER_DualMode_bits 1 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_DualMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_MEDIA_OBJECT_WALKER_DualMode_start 223 #define GFX7_MEDIA_OBJECT_WALKER_DualMode_start 223 #define GFX6_MEDIA_OBJECT_WALKER_DualMode_start 223 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_DualMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 223; case 70: return 223; case 60: return 223; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT_WALKER::Global Inner Loop Unit X */ #define GFX12_MEDIA_OBJECT_WALKER_GlobalInnerLoopUnitX_bits 12 #define GFX11_MEDIA_OBJECT_WALKER_GlobalInnerLoopUnitX_bits 12 #define GFX9_MEDIA_OBJECT_WALKER_GlobalInnerLoopUnitX_bits 12 #define GFX8_MEDIA_OBJECT_WALKER_GlobalInnerLoopUnitX_bits 10 #define GFX75_MEDIA_OBJECT_WALKER_GlobalInnerLoopUnitX_bits 10 #define GFX7_MEDIA_OBJECT_WALKER_GlobalInnerLoopUnitX_bits 10 #define GFX6_MEDIA_OBJECT_WALKER_GlobalInnerLoopUnitX_bits 10 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_GlobalInnerLoopUnitX_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 12; case 110: return 12; case 90: return 12; case 80: return 10; case 75: return 10; case 70: return 10; case 60: return 10; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_OBJECT_WALKER_GlobalInnerLoopUnitX_start 512 #define GFX11_MEDIA_OBJECT_WALKER_GlobalInnerLoopUnitX_start 512 #define GFX9_MEDIA_OBJECT_WALKER_GlobalInnerLoopUnitX_start 512 #define GFX8_MEDIA_OBJECT_WALKER_GlobalInnerLoopUnitX_start 512 #define GFX75_MEDIA_OBJECT_WALKER_GlobalInnerLoopUnitX_start 512 #define GFX7_MEDIA_OBJECT_WALKER_GlobalInnerLoopUnitX_start 512 #define GFX6_MEDIA_OBJECT_WALKER_GlobalInnerLoopUnitX_start 512 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_GlobalInnerLoopUnitX_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 512; case 110: return 512; case 90: return 512; case 80: return 512; case 75: return 512; case 70: return 512; case 60: return 512; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT_WALKER::Global Inner Loop Unit Y */ #define GFX12_MEDIA_OBJECT_WALKER_GlobalInnerLoopUnitY_bits 12 #define GFX11_MEDIA_OBJECT_WALKER_GlobalInnerLoopUnitY_bits 12 #define GFX9_MEDIA_OBJECT_WALKER_GlobalInnerLoopUnitY_bits 12 #define GFX8_MEDIA_OBJECT_WALKER_GlobalInnerLoopUnitY_bits 10 #define GFX75_MEDIA_OBJECT_WALKER_GlobalInnerLoopUnitY_bits 10 #define GFX7_MEDIA_OBJECT_WALKER_GlobalInnerLoopUnitY_bits 10 #define GFX6_MEDIA_OBJECT_WALKER_GlobalInnerLoopUnitY_bits 10 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_GlobalInnerLoopUnitY_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 12; case 110: return 12; case 90: return 12; case 80: return 10; case 75: return 10; case 70: return 10; case 60: return 10; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_OBJECT_WALKER_GlobalInnerLoopUnitY_start 528 #define GFX11_MEDIA_OBJECT_WALKER_GlobalInnerLoopUnitY_start 528 #define GFX9_MEDIA_OBJECT_WALKER_GlobalInnerLoopUnitY_start 528 #define GFX8_MEDIA_OBJECT_WALKER_GlobalInnerLoopUnitY_start 528 #define GFX75_MEDIA_OBJECT_WALKER_GlobalInnerLoopUnitY_start 528 #define GFX7_MEDIA_OBJECT_WALKER_GlobalInnerLoopUnitY_start 528 #define GFX6_MEDIA_OBJECT_WALKER_GlobalInnerLoopUnitY_start 528 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_GlobalInnerLoopUnitY_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 528; case 110: return 528; case 90: return 528; case 80: return 528; case 75: return 528; case 70: return 528; case 60: return 528; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT_WALKER::Global Loop Exec Count */ #define GFX12_MEDIA_OBJECT_WALKER_GlobalLoopExecCount_bits 12 #define GFX11_MEDIA_OBJECT_WALKER_GlobalLoopExecCount_bits 12 #define GFX9_MEDIA_OBJECT_WALKER_GlobalLoopExecCount_bits 12 #define GFX8_MEDIA_OBJECT_WALKER_GlobalLoopExecCount_bits 10 #define GFX75_MEDIA_OBJECT_WALKER_GlobalLoopExecCount_bits 10 #define GFX7_MEDIA_OBJECT_WALKER_GlobalLoopExecCount_bits 10 #define GFX6_MEDIA_OBJECT_WALKER_GlobalLoopExecCount_bits 10 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_GlobalLoopExecCount_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 12; case 110: return 12; case 90: return 12; case 80: return 10; case 75: return 10; case 70: return 10; case 60: return 10; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_OBJECT_WALKER_GlobalLoopExecCount_start 240 #define GFX11_MEDIA_OBJECT_WALKER_GlobalLoopExecCount_start 240 #define GFX9_MEDIA_OBJECT_WALKER_GlobalLoopExecCount_start 240 #define GFX8_MEDIA_OBJECT_WALKER_GlobalLoopExecCount_start 240 #define GFX75_MEDIA_OBJECT_WALKER_GlobalLoopExecCount_start 240 #define GFX7_MEDIA_OBJECT_WALKER_GlobalLoopExecCount_start 240 #define GFX6_MEDIA_OBJECT_WALKER_GlobalLoopExecCount_start 240 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_GlobalLoopExecCount_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 240; case 110: return 240; case 90: return 240; case 80: return 240; case 75: return 240; case 70: return 240; case 60: return 240; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT_WALKER::Global Outer Loop Stride X */ #define GFX12_MEDIA_OBJECT_WALKER_GlobalOuterLoopStrideX_bits 12 #define GFX11_MEDIA_OBJECT_WALKER_GlobalOuterLoopStrideX_bits 12 #define GFX9_MEDIA_OBJECT_WALKER_GlobalOuterLoopStrideX_bits 12 #define GFX8_MEDIA_OBJECT_WALKER_GlobalOuterLoopStrideX_bits 10 #define GFX75_MEDIA_OBJECT_WALKER_GlobalOuterLoopStrideX_bits 10 #define GFX7_MEDIA_OBJECT_WALKER_GlobalOuterLoopStrideX_bits 10 #define GFX6_MEDIA_OBJECT_WALKER_GlobalOuterLoopStrideX_bits 10 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_GlobalOuterLoopStrideX_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 12; case 110: return 12; case 90: return 12; case 80: return 10; case 75: return 10; case 70: return 10; case 60: return 10; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_OBJECT_WALKER_GlobalOuterLoopStrideX_start 480 #define GFX11_MEDIA_OBJECT_WALKER_GlobalOuterLoopStrideX_start 480 #define GFX9_MEDIA_OBJECT_WALKER_GlobalOuterLoopStrideX_start 480 #define GFX8_MEDIA_OBJECT_WALKER_GlobalOuterLoopStrideX_start 480 #define GFX75_MEDIA_OBJECT_WALKER_GlobalOuterLoopStrideX_start 480 #define GFX7_MEDIA_OBJECT_WALKER_GlobalOuterLoopStrideX_start 480 #define GFX6_MEDIA_OBJECT_WALKER_GlobalOuterLoopStrideX_start 480 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_GlobalOuterLoopStrideX_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 480; case 110: return 480; case 90: return 480; case 80: return 480; case 75: return 480; case 70: return 480; case 60: return 480; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT_WALKER::Global Outer Loop Stride Y */ #define GFX12_MEDIA_OBJECT_WALKER_GlobalOuterLoopStrideY_bits 12 #define GFX11_MEDIA_OBJECT_WALKER_GlobalOuterLoopStrideY_bits 12 #define GFX9_MEDIA_OBJECT_WALKER_GlobalOuterLoopStrideY_bits 12 #define GFX8_MEDIA_OBJECT_WALKER_GlobalOuterLoopStrideY_bits 10 #define GFX75_MEDIA_OBJECT_WALKER_GlobalOuterLoopStrideY_bits 10 #define GFX7_MEDIA_OBJECT_WALKER_GlobalOuterLoopStrideY_bits 10 #define GFX6_MEDIA_OBJECT_WALKER_GlobalOuterLoopStrideY_bits 10 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_GlobalOuterLoopStrideY_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 12; case 110: return 12; case 90: return 12; case 80: return 10; case 75: return 10; case 70: return 10; case 60: return 10; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_OBJECT_WALKER_GlobalOuterLoopStrideY_start 496 #define GFX11_MEDIA_OBJECT_WALKER_GlobalOuterLoopStrideY_start 496 #define GFX9_MEDIA_OBJECT_WALKER_GlobalOuterLoopStrideY_start 496 #define GFX8_MEDIA_OBJECT_WALKER_GlobalOuterLoopStrideY_start 496 #define GFX75_MEDIA_OBJECT_WALKER_GlobalOuterLoopStrideY_start 496 #define GFX7_MEDIA_OBJECT_WALKER_GlobalOuterLoopStrideY_start 496 #define GFX6_MEDIA_OBJECT_WALKER_GlobalOuterLoopStrideY_start 496 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_GlobalOuterLoopStrideY_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 496; case 110: return 496; case 90: return 496; case 80: return 496; case 75: return 496; case 70: return 496; case 60: return 496; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT_WALKER::Global Resolution X */ #define GFX12_MEDIA_OBJECT_WALKER_GlobalResolutionX_bits 11 #define GFX11_MEDIA_OBJECT_WALKER_GlobalResolutionX_bits 11 #define GFX9_MEDIA_OBJECT_WALKER_GlobalResolutionX_bits 11 #define GFX8_MEDIA_OBJECT_WALKER_GlobalResolutionX_bits 9 #define GFX75_MEDIA_OBJECT_WALKER_GlobalResolutionX_bits 9 #define GFX7_MEDIA_OBJECT_WALKER_GlobalResolutionX_bits 9 #define GFX6_MEDIA_OBJECT_WALKER_GlobalResolutionX_bits 9 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_GlobalResolutionX_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 11; case 110: return 11; case 90: return 11; case 80: return 9; case 75: return 9; case 70: return 9; case 60: return 9; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_OBJECT_WALKER_GlobalResolutionX_start 416 #define GFX11_MEDIA_OBJECT_WALKER_GlobalResolutionX_start 416 #define GFX9_MEDIA_OBJECT_WALKER_GlobalResolutionX_start 416 #define GFX8_MEDIA_OBJECT_WALKER_GlobalResolutionX_start 416 #define GFX75_MEDIA_OBJECT_WALKER_GlobalResolutionX_start 416 #define GFX7_MEDIA_OBJECT_WALKER_GlobalResolutionX_start 416 #define GFX6_MEDIA_OBJECT_WALKER_GlobalResolutionX_start 416 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_GlobalResolutionX_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 416; case 110: return 416; case 90: return 416; case 80: return 416; case 75: return 416; case 70: return 416; case 60: return 416; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT_WALKER::Global Resolution Y */ #define GFX12_MEDIA_OBJECT_WALKER_GlobalResolutionY_bits 11 #define GFX11_MEDIA_OBJECT_WALKER_GlobalResolutionY_bits 11 #define GFX9_MEDIA_OBJECT_WALKER_GlobalResolutionY_bits 11 #define GFX8_MEDIA_OBJECT_WALKER_GlobalResolutionY_bits 9 #define GFX75_MEDIA_OBJECT_WALKER_GlobalResolutionY_bits 9 #define GFX7_MEDIA_OBJECT_WALKER_GlobalResolutionY_bits 9 #define GFX6_MEDIA_OBJECT_WALKER_GlobalResolutionY_bits 9 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_GlobalResolutionY_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 11; case 110: return 11; case 90: return 11; case 80: return 9; case 75: return 9; case 70: return 9; case 60: return 9; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_OBJECT_WALKER_GlobalResolutionY_start 432 #define GFX11_MEDIA_OBJECT_WALKER_GlobalResolutionY_start 432 #define GFX9_MEDIA_OBJECT_WALKER_GlobalResolutionY_start 432 #define GFX8_MEDIA_OBJECT_WALKER_GlobalResolutionY_start 432 #define GFX75_MEDIA_OBJECT_WALKER_GlobalResolutionY_start 432 #define GFX7_MEDIA_OBJECT_WALKER_GlobalResolutionY_start 432 #define GFX6_MEDIA_OBJECT_WALKER_GlobalResolutionY_start 432 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_GlobalResolutionY_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 432; case 110: return 432; case 90: return 432; case 80: return 432; case 75: return 432; case 70: return 432; case 60: return 432; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT_WALKER::Global Start X */ #define GFX12_MEDIA_OBJECT_WALKER_GlobalStartX_bits 12 #define GFX11_MEDIA_OBJECT_WALKER_GlobalStartX_bits 12 #define GFX9_MEDIA_OBJECT_WALKER_GlobalStartX_bits 12 #define GFX8_MEDIA_OBJECT_WALKER_GlobalStartX_bits 10 #define GFX75_MEDIA_OBJECT_WALKER_GlobalStartX_bits 10 #define GFX7_MEDIA_OBJECT_WALKER_GlobalStartX_bits 10 #define GFX6_MEDIA_OBJECT_WALKER_GlobalStartX_bits 10 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_GlobalStartX_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 12; case 110: return 12; case 90: return 12; case 80: return 10; case 75: return 10; case 70: return 10; case 60: return 10; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_OBJECT_WALKER_GlobalStartX_start 448 #define GFX11_MEDIA_OBJECT_WALKER_GlobalStartX_start 448 #define GFX9_MEDIA_OBJECT_WALKER_GlobalStartX_start 448 #define GFX8_MEDIA_OBJECT_WALKER_GlobalStartX_start 448 #define GFX75_MEDIA_OBJECT_WALKER_GlobalStartX_start 448 #define GFX7_MEDIA_OBJECT_WALKER_GlobalStartX_start 448 #define GFX6_MEDIA_OBJECT_WALKER_GlobalStartX_start 448 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_GlobalStartX_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 448; case 110: return 448; case 90: return 448; case 80: return 448; case 75: return 448; case 70: return 448; case 60: return 448; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT_WALKER::Global Start Y */ #define GFX12_MEDIA_OBJECT_WALKER_GlobalStartY_bits 12 #define GFX11_MEDIA_OBJECT_WALKER_GlobalStartY_bits 12 #define GFX9_MEDIA_OBJECT_WALKER_GlobalStartY_bits 12 #define GFX8_MEDIA_OBJECT_WALKER_GlobalStartY_bits 10 #define GFX75_MEDIA_OBJECT_WALKER_GlobalStartY_bits 10 #define GFX7_MEDIA_OBJECT_WALKER_GlobalStartY_bits 10 #define GFX6_MEDIA_OBJECT_WALKER_GlobalStartY_bits 10 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_GlobalStartY_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 12; case 110: return 12; case 90: return 12; case 80: return 10; case 75: return 10; case 70: return 10; case 60: return 10; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_OBJECT_WALKER_GlobalStartY_start 464 #define GFX11_MEDIA_OBJECT_WALKER_GlobalStartY_start 464 #define GFX9_MEDIA_OBJECT_WALKER_GlobalStartY_start 464 #define GFX8_MEDIA_OBJECT_WALKER_GlobalStartY_start 464 #define GFX75_MEDIA_OBJECT_WALKER_GlobalStartY_start 464 #define GFX7_MEDIA_OBJECT_WALKER_GlobalStartY_start 464 #define GFX6_MEDIA_OBJECT_WALKER_GlobalStartY_start 464 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_GlobalStartY_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 464; case 110: return 464; case 90: return 464; case 80: return 464; case 75: return 464; case 70: return 464; case 60: return 464; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT_WALKER::Group ID Loop Select */ #define GFX12_MEDIA_OBJECT_WALKER_GroupIDLoopSelect_bits 24 #define GFX11_MEDIA_OBJECT_WALKER_GroupIDLoopSelect_bits 24 #define GFX9_MEDIA_OBJECT_WALKER_GroupIDLoopSelect_bits 24 #define GFX8_MEDIA_OBJECT_WALKER_GroupIDLoopSelect_bits 24 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_GroupIDLoopSelect_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_OBJECT_WALKER_GroupIDLoopSelect_start 168 #define GFX11_MEDIA_OBJECT_WALKER_GroupIDLoopSelect_start 168 #define GFX9_MEDIA_OBJECT_WALKER_GroupIDLoopSelect_start 168 #define GFX8_MEDIA_OBJECT_WALKER_GroupIDLoopSelect_start 168 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_GroupIDLoopSelect_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 168; case 110: return 168; case 90: return 168; case 80: return 168; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT_WALKER::Indirect Data Length */ #define GFX12_MEDIA_OBJECT_WALKER_IndirectDataLength_bits 17 #define GFX11_MEDIA_OBJECT_WALKER_IndirectDataLength_bits 17 #define GFX9_MEDIA_OBJECT_WALKER_IndirectDataLength_bits 17 #define GFX8_MEDIA_OBJECT_WALKER_IndirectDataLength_bits 17 #define GFX75_MEDIA_OBJECT_WALKER_IndirectDataLength_bits 17 #define GFX7_MEDIA_OBJECT_WALKER_IndirectDataLength_bits 17 #define GFX6_MEDIA_OBJECT_WALKER_IndirectDataLength_bits 17 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_IndirectDataLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 17; case 110: return 17; case 90: return 17; case 80: return 17; case 75: return 17; case 70: return 17; case 60: return 17; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_OBJECT_WALKER_IndirectDataLength_start 64 #define GFX11_MEDIA_OBJECT_WALKER_IndirectDataLength_start 64 #define GFX9_MEDIA_OBJECT_WALKER_IndirectDataLength_start 64 #define GFX8_MEDIA_OBJECT_WALKER_IndirectDataLength_start 64 #define GFX75_MEDIA_OBJECT_WALKER_IndirectDataLength_start 64 #define GFX7_MEDIA_OBJECT_WALKER_IndirectDataLength_start 64 #define GFX6_MEDIA_OBJECT_WALKER_IndirectDataLength_start 64 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_IndirectDataLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 64; case 110: return 64; case 90: return 64; case 80: return 64; case 75: return 64; case 70: return 64; case 60: return 64; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT_WALKER::Indirect Data Start Address */ #define GFX12_MEDIA_OBJECT_WALKER_IndirectDataStartAddress_bits 32 #define GFX11_MEDIA_OBJECT_WALKER_IndirectDataStartAddress_bits 32 #define GFX9_MEDIA_OBJECT_WALKER_IndirectDataStartAddress_bits 32 #define GFX8_MEDIA_OBJECT_WALKER_IndirectDataStartAddress_bits 32 #define GFX75_MEDIA_OBJECT_WALKER_IndirectDataStartAddress_bits 32 #define GFX7_MEDIA_OBJECT_WALKER_IndirectDataStartAddress_bits 32 #define GFX6_MEDIA_OBJECT_WALKER_IndirectDataStartAddress_bits 32 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_IndirectDataStartAddress_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 32; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_OBJECT_WALKER_IndirectDataStartAddress_start 96 #define GFX11_MEDIA_OBJECT_WALKER_IndirectDataStartAddress_start 96 #define GFX9_MEDIA_OBJECT_WALKER_IndirectDataStartAddress_start 96 #define GFX8_MEDIA_OBJECT_WALKER_IndirectDataStartAddress_start 96 #define GFX75_MEDIA_OBJECT_WALKER_IndirectDataStartAddress_start 96 #define GFX7_MEDIA_OBJECT_WALKER_IndirectDataStartAddress_start 96 #define GFX6_MEDIA_OBJECT_WALKER_IndirectDataStartAddress_start 96 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_IndirectDataStartAddress_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 96; case 110: return 96; case 90: return 96; case 80: return 96; case 75: return 96; case 70: return 96; case 60: return 96; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT_WALKER::Interface Descriptor Offset */ #define GFX12_MEDIA_OBJECT_WALKER_InterfaceDescriptorOffset_bits 6 #define GFX11_MEDIA_OBJECT_WALKER_InterfaceDescriptorOffset_bits 6 #define GFX9_MEDIA_OBJECT_WALKER_InterfaceDescriptorOffset_bits 6 #define GFX8_MEDIA_OBJECT_WALKER_InterfaceDescriptorOffset_bits 6 #define GFX75_MEDIA_OBJECT_WALKER_InterfaceDescriptorOffset_bits 6 #define GFX7_MEDIA_OBJECT_WALKER_InterfaceDescriptorOffset_bits 5 #define GFX6_MEDIA_OBJECT_WALKER_InterfaceDescriptorOffset_bits 5 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_InterfaceDescriptorOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 5; case 60: return 5; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_OBJECT_WALKER_InterfaceDescriptorOffset_start 32 #define GFX11_MEDIA_OBJECT_WALKER_InterfaceDescriptorOffset_start 32 #define GFX9_MEDIA_OBJECT_WALKER_InterfaceDescriptorOffset_start 32 #define GFX8_MEDIA_OBJECT_WALKER_InterfaceDescriptorOffset_start 32 #define GFX75_MEDIA_OBJECT_WALKER_InterfaceDescriptorOffset_start 32 #define GFX7_MEDIA_OBJECT_WALKER_InterfaceDescriptorOffset_start 32 #define GFX6_MEDIA_OBJECT_WALKER_InterfaceDescriptorOffset_start 32 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_InterfaceDescriptorOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 32; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT_WALKER::Local End X */ #define GFX7_MEDIA_OBJECT_WALKER_LocalEndX_bits 9 #define GFX6_MEDIA_OBJECT_WALKER_LocalEndX_bits 9 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_LocalEndX_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 9; case 60: return 9; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX7_MEDIA_OBJECT_WALKER_LocalEndX_start 320 #define GFX6_MEDIA_OBJECT_WALKER_LocalEndX_start 320 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_LocalEndX_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 320; case 60: return 320; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT_WALKER::Local End Y */ #define GFX7_MEDIA_OBJECT_WALKER_LocalEndY_bits 9 #define GFX6_MEDIA_OBJECT_WALKER_LocalEndY_bits 9 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_LocalEndY_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 9; case 60: return 9; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX7_MEDIA_OBJECT_WALKER_LocalEndY_start 336 #define GFX6_MEDIA_OBJECT_WALKER_LocalEndY_start 336 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_LocalEndY_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 336; case 60: return 336; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT_WALKER::Local Inner Loop Unit X */ #define GFX12_MEDIA_OBJECT_WALKER_LocalInnerLoopUnitX_bits 12 #define GFX11_MEDIA_OBJECT_WALKER_LocalInnerLoopUnitX_bits 12 #define GFX9_MEDIA_OBJECT_WALKER_LocalInnerLoopUnitX_bits 12 #define GFX8_MEDIA_OBJECT_WALKER_LocalInnerLoopUnitX_bits 10 #define GFX75_MEDIA_OBJECT_WALKER_LocalInnerLoopUnitX_bits 10 #define GFX7_MEDIA_OBJECT_WALKER_LocalInnerLoopUnitX_bits 10 #define GFX6_MEDIA_OBJECT_WALKER_LocalInnerLoopUnitX_bits 10 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_LocalInnerLoopUnitX_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 12; case 110: return 12; case 90: return 12; case 80: return 10; case 75: return 10; case 70: return 10; case 60: return 10; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_OBJECT_WALKER_LocalInnerLoopUnitX_start 384 #define GFX11_MEDIA_OBJECT_WALKER_LocalInnerLoopUnitX_start 384 #define GFX9_MEDIA_OBJECT_WALKER_LocalInnerLoopUnitX_start 384 #define GFX8_MEDIA_OBJECT_WALKER_LocalInnerLoopUnitX_start 384 #define GFX75_MEDIA_OBJECT_WALKER_LocalInnerLoopUnitX_start 384 #define GFX7_MEDIA_OBJECT_WALKER_LocalInnerLoopUnitX_start 384 #define GFX6_MEDIA_OBJECT_WALKER_LocalInnerLoopUnitX_start 384 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_LocalInnerLoopUnitX_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 384; case 110: return 384; case 90: return 384; case 80: return 384; case 75: return 384; case 70: return 384; case 60: return 384; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT_WALKER::Local Inner Loop Unit Y */ #define GFX12_MEDIA_OBJECT_WALKER_LocalInnerLoopUnitY_bits 12 #define GFX11_MEDIA_OBJECT_WALKER_LocalInnerLoopUnitY_bits 12 #define GFX9_MEDIA_OBJECT_WALKER_LocalInnerLoopUnitY_bits 12 #define GFX8_MEDIA_OBJECT_WALKER_LocalInnerLoopUnitY_bits 10 #define GFX75_MEDIA_OBJECT_WALKER_LocalInnerLoopUnitY_bits 10 #define GFX7_MEDIA_OBJECT_WALKER_LocalInnerLoopUnitY_bits 10 #define GFX6_MEDIA_OBJECT_WALKER_LocalInnerLoopUnitY_bits 10 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_LocalInnerLoopUnitY_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 12; case 110: return 12; case 90: return 12; case 80: return 10; case 75: return 10; case 70: return 10; case 60: return 10; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_OBJECT_WALKER_LocalInnerLoopUnitY_start 400 #define GFX11_MEDIA_OBJECT_WALKER_LocalInnerLoopUnitY_start 400 #define GFX9_MEDIA_OBJECT_WALKER_LocalInnerLoopUnitY_start 400 #define GFX8_MEDIA_OBJECT_WALKER_LocalInnerLoopUnitY_start 400 #define GFX75_MEDIA_OBJECT_WALKER_LocalInnerLoopUnitY_start 400 #define GFX7_MEDIA_OBJECT_WALKER_LocalInnerLoopUnitY_start 400 #define GFX6_MEDIA_OBJECT_WALKER_LocalInnerLoopUnitY_start 400 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_LocalInnerLoopUnitY_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 400; case 110: return 400; case 90: return 400; case 80: return 400; case 75: return 400; case 70: return 400; case 60: return 400; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT_WALKER::Local Loop Exec Count */ #define GFX12_MEDIA_OBJECT_WALKER_LocalLoopExecCount_bits 12 #define GFX11_MEDIA_OBJECT_WALKER_LocalLoopExecCount_bits 12 #define GFX9_MEDIA_OBJECT_WALKER_LocalLoopExecCount_bits 12 #define GFX8_MEDIA_OBJECT_WALKER_LocalLoopExecCount_bits 10 #define GFX75_MEDIA_OBJECT_WALKER_LocalLoopExecCount_bits 10 #define GFX7_MEDIA_OBJECT_WALKER_LocalLoopExecCount_bits 10 #define GFX6_MEDIA_OBJECT_WALKER_LocalLoopExecCount_bits 10 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_LocalLoopExecCount_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 12; case 110: return 12; case 90: return 12; case 80: return 10; case 75: return 10; case 70: return 10; case 60: return 10; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_OBJECT_WALKER_LocalLoopExecCount_start 224 #define GFX11_MEDIA_OBJECT_WALKER_LocalLoopExecCount_start 224 #define GFX9_MEDIA_OBJECT_WALKER_LocalLoopExecCount_start 224 #define GFX8_MEDIA_OBJECT_WALKER_LocalLoopExecCount_start 224 #define GFX75_MEDIA_OBJECT_WALKER_LocalLoopExecCount_start 224 #define GFX7_MEDIA_OBJECT_WALKER_LocalLoopExecCount_start 224 #define GFX6_MEDIA_OBJECT_WALKER_LocalLoopExecCount_start 224 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_LocalLoopExecCount_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 224; case 110: return 224; case 90: return 224; case 80: return 224; case 75: return 224; case 70: return 224; case 60: return 224; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT_WALKER::Local Mid-Loop Unit Y */ #define GFX12_MEDIA_OBJECT_WALKER_LocalMidLoopUnitY_bits 2 #define GFX11_MEDIA_OBJECT_WALKER_LocalMidLoopUnitY_bits 2 #define GFX9_MEDIA_OBJECT_WALKER_LocalMidLoopUnitY_bits 2 #define GFX8_MEDIA_OBJECT_WALKER_LocalMidLoopUnitY_bits 2 #define GFX75_MEDIA_OBJECT_WALKER_LocalMidLoopUnitY_bits 2 #define GFX7_MEDIA_OBJECT_WALKER_LocalMidLoopUnitY_bits 2 #define GFX6_MEDIA_OBJECT_WALKER_LocalMidLoopUnitY_bits 2 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_LocalMidLoopUnitY_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_OBJECT_WALKER_LocalMidLoopUnitY_start 204 #define GFX11_MEDIA_OBJECT_WALKER_LocalMidLoopUnitY_start 204 #define GFX9_MEDIA_OBJECT_WALKER_LocalMidLoopUnitY_start 204 #define GFX8_MEDIA_OBJECT_WALKER_LocalMidLoopUnitY_start 204 #define GFX75_MEDIA_OBJECT_WALKER_LocalMidLoopUnitY_start 204 #define GFX7_MEDIA_OBJECT_WALKER_LocalMidLoopUnitY_start 204 #define GFX6_MEDIA_OBJECT_WALKER_LocalMidLoopUnitY_start 204 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_LocalMidLoopUnitY_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 204; case 110: return 204; case 90: return 204; case 80: return 204; case 75: return 204; case 70: return 204; case 60: return 204; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT_WALKER::Local Outer Loop Stride X */ #define GFX12_MEDIA_OBJECT_WALKER_LocalOuterLoopStrideX_bits 12 #define GFX11_MEDIA_OBJECT_WALKER_LocalOuterLoopStrideX_bits 12 #define GFX9_MEDIA_OBJECT_WALKER_LocalOuterLoopStrideX_bits 12 #define GFX8_MEDIA_OBJECT_WALKER_LocalOuterLoopStrideX_bits 10 #define GFX75_MEDIA_OBJECT_WALKER_LocalOuterLoopStrideX_bits 10 #define GFX7_MEDIA_OBJECT_WALKER_LocalOuterLoopStrideX_bits 10 #define GFX6_MEDIA_OBJECT_WALKER_LocalOuterLoopStrideX_bits 10 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_LocalOuterLoopStrideX_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 12; case 110: return 12; case 90: return 12; case 80: return 10; case 75: return 10; case 70: return 10; case 60: return 10; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_OBJECT_WALKER_LocalOuterLoopStrideX_start 352 #define GFX11_MEDIA_OBJECT_WALKER_LocalOuterLoopStrideX_start 352 #define GFX9_MEDIA_OBJECT_WALKER_LocalOuterLoopStrideX_start 352 #define GFX8_MEDIA_OBJECT_WALKER_LocalOuterLoopStrideX_start 352 #define GFX75_MEDIA_OBJECT_WALKER_LocalOuterLoopStrideX_start 352 #define GFX7_MEDIA_OBJECT_WALKER_LocalOuterLoopStrideX_start 352 #define GFX6_MEDIA_OBJECT_WALKER_LocalOuterLoopStrideX_start 352 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_LocalOuterLoopStrideX_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 352; case 110: return 352; case 90: return 352; case 80: return 352; case 75: return 352; case 70: return 352; case 60: return 352; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT_WALKER::Local Outer Loop Stride Y */ #define GFX12_MEDIA_OBJECT_WALKER_LocalOuterLoopStrideY_bits 12 #define GFX11_MEDIA_OBJECT_WALKER_LocalOuterLoopStrideY_bits 12 #define GFX9_MEDIA_OBJECT_WALKER_LocalOuterLoopStrideY_bits 12 #define GFX8_MEDIA_OBJECT_WALKER_LocalOuterLoopStrideY_bits 10 #define GFX75_MEDIA_OBJECT_WALKER_LocalOuterLoopStrideY_bits 10 #define GFX7_MEDIA_OBJECT_WALKER_LocalOuterLoopStrideY_bits 10 #define GFX6_MEDIA_OBJECT_WALKER_LocalOuterLoopStrideY_bits 10 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_LocalOuterLoopStrideY_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 12; case 110: return 12; case 90: return 12; case 80: return 10; case 75: return 10; case 70: return 10; case 60: return 10; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_OBJECT_WALKER_LocalOuterLoopStrideY_start 368 #define GFX11_MEDIA_OBJECT_WALKER_LocalOuterLoopStrideY_start 368 #define GFX9_MEDIA_OBJECT_WALKER_LocalOuterLoopStrideY_start 368 #define GFX8_MEDIA_OBJECT_WALKER_LocalOuterLoopStrideY_start 368 #define GFX75_MEDIA_OBJECT_WALKER_LocalOuterLoopStrideY_start 368 #define GFX7_MEDIA_OBJECT_WALKER_LocalOuterLoopStrideY_start 368 #define GFX6_MEDIA_OBJECT_WALKER_LocalOuterLoopStrideY_start 368 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_LocalOuterLoopStrideY_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 368; case 110: return 368; case 90: return 368; case 80: return 368; case 75: return 368; case 70: return 368; case 60: return 368; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT_WALKER::Local Start X */ #define GFX12_MEDIA_OBJECT_WALKER_LocalStartX_bits 11 #define GFX11_MEDIA_OBJECT_WALKER_LocalStartX_bits 11 #define GFX9_MEDIA_OBJECT_WALKER_LocalStartX_bits 11 #define GFX8_MEDIA_OBJECT_WALKER_LocalStartX_bits 9 #define GFX75_MEDIA_OBJECT_WALKER_LocalStartX_bits 9 #define GFX7_MEDIA_OBJECT_WALKER_LocalStartX_bits 9 #define GFX6_MEDIA_OBJECT_WALKER_LocalStartX_bits 9 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_LocalStartX_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 11; case 110: return 11; case 90: return 11; case 80: return 9; case 75: return 9; case 70: return 9; case 60: return 9; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_OBJECT_WALKER_LocalStartX_start 288 #define GFX11_MEDIA_OBJECT_WALKER_LocalStartX_start 288 #define GFX9_MEDIA_OBJECT_WALKER_LocalStartX_start 288 #define GFX8_MEDIA_OBJECT_WALKER_LocalStartX_start 288 #define GFX75_MEDIA_OBJECT_WALKER_LocalStartX_start 288 #define GFX7_MEDIA_OBJECT_WALKER_LocalStartX_start 288 #define GFX6_MEDIA_OBJECT_WALKER_LocalStartX_start 288 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_LocalStartX_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 288; case 110: return 288; case 90: return 288; case 80: return 288; case 75: return 288; case 70: return 288; case 60: return 288; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT_WALKER::Local Start Y */ #define GFX12_MEDIA_OBJECT_WALKER_LocalStartY_bits 11 #define GFX11_MEDIA_OBJECT_WALKER_LocalStartY_bits 11 #define GFX9_MEDIA_OBJECT_WALKER_LocalStartY_bits 11 #define GFX8_MEDIA_OBJECT_WALKER_LocalStartY_bits 9 #define GFX75_MEDIA_OBJECT_WALKER_LocalStartY_bits 9 #define GFX7_MEDIA_OBJECT_WALKER_LocalStartY_bits 9 #define GFX6_MEDIA_OBJECT_WALKER_LocalStartY_bits 9 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_LocalStartY_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 11; case 110: return 11; case 90: return 11; case 80: return 9; case 75: return 9; case 70: return 9; case 60: return 9; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_OBJECT_WALKER_LocalStartY_start 304 #define GFX11_MEDIA_OBJECT_WALKER_LocalStartY_start 304 #define GFX9_MEDIA_OBJECT_WALKER_LocalStartY_start 304 #define GFX8_MEDIA_OBJECT_WALKER_LocalStartY_start 304 #define GFX75_MEDIA_OBJECT_WALKER_LocalStartY_start 304 #define GFX7_MEDIA_OBJECT_WALKER_LocalStartY_start 304 #define GFX6_MEDIA_OBJECT_WALKER_LocalStartY_start 304 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_LocalStartY_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 304; case 110: return 304; case 90: return 304; case 80: return 304; case 75: return 304; case 70: return 304; case 60: return 304; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT_WALKER::Masked Dispatch */ #define GFX12_MEDIA_OBJECT_WALKER_MaskedDispatch_bits 2 #define GFX11_MEDIA_OBJECT_WALKER_MaskedDispatch_bits 2 #define GFX9_MEDIA_OBJECT_WALKER_MaskedDispatch_bits 2 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_MaskedDispatch_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_OBJECT_WALKER_MaskedDispatch_start 86 #define GFX11_MEDIA_OBJECT_WALKER_MaskedDispatch_start 86 #define GFX9_MEDIA_OBJECT_WALKER_MaskedDispatch_start 86 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_MaskedDispatch_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 86; case 110: return 86; case 90: return 86; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT_WALKER::Media Command Opcode */ #define GFX12_MEDIA_OBJECT_WALKER_MediaCommandOpcode_bits 3 #define GFX11_MEDIA_OBJECT_WALKER_MediaCommandOpcode_bits 3 #define GFX9_MEDIA_OBJECT_WALKER_MediaCommandOpcode_bits 3 #define GFX8_MEDIA_OBJECT_WALKER_MediaCommandOpcode_bits 3 #define GFX75_MEDIA_OBJECT_WALKER_MediaCommandOpcode_bits 3 #define GFX7_MEDIA_OBJECT_WALKER_MediaCommandOpcode_bits 3 #define GFX6_MEDIA_OBJECT_WALKER_MediaCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_MediaCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_OBJECT_WALKER_MediaCommandOpcode_start 24 #define GFX11_MEDIA_OBJECT_WALKER_MediaCommandOpcode_start 24 #define GFX9_MEDIA_OBJECT_WALKER_MediaCommandOpcode_start 24 #define GFX8_MEDIA_OBJECT_WALKER_MediaCommandOpcode_start 24 #define GFX75_MEDIA_OBJECT_WALKER_MediaCommandOpcode_start 24 #define GFX7_MEDIA_OBJECT_WALKER_MediaCommandOpcode_start 24 #define GFX6_MEDIA_OBJECT_WALKER_MediaCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_MediaCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 24; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT_WALKER::Mid-Loop Unit X */ #define GFX12_MEDIA_OBJECT_WALKER_MidLoopUnitX_bits 2 #define GFX11_MEDIA_OBJECT_WALKER_MidLoopUnitX_bits 2 #define GFX9_MEDIA_OBJECT_WALKER_MidLoopUnitX_bits 2 #define GFX8_MEDIA_OBJECT_WALKER_MidLoopUnitX_bits 2 #define GFX75_MEDIA_OBJECT_WALKER_MidLoopUnitX_bits 2 #define GFX7_MEDIA_OBJECT_WALKER_MidLoopUnitX_bits 2 #define GFX6_MEDIA_OBJECT_WALKER_MidLoopUnitX_bits 2 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_MidLoopUnitX_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_OBJECT_WALKER_MidLoopUnitX_start 200 #define GFX11_MEDIA_OBJECT_WALKER_MidLoopUnitX_start 200 #define GFX9_MEDIA_OBJECT_WALKER_MidLoopUnitX_start 200 #define GFX8_MEDIA_OBJECT_WALKER_MidLoopUnitX_start 200 #define GFX75_MEDIA_OBJECT_WALKER_MidLoopUnitX_start 200 #define GFX7_MEDIA_OBJECT_WALKER_MidLoopUnitX_start 200 #define GFX6_MEDIA_OBJECT_WALKER_MidLoopUnitX_start 200 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_MidLoopUnitX_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 200; case 110: return 200; case 90: return 200; case 80: return 200; case 75: return 200; case 70: return 200; case 60: return 200; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT_WALKER::Middle Loop Extra Steps */ #define GFX12_MEDIA_OBJECT_WALKER_MiddleLoopExtraSteps_bits 5 #define GFX11_MEDIA_OBJECT_WALKER_MiddleLoopExtraSteps_bits 5 #define GFX9_MEDIA_OBJECT_WALKER_MiddleLoopExtraSteps_bits 5 #define GFX8_MEDIA_OBJECT_WALKER_MiddleLoopExtraSteps_bits 5 #define GFX75_MEDIA_OBJECT_WALKER_MiddleLoopExtraSteps_bits 5 #define GFX7_MEDIA_OBJECT_WALKER_MiddleLoopExtraSteps_bits 5 #define GFX6_MEDIA_OBJECT_WALKER_MiddleLoopExtraSteps_bits 5 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_MiddleLoopExtraSteps_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 5; case 110: return 5; case 90: return 5; case 80: return 5; case 75: return 5; case 70: return 5; case 60: return 5; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_OBJECT_WALKER_MiddleLoopExtraSteps_start 208 #define GFX11_MEDIA_OBJECT_WALKER_MiddleLoopExtraSteps_start 208 #define GFX9_MEDIA_OBJECT_WALKER_MiddleLoopExtraSteps_start 208 #define GFX8_MEDIA_OBJECT_WALKER_MiddleLoopExtraSteps_start 208 #define GFX75_MEDIA_OBJECT_WALKER_MiddleLoopExtraSteps_start 208 #define GFX7_MEDIA_OBJECT_WALKER_MiddleLoopExtraSteps_start 208 #define GFX6_MEDIA_OBJECT_WALKER_MiddleLoopExtraSteps_start 208 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_MiddleLoopExtraSteps_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 208; case 110: return 208; case 90: return 208; case 80: return 208; case 75: return 208; case 70: return 208; case 60: return 208; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT_WALKER::Pipeline */ #define GFX12_MEDIA_OBJECT_WALKER_Pipeline_bits 2 #define GFX11_MEDIA_OBJECT_WALKER_Pipeline_bits 2 #define GFX9_MEDIA_OBJECT_WALKER_Pipeline_bits 2 #define GFX8_MEDIA_OBJECT_WALKER_Pipeline_bits 2 #define GFX75_MEDIA_OBJECT_WALKER_Pipeline_bits 2 #define GFX7_MEDIA_OBJECT_WALKER_Pipeline_bits 2 #define GFX6_MEDIA_OBJECT_WALKER_Pipeline_bits 2 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_Pipeline_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_OBJECT_WALKER_Pipeline_start 27 #define GFX11_MEDIA_OBJECT_WALKER_Pipeline_start 27 #define GFX9_MEDIA_OBJECT_WALKER_Pipeline_start 27 #define GFX8_MEDIA_OBJECT_WALKER_Pipeline_start 27 #define GFX75_MEDIA_OBJECT_WALKER_Pipeline_start 27 #define GFX7_MEDIA_OBJECT_WALKER_Pipeline_start 27 #define GFX6_MEDIA_OBJECT_WALKER_Pipeline_start 27 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_Pipeline_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 27; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT_WALKER::Quad Mode */ #define GFX75_MEDIA_OBJECT_WALKER_QuadMode_bits 1 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_QuadMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_MEDIA_OBJECT_WALKER_QuadMode_start 221 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_QuadMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 221; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT_WALKER::Repel */ #define GFX75_MEDIA_OBJECT_WALKER_Repel_bits 1 #define GFX7_MEDIA_OBJECT_WALKER_Repel_bits 1 #define GFX6_MEDIA_OBJECT_WALKER_Repel_bits 1 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_Repel_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_MEDIA_OBJECT_WALKER_Repel_start 222 #define GFX7_MEDIA_OBJECT_WALKER_Repel_start 222 #define GFX6_MEDIA_OBJECT_WALKER_Repel_start 222 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_Repel_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 222; case 70: return 222; case 60: return 222; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT_WALKER::Scoreboard Mask */ #define GFX9_MEDIA_OBJECT_WALKER_ScoreboardMask_bits 8 #define GFX8_MEDIA_OBJECT_WALKER_ScoreboardMask_bits 8 #define GFX75_MEDIA_OBJECT_WALKER_ScoreboardMask_bits 8 #define GFX7_MEDIA_OBJECT_WALKER_ScoreboardMask_bits 8 #define GFX6_MEDIA_OBJECT_WALKER_ScoreboardMask_bits 8 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_ScoreboardMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_MEDIA_OBJECT_WALKER_ScoreboardMask_start 160 #define GFX8_MEDIA_OBJECT_WALKER_ScoreboardMask_start 160 #define GFX75_MEDIA_OBJECT_WALKER_ScoreboardMask_start 160 #define GFX7_MEDIA_OBJECT_WALKER_ScoreboardMask_start 160 #define GFX6_MEDIA_OBJECT_WALKER_ScoreboardMask_start 160 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_ScoreboardMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 160; case 80: return 160; case 75: return 160; case 70: return 160; case 60: return 160; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT_WALKER::SubOpcode */ #define GFX12_MEDIA_OBJECT_WALKER_SubOpcode_bits 8 #define GFX11_MEDIA_OBJECT_WALKER_SubOpcode_bits 8 #define GFX9_MEDIA_OBJECT_WALKER_SubOpcode_bits 8 #define GFX8_MEDIA_OBJECT_WALKER_SubOpcode_bits 8 #define GFX75_MEDIA_OBJECT_WALKER_SubOpcode_bits 8 #define GFX7_MEDIA_OBJECT_WALKER_SubOpcode_bits 8 #define GFX6_MEDIA_OBJECT_WALKER_SubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_SubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_OBJECT_WALKER_SubOpcode_start 16 #define GFX11_MEDIA_OBJECT_WALKER_SubOpcode_start 16 #define GFX9_MEDIA_OBJECT_WALKER_SubOpcode_start 16 #define GFX8_MEDIA_OBJECT_WALKER_SubOpcode_start 16 #define GFX75_MEDIA_OBJECT_WALKER_SubOpcode_start 16 #define GFX7_MEDIA_OBJECT_WALKER_SubOpcode_start 16 #define GFX6_MEDIA_OBJECT_WALKER_SubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_SubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 16; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT_WALKER::Thread Synchronization */ #define GFX12_MEDIA_OBJECT_WALKER_ThreadSynchronization_bits 1 #define GFX11_MEDIA_OBJECT_WALKER_ThreadSynchronization_bits 1 #define GFX9_MEDIA_OBJECT_WALKER_ThreadSynchronization_bits 1 #define GFX8_MEDIA_OBJECT_WALKER_ThreadSynchronization_bits 1 #define GFX75_MEDIA_OBJECT_WALKER_ThreadSynchronization_bits 1 #define GFX7_MEDIA_OBJECT_WALKER_ThreadSynchronization_bits 1 #define GFX6_MEDIA_OBJECT_WALKER_ThreadSynchronization_bits 1 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_ThreadSynchronization_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_OBJECT_WALKER_ThreadSynchronization_start 88 #define GFX11_MEDIA_OBJECT_WALKER_ThreadSynchronization_start 88 #define GFX9_MEDIA_OBJECT_WALKER_ThreadSynchronization_start 88 #define GFX8_MEDIA_OBJECT_WALKER_ThreadSynchronization_start 88 #define GFX75_MEDIA_OBJECT_WALKER_ThreadSynchronization_start 88 #define GFX7_MEDIA_OBJECT_WALKER_ThreadSynchronization_start 88 #define GFX6_MEDIA_OBJECT_WALKER_ThreadSynchronization_start 88 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_ThreadSynchronization_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 88; case 110: return 88; case 90: return 88; case 80: return 88; case 75: return 88; case 70: return 88; case 60: return 88; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_OBJECT_WALKER::Use Scoreboard */ #define GFX9_MEDIA_OBJECT_WALKER_UseScoreboard_bits 1 #define GFX8_MEDIA_OBJECT_WALKER_UseScoreboard_bits 1 #define GFX75_MEDIA_OBJECT_WALKER_UseScoreboard_bits 1 #define GFX7_MEDIA_OBJECT_WALKER_UseScoreboard_bits 1 #define GFX6_MEDIA_OBJECT_WALKER_UseScoreboard_bits 1 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_UseScoreboard_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_MEDIA_OBJECT_WALKER_UseScoreboard_start 85 #define GFX8_MEDIA_OBJECT_WALKER_UseScoreboard_start 85 #define GFX75_MEDIA_OBJECT_WALKER_UseScoreboard_start 85 #define GFX7_MEDIA_OBJECT_WALKER_UseScoreboard_start 85 #define GFX6_MEDIA_OBJECT_WALKER_UseScoreboard_start 85 static inline uint32_t ATTRIBUTE_PURE MEDIA_OBJECT_WALKER_UseScoreboard_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 85; case 80: return 85; case 75: return 85; case 70: return 85; case 60: return 85; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_STATE_FLUSH */ #define GFX12_MEDIA_STATE_FLUSH_length 2 #define GFX11_MEDIA_STATE_FLUSH_length 2 #define GFX9_MEDIA_STATE_FLUSH_length 2 #define GFX8_MEDIA_STATE_FLUSH_length 2 #define GFX75_MEDIA_STATE_FLUSH_length 2 #define GFX7_MEDIA_STATE_FLUSH_length 2 #define GFX6_MEDIA_STATE_FLUSH_length 2 static inline uint32_t ATTRIBUTE_PURE MEDIA_STATE_FLUSH_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_STATE_FLUSH::Barrier Mask */ #define GFX6_MEDIA_STATE_FLUSH_BarrierMask_bits 16 static inline uint32_t ATTRIBUTE_PURE MEDIA_STATE_FLUSH_BarrierMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 16; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_MEDIA_STATE_FLUSH_BarrierMask_start 32 static inline uint32_t ATTRIBUTE_PURE MEDIA_STATE_FLUSH_BarrierMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 32; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_STATE_FLUSH::Command Type */ #define GFX12_MEDIA_STATE_FLUSH_CommandType_bits 3 #define GFX11_MEDIA_STATE_FLUSH_CommandType_bits 3 #define GFX9_MEDIA_STATE_FLUSH_CommandType_bits 3 #define GFX8_MEDIA_STATE_FLUSH_CommandType_bits 3 #define GFX75_MEDIA_STATE_FLUSH_CommandType_bits 3 #define GFX7_MEDIA_STATE_FLUSH_CommandType_bits 3 #define GFX6_MEDIA_STATE_FLUSH_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE MEDIA_STATE_FLUSH_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_STATE_FLUSH_CommandType_start 29 #define GFX11_MEDIA_STATE_FLUSH_CommandType_start 29 #define GFX9_MEDIA_STATE_FLUSH_CommandType_start 29 #define GFX8_MEDIA_STATE_FLUSH_CommandType_start 29 #define GFX75_MEDIA_STATE_FLUSH_CommandType_start 29 #define GFX7_MEDIA_STATE_FLUSH_CommandType_start 29 #define GFX6_MEDIA_STATE_FLUSH_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE MEDIA_STATE_FLUSH_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 29; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_STATE_FLUSH::DWord Length */ #define GFX12_MEDIA_STATE_FLUSH_DWordLength_bits 16 #define GFX11_MEDIA_STATE_FLUSH_DWordLength_bits 16 #define GFX9_MEDIA_STATE_FLUSH_DWordLength_bits 16 #define GFX8_MEDIA_STATE_FLUSH_DWordLength_bits 16 #define GFX75_MEDIA_STATE_FLUSH_DWordLength_bits 16 #define GFX7_MEDIA_STATE_FLUSH_DWordLength_bits 16 #define GFX6_MEDIA_STATE_FLUSH_DWordLength_bits 16 static inline uint32_t ATTRIBUTE_PURE MEDIA_STATE_FLUSH_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 16; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_STATE_FLUSH_DWordLength_start 0 #define GFX11_MEDIA_STATE_FLUSH_DWordLength_start 0 #define GFX9_MEDIA_STATE_FLUSH_DWordLength_start 0 #define GFX8_MEDIA_STATE_FLUSH_DWordLength_start 0 #define GFX75_MEDIA_STATE_FLUSH_DWordLength_start 0 #define GFX7_MEDIA_STATE_FLUSH_DWordLength_start 0 #define GFX6_MEDIA_STATE_FLUSH_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE MEDIA_STATE_FLUSH_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_STATE_FLUSH::Disable Preemption */ #define GFX75_MEDIA_STATE_FLUSH_DisablePreemption_bits 1 static inline uint32_t ATTRIBUTE_PURE MEDIA_STATE_FLUSH_DisablePreemption_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_MEDIA_STATE_FLUSH_DisablePreemption_start 40 static inline uint32_t ATTRIBUTE_PURE MEDIA_STATE_FLUSH_DisablePreemption_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 40; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_STATE_FLUSH::Flush to GO */ #define GFX12_MEDIA_STATE_FLUSH_FlushtoGO_bits 1 #define GFX11_MEDIA_STATE_FLUSH_FlushtoGO_bits 1 #define GFX9_MEDIA_STATE_FLUSH_FlushtoGO_bits 1 #define GFX8_MEDIA_STATE_FLUSH_FlushtoGO_bits 1 #define GFX75_MEDIA_STATE_FLUSH_FlushtoGO_bits 1 static inline uint32_t ATTRIBUTE_PURE MEDIA_STATE_FLUSH_FlushtoGO_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_STATE_FLUSH_FlushtoGO_start 39 #define GFX11_MEDIA_STATE_FLUSH_FlushtoGO_start 39 #define GFX9_MEDIA_STATE_FLUSH_FlushtoGO_start 39 #define GFX8_MEDIA_STATE_FLUSH_FlushtoGO_start 39 #define GFX75_MEDIA_STATE_FLUSH_FlushtoGO_start 39 static inline uint32_t ATTRIBUTE_PURE MEDIA_STATE_FLUSH_FlushtoGO_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 39; case 110: return 39; case 90: return 39; case 80: return 39; case 75: return 39; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_STATE_FLUSH::Interface Descriptor Offset */ #define GFX12_MEDIA_STATE_FLUSH_InterfaceDescriptorOffset_bits 6 #define GFX11_MEDIA_STATE_FLUSH_InterfaceDescriptorOffset_bits 6 #define GFX9_MEDIA_STATE_FLUSH_InterfaceDescriptorOffset_bits 6 #define GFX8_MEDIA_STATE_FLUSH_InterfaceDescriptorOffset_bits 6 #define GFX75_MEDIA_STATE_FLUSH_InterfaceDescriptorOffset_bits 6 #define GFX7_MEDIA_STATE_FLUSH_InterfaceDescriptorOffset_bits 6 static inline uint32_t ATTRIBUTE_PURE MEDIA_STATE_FLUSH_InterfaceDescriptorOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 6; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_STATE_FLUSH_InterfaceDescriptorOffset_start 32 #define GFX11_MEDIA_STATE_FLUSH_InterfaceDescriptorOffset_start 32 #define GFX9_MEDIA_STATE_FLUSH_InterfaceDescriptorOffset_start 32 #define GFX8_MEDIA_STATE_FLUSH_InterfaceDescriptorOffset_start 32 #define GFX75_MEDIA_STATE_FLUSH_InterfaceDescriptorOffset_start 32 #define GFX7_MEDIA_STATE_FLUSH_InterfaceDescriptorOffset_start 32 static inline uint32_t ATTRIBUTE_PURE MEDIA_STATE_FLUSH_InterfaceDescriptorOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_STATE_FLUSH::Media Command Opcode */ #define GFX12_MEDIA_STATE_FLUSH_MediaCommandOpcode_bits 3 #define GFX11_MEDIA_STATE_FLUSH_MediaCommandOpcode_bits 3 #define GFX9_MEDIA_STATE_FLUSH_MediaCommandOpcode_bits 3 #define GFX8_MEDIA_STATE_FLUSH_MediaCommandOpcode_bits 3 #define GFX75_MEDIA_STATE_FLUSH_MediaCommandOpcode_bits 3 #define GFX7_MEDIA_STATE_FLUSH_MediaCommandOpcode_bits 3 #define GFX6_MEDIA_STATE_FLUSH_MediaCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE MEDIA_STATE_FLUSH_MediaCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_STATE_FLUSH_MediaCommandOpcode_start 24 #define GFX11_MEDIA_STATE_FLUSH_MediaCommandOpcode_start 24 #define GFX9_MEDIA_STATE_FLUSH_MediaCommandOpcode_start 24 #define GFX8_MEDIA_STATE_FLUSH_MediaCommandOpcode_start 24 #define GFX75_MEDIA_STATE_FLUSH_MediaCommandOpcode_start 24 #define GFX7_MEDIA_STATE_FLUSH_MediaCommandOpcode_start 24 #define GFX6_MEDIA_STATE_FLUSH_MediaCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE MEDIA_STATE_FLUSH_MediaCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 24; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_STATE_FLUSH::Pipeline */ #define GFX12_MEDIA_STATE_FLUSH_Pipeline_bits 2 #define GFX11_MEDIA_STATE_FLUSH_Pipeline_bits 2 #define GFX9_MEDIA_STATE_FLUSH_Pipeline_bits 2 #define GFX8_MEDIA_STATE_FLUSH_Pipeline_bits 2 #define GFX75_MEDIA_STATE_FLUSH_Pipeline_bits 2 #define GFX7_MEDIA_STATE_FLUSH_Pipeline_bits 2 #define GFX6_MEDIA_STATE_FLUSH_Pipeline_bits 2 static inline uint32_t ATTRIBUTE_PURE MEDIA_STATE_FLUSH_Pipeline_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_STATE_FLUSH_Pipeline_start 27 #define GFX11_MEDIA_STATE_FLUSH_Pipeline_start 27 #define GFX9_MEDIA_STATE_FLUSH_Pipeline_start 27 #define GFX8_MEDIA_STATE_FLUSH_Pipeline_start 27 #define GFX75_MEDIA_STATE_FLUSH_Pipeline_start 27 #define GFX7_MEDIA_STATE_FLUSH_Pipeline_start 27 #define GFX6_MEDIA_STATE_FLUSH_Pipeline_start 27 static inline uint32_t ATTRIBUTE_PURE MEDIA_STATE_FLUSH_Pipeline_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 27; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_STATE_FLUSH::SubOpcode */ #define GFX12_MEDIA_STATE_FLUSH_SubOpcode_bits 8 #define GFX11_MEDIA_STATE_FLUSH_SubOpcode_bits 8 #define GFX9_MEDIA_STATE_FLUSH_SubOpcode_bits 8 #define GFX8_MEDIA_STATE_FLUSH_SubOpcode_bits 8 #define GFX75_MEDIA_STATE_FLUSH_SubOpcode_bits 8 #define GFX7_MEDIA_STATE_FLUSH_SubOpcode_bits 8 #define GFX6_MEDIA_STATE_FLUSH_SubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE MEDIA_STATE_FLUSH_SubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_STATE_FLUSH_SubOpcode_start 16 #define GFX11_MEDIA_STATE_FLUSH_SubOpcode_start 16 #define GFX9_MEDIA_STATE_FLUSH_SubOpcode_start 16 #define GFX8_MEDIA_STATE_FLUSH_SubOpcode_start 16 #define GFX75_MEDIA_STATE_FLUSH_SubOpcode_start 16 #define GFX7_MEDIA_STATE_FLUSH_SubOpcode_start 16 #define GFX6_MEDIA_STATE_FLUSH_SubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE MEDIA_STATE_FLUSH_SubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 16; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_STATE_FLUSH::Thread Count WaterMark */ #define GFX6_MEDIA_STATE_FLUSH_ThreadCountWaterMark_bits 8 static inline uint32_t ATTRIBUTE_PURE MEDIA_STATE_FLUSH_ThreadCountWaterMark_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_MEDIA_STATE_FLUSH_ThreadCountWaterMark_start 48 static inline uint32_t ATTRIBUTE_PURE MEDIA_STATE_FLUSH_ThreadCountWaterMark_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 48; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_STATE_FLUSH::Watermark Required */ #define GFX9_MEDIA_STATE_FLUSH_WatermarkRequired_bits 1 #define GFX8_MEDIA_STATE_FLUSH_WatermarkRequired_bits 1 #define GFX75_MEDIA_STATE_FLUSH_WatermarkRequired_bits 1 #define GFX7_MEDIA_STATE_FLUSH_WatermarkRequired_bits 1 static inline uint32_t ATTRIBUTE_PURE MEDIA_STATE_FLUSH_WatermarkRequired_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_MEDIA_STATE_FLUSH_WatermarkRequired_start 38 #define GFX8_MEDIA_STATE_FLUSH_WatermarkRequired_start 38 #define GFX75_MEDIA_STATE_FLUSH_WatermarkRequired_start 38 #define GFX7_MEDIA_STATE_FLUSH_WatermarkRequired_start 38 static inline uint32_t ATTRIBUTE_PURE MEDIA_STATE_FLUSH_WatermarkRequired_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 38; case 80: return 38; case 75: return 38; case 70: return 38; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_VFE_STATE */ #define GFX12_MEDIA_VFE_STATE_length 9 #define GFX11_MEDIA_VFE_STATE_length 9 #define GFX9_MEDIA_VFE_STATE_length 9 #define GFX8_MEDIA_VFE_STATE_length 9 #define GFX75_MEDIA_VFE_STATE_length 8 #define GFX7_MEDIA_VFE_STATE_length 8 #define GFX6_MEDIA_VFE_STATE_length 8 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 9; case 110: return 9; case 90: return 9; case 80: return 9; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_VFE_STATE::Bypass Gateway Control */ #define GFX8_MEDIA_VFE_STATE_BypassGatewayControl_bits 1 #define GFX75_MEDIA_VFE_STATE_BypassGatewayControl_bits 1 #define GFX7_MEDIA_VFE_STATE_BypassGatewayControl_bits 1 #define GFX6_MEDIA_VFE_STATE_BypassGatewayControl_bits 1 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_BypassGatewayControl_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX8_MEDIA_VFE_STATE_BypassGatewayControl_start 102 #define GFX75_MEDIA_VFE_STATE_BypassGatewayControl_start 70 #define GFX7_MEDIA_VFE_STATE_BypassGatewayControl_start 70 #define GFX6_MEDIA_VFE_STATE_BypassGatewayControl_start 70 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_BypassGatewayControl_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 102; case 75: return 70; case 70: return 70; case 60: return 70; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_VFE_STATE::CURBE Allocation Size */ #define GFX12_MEDIA_VFE_STATE_CURBEAllocationSize_bits 16 #define GFX11_MEDIA_VFE_STATE_CURBEAllocationSize_bits 16 #define GFX9_MEDIA_VFE_STATE_CURBEAllocationSize_bits 16 #define GFX8_MEDIA_VFE_STATE_CURBEAllocationSize_bits 16 #define GFX75_MEDIA_VFE_STATE_CURBEAllocationSize_bits 16 #define GFX7_MEDIA_VFE_STATE_CURBEAllocationSize_bits 16 #define GFX6_MEDIA_VFE_STATE_CURBEAllocationSize_bits 16 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_CURBEAllocationSize_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 16; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_VFE_STATE_CURBEAllocationSize_start 160 #define GFX11_MEDIA_VFE_STATE_CURBEAllocationSize_start 160 #define GFX9_MEDIA_VFE_STATE_CURBEAllocationSize_start 160 #define GFX8_MEDIA_VFE_STATE_CURBEAllocationSize_start 160 #define GFX75_MEDIA_VFE_STATE_CURBEAllocationSize_start 128 #define GFX7_MEDIA_VFE_STATE_CURBEAllocationSize_start 128 #define GFX6_MEDIA_VFE_STATE_CURBEAllocationSize_start 128 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_CURBEAllocationSize_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 160; case 110: return 160; case 90: return 160; case 80: return 160; case 75: return 128; case 70: return 128; case 60: return 128; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_VFE_STATE::Command Type */ #define GFX12_MEDIA_VFE_STATE_CommandType_bits 3 #define GFX11_MEDIA_VFE_STATE_CommandType_bits 3 #define GFX9_MEDIA_VFE_STATE_CommandType_bits 3 #define GFX8_MEDIA_VFE_STATE_CommandType_bits 3 #define GFX75_MEDIA_VFE_STATE_CommandType_bits 3 #define GFX7_MEDIA_VFE_STATE_CommandType_bits 3 #define GFX6_MEDIA_VFE_STATE_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_VFE_STATE_CommandType_start 29 #define GFX11_MEDIA_VFE_STATE_CommandType_start 29 #define GFX9_MEDIA_VFE_STATE_CommandType_start 29 #define GFX8_MEDIA_VFE_STATE_CommandType_start 29 #define GFX75_MEDIA_VFE_STATE_CommandType_start 29 #define GFX7_MEDIA_VFE_STATE_CommandType_start 29 #define GFX6_MEDIA_VFE_STATE_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 29; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_VFE_STATE::DWord Length */ #define GFX12_MEDIA_VFE_STATE_DWordLength_bits 16 #define GFX11_MEDIA_VFE_STATE_DWordLength_bits 16 #define GFX9_MEDIA_VFE_STATE_DWordLength_bits 16 #define GFX8_MEDIA_VFE_STATE_DWordLength_bits 16 #define GFX75_MEDIA_VFE_STATE_DWordLength_bits 16 #define GFX7_MEDIA_VFE_STATE_DWordLength_bits 16 #define GFX6_MEDIA_VFE_STATE_DWordLength_bits 16 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 16; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_VFE_STATE_DWordLength_start 0 #define GFX11_MEDIA_VFE_STATE_DWordLength_start 0 #define GFX9_MEDIA_VFE_STATE_DWordLength_start 0 #define GFX8_MEDIA_VFE_STATE_DWordLength_start 0 #define GFX75_MEDIA_VFE_STATE_DWordLength_start 0 #define GFX7_MEDIA_VFE_STATE_DWordLength_start 0 #define GFX6_MEDIA_VFE_STATE_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_VFE_STATE::Dispatch Load Balance */ #define GFX12_MEDIA_VFE_STATE_DispatchLoadBalance_bits 1 #define GFX11_MEDIA_VFE_STATE_DispatchLoadBalance_bits 1 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_DispatchLoadBalance_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_VFE_STATE_DispatchLoadBalance_start 98 #define GFX11_MEDIA_VFE_STATE_DispatchLoadBalance_start 98 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_DispatchLoadBalance_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 98; case 110: return 98; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_VFE_STATE::Fast Preempt */ #define GFX6_MEDIA_VFE_STATE_FastPreempt_bits 1 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_FastPreempt_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_MEDIA_VFE_STATE_FastPreempt_start 69 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_FastPreempt_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 69; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_VFE_STATE::GPGPU Mode */ #define GFX75_MEDIA_VFE_STATE_GPGPUMode_bits 1 #define GFX7_MEDIA_VFE_STATE_GPGPUMode_bits 1 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_GPGPUMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_MEDIA_VFE_STATE_GPGPUMode_start 66 #define GFX7_MEDIA_VFE_STATE_GPGPUMode_start 66 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_GPGPUMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 66; case 70: return 66; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_VFE_STATE::Gateway MMIO Access Control */ #define GFX7_MEDIA_VFE_STATE_GatewayMMIOAccessControl_bits 2 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_GatewayMMIOAccessControl_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX7_MEDIA_VFE_STATE_GatewayMMIOAccessControl_start 67 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_GatewayMMIOAccessControl_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 67; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_VFE_STATE::Half-Slice Disable */ #define GFX75_MEDIA_VFE_STATE_HalfSliceDisable_bits 2 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_HalfSliceDisable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 2; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_MEDIA_VFE_STATE_HalfSliceDisable_start 96 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_HalfSliceDisable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 96; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_VFE_STATE::Maximum Number of Dual-Subslices */ #define GFX12_MEDIA_VFE_STATE_MaximumNumberofDualSubslices_bits 8 #define GFX11_MEDIA_VFE_STATE_MaximumNumberofDualSubslices_bits 8 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_MaximumNumberofDualSubslices_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 8; case 110: return 8; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_VFE_STATE_MaximumNumberofDualSubslices_start 128 #define GFX11_MEDIA_VFE_STATE_MaximumNumberofDualSubslices_start 128 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_MaximumNumberofDualSubslices_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 128; case 110: return 128; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_VFE_STATE::Maximum Number of Threads */ #define GFX12_MEDIA_VFE_STATE_MaximumNumberofThreads_bits 16 #define GFX11_MEDIA_VFE_STATE_MaximumNumberofThreads_bits 16 #define GFX9_MEDIA_VFE_STATE_MaximumNumberofThreads_bits 16 #define GFX8_MEDIA_VFE_STATE_MaximumNumberofThreads_bits 16 #define GFX75_MEDIA_VFE_STATE_MaximumNumberofThreads_bits 16 #define GFX7_MEDIA_VFE_STATE_MaximumNumberofThreads_bits 16 #define GFX6_MEDIA_VFE_STATE_MaximumNumberofThreads_bits 16 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_MaximumNumberofThreads_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 16; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_VFE_STATE_MaximumNumberofThreads_start 112 #define GFX11_MEDIA_VFE_STATE_MaximumNumberofThreads_start 112 #define GFX9_MEDIA_VFE_STATE_MaximumNumberofThreads_start 112 #define GFX8_MEDIA_VFE_STATE_MaximumNumberofThreads_start 112 #define GFX75_MEDIA_VFE_STATE_MaximumNumberofThreads_start 80 #define GFX7_MEDIA_VFE_STATE_MaximumNumberofThreads_start 80 #define GFX6_MEDIA_VFE_STATE_MaximumNumberofThreads_start 80 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_MaximumNumberofThreads_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 112; case 110: return 112; case 90: return 112; case 80: return 112; case 75: return 80; case 70: return 80; case 60: return 80; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_VFE_STATE::Media Command Opcode */ #define GFX12_MEDIA_VFE_STATE_MediaCommandOpcode_bits 3 #define GFX11_MEDIA_VFE_STATE_MediaCommandOpcode_bits 3 #define GFX9_MEDIA_VFE_STATE_MediaCommandOpcode_bits 3 #define GFX8_MEDIA_VFE_STATE_MediaCommandOpcode_bits 3 #define GFX75_MEDIA_VFE_STATE_MediaCommandOpcode_bits 3 #define GFX7_MEDIA_VFE_STATE_MediaCommandOpcode_bits 3 #define GFX6_MEDIA_VFE_STATE_MediaCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_MediaCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_VFE_STATE_MediaCommandOpcode_start 24 #define GFX11_MEDIA_VFE_STATE_MediaCommandOpcode_start 24 #define GFX9_MEDIA_VFE_STATE_MediaCommandOpcode_start 24 #define GFX8_MEDIA_VFE_STATE_MediaCommandOpcode_start 24 #define GFX75_MEDIA_VFE_STATE_MediaCommandOpcode_start 24 #define GFX7_MEDIA_VFE_STATE_MediaCommandOpcode_start 24 #define GFX6_MEDIA_VFE_STATE_MediaCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_MediaCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 24; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_VFE_STATE::Number of URB Entries */ #define GFX12_MEDIA_VFE_STATE_NumberofURBEntries_bits 8 #define GFX11_MEDIA_VFE_STATE_NumberofURBEntries_bits 8 #define GFX9_MEDIA_VFE_STATE_NumberofURBEntries_bits 8 #define GFX8_MEDIA_VFE_STATE_NumberofURBEntries_bits 8 #define GFX75_MEDIA_VFE_STATE_NumberofURBEntries_bits 8 #define GFX7_MEDIA_VFE_STATE_NumberofURBEntries_bits 8 #define GFX6_MEDIA_VFE_STATE_NumberofURBEntries_bits 8 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_NumberofURBEntries_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_VFE_STATE_NumberofURBEntries_start 104 #define GFX11_MEDIA_VFE_STATE_NumberofURBEntries_start 104 #define GFX9_MEDIA_VFE_STATE_NumberofURBEntries_start 104 #define GFX8_MEDIA_VFE_STATE_NumberofURBEntries_start 104 #define GFX75_MEDIA_VFE_STATE_NumberofURBEntries_start 72 #define GFX7_MEDIA_VFE_STATE_NumberofURBEntries_start 72 #define GFX6_MEDIA_VFE_STATE_NumberofURBEntries_start 72 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_NumberofURBEntries_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 104; case 110: return 104; case 90: return 104; case 80: return 104; case 75: return 72; case 70: return 72; case 60: return 72; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_VFE_STATE::Per Thread Scratch Space */ #define GFX12_MEDIA_VFE_STATE_PerThreadScratchSpace_bits 4 #define GFX11_MEDIA_VFE_STATE_PerThreadScratchSpace_bits 4 #define GFX9_MEDIA_VFE_STATE_PerThreadScratchSpace_bits 4 #define GFX8_MEDIA_VFE_STATE_PerThreadScratchSpace_bits 4 #define GFX75_MEDIA_VFE_STATE_PerThreadScratchSpace_bits 4 #define GFX7_MEDIA_VFE_STATE_PerThreadScratchSpace_bits 4 #define GFX6_MEDIA_VFE_STATE_PerThreadScratchSpace_bits 4 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_PerThreadScratchSpace_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 4; case 70: return 4; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_VFE_STATE_PerThreadScratchSpace_start 32 #define GFX11_MEDIA_VFE_STATE_PerThreadScratchSpace_start 32 #define GFX9_MEDIA_VFE_STATE_PerThreadScratchSpace_start 32 #define GFX8_MEDIA_VFE_STATE_PerThreadScratchSpace_start 32 #define GFX75_MEDIA_VFE_STATE_PerThreadScratchSpace_start 32 #define GFX7_MEDIA_VFE_STATE_PerThreadScratchSpace_start 32 #define GFX6_MEDIA_VFE_STATE_PerThreadScratchSpace_start 32 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_PerThreadScratchSpace_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 32; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_VFE_STATE::Pipeline */ #define GFX12_MEDIA_VFE_STATE_Pipeline_bits 2 #define GFX11_MEDIA_VFE_STATE_Pipeline_bits 2 #define GFX9_MEDIA_VFE_STATE_Pipeline_bits 2 #define GFX8_MEDIA_VFE_STATE_Pipeline_bits 2 #define GFX75_MEDIA_VFE_STATE_Pipeline_bits 2 #define GFX7_MEDIA_VFE_STATE_Pipeline_bits 2 #define GFX6_MEDIA_VFE_STATE_Pipeline_bits 2 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_Pipeline_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_VFE_STATE_Pipeline_start 27 #define GFX11_MEDIA_VFE_STATE_Pipeline_start 27 #define GFX9_MEDIA_VFE_STATE_Pipeline_start 27 #define GFX8_MEDIA_VFE_STATE_Pipeline_start 27 #define GFX75_MEDIA_VFE_STATE_Pipeline_start 27 #define GFX7_MEDIA_VFE_STATE_Pipeline_start 27 #define GFX6_MEDIA_VFE_STATE_Pipeline_start 27 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_Pipeline_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 27; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_VFE_STATE::Reset Gateway Timer */ #define GFX9_MEDIA_VFE_STATE_ResetGatewayTimer_bits 1 #define GFX8_MEDIA_VFE_STATE_ResetGatewayTimer_bits 1 #define GFX75_MEDIA_VFE_STATE_ResetGatewayTimer_bits 1 #define GFX7_MEDIA_VFE_STATE_ResetGatewayTimer_bits 1 #define GFX6_MEDIA_VFE_STATE_ResetGatewayTimer_bits 1 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_ResetGatewayTimer_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_MEDIA_VFE_STATE_ResetGatewayTimer_start 103 #define GFX8_MEDIA_VFE_STATE_ResetGatewayTimer_start 103 #define GFX75_MEDIA_VFE_STATE_ResetGatewayTimer_start 71 #define GFX7_MEDIA_VFE_STATE_ResetGatewayTimer_start 71 #define GFX6_MEDIA_VFE_STATE_ResetGatewayTimer_start 71 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_ResetGatewayTimer_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 103; case 80: return 103; case 75: return 71; case 70: return 71; case 60: return 71; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_VFE_STATE::Scoreboard 0 Delta X */ #define GFX9_MEDIA_VFE_STATE_Scoreboard0DeltaX_bits 4 #define GFX8_MEDIA_VFE_STATE_Scoreboard0DeltaX_bits 4 #define GFX75_MEDIA_VFE_STATE_Scoreboard0DeltaX_bits 4 #define GFX7_MEDIA_VFE_STATE_Scoreboard0DeltaX_bits 4 #define GFX6_MEDIA_VFE_STATE_Scoreboard0DeltaX_bits 4 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_Scoreboard0DeltaX_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 4; case 80: return 4; case 75: return 4; case 70: return 4; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_MEDIA_VFE_STATE_Scoreboard0DeltaX_start 224 #define GFX8_MEDIA_VFE_STATE_Scoreboard0DeltaX_start 224 #define GFX75_MEDIA_VFE_STATE_Scoreboard0DeltaX_start 192 #define GFX7_MEDIA_VFE_STATE_Scoreboard0DeltaX_start 192 #define GFX6_MEDIA_VFE_STATE_Scoreboard0DeltaX_start 192 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_Scoreboard0DeltaX_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 224; case 80: return 224; case 75: return 192; case 70: return 192; case 60: return 192; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_VFE_STATE::Scoreboard 0 Delta Y */ #define GFX9_MEDIA_VFE_STATE_Scoreboard0DeltaY_bits 4 #define GFX8_MEDIA_VFE_STATE_Scoreboard0DeltaY_bits 4 #define GFX75_MEDIA_VFE_STATE_Scoreboard0DeltaY_bits 4 #define GFX7_MEDIA_VFE_STATE_Scoreboard0DeltaY_bits 4 #define GFX6_MEDIA_VFE_STATE_Scoreboard0DeltaY_bits 4 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_Scoreboard0DeltaY_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 4; case 80: return 4; case 75: return 4; case 70: return 4; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_MEDIA_VFE_STATE_Scoreboard0DeltaY_start 228 #define GFX8_MEDIA_VFE_STATE_Scoreboard0DeltaY_start 228 #define GFX75_MEDIA_VFE_STATE_Scoreboard0DeltaY_start 196 #define GFX7_MEDIA_VFE_STATE_Scoreboard0DeltaY_start 196 #define GFX6_MEDIA_VFE_STATE_Scoreboard0DeltaY_start 196 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_Scoreboard0DeltaY_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 228; case 80: return 228; case 75: return 196; case 70: return 196; case 60: return 196; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_VFE_STATE::Scoreboard 1 Delta X */ #define GFX9_MEDIA_VFE_STATE_Scoreboard1DeltaX_bits 4 #define GFX8_MEDIA_VFE_STATE_Scoreboard1DeltaX_bits 4 #define GFX75_MEDIA_VFE_STATE_Scoreboard1DeltaX_bits 4 #define GFX7_MEDIA_VFE_STATE_Scoreboard1DeltaX_bits 4 #define GFX6_MEDIA_VFE_STATE_Scoreboard1DeltaX_bits 4 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_Scoreboard1DeltaX_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 4; case 80: return 4; case 75: return 4; case 70: return 4; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_MEDIA_VFE_STATE_Scoreboard1DeltaX_start 232 #define GFX8_MEDIA_VFE_STATE_Scoreboard1DeltaX_start 232 #define GFX75_MEDIA_VFE_STATE_Scoreboard1DeltaX_start 200 #define GFX7_MEDIA_VFE_STATE_Scoreboard1DeltaX_start 200 #define GFX6_MEDIA_VFE_STATE_Scoreboard1DeltaX_start 200 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_Scoreboard1DeltaX_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 232; case 80: return 232; case 75: return 200; case 70: return 200; case 60: return 200; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_VFE_STATE::Scoreboard 1 Delta Y */ #define GFX9_MEDIA_VFE_STATE_Scoreboard1DeltaY_bits 4 #define GFX8_MEDIA_VFE_STATE_Scoreboard1DeltaY_bits 4 #define GFX75_MEDIA_VFE_STATE_Scoreboard1DeltaY_bits 4 #define GFX7_MEDIA_VFE_STATE_Scoreboard1DeltaY_bits 4 #define GFX6_MEDIA_VFE_STATE_Scoreboard1DeltaY_bits 4 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_Scoreboard1DeltaY_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 4; case 80: return 4; case 75: return 4; case 70: return 4; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_MEDIA_VFE_STATE_Scoreboard1DeltaY_start 236 #define GFX8_MEDIA_VFE_STATE_Scoreboard1DeltaY_start 236 #define GFX75_MEDIA_VFE_STATE_Scoreboard1DeltaY_start 204 #define GFX7_MEDIA_VFE_STATE_Scoreboard1DeltaY_start 204 #define GFX6_MEDIA_VFE_STATE_Scoreboard1DeltaY_start 204 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_Scoreboard1DeltaY_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 236; case 80: return 236; case 75: return 204; case 70: return 204; case 60: return 204; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_VFE_STATE::Scoreboard 2 Delta X */ #define GFX9_MEDIA_VFE_STATE_Scoreboard2DeltaX_bits 4 #define GFX8_MEDIA_VFE_STATE_Scoreboard2DeltaX_bits 4 #define GFX75_MEDIA_VFE_STATE_Scoreboard2DeltaX_bits 4 #define GFX7_MEDIA_VFE_STATE_Scoreboard2DeltaX_bits 4 #define GFX6_MEDIA_VFE_STATE_Scoreboard2DeltaX_bits 4 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_Scoreboard2DeltaX_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 4; case 80: return 4; case 75: return 4; case 70: return 4; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_MEDIA_VFE_STATE_Scoreboard2DeltaX_start 240 #define GFX8_MEDIA_VFE_STATE_Scoreboard2DeltaX_start 240 #define GFX75_MEDIA_VFE_STATE_Scoreboard2DeltaX_start 208 #define GFX7_MEDIA_VFE_STATE_Scoreboard2DeltaX_start 208 #define GFX6_MEDIA_VFE_STATE_Scoreboard2DeltaX_start 208 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_Scoreboard2DeltaX_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 240; case 80: return 240; case 75: return 208; case 70: return 208; case 60: return 208; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_VFE_STATE::Scoreboard 2 Delta Y */ #define GFX9_MEDIA_VFE_STATE_Scoreboard2DeltaY_bits 4 #define GFX8_MEDIA_VFE_STATE_Scoreboard2DeltaY_bits 4 #define GFX75_MEDIA_VFE_STATE_Scoreboard2DeltaY_bits 4 #define GFX7_MEDIA_VFE_STATE_Scoreboard2DeltaY_bits 4 #define GFX6_MEDIA_VFE_STATE_Scoreboard2DeltaY_bits 4 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_Scoreboard2DeltaY_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 4; case 80: return 4; case 75: return 4; case 70: return 4; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_MEDIA_VFE_STATE_Scoreboard2DeltaY_start 244 #define GFX8_MEDIA_VFE_STATE_Scoreboard2DeltaY_start 244 #define GFX75_MEDIA_VFE_STATE_Scoreboard2DeltaY_start 212 #define GFX7_MEDIA_VFE_STATE_Scoreboard2DeltaY_start 212 #define GFX6_MEDIA_VFE_STATE_Scoreboard2DeltaY_start 212 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_Scoreboard2DeltaY_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 244; case 80: return 244; case 75: return 212; case 70: return 212; case 60: return 212; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_VFE_STATE::Scoreboard 3 Delta X */ #define GFX9_MEDIA_VFE_STATE_Scoreboard3DeltaX_bits 4 #define GFX8_MEDIA_VFE_STATE_Scoreboard3DeltaX_bits 4 #define GFX75_MEDIA_VFE_STATE_Scoreboard3DeltaX_bits 4 #define GFX7_MEDIA_VFE_STATE_Scoreboard3DeltaX_bits 4 #define GFX6_MEDIA_VFE_STATE_Scoreboard3DeltaX_bits 4 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_Scoreboard3DeltaX_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 4; case 80: return 4; case 75: return 4; case 70: return 4; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_MEDIA_VFE_STATE_Scoreboard3DeltaX_start 248 #define GFX8_MEDIA_VFE_STATE_Scoreboard3DeltaX_start 248 #define GFX75_MEDIA_VFE_STATE_Scoreboard3DeltaX_start 216 #define GFX7_MEDIA_VFE_STATE_Scoreboard3DeltaX_start 216 #define GFX6_MEDIA_VFE_STATE_Scoreboard3DeltaX_start 216 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_Scoreboard3DeltaX_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 248; case 80: return 248; case 75: return 216; case 70: return 216; case 60: return 216; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_VFE_STATE::Scoreboard 3 Delta Y */ #define GFX9_MEDIA_VFE_STATE_Scoreboard3DeltaY_bits 4 #define GFX8_MEDIA_VFE_STATE_Scoreboard3DeltaY_bits 4 #define GFX75_MEDIA_VFE_STATE_Scoreboard3DeltaY_bits 4 #define GFX7_MEDIA_VFE_STATE_Scoreboard3DeltaY_bits 4 #define GFX6_MEDIA_VFE_STATE_Scoreboard3DeltaY_bits 4 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_Scoreboard3DeltaY_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 4; case 80: return 4; case 75: return 4; case 70: return 4; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_MEDIA_VFE_STATE_Scoreboard3DeltaY_start 252 #define GFX8_MEDIA_VFE_STATE_Scoreboard3DeltaY_start 252 #define GFX75_MEDIA_VFE_STATE_Scoreboard3DeltaY_start 220 #define GFX7_MEDIA_VFE_STATE_Scoreboard3DeltaY_start 220 #define GFX6_MEDIA_VFE_STATE_Scoreboard3DeltaY_start 220 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_Scoreboard3DeltaY_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 252; case 80: return 252; case 75: return 220; case 70: return 220; case 60: return 220; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_VFE_STATE::Scoreboard 4 Delta X */ #define GFX9_MEDIA_VFE_STATE_Scoreboard4DeltaX_bits 4 #define GFX8_MEDIA_VFE_STATE_Scoreboard4DeltaX_bits 4 #define GFX75_MEDIA_VFE_STATE_Scoreboard4DeltaX_bits 4 #define GFX7_MEDIA_VFE_STATE_Scoreboard4DeltaX_bits 4 #define GFX6_MEDIA_VFE_STATE_Scoreboard4DeltaX_bits 4 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_Scoreboard4DeltaX_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 4; case 80: return 4; case 75: return 4; case 70: return 4; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_MEDIA_VFE_STATE_Scoreboard4DeltaX_start 256 #define GFX8_MEDIA_VFE_STATE_Scoreboard4DeltaX_start 256 #define GFX75_MEDIA_VFE_STATE_Scoreboard4DeltaX_start 224 #define GFX7_MEDIA_VFE_STATE_Scoreboard4DeltaX_start 224 #define GFX6_MEDIA_VFE_STATE_Scoreboard4DeltaX_start 224 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_Scoreboard4DeltaX_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 256; case 80: return 256; case 75: return 224; case 70: return 224; case 60: return 224; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_VFE_STATE::Scoreboard 4 Delta Y */ #define GFX9_MEDIA_VFE_STATE_Scoreboard4DeltaY_bits 4 #define GFX8_MEDIA_VFE_STATE_Scoreboard4DeltaY_bits 4 #define GFX75_MEDIA_VFE_STATE_Scoreboard4DeltaY_bits 4 #define GFX7_MEDIA_VFE_STATE_Scoreboard4DeltaY_bits 4 #define GFX6_MEDIA_VFE_STATE_Scoreboard4DeltaY_bits 4 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_Scoreboard4DeltaY_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 4; case 80: return 4; case 75: return 4; case 70: return 4; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_MEDIA_VFE_STATE_Scoreboard4DeltaY_start 260 #define GFX8_MEDIA_VFE_STATE_Scoreboard4DeltaY_start 260 #define GFX75_MEDIA_VFE_STATE_Scoreboard4DeltaY_start 228 #define GFX7_MEDIA_VFE_STATE_Scoreboard4DeltaY_start 228 #define GFX6_MEDIA_VFE_STATE_Scoreboard4DeltaY_start 228 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_Scoreboard4DeltaY_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 260; case 80: return 260; case 75: return 228; case 70: return 228; case 60: return 228; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_VFE_STATE::Scoreboard 5 Delta X */ #define GFX9_MEDIA_VFE_STATE_Scoreboard5DeltaX_bits 4 #define GFX8_MEDIA_VFE_STATE_Scoreboard5DeltaX_bits 4 #define GFX75_MEDIA_VFE_STATE_Scoreboard5DeltaX_bits 4 #define GFX7_MEDIA_VFE_STATE_Scoreboard5DeltaX_bits 4 #define GFX6_MEDIA_VFE_STATE_Scoreboard5DeltaX_bits 4 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_Scoreboard5DeltaX_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 4; case 80: return 4; case 75: return 4; case 70: return 4; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_MEDIA_VFE_STATE_Scoreboard5DeltaX_start 264 #define GFX8_MEDIA_VFE_STATE_Scoreboard5DeltaX_start 264 #define GFX75_MEDIA_VFE_STATE_Scoreboard5DeltaX_start 232 #define GFX7_MEDIA_VFE_STATE_Scoreboard5DeltaX_start 232 #define GFX6_MEDIA_VFE_STATE_Scoreboard5DeltaX_start 232 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_Scoreboard5DeltaX_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 264; case 80: return 264; case 75: return 232; case 70: return 232; case 60: return 232; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_VFE_STATE::Scoreboard 5 Delta Y */ #define GFX9_MEDIA_VFE_STATE_Scoreboard5DeltaY_bits 4 #define GFX8_MEDIA_VFE_STATE_Scoreboard5DeltaY_bits 4 #define GFX75_MEDIA_VFE_STATE_Scoreboard5DeltaY_bits 4 #define GFX7_MEDIA_VFE_STATE_Scoreboard5DeltaY_bits 4 #define GFX6_MEDIA_VFE_STATE_Scoreboard5DeltaY_bits 4 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_Scoreboard5DeltaY_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 4; case 80: return 4; case 75: return 4; case 70: return 4; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_MEDIA_VFE_STATE_Scoreboard5DeltaY_start 268 #define GFX8_MEDIA_VFE_STATE_Scoreboard5DeltaY_start 268 #define GFX75_MEDIA_VFE_STATE_Scoreboard5DeltaY_start 236 #define GFX7_MEDIA_VFE_STATE_Scoreboard5DeltaY_start 236 #define GFX6_MEDIA_VFE_STATE_Scoreboard5DeltaY_start 236 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_Scoreboard5DeltaY_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 268; case 80: return 268; case 75: return 236; case 70: return 236; case 60: return 236; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_VFE_STATE::Scoreboard 6 Delta X */ #define GFX9_MEDIA_VFE_STATE_Scoreboard6DeltaX_bits 4 #define GFX8_MEDIA_VFE_STATE_Scoreboard6DeltaX_bits 4 #define GFX75_MEDIA_VFE_STATE_Scoreboard6DeltaX_bits 4 #define GFX7_MEDIA_VFE_STATE_Scoreboard6DeltaX_bits 4 #define GFX6_MEDIA_VFE_STATE_Scoreboard6DeltaX_bits 4 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_Scoreboard6DeltaX_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 4; case 80: return 4; case 75: return 4; case 70: return 4; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_MEDIA_VFE_STATE_Scoreboard6DeltaX_start 272 #define GFX8_MEDIA_VFE_STATE_Scoreboard6DeltaX_start 272 #define GFX75_MEDIA_VFE_STATE_Scoreboard6DeltaX_start 240 #define GFX7_MEDIA_VFE_STATE_Scoreboard6DeltaX_start 240 #define GFX6_MEDIA_VFE_STATE_Scoreboard6DeltaX_start 240 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_Scoreboard6DeltaX_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 272; case 80: return 272; case 75: return 240; case 70: return 240; case 60: return 240; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_VFE_STATE::Scoreboard 6 Delta Y */ #define GFX9_MEDIA_VFE_STATE_Scoreboard6DeltaY_bits 4 #define GFX8_MEDIA_VFE_STATE_Scoreboard6DeltaY_bits 4 #define GFX75_MEDIA_VFE_STATE_Scoreboard6DeltaY_bits 4 #define GFX7_MEDIA_VFE_STATE_Scoreboard6DeltaY_bits 4 #define GFX6_MEDIA_VFE_STATE_Scoreboard6DeltaY_bits 4 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_Scoreboard6DeltaY_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 4; case 80: return 4; case 75: return 4; case 70: return 4; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_MEDIA_VFE_STATE_Scoreboard6DeltaY_start 276 #define GFX8_MEDIA_VFE_STATE_Scoreboard6DeltaY_start 276 #define GFX75_MEDIA_VFE_STATE_Scoreboard6DeltaY_start 244 #define GFX7_MEDIA_VFE_STATE_Scoreboard6DeltaY_start 244 #define GFX6_MEDIA_VFE_STATE_Scoreboard6DeltaY_start 244 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_Scoreboard6DeltaY_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 276; case 80: return 276; case 75: return 244; case 70: return 244; case 60: return 244; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_VFE_STATE::Scoreboard 7 Delta X */ #define GFX9_MEDIA_VFE_STATE_Scoreboard7DeltaX_bits 4 #define GFX8_MEDIA_VFE_STATE_Scoreboard7DeltaX_bits 4 #define GFX75_MEDIA_VFE_STATE_Scoreboard7DeltaX_bits 4 #define GFX7_MEDIA_VFE_STATE_Scoreboard7DeltaX_bits 4 #define GFX6_MEDIA_VFE_STATE_Scoreboard7DeltaX_bits 4 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_Scoreboard7DeltaX_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 4; case 80: return 4; case 75: return 4; case 70: return 4; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_MEDIA_VFE_STATE_Scoreboard7DeltaX_start 280 #define GFX8_MEDIA_VFE_STATE_Scoreboard7DeltaX_start 280 #define GFX75_MEDIA_VFE_STATE_Scoreboard7DeltaX_start 248 #define GFX7_MEDIA_VFE_STATE_Scoreboard7DeltaX_start 248 #define GFX6_MEDIA_VFE_STATE_Scoreboard7DeltaX_start 248 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_Scoreboard7DeltaX_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 280; case 80: return 280; case 75: return 248; case 70: return 248; case 60: return 248; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_VFE_STATE::Scoreboard 7 Delta Y */ #define GFX9_MEDIA_VFE_STATE_Scoreboard7DeltaY_bits 4 #define GFX8_MEDIA_VFE_STATE_Scoreboard7DeltaY_bits 4 #define GFX75_MEDIA_VFE_STATE_Scoreboard7DeltaY_bits 4 #define GFX7_MEDIA_VFE_STATE_Scoreboard7DeltaY_bits 4 #define GFX6_MEDIA_VFE_STATE_Scoreboard7DeltaY_bits 4 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_Scoreboard7DeltaY_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 4; case 80: return 4; case 75: return 4; case 70: return 4; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_MEDIA_VFE_STATE_Scoreboard7DeltaY_start 284 #define GFX8_MEDIA_VFE_STATE_Scoreboard7DeltaY_start 284 #define GFX75_MEDIA_VFE_STATE_Scoreboard7DeltaY_start 252 #define GFX7_MEDIA_VFE_STATE_Scoreboard7DeltaY_start 252 #define GFX6_MEDIA_VFE_STATE_Scoreboard7DeltaY_start 252 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_Scoreboard7DeltaY_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 284; case 80: return 284; case 75: return 252; case 70: return 252; case 60: return 252; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_VFE_STATE::Scoreboard Enable */ #define GFX9_MEDIA_VFE_STATE_ScoreboardEnable_bits 1 #define GFX8_MEDIA_VFE_STATE_ScoreboardEnable_bits 1 #define GFX75_MEDIA_VFE_STATE_ScoreboardEnable_bits 1 #define GFX7_MEDIA_VFE_STATE_ScoreboardEnable_bits 1 #define GFX6_MEDIA_VFE_STATE_ScoreboardEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_ScoreboardEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_MEDIA_VFE_STATE_ScoreboardEnable_start 223 #define GFX8_MEDIA_VFE_STATE_ScoreboardEnable_start 223 #define GFX75_MEDIA_VFE_STATE_ScoreboardEnable_start 191 #define GFX7_MEDIA_VFE_STATE_ScoreboardEnable_start 191 #define GFX6_MEDIA_VFE_STATE_ScoreboardEnable_start 191 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_ScoreboardEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 223; case 80: return 223; case 75: return 191; case 70: return 191; case 60: return 191; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_VFE_STATE::Scoreboard Mask */ #define GFX9_MEDIA_VFE_STATE_ScoreboardMask_bits 8 #define GFX8_MEDIA_VFE_STATE_ScoreboardMask_bits 8 #define GFX75_MEDIA_VFE_STATE_ScoreboardMask_bits 8 #define GFX7_MEDIA_VFE_STATE_ScoreboardMask_bits 8 #define GFX6_MEDIA_VFE_STATE_ScoreboardMask_bits 8 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_ScoreboardMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_MEDIA_VFE_STATE_ScoreboardMask_start 192 #define GFX8_MEDIA_VFE_STATE_ScoreboardMask_start 192 #define GFX75_MEDIA_VFE_STATE_ScoreboardMask_start 160 #define GFX7_MEDIA_VFE_STATE_ScoreboardMask_start 160 #define GFX6_MEDIA_VFE_STATE_ScoreboardMask_start 160 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_ScoreboardMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 192; case 80: return 192; case 75: return 160; case 70: return 160; case 60: return 160; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_VFE_STATE::Scoreboard Type */ #define GFX9_MEDIA_VFE_STATE_ScoreboardType_bits 1 #define GFX8_MEDIA_VFE_STATE_ScoreboardType_bits 1 #define GFX75_MEDIA_VFE_STATE_ScoreboardType_bits 1 #define GFX7_MEDIA_VFE_STATE_ScoreboardType_bits 1 #define GFX6_MEDIA_VFE_STATE_ScoreboardType_bits 1 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_ScoreboardType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_MEDIA_VFE_STATE_ScoreboardType_start 222 #define GFX8_MEDIA_VFE_STATE_ScoreboardType_start 222 #define GFX75_MEDIA_VFE_STATE_ScoreboardType_start 190 #define GFX7_MEDIA_VFE_STATE_ScoreboardType_start 190 #define GFX6_MEDIA_VFE_STATE_ScoreboardType_start 190 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_ScoreboardType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 222; case 80: return 222; case 75: return 190; case 70: return 190; case 60: return 190; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_VFE_STATE::Scratch Space Base Pointer */ #define GFX12_MEDIA_VFE_STATE_ScratchSpaceBasePointer_bits 38 #define GFX11_MEDIA_VFE_STATE_ScratchSpaceBasePointer_bits 38 #define GFX9_MEDIA_VFE_STATE_ScratchSpaceBasePointer_bits 38 #define GFX8_MEDIA_VFE_STATE_ScratchSpaceBasePointer_bits 38 #define GFX75_MEDIA_VFE_STATE_ScratchSpaceBasePointer_bits 22 #define GFX7_MEDIA_VFE_STATE_ScratchSpaceBasePointer_bits 22 #define GFX6_MEDIA_VFE_STATE_ScratchSpaceBasePointer_bits 22 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_ScratchSpaceBasePointer_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 38; case 110: return 38; case 90: return 38; case 80: return 38; case 75: return 22; case 70: return 22; case 60: return 22; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_VFE_STATE_ScratchSpaceBasePointer_start 42 #define GFX11_MEDIA_VFE_STATE_ScratchSpaceBasePointer_start 42 #define GFX9_MEDIA_VFE_STATE_ScratchSpaceBasePointer_start 42 #define GFX8_MEDIA_VFE_STATE_ScratchSpaceBasePointer_start 42 #define GFX75_MEDIA_VFE_STATE_ScratchSpaceBasePointer_start 42 #define GFX7_MEDIA_VFE_STATE_ScratchSpaceBasePointer_start 42 #define GFX6_MEDIA_VFE_STATE_ScratchSpaceBasePointer_start 42 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_ScratchSpaceBasePointer_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 42; case 110: return 42; case 90: return 42; case 80: return 42; case 75: return 42; case 70: return 42; case 60: return 42; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_VFE_STATE::Slice Disable */ #define GFX9_MEDIA_VFE_STATE_SliceDisable_bits 2 #define GFX8_MEDIA_VFE_STATE_SliceDisable_bits 2 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_SliceDisable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 2; case 80: return 2; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_MEDIA_VFE_STATE_SliceDisable_start 128 #define GFX8_MEDIA_VFE_STATE_SliceDisable_start 128 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_SliceDisable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 128; case 80: return 128; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_VFE_STATE::Stack Size */ #define GFX12_MEDIA_VFE_STATE_StackSize_bits 4 #define GFX11_MEDIA_VFE_STATE_StackSize_bits 4 #define GFX9_MEDIA_VFE_STATE_StackSize_bits 4 #define GFX8_MEDIA_VFE_STATE_StackSize_bits 4 #define GFX75_MEDIA_VFE_STATE_StackSize_bits 4 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_StackSize_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 4; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_VFE_STATE_StackSize_start 36 #define GFX11_MEDIA_VFE_STATE_StackSize_start 36 #define GFX9_MEDIA_VFE_STATE_StackSize_start 36 #define GFX8_MEDIA_VFE_STATE_StackSize_start 36 #define GFX75_MEDIA_VFE_STATE_StackSize_start 36 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_StackSize_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 36; case 110: return 36; case 90: return 36; case 80: return 36; case 75: return 36; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_VFE_STATE::SubOpcode */ #define GFX12_MEDIA_VFE_STATE_SubOpcode_bits 8 #define GFX11_MEDIA_VFE_STATE_SubOpcode_bits 8 #define GFX9_MEDIA_VFE_STATE_SubOpcode_bits 8 #define GFX8_MEDIA_VFE_STATE_SubOpcode_bits 8 #define GFX75_MEDIA_VFE_STATE_SubOpcode_bits 8 #define GFX7_MEDIA_VFE_STATE_SubOpcode_bits 8 #define GFX6_MEDIA_VFE_STATE_SubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_SubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_VFE_STATE_SubOpcode_start 16 #define GFX11_MEDIA_VFE_STATE_SubOpcode_start 16 #define GFX9_MEDIA_VFE_STATE_SubOpcode_start 16 #define GFX8_MEDIA_VFE_STATE_SubOpcode_start 16 #define GFX75_MEDIA_VFE_STATE_SubOpcode_start 16 #define GFX7_MEDIA_VFE_STATE_SubOpcode_start 16 #define GFX6_MEDIA_VFE_STATE_SubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_SubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 16; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEDIA_VFE_STATE::URB Entry Allocation Size */ #define GFX12_MEDIA_VFE_STATE_URBEntryAllocationSize_bits 16 #define GFX11_MEDIA_VFE_STATE_URBEntryAllocationSize_bits 16 #define GFX9_MEDIA_VFE_STATE_URBEntryAllocationSize_bits 16 #define GFX8_MEDIA_VFE_STATE_URBEntryAllocationSize_bits 16 #define GFX75_MEDIA_VFE_STATE_URBEntryAllocationSize_bits 16 #define GFX7_MEDIA_VFE_STATE_URBEntryAllocationSize_bits 16 #define GFX6_MEDIA_VFE_STATE_URBEntryAllocationSize_bits 16 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_URBEntryAllocationSize_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 16; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MEDIA_VFE_STATE_URBEntryAllocationSize_start 176 #define GFX11_MEDIA_VFE_STATE_URBEntryAllocationSize_start 176 #define GFX9_MEDIA_VFE_STATE_URBEntryAllocationSize_start 176 #define GFX8_MEDIA_VFE_STATE_URBEntryAllocationSize_start 176 #define GFX75_MEDIA_VFE_STATE_URBEntryAllocationSize_start 144 #define GFX7_MEDIA_VFE_STATE_URBEntryAllocationSize_start 144 #define GFX6_MEDIA_VFE_STATE_URBEntryAllocationSize_start 144 static inline uint32_t ATTRIBUTE_PURE MEDIA_VFE_STATE_URBEntryAllocationSize_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 176; case 110: return 176; case 90: return 176; case 80: return 176; case 75: return 144; case 70: return 144; case 60: return 144; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEMORYADDRESSATTRIBUTES */ #define GFX125_MEMORYADDRESSATTRIBUTES_length 1 #define GFX12_MEMORYADDRESSATTRIBUTES_length 1 #define GFX11_MEMORYADDRESSATTRIBUTES_length 1 #define GFX9_MEMORYADDRESSATTRIBUTES_length 1 #define GFX8_MEMORYADDRESSATTRIBUTES_length 1 static inline uint32_t ATTRIBUTE_PURE MEMORYADDRESSATTRIBUTES_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEMORYADDRESSATTRIBUTES::Age for QUADLRU */ #define GFX8_MEMORYADDRESSATTRIBUTES_AgeforQUADLRU_bits 2 static inline uint32_t ATTRIBUTE_PURE MEMORYADDRESSATTRIBUTES_AgeforQUADLRU_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 2; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX8_MEMORYADDRESSATTRIBUTES_AgeforQUADLRU_start 0 static inline uint32_t ATTRIBUTE_PURE MEMORYADDRESSATTRIBUTES_AgeforQUADLRU_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEMORYADDRESSATTRIBUTES::Arbitration Priority Control */ #define GFX125_MEMORYADDRESSATTRIBUTES_ArbitrationPriorityControl_bits 2 #define GFX12_MEMORYADDRESSATTRIBUTES_ArbitrationPriorityControl_bits 2 #define GFX11_MEMORYADDRESSATTRIBUTES_ArbitrationPriorityControl_bits 2 #define GFX9_MEMORYADDRESSATTRIBUTES_ArbitrationPriorityControl_bits 2 #define GFX8_MEMORYADDRESSATTRIBUTES_ArbitrationPriorityControl_bits 2 static inline uint32_t ATTRIBUTE_PURE MEMORYADDRESSATTRIBUTES_ArbitrationPriorityControl_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MEMORYADDRESSATTRIBUTES_ArbitrationPriorityControl_start 7 #define GFX12_MEMORYADDRESSATTRIBUTES_ArbitrationPriorityControl_start 7 #define GFX11_MEMORYADDRESSATTRIBUTES_ArbitrationPriorityControl_start 7 #define GFX9_MEMORYADDRESSATTRIBUTES_ArbitrationPriorityControl_start 7 #define GFX8_MEMORYADDRESSATTRIBUTES_ArbitrationPriorityControl_start 7 static inline uint32_t ATTRIBUTE_PURE MEMORYADDRESSATTRIBUTES_ArbitrationPriorityControl_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 7; case 120: return 7; case 110: return 7; case 90: return 7; case 80: return 7; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEMORYADDRESSATTRIBUTES::MOCS */ #define GFX125_MEMORYADDRESSATTRIBUTES_MOCS_bits 6 #define GFX12_MEMORYADDRESSATTRIBUTES_MOCS_bits 6 #define GFX11_MEMORYADDRESSATTRIBUTES_MOCS_bits 6 #define GFX9_MEMORYADDRESSATTRIBUTES_MOCS_bits 6 static inline uint32_t ATTRIBUTE_PURE MEMORYADDRESSATTRIBUTES_MOCS_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MEMORYADDRESSATTRIBUTES_MOCS_start 1 #define GFX12_MEMORYADDRESSATTRIBUTES_MOCS_start 1 #define GFX11_MEMORYADDRESSATTRIBUTES_MOCS_start 1 #define GFX9_MEMORYADDRESSATTRIBUTES_MOCS_start 1 static inline uint32_t ATTRIBUTE_PURE MEMORYADDRESSATTRIBUTES_MOCS_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEMORYADDRESSATTRIBUTES::Memory Compression Enable */ #define GFX125_MEMORYADDRESSATTRIBUTES_MemoryCompressionEnable_bits 1 #define GFX12_MEMORYADDRESSATTRIBUTES_MemoryCompressionEnable_bits 1 #define GFX11_MEMORYADDRESSATTRIBUTES_MemoryCompressionEnable_bits 1 #define GFX9_MEMORYADDRESSATTRIBUTES_MemoryCompressionEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE MEMORYADDRESSATTRIBUTES_MemoryCompressionEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MEMORYADDRESSATTRIBUTES_MemoryCompressionEnable_start 9 #define GFX12_MEMORYADDRESSATTRIBUTES_MemoryCompressionEnable_start 9 #define GFX11_MEMORYADDRESSATTRIBUTES_MemoryCompressionEnable_start 9 #define GFX9_MEMORYADDRESSATTRIBUTES_MemoryCompressionEnable_start 9 static inline uint32_t ATTRIBUTE_PURE MEMORYADDRESSATTRIBUTES_MemoryCompressionEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 9; case 120: return 9; case 110: return 9; case 90: return 9; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEMORYADDRESSATTRIBUTES::Memory Compression Mode */ #define GFX125_MEMORYADDRESSATTRIBUTES_MemoryCompressionMode_bits 1 #define GFX12_MEMORYADDRESSATTRIBUTES_MemoryCompressionMode_bits 1 #define GFX11_MEMORYADDRESSATTRIBUTES_MemoryCompressionMode_bits 1 static inline uint32_t ATTRIBUTE_PURE MEMORYADDRESSATTRIBUTES_MemoryCompressionMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MEMORYADDRESSATTRIBUTES_MemoryCompressionMode_start 10 #define GFX12_MEMORYADDRESSATTRIBUTES_MemoryCompressionMode_start 10 #define GFX11_MEMORYADDRESSATTRIBUTES_MemoryCompressionMode_start 10 static inline uint32_t ATTRIBUTE_PURE MEMORYADDRESSATTRIBUTES_MemoryCompressionMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 10; case 120: return 10; case 110: return 10; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEMORYADDRESSATTRIBUTES::Row Store Scratch Buffer Cache Select */ #define GFX125_MEMORYADDRESSATTRIBUTES_RowStoreScratchBufferCacheSelect_bits 1 #define GFX12_MEMORYADDRESSATTRIBUTES_RowStoreScratchBufferCacheSelect_bits 1 #define GFX11_MEMORYADDRESSATTRIBUTES_RowStoreScratchBufferCacheSelect_bits 1 #define GFX9_MEMORYADDRESSATTRIBUTES_RowStoreScratchBufferCacheSelect_bits 1 static inline uint32_t ATTRIBUTE_PURE MEMORYADDRESSATTRIBUTES_RowStoreScratchBufferCacheSelect_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MEMORYADDRESSATTRIBUTES_RowStoreScratchBufferCacheSelect_start 12 #define GFX12_MEMORYADDRESSATTRIBUTES_RowStoreScratchBufferCacheSelect_start 12 #define GFX11_MEMORYADDRESSATTRIBUTES_RowStoreScratchBufferCacheSelect_start 12 #define GFX9_MEMORYADDRESSATTRIBUTES_RowStoreScratchBufferCacheSelect_start 12 static inline uint32_t ATTRIBUTE_PURE MEMORYADDRESSATTRIBUTES_RowStoreScratchBufferCacheSelect_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 12; case 120: return 12; case 110: return 12; case 90: return 12; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEMORYADDRESSATTRIBUTES::Target Cache */ #define GFX8_MEMORYADDRESSATTRIBUTES_TargetCache_bits 2 static inline uint32_t ATTRIBUTE_PURE MEMORYADDRESSATTRIBUTES_TargetCache_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 2; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX8_MEMORYADDRESSATTRIBUTES_TargetCache_start 3 static inline uint32_t ATTRIBUTE_PURE MEMORYADDRESSATTRIBUTES_TargetCache_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 3; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEMORYADDRESSATTRIBUTES::Tiled Resource Mode */ #define GFX125_MEMORYADDRESSATTRIBUTES_TiledResourceMode_bits 2 #define GFX12_MEMORYADDRESSATTRIBUTES_TiledResourceMode_bits 2 #define GFX11_MEMORYADDRESSATTRIBUTES_TiledResourceMode_bits 2 #define GFX9_MEMORYADDRESSATTRIBUTES_TiledResourceMode_bits 2 static inline uint32_t ATTRIBUTE_PURE MEMORYADDRESSATTRIBUTES_TiledResourceMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MEMORYADDRESSATTRIBUTES_TiledResourceMode_start 13 #define GFX12_MEMORYADDRESSATTRIBUTES_TiledResourceMode_start 13 #define GFX11_MEMORYADDRESSATTRIBUTES_TiledResourceMode_start 13 #define GFX9_MEMORYADDRESSATTRIBUTES_TiledResourceMode_start 13 static inline uint32_t ATTRIBUTE_PURE MEMORYADDRESSATTRIBUTES_TiledResourceMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 13; case 120: return 13; case 110: return 13; case 90: return 13; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEMORY_OBJECT_CONTROL_STATE */ #define GFX8_MEMORY_OBJECT_CONTROL_STATE_length 1 #define GFX75_MEMORY_OBJECT_CONTROL_STATE_length 1 #define GFX7_MEMORY_OBJECT_CONTROL_STATE_length 1 #define GFX6_MEMORY_OBJECT_CONTROL_STATE_length 1 #define GFX5_MEMORY_OBJECT_CONTROL_STATE_length 1 static inline uint32_t ATTRIBUTE_PURE MEMORY_OBJECT_CONTROL_STATE_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 1; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEMORY_OBJECT_CONTROL_STATE::Age for QUADLRU */ #define GFX8_MEMORY_OBJECT_CONTROL_STATE_AgeforQUADLRU_bits 2 static inline uint32_t ATTRIBUTE_PURE MEMORY_OBJECT_CONTROL_STATE_AgeforQUADLRU_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 2; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX8_MEMORY_OBJECT_CONTROL_STATE_AgeforQUADLRU_start 0 static inline uint32_t ATTRIBUTE_PURE MEMORY_OBJECT_CONTROL_STATE_AgeforQUADLRU_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEMORY_OBJECT_CONTROL_STATE::Cacheability Control */ #define GFX6_MEMORY_OBJECT_CONTROL_STATE_CacheabilityControl_bits 2 #define GFX5_MEMORY_OBJECT_CONTROL_STATE_CacheabilityControl_bits 2 static inline uint32_t ATTRIBUTE_PURE MEMORY_OBJECT_CONTROL_STATE_CacheabilityControl_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 2; case 50: return 2; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_MEMORY_OBJECT_CONTROL_STATE_CacheabilityControl_start 0 #define GFX5_MEMORY_OBJECT_CONTROL_STATE_CacheabilityControl_start 0 static inline uint32_t ATTRIBUTE_PURE MEMORY_OBJECT_CONTROL_STATE_CacheabilityControl_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEMORY_OBJECT_CONTROL_STATE::Encrypted Data */ #define GFX5_MEMORY_OBJECT_CONTROL_STATE_EncryptedData_bits 1 static inline uint32_t ATTRIBUTE_PURE MEMORY_OBJECT_CONTROL_STATE_EncryptedData_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX5_MEMORY_OBJECT_CONTROL_STATE_EncryptedData_start 3 static inline uint32_t ATTRIBUTE_PURE MEMORY_OBJECT_CONTROL_STATE_EncryptedData_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 3; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEMORY_OBJECT_CONTROL_STATE::Graphics Data Type (GFDT) */ #define GFX7_MEMORY_OBJECT_CONTROL_STATE_GraphicsDataTypeGFDT_bits 1 #define GFX6_MEMORY_OBJECT_CONTROL_STATE_GraphicsDataTypeGFDT_bits 1 #define GFX5_MEMORY_OBJECT_CONTROL_STATE_GraphicsDataTypeGFDT_bits 1 static inline uint32_t ATTRIBUTE_PURE MEMORY_OBJECT_CONTROL_STATE_GraphicsDataTypeGFDT_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 1; case 60: return 1; case 50: return 1; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX7_MEMORY_OBJECT_CONTROL_STATE_GraphicsDataTypeGFDT_start 2 #define GFX6_MEMORY_OBJECT_CONTROL_STATE_GraphicsDataTypeGFDT_start 2 #define GFX5_MEMORY_OBJECT_CONTROL_STATE_GraphicsDataTypeGFDT_start 2 static inline uint32_t ATTRIBUTE_PURE MEMORY_OBJECT_CONTROL_STATE_GraphicsDataTypeGFDT_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 2; case 60: return 2; case 50: return 2; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEMORY_OBJECT_CONTROL_STATE::L3 Cacheability Control (L3CC) */ #define GFX75_MEMORY_OBJECT_CONTROL_STATE_L3CacheabilityControlL3CC_bits 1 #define GFX7_MEMORY_OBJECT_CONTROL_STATE_L3CacheabilityControlL3CC_bits 1 static inline uint32_t ATTRIBUTE_PURE MEMORY_OBJECT_CONTROL_STATE_L3CacheabilityControlL3CC_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_MEMORY_OBJECT_CONTROL_STATE_L3CacheabilityControlL3CC_start 0 #define GFX7_MEMORY_OBJECT_CONTROL_STATE_L3CacheabilityControlL3CC_start 0 static inline uint32_t ATTRIBUTE_PURE MEMORY_OBJECT_CONTROL_STATE_L3CacheabilityControlL3CC_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEMORY_OBJECT_CONTROL_STATE::LLC Cacheability Control (LLCCC) */ #define GFX7_MEMORY_OBJECT_CONTROL_STATE_LLCCacheabilityControlLLCCC_bits 1 static inline uint32_t ATTRIBUTE_PURE MEMORY_OBJECT_CONTROL_STATE_LLCCacheabilityControlLLCCC_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX7_MEMORY_OBJECT_CONTROL_STATE_LLCCacheabilityControlLLCCC_start 1 static inline uint32_t ATTRIBUTE_PURE MEMORY_OBJECT_CONTROL_STATE_LLCCacheabilityControlLLCCC_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEMORY_OBJECT_CONTROL_STATE::LLC/eLLC Cacheability Control (LLCCC) */ #define GFX75_MEMORY_OBJECT_CONTROL_STATE_LLCeLLCCacheabilityControlLLCCC_bits 2 static inline uint32_t ATTRIBUTE_PURE MEMORY_OBJECT_CONTROL_STATE_LLCeLLCCacheabilityControlLLCCC_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 2; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_MEMORY_OBJECT_CONTROL_STATE_LLCeLLCCacheabilityControlLLCCC_start 1 static inline uint32_t ATTRIBUTE_PURE MEMORY_OBJECT_CONTROL_STATE_LLCeLLCCacheabilityControlLLCCC_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEMORY_OBJECT_CONTROL_STATE::Memory Type:LLC/eLLC Cacheability Control */ #define GFX8_MEMORY_OBJECT_CONTROL_STATE_MemoryTypeLLCeLLCCacheabilityControl_bits 2 static inline uint32_t ATTRIBUTE_PURE MEMORY_OBJECT_CONTROL_STATE_MemoryTypeLLCeLLCCacheabilityControl_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 2; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX8_MEMORY_OBJECT_CONTROL_STATE_MemoryTypeLLCeLLCCacheabilityControl_start 5 static inline uint32_t ATTRIBUTE_PURE MEMORY_OBJECT_CONTROL_STATE_MemoryTypeLLCeLLCCacheabilityControl_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 5; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MEMORY_OBJECT_CONTROL_STATE::Target Cache */ #define GFX8_MEMORY_OBJECT_CONTROL_STATE_TargetCache_bits 2 static inline uint32_t ATTRIBUTE_PURE MEMORY_OBJECT_CONTROL_STATE_TargetCache_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 2; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX8_MEMORY_OBJECT_CONTROL_STATE_TargetCache_start 3 static inline uint32_t ATTRIBUTE_PURE MEMORY_OBJECT_CONTROL_STATE_TargetCache_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 3; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION */ #define GFX125_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_length 2 #define GFX12_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_length 2 #define GFX11_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_length 2 #define GFX9_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_length 2 #define GFX8_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_length 2 #define GFX75_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_length 2 #define GFX7_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_length 2 static inline uint32_t ATTRIBUTE_PURE MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION::First MB Bit Offset */ #define GFX125_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_FirstMBBitOffset_bits 3 #define GFX12_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_FirstMBBitOffset_bits 3 #define GFX11_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_FirstMBBitOffset_bits 3 #define GFX9_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_FirstMBBitOffset_bits 3 #define GFX8_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_FirstMBBitOffset_bits 3 #define GFX75_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_FirstMBBitOffset_bits 3 #define GFX7_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_FirstMBBitOffset_bits 3 static inline uint32_t ATTRIBUTE_PURE MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_FirstMBBitOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_FirstMBBitOffset_start 0 #define GFX12_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_FirstMBBitOffset_start 0 #define GFX11_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_FirstMBBitOffset_start 0 #define GFX9_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_FirstMBBitOffset_start 0 #define GFX8_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_FirstMBBitOffset_start 0 #define GFX75_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_FirstMBBitOffset_start 0 #define GFX7_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_FirstMBBitOffset_start 0 static inline uint32_t ATTRIBUTE_PURE MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_FirstMBBitOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION::Last MB */ #define GFX125_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_LastMB_bits 1 #define GFX12_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_LastMB_bits 1 #define GFX11_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_LastMB_bits 1 #define GFX9_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_LastMB_bits 1 #define GFX8_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_LastMB_bits 1 #define GFX75_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_LastMB_bits 1 #define GFX7_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_LastMB_bits 1 static inline uint32_t ATTRIBUTE_PURE MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_LastMB_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_LastMB_start 3 #define GFX12_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_LastMB_start 3 #define GFX11_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_LastMB_start 3 #define GFX9_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_LastMB_start 3 #define GFX8_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_LastMB_start 3 #define GFX75_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_LastMB_start 3 #define GFX7_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_LastMB_start 3 static inline uint32_t ATTRIBUTE_PURE MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_LastMB_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION::Last Pic Slice */ #define GFX125_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_LastPicSlice_bits 1 #define GFX12_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_LastPicSlice_bits 1 #define GFX11_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_LastPicSlice_bits 1 #define GFX9_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_LastPicSlice_bits 1 #define GFX8_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_LastPicSlice_bits 1 #define GFX75_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_LastPicSlice_bits 1 #define GFX7_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_LastPicSlice_bits 1 static inline uint32_t ATTRIBUTE_PURE MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_LastPicSlice_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_LastPicSlice_start 5 #define GFX12_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_LastPicSlice_start 5 #define GFX11_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_LastPicSlice_start 5 #define GFX9_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_LastPicSlice_start 5 #define GFX8_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_LastPicSlice_start 5 #define GFX75_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_LastPicSlice_start 5 #define GFX7_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_LastPicSlice_start 5 static inline uint32_t ATTRIBUTE_PURE MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_LastPicSlice_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 5; case 110: return 5; case 90: return 5; case 80: return 5; case 75: return 5; case 70: return 5; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION::MB Count */ #define GFX125_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_MBCount_bits 8 #define GFX12_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_MBCount_bits 8 #define GFX11_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_MBCount_bits 8 #define GFX9_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_MBCount_bits 8 #define GFX8_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_MBCount_bits 8 #define GFX75_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_MBCount_bits 8 #define GFX7_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_MBCount_bits 7 static inline uint32_t ATTRIBUTE_PURE MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_MBCount_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 7; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_MBCount_start 8 #define GFX12_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_MBCount_start 8 #define GFX11_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_MBCount_start 8 #define GFX9_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_MBCount_start 8 #define GFX8_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_MBCount_start 8 #define GFX75_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_MBCount_start 8 #define GFX7_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_MBCount_start 8 static inline uint32_t ATTRIBUTE_PURE MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_MBCount_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION::Next Slice Horizontal Position */ #define GFX125_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_NextSliceHorizontalPosition_bits 8 #define GFX12_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_NextSliceHorizontalPosition_bits 8 #define GFX11_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_NextSliceHorizontalPosition_bits 8 #define GFX9_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_NextSliceHorizontalPosition_bits 8 #define GFX8_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_NextSliceHorizontalPosition_bits 8 #define GFX75_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_NextSliceHorizontalPosition_bits 8 static inline uint32_t ATTRIBUTE_PURE MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_NextSliceHorizontalPosition_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_NextSliceHorizontalPosition_start 32 #define GFX12_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_NextSliceHorizontalPosition_start 32 #define GFX11_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_NextSliceHorizontalPosition_start 32 #define GFX9_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_NextSliceHorizontalPosition_start 32 #define GFX8_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_NextSliceHorizontalPosition_start 32 #define GFX75_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_NextSliceHorizontalPosition_start 32 static inline uint32_t ATTRIBUTE_PURE MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_NextSliceHorizontalPosition_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION::Next Slice Vertical Position */ #define GFX125_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_NextSliceVerticalPosition_bits 9 #define GFX12_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_NextSliceVerticalPosition_bits 9 #define GFX11_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_NextSliceVerticalPosition_bits 9 #define GFX9_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_NextSliceVerticalPosition_bits 9 #define GFX8_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_NextSliceVerticalPosition_bits 9 #define GFX75_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_NextSliceVerticalPosition_bits 9 static inline uint32_t ATTRIBUTE_PURE MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_NextSliceVerticalPosition_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 9; case 120: return 9; case 110: return 9; case 90: return 9; case 80: return 9; case 75: return 9; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_NextSliceVerticalPosition_start 40 #define GFX12_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_NextSliceVerticalPosition_start 40 #define GFX11_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_NextSliceVerticalPosition_start 40 #define GFX9_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_NextSliceVerticalPosition_start 40 #define GFX8_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_NextSliceVerticalPosition_start 40 #define GFX75_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_NextSliceVerticalPosition_start 40 static inline uint32_t ATTRIBUTE_PURE MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_NextSliceVerticalPosition_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 40; case 120: return 40; case 110: return 40; case 90: return 40; case 80: return 40; case 75: return 40; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION::Quantizer Scale Code */ #define GFX125_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_QuantizerScaleCode_bits 5 #define GFX12_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_QuantizerScaleCode_bits 5 #define GFX11_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_QuantizerScaleCode_bits 5 #define GFX9_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_QuantizerScaleCode_bits 5 #define GFX8_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_QuantizerScaleCode_bits 5 #define GFX75_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_QuantizerScaleCode_bits 5 #define GFX7_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_QuantizerScaleCode_bits 5 static inline uint32_t ATTRIBUTE_PURE MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_QuantizerScaleCode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 5; case 110: return 5; case 90: return 5; case 80: return 5; case 75: return 5; case 70: return 5; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_QuantizerScaleCode_start 56 #define GFX12_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_QuantizerScaleCode_start 56 #define GFX11_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_QuantizerScaleCode_start 56 #define GFX9_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_QuantizerScaleCode_start 56 #define GFX8_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_QuantizerScaleCode_start 56 #define GFX75_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_QuantizerScaleCode_start 56 #define GFX7_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_QuantizerScaleCode_start 56 static inline uint32_t ATTRIBUTE_PURE MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_QuantizerScaleCode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 56; case 120: return 56; case 110: return 56; case 90: return 56; case 80: return 56; case 75: return 56; case 70: return 56; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION::Slice Concealment Override */ #define GFX125_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_SliceConcealmentOverride_bits 1 #define GFX12_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_SliceConcealmentOverride_bits 1 #define GFX11_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_SliceConcealmentOverride_bits 1 #define GFX9_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_SliceConcealmentOverride_bits 1 #define GFX8_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_SliceConcealmentOverride_bits 1 #define GFX75_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_SliceConcealmentOverride_bits 1 static inline uint32_t ATTRIBUTE_PURE MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_SliceConcealmentOverride_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_SliceConcealmentOverride_start 7 #define GFX12_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_SliceConcealmentOverride_start 7 #define GFX11_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_SliceConcealmentOverride_start 7 #define GFX9_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_SliceConcealmentOverride_start 7 #define GFX8_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_SliceConcealmentOverride_start 7 #define GFX75_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_SliceConcealmentOverride_start 7 static inline uint32_t ATTRIBUTE_PURE MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_SliceConcealmentOverride_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 7; case 120: return 7; case 110: return 7; case 90: return 7; case 80: return 7; case 75: return 7; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION::Slice Concealment Type */ #define GFX125_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_SliceConcealmentType_bits 1 #define GFX12_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_SliceConcealmentType_bits 1 #define GFX11_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_SliceConcealmentType_bits 1 #define GFX9_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_SliceConcealmentType_bits 1 #define GFX8_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_SliceConcealmentType_bits 1 #define GFX75_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_SliceConcealmentType_bits 1 static inline uint32_t ATTRIBUTE_PURE MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_SliceConcealmentType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_SliceConcealmentType_start 6 #define GFX12_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_SliceConcealmentType_start 6 #define GFX11_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_SliceConcealmentType_start 6 #define GFX9_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_SliceConcealmentType_start 6 #define GFX8_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_SliceConcealmentType_start 6 #define GFX75_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_SliceConcealmentType_start 6 static inline uint32_t ATTRIBUTE_PURE MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_SliceConcealmentType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION::Slice Horizontal Position */ #define GFX125_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_SliceHorizontalPosition_bits 8 #define GFX12_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_SliceHorizontalPosition_bits 8 #define GFX11_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_SliceHorizontalPosition_bits 8 #define GFX9_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_SliceHorizontalPosition_bits 8 #define GFX8_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_SliceHorizontalPosition_bits 8 #define GFX75_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_SliceHorizontalPosition_bits 8 #define GFX7_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_SliceHorizontalPosition_bits 7 static inline uint32_t ATTRIBUTE_PURE MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_SliceHorizontalPosition_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 7; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_SliceHorizontalPosition_start 24 #define GFX12_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_SliceHorizontalPosition_start 24 #define GFX11_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_SliceHorizontalPosition_start 24 #define GFX9_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_SliceHorizontalPosition_start 24 #define GFX8_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_SliceHorizontalPosition_start 24 #define GFX75_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_SliceHorizontalPosition_start 24 #define GFX7_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_SliceHorizontalPosition_start 24 static inline uint32_t ATTRIBUTE_PURE MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_SliceHorizontalPosition_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION::Slice Vertical Position */ #define GFX125_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_SliceVerticalPosition_bits 8 #define GFX12_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_SliceVerticalPosition_bits 8 #define GFX11_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_SliceVerticalPosition_bits 8 #define GFX9_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_SliceVerticalPosition_bits 8 #define GFX8_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_SliceVerticalPosition_bits 8 #define GFX75_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_SliceVerticalPosition_bits 8 #define GFX7_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_SliceVerticalPosition_bits 7 static inline uint32_t ATTRIBUTE_PURE MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_SliceVerticalPosition_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 7; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_SliceVerticalPosition_start 16 #define GFX12_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_SliceVerticalPosition_start 16 #define GFX11_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_SliceVerticalPosition_start 16 #define GFX9_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_SliceVerticalPosition_start 16 #define GFX8_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_SliceVerticalPosition_start 16 #define GFX75_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_SliceVerticalPosition_start 16 #define GFX7_MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_SliceVerticalPosition_start 16 static inline uint32_t ATTRIBUTE_PURE MFD_MPEG2_BSD_OBJECT_INLINE_DATA_DESCRIPTION_SliceVerticalPosition_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_ARB_CHECK */ #define GFX125_MI_ARB_CHECK_length 1 #define GFX12_MI_ARB_CHECK_length 1 #define GFX11_MI_ARB_CHECK_length 1 #define GFX9_MI_ARB_CHECK_length 1 #define GFX8_MI_ARB_CHECK_length 1 #define GFX75_MI_ARB_CHECK_length 1 #define GFX7_MI_ARB_CHECK_length 1 #define GFX6_MI_ARB_CHECK_length 1 static inline uint32_t ATTRIBUTE_PURE MI_ARB_CHECK_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_ARB_CHECK::Command Type */ #define GFX125_MI_ARB_CHECK_CommandType_bits 3 #define GFX12_MI_ARB_CHECK_CommandType_bits 3 #define GFX11_MI_ARB_CHECK_CommandType_bits 3 #define GFX9_MI_ARB_CHECK_CommandType_bits 3 #define GFX8_MI_ARB_CHECK_CommandType_bits 3 #define GFX75_MI_ARB_CHECK_CommandType_bits 3 #define GFX7_MI_ARB_CHECK_CommandType_bits 3 #define GFX6_MI_ARB_CHECK_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE MI_ARB_CHECK_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_ARB_CHECK_CommandType_start 29 #define GFX12_MI_ARB_CHECK_CommandType_start 29 #define GFX11_MI_ARB_CHECK_CommandType_start 29 #define GFX9_MI_ARB_CHECK_CommandType_start 29 #define GFX8_MI_ARB_CHECK_CommandType_start 29 #define GFX75_MI_ARB_CHECK_CommandType_start 29 #define GFX7_MI_ARB_CHECK_CommandType_start 29 #define GFX6_MI_ARB_CHECK_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE MI_ARB_CHECK_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 29; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_ARB_CHECK::MI Command Opcode */ #define GFX125_MI_ARB_CHECK_MICommandOpcode_bits 6 #define GFX12_MI_ARB_CHECK_MICommandOpcode_bits 6 #define GFX11_MI_ARB_CHECK_MICommandOpcode_bits 6 #define GFX9_MI_ARB_CHECK_MICommandOpcode_bits 6 #define GFX8_MI_ARB_CHECK_MICommandOpcode_bits 6 #define GFX75_MI_ARB_CHECK_MICommandOpcode_bits 6 #define GFX7_MI_ARB_CHECK_MICommandOpcode_bits 6 #define GFX6_MI_ARB_CHECK_MICommandOpcode_bits 6 static inline uint32_t ATTRIBUTE_PURE MI_ARB_CHECK_MICommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 6; case 60: return 6; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_ARB_CHECK_MICommandOpcode_start 23 #define GFX12_MI_ARB_CHECK_MICommandOpcode_start 23 #define GFX11_MI_ARB_CHECK_MICommandOpcode_start 23 #define GFX9_MI_ARB_CHECK_MICommandOpcode_start 23 #define GFX8_MI_ARB_CHECK_MICommandOpcode_start 23 #define GFX75_MI_ARB_CHECK_MICommandOpcode_start 23 #define GFX7_MI_ARB_CHECK_MICommandOpcode_start 23 #define GFX6_MI_ARB_CHECK_MICommandOpcode_start 23 static inline uint32_t ATTRIBUTE_PURE MI_ARB_CHECK_MICommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 23; case 120: return 23; case 110: return 23; case 90: return 23; case 80: return 23; case 75: return 23; case 70: return 23; case 60: return 23; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_ARB_ON_OFF */ #define GFX125_MI_ARB_ON_OFF_length 1 #define GFX12_MI_ARB_ON_OFF_length 1 #define GFX11_MI_ARB_ON_OFF_length 1 #define GFX9_MI_ARB_ON_OFF_length 1 #define GFX8_MI_ARB_ON_OFF_length 1 #define GFX75_MI_ARB_ON_OFF_length 1 #define GFX7_MI_ARB_ON_OFF_length 1 #define GFX6_MI_ARB_ON_OFF_length 1 static inline uint32_t ATTRIBUTE_PURE MI_ARB_ON_OFF_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_ARB_ON_OFF::Allow Lite Restore */ #define GFX125_MI_ARB_ON_OFF_AllowLiteRestore_bits 1 #define GFX12_MI_ARB_ON_OFF_AllowLiteRestore_bits 1 #define GFX11_MI_ARB_ON_OFF_AllowLiteRestore_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_ARB_ON_OFF_AllowLiteRestore_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_ARB_ON_OFF_AllowLiteRestore_start 1 #define GFX12_MI_ARB_ON_OFF_AllowLiteRestore_start 1 #define GFX11_MI_ARB_ON_OFF_AllowLiteRestore_start 1 static inline uint32_t ATTRIBUTE_PURE MI_ARB_ON_OFF_AllowLiteRestore_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_ARB_ON_OFF::Arbitration Enable */ #define GFX125_MI_ARB_ON_OFF_ArbitrationEnable_bits 1 #define GFX12_MI_ARB_ON_OFF_ArbitrationEnable_bits 1 #define GFX11_MI_ARB_ON_OFF_ArbitrationEnable_bits 1 #define GFX9_MI_ARB_ON_OFF_ArbitrationEnable_bits 1 #define GFX8_MI_ARB_ON_OFF_ArbitrationEnable_bits 1 #define GFX75_MI_ARB_ON_OFF_ArbitrationEnable_bits 1 #define GFX7_MI_ARB_ON_OFF_ArbitrationEnable_bits 1 #define GFX6_MI_ARB_ON_OFF_ArbitrationEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_ARB_ON_OFF_ArbitrationEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_ARB_ON_OFF_ArbitrationEnable_start 0 #define GFX12_MI_ARB_ON_OFF_ArbitrationEnable_start 0 #define GFX11_MI_ARB_ON_OFF_ArbitrationEnable_start 0 #define GFX9_MI_ARB_ON_OFF_ArbitrationEnable_start 0 #define GFX8_MI_ARB_ON_OFF_ArbitrationEnable_start 0 #define GFX75_MI_ARB_ON_OFF_ArbitrationEnable_start 0 #define GFX7_MI_ARB_ON_OFF_ArbitrationEnable_start 0 #define GFX6_MI_ARB_ON_OFF_ArbitrationEnable_start 0 static inline uint32_t ATTRIBUTE_PURE MI_ARB_ON_OFF_ArbitrationEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_ARB_ON_OFF::Command Type */ #define GFX125_MI_ARB_ON_OFF_CommandType_bits 3 #define GFX12_MI_ARB_ON_OFF_CommandType_bits 3 #define GFX11_MI_ARB_ON_OFF_CommandType_bits 3 #define GFX9_MI_ARB_ON_OFF_CommandType_bits 3 #define GFX8_MI_ARB_ON_OFF_CommandType_bits 3 #define GFX75_MI_ARB_ON_OFF_CommandType_bits 3 #define GFX7_MI_ARB_ON_OFF_CommandType_bits 3 #define GFX6_MI_ARB_ON_OFF_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE MI_ARB_ON_OFF_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_ARB_ON_OFF_CommandType_start 29 #define GFX12_MI_ARB_ON_OFF_CommandType_start 29 #define GFX11_MI_ARB_ON_OFF_CommandType_start 29 #define GFX9_MI_ARB_ON_OFF_CommandType_start 29 #define GFX8_MI_ARB_ON_OFF_CommandType_start 29 #define GFX75_MI_ARB_ON_OFF_CommandType_start 29 #define GFX7_MI_ARB_ON_OFF_CommandType_start 29 #define GFX6_MI_ARB_ON_OFF_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE MI_ARB_ON_OFF_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 29; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_ARB_ON_OFF::MI Command Opcode */ #define GFX125_MI_ARB_ON_OFF_MICommandOpcode_bits 6 #define GFX12_MI_ARB_ON_OFF_MICommandOpcode_bits 6 #define GFX11_MI_ARB_ON_OFF_MICommandOpcode_bits 6 #define GFX9_MI_ARB_ON_OFF_MICommandOpcode_bits 6 #define GFX8_MI_ARB_ON_OFF_MICommandOpcode_bits 6 #define GFX75_MI_ARB_ON_OFF_MICommandOpcode_bits 6 #define GFX7_MI_ARB_ON_OFF_MICommandOpcode_bits 6 #define GFX6_MI_ARB_ON_OFF_MICommandOpcode_bits 6 static inline uint32_t ATTRIBUTE_PURE MI_ARB_ON_OFF_MICommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 6; case 60: return 6; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_ARB_ON_OFF_MICommandOpcode_start 23 #define GFX12_MI_ARB_ON_OFF_MICommandOpcode_start 23 #define GFX11_MI_ARB_ON_OFF_MICommandOpcode_start 23 #define GFX9_MI_ARB_ON_OFF_MICommandOpcode_start 23 #define GFX8_MI_ARB_ON_OFF_MICommandOpcode_start 23 #define GFX75_MI_ARB_ON_OFF_MICommandOpcode_start 23 #define GFX7_MI_ARB_ON_OFF_MICommandOpcode_start 23 #define GFX6_MI_ARB_ON_OFF_MICommandOpcode_start 23 static inline uint32_t ATTRIBUTE_PURE MI_ARB_ON_OFF_MICommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 23; case 120: return 23; case 110: return 23; case 90: return 23; case 80: return 23; case 75: return 23; case 70: return 23; case 60: return 23; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_ATOMIC */ #define GFX125_MI_ATOMIC_length 3 #define GFX12_MI_ATOMIC_length 3 #define GFX11_MI_ATOMIC_length 3 #define GFX9_MI_ATOMIC_length 3 #define GFX8_MI_ATOMIC_length 3 static inline uint32_t ATTRIBUTE_PURE MI_ATOMIC_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_ATOMIC::ATOMIC OPCODE */ #define GFX125_MI_ATOMIC_ATOMICOPCODE_bits 8 #define GFX12_MI_ATOMIC_ATOMICOPCODE_bits 8 #define GFX11_MI_ATOMIC_ATOMICOPCODE_bits 8 #define GFX9_MI_ATOMIC_ATOMICOPCODE_bits 8 #define GFX8_MI_ATOMIC_ATOMICOPCODE_bits 8 static inline uint32_t ATTRIBUTE_PURE MI_ATOMIC_ATOMICOPCODE_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_ATOMIC_ATOMICOPCODE_start 8 #define GFX12_MI_ATOMIC_ATOMICOPCODE_start 8 #define GFX11_MI_ATOMIC_ATOMICOPCODE_start 8 #define GFX9_MI_ATOMIC_ATOMICOPCODE_start 8 #define GFX8_MI_ATOMIC_ATOMICOPCODE_start 8 static inline uint32_t ATTRIBUTE_PURE MI_ATOMIC_ATOMICOPCODE_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_ATOMIC::CS STALL */ #define GFX125_MI_ATOMIC_CSSTALL_bits 1 #define GFX12_MI_ATOMIC_CSSTALL_bits 1 #define GFX11_MI_ATOMIC_CSSTALL_bits 1 #define GFX9_MI_ATOMIC_CSSTALL_bits 1 #define GFX8_MI_ATOMIC_CSSTALL_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_ATOMIC_CSSTALL_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_ATOMIC_CSSTALL_start 17 #define GFX12_MI_ATOMIC_CSSTALL_start 17 #define GFX11_MI_ATOMIC_CSSTALL_start 17 #define GFX9_MI_ATOMIC_CSSTALL_start 17 #define GFX8_MI_ATOMIC_CSSTALL_start 17 static inline uint32_t ATTRIBUTE_PURE MI_ATOMIC_CSSTALL_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 17; case 120: return 17; case 110: return 17; case 90: return 17; case 80: return 17; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_ATOMIC::Command Type */ #define GFX125_MI_ATOMIC_CommandType_bits 3 #define GFX12_MI_ATOMIC_CommandType_bits 3 #define GFX11_MI_ATOMIC_CommandType_bits 3 #define GFX9_MI_ATOMIC_CommandType_bits 3 #define GFX8_MI_ATOMIC_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE MI_ATOMIC_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_ATOMIC_CommandType_start 29 #define GFX12_MI_ATOMIC_CommandType_start 29 #define GFX11_MI_ATOMIC_CommandType_start 29 #define GFX9_MI_ATOMIC_CommandType_start 29 #define GFX8_MI_ATOMIC_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE MI_ATOMIC_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_ATOMIC::DWord Length */ #define GFX125_MI_ATOMIC_DWordLength_bits 8 #define GFX12_MI_ATOMIC_DWordLength_bits 8 #define GFX11_MI_ATOMIC_DWordLength_bits 8 #define GFX9_MI_ATOMIC_DWordLength_bits 8 #define GFX8_MI_ATOMIC_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE MI_ATOMIC_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_ATOMIC_DWordLength_start 0 #define GFX12_MI_ATOMIC_DWordLength_start 0 #define GFX11_MI_ATOMIC_DWordLength_start 0 #define GFX9_MI_ATOMIC_DWordLength_start 0 #define GFX8_MI_ATOMIC_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE MI_ATOMIC_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_ATOMIC::Data Size */ #define GFX125_MI_ATOMIC_DataSize_bits 2 #define GFX12_MI_ATOMIC_DataSize_bits 2 #define GFX11_MI_ATOMIC_DataSize_bits 2 #define GFX9_MI_ATOMIC_DataSize_bits 2 #define GFX8_MI_ATOMIC_DataSize_bits 2 static inline uint32_t ATTRIBUTE_PURE MI_ATOMIC_DataSize_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_ATOMIC_DataSize_start 19 #define GFX12_MI_ATOMIC_DataSize_start 19 #define GFX11_MI_ATOMIC_DataSize_start 19 #define GFX9_MI_ATOMIC_DataSize_start 19 #define GFX8_MI_ATOMIC_DataSize_start 19 static inline uint32_t ATTRIBUTE_PURE MI_ATOMIC_DataSize_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 19; case 120: return 19; case 110: return 19; case 90: return 19; case 80: return 19; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_ATOMIC::Inline Data */ #define GFX125_MI_ATOMIC_InlineData_bits 1 #define GFX12_MI_ATOMIC_InlineData_bits 1 #define GFX11_MI_ATOMIC_InlineData_bits 1 #define GFX9_MI_ATOMIC_InlineData_bits 1 #define GFX8_MI_ATOMIC_InlineData_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_ATOMIC_InlineData_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_ATOMIC_InlineData_start 18 #define GFX12_MI_ATOMIC_InlineData_start 18 #define GFX11_MI_ATOMIC_InlineData_start 18 #define GFX9_MI_ATOMIC_InlineData_start 18 #define GFX8_MI_ATOMIC_InlineData_start 18 static inline uint32_t ATTRIBUTE_PURE MI_ATOMIC_InlineData_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 18; case 120: return 18; case 110: return 18; case 90: return 18; case 80: return 18; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_ATOMIC::MI Command Opcode */ #define GFX125_MI_ATOMIC_MICommandOpcode_bits 6 #define GFX12_MI_ATOMIC_MICommandOpcode_bits 6 #define GFX11_MI_ATOMIC_MICommandOpcode_bits 6 #define GFX9_MI_ATOMIC_MICommandOpcode_bits 6 #define GFX8_MI_ATOMIC_MICommandOpcode_bits 6 static inline uint32_t ATTRIBUTE_PURE MI_ATOMIC_MICommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_ATOMIC_MICommandOpcode_start 23 #define GFX12_MI_ATOMIC_MICommandOpcode_start 23 #define GFX11_MI_ATOMIC_MICommandOpcode_start 23 #define GFX9_MI_ATOMIC_MICommandOpcode_start 23 #define GFX8_MI_ATOMIC_MICommandOpcode_start 23 static inline uint32_t ATTRIBUTE_PURE MI_ATOMIC_MICommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 23; case 120: return 23; case 110: return 23; case 90: return 23; case 80: return 23; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_ATOMIC::Memory Address */ #define GFX125_MI_ATOMIC_MemoryAddress_bits 46 #define GFX12_MI_ATOMIC_MemoryAddress_bits 46 #define GFX11_MI_ATOMIC_MemoryAddress_bits 46 #define GFX9_MI_ATOMIC_MemoryAddress_bits 46 #define GFX8_MI_ATOMIC_MemoryAddress_bits 46 static inline uint32_t ATTRIBUTE_PURE MI_ATOMIC_MemoryAddress_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 46; case 120: return 46; case 110: return 46; case 90: return 46; case 80: return 46; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_ATOMIC_MemoryAddress_start 34 #define GFX12_MI_ATOMIC_MemoryAddress_start 34 #define GFX11_MI_ATOMIC_MemoryAddress_start 34 #define GFX9_MI_ATOMIC_MemoryAddress_start 34 #define GFX8_MI_ATOMIC_MemoryAddress_start 34 static inline uint32_t ATTRIBUTE_PURE MI_ATOMIC_MemoryAddress_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 34; case 120: return 34; case 110: return 34; case 90: return 34; case 80: return 34; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_ATOMIC::Memory Type */ #define GFX125_MI_ATOMIC_MemoryType_bits 1 #define GFX12_MI_ATOMIC_MemoryType_bits 1 #define GFX11_MI_ATOMIC_MemoryType_bits 1 #define GFX9_MI_ATOMIC_MemoryType_bits 1 #define GFX8_MI_ATOMIC_MemoryType_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_ATOMIC_MemoryType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_ATOMIC_MemoryType_start 22 #define GFX12_MI_ATOMIC_MemoryType_start 22 #define GFX11_MI_ATOMIC_MemoryType_start 22 #define GFX9_MI_ATOMIC_MemoryType_start 22 #define GFX8_MI_ATOMIC_MemoryType_start 22 static inline uint32_t ATTRIBUTE_PURE MI_ATOMIC_MemoryType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 22; case 120: return 22; case 110: return 22; case 90: return 22; case 80: return 22; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_ATOMIC::Operand1 Data Dword 0 */ #define GFX125_MI_ATOMIC_Operand1DataDword0_bits 32 #define GFX12_MI_ATOMIC_Operand1DataDword0_bits 32 #define GFX11_MI_ATOMIC_Operand1DataDword0_bits 32 #define GFX9_MI_ATOMIC_Operand1DataDword0_bits 32 #define GFX8_MI_ATOMIC_Operand1DataDword0_bits 32 static inline uint32_t ATTRIBUTE_PURE MI_ATOMIC_Operand1DataDword0_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_ATOMIC_Operand1DataDword0_start 96 #define GFX12_MI_ATOMIC_Operand1DataDword0_start 96 #define GFX11_MI_ATOMIC_Operand1DataDword0_start 96 #define GFX9_MI_ATOMIC_Operand1DataDword0_start 96 #define GFX8_MI_ATOMIC_Operand1DataDword0_start 96 static inline uint32_t ATTRIBUTE_PURE MI_ATOMIC_Operand1DataDword0_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 96; case 120: return 96; case 110: return 96; case 90: return 96; case 80: return 96; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_ATOMIC::Operand1 Data Dword 1 */ #define GFX125_MI_ATOMIC_Operand1DataDword1_bits 32 #define GFX12_MI_ATOMIC_Operand1DataDword1_bits 32 #define GFX11_MI_ATOMIC_Operand1DataDword1_bits 32 #define GFX9_MI_ATOMIC_Operand1DataDword1_bits 32 #define GFX8_MI_ATOMIC_Operand1DataDword1_bits 32 static inline uint32_t ATTRIBUTE_PURE MI_ATOMIC_Operand1DataDword1_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_ATOMIC_Operand1DataDword1_start 160 #define GFX12_MI_ATOMIC_Operand1DataDword1_start 160 #define GFX11_MI_ATOMIC_Operand1DataDword1_start 160 #define GFX9_MI_ATOMIC_Operand1DataDword1_start 160 #define GFX8_MI_ATOMIC_Operand1DataDword1_start 160 static inline uint32_t ATTRIBUTE_PURE MI_ATOMIC_Operand1DataDword1_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 160; case 120: return 160; case 110: return 160; case 90: return 160; case 80: return 160; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_ATOMIC::Operand1 Data Dword 2 */ #define GFX125_MI_ATOMIC_Operand1DataDword2_bits 32 #define GFX12_MI_ATOMIC_Operand1DataDword2_bits 32 #define GFX11_MI_ATOMIC_Operand1DataDword2_bits 32 #define GFX9_MI_ATOMIC_Operand1DataDword2_bits 32 #define GFX8_MI_ATOMIC_Operand1DataDword2_bits 32 static inline uint32_t ATTRIBUTE_PURE MI_ATOMIC_Operand1DataDword2_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_ATOMIC_Operand1DataDword2_start 224 #define GFX12_MI_ATOMIC_Operand1DataDword2_start 224 #define GFX11_MI_ATOMIC_Operand1DataDword2_start 224 #define GFX9_MI_ATOMIC_Operand1DataDword2_start 224 #define GFX8_MI_ATOMIC_Operand1DataDword2_start 224 static inline uint32_t ATTRIBUTE_PURE MI_ATOMIC_Operand1DataDword2_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 224; case 120: return 224; case 110: return 224; case 90: return 224; case 80: return 224; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_ATOMIC::Operand1 Data Dword 3 */ #define GFX125_MI_ATOMIC_Operand1DataDword3_bits 32 #define GFX12_MI_ATOMIC_Operand1DataDword3_bits 32 #define GFX11_MI_ATOMIC_Operand1DataDword3_bits 32 #define GFX9_MI_ATOMIC_Operand1DataDword3_bits 32 #define GFX8_MI_ATOMIC_Operand1DataDword3_bits 32 static inline uint32_t ATTRIBUTE_PURE MI_ATOMIC_Operand1DataDword3_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_ATOMIC_Operand1DataDword3_start 288 #define GFX12_MI_ATOMIC_Operand1DataDword3_start 288 #define GFX11_MI_ATOMIC_Operand1DataDword3_start 288 #define GFX9_MI_ATOMIC_Operand1DataDword3_start 288 #define GFX8_MI_ATOMIC_Operand1DataDword3_start 288 static inline uint32_t ATTRIBUTE_PURE MI_ATOMIC_Operand1DataDword3_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 288; case 120: return 288; case 110: return 288; case 90: return 288; case 80: return 288; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_ATOMIC::Operand2 Data Dword 0 */ #define GFX125_MI_ATOMIC_Operand2DataDword0_bits 32 #define GFX12_MI_ATOMIC_Operand2DataDword0_bits 32 #define GFX11_MI_ATOMIC_Operand2DataDword0_bits 32 #define GFX9_MI_ATOMIC_Operand2DataDword0_bits 32 #define GFX8_MI_ATOMIC_Operand2DataDword0_bits 32 static inline uint32_t ATTRIBUTE_PURE MI_ATOMIC_Operand2DataDword0_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_ATOMIC_Operand2DataDword0_start 128 #define GFX12_MI_ATOMIC_Operand2DataDword0_start 128 #define GFX11_MI_ATOMIC_Operand2DataDword0_start 128 #define GFX9_MI_ATOMIC_Operand2DataDword0_start 128 #define GFX8_MI_ATOMIC_Operand2DataDword0_start 128 static inline uint32_t ATTRIBUTE_PURE MI_ATOMIC_Operand2DataDword0_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 128; case 120: return 128; case 110: return 128; case 90: return 128; case 80: return 128; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_ATOMIC::Operand2 Data Dword 1 */ #define GFX125_MI_ATOMIC_Operand2DataDword1_bits 32 #define GFX12_MI_ATOMIC_Operand2DataDword1_bits 32 #define GFX11_MI_ATOMIC_Operand2DataDword1_bits 32 #define GFX9_MI_ATOMIC_Operand2DataDword1_bits 32 #define GFX8_MI_ATOMIC_Operand2DataDword1_bits 32 static inline uint32_t ATTRIBUTE_PURE MI_ATOMIC_Operand2DataDword1_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_ATOMIC_Operand2DataDword1_start 192 #define GFX12_MI_ATOMIC_Operand2DataDword1_start 192 #define GFX11_MI_ATOMIC_Operand2DataDword1_start 192 #define GFX9_MI_ATOMIC_Operand2DataDword1_start 192 #define GFX8_MI_ATOMIC_Operand2DataDword1_start 192 static inline uint32_t ATTRIBUTE_PURE MI_ATOMIC_Operand2DataDword1_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 192; case 120: return 192; case 110: return 192; case 90: return 192; case 80: return 192; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_ATOMIC::Operand2 Data Dword 2 */ #define GFX125_MI_ATOMIC_Operand2DataDword2_bits 32 #define GFX12_MI_ATOMIC_Operand2DataDword2_bits 32 #define GFX11_MI_ATOMIC_Operand2DataDword2_bits 32 #define GFX9_MI_ATOMIC_Operand2DataDword2_bits 32 #define GFX8_MI_ATOMIC_Operand2DataDword2_bits 32 static inline uint32_t ATTRIBUTE_PURE MI_ATOMIC_Operand2DataDword2_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_ATOMIC_Operand2DataDword2_start 256 #define GFX12_MI_ATOMIC_Operand2DataDword2_start 256 #define GFX11_MI_ATOMIC_Operand2DataDword2_start 256 #define GFX9_MI_ATOMIC_Operand2DataDword2_start 256 #define GFX8_MI_ATOMIC_Operand2DataDword2_start 256 static inline uint32_t ATTRIBUTE_PURE MI_ATOMIC_Operand2DataDword2_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 256; case 120: return 256; case 110: return 256; case 90: return 256; case 80: return 256; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_ATOMIC::Operand2 Data Dword 3 */ #define GFX125_MI_ATOMIC_Operand2DataDword3_bits 32 #define GFX12_MI_ATOMIC_Operand2DataDword3_bits 32 #define GFX11_MI_ATOMIC_Operand2DataDword3_bits 32 #define GFX9_MI_ATOMIC_Operand2DataDword3_bits 32 #define GFX8_MI_ATOMIC_Operand2DataDword3_bits 32 static inline uint32_t ATTRIBUTE_PURE MI_ATOMIC_Operand2DataDword3_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_ATOMIC_Operand2DataDword3_start 320 #define GFX12_MI_ATOMIC_Operand2DataDword3_start 320 #define GFX11_MI_ATOMIC_Operand2DataDword3_start 320 #define GFX9_MI_ATOMIC_Operand2DataDword3_start 320 #define GFX8_MI_ATOMIC_Operand2DataDword3_start 320 static inline uint32_t ATTRIBUTE_PURE MI_ATOMIC_Operand2DataDword3_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 320; case 120: return 320; case 110: return 320; case 90: return 320; case 80: return 320; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_ATOMIC::Post-Sync Operation */ #define GFX125_MI_ATOMIC_PostSyncOperation_bits 1 #define GFX12_MI_ATOMIC_PostSyncOperation_bits 1 #define GFX11_MI_ATOMIC_PostSyncOperation_bits 1 #define GFX9_MI_ATOMIC_PostSyncOperation_bits 1 #define GFX8_MI_ATOMIC_PostSyncOperation_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_ATOMIC_PostSyncOperation_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_ATOMIC_PostSyncOperation_start 21 #define GFX12_MI_ATOMIC_PostSyncOperation_start 21 #define GFX11_MI_ATOMIC_PostSyncOperation_start 21 #define GFX9_MI_ATOMIC_PostSyncOperation_start 21 #define GFX8_MI_ATOMIC_PostSyncOperation_start 21 static inline uint32_t ATTRIBUTE_PURE MI_ATOMIC_PostSyncOperation_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 21; case 120: return 21; case 110: return 21; case 90: return 21; case 80: return 21; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_ATOMIC::Return Data Control */ #define GFX125_MI_ATOMIC_ReturnDataControl_bits 1 #define GFX12_MI_ATOMIC_ReturnDataControl_bits 1 #define GFX11_MI_ATOMIC_ReturnDataControl_bits 1 #define GFX9_MI_ATOMIC_ReturnDataControl_bits 1 #define GFX8_MI_ATOMIC_ReturnDataControl_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_ATOMIC_ReturnDataControl_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_ATOMIC_ReturnDataControl_start 16 #define GFX12_MI_ATOMIC_ReturnDataControl_start 16 #define GFX11_MI_ATOMIC_ReturnDataControl_start 16 #define GFX9_MI_ATOMIC_ReturnDataControl_start 16 #define GFX8_MI_ATOMIC_ReturnDataControl_start 16 static inline uint32_t ATTRIBUTE_PURE MI_ATOMIC_ReturnDataControl_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_BATCH_BUFFER_END */ #define GFX125_MI_BATCH_BUFFER_END_length 1 #define GFX12_MI_BATCH_BUFFER_END_length 1 #define GFX11_MI_BATCH_BUFFER_END_length 1 #define GFX9_MI_BATCH_BUFFER_END_length 1 #define GFX8_MI_BATCH_BUFFER_END_length 1 #define GFX75_MI_BATCH_BUFFER_END_length 1 #define GFX7_MI_BATCH_BUFFER_END_length 1 #define GFX6_MI_BATCH_BUFFER_END_length 1 static inline uint32_t ATTRIBUTE_PURE MI_BATCH_BUFFER_END_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_BATCH_BUFFER_END::Command Type */ #define GFX125_MI_BATCH_BUFFER_END_CommandType_bits 3 #define GFX12_MI_BATCH_BUFFER_END_CommandType_bits 3 #define GFX11_MI_BATCH_BUFFER_END_CommandType_bits 3 #define GFX9_MI_BATCH_BUFFER_END_CommandType_bits 3 #define GFX8_MI_BATCH_BUFFER_END_CommandType_bits 3 #define GFX75_MI_BATCH_BUFFER_END_CommandType_bits 3 #define GFX7_MI_BATCH_BUFFER_END_CommandType_bits 3 #define GFX6_MI_BATCH_BUFFER_END_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE MI_BATCH_BUFFER_END_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_BATCH_BUFFER_END_CommandType_start 29 #define GFX12_MI_BATCH_BUFFER_END_CommandType_start 29 #define GFX11_MI_BATCH_BUFFER_END_CommandType_start 29 #define GFX9_MI_BATCH_BUFFER_END_CommandType_start 29 #define GFX8_MI_BATCH_BUFFER_END_CommandType_start 29 #define GFX75_MI_BATCH_BUFFER_END_CommandType_start 29 #define GFX7_MI_BATCH_BUFFER_END_CommandType_start 29 #define GFX6_MI_BATCH_BUFFER_END_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE MI_BATCH_BUFFER_END_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 29; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_BATCH_BUFFER_END::End Context */ #define GFX125_MI_BATCH_BUFFER_END_EndContext_bits 1 #define GFX12_MI_BATCH_BUFFER_END_EndContext_bits 1 #define GFX11_MI_BATCH_BUFFER_END_EndContext_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_BATCH_BUFFER_END_EndContext_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_BATCH_BUFFER_END_EndContext_start 0 #define GFX12_MI_BATCH_BUFFER_END_EndContext_start 0 #define GFX11_MI_BATCH_BUFFER_END_EndContext_start 0 static inline uint32_t ATTRIBUTE_PURE MI_BATCH_BUFFER_END_EndContext_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_BATCH_BUFFER_END::MI Command Opcode */ #define GFX125_MI_BATCH_BUFFER_END_MICommandOpcode_bits 6 #define GFX12_MI_BATCH_BUFFER_END_MICommandOpcode_bits 6 #define GFX11_MI_BATCH_BUFFER_END_MICommandOpcode_bits 6 #define GFX9_MI_BATCH_BUFFER_END_MICommandOpcode_bits 6 #define GFX8_MI_BATCH_BUFFER_END_MICommandOpcode_bits 6 #define GFX75_MI_BATCH_BUFFER_END_MICommandOpcode_bits 6 #define GFX7_MI_BATCH_BUFFER_END_MICommandOpcode_bits 6 #define GFX6_MI_BATCH_BUFFER_END_MICommandOpcode_bits 6 static inline uint32_t ATTRIBUTE_PURE MI_BATCH_BUFFER_END_MICommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 6; case 60: return 6; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_BATCH_BUFFER_END_MICommandOpcode_start 23 #define GFX12_MI_BATCH_BUFFER_END_MICommandOpcode_start 23 #define GFX11_MI_BATCH_BUFFER_END_MICommandOpcode_start 23 #define GFX9_MI_BATCH_BUFFER_END_MICommandOpcode_start 23 #define GFX8_MI_BATCH_BUFFER_END_MICommandOpcode_start 23 #define GFX75_MI_BATCH_BUFFER_END_MICommandOpcode_start 23 #define GFX7_MI_BATCH_BUFFER_END_MICommandOpcode_start 23 #define GFX6_MI_BATCH_BUFFER_END_MICommandOpcode_start 23 static inline uint32_t ATTRIBUTE_PURE MI_BATCH_BUFFER_END_MICommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 23; case 120: return 23; case 110: return 23; case 90: return 23; case 80: return 23; case 75: return 23; case 70: return 23; case 60: return 23; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_BATCH_BUFFER_START */ #define GFX125_MI_BATCH_BUFFER_START_length 3 #define GFX12_MI_BATCH_BUFFER_START_length 3 #define GFX11_MI_BATCH_BUFFER_START_length 3 #define GFX9_MI_BATCH_BUFFER_START_length 3 #define GFX8_MI_BATCH_BUFFER_START_length 3 #define GFX75_MI_BATCH_BUFFER_START_length 2 #define GFX7_MI_BATCH_BUFFER_START_length 2 #define GFX6_MI_BATCH_BUFFER_START_length 2 static inline uint32_t ATTRIBUTE_PURE MI_BATCH_BUFFER_START_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_BATCH_BUFFER_START::Add Offset Enable */ #define GFX9_MI_BATCH_BUFFER_START_AddOffsetEnable_bits 1 #define GFX8_MI_BATCH_BUFFER_START_AddOffsetEnable_bits 1 #define GFX75_MI_BATCH_BUFFER_START_AddOffsetEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_BATCH_BUFFER_START_AddOffsetEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_MI_BATCH_BUFFER_START_AddOffsetEnable_start 16 #define GFX8_MI_BATCH_BUFFER_START_AddOffsetEnable_start 16 #define GFX75_MI_BATCH_BUFFER_START_AddOffsetEnable_start 16 static inline uint32_t ATTRIBUTE_PURE MI_BATCH_BUFFER_START_AddOffsetEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_BATCH_BUFFER_START::Address Space Indicator */ #define GFX125_MI_BATCH_BUFFER_START_AddressSpaceIndicator_bits 1 #define GFX12_MI_BATCH_BUFFER_START_AddressSpaceIndicator_bits 1 #define GFX11_MI_BATCH_BUFFER_START_AddressSpaceIndicator_bits 1 #define GFX9_MI_BATCH_BUFFER_START_AddressSpaceIndicator_bits 1 #define GFX8_MI_BATCH_BUFFER_START_AddressSpaceIndicator_bits 1 #define GFX75_MI_BATCH_BUFFER_START_AddressSpaceIndicator_bits 1 #define GFX7_MI_BATCH_BUFFER_START_AddressSpaceIndicator_bits 1 #define GFX6_MI_BATCH_BUFFER_START_AddressSpaceIndicator_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_BATCH_BUFFER_START_AddressSpaceIndicator_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_BATCH_BUFFER_START_AddressSpaceIndicator_start 8 #define GFX12_MI_BATCH_BUFFER_START_AddressSpaceIndicator_start 8 #define GFX11_MI_BATCH_BUFFER_START_AddressSpaceIndicator_start 8 #define GFX9_MI_BATCH_BUFFER_START_AddressSpaceIndicator_start 8 #define GFX8_MI_BATCH_BUFFER_START_AddressSpaceIndicator_start 8 #define GFX75_MI_BATCH_BUFFER_START_AddressSpaceIndicator_start 8 #define GFX7_MI_BATCH_BUFFER_START_AddressSpaceIndicator_start 8 #define GFX6_MI_BATCH_BUFFER_START_AddressSpaceIndicator_start 8 static inline uint32_t ATTRIBUTE_PURE MI_BATCH_BUFFER_START_AddressSpaceIndicator_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_BATCH_BUFFER_START::Batch Buffer Start Address */ #define GFX125_MI_BATCH_BUFFER_START_BatchBufferStartAddress_bits 62 #define GFX12_MI_BATCH_BUFFER_START_BatchBufferStartAddress_bits 62 #define GFX11_MI_BATCH_BUFFER_START_BatchBufferStartAddress_bits 62 #define GFX9_MI_BATCH_BUFFER_START_BatchBufferStartAddress_bits 62 #define GFX8_MI_BATCH_BUFFER_START_BatchBufferStartAddress_bits 46 #define GFX75_MI_BATCH_BUFFER_START_BatchBufferStartAddress_bits 30 #define GFX7_MI_BATCH_BUFFER_START_BatchBufferStartAddress_bits 30 #define GFX6_MI_BATCH_BUFFER_START_BatchBufferStartAddress_bits 30 static inline uint32_t ATTRIBUTE_PURE MI_BATCH_BUFFER_START_BatchBufferStartAddress_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 62; case 120: return 62; case 110: return 62; case 90: return 62; case 80: return 46; case 75: return 30; case 70: return 30; case 60: return 30; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_BATCH_BUFFER_START_BatchBufferStartAddress_start 34 #define GFX12_MI_BATCH_BUFFER_START_BatchBufferStartAddress_start 34 #define GFX11_MI_BATCH_BUFFER_START_BatchBufferStartAddress_start 34 #define GFX9_MI_BATCH_BUFFER_START_BatchBufferStartAddress_start 34 #define GFX8_MI_BATCH_BUFFER_START_BatchBufferStartAddress_start 34 #define GFX75_MI_BATCH_BUFFER_START_BatchBufferStartAddress_start 34 #define GFX7_MI_BATCH_BUFFER_START_BatchBufferStartAddress_start 34 #define GFX6_MI_BATCH_BUFFER_START_BatchBufferStartAddress_start 34 static inline uint32_t ATTRIBUTE_PURE MI_BATCH_BUFFER_START_BatchBufferStartAddress_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 34; case 120: return 34; case 110: return 34; case 90: return 34; case 80: return 34; case 75: return 34; case 70: return 34; case 60: return 34; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_BATCH_BUFFER_START::Clear Command Buffer Enable */ #define GFX75_MI_BATCH_BUFFER_START_ClearCommandBufferEnable_bits 1 #define GFX7_MI_BATCH_BUFFER_START_ClearCommandBufferEnable_bits 1 #define GFX6_MI_BATCH_BUFFER_START_ClearCommandBufferEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_BATCH_BUFFER_START_ClearCommandBufferEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_MI_BATCH_BUFFER_START_ClearCommandBufferEnable_start 11 #define GFX7_MI_BATCH_BUFFER_START_ClearCommandBufferEnable_start 11 #define GFX6_MI_BATCH_BUFFER_START_ClearCommandBufferEnable_start 11 static inline uint32_t ATTRIBUTE_PURE MI_BATCH_BUFFER_START_ClearCommandBufferEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 11; case 70: return 11; case 60: return 11; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_BATCH_BUFFER_START::Command Type */ #define GFX125_MI_BATCH_BUFFER_START_CommandType_bits 3 #define GFX12_MI_BATCH_BUFFER_START_CommandType_bits 3 #define GFX11_MI_BATCH_BUFFER_START_CommandType_bits 3 #define GFX9_MI_BATCH_BUFFER_START_CommandType_bits 3 #define GFX8_MI_BATCH_BUFFER_START_CommandType_bits 3 #define GFX75_MI_BATCH_BUFFER_START_CommandType_bits 3 #define GFX7_MI_BATCH_BUFFER_START_CommandType_bits 3 #define GFX6_MI_BATCH_BUFFER_START_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE MI_BATCH_BUFFER_START_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_BATCH_BUFFER_START_CommandType_start 29 #define GFX12_MI_BATCH_BUFFER_START_CommandType_start 29 #define GFX11_MI_BATCH_BUFFER_START_CommandType_start 29 #define GFX9_MI_BATCH_BUFFER_START_CommandType_start 29 #define GFX8_MI_BATCH_BUFFER_START_CommandType_start 29 #define GFX75_MI_BATCH_BUFFER_START_CommandType_start 29 #define GFX7_MI_BATCH_BUFFER_START_CommandType_start 29 #define GFX6_MI_BATCH_BUFFER_START_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE MI_BATCH_BUFFER_START_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 29; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_BATCH_BUFFER_START::DWord Length */ #define GFX125_MI_BATCH_BUFFER_START_DWordLength_bits 8 #define GFX12_MI_BATCH_BUFFER_START_DWordLength_bits 8 #define GFX11_MI_BATCH_BUFFER_START_DWordLength_bits 8 #define GFX9_MI_BATCH_BUFFER_START_DWordLength_bits 8 #define GFX8_MI_BATCH_BUFFER_START_DWordLength_bits 8 #define GFX75_MI_BATCH_BUFFER_START_DWordLength_bits 8 #define GFX7_MI_BATCH_BUFFER_START_DWordLength_bits 8 #define GFX6_MI_BATCH_BUFFER_START_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE MI_BATCH_BUFFER_START_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_BATCH_BUFFER_START_DWordLength_start 0 #define GFX12_MI_BATCH_BUFFER_START_DWordLength_start 0 #define GFX11_MI_BATCH_BUFFER_START_DWordLength_start 0 #define GFX9_MI_BATCH_BUFFER_START_DWordLength_start 0 #define GFX8_MI_BATCH_BUFFER_START_DWordLength_start 0 #define GFX75_MI_BATCH_BUFFER_START_DWordLength_start 0 #define GFX7_MI_BATCH_BUFFER_START_DWordLength_start 0 #define GFX6_MI_BATCH_BUFFER_START_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE MI_BATCH_BUFFER_START_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_BATCH_BUFFER_START::MI Command Opcode */ #define GFX125_MI_BATCH_BUFFER_START_MICommandOpcode_bits 6 #define GFX12_MI_BATCH_BUFFER_START_MICommandOpcode_bits 6 #define GFX11_MI_BATCH_BUFFER_START_MICommandOpcode_bits 6 #define GFX9_MI_BATCH_BUFFER_START_MICommandOpcode_bits 6 #define GFX8_MI_BATCH_BUFFER_START_MICommandOpcode_bits 6 #define GFX75_MI_BATCH_BUFFER_START_MICommandOpcode_bits 6 #define GFX7_MI_BATCH_BUFFER_START_MICommandOpcode_bits 6 #define GFX6_MI_BATCH_BUFFER_START_MICommandOpcode_bits 6 static inline uint32_t ATTRIBUTE_PURE MI_BATCH_BUFFER_START_MICommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 6; case 60: return 6; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_BATCH_BUFFER_START_MICommandOpcode_start 23 #define GFX12_MI_BATCH_BUFFER_START_MICommandOpcode_start 23 #define GFX11_MI_BATCH_BUFFER_START_MICommandOpcode_start 23 #define GFX9_MI_BATCH_BUFFER_START_MICommandOpcode_start 23 #define GFX8_MI_BATCH_BUFFER_START_MICommandOpcode_start 23 #define GFX75_MI_BATCH_BUFFER_START_MICommandOpcode_start 23 #define GFX7_MI_BATCH_BUFFER_START_MICommandOpcode_start 23 #define GFX6_MI_BATCH_BUFFER_START_MICommandOpcode_start 23 static inline uint32_t ATTRIBUTE_PURE MI_BATCH_BUFFER_START_MICommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 23; case 120: return 23; case 110: return 23; case 90: return 23; case 80: return 23; case 75: return 23; case 70: return 23; case 60: return 23; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_BATCH_BUFFER_START::Non-Privileged */ #define GFX75_MI_BATCH_BUFFER_START_NonPrivileged_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_BATCH_BUFFER_START_NonPrivileged_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_MI_BATCH_BUFFER_START_NonPrivileged_start 13 static inline uint32_t ATTRIBUTE_PURE MI_BATCH_BUFFER_START_NonPrivileged_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 13; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_BATCH_BUFFER_START::Predication Enable */ #define GFX125_MI_BATCH_BUFFER_START_PredicationEnable_bits 1 #define GFX12_MI_BATCH_BUFFER_START_PredicationEnable_bits 1 #define GFX11_MI_BATCH_BUFFER_START_PredicationEnable_bits 1 #define GFX9_MI_BATCH_BUFFER_START_PredicationEnable_bits 1 #define GFX8_MI_BATCH_BUFFER_START_PredicationEnable_bits 1 #define GFX75_MI_BATCH_BUFFER_START_PredicationEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_BATCH_BUFFER_START_PredicationEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_BATCH_BUFFER_START_PredicationEnable_start 15 #define GFX12_MI_BATCH_BUFFER_START_PredicationEnable_start 15 #define GFX11_MI_BATCH_BUFFER_START_PredicationEnable_start 15 #define GFX9_MI_BATCH_BUFFER_START_PredicationEnable_start 15 #define GFX8_MI_BATCH_BUFFER_START_PredicationEnable_start 15 #define GFX75_MI_BATCH_BUFFER_START_PredicationEnable_start 15 static inline uint32_t ATTRIBUTE_PURE MI_BATCH_BUFFER_START_PredicationEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 15; case 120: return 15; case 110: return 15; case 90: return 15; case 80: return 15; case 75: return 15; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_BATCH_BUFFER_START::Resource Streamer Enable */ #define GFX125_MI_BATCH_BUFFER_START_ResourceStreamerEnable_bits 1 #define GFX12_MI_BATCH_BUFFER_START_ResourceStreamerEnable_bits 1 #define GFX11_MI_BATCH_BUFFER_START_ResourceStreamerEnable_bits 1 #define GFX9_MI_BATCH_BUFFER_START_ResourceStreamerEnable_bits 1 #define GFX8_MI_BATCH_BUFFER_START_ResourceStreamerEnable_bits 1 #define GFX75_MI_BATCH_BUFFER_START_ResourceStreamerEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_BATCH_BUFFER_START_ResourceStreamerEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_BATCH_BUFFER_START_ResourceStreamerEnable_start 10 #define GFX12_MI_BATCH_BUFFER_START_ResourceStreamerEnable_start 10 #define GFX11_MI_BATCH_BUFFER_START_ResourceStreamerEnable_start 10 #define GFX9_MI_BATCH_BUFFER_START_ResourceStreamerEnable_start 10 #define GFX8_MI_BATCH_BUFFER_START_ResourceStreamerEnable_start 10 #define GFX75_MI_BATCH_BUFFER_START_ResourceStreamerEnable_start 10 static inline uint32_t ATTRIBUTE_PURE MI_BATCH_BUFFER_START_ResourceStreamerEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 10; case 120: return 10; case 110: return 10; case 90: return 10; case 80: return 10; case 75: return 10; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_BATCH_BUFFER_START::Second Level Batch Buffer */ #define GFX125_MI_BATCH_BUFFER_START_SecondLevelBatchBuffer_bits 1 #define GFX12_MI_BATCH_BUFFER_START_SecondLevelBatchBuffer_bits 1 #define GFX11_MI_BATCH_BUFFER_START_SecondLevelBatchBuffer_bits 1 #define GFX9_MI_BATCH_BUFFER_START_SecondLevelBatchBuffer_bits 1 #define GFX8_MI_BATCH_BUFFER_START_SecondLevelBatchBuffer_bits 1 #define GFX75_MI_BATCH_BUFFER_START_SecondLevelBatchBuffer_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_BATCH_BUFFER_START_SecondLevelBatchBuffer_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_BATCH_BUFFER_START_SecondLevelBatchBuffer_start 22 #define GFX12_MI_BATCH_BUFFER_START_SecondLevelBatchBuffer_start 22 #define GFX11_MI_BATCH_BUFFER_START_SecondLevelBatchBuffer_start 22 #define GFX9_MI_BATCH_BUFFER_START_SecondLevelBatchBuffer_start 22 #define GFX8_MI_BATCH_BUFFER_START_SecondLevelBatchBuffer_start 22 #define GFX75_MI_BATCH_BUFFER_START_SecondLevelBatchBuffer_start 22 static inline uint32_t ATTRIBUTE_PURE MI_BATCH_BUFFER_START_SecondLevelBatchBuffer_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 22; case 120: return 22; case 110: return 22; case 90: return 22; case 80: return 22; case 75: return 22; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_CLFLUSH */ /* MI_CLFLUSH::Command Type */ #define GFX125_MI_CLFLUSH_CommandType_bits 3 #define GFX12_MI_CLFLUSH_CommandType_bits 3 #define GFX11_MI_CLFLUSH_CommandType_bits 3 #define GFX9_MI_CLFLUSH_CommandType_bits 3 #define GFX8_MI_CLFLUSH_CommandType_bits 3 #define GFX75_MI_CLFLUSH_CommandType_bits 3 #define GFX7_MI_CLFLUSH_CommandType_bits 3 #define GFX6_MI_CLFLUSH_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE MI_CLFLUSH_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_CLFLUSH_CommandType_start 29 #define GFX12_MI_CLFLUSH_CommandType_start 29 #define GFX11_MI_CLFLUSH_CommandType_start 29 #define GFX9_MI_CLFLUSH_CommandType_start 29 #define GFX8_MI_CLFLUSH_CommandType_start 29 #define GFX75_MI_CLFLUSH_CommandType_start 29 #define GFX7_MI_CLFLUSH_CommandType_start 29 #define GFX6_MI_CLFLUSH_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE MI_CLFLUSH_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 29; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_CLFLUSH::DWord Length */ #define GFX125_MI_CLFLUSH_DWordLength_bits 10 #define GFX12_MI_CLFLUSH_DWordLength_bits 10 #define GFX11_MI_CLFLUSH_DWordLength_bits 10 #define GFX9_MI_CLFLUSH_DWordLength_bits 10 #define GFX8_MI_CLFLUSH_DWordLength_bits 10 #define GFX75_MI_CLFLUSH_DWordLength_bits 10 #define GFX7_MI_CLFLUSH_DWordLength_bits 10 #define GFX6_MI_CLFLUSH_DWordLength_bits 6 static inline uint32_t ATTRIBUTE_PURE MI_CLFLUSH_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 10; case 120: return 10; case 110: return 10; case 90: return 10; case 80: return 10; case 75: return 10; case 70: return 10; case 60: return 6; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_CLFLUSH_DWordLength_start 0 #define GFX12_MI_CLFLUSH_DWordLength_start 0 #define GFX11_MI_CLFLUSH_DWordLength_start 0 #define GFX9_MI_CLFLUSH_DWordLength_start 0 #define GFX8_MI_CLFLUSH_DWordLength_start 0 #define GFX75_MI_CLFLUSH_DWordLength_start 0 #define GFX7_MI_CLFLUSH_DWordLength_start 0 #define GFX6_MI_CLFLUSH_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE MI_CLFLUSH_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_CLFLUSH::MI Command Opcode */ #define GFX125_MI_CLFLUSH_MICommandOpcode_bits 6 #define GFX12_MI_CLFLUSH_MICommandOpcode_bits 6 #define GFX11_MI_CLFLUSH_MICommandOpcode_bits 6 #define GFX9_MI_CLFLUSH_MICommandOpcode_bits 6 #define GFX8_MI_CLFLUSH_MICommandOpcode_bits 6 #define GFX75_MI_CLFLUSH_MICommandOpcode_bits 6 #define GFX7_MI_CLFLUSH_MICommandOpcode_bits 6 #define GFX6_MI_CLFLUSH_MICommandOpcode_bits 6 static inline uint32_t ATTRIBUTE_PURE MI_CLFLUSH_MICommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 6; case 60: return 6; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_CLFLUSH_MICommandOpcode_start 23 #define GFX12_MI_CLFLUSH_MICommandOpcode_start 23 #define GFX11_MI_CLFLUSH_MICommandOpcode_start 23 #define GFX9_MI_CLFLUSH_MICommandOpcode_start 23 #define GFX8_MI_CLFLUSH_MICommandOpcode_start 23 #define GFX75_MI_CLFLUSH_MICommandOpcode_start 23 #define GFX7_MI_CLFLUSH_MICommandOpcode_start 23 #define GFX6_MI_CLFLUSH_MICommandOpcode_start 23 static inline uint32_t ATTRIBUTE_PURE MI_CLFLUSH_MICommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 23; case 120: return 23; case 110: return 23; case 90: return 23; case 80: return 23; case 75: return 23; case 70: return 23; case 60: return 23; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_CLFLUSH::Page Base Address */ #define GFX125_MI_CLFLUSH_PageBaseAddress_bits 36 #define GFX12_MI_CLFLUSH_PageBaseAddress_bits 36 #define GFX11_MI_CLFLUSH_PageBaseAddress_bits 36 #define GFX9_MI_CLFLUSH_PageBaseAddress_bits 36 #define GFX8_MI_CLFLUSH_PageBaseAddress_bits 36 #define GFX75_MI_CLFLUSH_PageBaseAddress_bits 20 #define GFX7_MI_CLFLUSH_PageBaseAddress_bits 20 #define GFX6_MI_CLFLUSH_PageBaseAddress_bits 20 static inline uint32_t ATTRIBUTE_PURE MI_CLFLUSH_PageBaseAddress_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 36; case 120: return 36; case 110: return 36; case 90: return 36; case 80: return 36; case 75: return 20; case 70: return 20; case 60: return 20; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_CLFLUSH_PageBaseAddress_start 44 #define GFX12_MI_CLFLUSH_PageBaseAddress_start 44 #define GFX11_MI_CLFLUSH_PageBaseAddress_start 44 #define GFX9_MI_CLFLUSH_PageBaseAddress_start 44 #define GFX8_MI_CLFLUSH_PageBaseAddress_start 44 #define GFX75_MI_CLFLUSH_PageBaseAddress_start 44 #define GFX7_MI_CLFLUSH_PageBaseAddress_start 44 #define GFX6_MI_CLFLUSH_PageBaseAddress_start 44 static inline uint32_t ATTRIBUTE_PURE MI_CLFLUSH_PageBaseAddress_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 44; case 120: return 44; case 110: return 44; case 90: return 44; case 80: return 44; case 75: return 44; case 70: return 44; case 60: return 44; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_CLFLUSH::Page Base Address High */ #define GFX75_MI_CLFLUSH_PageBaseAddressHigh_bits 16 #define GFX7_MI_CLFLUSH_PageBaseAddressHigh_bits 16 static inline uint32_t ATTRIBUTE_PURE MI_CLFLUSH_PageBaseAddressHigh_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 16; case 70: return 16; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_MI_CLFLUSH_PageBaseAddressHigh_start 64 #define GFX7_MI_CLFLUSH_PageBaseAddressHigh_start 64 static inline uint32_t ATTRIBUTE_PURE MI_CLFLUSH_PageBaseAddressHigh_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 64; case 70: return 64; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_CLFLUSH::Starting Cacheline Offset */ #define GFX125_MI_CLFLUSH_StartingCachelineOffset_bits 6 #define GFX12_MI_CLFLUSH_StartingCachelineOffset_bits 6 #define GFX11_MI_CLFLUSH_StartingCachelineOffset_bits 6 #define GFX9_MI_CLFLUSH_StartingCachelineOffset_bits 6 #define GFX8_MI_CLFLUSH_StartingCachelineOffset_bits 6 #define GFX75_MI_CLFLUSH_StartingCachelineOffset_bits 6 #define GFX7_MI_CLFLUSH_StartingCachelineOffset_bits 6 #define GFX6_MI_CLFLUSH_StartingCachelineOffset_bits 6 static inline uint32_t ATTRIBUTE_PURE MI_CLFLUSH_StartingCachelineOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 6; case 60: return 6; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_CLFLUSH_StartingCachelineOffset_start 38 #define GFX12_MI_CLFLUSH_StartingCachelineOffset_start 38 #define GFX11_MI_CLFLUSH_StartingCachelineOffset_start 38 #define GFX9_MI_CLFLUSH_StartingCachelineOffset_start 38 #define GFX8_MI_CLFLUSH_StartingCachelineOffset_start 38 #define GFX75_MI_CLFLUSH_StartingCachelineOffset_start 38 #define GFX7_MI_CLFLUSH_StartingCachelineOffset_start 38 #define GFX6_MI_CLFLUSH_StartingCachelineOffset_start 38 static inline uint32_t ATTRIBUTE_PURE MI_CLFLUSH_StartingCachelineOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 38; case 120: return 38; case 110: return 38; case 90: return 38; case 80: return 38; case 75: return 38; case 70: return 38; case 60: return 38; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_CLFLUSH::Use Global GTT */ #define GFX125_MI_CLFLUSH_UseGlobalGTT_bits 1 #define GFX12_MI_CLFLUSH_UseGlobalGTT_bits 1 #define GFX11_MI_CLFLUSH_UseGlobalGTT_bits 1 #define GFX9_MI_CLFLUSH_UseGlobalGTT_bits 1 #define GFX8_MI_CLFLUSH_UseGlobalGTT_bits 1 #define GFX75_MI_CLFLUSH_UseGlobalGTT_bits 1 #define GFX7_MI_CLFLUSH_UseGlobalGTT_bits 1 #define GFX6_MI_CLFLUSH_UseGlobalGTT_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_CLFLUSH_UseGlobalGTT_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_CLFLUSH_UseGlobalGTT_start 22 #define GFX12_MI_CLFLUSH_UseGlobalGTT_start 22 #define GFX11_MI_CLFLUSH_UseGlobalGTT_start 22 #define GFX9_MI_CLFLUSH_UseGlobalGTT_start 22 #define GFX8_MI_CLFLUSH_UseGlobalGTT_start 22 #define GFX75_MI_CLFLUSH_UseGlobalGTT_start 22 #define GFX7_MI_CLFLUSH_UseGlobalGTT_start 22 #define GFX6_MI_CLFLUSH_UseGlobalGTT_start 22 static inline uint32_t ATTRIBUTE_PURE MI_CLFLUSH_UseGlobalGTT_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 22; case 120: return 22; case 110: return 22; case 90: return 22; case 80: return 22; case 75: return 22; case 70: return 22; case 60: return 22; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_CONDITIONAL_BATCH_BUFFER_END */ #define GFX125_MI_CONDITIONAL_BATCH_BUFFER_END_length 4 #define GFX12_MI_CONDITIONAL_BATCH_BUFFER_END_length 4 #define GFX11_MI_CONDITIONAL_BATCH_BUFFER_END_length 4 #define GFX9_MI_CONDITIONAL_BATCH_BUFFER_END_length 4 #define GFX8_MI_CONDITIONAL_BATCH_BUFFER_END_length 3 #define GFX75_MI_CONDITIONAL_BATCH_BUFFER_END_length 2 #define GFX7_MI_CONDITIONAL_BATCH_BUFFER_END_length 2 #define GFX6_MI_CONDITIONAL_BATCH_BUFFER_END_length 2 static inline uint32_t ATTRIBUTE_PURE MI_CONDITIONAL_BATCH_BUFFER_END_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 3; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_CONDITIONAL_BATCH_BUFFER_END::Command Type */ #define GFX125_MI_CONDITIONAL_BATCH_BUFFER_END_CommandType_bits 3 #define GFX12_MI_CONDITIONAL_BATCH_BUFFER_END_CommandType_bits 3 #define GFX11_MI_CONDITIONAL_BATCH_BUFFER_END_CommandType_bits 3 #define GFX9_MI_CONDITIONAL_BATCH_BUFFER_END_CommandType_bits 3 #define GFX8_MI_CONDITIONAL_BATCH_BUFFER_END_CommandType_bits 3 #define GFX75_MI_CONDITIONAL_BATCH_BUFFER_END_CommandType_bits 3 #define GFX7_MI_CONDITIONAL_BATCH_BUFFER_END_CommandType_bits 3 #define GFX6_MI_CONDITIONAL_BATCH_BUFFER_END_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE MI_CONDITIONAL_BATCH_BUFFER_END_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_CONDITIONAL_BATCH_BUFFER_END_CommandType_start 29 #define GFX12_MI_CONDITIONAL_BATCH_BUFFER_END_CommandType_start 29 #define GFX11_MI_CONDITIONAL_BATCH_BUFFER_END_CommandType_start 29 #define GFX9_MI_CONDITIONAL_BATCH_BUFFER_END_CommandType_start 29 #define GFX8_MI_CONDITIONAL_BATCH_BUFFER_END_CommandType_start 29 #define GFX75_MI_CONDITIONAL_BATCH_BUFFER_END_CommandType_start 29 #define GFX7_MI_CONDITIONAL_BATCH_BUFFER_END_CommandType_start 29 #define GFX6_MI_CONDITIONAL_BATCH_BUFFER_END_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE MI_CONDITIONAL_BATCH_BUFFER_END_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 29; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_CONDITIONAL_BATCH_BUFFER_END::Compare Address */ #define GFX125_MI_CONDITIONAL_BATCH_BUFFER_END_CompareAddress_bits 61 #define GFX12_MI_CONDITIONAL_BATCH_BUFFER_END_CompareAddress_bits 61 #define GFX11_MI_CONDITIONAL_BATCH_BUFFER_END_CompareAddress_bits 61 #define GFX9_MI_CONDITIONAL_BATCH_BUFFER_END_CompareAddress_bits 61 #define GFX8_MI_CONDITIONAL_BATCH_BUFFER_END_CompareAddress_bits 45 #define GFX75_MI_CONDITIONAL_BATCH_BUFFER_END_CompareAddress_bits 29 #define GFX7_MI_CONDITIONAL_BATCH_BUFFER_END_CompareAddress_bits 29 #define GFX6_MI_CONDITIONAL_BATCH_BUFFER_END_CompareAddress_bits 29 static inline uint32_t ATTRIBUTE_PURE MI_CONDITIONAL_BATCH_BUFFER_END_CompareAddress_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 61; case 120: return 61; case 110: return 61; case 90: return 61; case 80: return 45; case 75: return 29; case 70: return 29; case 60: return 29; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_CONDITIONAL_BATCH_BUFFER_END_CompareAddress_start 67 #define GFX12_MI_CONDITIONAL_BATCH_BUFFER_END_CompareAddress_start 67 #define GFX11_MI_CONDITIONAL_BATCH_BUFFER_END_CompareAddress_start 67 #define GFX9_MI_CONDITIONAL_BATCH_BUFFER_END_CompareAddress_start 67 #define GFX8_MI_CONDITIONAL_BATCH_BUFFER_END_CompareAddress_start 67 #define GFX75_MI_CONDITIONAL_BATCH_BUFFER_END_CompareAddress_start 67 #define GFX7_MI_CONDITIONAL_BATCH_BUFFER_END_CompareAddress_start 67 #define GFX6_MI_CONDITIONAL_BATCH_BUFFER_END_CompareAddress_start 67 static inline uint32_t ATTRIBUTE_PURE MI_CONDITIONAL_BATCH_BUFFER_END_CompareAddress_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 67; case 120: return 67; case 110: return 67; case 90: return 67; case 80: return 67; case 75: return 67; case 70: return 67; case 60: return 67; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_CONDITIONAL_BATCH_BUFFER_END::Compare Data Dword */ #define GFX125_MI_CONDITIONAL_BATCH_BUFFER_END_CompareDataDword_bits 32 #define GFX12_MI_CONDITIONAL_BATCH_BUFFER_END_CompareDataDword_bits 32 #define GFX11_MI_CONDITIONAL_BATCH_BUFFER_END_CompareDataDword_bits 32 #define GFX9_MI_CONDITIONAL_BATCH_BUFFER_END_CompareDataDword_bits 32 #define GFX8_MI_CONDITIONAL_BATCH_BUFFER_END_CompareDataDword_bits 32 #define GFX75_MI_CONDITIONAL_BATCH_BUFFER_END_CompareDataDword_bits 32 #define GFX7_MI_CONDITIONAL_BATCH_BUFFER_END_CompareDataDword_bits 32 #define GFX6_MI_CONDITIONAL_BATCH_BUFFER_END_CompareDataDword_bits 32 static inline uint32_t ATTRIBUTE_PURE MI_CONDITIONAL_BATCH_BUFFER_END_CompareDataDword_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 32; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_CONDITIONAL_BATCH_BUFFER_END_CompareDataDword_start 32 #define GFX12_MI_CONDITIONAL_BATCH_BUFFER_END_CompareDataDword_start 32 #define GFX11_MI_CONDITIONAL_BATCH_BUFFER_END_CompareDataDword_start 32 #define GFX9_MI_CONDITIONAL_BATCH_BUFFER_END_CompareDataDword_start 32 #define GFX8_MI_CONDITIONAL_BATCH_BUFFER_END_CompareDataDword_start 32 #define GFX75_MI_CONDITIONAL_BATCH_BUFFER_END_CompareDataDword_start 32 #define GFX7_MI_CONDITIONAL_BATCH_BUFFER_END_CompareDataDword_start 32 #define GFX6_MI_CONDITIONAL_BATCH_BUFFER_END_CompareDataDword_start 32 static inline uint32_t ATTRIBUTE_PURE MI_CONDITIONAL_BATCH_BUFFER_END_CompareDataDword_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 32; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_CONDITIONAL_BATCH_BUFFER_END::Compare Mask Mode */ #define GFX125_MI_CONDITIONAL_BATCH_BUFFER_END_CompareMaskMode_bits 1 #define GFX12_MI_CONDITIONAL_BATCH_BUFFER_END_CompareMaskMode_bits 1 #define GFX11_MI_CONDITIONAL_BATCH_BUFFER_END_CompareMaskMode_bits 1 #define GFX9_MI_CONDITIONAL_BATCH_BUFFER_END_CompareMaskMode_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_CONDITIONAL_BATCH_BUFFER_END_CompareMaskMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_CONDITIONAL_BATCH_BUFFER_END_CompareMaskMode_start 19 #define GFX12_MI_CONDITIONAL_BATCH_BUFFER_END_CompareMaskMode_start 19 #define GFX11_MI_CONDITIONAL_BATCH_BUFFER_END_CompareMaskMode_start 19 #define GFX9_MI_CONDITIONAL_BATCH_BUFFER_END_CompareMaskMode_start 19 static inline uint32_t ATTRIBUTE_PURE MI_CONDITIONAL_BATCH_BUFFER_END_CompareMaskMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 19; case 120: return 19; case 110: return 19; case 90: return 19; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_CONDITIONAL_BATCH_BUFFER_END::Compare Semaphore */ #define GFX125_MI_CONDITIONAL_BATCH_BUFFER_END_CompareSemaphore_bits 1 #define GFX12_MI_CONDITIONAL_BATCH_BUFFER_END_CompareSemaphore_bits 1 #define GFX11_MI_CONDITIONAL_BATCH_BUFFER_END_CompareSemaphore_bits 1 #define GFX9_MI_CONDITIONAL_BATCH_BUFFER_END_CompareSemaphore_bits 1 #define GFX8_MI_CONDITIONAL_BATCH_BUFFER_END_CompareSemaphore_bits 1 #define GFX75_MI_CONDITIONAL_BATCH_BUFFER_END_CompareSemaphore_bits 1 #define GFX7_MI_CONDITIONAL_BATCH_BUFFER_END_CompareSemaphore_bits 1 #define GFX6_MI_CONDITIONAL_BATCH_BUFFER_END_CompareSemaphore_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_CONDITIONAL_BATCH_BUFFER_END_CompareSemaphore_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_CONDITIONAL_BATCH_BUFFER_END_CompareSemaphore_start 21 #define GFX12_MI_CONDITIONAL_BATCH_BUFFER_END_CompareSemaphore_start 21 #define GFX11_MI_CONDITIONAL_BATCH_BUFFER_END_CompareSemaphore_start 21 #define GFX9_MI_CONDITIONAL_BATCH_BUFFER_END_CompareSemaphore_start 21 #define GFX8_MI_CONDITIONAL_BATCH_BUFFER_END_CompareSemaphore_start 21 #define GFX75_MI_CONDITIONAL_BATCH_BUFFER_END_CompareSemaphore_start 21 #define GFX7_MI_CONDITIONAL_BATCH_BUFFER_END_CompareSemaphore_start 21 #define GFX6_MI_CONDITIONAL_BATCH_BUFFER_END_CompareSemaphore_start 21 static inline uint32_t ATTRIBUTE_PURE MI_CONDITIONAL_BATCH_BUFFER_END_CompareSemaphore_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 21; case 120: return 21; case 110: return 21; case 90: return 21; case 80: return 21; case 75: return 21; case 70: return 21; case 60: return 21; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_CONDITIONAL_BATCH_BUFFER_END::DWord Length */ #define GFX125_MI_CONDITIONAL_BATCH_BUFFER_END_DWordLength_bits 8 #define GFX12_MI_CONDITIONAL_BATCH_BUFFER_END_DWordLength_bits 8 #define GFX11_MI_CONDITIONAL_BATCH_BUFFER_END_DWordLength_bits 8 #define GFX9_MI_CONDITIONAL_BATCH_BUFFER_END_DWordLength_bits 8 #define GFX8_MI_CONDITIONAL_BATCH_BUFFER_END_DWordLength_bits 8 #define GFX75_MI_CONDITIONAL_BATCH_BUFFER_END_DWordLength_bits 8 #define GFX7_MI_CONDITIONAL_BATCH_BUFFER_END_DWordLength_bits 8 #define GFX6_MI_CONDITIONAL_BATCH_BUFFER_END_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE MI_CONDITIONAL_BATCH_BUFFER_END_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_CONDITIONAL_BATCH_BUFFER_END_DWordLength_start 0 #define GFX12_MI_CONDITIONAL_BATCH_BUFFER_END_DWordLength_start 0 #define GFX11_MI_CONDITIONAL_BATCH_BUFFER_END_DWordLength_start 0 #define GFX9_MI_CONDITIONAL_BATCH_BUFFER_END_DWordLength_start 0 #define GFX8_MI_CONDITIONAL_BATCH_BUFFER_END_DWordLength_start 0 #define GFX75_MI_CONDITIONAL_BATCH_BUFFER_END_DWordLength_start 0 #define GFX7_MI_CONDITIONAL_BATCH_BUFFER_END_DWordLength_start 0 #define GFX6_MI_CONDITIONAL_BATCH_BUFFER_END_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE MI_CONDITIONAL_BATCH_BUFFER_END_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_CONDITIONAL_BATCH_BUFFER_END::MI Command Opcode */ #define GFX125_MI_CONDITIONAL_BATCH_BUFFER_END_MICommandOpcode_bits 6 #define GFX12_MI_CONDITIONAL_BATCH_BUFFER_END_MICommandOpcode_bits 6 #define GFX11_MI_CONDITIONAL_BATCH_BUFFER_END_MICommandOpcode_bits 6 #define GFX9_MI_CONDITIONAL_BATCH_BUFFER_END_MICommandOpcode_bits 6 #define GFX8_MI_CONDITIONAL_BATCH_BUFFER_END_MICommandOpcode_bits 6 #define GFX75_MI_CONDITIONAL_BATCH_BUFFER_END_MICommandOpcode_bits 6 #define GFX7_MI_CONDITIONAL_BATCH_BUFFER_END_MICommandOpcode_bits 6 #define GFX6_MI_CONDITIONAL_BATCH_BUFFER_END_MICommandOpcode_bits 6 static inline uint32_t ATTRIBUTE_PURE MI_CONDITIONAL_BATCH_BUFFER_END_MICommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 6; case 60: return 6; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_CONDITIONAL_BATCH_BUFFER_END_MICommandOpcode_start 23 #define GFX12_MI_CONDITIONAL_BATCH_BUFFER_END_MICommandOpcode_start 23 #define GFX11_MI_CONDITIONAL_BATCH_BUFFER_END_MICommandOpcode_start 23 #define GFX9_MI_CONDITIONAL_BATCH_BUFFER_END_MICommandOpcode_start 23 #define GFX8_MI_CONDITIONAL_BATCH_BUFFER_END_MICommandOpcode_start 23 #define GFX75_MI_CONDITIONAL_BATCH_BUFFER_END_MICommandOpcode_start 23 #define GFX7_MI_CONDITIONAL_BATCH_BUFFER_END_MICommandOpcode_start 23 #define GFX6_MI_CONDITIONAL_BATCH_BUFFER_END_MICommandOpcode_start 23 static inline uint32_t ATTRIBUTE_PURE MI_CONDITIONAL_BATCH_BUFFER_END_MICommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 23; case 120: return 23; case 110: return 23; case 90: return 23; case 80: return 23; case 75: return 23; case 70: return 23; case 60: return 23; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_CONDITIONAL_BATCH_BUFFER_END::Use Global GTT */ #define GFX125_MI_CONDITIONAL_BATCH_BUFFER_END_UseGlobalGTT_bits 1 #define GFX12_MI_CONDITIONAL_BATCH_BUFFER_END_UseGlobalGTT_bits 1 #define GFX11_MI_CONDITIONAL_BATCH_BUFFER_END_UseGlobalGTT_bits 1 #define GFX9_MI_CONDITIONAL_BATCH_BUFFER_END_UseGlobalGTT_bits 1 #define GFX8_MI_CONDITIONAL_BATCH_BUFFER_END_UseGlobalGTT_bits 1 #define GFX75_MI_CONDITIONAL_BATCH_BUFFER_END_UseGlobalGTT_bits 1 #define GFX7_MI_CONDITIONAL_BATCH_BUFFER_END_UseGlobalGTT_bits 1 #define GFX6_MI_CONDITIONAL_BATCH_BUFFER_END_UseGlobalGTT_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_CONDITIONAL_BATCH_BUFFER_END_UseGlobalGTT_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_CONDITIONAL_BATCH_BUFFER_END_UseGlobalGTT_start 22 #define GFX12_MI_CONDITIONAL_BATCH_BUFFER_END_UseGlobalGTT_start 22 #define GFX11_MI_CONDITIONAL_BATCH_BUFFER_END_UseGlobalGTT_start 22 #define GFX9_MI_CONDITIONAL_BATCH_BUFFER_END_UseGlobalGTT_start 22 #define GFX8_MI_CONDITIONAL_BATCH_BUFFER_END_UseGlobalGTT_start 22 #define GFX75_MI_CONDITIONAL_BATCH_BUFFER_END_UseGlobalGTT_start 22 #define GFX7_MI_CONDITIONAL_BATCH_BUFFER_END_UseGlobalGTT_start 22 #define GFX6_MI_CONDITIONAL_BATCH_BUFFER_END_UseGlobalGTT_start 22 static inline uint32_t ATTRIBUTE_PURE MI_CONDITIONAL_BATCH_BUFFER_END_UseGlobalGTT_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 22; case 120: return 22; case 110: return 22; case 90: return 22; case 80: return 22; case 75: return 22; case 70: return 22; case 60: return 22; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_COPY_MEM_MEM */ #define GFX125_MI_COPY_MEM_MEM_length 5 #define GFX12_MI_COPY_MEM_MEM_length 5 #define GFX11_MI_COPY_MEM_MEM_length 5 #define GFX9_MI_COPY_MEM_MEM_length 5 #define GFX8_MI_COPY_MEM_MEM_length 5 static inline uint32_t ATTRIBUTE_PURE MI_COPY_MEM_MEM_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 5; case 110: return 5; case 90: return 5; case 80: return 5; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_COPY_MEM_MEM::Command Type */ #define GFX125_MI_COPY_MEM_MEM_CommandType_bits 3 #define GFX12_MI_COPY_MEM_MEM_CommandType_bits 3 #define GFX11_MI_COPY_MEM_MEM_CommandType_bits 3 #define GFX9_MI_COPY_MEM_MEM_CommandType_bits 3 #define GFX8_MI_COPY_MEM_MEM_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE MI_COPY_MEM_MEM_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_COPY_MEM_MEM_CommandType_start 29 #define GFX12_MI_COPY_MEM_MEM_CommandType_start 29 #define GFX11_MI_COPY_MEM_MEM_CommandType_start 29 #define GFX9_MI_COPY_MEM_MEM_CommandType_start 29 #define GFX8_MI_COPY_MEM_MEM_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE MI_COPY_MEM_MEM_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_COPY_MEM_MEM::DWord Length */ #define GFX125_MI_COPY_MEM_MEM_DWordLength_bits 8 #define GFX12_MI_COPY_MEM_MEM_DWordLength_bits 8 #define GFX11_MI_COPY_MEM_MEM_DWordLength_bits 8 #define GFX9_MI_COPY_MEM_MEM_DWordLength_bits 8 #define GFX8_MI_COPY_MEM_MEM_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE MI_COPY_MEM_MEM_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_COPY_MEM_MEM_DWordLength_start 0 #define GFX12_MI_COPY_MEM_MEM_DWordLength_start 0 #define GFX11_MI_COPY_MEM_MEM_DWordLength_start 0 #define GFX9_MI_COPY_MEM_MEM_DWordLength_start 0 #define GFX8_MI_COPY_MEM_MEM_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE MI_COPY_MEM_MEM_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_COPY_MEM_MEM::Destination Memory Address */ #define GFX125_MI_COPY_MEM_MEM_DestinationMemoryAddress_bits 62 #define GFX12_MI_COPY_MEM_MEM_DestinationMemoryAddress_bits 62 #define GFX11_MI_COPY_MEM_MEM_DestinationMemoryAddress_bits 62 #define GFX9_MI_COPY_MEM_MEM_DestinationMemoryAddress_bits 62 #define GFX8_MI_COPY_MEM_MEM_DestinationMemoryAddress_bits 62 static inline uint32_t ATTRIBUTE_PURE MI_COPY_MEM_MEM_DestinationMemoryAddress_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 62; case 120: return 62; case 110: return 62; case 90: return 62; case 80: return 62; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_COPY_MEM_MEM_DestinationMemoryAddress_start 34 #define GFX12_MI_COPY_MEM_MEM_DestinationMemoryAddress_start 34 #define GFX11_MI_COPY_MEM_MEM_DestinationMemoryAddress_start 34 #define GFX9_MI_COPY_MEM_MEM_DestinationMemoryAddress_start 34 #define GFX8_MI_COPY_MEM_MEM_DestinationMemoryAddress_start 34 static inline uint32_t ATTRIBUTE_PURE MI_COPY_MEM_MEM_DestinationMemoryAddress_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 34; case 120: return 34; case 110: return 34; case 90: return 34; case 80: return 34; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_COPY_MEM_MEM::MI Command Opcode */ #define GFX125_MI_COPY_MEM_MEM_MICommandOpcode_bits 6 #define GFX12_MI_COPY_MEM_MEM_MICommandOpcode_bits 6 #define GFX11_MI_COPY_MEM_MEM_MICommandOpcode_bits 6 #define GFX9_MI_COPY_MEM_MEM_MICommandOpcode_bits 6 #define GFX8_MI_COPY_MEM_MEM_MICommandOpcode_bits 6 static inline uint32_t ATTRIBUTE_PURE MI_COPY_MEM_MEM_MICommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_COPY_MEM_MEM_MICommandOpcode_start 23 #define GFX12_MI_COPY_MEM_MEM_MICommandOpcode_start 23 #define GFX11_MI_COPY_MEM_MEM_MICommandOpcode_start 23 #define GFX9_MI_COPY_MEM_MEM_MICommandOpcode_start 23 #define GFX8_MI_COPY_MEM_MEM_MICommandOpcode_start 23 static inline uint32_t ATTRIBUTE_PURE MI_COPY_MEM_MEM_MICommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 23; case 120: return 23; case 110: return 23; case 90: return 23; case 80: return 23; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_COPY_MEM_MEM::Source Memory Address */ #define GFX125_MI_COPY_MEM_MEM_SourceMemoryAddress_bits 62 #define GFX12_MI_COPY_MEM_MEM_SourceMemoryAddress_bits 62 #define GFX11_MI_COPY_MEM_MEM_SourceMemoryAddress_bits 62 #define GFX9_MI_COPY_MEM_MEM_SourceMemoryAddress_bits 62 #define GFX8_MI_COPY_MEM_MEM_SourceMemoryAddress_bits 62 static inline uint32_t ATTRIBUTE_PURE MI_COPY_MEM_MEM_SourceMemoryAddress_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 62; case 120: return 62; case 110: return 62; case 90: return 62; case 80: return 62; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_COPY_MEM_MEM_SourceMemoryAddress_start 98 #define GFX12_MI_COPY_MEM_MEM_SourceMemoryAddress_start 98 #define GFX11_MI_COPY_MEM_MEM_SourceMemoryAddress_start 98 #define GFX9_MI_COPY_MEM_MEM_SourceMemoryAddress_start 98 #define GFX8_MI_COPY_MEM_MEM_SourceMemoryAddress_start 98 static inline uint32_t ATTRIBUTE_PURE MI_COPY_MEM_MEM_SourceMemoryAddress_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 98; case 120: return 98; case 110: return 98; case 90: return 98; case 80: return 98; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_COPY_MEM_MEM::Use Global GTT Destination */ #define GFX125_MI_COPY_MEM_MEM_UseGlobalGTTDestination_bits 1 #define GFX12_MI_COPY_MEM_MEM_UseGlobalGTTDestination_bits 1 #define GFX11_MI_COPY_MEM_MEM_UseGlobalGTTDestination_bits 1 #define GFX9_MI_COPY_MEM_MEM_UseGlobalGTTDestination_bits 1 #define GFX8_MI_COPY_MEM_MEM_UseGlobalGTTDestination_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_COPY_MEM_MEM_UseGlobalGTTDestination_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_COPY_MEM_MEM_UseGlobalGTTDestination_start 21 #define GFX12_MI_COPY_MEM_MEM_UseGlobalGTTDestination_start 21 #define GFX11_MI_COPY_MEM_MEM_UseGlobalGTTDestination_start 21 #define GFX9_MI_COPY_MEM_MEM_UseGlobalGTTDestination_start 21 #define GFX8_MI_COPY_MEM_MEM_UseGlobalGTTDestination_start 21 static inline uint32_t ATTRIBUTE_PURE MI_COPY_MEM_MEM_UseGlobalGTTDestination_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 21; case 120: return 21; case 110: return 21; case 90: return 21; case 80: return 21; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_COPY_MEM_MEM::Use Global GTT Source */ #define GFX125_MI_COPY_MEM_MEM_UseGlobalGTTSource_bits 1 #define GFX12_MI_COPY_MEM_MEM_UseGlobalGTTSource_bits 1 #define GFX11_MI_COPY_MEM_MEM_UseGlobalGTTSource_bits 1 #define GFX9_MI_COPY_MEM_MEM_UseGlobalGTTSource_bits 1 #define GFX8_MI_COPY_MEM_MEM_UseGlobalGTTSource_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_COPY_MEM_MEM_UseGlobalGTTSource_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_COPY_MEM_MEM_UseGlobalGTTSource_start 22 #define GFX12_MI_COPY_MEM_MEM_UseGlobalGTTSource_start 22 #define GFX11_MI_COPY_MEM_MEM_UseGlobalGTTSource_start 22 #define GFX9_MI_COPY_MEM_MEM_UseGlobalGTTSource_start 22 #define GFX8_MI_COPY_MEM_MEM_UseGlobalGTTSource_start 22 static inline uint32_t ATTRIBUTE_PURE MI_COPY_MEM_MEM_UseGlobalGTTSource_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 22; case 120: return 22; case 110: return 22; case 90: return 22; case 80: return 22; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_DISPLAY_FLIP */ #define GFX125_MI_DISPLAY_FLIP_length 3 #define GFX12_MI_DISPLAY_FLIP_length 3 #define GFX11_MI_DISPLAY_FLIP_length 3 #define GFX9_MI_DISPLAY_FLIP_length 3 static inline uint32_t ATTRIBUTE_PURE MI_DISPLAY_FLIP_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_DISPLAY_FLIP::Async Flip Indicator */ #define GFX125_MI_DISPLAY_FLIP_AsyncFlipIndicator_bits 1 #define GFX12_MI_DISPLAY_FLIP_AsyncFlipIndicator_bits 1 #define GFX11_MI_DISPLAY_FLIP_AsyncFlipIndicator_bits 1 #define GFX9_MI_DISPLAY_FLIP_AsyncFlipIndicator_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_DISPLAY_FLIP_AsyncFlipIndicator_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_DISPLAY_FLIP_AsyncFlipIndicator_start 22 #define GFX12_MI_DISPLAY_FLIP_AsyncFlipIndicator_start 22 #define GFX11_MI_DISPLAY_FLIP_AsyncFlipIndicator_start 22 #define GFX9_MI_DISPLAY_FLIP_AsyncFlipIndicator_start 22 static inline uint32_t ATTRIBUTE_PURE MI_DISPLAY_FLIP_AsyncFlipIndicator_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 22; case 120: return 22; case 110: return 22; case 90: return 22; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_DISPLAY_FLIP::Command Type */ #define GFX125_MI_DISPLAY_FLIP_CommandType_bits 3 #define GFX12_MI_DISPLAY_FLIP_CommandType_bits 3 #define GFX11_MI_DISPLAY_FLIP_CommandType_bits 3 #define GFX9_MI_DISPLAY_FLIP_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE MI_DISPLAY_FLIP_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_DISPLAY_FLIP_CommandType_start 29 #define GFX12_MI_DISPLAY_FLIP_CommandType_start 29 #define GFX11_MI_DISPLAY_FLIP_CommandType_start 29 #define GFX9_MI_DISPLAY_FLIP_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE MI_DISPLAY_FLIP_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_DISPLAY_FLIP::DWord Length */ #define GFX125_MI_DISPLAY_FLIP_DWordLength_bits 8 #define GFX12_MI_DISPLAY_FLIP_DWordLength_bits 8 #define GFX11_MI_DISPLAY_FLIP_DWordLength_bits 8 #define GFX9_MI_DISPLAY_FLIP_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE MI_DISPLAY_FLIP_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_DISPLAY_FLIP_DWordLength_start 0 #define GFX12_MI_DISPLAY_FLIP_DWordLength_start 0 #define GFX11_MI_DISPLAY_FLIP_DWordLength_start 0 #define GFX9_MI_DISPLAY_FLIP_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE MI_DISPLAY_FLIP_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_DISPLAY_FLIP::Display Buffer Base Address */ #define GFX125_MI_DISPLAY_FLIP_DisplayBufferBaseAddress_bits 20 #define GFX12_MI_DISPLAY_FLIP_DisplayBufferBaseAddress_bits 20 #define GFX11_MI_DISPLAY_FLIP_DisplayBufferBaseAddress_bits 20 #define GFX9_MI_DISPLAY_FLIP_DisplayBufferBaseAddress_bits 20 static inline uint32_t ATTRIBUTE_PURE MI_DISPLAY_FLIP_DisplayBufferBaseAddress_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 20; case 120: return 20; case 110: return 20; case 90: return 20; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_DISPLAY_FLIP_DisplayBufferBaseAddress_start 76 #define GFX12_MI_DISPLAY_FLIP_DisplayBufferBaseAddress_start 76 #define GFX11_MI_DISPLAY_FLIP_DisplayBufferBaseAddress_start 76 #define GFX9_MI_DISPLAY_FLIP_DisplayBufferBaseAddress_start 76 static inline uint32_t ATTRIBUTE_PURE MI_DISPLAY_FLIP_DisplayBufferBaseAddress_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 76; case 120: return 76; case 110: return 76; case 90: return 76; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_DISPLAY_FLIP::Display Buffer Pitch */ #define GFX125_MI_DISPLAY_FLIP_DisplayBufferPitch_bits 10 #define GFX12_MI_DISPLAY_FLIP_DisplayBufferPitch_bits 10 #define GFX11_MI_DISPLAY_FLIP_DisplayBufferPitch_bits 10 #define GFX9_MI_DISPLAY_FLIP_DisplayBufferPitch_bits 10 static inline uint32_t ATTRIBUTE_PURE MI_DISPLAY_FLIP_DisplayBufferPitch_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 10; case 120: return 10; case 110: return 10; case 90: return 10; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_DISPLAY_FLIP_DisplayBufferPitch_start 38 #define GFX12_MI_DISPLAY_FLIP_DisplayBufferPitch_start 38 #define GFX11_MI_DISPLAY_FLIP_DisplayBufferPitch_start 38 #define GFX9_MI_DISPLAY_FLIP_DisplayBufferPitch_start 38 static inline uint32_t ATTRIBUTE_PURE MI_DISPLAY_FLIP_DisplayBufferPitch_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 38; case 120: return 38; case 110: return 38; case 90: return 38; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_DISPLAY_FLIP::Display Plane Select */ #define GFX125_MI_DISPLAY_FLIP_DisplayPlaneSelect_bits 6 #define GFX12_MI_DISPLAY_FLIP_DisplayPlaneSelect_bits 6 #define GFX11_MI_DISPLAY_FLIP_DisplayPlaneSelect_bits 6 #define GFX9_MI_DISPLAY_FLIP_DisplayPlaneSelect_bits 5 static inline uint32_t ATTRIBUTE_PURE MI_DISPLAY_FLIP_DisplayPlaneSelect_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 5; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_DISPLAY_FLIP_DisplayPlaneSelect_start 8 #define GFX12_MI_DISPLAY_FLIP_DisplayPlaneSelect_start 8 #define GFX11_MI_DISPLAY_FLIP_DisplayPlaneSelect_start 8 #define GFX9_MI_DISPLAY_FLIP_DisplayPlaneSelect_start 8 static inline uint32_t ATTRIBUTE_PURE MI_DISPLAY_FLIP_DisplayPlaneSelect_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_DISPLAY_FLIP::Flip Type */ #define GFX125_MI_DISPLAY_FLIP_FlipType_bits 2 #define GFX12_MI_DISPLAY_FLIP_FlipType_bits 2 #define GFX11_MI_DISPLAY_FLIP_FlipType_bits 2 #define GFX9_MI_DISPLAY_FLIP_FlipType_bits 2 static inline uint32_t ATTRIBUTE_PURE MI_DISPLAY_FLIP_FlipType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_DISPLAY_FLIP_FlipType_start 64 #define GFX12_MI_DISPLAY_FLIP_FlipType_start 64 #define GFX11_MI_DISPLAY_FLIP_FlipType_start 64 #define GFX9_MI_DISPLAY_FLIP_FlipType_start 64 static inline uint32_t ATTRIBUTE_PURE MI_DISPLAY_FLIP_FlipType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 64; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_DISPLAY_FLIP::Left Eye Display Buffer Base Address */ #define GFX125_MI_DISPLAY_FLIP_LeftEyeDisplayBufferBaseAddress_bits 20 #define GFX12_MI_DISPLAY_FLIP_LeftEyeDisplayBufferBaseAddress_bits 20 #define GFX11_MI_DISPLAY_FLIP_LeftEyeDisplayBufferBaseAddress_bits 20 #define GFX9_MI_DISPLAY_FLIP_LeftEyeDisplayBufferBaseAddress_bits 20 static inline uint32_t ATTRIBUTE_PURE MI_DISPLAY_FLIP_LeftEyeDisplayBufferBaseAddress_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 20; case 120: return 20; case 110: return 20; case 90: return 20; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_DISPLAY_FLIP_LeftEyeDisplayBufferBaseAddress_start 108 #define GFX12_MI_DISPLAY_FLIP_LeftEyeDisplayBufferBaseAddress_start 108 #define GFX11_MI_DISPLAY_FLIP_LeftEyeDisplayBufferBaseAddress_start 108 #define GFX9_MI_DISPLAY_FLIP_LeftEyeDisplayBufferBaseAddress_start 108 static inline uint32_t ATTRIBUTE_PURE MI_DISPLAY_FLIP_LeftEyeDisplayBufferBaseAddress_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 108; case 120: return 108; case 110: return 108; case 90: return 108; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_DISPLAY_FLIP::MI Command Opcode */ #define GFX125_MI_DISPLAY_FLIP_MICommandOpcode_bits 6 #define GFX12_MI_DISPLAY_FLIP_MICommandOpcode_bits 6 #define GFX11_MI_DISPLAY_FLIP_MICommandOpcode_bits 6 #define GFX9_MI_DISPLAY_FLIP_MICommandOpcode_bits 6 static inline uint32_t ATTRIBUTE_PURE MI_DISPLAY_FLIP_MICommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_DISPLAY_FLIP_MICommandOpcode_start 23 #define GFX12_MI_DISPLAY_FLIP_MICommandOpcode_start 23 #define GFX11_MI_DISPLAY_FLIP_MICommandOpcode_start 23 #define GFX9_MI_DISPLAY_FLIP_MICommandOpcode_start 23 static inline uint32_t ATTRIBUTE_PURE MI_DISPLAY_FLIP_MICommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 23; case 120: return 23; case 110: return 23; case 90: return 23; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_DISPLAY_FLIP::Stereoscopic 3D Mode */ #define GFX125_MI_DISPLAY_FLIP_Stereoscopic3DMode_bits 1 #define GFX12_MI_DISPLAY_FLIP_Stereoscopic3DMode_bits 1 #define GFX11_MI_DISPLAY_FLIP_Stereoscopic3DMode_bits 1 #define GFX9_MI_DISPLAY_FLIP_Stereoscopic3DMode_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_DISPLAY_FLIP_Stereoscopic3DMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_DISPLAY_FLIP_Stereoscopic3DMode_start 63 #define GFX12_MI_DISPLAY_FLIP_Stereoscopic3DMode_start 63 #define GFX11_MI_DISPLAY_FLIP_Stereoscopic3DMode_start 63 #define GFX9_MI_DISPLAY_FLIP_Stereoscopic3DMode_start 63 static inline uint32_t ATTRIBUTE_PURE MI_DISPLAY_FLIP_Stereoscopic3DMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 63; case 120: return 63; case 110: return 63; case 90: return 63; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_DISPLAY_FLIP::Tile Parameter */ #define GFX125_MI_DISPLAY_FLIP_TileParameter_bits 3 #define GFX12_MI_DISPLAY_FLIP_TileParameter_bits 3 #define GFX11_MI_DISPLAY_FLIP_TileParameter_bits 3 #define GFX9_MI_DISPLAY_FLIP_TileParameter_bits 3 static inline uint32_t ATTRIBUTE_PURE MI_DISPLAY_FLIP_TileParameter_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_DISPLAY_FLIP_TileParameter_start 32 #define GFX12_MI_DISPLAY_FLIP_TileParameter_start 32 #define GFX11_MI_DISPLAY_FLIP_TileParameter_start 32 #define GFX9_MI_DISPLAY_FLIP_TileParameter_start 32 static inline uint32_t ATTRIBUTE_PURE MI_DISPLAY_FLIP_TileParameter_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_DISPLAY_FLIP::VRR Master Flip */ #define GFX125_MI_DISPLAY_FLIP_VRRMasterFlip_bits 1 #define GFX12_MI_DISPLAY_FLIP_VRRMasterFlip_bits 1 #define GFX11_MI_DISPLAY_FLIP_VRRMasterFlip_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_DISPLAY_FLIP_VRRMasterFlip_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_DISPLAY_FLIP_VRRMasterFlip_start 75 #define GFX12_MI_DISPLAY_FLIP_VRRMasterFlip_start 75 #define GFX11_MI_DISPLAY_FLIP_VRRMasterFlip_start 75 static inline uint32_t ATTRIBUTE_PURE MI_DISPLAY_FLIP_VRRMasterFlip_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 75; case 120: return 75; case 110: return 75; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_FLUSH */ #define GFX75_MI_FLUSH_length 1 #define GFX7_MI_FLUSH_length 1 #define GFX6_MI_FLUSH_length 1 #define GFX5_MI_FLUSH_length 1 #define GFX45_MI_FLUSH_length 1 #define GFX4_MI_FLUSH_length 1 static inline uint32_t ATTRIBUTE_PURE MI_FLUSH_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } /* MI_FLUSH::Command Type */ #define GFX75_MI_FLUSH_CommandType_bits 3 #define GFX7_MI_FLUSH_CommandType_bits 3 #define GFX6_MI_FLUSH_CommandType_bits 3 #define GFX5_MI_FLUSH_CommandType_bits 3 #define GFX45_MI_FLUSH_CommandType_bits 3 #define GFX4_MI_FLUSH_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE MI_FLUSH_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX75_MI_FLUSH_CommandType_start 29 #define GFX7_MI_FLUSH_CommandType_start 29 #define GFX6_MI_FLUSH_CommandType_start 29 #define GFX5_MI_FLUSH_CommandType_start 29 #define GFX45_MI_FLUSH_CommandType_start 29 #define GFX4_MI_FLUSH_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE MI_FLUSH_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 29; case 70: return 29; case 60: return 29; case 50: return 29; case 45: return 29; case 40: return 29; default: unreachable("Invalid hardware generation"); } } /* MI_FLUSH::Generic Media State Clear */ #define GFX75_MI_FLUSH_GenericMediaStateClear_bits 1 #define GFX7_MI_FLUSH_GenericMediaStateClear_bits 1 #define GFX6_MI_FLUSH_GenericMediaStateClear_bits 1 #define GFX5_MI_FLUSH_GenericMediaStateClear_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_FLUSH_GenericMediaStateClear_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 1; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_MI_FLUSH_GenericMediaStateClear_start 4 #define GFX7_MI_FLUSH_GenericMediaStateClear_start 4 #define GFX6_MI_FLUSH_GenericMediaStateClear_start 4 #define GFX5_MI_FLUSH_GenericMediaStateClear_start 4 static inline uint32_t ATTRIBUTE_PURE MI_FLUSH_GenericMediaStateClear_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 4; case 70: return 4; case 60: return 4; case 50: return 4; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_FLUSH::Global Snapshot Count Reset */ #define GFX75_MI_FLUSH_GlobalSnapshotCountReset_bits 1 #define GFX7_MI_FLUSH_GlobalSnapshotCountReset_bits 1 #define GFX6_MI_FLUSH_GlobalSnapshotCountReset_bits 1 #define GFX5_MI_FLUSH_GlobalSnapshotCountReset_bits 1 #define GFX45_MI_FLUSH_GlobalSnapshotCountReset_bits 1 #define GFX4_MI_FLUSH_GlobalSnapshotCountReset_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_FLUSH_GlobalSnapshotCountReset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX75_MI_FLUSH_GlobalSnapshotCountReset_start 3 #define GFX7_MI_FLUSH_GlobalSnapshotCountReset_start 3 #define GFX6_MI_FLUSH_GlobalSnapshotCountReset_start 3 #define GFX5_MI_FLUSH_GlobalSnapshotCountReset_start 3 #define GFX45_MI_FLUSH_GlobalSnapshotCountReset_start 3 #define GFX4_MI_FLUSH_GlobalSnapshotCountReset_start 3 static inline uint32_t ATTRIBUTE_PURE MI_FLUSH_GlobalSnapshotCountReset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } /* MI_FLUSH::Indirect State Pointers Disable */ #define GFX75_MI_FLUSH_IndirectStatePointersDisable_bits 1 #define GFX7_MI_FLUSH_IndirectStatePointersDisable_bits 1 #define GFX6_MI_FLUSH_IndirectStatePointersDisable_bits 1 #define GFX5_MI_FLUSH_IndirectStatePointersDisable_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_FLUSH_IndirectStatePointersDisable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 1; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_MI_FLUSH_IndirectStatePointersDisable_start 5 #define GFX7_MI_FLUSH_IndirectStatePointersDisable_start 5 #define GFX6_MI_FLUSH_IndirectStatePointersDisable_start 5 #define GFX5_MI_FLUSH_IndirectStatePointersDisable_start 5 static inline uint32_t ATTRIBUTE_PURE MI_FLUSH_IndirectStatePointersDisable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 5; case 70: return 5; case 60: return 5; case 50: return 5; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_FLUSH::MI Command Opcode */ #define GFX75_MI_FLUSH_MICommandOpcode_bits 6 #define GFX7_MI_FLUSH_MICommandOpcode_bits 6 #define GFX6_MI_FLUSH_MICommandOpcode_bits 6 #define GFX5_MI_FLUSH_MICommandOpcode_bits 6 #define GFX45_MI_FLUSH_MICommandOpcode_bits 6 #define GFX4_MI_FLUSH_MICommandOpcode_bits 6 static inline uint32_t ATTRIBUTE_PURE MI_FLUSH_MICommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 6; case 70: return 6; case 60: return 6; case 50: return 6; case 45: return 6; case 40: return 6; default: unreachable("Invalid hardware generation"); } } #define GFX75_MI_FLUSH_MICommandOpcode_start 23 #define GFX7_MI_FLUSH_MICommandOpcode_start 23 #define GFX6_MI_FLUSH_MICommandOpcode_start 23 #define GFX5_MI_FLUSH_MICommandOpcode_start 23 #define GFX45_MI_FLUSH_MICommandOpcode_start 23 #define GFX4_MI_FLUSH_MICommandOpcode_start 23 static inline uint32_t ATTRIBUTE_PURE MI_FLUSH_MICommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 23; case 70: return 23; case 60: return 23; case 50: return 23; case 45: return 23; case 40: return 23; default: unreachable("Invalid hardware generation"); } } /* MI_FLUSH::Protected Memory Enable */ #define GFX5_MI_FLUSH_ProtectedMemoryEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_FLUSH_ProtectedMemoryEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX5_MI_FLUSH_ProtectedMemoryEnable_start 6 static inline uint32_t ATTRIBUTE_PURE MI_FLUSH_ProtectedMemoryEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 6; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_FLUSH::Render Cache Flush Inhibit */ #define GFX75_MI_FLUSH_RenderCacheFlushInhibit_bits 1 #define GFX7_MI_FLUSH_RenderCacheFlushInhibit_bits 1 #define GFX6_MI_FLUSH_RenderCacheFlushInhibit_bits 1 #define GFX5_MI_FLUSH_RenderCacheFlushInhibit_bits 1 #define GFX45_MI_FLUSH_RenderCacheFlushInhibit_bits 1 #define GFX4_MI_FLUSH_RenderCacheFlushInhibit_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_FLUSH_RenderCacheFlushInhibit_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX75_MI_FLUSH_RenderCacheFlushInhibit_start 2 #define GFX7_MI_FLUSH_RenderCacheFlushInhibit_start 2 #define GFX6_MI_FLUSH_RenderCacheFlushInhibit_start 2 #define GFX5_MI_FLUSH_RenderCacheFlushInhibit_start 2 #define GFX45_MI_FLUSH_RenderCacheFlushInhibit_start 2 #define GFX4_MI_FLUSH_RenderCacheFlushInhibit_start 2 static inline uint32_t ATTRIBUTE_PURE MI_FLUSH_RenderCacheFlushInhibit_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 2; case 45: return 2; case 40: return 2; default: unreachable("Invalid hardware generation"); } } /* MI_FLUSH::State/Instruction Cache Invalidate */ #define GFX75_MI_FLUSH_StateInstructionCacheInvalidate_bits 1 #define GFX7_MI_FLUSH_StateInstructionCacheInvalidate_bits 1 #define GFX6_MI_FLUSH_StateInstructionCacheInvalidate_bits 1 #define GFX5_MI_FLUSH_StateInstructionCacheInvalidate_bits 1 #define GFX45_MI_FLUSH_StateInstructionCacheInvalidate_bits 1 #define GFX4_MI_FLUSH_StateInstructionCacheInvalidate_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_FLUSH_StateInstructionCacheInvalidate_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX75_MI_FLUSH_StateInstructionCacheInvalidate_start 1 #define GFX7_MI_FLUSH_StateInstructionCacheInvalidate_start 1 #define GFX6_MI_FLUSH_StateInstructionCacheInvalidate_start 1 #define GFX5_MI_FLUSH_StateInstructionCacheInvalidate_start 1 #define GFX45_MI_FLUSH_StateInstructionCacheInvalidate_start 1 #define GFX4_MI_FLUSH_StateInstructionCacheInvalidate_start 1 static inline uint32_t ATTRIBUTE_PURE MI_FLUSH_StateInstructionCacheInvalidate_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } /* MI_FORCE_WAKEUP */ #define GFX125_MI_FORCE_WAKEUP_length 2 #define GFX12_MI_FORCE_WAKEUP_length 2 #define GFX11_MI_FORCE_WAKEUP_length 2 #define GFX9_MI_FORCE_WAKEUP_length 2 static inline uint32_t ATTRIBUTE_PURE MI_FORCE_WAKEUP_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_FORCE_WAKEUP::Command Type */ #define GFX125_MI_FORCE_WAKEUP_CommandType_bits 3 #define GFX12_MI_FORCE_WAKEUP_CommandType_bits 3 #define GFX11_MI_FORCE_WAKEUP_CommandType_bits 3 #define GFX9_MI_FORCE_WAKEUP_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE MI_FORCE_WAKEUP_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_FORCE_WAKEUP_CommandType_start 29 #define GFX12_MI_FORCE_WAKEUP_CommandType_start 29 #define GFX11_MI_FORCE_WAKEUP_CommandType_start 29 #define GFX9_MI_FORCE_WAKEUP_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE MI_FORCE_WAKEUP_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_FORCE_WAKEUP::DWord Length */ #define GFX125_MI_FORCE_WAKEUP_DWordLength_bits 8 #define GFX12_MI_FORCE_WAKEUP_DWordLength_bits 8 #define GFX11_MI_FORCE_WAKEUP_DWordLength_bits 8 #define GFX9_MI_FORCE_WAKEUP_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE MI_FORCE_WAKEUP_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_FORCE_WAKEUP_DWordLength_start 0 #define GFX12_MI_FORCE_WAKEUP_DWordLength_start 0 #define GFX11_MI_FORCE_WAKEUP_DWordLength_start 0 #define GFX9_MI_FORCE_WAKEUP_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE MI_FORCE_WAKEUP_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_FORCE_WAKEUP::Force Media Awake */ #define GFX9_MI_FORCE_WAKEUP_ForceMediaAwake_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_FORCE_WAKEUP_ForceMediaAwake_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_MI_FORCE_WAKEUP_ForceMediaAwake_start 32 static inline uint32_t ATTRIBUTE_PURE MI_FORCE_WAKEUP_ForceMediaAwake_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 32; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_FORCE_WAKEUP::Force Media-Slice0 Awake */ #define GFX125_MI_FORCE_WAKEUP_ForceMediaSlice0Awake_bits 1 #define GFX12_MI_FORCE_WAKEUP_ForceMediaSlice0Awake_bits 1 #define GFX11_MI_FORCE_WAKEUP_ForceMediaSlice0Awake_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_FORCE_WAKEUP_ForceMediaSlice0Awake_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_FORCE_WAKEUP_ForceMediaSlice0Awake_start 32 #define GFX12_MI_FORCE_WAKEUP_ForceMediaSlice0Awake_start 32 #define GFX11_MI_FORCE_WAKEUP_ForceMediaSlice0Awake_start 32 static inline uint32_t ATTRIBUTE_PURE MI_FORCE_WAKEUP_ForceMediaSlice0Awake_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_FORCE_WAKEUP::Force Media-Slice1 Awake */ #define GFX125_MI_FORCE_WAKEUP_ForceMediaSlice1Awake_bits 1 #define GFX12_MI_FORCE_WAKEUP_ForceMediaSlice1Awake_bits 1 #define GFX11_MI_FORCE_WAKEUP_ForceMediaSlice1Awake_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_FORCE_WAKEUP_ForceMediaSlice1Awake_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_FORCE_WAKEUP_ForceMediaSlice1Awake_start 34 #define GFX12_MI_FORCE_WAKEUP_ForceMediaSlice1Awake_start 34 #define GFX11_MI_FORCE_WAKEUP_ForceMediaSlice1Awake_start 34 static inline uint32_t ATTRIBUTE_PURE MI_FORCE_WAKEUP_ForceMediaSlice1Awake_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 34; case 120: return 34; case 110: return 34; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_FORCE_WAKEUP::Force Media-Slice2 Awake */ #define GFX125_MI_FORCE_WAKEUP_ForceMediaSlice2Awake_bits 1 #define GFX12_MI_FORCE_WAKEUP_ForceMediaSlice2Awake_bits 1 #define GFX11_MI_FORCE_WAKEUP_ForceMediaSlice2Awake_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_FORCE_WAKEUP_ForceMediaSlice2Awake_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_FORCE_WAKEUP_ForceMediaSlice2Awake_start 35 #define GFX12_MI_FORCE_WAKEUP_ForceMediaSlice2Awake_start 35 #define GFX11_MI_FORCE_WAKEUP_ForceMediaSlice2Awake_start 35 static inline uint32_t ATTRIBUTE_PURE MI_FORCE_WAKEUP_ForceMediaSlice2Awake_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 35; case 120: return 35; case 110: return 35; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_FORCE_WAKEUP::Force Media-Slice3 Awake */ #define GFX125_MI_FORCE_WAKEUP_ForceMediaSlice3Awake_bits 1 #define GFX12_MI_FORCE_WAKEUP_ForceMediaSlice3Awake_bits 1 #define GFX11_MI_FORCE_WAKEUP_ForceMediaSlice3Awake_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_FORCE_WAKEUP_ForceMediaSlice3Awake_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_FORCE_WAKEUP_ForceMediaSlice3Awake_start 36 #define GFX12_MI_FORCE_WAKEUP_ForceMediaSlice3Awake_start 36 #define GFX11_MI_FORCE_WAKEUP_ForceMediaSlice3Awake_start 36 static inline uint32_t ATTRIBUTE_PURE MI_FORCE_WAKEUP_ForceMediaSlice3Awake_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 36; case 120: return 36; case 110: return 36; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_FORCE_WAKEUP::Force Render Awake */ #define GFX125_MI_FORCE_WAKEUP_ForceRenderAwake_bits 1 #define GFX12_MI_FORCE_WAKEUP_ForceRenderAwake_bits 1 #define GFX11_MI_FORCE_WAKEUP_ForceRenderAwake_bits 1 #define GFX9_MI_FORCE_WAKEUP_ForceRenderAwake_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_FORCE_WAKEUP_ForceRenderAwake_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_FORCE_WAKEUP_ForceRenderAwake_start 33 #define GFX12_MI_FORCE_WAKEUP_ForceRenderAwake_start 33 #define GFX11_MI_FORCE_WAKEUP_ForceRenderAwake_start 33 #define GFX9_MI_FORCE_WAKEUP_ForceRenderAwake_start 33 static inline uint32_t ATTRIBUTE_PURE MI_FORCE_WAKEUP_ForceRenderAwake_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 33; case 120: return 33; case 110: return 33; case 90: return 33; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_FORCE_WAKEUP::MI Command Opcode */ #define GFX125_MI_FORCE_WAKEUP_MICommandOpcode_bits 6 #define GFX12_MI_FORCE_WAKEUP_MICommandOpcode_bits 6 #define GFX11_MI_FORCE_WAKEUP_MICommandOpcode_bits 6 #define GFX9_MI_FORCE_WAKEUP_MICommandOpcode_bits 6 static inline uint32_t ATTRIBUTE_PURE MI_FORCE_WAKEUP_MICommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_FORCE_WAKEUP_MICommandOpcode_start 23 #define GFX12_MI_FORCE_WAKEUP_MICommandOpcode_start 23 #define GFX11_MI_FORCE_WAKEUP_MICommandOpcode_start 23 #define GFX9_MI_FORCE_WAKEUP_MICommandOpcode_start 23 static inline uint32_t ATTRIBUTE_PURE MI_FORCE_WAKEUP_MICommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 23; case 120: return 23; case 110: return 23; case 90: return 23; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_FORCE_WAKEUP::Mask Bits */ #define GFX125_MI_FORCE_WAKEUP_MaskBits_bits 16 #define GFX12_MI_FORCE_WAKEUP_MaskBits_bits 16 #define GFX11_MI_FORCE_WAKEUP_MaskBits_bits 16 #define GFX9_MI_FORCE_WAKEUP_MaskBits_bits 16 static inline uint32_t ATTRIBUTE_PURE MI_FORCE_WAKEUP_MaskBits_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_FORCE_WAKEUP_MaskBits_start 48 #define GFX12_MI_FORCE_WAKEUP_MaskBits_start 48 #define GFX11_MI_FORCE_WAKEUP_MaskBits_start 48 #define GFX9_MI_FORCE_WAKEUP_MaskBits_start 48 static inline uint32_t ATTRIBUTE_PURE MI_FORCE_WAKEUP_MaskBits_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 48; case 120: return 48; case 110: return 48; case 90: return 48; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_LOAD_REGISTER_IMM */ #define GFX125_MI_LOAD_REGISTER_IMM_length 3 #define GFX12_MI_LOAD_REGISTER_IMM_length 3 #define GFX11_MI_LOAD_REGISTER_IMM_length 3 #define GFX9_MI_LOAD_REGISTER_IMM_length 3 #define GFX8_MI_LOAD_REGISTER_IMM_length 3 #define GFX75_MI_LOAD_REGISTER_IMM_length 3 #define GFX7_MI_LOAD_REGISTER_IMM_length 3 #define GFX6_MI_LOAD_REGISTER_IMM_length 3 #define GFX5_MI_LOAD_REGISTER_IMM_length 3 #define GFX45_MI_LOAD_REGISTER_IMM_length 3 #define GFX4_MI_LOAD_REGISTER_IMM_length 3 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_REGISTER_IMM_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } /* MI_LOAD_REGISTER_IMM::Add CS MMIO Start Offset */ #define GFX125_MI_LOAD_REGISTER_IMM_AddCSMMIOStartOffset_bits 1 #define GFX12_MI_LOAD_REGISTER_IMM_AddCSMMIOStartOffset_bits 1 #define GFX11_MI_LOAD_REGISTER_IMM_AddCSMMIOStartOffset_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_REGISTER_IMM_AddCSMMIOStartOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_LOAD_REGISTER_IMM_AddCSMMIOStartOffset_start 19 #define GFX12_MI_LOAD_REGISTER_IMM_AddCSMMIOStartOffset_start 19 #define GFX11_MI_LOAD_REGISTER_IMM_AddCSMMIOStartOffset_start 19 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_REGISTER_IMM_AddCSMMIOStartOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 19; case 120: return 19; case 110: return 19; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_LOAD_REGISTER_IMM::Byte Write Disables */ #define GFX125_MI_LOAD_REGISTER_IMM_ByteWriteDisables_bits 4 #define GFX12_MI_LOAD_REGISTER_IMM_ByteWriteDisables_bits 4 #define GFX11_MI_LOAD_REGISTER_IMM_ByteWriteDisables_bits 4 #define GFX9_MI_LOAD_REGISTER_IMM_ByteWriteDisables_bits 4 #define GFX8_MI_LOAD_REGISTER_IMM_ByteWriteDisables_bits 4 #define GFX75_MI_LOAD_REGISTER_IMM_ByteWriteDisables_bits 4 #define GFX7_MI_LOAD_REGISTER_IMM_ByteWriteDisables_bits 4 #define GFX6_MI_LOAD_REGISTER_IMM_ByteWriteDisables_bits 4 #define GFX5_MI_LOAD_REGISTER_IMM_ByteWriteDisables_bits 4 #define GFX45_MI_LOAD_REGISTER_IMM_ByteWriteDisables_bits 4 #define GFX4_MI_LOAD_REGISTER_IMM_ByteWriteDisables_bits 4 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_REGISTER_IMM_ByteWriteDisables_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 4; case 70: return 4; case 60: return 4; case 50: return 4; case 45: return 4; case 40: return 4; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_LOAD_REGISTER_IMM_ByteWriteDisables_start 8 #define GFX12_MI_LOAD_REGISTER_IMM_ByteWriteDisables_start 8 #define GFX11_MI_LOAD_REGISTER_IMM_ByteWriteDisables_start 8 #define GFX9_MI_LOAD_REGISTER_IMM_ByteWriteDisables_start 8 #define GFX8_MI_LOAD_REGISTER_IMM_ByteWriteDisables_start 8 #define GFX75_MI_LOAD_REGISTER_IMM_ByteWriteDisables_start 8 #define GFX7_MI_LOAD_REGISTER_IMM_ByteWriteDisables_start 8 #define GFX6_MI_LOAD_REGISTER_IMM_ByteWriteDisables_start 8 #define GFX5_MI_LOAD_REGISTER_IMM_ByteWriteDisables_start 8 #define GFX45_MI_LOAD_REGISTER_IMM_ByteWriteDisables_start 8 #define GFX4_MI_LOAD_REGISTER_IMM_ByteWriteDisables_start 8 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_REGISTER_IMM_ByteWriteDisables_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 8; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } /* MI_LOAD_REGISTER_IMM::Command Type */ #define GFX125_MI_LOAD_REGISTER_IMM_CommandType_bits 3 #define GFX12_MI_LOAD_REGISTER_IMM_CommandType_bits 3 #define GFX11_MI_LOAD_REGISTER_IMM_CommandType_bits 3 #define GFX9_MI_LOAD_REGISTER_IMM_CommandType_bits 3 #define GFX8_MI_LOAD_REGISTER_IMM_CommandType_bits 3 #define GFX75_MI_LOAD_REGISTER_IMM_CommandType_bits 3 #define GFX7_MI_LOAD_REGISTER_IMM_CommandType_bits 3 #define GFX6_MI_LOAD_REGISTER_IMM_CommandType_bits 3 #define GFX5_MI_LOAD_REGISTER_IMM_CommandType_bits 3 #define GFX45_MI_LOAD_REGISTER_IMM_CommandType_bits 3 #define GFX4_MI_LOAD_REGISTER_IMM_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_REGISTER_IMM_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_LOAD_REGISTER_IMM_CommandType_start 29 #define GFX12_MI_LOAD_REGISTER_IMM_CommandType_start 29 #define GFX11_MI_LOAD_REGISTER_IMM_CommandType_start 29 #define GFX9_MI_LOAD_REGISTER_IMM_CommandType_start 29 #define GFX8_MI_LOAD_REGISTER_IMM_CommandType_start 29 #define GFX75_MI_LOAD_REGISTER_IMM_CommandType_start 29 #define GFX7_MI_LOAD_REGISTER_IMM_CommandType_start 29 #define GFX6_MI_LOAD_REGISTER_IMM_CommandType_start 29 #define GFX5_MI_LOAD_REGISTER_IMM_CommandType_start 29 #define GFX45_MI_LOAD_REGISTER_IMM_CommandType_start 29 #define GFX4_MI_LOAD_REGISTER_IMM_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_REGISTER_IMM_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 29; case 50: return 29; case 45: return 29; case 40: return 29; default: unreachable("Invalid hardware generation"); } } /* MI_LOAD_REGISTER_IMM::DWord Length */ #define GFX125_MI_LOAD_REGISTER_IMM_DWordLength_bits 8 #define GFX12_MI_LOAD_REGISTER_IMM_DWordLength_bits 8 #define GFX11_MI_LOAD_REGISTER_IMM_DWordLength_bits 8 #define GFX9_MI_LOAD_REGISTER_IMM_DWordLength_bits 8 #define GFX8_MI_LOAD_REGISTER_IMM_DWordLength_bits 8 #define GFX75_MI_LOAD_REGISTER_IMM_DWordLength_bits 8 #define GFX7_MI_LOAD_REGISTER_IMM_DWordLength_bits 8 #define GFX6_MI_LOAD_REGISTER_IMM_DWordLength_bits 8 #define GFX5_MI_LOAD_REGISTER_IMM_DWordLength_bits 6 #define GFX45_MI_LOAD_REGISTER_IMM_DWordLength_bits 6 #define GFX4_MI_LOAD_REGISTER_IMM_DWordLength_bits 6 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_REGISTER_IMM_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 6; case 45: return 6; case 40: return 6; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_LOAD_REGISTER_IMM_DWordLength_start 0 #define GFX12_MI_LOAD_REGISTER_IMM_DWordLength_start 0 #define GFX11_MI_LOAD_REGISTER_IMM_DWordLength_start 0 #define GFX9_MI_LOAD_REGISTER_IMM_DWordLength_start 0 #define GFX8_MI_LOAD_REGISTER_IMM_DWordLength_start 0 #define GFX75_MI_LOAD_REGISTER_IMM_DWordLength_start 0 #define GFX7_MI_LOAD_REGISTER_IMM_DWordLength_start 0 #define GFX6_MI_LOAD_REGISTER_IMM_DWordLength_start 0 #define GFX5_MI_LOAD_REGISTER_IMM_DWordLength_start 0 #define GFX45_MI_LOAD_REGISTER_IMM_DWordLength_start 0 #define GFX4_MI_LOAD_REGISTER_IMM_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_REGISTER_IMM_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_LOAD_REGISTER_IMM::Data DWord */ #define GFX125_MI_LOAD_REGISTER_IMM_DataDWord_bits 32 #define GFX12_MI_LOAD_REGISTER_IMM_DataDWord_bits 32 #define GFX11_MI_LOAD_REGISTER_IMM_DataDWord_bits 32 #define GFX9_MI_LOAD_REGISTER_IMM_DataDWord_bits 32 #define GFX8_MI_LOAD_REGISTER_IMM_DataDWord_bits 32 #define GFX75_MI_LOAD_REGISTER_IMM_DataDWord_bits 32 #define GFX7_MI_LOAD_REGISTER_IMM_DataDWord_bits 32 #define GFX6_MI_LOAD_REGISTER_IMM_DataDWord_bits 32 #define GFX5_MI_LOAD_REGISTER_IMM_DataDWord_bits 32 #define GFX45_MI_LOAD_REGISTER_IMM_DataDWord_bits 32 #define GFX4_MI_LOAD_REGISTER_IMM_DataDWord_bits 32 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_REGISTER_IMM_DataDWord_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 32; case 50: return 32; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_LOAD_REGISTER_IMM_DataDWord_start 64 #define GFX12_MI_LOAD_REGISTER_IMM_DataDWord_start 64 #define GFX11_MI_LOAD_REGISTER_IMM_DataDWord_start 64 #define GFX9_MI_LOAD_REGISTER_IMM_DataDWord_start 64 #define GFX8_MI_LOAD_REGISTER_IMM_DataDWord_start 64 #define GFX75_MI_LOAD_REGISTER_IMM_DataDWord_start 64 #define GFX7_MI_LOAD_REGISTER_IMM_DataDWord_start 64 #define GFX6_MI_LOAD_REGISTER_IMM_DataDWord_start 64 #define GFX5_MI_LOAD_REGISTER_IMM_DataDWord_start 64 #define GFX45_MI_LOAD_REGISTER_IMM_DataDWord_start 64 #define GFX4_MI_LOAD_REGISTER_IMM_DataDWord_start 64 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_REGISTER_IMM_DataDWord_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 64; case 80: return 64; case 75: return 64; case 70: return 64; case 60: return 64; case 50: return 64; case 45: return 64; case 40: return 64; default: unreachable("Invalid hardware generation"); } } /* MI_LOAD_REGISTER_IMM::MI Command Opcode */ #define GFX125_MI_LOAD_REGISTER_IMM_MICommandOpcode_bits 6 #define GFX12_MI_LOAD_REGISTER_IMM_MICommandOpcode_bits 6 #define GFX11_MI_LOAD_REGISTER_IMM_MICommandOpcode_bits 6 #define GFX9_MI_LOAD_REGISTER_IMM_MICommandOpcode_bits 6 #define GFX8_MI_LOAD_REGISTER_IMM_MICommandOpcode_bits 6 #define GFX75_MI_LOAD_REGISTER_IMM_MICommandOpcode_bits 6 #define GFX7_MI_LOAD_REGISTER_IMM_MICommandOpcode_bits 6 #define GFX6_MI_LOAD_REGISTER_IMM_MICommandOpcode_bits 6 #define GFX5_MI_LOAD_REGISTER_IMM_MICommandOpcode_bits 6 #define GFX45_MI_LOAD_REGISTER_IMM_MICommandOpcode_bits 6 #define GFX4_MI_LOAD_REGISTER_IMM_MICommandOpcode_bits 6 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_REGISTER_IMM_MICommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 6; case 60: return 6; case 50: return 6; case 45: return 6; case 40: return 6; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_LOAD_REGISTER_IMM_MICommandOpcode_start 23 #define GFX12_MI_LOAD_REGISTER_IMM_MICommandOpcode_start 23 #define GFX11_MI_LOAD_REGISTER_IMM_MICommandOpcode_start 23 #define GFX9_MI_LOAD_REGISTER_IMM_MICommandOpcode_start 23 #define GFX8_MI_LOAD_REGISTER_IMM_MICommandOpcode_start 23 #define GFX75_MI_LOAD_REGISTER_IMM_MICommandOpcode_start 23 #define GFX7_MI_LOAD_REGISTER_IMM_MICommandOpcode_start 23 #define GFX6_MI_LOAD_REGISTER_IMM_MICommandOpcode_start 23 #define GFX5_MI_LOAD_REGISTER_IMM_MICommandOpcode_start 23 #define GFX45_MI_LOAD_REGISTER_IMM_MICommandOpcode_start 23 #define GFX4_MI_LOAD_REGISTER_IMM_MICommandOpcode_start 23 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_REGISTER_IMM_MICommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 23; case 120: return 23; case 110: return 23; case 90: return 23; case 80: return 23; case 75: return 23; case 70: return 23; case 60: return 23; case 50: return 23; case 45: return 23; case 40: return 23; default: unreachable("Invalid hardware generation"); } } /* MI_LOAD_REGISTER_IMM::Register Offset */ #define GFX125_MI_LOAD_REGISTER_IMM_RegisterOffset_bits 21 #define GFX12_MI_LOAD_REGISTER_IMM_RegisterOffset_bits 21 #define GFX11_MI_LOAD_REGISTER_IMM_RegisterOffset_bits 21 #define GFX9_MI_LOAD_REGISTER_IMM_RegisterOffset_bits 21 #define GFX8_MI_LOAD_REGISTER_IMM_RegisterOffset_bits 21 #define GFX75_MI_LOAD_REGISTER_IMM_RegisterOffset_bits 21 #define GFX7_MI_LOAD_REGISTER_IMM_RegisterOffset_bits 21 #define GFX6_MI_LOAD_REGISTER_IMM_RegisterOffset_bits 21 #define GFX5_MI_LOAD_REGISTER_IMM_RegisterOffset_bits 30 #define GFX45_MI_LOAD_REGISTER_IMM_RegisterOffset_bits 30 #define GFX4_MI_LOAD_REGISTER_IMM_RegisterOffset_bits 30 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_REGISTER_IMM_RegisterOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 21; case 120: return 21; case 110: return 21; case 90: return 21; case 80: return 21; case 75: return 21; case 70: return 21; case 60: return 21; case 50: return 30; case 45: return 30; case 40: return 30; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_LOAD_REGISTER_IMM_RegisterOffset_start 34 #define GFX12_MI_LOAD_REGISTER_IMM_RegisterOffset_start 34 #define GFX11_MI_LOAD_REGISTER_IMM_RegisterOffset_start 34 #define GFX9_MI_LOAD_REGISTER_IMM_RegisterOffset_start 34 #define GFX8_MI_LOAD_REGISTER_IMM_RegisterOffset_start 34 #define GFX75_MI_LOAD_REGISTER_IMM_RegisterOffset_start 34 #define GFX7_MI_LOAD_REGISTER_IMM_RegisterOffset_start 34 #define GFX6_MI_LOAD_REGISTER_IMM_RegisterOffset_start 34 #define GFX5_MI_LOAD_REGISTER_IMM_RegisterOffset_start 34 #define GFX45_MI_LOAD_REGISTER_IMM_RegisterOffset_start 34 #define GFX4_MI_LOAD_REGISTER_IMM_RegisterOffset_start 34 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_REGISTER_IMM_RegisterOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 34; case 120: return 34; case 110: return 34; case 90: return 34; case 80: return 34; case 75: return 34; case 70: return 34; case 60: return 34; case 50: return 34; case 45: return 34; case 40: return 34; default: unreachable("Invalid hardware generation"); } } /* MI_LOAD_REGISTER_MEM */ #define GFX125_MI_LOAD_REGISTER_MEM_length 4 #define GFX12_MI_LOAD_REGISTER_MEM_length 4 #define GFX11_MI_LOAD_REGISTER_MEM_length 4 #define GFX9_MI_LOAD_REGISTER_MEM_length 4 #define GFX8_MI_LOAD_REGISTER_MEM_length 4 #define GFX75_MI_LOAD_REGISTER_MEM_length 3 #define GFX7_MI_LOAD_REGISTER_MEM_length 3 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_REGISTER_MEM_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_LOAD_REGISTER_MEM::Add CS MMIO Start Offset */ #define GFX125_MI_LOAD_REGISTER_MEM_AddCSMMIOStartOffset_bits 1 #define GFX12_MI_LOAD_REGISTER_MEM_AddCSMMIOStartOffset_bits 1 #define GFX11_MI_LOAD_REGISTER_MEM_AddCSMMIOStartOffset_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_REGISTER_MEM_AddCSMMIOStartOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_LOAD_REGISTER_MEM_AddCSMMIOStartOffset_start 19 #define GFX12_MI_LOAD_REGISTER_MEM_AddCSMMIOStartOffset_start 19 #define GFX11_MI_LOAD_REGISTER_MEM_AddCSMMIOStartOffset_start 19 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_REGISTER_MEM_AddCSMMIOStartOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 19; case 120: return 19; case 110: return 19; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_LOAD_REGISTER_MEM::Add Loop Variable */ #define GFX125_MI_LOAD_REGISTER_MEM_AddLoopVariable_bits 1 #define GFX12_MI_LOAD_REGISTER_MEM_AddLoopVariable_bits 1 #define GFX11_MI_LOAD_REGISTER_MEM_AddLoopVariable_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_REGISTER_MEM_AddLoopVariable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_LOAD_REGISTER_MEM_AddLoopVariable_start 20 #define GFX12_MI_LOAD_REGISTER_MEM_AddLoopVariable_start 20 #define GFX11_MI_LOAD_REGISTER_MEM_AddLoopVariable_start 20 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_REGISTER_MEM_AddLoopVariable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 20; case 120: return 20; case 110: return 20; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_LOAD_REGISTER_MEM::Async Mode Enable */ #define GFX125_MI_LOAD_REGISTER_MEM_AsyncModeEnable_bits 1 #define GFX12_MI_LOAD_REGISTER_MEM_AsyncModeEnable_bits 1 #define GFX11_MI_LOAD_REGISTER_MEM_AsyncModeEnable_bits 1 #define GFX9_MI_LOAD_REGISTER_MEM_AsyncModeEnable_bits 1 #define GFX8_MI_LOAD_REGISTER_MEM_AsyncModeEnable_bits 1 #define GFX75_MI_LOAD_REGISTER_MEM_AsyncModeEnable_bits 1 #define GFX7_MI_LOAD_REGISTER_MEM_AsyncModeEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_REGISTER_MEM_AsyncModeEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_LOAD_REGISTER_MEM_AsyncModeEnable_start 21 #define GFX12_MI_LOAD_REGISTER_MEM_AsyncModeEnable_start 21 #define GFX11_MI_LOAD_REGISTER_MEM_AsyncModeEnable_start 21 #define GFX9_MI_LOAD_REGISTER_MEM_AsyncModeEnable_start 21 #define GFX8_MI_LOAD_REGISTER_MEM_AsyncModeEnable_start 21 #define GFX75_MI_LOAD_REGISTER_MEM_AsyncModeEnable_start 21 #define GFX7_MI_LOAD_REGISTER_MEM_AsyncModeEnable_start 21 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_REGISTER_MEM_AsyncModeEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 21; case 120: return 21; case 110: return 21; case 90: return 21; case 80: return 21; case 75: return 21; case 70: return 21; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_LOAD_REGISTER_MEM::Command Type */ #define GFX125_MI_LOAD_REGISTER_MEM_CommandType_bits 3 #define GFX12_MI_LOAD_REGISTER_MEM_CommandType_bits 3 #define GFX11_MI_LOAD_REGISTER_MEM_CommandType_bits 3 #define GFX9_MI_LOAD_REGISTER_MEM_CommandType_bits 3 #define GFX8_MI_LOAD_REGISTER_MEM_CommandType_bits 3 #define GFX75_MI_LOAD_REGISTER_MEM_CommandType_bits 3 #define GFX7_MI_LOAD_REGISTER_MEM_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_REGISTER_MEM_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_LOAD_REGISTER_MEM_CommandType_start 29 #define GFX12_MI_LOAD_REGISTER_MEM_CommandType_start 29 #define GFX11_MI_LOAD_REGISTER_MEM_CommandType_start 29 #define GFX9_MI_LOAD_REGISTER_MEM_CommandType_start 29 #define GFX8_MI_LOAD_REGISTER_MEM_CommandType_start 29 #define GFX75_MI_LOAD_REGISTER_MEM_CommandType_start 29 #define GFX7_MI_LOAD_REGISTER_MEM_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_REGISTER_MEM_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_LOAD_REGISTER_MEM::DWord Length */ #define GFX125_MI_LOAD_REGISTER_MEM_DWordLength_bits 8 #define GFX12_MI_LOAD_REGISTER_MEM_DWordLength_bits 8 #define GFX11_MI_LOAD_REGISTER_MEM_DWordLength_bits 8 #define GFX9_MI_LOAD_REGISTER_MEM_DWordLength_bits 8 #define GFX8_MI_LOAD_REGISTER_MEM_DWordLength_bits 8 #define GFX75_MI_LOAD_REGISTER_MEM_DWordLength_bits 8 #define GFX7_MI_LOAD_REGISTER_MEM_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_REGISTER_MEM_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_LOAD_REGISTER_MEM_DWordLength_start 0 #define GFX12_MI_LOAD_REGISTER_MEM_DWordLength_start 0 #define GFX11_MI_LOAD_REGISTER_MEM_DWordLength_start 0 #define GFX9_MI_LOAD_REGISTER_MEM_DWordLength_start 0 #define GFX8_MI_LOAD_REGISTER_MEM_DWordLength_start 0 #define GFX75_MI_LOAD_REGISTER_MEM_DWordLength_start 0 #define GFX7_MI_LOAD_REGISTER_MEM_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_REGISTER_MEM_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_LOAD_REGISTER_MEM::MI Command Opcode */ #define GFX125_MI_LOAD_REGISTER_MEM_MICommandOpcode_bits 6 #define GFX12_MI_LOAD_REGISTER_MEM_MICommandOpcode_bits 6 #define GFX11_MI_LOAD_REGISTER_MEM_MICommandOpcode_bits 6 #define GFX9_MI_LOAD_REGISTER_MEM_MICommandOpcode_bits 6 #define GFX8_MI_LOAD_REGISTER_MEM_MICommandOpcode_bits 6 #define GFX75_MI_LOAD_REGISTER_MEM_MICommandOpcode_bits 6 #define GFX7_MI_LOAD_REGISTER_MEM_MICommandOpcode_bits 6 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_REGISTER_MEM_MICommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 6; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_LOAD_REGISTER_MEM_MICommandOpcode_start 23 #define GFX12_MI_LOAD_REGISTER_MEM_MICommandOpcode_start 23 #define GFX11_MI_LOAD_REGISTER_MEM_MICommandOpcode_start 23 #define GFX9_MI_LOAD_REGISTER_MEM_MICommandOpcode_start 23 #define GFX8_MI_LOAD_REGISTER_MEM_MICommandOpcode_start 23 #define GFX75_MI_LOAD_REGISTER_MEM_MICommandOpcode_start 23 #define GFX7_MI_LOAD_REGISTER_MEM_MICommandOpcode_start 23 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_REGISTER_MEM_MICommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 23; case 120: return 23; case 110: return 23; case 90: return 23; case 80: return 23; case 75: return 23; case 70: return 23; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_LOAD_REGISTER_MEM::Memory Address */ #define GFX125_MI_LOAD_REGISTER_MEM_MemoryAddress_bits 62 #define GFX12_MI_LOAD_REGISTER_MEM_MemoryAddress_bits 62 #define GFX11_MI_LOAD_REGISTER_MEM_MemoryAddress_bits 62 #define GFX9_MI_LOAD_REGISTER_MEM_MemoryAddress_bits 62 #define GFX8_MI_LOAD_REGISTER_MEM_MemoryAddress_bits 62 #define GFX75_MI_LOAD_REGISTER_MEM_MemoryAddress_bits 30 #define GFX7_MI_LOAD_REGISTER_MEM_MemoryAddress_bits 30 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_REGISTER_MEM_MemoryAddress_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 62; case 120: return 62; case 110: return 62; case 90: return 62; case 80: return 62; case 75: return 30; case 70: return 30; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_LOAD_REGISTER_MEM_MemoryAddress_start 66 #define GFX12_MI_LOAD_REGISTER_MEM_MemoryAddress_start 66 #define GFX11_MI_LOAD_REGISTER_MEM_MemoryAddress_start 66 #define GFX9_MI_LOAD_REGISTER_MEM_MemoryAddress_start 66 #define GFX8_MI_LOAD_REGISTER_MEM_MemoryAddress_start 66 #define GFX75_MI_LOAD_REGISTER_MEM_MemoryAddress_start 66 #define GFX7_MI_LOAD_REGISTER_MEM_MemoryAddress_start 66 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_REGISTER_MEM_MemoryAddress_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 66; case 120: return 66; case 110: return 66; case 90: return 66; case 80: return 66; case 75: return 66; case 70: return 66; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_LOAD_REGISTER_MEM::Register Address */ #define GFX125_MI_LOAD_REGISTER_MEM_RegisterAddress_bits 21 #define GFX12_MI_LOAD_REGISTER_MEM_RegisterAddress_bits 21 #define GFX11_MI_LOAD_REGISTER_MEM_RegisterAddress_bits 21 #define GFX9_MI_LOAD_REGISTER_MEM_RegisterAddress_bits 21 #define GFX8_MI_LOAD_REGISTER_MEM_RegisterAddress_bits 21 #define GFX75_MI_LOAD_REGISTER_MEM_RegisterAddress_bits 21 #define GFX7_MI_LOAD_REGISTER_MEM_RegisterAddress_bits 21 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_REGISTER_MEM_RegisterAddress_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 21; case 120: return 21; case 110: return 21; case 90: return 21; case 80: return 21; case 75: return 21; case 70: return 21; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_LOAD_REGISTER_MEM_RegisterAddress_start 34 #define GFX12_MI_LOAD_REGISTER_MEM_RegisterAddress_start 34 #define GFX11_MI_LOAD_REGISTER_MEM_RegisterAddress_start 34 #define GFX9_MI_LOAD_REGISTER_MEM_RegisterAddress_start 34 #define GFX8_MI_LOAD_REGISTER_MEM_RegisterAddress_start 34 #define GFX75_MI_LOAD_REGISTER_MEM_RegisterAddress_start 34 #define GFX7_MI_LOAD_REGISTER_MEM_RegisterAddress_start 34 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_REGISTER_MEM_RegisterAddress_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 34; case 120: return 34; case 110: return 34; case 90: return 34; case 80: return 34; case 75: return 34; case 70: return 34; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_LOAD_REGISTER_MEM::Use Global GTT */ #define GFX125_MI_LOAD_REGISTER_MEM_UseGlobalGTT_bits 1 #define GFX12_MI_LOAD_REGISTER_MEM_UseGlobalGTT_bits 1 #define GFX11_MI_LOAD_REGISTER_MEM_UseGlobalGTT_bits 1 #define GFX9_MI_LOAD_REGISTER_MEM_UseGlobalGTT_bits 1 #define GFX8_MI_LOAD_REGISTER_MEM_UseGlobalGTT_bits 1 #define GFX75_MI_LOAD_REGISTER_MEM_UseGlobalGTT_bits 1 #define GFX7_MI_LOAD_REGISTER_MEM_UseGlobalGTT_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_REGISTER_MEM_UseGlobalGTT_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_LOAD_REGISTER_MEM_UseGlobalGTT_start 22 #define GFX12_MI_LOAD_REGISTER_MEM_UseGlobalGTT_start 22 #define GFX11_MI_LOAD_REGISTER_MEM_UseGlobalGTT_start 22 #define GFX9_MI_LOAD_REGISTER_MEM_UseGlobalGTT_start 22 #define GFX8_MI_LOAD_REGISTER_MEM_UseGlobalGTT_start 22 #define GFX75_MI_LOAD_REGISTER_MEM_UseGlobalGTT_start 22 #define GFX7_MI_LOAD_REGISTER_MEM_UseGlobalGTT_start 22 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_REGISTER_MEM_UseGlobalGTT_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 22; case 120: return 22; case 110: return 22; case 90: return 22; case 80: return 22; case 75: return 22; case 70: return 22; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_LOAD_REGISTER_REG */ #define GFX125_MI_LOAD_REGISTER_REG_length 3 #define GFX12_MI_LOAD_REGISTER_REG_length 3 #define GFX11_MI_LOAD_REGISTER_REG_length 3 #define GFX9_MI_LOAD_REGISTER_REG_length 3 #define GFX8_MI_LOAD_REGISTER_REG_length 3 #define GFX75_MI_LOAD_REGISTER_REG_length 3 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_REGISTER_REG_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_LOAD_REGISTER_REG::Add CS MMIO Start Offset Destination */ #define GFX125_MI_LOAD_REGISTER_REG_AddCSMMIOStartOffsetDestination_bits 1 #define GFX12_MI_LOAD_REGISTER_REG_AddCSMMIOStartOffsetDestination_bits 1 #define GFX11_MI_LOAD_REGISTER_REG_AddCSMMIOStartOffsetDestination_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_REGISTER_REG_AddCSMMIOStartOffsetDestination_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_LOAD_REGISTER_REG_AddCSMMIOStartOffsetDestination_start 19 #define GFX12_MI_LOAD_REGISTER_REG_AddCSMMIOStartOffsetDestination_start 19 #define GFX11_MI_LOAD_REGISTER_REG_AddCSMMIOStartOffsetDestination_start 19 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_REGISTER_REG_AddCSMMIOStartOffsetDestination_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 19; case 120: return 19; case 110: return 19; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_LOAD_REGISTER_REG::Add CS MMIO Start Offset Source */ #define GFX125_MI_LOAD_REGISTER_REG_AddCSMMIOStartOffsetSource_bits 1 #define GFX12_MI_LOAD_REGISTER_REG_AddCSMMIOStartOffsetSource_bits 1 #define GFX11_MI_LOAD_REGISTER_REG_AddCSMMIOStartOffsetSource_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_REGISTER_REG_AddCSMMIOStartOffsetSource_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_LOAD_REGISTER_REG_AddCSMMIOStartOffsetSource_start 18 #define GFX12_MI_LOAD_REGISTER_REG_AddCSMMIOStartOffsetSource_start 18 #define GFX11_MI_LOAD_REGISTER_REG_AddCSMMIOStartOffsetSource_start 18 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_REGISTER_REG_AddCSMMIOStartOffsetSource_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 18; case 120: return 18; case 110: return 18; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_LOAD_REGISTER_REG::Command Type */ #define GFX125_MI_LOAD_REGISTER_REG_CommandType_bits 3 #define GFX12_MI_LOAD_REGISTER_REG_CommandType_bits 3 #define GFX11_MI_LOAD_REGISTER_REG_CommandType_bits 3 #define GFX9_MI_LOAD_REGISTER_REG_CommandType_bits 3 #define GFX8_MI_LOAD_REGISTER_REG_CommandType_bits 3 #define GFX75_MI_LOAD_REGISTER_REG_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_REGISTER_REG_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_LOAD_REGISTER_REG_CommandType_start 29 #define GFX12_MI_LOAD_REGISTER_REG_CommandType_start 29 #define GFX11_MI_LOAD_REGISTER_REG_CommandType_start 29 #define GFX9_MI_LOAD_REGISTER_REG_CommandType_start 29 #define GFX8_MI_LOAD_REGISTER_REG_CommandType_start 29 #define GFX75_MI_LOAD_REGISTER_REG_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_REGISTER_REG_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_LOAD_REGISTER_REG::DWord Length */ #define GFX125_MI_LOAD_REGISTER_REG_DWordLength_bits 8 #define GFX12_MI_LOAD_REGISTER_REG_DWordLength_bits 8 #define GFX11_MI_LOAD_REGISTER_REG_DWordLength_bits 8 #define GFX9_MI_LOAD_REGISTER_REG_DWordLength_bits 8 #define GFX8_MI_LOAD_REGISTER_REG_DWordLength_bits 8 #define GFX75_MI_LOAD_REGISTER_REG_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_REGISTER_REG_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_LOAD_REGISTER_REG_DWordLength_start 0 #define GFX12_MI_LOAD_REGISTER_REG_DWordLength_start 0 #define GFX11_MI_LOAD_REGISTER_REG_DWordLength_start 0 #define GFX9_MI_LOAD_REGISTER_REG_DWordLength_start 0 #define GFX8_MI_LOAD_REGISTER_REG_DWordLength_start 0 #define GFX75_MI_LOAD_REGISTER_REG_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_REGISTER_REG_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_LOAD_REGISTER_REG::Destination Register Address */ #define GFX125_MI_LOAD_REGISTER_REG_DestinationRegisterAddress_bits 21 #define GFX12_MI_LOAD_REGISTER_REG_DestinationRegisterAddress_bits 21 #define GFX11_MI_LOAD_REGISTER_REG_DestinationRegisterAddress_bits 21 #define GFX9_MI_LOAD_REGISTER_REG_DestinationRegisterAddress_bits 21 #define GFX8_MI_LOAD_REGISTER_REG_DestinationRegisterAddress_bits 21 #define GFX75_MI_LOAD_REGISTER_REG_DestinationRegisterAddress_bits 21 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_REGISTER_REG_DestinationRegisterAddress_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 21; case 120: return 21; case 110: return 21; case 90: return 21; case 80: return 21; case 75: return 21; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_LOAD_REGISTER_REG_DestinationRegisterAddress_start 66 #define GFX12_MI_LOAD_REGISTER_REG_DestinationRegisterAddress_start 66 #define GFX11_MI_LOAD_REGISTER_REG_DestinationRegisterAddress_start 66 #define GFX9_MI_LOAD_REGISTER_REG_DestinationRegisterAddress_start 66 #define GFX8_MI_LOAD_REGISTER_REG_DestinationRegisterAddress_start 66 #define GFX75_MI_LOAD_REGISTER_REG_DestinationRegisterAddress_start 66 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_REGISTER_REG_DestinationRegisterAddress_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 66; case 120: return 66; case 110: return 66; case 90: return 66; case 80: return 66; case 75: return 66; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_LOAD_REGISTER_REG::MI Command Opcode */ #define GFX125_MI_LOAD_REGISTER_REG_MICommandOpcode_bits 6 #define GFX12_MI_LOAD_REGISTER_REG_MICommandOpcode_bits 6 #define GFX11_MI_LOAD_REGISTER_REG_MICommandOpcode_bits 6 #define GFX9_MI_LOAD_REGISTER_REG_MICommandOpcode_bits 6 #define GFX8_MI_LOAD_REGISTER_REG_MICommandOpcode_bits 6 #define GFX75_MI_LOAD_REGISTER_REG_MICommandOpcode_bits 6 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_REGISTER_REG_MICommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_LOAD_REGISTER_REG_MICommandOpcode_start 23 #define GFX12_MI_LOAD_REGISTER_REG_MICommandOpcode_start 23 #define GFX11_MI_LOAD_REGISTER_REG_MICommandOpcode_start 23 #define GFX9_MI_LOAD_REGISTER_REG_MICommandOpcode_start 23 #define GFX8_MI_LOAD_REGISTER_REG_MICommandOpcode_start 23 #define GFX75_MI_LOAD_REGISTER_REG_MICommandOpcode_start 23 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_REGISTER_REG_MICommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 23; case 120: return 23; case 110: return 23; case 90: return 23; case 80: return 23; case 75: return 23; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_LOAD_REGISTER_REG::Source Register Address */ #define GFX125_MI_LOAD_REGISTER_REG_SourceRegisterAddress_bits 21 #define GFX12_MI_LOAD_REGISTER_REG_SourceRegisterAddress_bits 21 #define GFX11_MI_LOAD_REGISTER_REG_SourceRegisterAddress_bits 21 #define GFX9_MI_LOAD_REGISTER_REG_SourceRegisterAddress_bits 21 #define GFX8_MI_LOAD_REGISTER_REG_SourceRegisterAddress_bits 21 #define GFX75_MI_LOAD_REGISTER_REG_SourceRegisterAddress_bits 21 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_REGISTER_REG_SourceRegisterAddress_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 21; case 120: return 21; case 110: return 21; case 90: return 21; case 80: return 21; case 75: return 21; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_LOAD_REGISTER_REG_SourceRegisterAddress_start 34 #define GFX12_MI_LOAD_REGISTER_REG_SourceRegisterAddress_start 34 #define GFX11_MI_LOAD_REGISTER_REG_SourceRegisterAddress_start 34 #define GFX9_MI_LOAD_REGISTER_REG_SourceRegisterAddress_start 34 #define GFX8_MI_LOAD_REGISTER_REG_SourceRegisterAddress_start 34 #define GFX75_MI_LOAD_REGISTER_REG_SourceRegisterAddress_start 34 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_REGISTER_REG_SourceRegisterAddress_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 34; case 120: return 34; case 110: return 34; case 90: return 34; case 80: return 34; case 75: return 34; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_LOAD_SCAN_LINES_EXCL */ #define GFX125_MI_LOAD_SCAN_LINES_EXCL_length 2 #define GFX12_MI_LOAD_SCAN_LINES_EXCL_length 2 #define GFX11_MI_LOAD_SCAN_LINES_EXCL_length 2 #define GFX9_MI_LOAD_SCAN_LINES_EXCL_length 2 #define GFX8_MI_LOAD_SCAN_LINES_EXCL_length 2 #define GFX75_MI_LOAD_SCAN_LINES_EXCL_length 2 #define GFX6_MI_LOAD_SCAN_LINES_EXCL_length 2 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_SCAN_LINES_EXCL_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 0; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_LOAD_SCAN_LINES_EXCL::Command Type */ #define GFX125_MI_LOAD_SCAN_LINES_EXCL_CommandType_bits 3 #define GFX12_MI_LOAD_SCAN_LINES_EXCL_CommandType_bits 3 #define GFX11_MI_LOAD_SCAN_LINES_EXCL_CommandType_bits 3 #define GFX9_MI_LOAD_SCAN_LINES_EXCL_CommandType_bits 3 #define GFX8_MI_LOAD_SCAN_LINES_EXCL_CommandType_bits 3 #define GFX75_MI_LOAD_SCAN_LINES_EXCL_CommandType_bits 3 #define GFX6_MI_LOAD_SCAN_LINES_EXCL_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_SCAN_LINES_EXCL_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 0; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_LOAD_SCAN_LINES_EXCL_CommandType_start 29 #define GFX12_MI_LOAD_SCAN_LINES_EXCL_CommandType_start 29 #define GFX11_MI_LOAD_SCAN_LINES_EXCL_CommandType_start 29 #define GFX9_MI_LOAD_SCAN_LINES_EXCL_CommandType_start 29 #define GFX8_MI_LOAD_SCAN_LINES_EXCL_CommandType_start 29 #define GFX75_MI_LOAD_SCAN_LINES_EXCL_CommandType_start 29 #define GFX6_MI_LOAD_SCAN_LINES_EXCL_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_SCAN_LINES_EXCL_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 0; case 60: return 29; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_LOAD_SCAN_LINES_EXCL::DWord Length */ #define GFX125_MI_LOAD_SCAN_LINES_EXCL_DWordLength_bits 6 #define GFX12_MI_LOAD_SCAN_LINES_EXCL_DWordLength_bits 6 #define GFX11_MI_LOAD_SCAN_LINES_EXCL_DWordLength_bits 6 #define GFX9_MI_LOAD_SCAN_LINES_EXCL_DWordLength_bits 6 #define GFX8_MI_LOAD_SCAN_LINES_EXCL_DWordLength_bits 6 #define GFX75_MI_LOAD_SCAN_LINES_EXCL_DWordLength_bits 6 #define GFX6_MI_LOAD_SCAN_LINES_EXCL_DWordLength_bits 6 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_SCAN_LINES_EXCL_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 0; case 60: return 6; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_LOAD_SCAN_LINES_EXCL_DWordLength_start 0 #define GFX12_MI_LOAD_SCAN_LINES_EXCL_DWordLength_start 0 #define GFX11_MI_LOAD_SCAN_LINES_EXCL_DWordLength_start 0 #define GFX9_MI_LOAD_SCAN_LINES_EXCL_DWordLength_start 0 #define GFX8_MI_LOAD_SCAN_LINES_EXCL_DWordLength_start 0 #define GFX75_MI_LOAD_SCAN_LINES_EXCL_DWordLength_start 0 #define GFX6_MI_LOAD_SCAN_LINES_EXCL_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_SCAN_LINES_EXCL_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_LOAD_SCAN_LINES_EXCL::Display (Plane) Select */ #define GFX125_MI_LOAD_SCAN_LINES_EXCL_DisplayPlaneSelect_bits 3 #define GFX12_MI_LOAD_SCAN_LINES_EXCL_DisplayPlaneSelect_bits 3 #define GFX11_MI_LOAD_SCAN_LINES_EXCL_DisplayPlaneSelect_bits 3 #define GFX9_MI_LOAD_SCAN_LINES_EXCL_DisplayPlaneSelect_bits 3 #define GFX8_MI_LOAD_SCAN_LINES_EXCL_DisplayPlaneSelect_bits 3 #define GFX75_MI_LOAD_SCAN_LINES_EXCL_DisplayPlaneSelect_bits 3 #define GFX6_MI_LOAD_SCAN_LINES_EXCL_DisplayPlaneSelect_bits 3 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_SCAN_LINES_EXCL_DisplayPlaneSelect_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 0; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_LOAD_SCAN_LINES_EXCL_DisplayPlaneSelect_start 19 #define GFX12_MI_LOAD_SCAN_LINES_EXCL_DisplayPlaneSelect_start 19 #define GFX11_MI_LOAD_SCAN_LINES_EXCL_DisplayPlaneSelect_start 19 #define GFX9_MI_LOAD_SCAN_LINES_EXCL_DisplayPlaneSelect_start 19 #define GFX8_MI_LOAD_SCAN_LINES_EXCL_DisplayPlaneSelect_start 19 #define GFX75_MI_LOAD_SCAN_LINES_EXCL_DisplayPlaneSelect_start 19 #define GFX6_MI_LOAD_SCAN_LINES_EXCL_DisplayPlaneSelect_start 19 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_SCAN_LINES_EXCL_DisplayPlaneSelect_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 19; case 120: return 19; case 110: return 19; case 90: return 19; case 80: return 19; case 75: return 19; case 70: return 0; case 60: return 19; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_LOAD_SCAN_LINES_EXCL::End Scan Line Number */ #define GFX125_MI_LOAD_SCAN_LINES_EXCL_EndScanLineNumber_bits 13 #define GFX12_MI_LOAD_SCAN_LINES_EXCL_EndScanLineNumber_bits 13 #define GFX11_MI_LOAD_SCAN_LINES_EXCL_EndScanLineNumber_bits 13 #define GFX9_MI_LOAD_SCAN_LINES_EXCL_EndScanLineNumber_bits 13 #define GFX8_MI_LOAD_SCAN_LINES_EXCL_EndScanLineNumber_bits 13 #define GFX75_MI_LOAD_SCAN_LINES_EXCL_EndScanLineNumber_bits 13 #define GFX6_MI_LOAD_SCAN_LINES_EXCL_EndScanLineNumber_bits 13 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_SCAN_LINES_EXCL_EndScanLineNumber_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 13; case 120: return 13; case 110: return 13; case 90: return 13; case 80: return 13; case 75: return 13; case 70: return 0; case 60: return 13; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_LOAD_SCAN_LINES_EXCL_EndScanLineNumber_start 32 #define GFX12_MI_LOAD_SCAN_LINES_EXCL_EndScanLineNumber_start 32 #define GFX11_MI_LOAD_SCAN_LINES_EXCL_EndScanLineNumber_start 32 #define GFX9_MI_LOAD_SCAN_LINES_EXCL_EndScanLineNumber_start 32 #define GFX8_MI_LOAD_SCAN_LINES_EXCL_EndScanLineNumber_start 32 #define GFX75_MI_LOAD_SCAN_LINES_EXCL_EndScanLineNumber_start 32 #define GFX6_MI_LOAD_SCAN_LINES_EXCL_EndScanLineNumber_start 32 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_SCAN_LINES_EXCL_EndScanLineNumber_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 0; case 60: return 32; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_LOAD_SCAN_LINES_EXCL::MI Command Opcode */ #define GFX125_MI_LOAD_SCAN_LINES_EXCL_MICommandOpcode_bits 6 #define GFX12_MI_LOAD_SCAN_LINES_EXCL_MICommandOpcode_bits 6 #define GFX11_MI_LOAD_SCAN_LINES_EXCL_MICommandOpcode_bits 6 #define GFX9_MI_LOAD_SCAN_LINES_EXCL_MICommandOpcode_bits 6 #define GFX8_MI_LOAD_SCAN_LINES_EXCL_MICommandOpcode_bits 6 #define GFX75_MI_LOAD_SCAN_LINES_EXCL_MICommandOpcode_bits 6 #define GFX6_MI_LOAD_SCAN_LINES_EXCL_MICommandOpcode_bits 6 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_SCAN_LINES_EXCL_MICommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 0; case 60: return 6; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_LOAD_SCAN_LINES_EXCL_MICommandOpcode_start 23 #define GFX12_MI_LOAD_SCAN_LINES_EXCL_MICommandOpcode_start 23 #define GFX11_MI_LOAD_SCAN_LINES_EXCL_MICommandOpcode_start 23 #define GFX9_MI_LOAD_SCAN_LINES_EXCL_MICommandOpcode_start 23 #define GFX8_MI_LOAD_SCAN_LINES_EXCL_MICommandOpcode_start 23 #define GFX75_MI_LOAD_SCAN_LINES_EXCL_MICommandOpcode_start 23 #define GFX6_MI_LOAD_SCAN_LINES_EXCL_MICommandOpcode_start 23 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_SCAN_LINES_EXCL_MICommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 23; case 120: return 23; case 110: return 23; case 90: return 23; case 80: return 23; case 75: return 23; case 70: return 0; case 60: return 23; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_LOAD_SCAN_LINES_EXCL::Start Scan Line Number */ #define GFX125_MI_LOAD_SCAN_LINES_EXCL_StartScanLineNumber_bits 13 #define GFX12_MI_LOAD_SCAN_LINES_EXCL_StartScanLineNumber_bits 13 #define GFX11_MI_LOAD_SCAN_LINES_EXCL_StartScanLineNumber_bits 13 #define GFX9_MI_LOAD_SCAN_LINES_EXCL_StartScanLineNumber_bits 13 #define GFX8_MI_LOAD_SCAN_LINES_EXCL_StartScanLineNumber_bits 13 #define GFX75_MI_LOAD_SCAN_LINES_EXCL_StartScanLineNumber_bits 13 #define GFX6_MI_LOAD_SCAN_LINES_EXCL_StartScanLineNumber_bits 13 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_SCAN_LINES_EXCL_StartScanLineNumber_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 13; case 120: return 13; case 110: return 13; case 90: return 13; case 80: return 13; case 75: return 13; case 70: return 0; case 60: return 13; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_LOAD_SCAN_LINES_EXCL_StartScanLineNumber_start 48 #define GFX12_MI_LOAD_SCAN_LINES_EXCL_StartScanLineNumber_start 48 #define GFX11_MI_LOAD_SCAN_LINES_EXCL_StartScanLineNumber_start 48 #define GFX9_MI_LOAD_SCAN_LINES_EXCL_StartScanLineNumber_start 48 #define GFX8_MI_LOAD_SCAN_LINES_EXCL_StartScanLineNumber_start 48 #define GFX75_MI_LOAD_SCAN_LINES_EXCL_StartScanLineNumber_start 48 #define GFX6_MI_LOAD_SCAN_LINES_EXCL_StartScanLineNumber_start 48 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_SCAN_LINES_EXCL_StartScanLineNumber_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 48; case 120: return 48; case 110: return 48; case 90: return 48; case 80: return 48; case 75: return 48; case 70: return 0; case 60: return 48; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_LOAD_SCAN_LINES_INCL */ #define GFX125_MI_LOAD_SCAN_LINES_INCL_length 2 #define GFX12_MI_LOAD_SCAN_LINES_INCL_length 2 #define GFX11_MI_LOAD_SCAN_LINES_INCL_length 2 #define GFX9_MI_LOAD_SCAN_LINES_INCL_length 2 #define GFX8_MI_LOAD_SCAN_LINES_INCL_length 2 #define GFX75_MI_LOAD_SCAN_LINES_INCL_length 2 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_SCAN_LINES_INCL_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_LOAD_SCAN_LINES_INCL::Command Type */ #define GFX125_MI_LOAD_SCAN_LINES_INCL_CommandType_bits 3 #define GFX12_MI_LOAD_SCAN_LINES_INCL_CommandType_bits 3 #define GFX11_MI_LOAD_SCAN_LINES_INCL_CommandType_bits 3 #define GFX9_MI_LOAD_SCAN_LINES_INCL_CommandType_bits 3 #define GFX8_MI_LOAD_SCAN_LINES_INCL_CommandType_bits 3 #define GFX75_MI_LOAD_SCAN_LINES_INCL_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_SCAN_LINES_INCL_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_LOAD_SCAN_LINES_INCL_CommandType_start 29 #define GFX12_MI_LOAD_SCAN_LINES_INCL_CommandType_start 29 #define GFX11_MI_LOAD_SCAN_LINES_INCL_CommandType_start 29 #define GFX9_MI_LOAD_SCAN_LINES_INCL_CommandType_start 29 #define GFX8_MI_LOAD_SCAN_LINES_INCL_CommandType_start 29 #define GFX75_MI_LOAD_SCAN_LINES_INCL_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_SCAN_LINES_INCL_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_LOAD_SCAN_LINES_INCL::DWord Length */ #define GFX125_MI_LOAD_SCAN_LINES_INCL_DWordLength_bits 6 #define GFX12_MI_LOAD_SCAN_LINES_INCL_DWordLength_bits 6 #define GFX11_MI_LOAD_SCAN_LINES_INCL_DWordLength_bits 6 #define GFX9_MI_LOAD_SCAN_LINES_INCL_DWordLength_bits 6 #define GFX8_MI_LOAD_SCAN_LINES_INCL_DWordLength_bits 6 #define GFX75_MI_LOAD_SCAN_LINES_INCL_DWordLength_bits 6 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_SCAN_LINES_INCL_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_LOAD_SCAN_LINES_INCL_DWordLength_start 0 #define GFX12_MI_LOAD_SCAN_LINES_INCL_DWordLength_start 0 #define GFX11_MI_LOAD_SCAN_LINES_INCL_DWordLength_start 0 #define GFX9_MI_LOAD_SCAN_LINES_INCL_DWordLength_start 0 #define GFX8_MI_LOAD_SCAN_LINES_INCL_DWordLength_start 0 #define GFX75_MI_LOAD_SCAN_LINES_INCL_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_SCAN_LINES_INCL_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_LOAD_SCAN_LINES_INCL::Display (Plane) Select */ #define GFX125_MI_LOAD_SCAN_LINES_INCL_DisplayPlaneSelect_bits 3 #define GFX12_MI_LOAD_SCAN_LINES_INCL_DisplayPlaneSelect_bits 3 #define GFX11_MI_LOAD_SCAN_LINES_INCL_DisplayPlaneSelect_bits 3 #define GFX9_MI_LOAD_SCAN_LINES_INCL_DisplayPlaneSelect_bits 3 #define GFX8_MI_LOAD_SCAN_LINES_INCL_DisplayPlaneSelect_bits 3 #define GFX75_MI_LOAD_SCAN_LINES_INCL_DisplayPlaneSelect_bits 3 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_SCAN_LINES_INCL_DisplayPlaneSelect_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_LOAD_SCAN_LINES_INCL_DisplayPlaneSelect_start 19 #define GFX12_MI_LOAD_SCAN_LINES_INCL_DisplayPlaneSelect_start 19 #define GFX11_MI_LOAD_SCAN_LINES_INCL_DisplayPlaneSelect_start 19 #define GFX9_MI_LOAD_SCAN_LINES_INCL_DisplayPlaneSelect_start 19 #define GFX8_MI_LOAD_SCAN_LINES_INCL_DisplayPlaneSelect_start 19 #define GFX75_MI_LOAD_SCAN_LINES_INCL_DisplayPlaneSelect_start 19 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_SCAN_LINES_INCL_DisplayPlaneSelect_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 19; case 120: return 19; case 110: return 19; case 90: return 19; case 80: return 19; case 75: return 19; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_LOAD_SCAN_LINES_INCL::End Scan Line Number */ #define GFX125_MI_LOAD_SCAN_LINES_INCL_EndScanLineNumber_bits 13 #define GFX12_MI_LOAD_SCAN_LINES_INCL_EndScanLineNumber_bits 13 #define GFX11_MI_LOAD_SCAN_LINES_INCL_EndScanLineNumber_bits 13 #define GFX9_MI_LOAD_SCAN_LINES_INCL_EndScanLineNumber_bits 13 #define GFX8_MI_LOAD_SCAN_LINES_INCL_EndScanLineNumber_bits 13 #define GFX75_MI_LOAD_SCAN_LINES_INCL_EndScanLineNumber_bits 13 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_SCAN_LINES_INCL_EndScanLineNumber_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 13; case 120: return 13; case 110: return 13; case 90: return 13; case 80: return 13; case 75: return 13; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_LOAD_SCAN_LINES_INCL_EndScanLineNumber_start 32 #define GFX12_MI_LOAD_SCAN_LINES_INCL_EndScanLineNumber_start 32 #define GFX11_MI_LOAD_SCAN_LINES_INCL_EndScanLineNumber_start 32 #define GFX9_MI_LOAD_SCAN_LINES_INCL_EndScanLineNumber_start 32 #define GFX8_MI_LOAD_SCAN_LINES_INCL_EndScanLineNumber_start 32 #define GFX75_MI_LOAD_SCAN_LINES_INCL_EndScanLineNumber_start 32 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_SCAN_LINES_INCL_EndScanLineNumber_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_LOAD_SCAN_LINES_INCL::MI Command Opcode */ #define GFX125_MI_LOAD_SCAN_LINES_INCL_MICommandOpcode_bits 6 #define GFX12_MI_LOAD_SCAN_LINES_INCL_MICommandOpcode_bits 6 #define GFX11_MI_LOAD_SCAN_LINES_INCL_MICommandOpcode_bits 6 #define GFX9_MI_LOAD_SCAN_LINES_INCL_MICommandOpcode_bits 6 #define GFX8_MI_LOAD_SCAN_LINES_INCL_MICommandOpcode_bits 6 #define GFX75_MI_LOAD_SCAN_LINES_INCL_MICommandOpcode_bits 6 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_SCAN_LINES_INCL_MICommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_LOAD_SCAN_LINES_INCL_MICommandOpcode_start 23 #define GFX12_MI_LOAD_SCAN_LINES_INCL_MICommandOpcode_start 23 #define GFX11_MI_LOAD_SCAN_LINES_INCL_MICommandOpcode_start 23 #define GFX9_MI_LOAD_SCAN_LINES_INCL_MICommandOpcode_start 23 #define GFX8_MI_LOAD_SCAN_LINES_INCL_MICommandOpcode_start 23 #define GFX75_MI_LOAD_SCAN_LINES_INCL_MICommandOpcode_start 23 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_SCAN_LINES_INCL_MICommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 23; case 120: return 23; case 110: return 23; case 90: return 23; case 80: return 23; case 75: return 23; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_LOAD_SCAN_LINES_INCL::Scan Line Event Done Forward */ #define GFX125_MI_LOAD_SCAN_LINES_INCL_ScanLineEventDoneForward_bits 2 #define GFX12_MI_LOAD_SCAN_LINES_INCL_ScanLineEventDoneForward_bits 2 #define GFX11_MI_LOAD_SCAN_LINES_INCL_ScanLineEventDoneForward_bits 2 #define GFX9_MI_LOAD_SCAN_LINES_INCL_ScanLineEventDoneForward_bits 2 #define GFX8_MI_LOAD_SCAN_LINES_INCL_ScanLineEventDoneForward_bits 2 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_SCAN_LINES_INCL_ScanLineEventDoneForward_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_LOAD_SCAN_LINES_INCL_ScanLineEventDoneForward_start 17 #define GFX12_MI_LOAD_SCAN_LINES_INCL_ScanLineEventDoneForward_start 17 #define GFX11_MI_LOAD_SCAN_LINES_INCL_ScanLineEventDoneForward_start 17 #define GFX9_MI_LOAD_SCAN_LINES_INCL_ScanLineEventDoneForward_start 17 #define GFX8_MI_LOAD_SCAN_LINES_INCL_ScanLineEventDoneForward_start 17 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_SCAN_LINES_INCL_ScanLineEventDoneForward_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 17; case 120: return 17; case 110: return 17; case 90: return 17; case 80: return 17; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_LOAD_SCAN_LINES_INCL::Start Scan Line Number */ #define GFX125_MI_LOAD_SCAN_LINES_INCL_StartScanLineNumber_bits 13 #define GFX12_MI_LOAD_SCAN_LINES_INCL_StartScanLineNumber_bits 13 #define GFX11_MI_LOAD_SCAN_LINES_INCL_StartScanLineNumber_bits 13 #define GFX9_MI_LOAD_SCAN_LINES_INCL_StartScanLineNumber_bits 13 #define GFX8_MI_LOAD_SCAN_LINES_INCL_StartScanLineNumber_bits 13 #define GFX75_MI_LOAD_SCAN_LINES_INCL_StartScanLineNumber_bits 13 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_SCAN_LINES_INCL_StartScanLineNumber_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 13; case 120: return 13; case 110: return 13; case 90: return 13; case 80: return 13; case 75: return 13; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_LOAD_SCAN_LINES_INCL_StartScanLineNumber_start 48 #define GFX12_MI_LOAD_SCAN_LINES_INCL_StartScanLineNumber_start 48 #define GFX11_MI_LOAD_SCAN_LINES_INCL_StartScanLineNumber_start 48 #define GFX9_MI_LOAD_SCAN_LINES_INCL_StartScanLineNumber_start 48 #define GFX8_MI_LOAD_SCAN_LINES_INCL_StartScanLineNumber_start 48 #define GFX75_MI_LOAD_SCAN_LINES_INCL_StartScanLineNumber_start 48 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_SCAN_LINES_INCL_StartScanLineNumber_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 48; case 120: return 48; case 110: return 48; case 90: return 48; case 80: return 48; case 75: return 48; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_LOAD_URB_MEM */ #define GFX9_MI_LOAD_URB_MEM_length 4 #define GFX8_MI_LOAD_URB_MEM_length 4 #define GFX75_MI_LOAD_URB_MEM_length 3 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_URB_MEM_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 4; case 80: return 4; case 75: return 3; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_LOAD_URB_MEM::Command Type */ #define GFX9_MI_LOAD_URB_MEM_CommandType_bits 3 #define GFX8_MI_LOAD_URB_MEM_CommandType_bits 3 #define GFX75_MI_LOAD_URB_MEM_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_URB_MEM_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_MI_LOAD_URB_MEM_CommandType_start 29 #define GFX8_MI_LOAD_URB_MEM_CommandType_start 29 #define GFX75_MI_LOAD_URB_MEM_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_URB_MEM_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_LOAD_URB_MEM::DWord Length */ #define GFX9_MI_LOAD_URB_MEM_DWordLength_bits 8 #define GFX8_MI_LOAD_URB_MEM_DWordLength_bits 8 #define GFX75_MI_LOAD_URB_MEM_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_URB_MEM_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_MI_LOAD_URB_MEM_DWordLength_start 0 #define GFX8_MI_LOAD_URB_MEM_DWordLength_start 0 #define GFX75_MI_LOAD_URB_MEM_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_URB_MEM_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_LOAD_URB_MEM::MI Command Opcode */ #define GFX9_MI_LOAD_URB_MEM_MICommandOpcode_bits 6 #define GFX8_MI_LOAD_URB_MEM_MICommandOpcode_bits 6 #define GFX75_MI_LOAD_URB_MEM_MICommandOpcode_bits 6 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_URB_MEM_MICommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_MI_LOAD_URB_MEM_MICommandOpcode_start 23 #define GFX8_MI_LOAD_URB_MEM_MICommandOpcode_start 23 #define GFX75_MI_LOAD_URB_MEM_MICommandOpcode_start 23 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_URB_MEM_MICommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 23; case 80: return 23; case 75: return 23; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_LOAD_URB_MEM::Memory Address */ #define GFX9_MI_LOAD_URB_MEM_MemoryAddress_bits 58 #define GFX8_MI_LOAD_URB_MEM_MemoryAddress_bits 58 #define GFX75_MI_LOAD_URB_MEM_MemoryAddress_bits 26 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_URB_MEM_MemoryAddress_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 58; case 80: return 58; case 75: return 26; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_MI_LOAD_URB_MEM_MemoryAddress_start 70 #define GFX8_MI_LOAD_URB_MEM_MemoryAddress_start 70 #define GFX75_MI_LOAD_URB_MEM_MemoryAddress_start 70 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_URB_MEM_MemoryAddress_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 70; case 80: return 70; case 75: return 70; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_LOAD_URB_MEM::URB Address */ #define GFX9_MI_LOAD_URB_MEM_URBAddress_bits 13 #define GFX8_MI_LOAD_URB_MEM_URBAddress_bits 13 #define GFX75_MI_LOAD_URB_MEM_URBAddress_bits 13 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_URB_MEM_URBAddress_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 13; case 80: return 13; case 75: return 13; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_MI_LOAD_URB_MEM_URBAddress_start 34 #define GFX8_MI_LOAD_URB_MEM_URBAddress_start 34 #define GFX75_MI_LOAD_URB_MEM_URBAddress_start 34 static inline uint32_t ATTRIBUTE_PURE MI_LOAD_URB_MEM_URBAddress_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 34; case 80: return 34; case 75: return 34; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_MATH */ /* MI_MATH::Command Type */ #define GFX125_MI_MATH_CommandType_bits 3 #define GFX12_MI_MATH_CommandType_bits 3 #define GFX11_MI_MATH_CommandType_bits 3 #define GFX9_MI_MATH_CommandType_bits 3 #define GFX8_MI_MATH_CommandType_bits 3 #define GFX75_MI_MATH_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE MI_MATH_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_MATH_CommandType_start 29 #define GFX12_MI_MATH_CommandType_start 29 #define GFX11_MI_MATH_CommandType_start 29 #define GFX9_MI_MATH_CommandType_start 29 #define GFX8_MI_MATH_CommandType_start 29 #define GFX75_MI_MATH_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE MI_MATH_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_MATH::DWord Length */ #define GFX125_MI_MATH_DWordLength_bits 8 #define GFX12_MI_MATH_DWordLength_bits 8 #define GFX11_MI_MATH_DWordLength_bits 8 #define GFX9_MI_MATH_DWordLength_bits 8 #define GFX8_MI_MATH_DWordLength_bits 6 #define GFX75_MI_MATH_DWordLength_bits 6 static inline uint32_t ATTRIBUTE_PURE MI_MATH_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 6; case 75: return 6; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_MATH_DWordLength_start 0 #define GFX12_MI_MATH_DWordLength_start 0 #define GFX11_MI_MATH_DWordLength_start 0 #define GFX9_MI_MATH_DWordLength_start 0 #define GFX8_MI_MATH_DWordLength_start 0 #define GFX75_MI_MATH_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE MI_MATH_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_MATH::MI Command Opcode */ #define GFX125_MI_MATH_MICommandOpcode_bits 6 #define GFX12_MI_MATH_MICommandOpcode_bits 6 #define GFX11_MI_MATH_MICommandOpcode_bits 6 #define GFX9_MI_MATH_MICommandOpcode_bits 6 #define GFX8_MI_MATH_MICommandOpcode_bits 6 #define GFX75_MI_MATH_MICommandOpcode_bits 6 static inline uint32_t ATTRIBUTE_PURE MI_MATH_MICommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_MATH_MICommandOpcode_start 23 #define GFX12_MI_MATH_MICommandOpcode_start 23 #define GFX11_MI_MATH_MICommandOpcode_start 23 #define GFX9_MI_MATH_MICommandOpcode_start 23 #define GFX8_MI_MATH_MICommandOpcode_start 23 #define GFX75_MI_MATH_MICommandOpcode_start 23 static inline uint32_t ATTRIBUTE_PURE MI_MATH_MICommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 23; case 120: return 23; case 110: return 23; case 90: return 23; case 80: return 23; case 75: return 23; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_MATH_ALU_INSTRUCTION */ #define GFX125_MI_MATH_ALU_INSTRUCTION_length 1 #define GFX12_MI_MATH_ALU_INSTRUCTION_length 1 #define GFX11_MI_MATH_ALU_INSTRUCTION_length 1 #define GFX9_MI_MATH_ALU_INSTRUCTION_length 1 #define GFX8_MI_MATH_ALU_INSTRUCTION_length 1 #define GFX75_MI_MATH_ALU_INSTRUCTION_length 1 static inline uint32_t ATTRIBUTE_PURE MI_MATH_ALU_INSTRUCTION_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_MATH_ALU_INSTRUCTION::ALU Opcode */ #define GFX125_MI_MATH_ALU_INSTRUCTION_ALUOpcode_bits 12 #define GFX12_MI_MATH_ALU_INSTRUCTION_ALUOpcode_bits 12 #define GFX11_MI_MATH_ALU_INSTRUCTION_ALUOpcode_bits 12 #define GFX9_MI_MATH_ALU_INSTRUCTION_ALUOpcode_bits 12 #define GFX8_MI_MATH_ALU_INSTRUCTION_ALUOpcode_bits 12 #define GFX75_MI_MATH_ALU_INSTRUCTION_ALUOpcode_bits 12 static inline uint32_t ATTRIBUTE_PURE MI_MATH_ALU_INSTRUCTION_ALUOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 12; case 120: return 12; case 110: return 12; case 90: return 12; case 80: return 12; case 75: return 12; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_MATH_ALU_INSTRUCTION_ALUOpcode_start 20 #define GFX12_MI_MATH_ALU_INSTRUCTION_ALUOpcode_start 20 #define GFX11_MI_MATH_ALU_INSTRUCTION_ALUOpcode_start 20 #define GFX9_MI_MATH_ALU_INSTRUCTION_ALUOpcode_start 20 #define GFX8_MI_MATH_ALU_INSTRUCTION_ALUOpcode_start 20 #define GFX75_MI_MATH_ALU_INSTRUCTION_ALUOpcode_start 20 static inline uint32_t ATTRIBUTE_PURE MI_MATH_ALU_INSTRUCTION_ALUOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 20; case 120: return 20; case 110: return 20; case 90: return 20; case 80: return 20; case 75: return 20; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_MATH_ALU_INSTRUCTION::Operand 1 */ #define GFX125_MI_MATH_ALU_INSTRUCTION_Operand1_bits 10 #define GFX12_MI_MATH_ALU_INSTRUCTION_Operand1_bits 10 #define GFX11_MI_MATH_ALU_INSTRUCTION_Operand1_bits 10 #define GFX9_MI_MATH_ALU_INSTRUCTION_Operand1_bits 10 #define GFX8_MI_MATH_ALU_INSTRUCTION_Operand1_bits 10 #define GFX75_MI_MATH_ALU_INSTRUCTION_Operand1_bits 10 static inline uint32_t ATTRIBUTE_PURE MI_MATH_ALU_INSTRUCTION_Operand1_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 10; case 120: return 10; case 110: return 10; case 90: return 10; case 80: return 10; case 75: return 10; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_MATH_ALU_INSTRUCTION_Operand1_start 10 #define GFX12_MI_MATH_ALU_INSTRUCTION_Operand1_start 10 #define GFX11_MI_MATH_ALU_INSTRUCTION_Operand1_start 10 #define GFX9_MI_MATH_ALU_INSTRUCTION_Operand1_start 10 #define GFX8_MI_MATH_ALU_INSTRUCTION_Operand1_start 10 #define GFX75_MI_MATH_ALU_INSTRUCTION_Operand1_start 10 static inline uint32_t ATTRIBUTE_PURE MI_MATH_ALU_INSTRUCTION_Operand1_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 10; case 120: return 10; case 110: return 10; case 90: return 10; case 80: return 10; case 75: return 10; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_MATH_ALU_INSTRUCTION::Operand 2 */ #define GFX125_MI_MATH_ALU_INSTRUCTION_Operand2_bits 10 #define GFX12_MI_MATH_ALU_INSTRUCTION_Operand2_bits 10 #define GFX11_MI_MATH_ALU_INSTRUCTION_Operand2_bits 10 #define GFX9_MI_MATH_ALU_INSTRUCTION_Operand2_bits 10 #define GFX8_MI_MATH_ALU_INSTRUCTION_Operand2_bits 10 #define GFX75_MI_MATH_ALU_INSTRUCTION_Operand2_bits 10 static inline uint32_t ATTRIBUTE_PURE MI_MATH_ALU_INSTRUCTION_Operand2_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 10; case 120: return 10; case 110: return 10; case 90: return 10; case 80: return 10; case 75: return 10; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_MATH_ALU_INSTRUCTION_Operand2_start 0 #define GFX12_MI_MATH_ALU_INSTRUCTION_Operand2_start 0 #define GFX11_MI_MATH_ALU_INSTRUCTION_Operand2_start 0 #define GFX9_MI_MATH_ALU_INSTRUCTION_Operand2_start 0 #define GFX8_MI_MATH_ALU_INSTRUCTION_Operand2_start 0 #define GFX75_MI_MATH_ALU_INSTRUCTION_Operand2_start 0 static inline uint32_t ATTRIBUTE_PURE MI_MATH_ALU_INSTRUCTION_Operand2_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_NOOP */ #define GFX125_MI_NOOP_length 1 #define GFX12_MI_NOOP_length 1 #define GFX11_MI_NOOP_length 1 #define GFX9_MI_NOOP_length 1 #define GFX8_MI_NOOP_length 1 #define GFX75_MI_NOOP_length 1 #define GFX7_MI_NOOP_length 1 #define GFX6_MI_NOOP_length 1 static inline uint32_t ATTRIBUTE_PURE MI_NOOP_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_NOOP::Command Type */ #define GFX125_MI_NOOP_CommandType_bits 3 #define GFX12_MI_NOOP_CommandType_bits 3 #define GFX11_MI_NOOP_CommandType_bits 3 #define GFX9_MI_NOOP_CommandType_bits 3 #define GFX8_MI_NOOP_CommandType_bits 3 #define GFX75_MI_NOOP_CommandType_bits 3 #define GFX7_MI_NOOP_CommandType_bits 3 #define GFX6_MI_NOOP_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE MI_NOOP_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_NOOP_CommandType_start 29 #define GFX12_MI_NOOP_CommandType_start 29 #define GFX11_MI_NOOP_CommandType_start 29 #define GFX9_MI_NOOP_CommandType_start 29 #define GFX8_MI_NOOP_CommandType_start 29 #define GFX75_MI_NOOP_CommandType_start 29 #define GFX7_MI_NOOP_CommandType_start 29 #define GFX6_MI_NOOP_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE MI_NOOP_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 29; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_NOOP::Identification Number */ #define GFX125_MI_NOOP_IdentificationNumber_bits 22 #define GFX12_MI_NOOP_IdentificationNumber_bits 22 #define GFX11_MI_NOOP_IdentificationNumber_bits 22 #define GFX9_MI_NOOP_IdentificationNumber_bits 22 #define GFX8_MI_NOOP_IdentificationNumber_bits 22 #define GFX75_MI_NOOP_IdentificationNumber_bits 22 #define GFX7_MI_NOOP_IdentificationNumber_bits 22 #define GFX6_MI_NOOP_IdentificationNumber_bits 22 static inline uint32_t ATTRIBUTE_PURE MI_NOOP_IdentificationNumber_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 22; case 120: return 22; case 110: return 22; case 90: return 22; case 80: return 22; case 75: return 22; case 70: return 22; case 60: return 22; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_NOOP_IdentificationNumber_start 0 #define GFX12_MI_NOOP_IdentificationNumber_start 0 #define GFX11_MI_NOOP_IdentificationNumber_start 0 #define GFX9_MI_NOOP_IdentificationNumber_start 0 #define GFX8_MI_NOOP_IdentificationNumber_start 0 #define GFX75_MI_NOOP_IdentificationNumber_start 0 #define GFX7_MI_NOOP_IdentificationNumber_start 0 #define GFX6_MI_NOOP_IdentificationNumber_start 0 static inline uint32_t ATTRIBUTE_PURE MI_NOOP_IdentificationNumber_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_NOOP::Identification Number Register Write Enable */ #define GFX125_MI_NOOP_IdentificationNumberRegisterWriteEnable_bits 1 #define GFX12_MI_NOOP_IdentificationNumberRegisterWriteEnable_bits 1 #define GFX11_MI_NOOP_IdentificationNumberRegisterWriteEnable_bits 1 #define GFX9_MI_NOOP_IdentificationNumberRegisterWriteEnable_bits 1 #define GFX8_MI_NOOP_IdentificationNumberRegisterWriteEnable_bits 1 #define GFX75_MI_NOOP_IdentificationNumberRegisterWriteEnable_bits 1 #define GFX7_MI_NOOP_IdentificationNumberRegisterWriteEnable_bits 1 #define GFX6_MI_NOOP_IdentificationNumberRegisterWriteEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_NOOP_IdentificationNumberRegisterWriteEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_NOOP_IdentificationNumberRegisterWriteEnable_start 22 #define GFX12_MI_NOOP_IdentificationNumberRegisterWriteEnable_start 22 #define GFX11_MI_NOOP_IdentificationNumberRegisterWriteEnable_start 22 #define GFX9_MI_NOOP_IdentificationNumberRegisterWriteEnable_start 22 #define GFX8_MI_NOOP_IdentificationNumberRegisterWriteEnable_start 22 #define GFX75_MI_NOOP_IdentificationNumberRegisterWriteEnable_start 22 #define GFX7_MI_NOOP_IdentificationNumberRegisterWriteEnable_start 22 #define GFX6_MI_NOOP_IdentificationNumberRegisterWriteEnable_start 22 static inline uint32_t ATTRIBUTE_PURE MI_NOOP_IdentificationNumberRegisterWriteEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 22; case 120: return 22; case 110: return 22; case 90: return 22; case 80: return 22; case 75: return 22; case 70: return 22; case 60: return 22; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_NOOP::MI Command Opcode */ #define GFX125_MI_NOOP_MICommandOpcode_bits 6 #define GFX12_MI_NOOP_MICommandOpcode_bits 6 #define GFX11_MI_NOOP_MICommandOpcode_bits 6 #define GFX9_MI_NOOP_MICommandOpcode_bits 6 #define GFX8_MI_NOOP_MICommandOpcode_bits 6 #define GFX75_MI_NOOP_MICommandOpcode_bits 6 #define GFX7_MI_NOOP_MICommandOpcode_bits 6 #define GFX6_MI_NOOP_MICommandOpcode_bits 6 static inline uint32_t ATTRIBUTE_PURE MI_NOOP_MICommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 6; case 60: return 6; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_NOOP_MICommandOpcode_start 23 #define GFX12_MI_NOOP_MICommandOpcode_start 23 #define GFX11_MI_NOOP_MICommandOpcode_start 23 #define GFX9_MI_NOOP_MICommandOpcode_start 23 #define GFX8_MI_NOOP_MICommandOpcode_start 23 #define GFX75_MI_NOOP_MICommandOpcode_start 23 #define GFX7_MI_NOOP_MICommandOpcode_start 23 #define GFX6_MI_NOOP_MICommandOpcode_start 23 static inline uint32_t ATTRIBUTE_PURE MI_NOOP_MICommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 23; case 120: return 23; case 110: return 23; case 90: return 23; case 80: return 23; case 75: return 23; case 70: return 23; case 60: return 23; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_PREDICATE */ #define GFX125_MI_PREDICATE_length 1 #define GFX12_MI_PREDICATE_length 1 #define GFX11_MI_PREDICATE_length 1 #define GFX9_MI_PREDICATE_length 1 #define GFX8_MI_PREDICATE_length 1 #define GFX75_MI_PREDICATE_length 1 #define GFX7_MI_PREDICATE_length 1 static inline uint32_t ATTRIBUTE_PURE MI_PREDICATE_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_PREDICATE::Combine Operation */ #define GFX125_MI_PREDICATE_CombineOperation_bits 2 #define GFX12_MI_PREDICATE_CombineOperation_bits 2 #define GFX11_MI_PREDICATE_CombineOperation_bits 2 #define GFX9_MI_PREDICATE_CombineOperation_bits 2 #define GFX8_MI_PREDICATE_CombineOperation_bits 2 #define GFX75_MI_PREDICATE_CombineOperation_bits 2 #define GFX7_MI_PREDICATE_CombineOperation_bits 2 static inline uint32_t ATTRIBUTE_PURE MI_PREDICATE_CombineOperation_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_PREDICATE_CombineOperation_start 3 #define GFX12_MI_PREDICATE_CombineOperation_start 3 #define GFX11_MI_PREDICATE_CombineOperation_start 3 #define GFX9_MI_PREDICATE_CombineOperation_start 3 #define GFX8_MI_PREDICATE_CombineOperation_start 3 #define GFX75_MI_PREDICATE_CombineOperation_start 3 #define GFX7_MI_PREDICATE_CombineOperation_start 3 static inline uint32_t ATTRIBUTE_PURE MI_PREDICATE_CombineOperation_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_PREDICATE::Command Type */ #define GFX125_MI_PREDICATE_CommandType_bits 3 #define GFX12_MI_PREDICATE_CommandType_bits 3 #define GFX11_MI_PREDICATE_CommandType_bits 3 #define GFX9_MI_PREDICATE_CommandType_bits 3 #define GFX8_MI_PREDICATE_CommandType_bits 3 #define GFX75_MI_PREDICATE_CommandType_bits 3 #define GFX7_MI_PREDICATE_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE MI_PREDICATE_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_PREDICATE_CommandType_start 29 #define GFX12_MI_PREDICATE_CommandType_start 29 #define GFX11_MI_PREDICATE_CommandType_start 29 #define GFX9_MI_PREDICATE_CommandType_start 29 #define GFX8_MI_PREDICATE_CommandType_start 29 #define GFX75_MI_PREDICATE_CommandType_start 29 #define GFX7_MI_PREDICATE_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE MI_PREDICATE_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_PREDICATE::Compare Operation */ #define GFX125_MI_PREDICATE_CompareOperation_bits 2 #define GFX12_MI_PREDICATE_CompareOperation_bits 2 #define GFX11_MI_PREDICATE_CompareOperation_bits 2 #define GFX9_MI_PREDICATE_CompareOperation_bits 2 #define GFX8_MI_PREDICATE_CompareOperation_bits 2 #define GFX75_MI_PREDICATE_CompareOperation_bits 2 #define GFX7_MI_PREDICATE_CompareOperation_bits 2 static inline uint32_t ATTRIBUTE_PURE MI_PREDICATE_CompareOperation_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_PREDICATE_CompareOperation_start 0 #define GFX12_MI_PREDICATE_CompareOperation_start 0 #define GFX11_MI_PREDICATE_CompareOperation_start 0 #define GFX9_MI_PREDICATE_CompareOperation_start 0 #define GFX8_MI_PREDICATE_CompareOperation_start 0 #define GFX75_MI_PREDICATE_CompareOperation_start 0 #define GFX7_MI_PREDICATE_CompareOperation_start 0 static inline uint32_t ATTRIBUTE_PURE MI_PREDICATE_CompareOperation_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_PREDICATE::Load Operation */ #define GFX125_MI_PREDICATE_LoadOperation_bits 2 #define GFX12_MI_PREDICATE_LoadOperation_bits 2 #define GFX11_MI_PREDICATE_LoadOperation_bits 2 #define GFX9_MI_PREDICATE_LoadOperation_bits 2 #define GFX8_MI_PREDICATE_LoadOperation_bits 2 #define GFX75_MI_PREDICATE_LoadOperation_bits 2 #define GFX7_MI_PREDICATE_LoadOperation_bits 2 static inline uint32_t ATTRIBUTE_PURE MI_PREDICATE_LoadOperation_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_PREDICATE_LoadOperation_start 6 #define GFX12_MI_PREDICATE_LoadOperation_start 6 #define GFX11_MI_PREDICATE_LoadOperation_start 6 #define GFX9_MI_PREDICATE_LoadOperation_start 6 #define GFX8_MI_PREDICATE_LoadOperation_start 6 #define GFX75_MI_PREDICATE_LoadOperation_start 6 #define GFX7_MI_PREDICATE_LoadOperation_start 6 static inline uint32_t ATTRIBUTE_PURE MI_PREDICATE_LoadOperation_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 6; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_PREDICATE::MI Command Opcode */ #define GFX125_MI_PREDICATE_MICommandOpcode_bits 6 #define GFX12_MI_PREDICATE_MICommandOpcode_bits 6 #define GFX11_MI_PREDICATE_MICommandOpcode_bits 6 #define GFX9_MI_PREDICATE_MICommandOpcode_bits 6 #define GFX8_MI_PREDICATE_MICommandOpcode_bits 6 #define GFX75_MI_PREDICATE_MICommandOpcode_bits 6 #define GFX7_MI_PREDICATE_MICommandOpcode_bits 6 static inline uint32_t ATTRIBUTE_PURE MI_PREDICATE_MICommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 6; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_PREDICATE_MICommandOpcode_start 23 #define GFX12_MI_PREDICATE_MICommandOpcode_start 23 #define GFX11_MI_PREDICATE_MICommandOpcode_start 23 #define GFX9_MI_PREDICATE_MICommandOpcode_start 23 #define GFX8_MI_PREDICATE_MICommandOpcode_start 23 #define GFX75_MI_PREDICATE_MICommandOpcode_start 23 #define GFX7_MI_PREDICATE_MICommandOpcode_start 23 static inline uint32_t ATTRIBUTE_PURE MI_PREDICATE_MICommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 23; case 120: return 23; case 110: return 23; case 90: return 23; case 80: return 23; case 75: return 23; case 70: return 23; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_REPORT_HEAD */ #define GFX125_MI_REPORT_HEAD_length 1 #define GFX12_MI_REPORT_HEAD_length 1 #define GFX11_MI_REPORT_HEAD_length 1 #define GFX9_MI_REPORT_HEAD_length 1 #define GFX8_MI_REPORT_HEAD_length 1 #define GFX75_MI_REPORT_HEAD_length 1 #define GFX7_MI_REPORT_HEAD_length 1 #define GFX6_MI_REPORT_HEAD_length 1 static inline uint32_t ATTRIBUTE_PURE MI_REPORT_HEAD_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_REPORT_HEAD::Command Type */ #define GFX125_MI_REPORT_HEAD_CommandType_bits 3 #define GFX12_MI_REPORT_HEAD_CommandType_bits 3 #define GFX11_MI_REPORT_HEAD_CommandType_bits 3 #define GFX9_MI_REPORT_HEAD_CommandType_bits 3 #define GFX8_MI_REPORT_HEAD_CommandType_bits 3 #define GFX75_MI_REPORT_HEAD_CommandType_bits 3 #define GFX7_MI_REPORT_HEAD_CommandType_bits 3 #define GFX6_MI_REPORT_HEAD_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE MI_REPORT_HEAD_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_REPORT_HEAD_CommandType_start 29 #define GFX12_MI_REPORT_HEAD_CommandType_start 29 #define GFX11_MI_REPORT_HEAD_CommandType_start 29 #define GFX9_MI_REPORT_HEAD_CommandType_start 29 #define GFX8_MI_REPORT_HEAD_CommandType_start 29 #define GFX75_MI_REPORT_HEAD_CommandType_start 29 #define GFX7_MI_REPORT_HEAD_CommandType_start 29 #define GFX6_MI_REPORT_HEAD_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE MI_REPORT_HEAD_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 29; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_REPORT_HEAD::MI Command Opcode */ #define GFX125_MI_REPORT_HEAD_MICommandOpcode_bits 6 #define GFX12_MI_REPORT_HEAD_MICommandOpcode_bits 6 #define GFX11_MI_REPORT_HEAD_MICommandOpcode_bits 6 #define GFX9_MI_REPORT_HEAD_MICommandOpcode_bits 6 #define GFX8_MI_REPORT_HEAD_MICommandOpcode_bits 6 #define GFX75_MI_REPORT_HEAD_MICommandOpcode_bits 6 #define GFX7_MI_REPORT_HEAD_MICommandOpcode_bits 6 #define GFX6_MI_REPORT_HEAD_MICommandOpcode_bits 6 static inline uint32_t ATTRIBUTE_PURE MI_REPORT_HEAD_MICommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 6; case 60: return 6; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_REPORT_HEAD_MICommandOpcode_start 23 #define GFX12_MI_REPORT_HEAD_MICommandOpcode_start 23 #define GFX11_MI_REPORT_HEAD_MICommandOpcode_start 23 #define GFX9_MI_REPORT_HEAD_MICommandOpcode_start 23 #define GFX8_MI_REPORT_HEAD_MICommandOpcode_start 23 #define GFX75_MI_REPORT_HEAD_MICommandOpcode_start 23 #define GFX7_MI_REPORT_HEAD_MICommandOpcode_start 23 #define GFX6_MI_REPORT_HEAD_MICommandOpcode_start 23 static inline uint32_t ATTRIBUTE_PURE MI_REPORT_HEAD_MICommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 23; case 120: return 23; case 110: return 23; case 90: return 23; case 80: return 23; case 75: return 23; case 70: return 23; case 60: return 23; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_REPORT_PERF_COUNT */ #define GFX125_MI_REPORT_PERF_COUNT_length 4 #define GFX12_MI_REPORT_PERF_COUNT_length 4 #define GFX11_MI_REPORT_PERF_COUNT_length 4 #define GFX9_MI_REPORT_PERF_COUNT_length 4 #define GFX8_MI_REPORT_PERF_COUNT_length 4 #define GFX75_MI_REPORT_PERF_COUNT_length 3 #define GFX7_MI_REPORT_PERF_COUNT_length 3 static inline uint32_t ATTRIBUTE_PURE MI_REPORT_PERF_COUNT_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_REPORT_PERF_COUNT::Command Type */ #define GFX125_MI_REPORT_PERF_COUNT_CommandType_bits 3 #define GFX12_MI_REPORT_PERF_COUNT_CommandType_bits 3 #define GFX11_MI_REPORT_PERF_COUNT_CommandType_bits 3 #define GFX9_MI_REPORT_PERF_COUNT_CommandType_bits 3 #define GFX8_MI_REPORT_PERF_COUNT_CommandType_bits 3 #define GFX75_MI_REPORT_PERF_COUNT_CommandType_bits 3 #define GFX7_MI_REPORT_PERF_COUNT_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE MI_REPORT_PERF_COUNT_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_REPORT_PERF_COUNT_CommandType_start 29 #define GFX12_MI_REPORT_PERF_COUNT_CommandType_start 29 #define GFX11_MI_REPORT_PERF_COUNT_CommandType_start 29 #define GFX9_MI_REPORT_PERF_COUNT_CommandType_start 29 #define GFX8_MI_REPORT_PERF_COUNT_CommandType_start 29 #define GFX75_MI_REPORT_PERF_COUNT_CommandType_start 29 #define GFX7_MI_REPORT_PERF_COUNT_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE MI_REPORT_PERF_COUNT_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_REPORT_PERF_COUNT::Core Mode Enable */ #define GFX125_MI_REPORT_PERF_COUNT_CoreModeEnable_bits 1 #define GFX12_MI_REPORT_PERF_COUNT_CoreModeEnable_bits 1 #define GFX11_MI_REPORT_PERF_COUNT_CoreModeEnable_bits 1 #define GFX9_MI_REPORT_PERF_COUNT_CoreModeEnable_bits 1 #define GFX8_MI_REPORT_PERF_COUNT_CoreModeEnable_bits 1 #define GFX75_MI_REPORT_PERF_COUNT_CoreModeEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_REPORT_PERF_COUNT_CoreModeEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_REPORT_PERF_COUNT_CoreModeEnable_start 36 #define GFX12_MI_REPORT_PERF_COUNT_CoreModeEnable_start 36 #define GFX11_MI_REPORT_PERF_COUNT_CoreModeEnable_start 36 #define GFX9_MI_REPORT_PERF_COUNT_CoreModeEnable_start 36 #define GFX8_MI_REPORT_PERF_COUNT_CoreModeEnable_start 36 #define GFX75_MI_REPORT_PERF_COUNT_CoreModeEnable_start 36 static inline uint32_t ATTRIBUTE_PURE MI_REPORT_PERF_COUNT_CoreModeEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 36; case 120: return 36; case 110: return 36; case 90: return 36; case 80: return 36; case 75: return 36; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_REPORT_PERF_COUNT::DWord Length */ #define GFX125_MI_REPORT_PERF_COUNT_DWordLength_bits 6 #define GFX12_MI_REPORT_PERF_COUNT_DWordLength_bits 6 #define GFX11_MI_REPORT_PERF_COUNT_DWordLength_bits 6 #define GFX9_MI_REPORT_PERF_COUNT_DWordLength_bits 6 #define GFX8_MI_REPORT_PERF_COUNT_DWordLength_bits 6 #define GFX75_MI_REPORT_PERF_COUNT_DWordLength_bits 6 #define GFX7_MI_REPORT_PERF_COUNT_DWordLength_bits 6 static inline uint32_t ATTRIBUTE_PURE MI_REPORT_PERF_COUNT_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 6; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_REPORT_PERF_COUNT_DWordLength_start 0 #define GFX12_MI_REPORT_PERF_COUNT_DWordLength_start 0 #define GFX11_MI_REPORT_PERF_COUNT_DWordLength_start 0 #define GFX9_MI_REPORT_PERF_COUNT_DWordLength_start 0 #define GFX8_MI_REPORT_PERF_COUNT_DWordLength_start 0 #define GFX75_MI_REPORT_PERF_COUNT_DWordLength_start 0 #define GFX7_MI_REPORT_PERF_COUNT_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE MI_REPORT_PERF_COUNT_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_REPORT_PERF_COUNT::MI Command Opcode */ #define GFX125_MI_REPORT_PERF_COUNT_MICommandOpcode_bits 6 #define GFX12_MI_REPORT_PERF_COUNT_MICommandOpcode_bits 6 #define GFX11_MI_REPORT_PERF_COUNT_MICommandOpcode_bits 6 #define GFX9_MI_REPORT_PERF_COUNT_MICommandOpcode_bits 6 #define GFX8_MI_REPORT_PERF_COUNT_MICommandOpcode_bits 6 #define GFX75_MI_REPORT_PERF_COUNT_MICommandOpcode_bits 6 #define GFX7_MI_REPORT_PERF_COUNT_MICommandOpcode_bits 6 static inline uint32_t ATTRIBUTE_PURE MI_REPORT_PERF_COUNT_MICommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 6; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_REPORT_PERF_COUNT_MICommandOpcode_start 23 #define GFX12_MI_REPORT_PERF_COUNT_MICommandOpcode_start 23 #define GFX11_MI_REPORT_PERF_COUNT_MICommandOpcode_start 23 #define GFX9_MI_REPORT_PERF_COUNT_MICommandOpcode_start 23 #define GFX8_MI_REPORT_PERF_COUNT_MICommandOpcode_start 23 #define GFX75_MI_REPORT_PERF_COUNT_MICommandOpcode_start 23 #define GFX7_MI_REPORT_PERF_COUNT_MICommandOpcode_start 23 static inline uint32_t ATTRIBUTE_PURE MI_REPORT_PERF_COUNT_MICommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 23; case 120: return 23; case 110: return 23; case 90: return 23; case 80: return 23; case 75: return 23; case 70: return 23; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_REPORT_PERF_COUNT::Memory Address */ #define GFX125_MI_REPORT_PERF_COUNT_MemoryAddress_bits 58 #define GFX12_MI_REPORT_PERF_COUNT_MemoryAddress_bits 58 #define GFX11_MI_REPORT_PERF_COUNT_MemoryAddress_bits 58 #define GFX9_MI_REPORT_PERF_COUNT_MemoryAddress_bits 58 #define GFX8_MI_REPORT_PERF_COUNT_MemoryAddress_bits 58 #define GFX75_MI_REPORT_PERF_COUNT_MemoryAddress_bits 26 #define GFX7_MI_REPORT_PERF_COUNT_MemoryAddress_bits 26 static inline uint32_t ATTRIBUTE_PURE MI_REPORT_PERF_COUNT_MemoryAddress_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 58; case 120: return 58; case 110: return 58; case 90: return 58; case 80: return 58; case 75: return 26; case 70: return 26; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_REPORT_PERF_COUNT_MemoryAddress_start 38 #define GFX12_MI_REPORT_PERF_COUNT_MemoryAddress_start 38 #define GFX11_MI_REPORT_PERF_COUNT_MemoryAddress_start 38 #define GFX9_MI_REPORT_PERF_COUNT_MemoryAddress_start 38 #define GFX8_MI_REPORT_PERF_COUNT_MemoryAddress_start 38 #define GFX75_MI_REPORT_PERF_COUNT_MemoryAddress_start 38 #define GFX7_MI_REPORT_PERF_COUNT_MemoryAddress_start 38 static inline uint32_t ATTRIBUTE_PURE MI_REPORT_PERF_COUNT_MemoryAddress_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 38; case 120: return 38; case 110: return 38; case 90: return 38; case 80: return 38; case 75: return 38; case 70: return 38; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_REPORT_PERF_COUNT::Report ID */ #define GFX125_MI_REPORT_PERF_COUNT_ReportID_bits 32 #define GFX12_MI_REPORT_PERF_COUNT_ReportID_bits 32 #define GFX11_MI_REPORT_PERF_COUNT_ReportID_bits 32 #define GFX9_MI_REPORT_PERF_COUNT_ReportID_bits 32 #define GFX8_MI_REPORT_PERF_COUNT_ReportID_bits 32 #define GFX75_MI_REPORT_PERF_COUNT_ReportID_bits 32 #define GFX7_MI_REPORT_PERF_COUNT_ReportID_bits 32 static inline uint32_t ATTRIBUTE_PURE MI_REPORT_PERF_COUNT_ReportID_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_REPORT_PERF_COUNT_ReportID_start 96 #define GFX12_MI_REPORT_PERF_COUNT_ReportID_start 96 #define GFX11_MI_REPORT_PERF_COUNT_ReportID_start 96 #define GFX9_MI_REPORT_PERF_COUNT_ReportID_start 96 #define GFX8_MI_REPORT_PERF_COUNT_ReportID_start 96 #define GFX75_MI_REPORT_PERF_COUNT_ReportID_start 64 #define GFX7_MI_REPORT_PERF_COUNT_ReportID_start 64 static inline uint32_t ATTRIBUTE_PURE MI_REPORT_PERF_COUNT_ReportID_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 96; case 120: return 96; case 110: return 96; case 90: return 96; case 80: return 96; case 75: return 64; case 70: return 64; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_REPORT_PERF_COUNT::Use Global GTT */ #define GFX125_MI_REPORT_PERF_COUNT_UseGlobalGTT_bits 1 #define GFX12_MI_REPORT_PERF_COUNT_UseGlobalGTT_bits 1 #define GFX11_MI_REPORT_PERF_COUNT_UseGlobalGTT_bits 1 #define GFX9_MI_REPORT_PERF_COUNT_UseGlobalGTT_bits 1 #define GFX8_MI_REPORT_PERF_COUNT_UseGlobalGTT_bits 1 #define GFX75_MI_REPORT_PERF_COUNT_UseGlobalGTT_bits 1 #define GFX7_MI_REPORT_PERF_COUNT_UseGlobalGTT_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_REPORT_PERF_COUNT_UseGlobalGTT_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_REPORT_PERF_COUNT_UseGlobalGTT_start 32 #define GFX12_MI_REPORT_PERF_COUNT_UseGlobalGTT_start 32 #define GFX11_MI_REPORT_PERF_COUNT_UseGlobalGTT_start 32 #define GFX9_MI_REPORT_PERF_COUNT_UseGlobalGTT_start 32 #define GFX8_MI_REPORT_PERF_COUNT_UseGlobalGTT_start 32 #define GFX75_MI_REPORT_PERF_COUNT_UseGlobalGTT_start 32 #define GFX7_MI_REPORT_PERF_COUNT_UseGlobalGTT_start 32 static inline uint32_t ATTRIBUTE_PURE MI_REPORT_PERF_COUNT_UseGlobalGTT_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_RS_CONTEXT */ #define GFX125_MI_RS_CONTEXT_length 1 #define GFX12_MI_RS_CONTEXT_length 1 #define GFX11_MI_RS_CONTEXT_length 1 #define GFX9_MI_RS_CONTEXT_length 1 #define GFX8_MI_RS_CONTEXT_length 1 #define GFX75_MI_RS_CONTEXT_length 1 static inline uint32_t ATTRIBUTE_PURE MI_RS_CONTEXT_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_RS_CONTEXT::Command Type */ #define GFX125_MI_RS_CONTEXT_CommandType_bits 3 #define GFX12_MI_RS_CONTEXT_CommandType_bits 3 #define GFX11_MI_RS_CONTEXT_CommandType_bits 3 #define GFX9_MI_RS_CONTEXT_CommandType_bits 3 #define GFX8_MI_RS_CONTEXT_CommandType_bits 3 #define GFX75_MI_RS_CONTEXT_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE MI_RS_CONTEXT_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_RS_CONTEXT_CommandType_start 29 #define GFX12_MI_RS_CONTEXT_CommandType_start 29 #define GFX11_MI_RS_CONTEXT_CommandType_start 29 #define GFX9_MI_RS_CONTEXT_CommandType_start 29 #define GFX8_MI_RS_CONTEXT_CommandType_start 29 #define GFX75_MI_RS_CONTEXT_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE MI_RS_CONTEXT_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_RS_CONTEXT::MI Command Opcode */ #define GFX125_MI_RS_CONTEXT_MICommandOpcode_bits 6 #define GFX12_MI_RS_CONTEXT_MICommandOpcode_bits 6 #define GFX11_MI_RS_CONTEXT_MICommandOpcode_bits 6 #define GFX9_MI_RS_CONTEXT_MICommandOpcode_bits 6 #define GFX8_MI_RS_CONTEXT_MICommandOpcode_bits 6 #define GFX75_MI_RS_CONTEXT_MICommandOpcode_bits 6 static inline uint32_t ATTRIBUTE_PURE MI_RS_CONTEXT_MICommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_RS_CONTEXT_MICommandOpcode_start 23 #define GFX12_MI_RS_CONTEXT_MICommandOpcode_start 23 #define GFX11_MI_RS_CONTEXT_MICommandOpcode_start 23 #define GFX9_MI_RS_CONTEXT_MICommandOpcode_start 23 #define GFX8_MI_RS_CONTEXT_MICommandOpcode_start 23 #define GFX75_MI_RS_CONTEXT_MICommandOpcode_start 23 static inline uint32_t ATTRIBUTE_PURE MI_RS_CONTEXT_MICommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 23; case 120: return 23; case 110: return 23; case 90: return 23; case 80: return 23; case 75: return 23; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_RS_CONTEXT::Resource Streamer Save */ #define GFX125_MI_RS_CONTEXT_ResourceStreamerSave_bits 1 #define GFX12_MI_RS_CONTEXT_ResourceStreamerSave_bits 1 #define GFX11_MI_RS_CONTEXT_ResourceStreamerSave_bits 1 #define GFX9_MI_RS_CONTEXT_ResourceStreamerSave_bits 1 #define GFX8_MI_RS_CONTEXT_ResourceStreamerSave_bits 1 #define GFX75_MI_RS_CONTEXT_ResourceStreamerSave_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_RS_CONTEXT_ResourceStreamerSave_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_RS_CONTEXT_ResourceStreamerSave_start 0 #define GFX12_MI_RS_CONTEXT_ResourceStreamerSave_start 0 #define GFX11_MI_RS_CONTEXT_ResourceStreamerSave_start 0 #define GFX9_MI_RS_CONTEXT_ResourceStreamerSave_start 0 #define GFX8_MI_RS_CONTEXT_ResourceStreamerSave_start 0 #define GFX75_MI_RS_CONTEXT_ResourceStreamerSave_start 0 static inline uint32_t ATTRIBUTE_PURE MI_RS_CONTEXT_ResourceStreamerSave_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_RS_CONTROL */ #define GFX125_MI_RS_CONTROL_length 1 #define GFX12_MI_RS_CONTROL_length 1 #define GFX11_MI_RS_CONTROL_length 1 #define GFX9_MI_RS_CONTROL_length 1 #define GFX8_MI_RS_CONTROL_length 1 #define GFX75_MI_RS_CONTROL_length 1 static inline uint32_t ATTRIBUTE_PURE MI_RS_CONTROL_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_RS_CONTROL::Command Type */ #define GFX125_MI_RS_CONTROL_CommandType_bits 3 #define GFX12_MI_RS_CONTROL_CommandType_bits 3 #define GFX11_MI_RS_CONTROL_CommandType_bits 3 #define GFX9_MI_RS_CONTROL_CommandType_bits 3 #define GFX8_MI_RS_CONTROL_CommandType_bits 3 #define GFX75_MI_RS_CONTROL_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE MI_RS_CONTROL_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_RS_CONTROL_CommandType_start 29 #define GFX12_MI_RS_CONTROL_CommandType_start 29 #define GFX11_MI_RS_CONTROL_CommandType_start 29 #define GFX9_MI_RS_CONTROL_CommandType_start 29 #define GFX8_MI_RS_CONTROL_CommandType_start 29 #define GFX75_MI_RS_CONTROL_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE MI_RS_CONTROL_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_RS_CONTROL::MI Command Opcode */ #define GFX125_MI_RS_CONTROL_MICommandOpcode_bits 6 #define GFX12_MI_RS_CONTROL_MICommandOpcode_bits 6 #define GFX11_MI_RS_CONTROL_MICommandOpcode_bits 6 #define GFX9_MI_RS_CONTROL_MICommandOpcode_bits 6 #define GFX8_MI_RS_CONTROL_MICommandOpcode_bits 6 #define GFX75_MI_RS_CONTROL_MICommandOpcode_bits 6 static inline uint32_t ATTRIBUTE_PURE MI_RS_CONTROL_MICommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_RS_CONTROL_MICommandOpcode_start 23 #define GFX12_MI_RS_CONTROL_MICommandOpcode_start 23 #define GFX11_MI_RS_CONTROL_MICommandOpcode_start 23 #define GFX9_MI_RS_CONTROL_MICommandOpcode_start 23 #define GFX8_MI_RS_CONTROL_MICommandOpcode_start 23 #define GFX75_MI_RS_CONTROL_MICommandOpcode_start 23 static inline uint32_t ATTRIBUTE_PURE MI_RS_CONTROL_MICommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 23; case 120: return 23; case 110: return 23; case 90: return 23; case 80: return 23; case 75: return 23; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_RS_CONTROL::Resource Streamer Control */ #define GFX125_MI_RS_CONTROL_ResourceStreamerControl_bits 1 #define GFX12_MI_RS_CONTROL_ResourceStreamerControl_bits 1 #define GFX11_MI_RS_CONTROL_ResourceStreamerControl_bits 1 #define GFX9_MI_RS_CONTROL_ResourceStreamerControl_bits 1 #define GFX8_MI_RS_CONTROL_ResourceStreamerControl_bits 1 #define GFX75_MI_RS_CONTROL_ResourceStreamerControl_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_RS_CONTROL_ResourceStreamerControl_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_RS_CONTROL_ResourceStreamerControl_start 0 #define GFX12_MI_RS_CONTROL_ResourceStreamerControl_start 0 #define GFX11_MI_RS_CONTROL_ResourceStreamerControl_start 0 #define GFX9_MI_RS_CONTROL_ResourceStreamerControl_start 0 #define GFX8_MI_RS_CONTROL_ResourceStreamerControl_start 0 #define GFX75_MI_RS_CONTROL_ResourceStreamerControl_start 0 static inline uint32_t ATTRIBUTE_PURE MI_RS_CONTROL_ResourceStreamerControl_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_RS_STORE_DATA_IMM */ #define GFX125_MI_RS_STORE_DATA_IMM_length 4 #define GFX12_MI_RS_STORE_DATA_IMM_length 4 #define GFX11_MI_RS_STORE_DATA_IMM_length 4 #define GFX9_MI_RS_STORE_DATA_IMM_length 4 #define GFX8_MI_RS_STORE_DATA_IMM_length 4 #define GFX75_MI_RS_STORE_DATA_IMM_length 4 static inline uint32_t ATTRIBUTE_PURE MI_RS_STORE_DATA_IMM_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 4; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_RS_STORE_DATA_IMM::Command Type */ #define GFX125_MI_RS_STORE_DATA_IMM_CommandType_bits 3 #define GFX12_MI_RS_STORE_DATA_IMM_CommandType_bits 3 #define GFX11_MI_RS_STORE_DATA_IMM_CommandType_bits 3 #define GFX9_MI_RS_STORE_DATA_IMM_CommandType_bits 3 #define GFX8_MI_RS_STORE_DATA_IMM_CommandType_bits 3 #define GFX75_MI_RS_STORE_DATA_IMM_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE MI_RS_STORE_DATA_IMM_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_RS_STORE_DATA_IMM_CommandType_start 29 #define GFX12_MI_RS_STORE_DATA_IMM_CommandType_start 29 #define GFX11_MI_RS_STORE_DATA_IMM_CommandType_start 29 #define GFX9_MI_RS_STORE_DATA_IMM_CommandType_start 29 #define GFX8_MI_RS_STORE_DATA_IMM_CommandType_start 29 #define GFX75_MI_RS_STORE_DATA_IMM_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE MI_RS_STORE_DATA_IMM_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_RS_STORE_DATA_IMM::Core Mode Enable */ #define GFX125_MI_RS_STORE_DATA_IMM_CoreModeEnable_bits 1 #define GFX12_MI_RS_STORE_DATA_IMM_CoreModeEnable_bits 1 #define GFX11_MI_RS_STORE_DATA_IMM_CoreModeEnable_bits 1 #define GFX9_MI_RS_STORE_DATA_IMM_CoreModeEnable_bits 1 #define GFX8_MI_RS_STORE_DATA_IMM_CoreModeEnable_bits 1 #define GFX75_MI_RS_STORE_DATA_IMM_CoreModeEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_RS_STORE_DATA_IMM_CoreModeEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_RS_STORE_DATA_IMM_CoreModeEnable_start 32 #define GFX12_MI_RS_STORE_DATA_IMM_CoreModeEnable_start 32 #define GFX11_MI_RS_STORE_DATA_IMM_CoreModeEnable_start 32 #define GFX9_MI_RS_STORE_DATA_IMM_CoreModeEnable_start 32 #define GFX8_MI_RS_STORE_DATA_IMM_CoreModeEnable_start 32 #define GFX75_MI_RS_STORE_DATA_IMM_CoreModeEnable_start 64 static inline uint32_t ATTRIBUTE_PURE MI_RS_STORE_DATA_IMM_CoreModeEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 64; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_RS_STORE_DATA_IMM::DWord Length */ #define GFX125_MI_RS_STORE_DATA_IMM_DWordLength_bits 8 #define GFX12_MI_RS_STORE_DATA_IMM_DWordLength_bits 8 #define GFX11_MI_RS_STORE_DATA_IMM_DWordLength_bits 8 #define GFX9_MI_RS_STORE_DATA_IMM_DWordLength_bits 8 #define GFX8_MI_RS_STORE_DATA_IMM_DWordLength_bits 8 #define GFX75_MI_RS_STORE_DATA_IMM_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE MI_RS_STORE_DATA_IMM_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_RS_STORE_DATA_IMM_DWordLength_start 0 #define GFX12_MI_RS_STORE_DATA_IMM_DWordLength_start 0 #define GFX11_MI_RS_STORE_DATA_IMM_DWordLength_start 0 #define GFX9_MI_RS_STORE_DATA_IMM_DWordLength_start 0 #define GFX8_MI_RS_STORE_DATA_IMM_DWordLength_start 0 #define GFX75_MI_RS_STORE_DATA_IMM_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE MI_RS_STORE_DATA_IMM_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_RS_STORE_DATA_IMM::Data DWord 0 */ #define GFX125_MI_RS_STORE_DATA_IMM_DataDWord0_bits 32 #define GFX12_MI_RS_STORE_DATA_IMM_DataDWord0_bits 32 #define GFX11_MI_RS_STORE_DATA_IMM_DataDWord0_bits 32 #define GFX9_MI_RS_STORE_DATA_IMM_DataDWord0_bits 32 #define GFX8_MI_RS_STORE_DATA_IMM_DataDWord0_bits 32 #define GFX75_MI_RS_STORE_DATA_IMM_DataDWord0_bits 32 static inline uint32_t ATTRIBUTE_PURE MI_RS_STORE_DATA_IMM_DataDWord0_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_RS_STORE_DATA_IMM_DataDWord0_start 96 #define GFX12_MI_RS_STORE_DATA_IMM_DataDWord0_start 96 #define GFX11_MI_RS_STORE_DATA_IMM_DataDWord0_start 96 #define GFX9_MI_RS_STORE_DATA_IMM_DataDWord0_start 96 #define GFX8_MI_RS_STORE_DATA_IMM_DataDWord0_start 96 #define GFX75_MI_RS_STORE_DATA_IMM_DataDWord0_start 96 static inline uint32_t ATTRIBUTE_PURE MI_RS_STORE_DATA_IMM_DataDWord0_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 96; case 120: return 96; case 110: return 96; case 90: return 96; case 80: return 96; case 75: return 96; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_RS_STORE_DATA_IMM::Destination Address */ #define GFX125_MI_RS_STORE_DATA_IMM_DestinationAddress_bits 62 #define GFX12_MI_RS_STORE_DATA_IMM_DestinationAddress_bits 62 #define GFX11_MI_RS_STORE_DATA_IMM_DestinationAddress_bits 62 #define GFX9_MI_RS_STORE_DATA_IMM_DestinationAddress_bits 62 #define GFX8_MI_RS_STORE_DATA_IMM_DestinationAddress_bits 62 #define GFX75_MI_RS_STORE_DATA_IMM_DestinationAddress_bits 30 static inline uint32_t ATTRIBUTE_PURE MI_RS_STORE_DATA_IMM_DestinationAddress_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 62; case 120: return 62; case 110: return 62; case 90: return 62; case 80: return 62; case 75: return 30; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_RS_STORE_DATA_IMM_DestinationAddress_start 34 #define GFX12_MI_RS_STORE_DATA_IMM_DestinationAddress_start 34 #define GFX11_MI_RS_STORE_DATA_IMM_DestinationAddress_start 34 #define GFX9_MI_RS_STORE_DATA_IMM_DestinationAddress_start 34 #define GFX8_MI_RS_STORE_DATA_IMM_DestinationAddress_start 34 #define GFX75_MI_RS_STORE_DATA_IMM_DestinationAddress_start 66 static inline uint32_t ATTRIBUTE_PURE MI_RS_STORE_DATA_IMM_DestinationAddress_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 34; case 120: return 34; case 110: return 34; case 90: return 34; case 80: return 34; case 75: return 66; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_RS_STORE_DATA_IMM::MI Command Opcode */ #define GFX125_MI_RS_STORE_DATA_IMM_MICommandOpcode_bits 6 #define GFX12_MI_RS_STORE_DATA_IMM_MICommandOpcode_bits 6 #define GFX11_MI_RS_STORE_DATA_IMM_MICommandOpcode_bits 6 #define GFX9_MI_RS_STORE_DATA_IMM_MICommandOpcode_bits 6 #define GFX8_MI_RS_STORE_DATA_IMM_MICommandOpcode_bits 6 #define GFX75_MI_RS_STORE_DATA_IMM_MICommandOpcode_bits 6 static inline uint32_t ATTRIBUTE_PURE MI_RS_STORE_DATA_IMM_MICommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_RS_STORE_DATA_IMM_MICommandOpcode_start 23 #define GFX12_MI_RS_STORE_DATA_IMM_MICommandOpcode_start 23 #define GFX11_MI_RS_STORE_DATA_IMM_MICommandOpcode_start 23 #define GFX9_MI_RS_STORE_DATA_IMM_MICommandOpcode_start 23 #define GFX8_MI_RS_STORE_DATA_IMM_MICommandOpcode_start 23 #define GFX75_MI_RS_STORE_DATA_IMM_MICommandOpcode_start 23 static inline uint32_t ATTRIBUTE_PURE MI_RS_STORE_DATA_IMM_MICommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 23; case 120: return 23; case 110: return 23; case 90: return 23; case 80: return 23; case 75: return 23; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_SEMAPHORE_MBOX */ #define GFX75_MI_SEMAPHORE_MBOX_length 3 #define GFX7_MI_SEMAPHORE_MBOX_length 3 #define GFX6_MI_SEMAPHORE_MBOX_length 3 static inline uint32_t ATTRIBUTE_PURE MI_SEMAPHORE_MBOX_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_SEMAPHORE_MBOX::Command Type */ #define GFX75_MI_SEMAPHORE_MBOX_CommandType_bits 3 #define GFX7_MI_SEMAPHORE_MBOX_CommandType_bits 3 #define GFX6_MI_SEMAPHORE_MBOX_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE MI_SEMAPHORE_MBOX_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_MI_SEMAPHORE_MBOX_CommandType_start 29 #define GFX7_MI_SEMAPHORE_MBOX_CommandType_start 29 #define GFX6_MI_SEMAPHORE_MBOX_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE MI_SEMAPHORE_MBOX_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 29; case 70: return 29; case 60: return 29; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_SEMAPHORE_MBOX::DWord Length */ #define GFX75_MI_SEMAPHORE_MBOX_DWordLength_bits 8 #define GFX7_MI_SEMAPHORE_MBOX_DWordLength_bits 8 #define GFX6_MI_SEMAPHORE_MBOX_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE MI_SEMAPHORE_MBOX_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_MI_SEMAPHORE_MBOX_DWordLength_start 0 #define GFX7_MI_SEMAPHORE_MBOX_DWordLength_start 0 #define GFX6_MI_SEMAPHORE_MBOX_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE MI_SEMAPHORE_MBOX_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_SEMAPHORE_MBOX::General Register Select */ #define GFX75_MI_SEMAPHORE_MBOX_GeneralRegisterSelect_bits 6 static inline uint32_t ATTRIBUTE_PURE MI_SEMAPHORE_MBOX_GeneralRegisterSelect_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 6; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_MI_SEMAPHORE_MBOX_GeneralRegisterSelect_start 8 static inline uint32_t ATTRIBUTE_PURE MI_SEMAPHORE_MBOX_GeneralRegisterSelect_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 8; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_SEMAPHORE_MBOX::MI Command Opcode */ #define GFX75_MI_SEMAPHORE_MBOX_MICommandOpcode_bits 6 #define GFX7_MI_SEMAPHORE_MBOX_MICommandOpcode_bits 6 #define GFX6_MI_SEMAPHORE_MBOX_MICommandOpcode_bits 6 static inline uint32_t ATTRIBUTE_PURE MI_SEMAPHORE_MBOX_MICommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 6; case 70: return 6; case 60: return 6; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_MI_SEMAPHORE_MBOX_MICommandOpcode_start 23 #define GFX7_MI_SEMAPHORE_MBOX_MICommandOpcode_start 23 #define GFX6_MI_SEMAPHORE_MBOX_MICommandOpcode_start 23 static inline uint32_t ATTRIBUTE_PURE MI_SEMAPHORE_MBOX_MICommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 23; case 70: return 23; case 60: return 23; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_SEMAPHORE_MBOX::Register Select */ #define GFX75_MI_SEMAPHORE_MBOX_RegisterSelect_bits 2 #define GFX7_MI_SEMAPHORE_MBOX_RegisterSelect_bits 2 #define GFX6_MI_SEMAPHORE_MBOX_RegisterSelect_bits 2 static inline uint32_t ATTRIBUTE_PURE MI_SEMAPHORE_MBOX_RegisterSelect_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_MI_SEMAPHORE_MBOX_RegisterSelect_start 16 #define GFX7_MI_SEMAPHORE_MBOX_RegisterSelect_start 16 #define GFX6_MI_SEMAPHORE_MBOX_RegisterSelect_start 16 static inline uint32_t ATTRIBUTE_PURE MI_SEMAPHORE_MBOX_RegisterSelect_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 16; case 70: return 16; case 60: return 16; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_SEMAPHORE_MBOX::Semaphore Data Dword */ #define GFX75_MI_SEMAPHORE_MBOX_SemaphoreDataDword_bits 32 #define GFX7_MI_SEMAPHORE_MBOX_SemaphoreDataDword_bits 32 #define GFX6_MI_SEMAPHORE_MBOX_SemaphoreDataDword_bits 32 static inline uint32_t ATTRIBUTE_PURE MI_SEMAPHORE_MBOX_SemaphoreDataDword_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 32; case 70: return 32; case 60: return 32; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_MI_SEMAPHORE_MBOX_SemaphoreDataDword_start 32 #define GFX7_MI_SEMAPHORE_MBOX_SemaphoreDataDword_start 32 #define GFX6_MI_SEMAPHORE_MBOX_SemaphoreDataDword_start 32 static inline uint32_t ATTRIBUTE_PURE MI_SEMAPHORE_MBOX_SemaphoreDataDword_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 32; case 70: return 32; case 60: return 32; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_SEMAPHORE_SIGNAL */ #define GFX125_MI_SEMAPHORE_SIGNAL_length 2 #define GFX12_MI_SEMAPHORE_SIGNAL_length 2 #define GFX11_MI_SEMAPHORE_SIGNAL_length 2 #define GFX9_MI_SEMAPHORE_SIGNAL_length 2 #define GFX8_MI_SEMAPHORE_SIGNAL_length 2 static inline uint32_t ATTRIBUTE_PURE MI_SEMAPHORE_SIGNAL_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_SEMAPHORE_SIGNAL::Command Type */ #define GFX125_MI_SEMAPHORE_SIGNAL_CommandType_bits 3 #define GFX12_MI_SEMAPHORE_SIGNAL_CommandType_bits 3 #define GFX11_MI_SEMAPHORE_SIGNAL_CommandType_bits 3 #define GFX9_MI_SEMAPHORE_SIGNAL_CommandType_bits 3 #define GFX8_MI_SEMAPHORE_SIGNAL_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE MI_SEMAPHORE_SIGNAL_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_SEMAPHORE_SIGNAL_CommandType_start 29 #define GFX12_MI_SEMAPHORE_SIGNAL_CommandType_start 29 #define GFX11_MI_SEMAPHORE_SIGNAL_CommandType_start 29 #define GFX9_MI_SEMAPHORE_SIGNAL_CommandType_start 29 #define GFX8_MI_SEMAPHORE_SIGNAL_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE MI_SEMAPHORE_SIGNAL_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_SEMAPHORE_SIGNAL::DWord Length */ #define GFX125_MI_SEMAPHORE_SIGNAL_DWordLength_bits 8 #define GFX12_MI_SEMAPHORE_SIGNAL_DWordLength_bits 8 #define GFX11_MI_SEMAPHORE_SIGNAL_DWordLength_bits 8 #define GFX9_MI_SEMAPHORE_SIGNAL_DWordLength_bits 8 #define GFX8_MI_SEMAPHORE_SIGNAL_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE MI_SEMAPHORE_SIGNAL_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_SEMAPHORE_SIGNAL_DWordLength_start 0 #define GFX12_MI_SEMAPHORE_SIGNAL_DWordLength_start 0 #define GFX11_MI_SEMAPHORE_SIGNAL_DWordLength_start 0 #define GFX9_MI_SEMAPHORE_SIGNAL_DWordLength_start 0 #define GFX8_MI_SEMAPHORE_SIGNAL_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE MI_SEMAPHORE_SIGNAL_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_SEMAPHORE_SIGNAL::MI Command Opcode */ #define GFX125_MI_SEMAPHORE_SIGNAL_MICommandOpcode_bits 6 #define GFX12_MI_SEMAPHORE_SIGNAL_MICommandOpcode_bits 6 #define GFX11_MI_SEMAPHORE_SIGNAL_MICommandOpcode_bits 6 #define GFX9_MI_SEMAPHORE_SIGNAL_MICommandOpcode_bits 6 #define GFX8_MI_SEMAPHORE_SIGNAL_MICommandOpcode_bits 6 static inline uint32_t ATTRIBUTE_PURE MI_SEMAPHORE_SIGNAL_MICommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_SEMAPHORE_SIGNAL_MICommandOpcode_start 23 #define GFX12_MI_SEMAPHORE_SIGNAL_MICommandOpcode_start 23 #define GFX11_MI_SEMAPHORE_SIGNAL_MICommandOpcode_start 23 #define GFX9_MI_SEMAPHORE_SIGNAL_MICommandOpcode_start 23 #define GFX8_MI_SEMAPHORE_SIGNAL_MICommandOpcode_start 23 static inline uint32_t ATTRIBUTE_PURE MI_SEMAPHORE_SIGNAL_MICommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 23; case 120: return 23; case 110: return 23; case 90: return 23; case 80: return 23; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_SEMAPHORE_SIGNAL::Post-Sync Operation */ #define GFX125_MI_SEMAPHORE_SIGNAL_PostSyncOperation_bits 1 #define GFX12_MI_SEMAPHORE_SIGNAL_PostSyncOperation_bits 1 #define GFX11_MI_SEMAPHORE_SIGNAL_PostSyncOperation_bits 1 #define GFX9_MI_SEMAPHORE_SIGNAL_PostSyncOperation_bits 1 #define GFX8_MI_SEMAPHORE_SIGNAL_PostSyncOperation_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_SEMAPHORE_SIGNAL_PostSyncOperation_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_SEMAPHORE_SIGNAL_PostSyncOperation_start 21 #define GFX12_MI_SEMAPHORE_SIGNAL_PostSyncOperation_start 21 #define GFX11_MI_SEMAPHORE_SIGNAL_PostSyncOperation_start 21 #define GFX9_MI_SEMAPHORE_SIGNAL_PostSyncOperation_start 21 #define GFX8_MI_SEMAPHORE_SIGNAL_PostSyncOperation_start 21 static inline uint32_t ATTRIBUTE_PURE MI_SEMAPHORE_SIGNAL_PostSyncOperation_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 21; case 120: return 21; case 110: return 21; case 90: return 21; case 80: return 21; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_SEMAPHORE_SIGNAL::Target Context ID */ #define GFX125_MI_SEMAPHORE_SIGNAL_TargetContextID_bits 32 #define GFX12_MI_SEMAPHORE_SIGNAL_TargetContextID_bits 32 #define GFX11_MI_SEMAPHORE_SIGNAL_TargetContextID_bits 32 #define GFX9_MI_SEMAPHORE_SIGNAL_TargetContextID_bits 32 #define GFX8_MI_SEMAPHORE_SIGNAL_TargetContextID_bits 32 static inline uint32_t ATTRIBUTE_PURE MI_SEMAPHORE_SIGNAL_TargetContextID_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_SEMAPHORE_SIGNAL_TargetContextID_start 32 #define GFX12_MI_SEMAPHORE_SIGNAL_TargetContextID_start 32 #define GFX11_MI_SEMAPHORE_SIGNAL_TargetContextID_start 32 #define GFX9_MI_SEMAPHORE_SIGNAL_TargetContextID_start 32 #define GFX8_MI_SEMAPHORE_SIGNAL_TargetContextID_start 32 static inline uint32_t ATTRIBUTE_PURE MI_SEMAPHORE_SIGNAL_TargetContextID_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_SEMAPHORE_SIGNAL::Target Engine Select */ #define GFX125_MI_SEMAPHORE_SIGNAL_TargetEngineSelect_bits 4 #define GFX12_MI_SEMAPHORE_SIGNAL_TargetEngineSelect_bits 4 #define GFX11_MI_SEMAPHORE_SIGNAL_TargetEngineSelect_bits 4 #define GFX9_MI_SEMAPHORE_SIGNAL_TargetEngineSelect_bits 3 #define GFX8_MI_SEMAPHORE_SIGNAL_TargetEngineSelect_bits 3 static inline uint32_t ATTRIBUTE_PURE MI_SEMAPHORE_SIGNAL_TargetEngineSelect_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 3; case 80: return 3; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_SEMAPHORE_SIGNAL_TargetEngineSelect_start 15 #define GFX12_MI_SEMAPHORE_SIGNAL_TargetEngineSelect_start 15 #define GFX11_MI_SEMAPHORE_SIGNAL_TargetEngineSelect_start 15 #define GFX9_MI_SEMAPHORE_SIGNAL_TargetEngineSelect_start 15 #define GFX8_MI_SEMAPHORE_SIGNAL_TargetEngineSelect_start 15 static inline uint32_t ATTRIBUTE_PURE MI_SEMAPHORE_SIGNAL_TargetEngineSelect_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 15; case 120: return 15; case 110: return 15; case 90: return 15; case 80: return 15; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_SEMAPHORE_WAIT */ #define GFX125_MI_SEMAPHORE_WAIT_length 4 #define GFX12_MI_SEMAPHORE_WAIT_length 4 #define GFX11_MI_SEMAPHORE_WAIT_length 4 #define GFX9_MI_SEMAPHORE_WAIT_length 4 #define GFX8_MI_SEMAPHORE_WAIT_length 4 static inline uint32_t ATTRIBUTE_PURE MI_SEMAPHORE_WAIT_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_SEMAPHORE_WAIT::Command Type */ #define GFX125_MI_SEMAPHORE_WAIT_CommandType_bits 3 #define GFX12_MI_SEMAPHORE_WAIT_CommandType_bits 3 #define GFX11_MI_SEMAPHORE_WAIT_CommandType_bits 3 #define GFX9_MI_SEMAPHORE_WAIT_CommandType_bits 3 #define GFX8_MI_SEMAPHORE_WAIT_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE MI_SEMAPHORE_WAIT_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_SEMAPHORE_WAIT_CommandType_start 29 #define GFX12_MI_SEMAPHORE_WAIT_CommandType_start 29 #define GFX11_MI_SEMAPHORE_WAIT_CommandType_start 29 #define GFX9_MI_SEMAPHORE_WAIT_CommandType_start 29 #define GFX8_MI_SEMAPHORE_WAIT_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE MI_SEMAPHORE_WAIT_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_SEMAPHORE_WAIT::Compare Operation */ #define GFX125_MI_SEMAPHORE_WAIT_CompareOperation_bits 3 #define GFX12_MI_SEMAPHORE_WAIT_CompareOperation_bits 3 #define GFX11_MI_SEMAPHORE_WAIT_CompareOperation_bits 3 #define GFX9_MI_SEMAPHORE_WAIT_CompareOperation_bits 3 #define GFX8_MI_SEMAPHORE_WAIT_CompareOperation_bits 3 static inline uint32_t ATTRIBUTE_PURE MI_SEMAPHORE_WAIT_CompareOperation_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_SEMAPHORE_WAIT_CompareOperation_start 12 #define GFX12_MI_SEMAPHORE_WAIT_CompareOperation_start 12 #define GFX11_MI_SEMAPHORE_WAIT_CompareOperation_start 12 #define GFX9_MI_SEMAPHORE_WAIT_CompareOperation_start 12 #define GFX8_MI_SEMAPHORE_WAIT_CompareOperation_start 12 static inline uint32_t ATTRIBUTE_PURE MI_SEMAPHORE_WAIT_CompareOperation_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 12; case 120: return 12; case 110: return 12; case 90: return 12; case 80: return 12; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_SEMAPHORE_WAIT::DWord Length */ #define GFX125_MI_SEMAPHORE_WAIT_DWordLength_bits 8 #define GFX12_MI_SEMAPHORE_WAIT_DWordLength_bits 8 #define GFX11_MI_SEMAPHORE_WAIT_DWordLength_bits 8 #define GFX9_MI_SEMAPHORE_WAIT_DWordLength_bits 8 #define GFX8_MI_SEMAPHORE_WAIT_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE MI_SEMAPHORE_WAIT_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_SEMAPHORE_WAIT_DWordLength_start 0 #define GFX12_MI_SEMAPHORE_WAIT_DWordLength_start 0 #define GFX11_MI_SEMAPHORE_WAIT_DWordLength_start 0 #define GFX9_MI_SEMAPHORE_WAIT_DWordLength_start 0 #define GFX8_MI_SEMAPHORE_WAIT_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE MI_SEMAPHORE_WAIT_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_SEMAPHORE_WAIT::MI Command Opcode */ #define GFX125_MI_SEMAPHORE_WAIT_MICommandOpcode_bits 6 #define GFX12_MI_SEMAPHORE_WAIT_MICommandOpcode_bits 6 #define GFX11_MI_SEMAPHORE_WAIT_MICommandOpcode_bits 6 #define GFX9_MI_SEMAPHORE_WAIT_MICommandOpcode_bits 6 #define GFX8_MI_SEMAPHORE_WAIT_MICommandOpcode_bits 6 static inline uint32_t ATTRIBUTE_PURE MI_SEMAPHORE_WAIT_MICommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_SEMAPHORE_WAIT_MICommandOpcode_start 23 #define GFX12_MI_SEMAPHORE_WAIT_MICommandOpcode_start 23 #define GFX11_MI_SEMAPHORE_WAIT_MICommandOpcode_start 23 #define GFX9_MI_SEMAPHORE_WAIT_MICommandOpcode_start 23 #define GFX8_MI_SEMAPHORE_WAIT_MICommandOpcode_start 23 static inline uint32_t ATTRIBUTE_PURE MI_SEMAPHORE_WAIT_MICommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 23; case 120: return 23; case 110: return 23; case 90: return 23; case 80: return 23; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_SEMAPHORE_WAIT::Memory Type */ #define GFX125_MI_SEMAPHORE_WAIT_MemoryType_bits 1 #define GFX12_MI_SEMAPHORE_WAIT_MemoryType_bits 1 #define GFX11_MI_SEMAPHORE_WAIT_MemoryType_bits 1 #define GFX9_MI_SEMAPHORE_WAIT_MemoryType_bits 1 #define GFX8_MI_SEMAPHORE_WAIT_MemoryType_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_SEMAPHORE_WAIT_MemoryType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_SEMAPHORE_WAIT_MemoryType_start 22 #define GFX12_MI_SEMAPHORE_WAIT_MemoryType_start 22 #define GFX11_MI_SEMAPHORE_WAIT_MemoryType_start 22 #define GFX9_MI_SEMAPHORE_WAIT_MemoryType_start 22 #define GFX8_MI_SEMAPHORE_WAIT_MemoryType_start 22 static inline uint32_t ATTRIBUTE_PURE MI_SEMAPHORE_WAIT_MemoryType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 22; case 120: return 22; case 110: return 22; case 90: return 22; case 80: return 22; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_SEMAPHORE_WAIT::Register Poll Mode */ #define GFX125_MI_SEMAPHORE_WAIT_RegisterPollMode_bits 1 #define GFX12_MI_SEMAPHORE_WAIT_RegisterPollMode_bits 1 #define GFX11_MI_SEMAPHORE_WAIT_RegisterPollMode_bits 1 #define GFX9_MI_SEMAPHORE_WAIT_RegisterPollMode_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_SEMAPHORE_WAIT_RegisterPollMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_SEMAPHORE_WAIT_RegisterPollMode_start 16 #define GFX12_MI_SEMAPHORE_WAIT_RegisterPollMode_start 16 #define GFX11_MI_SEMAPHORE_WAIT_RegisterPollMode_start 16 #define GFX9_MI_SEMAPHORE_WAIT_RegisterPollMode_start 16 static inline uint32_t ATTRIBUTE_PURE MI_SEMAPHORE_WAIT_RegisterPollMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_SEMAPHORE_WAIT::Semaphore Address */ #define GFX125_MI_SEMAPHORE_WAIT_SemaphoreAddress_bits 62 #define GFX12_MI_SEMAPHORE_WAIT_SemaphoreAddress_bits 62 #define GFX11_MI_SEMAPHORE_WAIT_SemaphoreAddress_bits 62 #define GFX9_MI_SEMAPHORE_WAIT_SemaphoreAddress_bits 62 #define GFX8_MI_SEMAPHORE_WAIT_SemaphoreAddress_bits 30 static inline uint32_t ATTRIBUTE_PURE MI_SEMAPHORE_WAIT_SemaphoreAddress_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 62; case 120: return 62; case 110: return 62; case 90: return 62; case 80: return 30; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_SEMAPHORE_WAIT_SemaphoreAddress_start 66 #define GFX12_MI_SEMAPHORE_WAIT_SemaphoreAddress_start 66 #define GFX11_MI_SEMAPHORE_WAIT_SemaphoreAddress_start 66 #define GFX9_MI_SEMAPHORE_WAIT_SemaphoreAddress_start 66 #define GFX8_MI_SEMAPHORE_WAIT_SemaphoreAddress_start 66 static inline uint32_t ATTRIBUTE_PURE MI_SEMAPHORE_WAIT_SemaphoreAddress_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 66; case 120: return 66; case 110: return 66; case 90: return 66; case 80: return 66; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_SEMAPHORE_WAIT::Semaphore Address High */ #define GFX8_MI_SEMAPHORE_WAIT_SemaphoreAddressHigh_bits 16 static inline uint32_t ATTRIBUTE_PURE MI_SEMAPHORE_WAIT_SemaphoreAddressHigh_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 16; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX8_MI_SEMAPHORE_WAIT_SemaphoreAddressHigh_start 96 static inline uint32_t ATTRIBUTE_PURE MI_SEMAPHORE_WAIT_SemaphoreAddressHigh_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 96; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_SEMAPHORE_WAIT::Semaphore Data Dword */ #define GFX125_MI_SEMAPHORE_WAIT_SemaphoreDataDword_bits 32 #define GFX12_MI_SEMAPHORE_WAIT_SemaphoreDataDword_bits 32 #define GFX11_MI_SEMAPHORE_WAIT_SemaphoreDataDword_bits 32 #define GFX9_MI_SEMAPHORE_WAIT_SemaphoreDataDword_bits 32 #define GFX8_MI_SEMAPHORE_WAIT_SemaphoreDataDword_bits 32 static inline uint32_t ATTRIBUTE_PURE MI_SEMAPHORE_WAIT_SemaphoreDataDword_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_SEMAPHORE_WAIT_SemaphoreDataDword_start 32 #define GFX12_MI_SEMAPHORE_WAIT_SemaphoreDataDword_start 32 #define GFX11_MI_SEMAPHORE_WAIT_SemaphoreDataDword_start 32 #define GFX9_MI_SEMAPHORE_WAIT_SemaphoreDataDword_start 32 #define GFX8_MI_SEMAPHORE_WAIT_SemaphoreDataDword_start 32 static inline uint32_t ATTRIBUTE_PURE MI_SEMAPHORE_WAIT_SemaphoreDataDword_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_SEMAPHORE_WAIT::Wait Mode */ #define GFX125_MI_SEMAPHORE_WAIT_WaitMode_bits 1 #define GFX12_MI_SEMAPHORE_WAIT_WaitMode_bits 1 #define GFX11_MI_SEMAPHORE_WAIT_WaitMode_bits 1 #define GFX9_MI_SEMAPHORE_WAIT_WaitMode_bits 1 #define GFX8_MI_SEMAPHORE_WAIT_WaitMode_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_SEMAPHORE_WAIT_WaitMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_SEMAPHORE_WAIT_WaitMode_start 15 #define GFX12_MI_SEMAPHORE_WAIT_WaitMode_start 15 #define GFX11_MI_SEMAPHORE_WAIT_WaitMode_start 15 #define GFX9_MI_SEMAPHORE_WAIT_WaitMode_start 15 #define GFX8_MI_SEMAPHORE_WAIT_WaitMode_start 15 static inline uint32_t ATTRIBUTE_PURE MI_SEMAPHORE_WAIT_WaitMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 15; case 120: return 15; case 110: return 15; case 90: return 15; case 80: return 15; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_SET_APPID */ #define GFX125_MI_SET_APPID_length 1 #define GFX12_MI_SET_APPID_length 1 static inline uint32_t ATTRIBUTE_PURE MI_SET_APPID_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_SET_APPID::Command Type */ #define GFX125_MI_SET_APPID_CommandType_bits 3 #define GFX12_MI_SET_APPID_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE MI_SET_APPID_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_SET_APPID_CommandType_start 29 #define GFX12_MI_SET_APPID_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE MI_SET_APPID_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_SET_APPID::MI Command Opcode */ #define GFX125_MI_SET_APPID_MICommandOpcode_bits 6 #define GFX12_MI_SET_APPID_MICommandOpcode_bits 6 static inline uint32_t ATTRIBUTE_PURE MI_SET_APPID_MICommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_SET_APPID_MICommandOpcode_start 23 #define GFX12_MI_SET_APPID_MICommandOpcode_start 23 static inline uint32_t ATTRIBUTE_PURE MI_SET_APPID_MICommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 23; case 120: return 23; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_SET_APPID::Protected Memory Application ID */ #define GFX125_MI_SET_APPID_ProtectedMemoryApplicationID_bits 7 #define GFX12_MI_SET_APPID_ProtectedMemoryApplicationID_bits 7 static inline uint32_t ATTRIBUTE_PURE MI_SET_APPID_ProtectedMemoryApplicationID_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 7; case 120: return 7; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_SET_APPID_ProtectedMemoryApplicationID_start 0 #define GFX12_MI_SET_APPID_ProtectedMemoryApplicationID_start 0 static inline uint32_t ATTRIBUTE_PURE MI_SET_APPID_ProtectedMemoryApplicationID_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_SET_APPID::Protected Memory Application ID Type */ #define GFX125_MI_SET_APPID_ProtectedMemoryApplicationIDType_bits 1 #define GFX12_MI_SET_APPID_ProtectedMemoryApplicationIDType_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_SET_APPID_ProtectedMemoryApplicationIDType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_SET_APPID_ProtectedMemoryApplicationIDType_start 7 #define GFX12_MI_SET_APPID_ProtectedMemoryApplicationIDType_start 7 static inline uint32_t ATTRIBUTE_PURE MI_SET_APPID_ProtectedMemoryApplicationIDType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 7; case 120: return 7; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_SET_CONTEXT */ #define GFX125_MI_SET_CONTEXT_length 2 #define GFX12_MI_SET_CONTEXT_length 2 #define GFX11_MI_SET_CONTEXT_length 2 #define GFX9_MI_SET_CONTEXT_length 2 #define GFX8_MI_SET_CONTEXT_length 2 #define GFX75_MI_SET_CONTEXT_length 2 #define GFX7_MI_SET_CONTEXT_length 2 #define GFX6_MI_SET_CONTEXT_length 2 static inline uint32_t ATTRIBUTE_PURE MI_SET_CONTEXT_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_SET_CONTEXT::Command Type */ #define GFX125_MI_SET_CONTEXT_CommandType_bits 3 #define GFX12_MI_SET_CONTEXT_CommandType_bits 3 #define GFX11_MI_SET_CONTEXT_CommandType_bits 3 #define GFX9_MI_SET_CONTEXT_CommandType_bits 3 #define GFX8_MI_SET_CONTEXT_CommandType_bits 3 #define GFX75_MI_SET_CONTEXT_CommandType_bits 3 #define GFX7_MI_SET_CONTEXT_CommandType_bits 3 #define GFX6_MI_SET_CONTEXT_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE MI_SET_CONTEXT_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_SET_CONTEXT_CommandType_start 29 #define GFX12_MI_SET_CONTEXT_CommandType_start 29 #define GFX11_MI_SET_CONTEXT_CommandType_start 29 #define GFX9_MI_SET_CONTEXT_CommandType_start 29 #define GFX8_MI_SET_CONTEXT_CommandType_start 29 #define GFX75_MI_SET_CONTEXT_CommandType_start 29 #define GFX7_MI_SET_CONTEXT_CommandType_start 29 #define GFX6_MI_SET_CONTEXT_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE MI_SET_CONTEXT_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 29; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_SET_CONTEXT::Core Mode Enable */ #define GFX125_MI_SET_CONTEXT_CoreModeEnable_bits 1 #define GFX12_MI_SET_CONTEXT_CoreModeEnable_bits 1 #define GFX11_MI_SET_CONTEXT_CoreModeEnable_bits 1 #define GFX9_MI_SET_CONTEXT_CoreModeEnable_bits 1 #define GFX8_MI_SET_CONTEXT_CoreModeEnable_bits 1 #define GFX75_MI_SET_CONTEXT_CoreModeEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_SET_CONTEXT_CoreModeEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_SET_CONTEXT_CoreModeEnable_start 36 #define GFX12_MI_SET_CONTEXT_CoreModeEnable_start 36 #define GFX11_MI_SET_CONTEXT_CoreModeEnable_start 36 #define GFX9_MI_SET_CONTEXT_CoreModeEnable_start 36 #define GFX8_MI_SET_CONTEXT_CoreModeEnable_start 36 #define GFX75_MI_SET_CONTEXT_CoreModeEnable_start 36 static inline uint32_t ATTRIBUTE_PURE MI_SET_CONTEXT_CoreModeEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 36; case 120: return 36; case 110: return 36; case 90: return 36; case 80: return 36; case 75: return 36; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_SET_CONTEXT::DWord Length */ #define GFX125_MI_SET_CONTEXT_DWordLength_bits 8 #define GFX12_MI_SET_CONTEXT_DWordLength_bits 8 #define GFX11_MI_SET_CONTEXT_DWordLength_bits 8 #define GFX9_MI_SET_CONTEXT_DWordLength_bits 8 #define GFX8_MI_SET_CONTEXT_DWordLength_bits 8 #define GFX75_MI_SET_CONTEXT_DWordLength_bits 8 #define GFX7_MI_SET_CONTEXT_DWordLength_bits 8 #define GFX6_MI_SET_CONTEXT_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE MI_SET_CONTEXT_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_SET_CONTEXT_DWordLength_start 0 #define GFX12_MI_SET_CONTEXT_DWordLength_start 0 #define GFX11_MI_SET_CONTEXT_DWordLength_start 0 #define GFX9_MI_SET_CONTEXT_DWordLength_start 0 #define GFX8_MI_SET_CONTEXT_DWordLength_start 0 #define GFX75_MI_SET_CONTEXT_DWordLength_start 0 #define GFX7_MI_SET_CONTEXT_DWordLength_start 0 #define GFX6_MI_SET_CONTEXT_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE MI_SET_CONTEXT_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_SET_CONTEXT::Extended State Restore Enable */ #define GFX7_MI_SET_CONTEXT_ExtendedStateRestoreEnable_bits 1 #define GFX6_MI_SET_CONTEXT_ExtendedStateRestoreEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_SET_CONTEXT_ExtendedStateRestoreEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX7_MI_SET_CONTEXT_ExtendedStateRestoreEnable_start 34 #define GFX6_MI_SET_CONTEXT_ExtendedStateRestoreEnable_start 34 static inline uint32_t ATTRIBUTE_PURE MI_SET_CONTEXT_ExtendedStateRestoreEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 34; case 60: return 34; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_SET_CONTEXT::Extended State Save Enable */ #define GFX7_MI_SET_CONTEXT_ExtendedStateSaveEnable_bits 1 #define GFX6_MI_SET_CONTEXT_ExtendedStateSaveEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_SET_CONTEXT_ExtendedStateSaveEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX7_MI_SET_CONTEXT_ExtendedStateSaveEnable_start 35 #define GFX6_MI_SET_CONTEXT_ExtendedStateSaveEnable_start 35 static inline uint32_t ATTRIBUTE_PURE MI_SET_CONTEXT_ExtendedStateSaveEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 35; case 60: return 35; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_SET_CONTEXT::Force Restore */ #define GFX125_MI_SET_CONTEXT_ForceRestore_bits 1 #define GFX12_MI_SET_CONTEXT_ForceRestore_bits 1 #define GFX11_MI_SET_CONTEXT_ForceRestore_bits 1 #define GFX9_MI_SET_CONTEXT_ForceRestore_bits 1 #define GFX8_MI_SET_CONTEXT_ForceRestore_bits 1 #define GFX75_MI_SET_CONTEXT_ForceRestore_bits 1 #define GFX7_MI_SET_CONTEXT_ForceRestore_bits 1 #define GFX6_MI_SET_CONTEXT_ForceRestore_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_SET_CONTEXT_ForceRestore_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_SET_CONTEXT_ForceRestore_start 33 #define GFX12_MI_SET_CONTEXT_ForceRestore_start 33 #define GFX11_MI_SET_CONTEXT_ForceRestore_start 33 #define GFX9_MI_SET_CONTEXT_ForceRestore_start 33 #define GFX8_MI_SET_CONTEXT_ForceRestore_start 33 #define GFX75_MI_SET_CONTEXT_ForceRestore_start 33 #define GFX7_MI_SET_CONTEXT_ForceRestore_start 33 #define GFX6_MI_SET_CONTEXT_ForceRestore_start 33 static inline uint32_t ATTRIBUTE_PURE MI_SET_CONTEXT_ForceRestore_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 33; case 120: return 33; case 110: return 33; case 90: return 33; case 80: return 33; case 75: return 33; case 70: return 33; case 60: return 33; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_SET_CONTEXT::HD DVD Context */ #define GFX6_MI_SET_CONTEXT_HDDVDContext_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_SET_CONTEXT_HDDVDContext_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_MI_SET_CONTEXT_HDDVDContext_start 41 static inline uint32_t ATTRIBUTE_PURE MI_SET_CONTEXT_HDDVDContext_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 41; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_SET_CONTEXT::Logical Context Address */ #define GFX125_MI_SET_CONTEXT_LogicalContextAddress_bits 20 #define GFX12_MI_SET_CONTEXT_LogicalContextAddress_bits 20 #define GFX11_MI_SET_CONTEXT_LogicalContextAddress_bits 20 #define GFX9_MI_SET_CONTEXT_LogicalContextAddress_bits 20 #define GFX8_MI_SET_CONTEXT_LogicalContextAddress_bits 20 #define GFX75_MI_SET_CONTEXT_LogicalContextAddress_bits 20 #define GFX7_MI_SET_CONTEXT_LogicalContextAddress_bits 20 #define GFX6_MI_SET_CONTEXT_LogicalContextAddress_bits 20 static inline uint32_t ATTRIBUTE_PURE MI_SET_CONTEXT_LogicalContextAddress_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 20; case 120: return 20; case 110: return 20; case 90: return 20; case 80: return 20; case 75: return 20; case 70: return 20; case 60: return 20; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_SET_CONTEXT_LogicalContextAddress_start 44 #define GFX12_MI_SET_CONTEXT_LogicalContextAddress_start 44 #define GFX11_MI_SET_CONTEXT_LogicalContextAddress_start 44 #define GFX9_MI_SET_CONTEXT_LogicalContextAddress_start 44 #define GFX8_MI_SET_CONTEXT_LogicalContextAddress_start 44 #define GFX75_MI_SET_CONTEXT_LogicalContextAddress_start 44 #define GFX7_MI_SET_CONTEXT_LogicalContextAddress_start 44 #define GFX6_MI_SET_CONTEXT_LogicalContextAddress_start 44 static inline uint32_t ATTRIBUTE_PURE MI_SET_CONTEXT_LogicalContextAddress_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 44; case 120: return 44; case 110: return 44; case 90: return 44; case 80: return 44; case 75: return 44; case 70: return 44; case 60: return 44; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_SET_CONTEXT::MI Command Opcode */ #define GFX125_MI_SET_CONTEXT_MICommandOpcode_bits 6 #define GFX12_MI_SET_CONTEXT_MICommandOpcode_bits 6 #define GFX11_MI_SET_CONTEXT_MICommandOpcode_bits 6 #define GFX9_MI_SET_CONTEXT_MICommandOpcode_bits 6 #define GFX8_MI_SET_CONTEXT_MICommandOpcode_bits 6 #define GFX75_MI_SET_CONTEXT_MICommandOpcode_bits 6 #define GFX7_MI_SET_CONTEXT_MICommandOpcode_bits 6 #define GFX6_MI_SET_CONTEXT_MICommandOpcode_bits 6 static inline uint32_t ATTRIBUTE_PURE MI_SET_CONTEXT_MICommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 6; case 60: return 6; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_SET_CONTEXT_MICommandOpcode_start 23 #define GFX12_MI_SET_CONTEXT_MICommandOpcode_start 23 #define GFX11_MI_SET_CONTEXT_MICommandOpcode_start 23 #define GFX9_MI_SET_CONTEXT_MICommandOpcode_start 23 #define GFX8_MI_SET_CONTEXT_MICommandOpcode_start 23 #define GFX75_MI_SET_CONTEXT_MICommandOpcode_start 23 #define GFX7_MI_SET_CONTEXT_MICommandOpcode_start 23 #define GFX6_MI_SET_CONTEXT_MICommandOpcode_start 23 static inline uint32_t ATTRIBUTE_PURE MI_SET_CONTEXT_MICommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 23; case 120: return 23; case 110: return 23; case 90: return 23; case 80: return 23; case 75: return 23; case 70: return 23; case 60: return 23; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_SET_CONTEXT::Reserved, Must be 1 */ #define GFX125_MI_SET_CONTEXT_ReservedMustbe1_bits 1 #define GFX12_MI_SET_CONTEXT_ReservedMustbe1_bits 1 #define GFX11_MI_SET_CONTEXT_ReservedMustbe1_bits 1 #define GFX9_MI_SET_CONTEXT_ReservedMustbe1_bits 1 #define GFX8_MI_SET_CONTEXT_ReservedMustbe1_bits 1 #define GFX75_MI_SET_CONTEXT_ReservedMustbe1_bits 1 #define GFX7_MI_SET_CONTEXT_ReservedMustbe1_bits 1 #define GFX6_MI_SET_CONTEXT_ReservedMustbe1_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_SET_CONTEXT_ReservedMustbe1_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_SET_CONTEXT_ReservedMustbe1_start 40 #define GFX12_MI_SET_CONTEXT_ReservedMustbe1_start 40 #define GFX11_MI_SET_CONTEXT_ReservedMustbe1_start 40 #define GFX9_MI_SET_CONTEXT_ReservedMustbe1_start 40 #define GFX8_MI_SET_CONTEXT_ReservedMustbe1_start 40 #define GFX75_MI_SET_CONTEXT_ReservedMustbe1_start 40 #define GFX7_MI_SET_CONTEXT_ReservedMustbe1_start 40 #define GFX6_MI_SET_CONTEXT_ReservedMustbe1_start 40 static inline uint32_t ATTRIBUTE_PURE MI_SET_CONTEXT_ReservedMustbe1_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 40; case 120: return 40; case 110: return 40; case 90: return 40; case 80: return 40; case 75: return 40; case 70: return 40; case 60: return 40; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_SET_CONTEXT::Resource Streamer State Restore Enable */ #define GFX125_MI_SET_CONTEXT_ResourceStreamerStateRestoreEnable_bits 1 #define GFX12_MI_SET_CONTEXT_ResourceStreamerStateRestoreEnable_bits 1 #define GFX11_MI_SET_CONTEXT_ResourceStreamerStateRestoreEnable_bits 1 #define GFX9_MI_SET_CONTEXT_ResourceStreamerStateRestoreEnable_bits 1 #define GFX8_MI_SET_CONTEXT_ResourceStreamerStateRestoreEnable_bits 1 #define GFX75_MI_SET_CONTEXT_ResourceStreamerStateRestoreEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_SET_CONTEXT_ResourceStreamerStateRestoreEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_SET_CONTEXT_ResourceStreamerStateRestoreEnable_start 34 #define GFX12_MI_SET_CONTEXT_ResourceStreamerStateRestoreEnable_start 34 #define GFX11_MI_SET_CONTEXT_ResourceStreamerStateRestoreEnable_start 34 #define GFX9_MI_SET_CONTEXT_ResourceStreamerStateRestoreEnable_start 34 #define GFX8_MI_SET_CONTEXT_ResourceStreamerStateRestoreEnable_start 34 #define GFX75_MI_SET_CONTEXT_ResourceStreamerStateRestoreEnable_start 34 static inline uint32_t ATTRIBUTE_PURE MI_SET_CONTEXT_ResourceStreamerStateRestoreEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 34; case 120: return 34; case 110: return 34; case 90: return 34; case 80: return 34; case 75: return 34; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_SET_CONTEXT::Resource Streamer State Save Enable */ #define GFX125_MI_SET_CONTEXT_ResourceStreamerStateSaveEnable_bits 1 #define GFX12_MI_SET_CONTEXT_ResourceStreamerStateSaveEnable_bits 1 #define GFX11_MI_SET_CONTEXT_ResourceStreamerStateSaveEnable_bits 1 #define GFX9_MI_SET_CONTEXT_ResourceStreamerStateSaveEnable_bits 1 #define GFX8_MI_SET_CONTEXT_ResourceStreamerStateSaveEnable_bits 1 #define GFX75_MI_SET_CONTEXT_ResourceStreamerStateSaveEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_SET_CONTEXT_ResourceStreamerStateSaveEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_SET_CONTEXT_ResourceStreamerStateSaveEnable_start 35 #define GFX12_MI_SET_CONTEXT_ResourceStreamerStateSaveEnable_start 35 #define GFX11_MI_SET_CONTEXT_ResourceStreamerStateSaveEnable_start 35 #define GFX9_MI_SET_CONTEXT_ResourceStreamerStateSaveEnable_start 35 #define GFX8_MI_SET_CONTEXT_ResourceStreamerStateSaveEnable_start 35 #define GFX75_MI_SET_CONTEXT_ResourceStreamerStateSaveEnable_start 35 static inline uint32_t ATTRIBUTE_PURE MI_SET_CONTEXT_ResourceStreamerStateSaveEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 35; case 120: return 35; case 110: return 35; case 90: return 35; case 80: return 35; case 75: return 35; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_SET_CONTEXT::Restore Inhibit */ #define GFX125_MI_SET_CONTEXT_RestoreInhibit_bits 1 #define GFX12_MI_SET_CONTEXT_RestoreInhibit_bits 1 #define GFX11_MI_SET_CONTEXT_RestoreInhibit_bits 1 #define GFX9_MI_SET_CONTEXT_RestoreInhibit_bits 1 #define GFX8_MI_SET_CONTEXT_RestoreInhibit_bits 1 #define GFX75_MI_SET_CONTEXT_RestoreInhibit_bits 1 #define GFX7_MI_SET_CONTEXT_RestoreInhibit_bits 1 #define GFX6_MI_SET_CONTEXT_RestoreInhibit_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_SET_CONTEXT_RestoreInhibit_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_SET_CONTEXT_RestoreInhibit_start 32 #define GFX12_MI_SET_CONTEXT_RestoreInhibit_start 32 #define GFX11_MI_SET_CONTEXT_RestoreInhibit_start 32 #define GFX9_MI_SET_CONTEXT_RestoreInhibit_start 32 #define GFX8_MI_SET_CONTEXT_RestoreInhibit_start 32 #define GFX75_MI_SET_CONTEXT_RestoreInhibit_start 32 #define GFX7_MI_SET_CONTEXT_RestoreInhibit_start 32 #define GFX6_MI_SET_CONTEXT_RestoreInhibit_start 32 static inline uint32_t ATTRIBUTE_PURE MI_SET_CONTEXT_RestoreInhibit_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 32; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_SET_PREDICATE */ #define GFX125_MI_SET_PREDICATE_length 1 #define GFX12_MI_SET_PREDICATE_length 1 #define GFX11_MI_SET_PREDICATE_length 1 #define GFX9_MI_SET_PREDICATE_length 1 #define GFX8_MI_SET_PREDICATE_length 1 #define GFX75_MI_SET_PREDICATE_length 1 static inline uint32_t ATTRIBUTE_PURE MI_SET_PREDICATE_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_SET_PREDICATE::Command Type */ #define GFX125_MI_SET_PREDICATE_CommandType_bits 3 #define GFX12_MI_SET_PREDICATE_CommandType_bits 3 #define GFX11_MI_SET_PREDICATE_CommandType_bits 3 #define GFX9_MI_SET_PREDICATE_CommandType_bits 3 #define GFX8_MI_SET_PREDICATE_CommandType_bits 3 #define GFX75_MI_SET_PREDICATE_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE MI_SET_PREDICATE_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_SET_PREDICATE_CommandType_start 29 #define GFX12_MI_SET_PREDICATE_CommandType_start 29 #define GFX11_MI_SET_PREDICATE_CommandType_start 29 #define GFX9_MI_SET_PREDICATE_CommandType_start 29 #define GFX8_MI_SET_PREDICATE_CommandType_start 29 #define GFX75_MI_SET_PREDICATE_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE MI_SET_PREDICATE_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_SET_PREDICATE::MI Command Opcode */ #define GFX125_MI_SET_PREDICATE_MICommandOpcode_bits 6 #define GFX12_MI_SET_PREDICATE_MICommandOpcode_bits 6 #define GFX11_MI_SET_PREDICATE_MICommandOpcode_bits 6 #define GFX9_MI_SET_PREDICATE_MICommandOpcode_bits 6 #define GFX8_MI_SET_PREDICATE_MICommandOpcode_bits 6 #define GFX75_MI_SET_PREDICATE_MICommandOpcode_bits 6 static inline uint32_t ATTRIBUTE_PURE MI_SET_PREDICATE_MICommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_SET_PREDICATE_MICommandOpcode_start 23 #define GFX12_MI_SET_PREDICATE_MICommandOpcode_start 23 #define GFX11_MI_SET_PREDICATE_MICommandOpcode_start 23 #define GFX9_MI_SET_PREDICATE_MICommandOpcode_start 23 #define GFX8_MI_SET_PREDICATE_MICommandOpcode_start 23 #define GFX75_MI_SET_PREDICATE_MICommandOpcode_start 23 static inline uint32_t ATTRIBUTE_PURE MI_SET_PREDICATE_MICommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 23; case 120: return 23; case 110: return 23; case 90: return 23; case 80: return 23; case 75: return 23; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_SET_PREDICATE::PREDICATE ENABLE */ #define GFX12_MI_SET_PREDICATE_PREDICATEENABLE_bits 4 #define GFX11_MI_SET_PREDICATE_PREDICATEENABLE_bits 4 #define GFX9_MI_SET_PREDICATE_PREDICATEENABLE_bits 4 #define GFX8_MI_SET_PREDICATE_PREDICATEENABLE_bits 4 #define GFX75_MI_SET_PREDICATE_PREDICATEENABLE_bits 2 static inline uint32_t ATTRIBUTE_PURE MI_SET_PREDICATE_PREDICATEENABLE_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 2; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_MI_SET_PREDICATE_PREDICATEENABLE_start 0 #define GFX11_MI_SET_PREDICATE_PREDICATEENABLE_start 0 #define GFX9_MI_SET_PREDICATE_PREDICATEENABLE_start 0 #define GFX8_MI_SET_PREDICATE_PREDICATEENABLE_start 0 #define GFX75_MI_SET_PREDICATE_PREDICATEENABLE_start 0 static inline uint32_t ATTRIBUTE_PURE MI_SET_PREDICATE_PREDICATEENABLE_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_SET_PREDICATE::Predicate Enable */ #define GFX125_MI_SET_PREDICATE_PredicateEnable_bits 4 static inline uint32_t ATTRIBUTE_PURE MI_SET_PREDICATE_PredicateEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_SET_PREDICATE_PredicateEnable_start 0 static inline uint32_t ATTRIBUTE_PURE MI_SET_PREDICATE_PredicateEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_STORE_DATA_IMM */ #define GFX125_MI_STORE_DATA_IMM_length 4 #define GFX12_MI_STORE_DATA_IMM_length 4 #define GFX11_MI_STORE_DATA_IMM_length 4 #define GFX9_MI_STORE_DATA_IMM_length 4 #define GFX8_MI_STORE_DATA_IMM_length 4 #define GFX75_MI_STORE_DATA_IMM_length 4 #define GFX7_MI_STORE_DATA_IMM_length 4 #define GFX6_MI_STORE_DATA_IMM_length 4 #define GFX5_MI_STORE_DATA_IMM_length 5 #define GFX45_MI_STORE_DATA_IMM_length 5 #define GFX4_MI_STORE_DATA_IMM_length 5 static inline uint32_t ATTRIBUTE_PURE MI_STORE_DATA_IMM_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 4; case 70: return 4; case 60: return 4; case 50: return 5; case 45: return 5; case 40: return 5; default: unreachable("Invalid hardware generation"); } } /* MI_STORE_DATA_IMM::Address */ #define GFX125_MI_STORE_DATA_IMM_Address_bits 46 #define GFX12_MI_STORE_DATA_IMM_Address_bits 46 #define GFX11_MI_STORE_DATA_IMM_Address_bits 46 #define GFX9_MI_STORE_DATA_IMM_Address_bits 46 #define GFX8_MI_STORE_DATA_IMM_Address_bits 46 #define GFX75_MI_STORE_DATA_IMM_Address_bits 30 #define GFX7_MI_STORE_DATA_IMM_Address_bits 30 #define GFX6_MI_STORE_DATA_IMM_Address_bits 30 #define GFX5_MI_STORE_DATA_IMM_Address_bits 30 #define GFX45_MI_STORE_DATA_IMM_Address_bits 30 #define GFX4_MI_STORE_DATA_IMM_Address_bits 30 static inline uint32_t ATTRIBUTE_PURE MI_STORE_DATA_IMM_Address_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 46; case 120: return 46; case 110: return 46; case 90: return 46; case 80: return 46; case 75: return 30; case 70: return 30; case 60: return 30; case 50: return 30; case 45: return 30; case 40: return 30; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_STORE_DATA_IMM_Address_start 34 #define GFX12_MI_STORE_DATA_IMM_Address_start 34 #define GFX11_MI_STORE_DATA_IMM_Address_start 34 #define GFX9_MI_STORE_DATA_IMM_Address_start 34 #define GFX8_MI_STORE_DATA_IMM_Address_start 34 #define GFX75_MI_STORE_DATA_IMM_Address_start 66 #define GFX7_MI_STORE_DATA_IMM_Address_start 66 #define GFX6_MI_STORE_DATA_IMM_Address_start 66 #define GFX5_MI_STORE_DATA_IMM_Address_start 66 #define GFX45_MI_STORE_DATA_IMM_Address_start 66 #define GFX4_MI_STORE_DATA_IMM_Address_start 66 static inline uint32_t ATTRIBUTE_PURE MI_STORE_DATA_IMM_Address_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 34; case 120: return 34; case 110: return 34; case 90: return 34; case 80: return 34; case 75: return 66; case 70: return 66; case 60: return 66; case 50: return 66; case 45: return 66; case 40: return 66; default: unreachable("Invalid hardware generation"); } } /* MI_STORE_DATA_IMM::BitFieldName */ #define GFX45_MI_STORE_DATA_IMM_BitFieldName_bits 1 #define GFX4_MI_STORE_DATA_IMM_BitFieldName_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_STORE_DATA_IMM_BitFieldName_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX45_MI_STORE_DATA_IMM_BitFieldName_start 21 #define GFX4_MI_STORE_DATA_IMM_BitFieldName_start 21 static inline uint32_t ATTRIBUTE_PURE MI_STORE_DATA_IMM_BitFieldName_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 21; case 40: return 21; default: unreachable("Invalid hardware generation"); } } /* MI_STORE_DATA_IMM::Command Type */ #define GFX125_MI_STORE_DATA_IMM_CommandType_bits 3 #define GFX12_MI_STORE_DATA_IMM_CommandType_bits 3 #define GFX11_MI_STORE_DATA_IMM_CommandType_bits 3 #define GFX9_MI_STORE_DATA_IMM_CommandType_bits 3 #define GFX8_MI_STORE_DATA_IMM_CommandType_bits 3 #define GFX75_MI_STORE_DATA_IMM_CommandType_bits 3 #define GFX7_MI_STORE_DATA_IMM_CommandType_bits 3 #define GFX6_MI_STORE_DATA_IMM_CommandType_bits 3 #define GFX5_MI_STORE_DATA_IMM_CommandType_bits 3 #define GFX45_MI_STORE_DATA_IMM_CommandType_bits 3 #define GFX4_MI_STORE_DATA_IMM_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE MI_STORE_DATA_IMM_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_STORE_DATA_IMM_CommandType_start 29 #define GFX12_MI_STORE_DATA_IMM_CommandType_start 29 #define GFX11_MI_STORE_DATA_IMM_CommandType_start 29 #define GFX9_MI_STORE_DATA_IMM_CommandType_start 29 #define GFX8_MI_STORE_DATA_IMM_CommandType_start 29 #define GFX75_MI_STORE_DATA_IMM_CommandType_start 29 #define GFX7_MI_STORE_DATA_IMM_CommandType_start 29 #define GFX6_MI_STORE_DATA_IMM_CommandType_start 29 #define GFX5_MI_STORE_DATA_IMM_CommandType_start 29 #define GFX45_MI_STORE_DATA_IMM_CommandType_start 29 #define GFX4_MI_STORE_DATA_IMM_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE MI_STORE_DATA_IMM_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 29; case 50: return 29; case 45: return 29; case 40: return 29; default: unreachable("Invalid hardware generation"); } } /* MI_STORE_DATA_IMM::Core Mode Enable */ #define GFX125_MI_STORE_DATA_IMM_CoreModeEnable_bits 1 #define GFX12_MI_STORE_DATA_IMM_CoreModeEnable_bits 1 #define GFX11_MI_STORE_DATA_IMM_CoreModeEnable_bits 1 #define GFX9_MI_STORE_DATA_IMM_CoreModeEnable_bits 1 #define GFX8_MI_STORE_DATA_IMM_CoreModeEnable_bits 1 #define GFX75_MI_STORE_DATA_IMM_CoreModeEnable_bits 1 #define GFX7_MI_STORE_DATA_IMM_CoreModeEnable_bits 1 #define GFX6_MI_STORE_DATA_IMM_CoreModeEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_STORE_DATA_IMM_CoreModeEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_STORE_DATA_IMM_CoreModeEnable_start 32 #define GFX12_MI_STORE_DATA_IMM_CoreModeEnable_start 32 #define GFX11_MI_STORE_DATA_IMM_CoreModeEnable_start 32 #define GFX9_MI_STORE_DATA_IMM_CoreModeEnable_start 32 #define GFX8_MI_STORE_DATA_IMM_CoreModeEnable_start 32 #define GFX75_MI_STORE_DATA_IMM_CoreModeEnable_start 64 #define GFX7_MI_STORE_DATA_IMM_CoreModeEnable_start 64 #define GFX6_MI_STORE_DATA_IMM_CoreModeEnable_start 64 static inline uint32_t ATTRIBUTE_PURE MI_STORE_DATA_IMM_CoreModeEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 64; case 70: return 64; case 60: return 64; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_STORE_DATA_IMM::DWord Length */ #define GFX125_MI_STORE_DATA_IMM_DWordLength_bits 10 #define GFX12_MI_STORE_DATA_IMM_DWordLength_bits 10 #define GFX11_MI_STORE_DATA_IMM_DWordLength_bits 10 #define GFX9_MI_STORE_DATA_IMM_DWordLength_bits 10 #define GFX8_MI_STORE_DATA_IMM_DWordLength_bits 10 #define GFX75_MI_STORE_DATA_IMM_DWordLength_bits 6 #define GFX7_MI_STORE_DATA_IMM_DWordLength_bits 6 #define GFX6_MI_STORE_DATA_IMM_DWordLength_bits 6 #define GFX5_MI_STORE_DATA_IMM_DWordLength_bits 6 #define GFX45_MI_STORE_DATA_IMM_DWordLength_bits 6 #define GFX4_MI_STORE_DATA_IMM_DWordLength_bits 6 static inline uint32_t ATTRIBUTE_PURE MI_STORE_DATA_IMM_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 10; case 120: return 10; case 110: return 10; case 90: return 10; case 80: return 10; case 75: return 6; case 70: return 6; case 60: return 6; case 50: return 6; case 45: return 6; case 40: return 6; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_STORE_DATA_IMM_DWordLength_start 0 #define GFX12_MI_STORE_DATA_IMM_DWordLength_start 0 #define GFX11_MI_STORE_DATA_IMM_DWordLength_start 0 #define GFX9_MI_STORE_DATA_IMM_DWordLength_start 0 #define GFX8_MI_STORE_DATA_IMM_DWordLength_start 0 #define GFX75_MI_STORE_DATA_IMM_DWordLength_start 0 #define GFX7_MI_STORE_DATA_IMM_DWordLength_start 0 #define GFX6_MI_STORE_DATA_IMM_DWordLength_start 0 #define GFX5_MI_STORE_DATA_IMM_DWordLength_start 0 #define GFX45_MI_STORE_DATA_IMM_DWordLength_start 0 #define GFX4_MI_STORE_DATA_IMM_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE MI_STORE_DATA_IMM_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_STORE_DATA_IMM::Force Write Completion Check */ #define GFX125_MI_STORE_DATA_IMM_ForceWriteCompletionCheck_bits 1 #define GFX12_MI_STORE_DATA_IMM_ForceWriteCompletionCheck_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_STORE_DATA_IMM_ForceWriteCompletionCheck_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_STORE_DATA_IMM_ForceWriteCompletionCheck_start 10 #define GFX12_MI_STORE_DATA_IMM_ForceWriteCompletionCheck_start 10 static inline uint32_t ATTRIBUTE_PURE MI_STORE_DATA_IMM_ForceWriteCompletionCheck_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 10; case 120: return 10; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_STORE_DATA_IMM::Immediate Data */ #define GFX125_MI_STORE_DATA_IMM_ImmediateData_bits 64 #define GFX12_MI_STORE_DATA_IMM_ImmediateData_bits 64 #define GFX11_MI_STORE_DATA_IMM_ImmediateData_bits 64 #define GFX9_MI_STORE_DATA_IMM_ImmediateData_bits 64 #define GFX8_MI_STORE_DATA_IMM_ImmediateData_bits 64 #define GFX75_MI_STORE_DATA_IMM_ImmediateData_bits 64 #define GFX7_MI_STORE_DATA_IMM_ImmediateData_bits 64 #define GFX6_MI_STORE_DATA_IMM_ImmediateData_bits 64 #define GFX5_MI_STORE_DATA_IMM_ImmediateData_bits 64 #define GFX45_MI_STORE_DATA_IMM_ImmediateData_bits 64 #define GFX4_MI_STORE_DATA_IMM_ImmediateData_bits 64 static inline uint32_t ATTRIBUTE_PURE MI_STORE_DATA_IMM_ImmediateData_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 64; case 80: return 64; case 75: return 64; case 70: return 64; case 60: return 64; case 50: return 64; case 45: return 64; case 40: return 64; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_STORE_DATA_IMM_ImmediateData_start 96 #define GFX12_MI_STORE_DATA_IMM_ImmediateData_start 96 #define GFX11_MI_STORE_DATA_IMM_ImmediateData_start 96 #define GFX9_MI_STORE_DATA_IMM_ImmediateData_start 96 #define GFX8_MI_STORE_DATA_IMM_ImmediateData_start 96 #define GFX75_MI_STORE_DATA_IMM_ImmediateData_start 96 #define GFX7_MI_STORE_DATA_IMM_ImmediateData_start 96 #define GFX6_MI_STORE_DATA_IMM_ImmediateData_start 96 #define GFX5_MI_STORE_DATA_IMM_ImmediateData_start 96 #define GFX45_MI_STORE_DATA_IMM_ImmediateData_start 96 #define GFX4_MI_STORE_DATA_IMM_ImmediateData_start 96 static inline uint32_t ATTRIBUTE_PURE MI_STORE_DATA_IMM_ImmediateData_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 96; case 120: return 96; case 110: return 96; case 90: return 96; case 80: return 96; case 75: return 96; case 70: return 96; case 60: return 96; case 50: return 96; case 45: return 96; case 40: return 96; default: unreachable("Invalid hardware generation"); } } /* MI_STORE_DATA_IMM::MI Command Opcode */ #define GFX125_MI_STORE_DATA_IMM_MICommandOpcode_bits 6 #define GFX12_MI_STORE_DATA_IMM_MICommandOpcode_bits 6 #define GFX11_MI_STORE_DATA_IMM_MICommandOpcode_bits 6 #define GFX9_MI_STORE_DATA_IMM_MICommandOpcode_bits 6 #define GFX8_MI_STORE_DATA_IMM_MICommandOpcode_bits 6 #define GFX75_MI_STORE_DATA_IMM_MICommandOpcode_bits 6 #define GFX7_MI_STORE_DATA_IMM_MICommandOpcode_bits 6 #define GFX6_MI_STORE_DATA_IMM_MICommandOpcode_bits 6 #define GFX5_MI_STORE_DATA_IMM_MICommandOpcode_bits 6 #define GFX45_MI_STORE_DATA_IMM_MICommandOpcode_bits 6 #define GFX4_MI_STORE_DATA_IMM_MICommandOpcode_bits 6 static inline uint32_t ATTRIBUTE_PURE MI_STORE_DATA_IMM_MICommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 6; case 60: return 6; case 50: return 6; case 45: return 6; case 40: return 6; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_STORE_DATA_IMM_MICommandOpcode_start 23 #define GFX12_MI_STORE_DATA_IMM_MICommandOpcode_start 23 #define GFX11_MI_STORE_DATA_IMM_MICommandOpcode_start 23 #define GFX9_MI_STORE_DATA_IMM_MICommandOpcode_start 23 #define GFX8_MI_STORE_DATA_IMM_MICommandOpcode_start 23 #define GFX75_MI_STORE_DATA_IMM_MICommandOpcode_start 23 #define GFX7_MI_STORE_DATA_IMM_MICommandOpcode_start 23 #define GFX6_MI_STORE_DATA_IMM_MICommandOpcode_start 23 #define GFX5_MI_STORE_DATA_IMM_MICommandOpcode_start 23 #define GFX45_MI_STORE_DATA_IMM_MICommandOpcode_start 23 #define GFX4_MI_STORE_DATA_IMM_MICommandOpcode_start 23 static inline uint32_t ATTRIBUTE_PURE MI_STORE_DATA_IMM_MICommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 23; case 120: return 23; case 110: return 23; case 90: return 23; case 80: return 23; case 75: return 23; case 70: return 23; case 60: return 23; case 50: return 23; case 45: return 23; case 40: return 23; default: unreachable("Invalid hardware generation"); } } /* MI_STORE_DATA_IMM::Memory Address Type */ #define GFX5_MI_STORE_DATA_IMM_MemoryAddressType_bits 1 #define GFX45_MI_STORE_DATA_IMM_MemoryAddressType_bits 1 #define GFX4_MI_STORE_DATA_IMM_MemoryAddressType_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_STORE_DATA_IMM_MemoryAddressType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_MI_STORE_DATA_IMM_MemoryAddressType_start 22 #define GFX45_MI_STORE_DATA_IMM_MemoryAddressType_start 22 #define GFX4_MI_STORE_DATA_IMM_MemoryAddressType_start 22 static inline uint32_t ATTRIBUTE_PURE MI_STORE_DATA_IMM_MemoryAddressType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 22; case 45: return 22; case 40: return 22; default: unreachable("Invalid hardware generation"); } } /* MI_STORE_DATA_IMM::Physical Start Address Extension */ #define GFX5_MI_STORE_DATA_IMM_PhysicalStartAddressExtension_bits 4 #define GFX45_MI_STORE_DATA_IMM_PhysicalStartAddressExtension_bits 4 #define GFX4_MI_STORE_DATA_IMM_PhysicalStartAddressExtension_bits 4 static inline uint32_t ATTRIBUTE_PURE MI_STORE_DATA_IMM_PhysicalStartAddressExtension_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 4; case 45: return 4; case 40: return 4; default: unreachable("Invalid hardware generation"); } } #define GFX5_MI_STORE_DATA_IMM_PhysicalStartAddressExtension_start 32 #define GFX45_MI_STORE_DATA_IMM_PhysicalStartAddressExtension_start 32 #define GFX4_MI_STORE_DATA_IMM_PhysicalStartAddressExtension_start 32 static inline uint32_t ATTRIBUTE_PURE MI_STORE_DATA_IMM_PhysicalStartAddressExtension_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 32; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } /* MI_STORE_DATA_IMM::Store Qword */ #define GFX125_MI_STORE_DATA_IMM_StoreQword_bits 1 #define GFX12_MI_STORE_DATA_IMM_StoreQword_bits 1 #define GFX11_MI_STORE_DATA_IMM_StoreQword_bits 1 #define GFX9_MI_STORE_DATA_IMM_StoreQword_bits 1 #define GFX8_MI_STORE_DATA_IMM_StoreQword_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_STORE_DATA_IMM_StoreQword_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_STORE_DATA_IMM_StoreQword_start 21 #define GFX12_MI_STORE_DATA_IMM_StoreQword_start 21 #define GFX11_MI_STORE_DATA_IMM_StoreQword_start 21 #define GFX9_MI_STORE_DATA_IMM_StoreQword_start 21 #define GFX8_MI_STORE_DATA_IMM_StoreQword_start 21 static inline uint32_t ATTRIBUTE_PURE MI_STORE_DATA_IMM_StoreQword_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 21; case 120: return 21; case 110: return 21; case 90: return 21; case 80: return 21; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_STORE_DATA_IMM::Use Global GTT */ #define GFX125_MI_STORE_DATA_IMM_UseGlobalGTT_bits 1 #define GFX12_MI_STORE_DATA_IMM_UseGlobalGTT_bits 1 #define GFX11_MI_STORE_DATA_IMM_UseGlobalGTT_bits 1 #define GFX9_MI_STORE_DATA_IMM_UseGlobalGTT_bits 1 #define GFX8_MI_STORE_DATA_IMM_UseGlobalGTT_bits 1 #define GFX75_MI_STORE_DATA_IMM_UseGlobalGTT_bits 1 #define GFX7_MI_STORE_DATA_IMM_UseGlobalGTT_bits 1 #define GFX6_MI_STORE_DATA_IMM_UseGlobalGTT_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_STORE_DATA_IMM_UseGlobalGTT_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_STORE_DATA_IMM_UseGlobalGTT_start 22 #define GFX12_MI_STORE_DATA_IMM_UseGlobalGTT_start 22 #define GFX11_MI_STORE_DATA_IMM_UseGlobalGTT_start 22 #define GFX9_MI_STORE_DATA_IMM_UseGlobalGTT_start 22 #define GFX8_MI_STORE_DATA_IMM_UseGlobalGTT_start 22 #define GFX75_MI_STORE_DATA_IMM_UseGlobalGTT_start 22 #define GFX7_MI_STORE_DATA_IMM_UseGlobalGTT_start 22 #define GFX6_MI_STORE_DATA_IMM_UseGlobalGTT_start 22 static inline uint32_t ATTRIBUTE_PURE MI_STORE_DATA_IMM_UseGlobalGTT_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 22; case 120: return 22; case 110: return 22; case 90: return 22; case 80: return 22; case 75: return 22; case 70: return 22; case 60: return 22; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_STORE_DATA_INDEX */ #define GFX125_MI_STORE_DATA_INDEX_length 3 #define GFX12_MI_STORE_DATA_INDEX_length 3 #define GFX11_MI_STORE_DATA_INDEX_length 3 #define GFX9_MI_STORE_DATA_INDEX_length 3 #define GFX8_MI_STORE_DATA_INDEX_length 3 #define GFX75_MI_STORE_DATA_INDEX_length 3 #define GFX7_MI_STORE_DATA_INDEX_length 3 #define GFX6_MI_STORE_DATA_INDEX_length 3 static inline uint32_t ATTRIBUTE_PURE MI_STORE_DATA_INDEX_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_STORE_DATA_INDEX::Command Type */ #define GFX125_MI_STORE_DATA_INDEX_CommandType_bits 3 #define GFX12_MI_STORE_DATA_INDEX_CommandType_bits 3 #define GFX11_MI_STORE_DATA_INDEX_CommandType_bits 3 #define GFX9_MI_STORE_DATA_INDEX_CommandType_bits 3 #define GFX8_MI_STORE_DATA_INDEX_CommandType_bits 3 #define GFX75_MI_STORE_DATA_INDEX_CommandType_bits 3 #define GFX7_MI_STORE_DATA_INDEX_CommandType_bits 3 #define GFX6_MI_STORE_DATA_INDEX_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE MI_STORE_DATA_INDEX_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_STORE_DATA_INDEX_CommandType_start 29 #define GFX12_MI_STORE_DATA_INDEX_CommandType_start 29 #define GFX11_MI_STORE_DATA_INDEX_CommandType_start 29 #define GFX9_MI_STORE_DATA_INDEX_CommandType_start 29 #define GFX8_MI_STORE_DATA_INDEX_CommandType_start 29 #define GFX75_MI_STORE_DATA_INDEX_CommandType_start 29 #define GFX7_MI_STORE_DATA_INDEX_CommandType_start 29 #define GFX6_MI_STORE_DATA_INDEX_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE MI_STORE_DATA_INDEX_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 29; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_STORE_DATA_INDEX::DWord Length */ #define GFX125_MI_STORE_DATA_INDEX_DWordLength_bits 8 #define GFX12_MI_STORE_DATA_INDEX_DWordLength_bits 8 #define GFX11_MI_STORE_DATA_INDEX_DWordLength_bits 8 #define GFX9_MI_STORE_DATA_INDEX_DWordLength_bits 8 #define GFX8_MI_STORE_DATA_INDEX_DWordLength_bits 8 #define GFX75_MI_STORE_DATA_INDEX_DWordLength_bits 8 #define GFX7_MI_STORE_DATA_INDEX_DWordLength_bits 8 #define GFX6_MI_STORE_DATA_INDEX_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE MI_STORE_DATA_INDEX_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_STORE_DATA_INDEX_DWordLength_start 0 #define GFX12_MI_STORE_DATA_INDEX_DWordLength_start 0 #define GFX11_MI_STORE_DATA_INDEX_DWordLength_start 0 #define GFX9_MI_STORE_DATA_INDEX_DWordLength_start 0 #define GFX8_MI_STORE_DATA_INDEX_DWordLength_start 0 #define GFX75_MI_STORE_DATA_INDEX_DWordLength_start 0 #define GFX7_MI_STORE_DATA_INDEX_DWordLength_start 0 #define GFX6_MI_STORE_DATA_INDEX_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE MI_STORE_DATA_INDEX_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_STORE_DATA_INDEX::Data DWord 0 */ #define GFX125_MI_STORE_DATA_INDEX_DataDWord0_bits 32 #define GFX12_MI_STORE_DATA_INDEX_DataDWord0_bits 32 #define GFX11_MI_STORE_DATA_INDEX_DataDWord0_bits 32 #define GFX9_MI_STORE_DATA_INDEX_DataDWord0_bits 32 #define GFX8_MI_STORE_DATA_INDEX_DataDWord0_bits 32 #define GFX75_MI_STORE_DATA_INDEX_DataDWord0_bits 32 #define GFX7_MI_STORE_DATA_INDEX_DataDWord0_bits 32 #define GFX6_MI_STORE_DATA_INDEX_DataDWord0_bits 32 static inline uint32_t ATTRIBUTE_PURE MI_STORE_DATA_INDEX_DataDWord0_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 32; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_STORE_DATA_INDEX_DataDWord0_start 64 #define GFX12_MI_STORE_DATA_INDEX_DataDWord0_start 64 #define GFX11_MI_STORE_DATA_INDEX_DataDWord0_start 64 #define GFX9_MI_STORE_DATA_INDEX_DataDWord0_start 64 #define GFX8_MI_STORE_DATA_INDEX_DataDWord0_start 64 #define GFX75_MI_STORE_DATA_INDEX_DataDWord0_start 64 #define GFX7_MI_STORE_DATA_INDEX_DataDWord0_start 64 #define GFX6_MI_STORE_DATA_INDEX_DataDWord0_start 64 static inline uint32_t ATTRIBUTE_PURE MI_STORE_DATA_INDEX_DataDWord0_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 64; case 80: return 64; case 75: return 64; case 70: return 64; case 60: return 64; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_STORE_DATA_INDEX::Data DWord 1 */ #define GFX125_MI_STORE_DATA_INDEX_DataDWord1_bits 32 #define GFX12_MI_STORE_DATA_INDEX_DataDWord1_bits 32 #define GFX11_MI_STORE_DATA_INDEX_DataDWord1_bits 32 #define GFX9_MI_STORE_DATA_INDEX_DataDWord1_bits 32 #define GFX8_MI_STORE_DATA_INDEX_DataDWord1_bits 32 #define GFX75_MI_STORE_DATA_INDEX_DataDWord1_bits 32 #define GFX7_MI_STORE_DATA_INDEX_DataDWord1_bits 32 #define GFX6_MI_STORE_DATA_INDEX_DataDWord1_bits 32 static inline uint32_t ATTRIBUTE_PURE MI_STORE_DATA_INDEX_DataDWord1_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 32; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_STORE_DATA_INDEX_DataDWord1_start 96 #define GFX12_MI_STORE_DATA_INDEX_DataDWord1_start 96 #define GFX11_MI_STORE_DATA_INDEX_DataDWord1_start 96 #define GFX9_MI_STORE_DATA_INDEX_DataDWord1_start 96 #define GFX8_MI_STORE_DATA_INDEX_DataDWord1_start 96 #define GFX75_MI_STORE_DATA_INDEX_DataDWord1_start 96 #define GFX7_MI_STORE_DATA_INDEX_DataDWord1_start 96 #define GFX6_MI_STORE_DATA_INDEX_DataDWord1_start 96 static inline uint32_t ATTRIBUTE_PURE MI_STORE_DATA_INDEX_DataDWord1_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 96; case 120: return 96; case 110: return 96; case 90: return 96; case 80: return 96; case 75: return 96; case 70: return 96; case 60: return 96; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_STORE_DATA_INDEX::MI Command Opcode */ #define GFX125_MI_STORE_DATA_INDEX_MICommandOpcode_bits 6 #define GFX12_MI_STORE_DATA_INDEX_MICommandOpcode_bits 6 #define GFX11_MI_STORE_DATA_INDEX_MICommandOpcode_bits 6 #define GFX9_MI_STORE_DATA_INDEX_MICommandOpcode_bits 6 #define GFX8_MI_STORE_DATA_INDEX_MICommandOpcode_bits 6 #define GFX75_MI_STORE_DATA_INDEX_MICommandOpcode_bits 6 #define GFX7_MI_STORE_DATA_INDEX_MICommandOpcode_bits 6 #define GFX6_MI_STORE_DATA_INDEX_MICommandOpcode_bits 6 static inline uint32_t ATTRIBUTE_PURE MI_STORE_DATA_INDEX_MICommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 6; case 60: return 6; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_STORE_DATA_INDEX_MICommandOpcode_start 23 #define GFX12_MI_STORE_DATA_INDEX_MICommandOpcode_start 23 #define GFX11_MI_STORE_DATA_INDEX_MICommandOpcode_start 23 #define GFX9_MI_STORE_DATA_INDEX_MICommandOpcode_start 23 #define GFX8_MI_STORE_DATA_INDEX_MICommandOpcode_start 23 #define GFX75_MI_STORE_DATA_INDEX_MICommandOpcode_start 23 #define GFX7_MI_STORE_DATA_INDEX_MICommandOpcode_start 23 #define GFX6_MI_STORE_DATA_INDEX_MICommandOpcode_start 23 static inline uint32_t ATTRIBUTE_PURE MI_STORE_DATA_INDEX_MICommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 23; case 120: return 23; case 110: return 23; case 90: return 23; case 80: return 23; case 75: return 23; case 70: return 23; case 60: return 23; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_STORE_DATA_INDEX::Offset */ #define GFX125_MI_STORE_DATA_INDEX_Offset_bits 10 #define GFX12_MI_STORE_DATA_INDEX_Offset_bits 10 #define GFX11_MI_STORE_DATA_INDEX_Offset_bits 10 #define GFX9_MI_STORE_DATA_INDEX_Offset_bits 10 #define GFX8_MI_STORE_DATA_INDEX_Offset_bits 10 #define GFX75_MI_STORE_DATA_INDEX_Offset_bits 10 #define GFX7_MI_STORE_DATA_INDEX_Offset_bits 10 #define GFX6_MI_STORE_DATA_INDEX_Offset_bits 10 static inline uint32_t ATTRIBUTE_PURE MI_STORE_DATA_INDEX_Offset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 10; case 120: return 10; case 110: return 10; case 90: return 10; case 80: return 10; case 75: return 10; case 70: return 10; case 60: return 10; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_STORE_DATA_INDEX_Offset_start 34 #define GFX12_MI_STORE_DATA_INDEX_Offset_start 34 #define GFX11_MI_STORE_DATA_INDEX_Offset_start 34 #define GFX9_MI_STORE_DATA_INDEX_Offset_start 34 #define GFX8_MI_STORE_DATA_INDEX_Offset_start 34 #define GFX75_MI_STORE_DATA_INDEX_Offset_start 34 #define GFX7_MI_STORE_DATA_INDEX_Offset_start 34 #define GFX6_MI_STORE_DATA_INDEX_Offset_start 34 static inline uint32_t ATTRIBUTE_PURE MI_STORE_DATA_INDEX_Offset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 34; case 120: return 34; case 110: return 34; case 90: return 34; case 80: return 34; case 75: return 34; case 70: return 34; case 60: return 34; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_STORE_DATA_INDEX::Use Per-Process Hardware Status Page */ #define GFX125_MI_STORE_DATA_INDEX_UsePerProcessHardwareStatusPage_bits 1 #define GFX12_MI_STORE_DATA_INDEX_UsePerProcessHardwareStatusPage_bits 1 #define GFX11_MI_STORE_DATA_INDEX_UsePerProcessHardwareStatusPage_bits 1 #define GFX9_MI_STORE_DATA_INDEX_UsePerProcessHardwareStatusPage_bits 1 #define GFX8_MI_STORE_DATA_INDEX_UsePerProcessHardwareStatusPage_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_STORE_DATA_INDEX_UsePerProcessHardwareStatusPage_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_STORE_DATA_INDEX_UsePerProcessHardwareStatusPage_start 21 #define GFX12_MI_STORE_DATA_INDEX_UsePerProcessHardwareStatusPage_start 21 #define GFX11_MI_STORE_DATA_INDEX_UsePerProcessHardwareStatusPage_start 21 #define GFX9_MI_STORE_DATA_INDEX_UsePerProcessHardwareStatusPage_start 21 #define GFX8_MI_STORE_DATA_INDEX_UsePerProcessHardwareStatusPage_start 21 static inline uint32_t ATTRIBUTE_PURE MI_STORE_DATA_INDEX_UsePerProcessHardwareStatusPage_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 21; case 120: return 21; case 110: return 21; case 90: return 21; case 80: return 21; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_STORE_REGISTER_MEM */ #define GFX125_MI_STORE_REGISTER_MEM_length 4 #define GFX12_MI_STORE_REGISTER_MEM_length 4 #define GFX11_MI_STORE_REGISTER_MEM_length 4 #define GFX9_MI_STORE_REGISTER_MEM_length 4 #define GFX8_MI_STORE_REGISTER_MEM_length 4 #define GFX75_MI_STORE_REGISTER_MEM_length 3 #define GFX7_MI_STORE_REGISTER_MEM_length 3 #define GFX6_MI_STORE_REGISTER_MEM_length 3 #define GFX5_MI_STORE_REGISTER_MEM_length 3 #define GFX45_MI_STORE_REGISTER_MEM_length 3 #define GFX4_MI_STORE_REGISTER_MEM_length 3 static inline uint32_t ATTRIBUTE_PURE MI_STORE_REGISTER_MEM_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } /* MI_STORE_REGISTER_MEM::Add CS MMIO Start Offset */ #define GFX125_MI_STORE_REGISTER_MEM_AddCSMMIOStartOffset_bits 1 #define GFX12_MI_STORE_REGISTER_MEM_AddCSMMIOStartOffset_bits 1 #define GFX11_MI_STORE_REGISTER_MEM_AddCSMMIOStartOffset_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_STORE_REGISTER_MEM_AddCSMMIOStartOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_STORE_REGISTER_MEM_AddCSMMIOStartOffset_start 19 #define GFX12_MI_STORE_REGISTER_MEM_AddCSMMIOStartOffset_start 19 #define GFX11_MI_STORE_REGISTER_MEM_AddCSMMIOStartOffset_start 19 static inline uint32_t ATTRIBUTE_PURE MI_STORE_REGISTER_MEM_AddCSMMIOStartOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 19; case 120: return 19; case 110: return 19; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_STORE_REGISTER_MEM::Command Type */ #define GFX125_MI_STORE_REGISTER_MEM_CommandType_bits 3 #define GFX12_MI_STORE_REGISTER_MEM_CommandType_bits 3 #define GFX11_MI_STORE_REGISTER_MEM_CommandType_bits 3 #define GFX9_MI_STORE_REGISTER_MEM_CommandType_bits 3 #define GFX8_MI_STORE_REGISTER_MEM_CommandType_bits 3 #define GFX75_MI_STORE_REGISTER_MEM_CommandType_bits 3 #define GFX7_MI_STORE_REGISTER_MEM_CommandType_bits 3 #define GFX6_MI_STORE_REGISTER_MEM_CommandType_bits 3 #define GFX5_MI_STORE_REGISTER_MEM_CommandType_bits 3 #define GFX45_MI_STORE_REGISTER_MEM_CommandType_bits 3 #define GFX4_MI_STORE_REGISTER_MEM_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE MI_STORE_REGISTER_MEM_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_STORE_REGISTER_MEM_CommandType_start 29 #define GFX12_MI_STORE_REGISTER_MEM_CommandType_start 29 #define GFX11_MI_STORE_REGISTER_MEM_CommandType_start 29 #define GFX9_MI_STORE_REGISTER_MEM_CommandType_start 29 #define GFX8_MI_STORE_REGISTER_MEM_CommandType_start 29 #define GFX75_MI_STORE_REGISTER_MEM_CommandType_start 29 #define GFX7_MI_STORE_REGISTER_MEM_CommandType_start 29 #define GFX6_MI_STORE_REGISTER_MEM_CommandType_start 29 #define GFX5_MI_STORE_REGISTER_MEM_CommandType_start 29 #define GFX45_MI_STORE_REGISTER_MEM_CommandType_start 29 #define GFX4_MI_STORE_REGISTER_MEM_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE MI_STORE_REGISTER_MEM_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 29; case 50: return 29; case 45: return 29; case 40: return 29; default: unreachable("Invalid hardware generation"); } } /* MI_STORE_REGISTER_MEM::DWord Length */ #define GFX125_MI_STORE_REGISTER_MEM_DWordLength_bits 8 #define GFX12_MI_STORE_REGISTER_MEM_DWordLength_bits 8 #define GFX11_MI_STORE_REGISTER_MEM_DWordLength_bits 8 #define GFX9_MI_STORE_REGISTER_MEM_DWordLength_bits 8 #define GFX8_MI_STORE_REGISTER_MEM_DWordLength_bits 8 #define GFX75_MI_STORE_REGISTER_MEM_DWordLength_bits 8 #define GFX7_MI_STORE_REGISTER_MEM_DWordLength_bits 8 #define GFX6_MI_STORE_REGISTER_MEM_DWordLength_bits 8 #define GFX5_MI_STORE_REGISTER_MEM_DWordLength_bits 8 #define GFX45_MI_STORE_REGISTER_MEM_DWordLength_bits 8 #define GFX4_MI_STORE_REGISTER_MEM_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE MI_STORE_REGISTER_MEM_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 8; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_STORE_REGISTER_MEM_DWordLength_start 0 #define GFX12_MI_STORE_REGISTER_MEM_DWordLength_start 0 #define GFX11_MI_STORE_REGISTER_MEM_DWordLength_start 0 #define GFX9_MI_STORE_REGISTER_MEM_DWordLength_start 0 #define GFX8_MI_STORE_REGISTER_MEM_DWordLength_start 0 #define GFX75_MI_STORE_REGISTER_MEM_DWordLength_start 0 #define GFX7_MI_STORE_REGISTER_MEM_DWordLength_start 0 #define GFX6_MI_STORE_REGISTER_MEM_DWordLength_start 0 #define GFX5_MI_STORE_REGISTER_MEM_DWordLength_start 0 #define GFX45_MI_STORE_REGISTER_MEM_DWordLength_start 0 #define GFX4_MI_STORE_REGISTER_MEM_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE MI_STORE_REGISTER_MEM_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_STORE_REGISTER_MEM::MI Command Opcode */ #define GFX125_MI_STORE_REGISTER_MEM_MICommandOpcode_bits 6 #define GFX12_MI_STORE_REGISTER_MEM_MICommandOpcode_bits 6 #define GFX11_MI_STORE_REGISTER_MEM_MICommandOpcode_bits 6 #define GFX9_MI_STORE_REGISTER_MEM_MICommandOpcode_bits 6 #define GFX8_MI_STORE_REGISTER_MEM_MICommandOpcode_bits 6 #define GFX75_MI_STORE_REGISTER_MEM_MICommandOpcode_bits 6 #define GFX7_MI_STORE_REGISTER_MEM_MICommandOpcode_bits 6 #define GFX6_MI_STORE_REGISTER_MEM_MICommandOpcode_bits 6 #define GFX5_MI_STORE_REGISTER_MEM_MICommandOpcode_bits 6 #define GFX45_MI_STORE_REGISTER_MEM_MICommandOpcode_bits 6 #define GFX4_MI_STORE_REGISTER_MEM_MICommandOpcode_bits 6 static inline uint32_t ATTRIBUTE_PURE MI_STORE_REGISTER_MEM_MICommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 6; case 60: return 6; case 50: return 6; case 45: return 6; case 40: return 6; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_STORE_REGISTER_MEM_MICommandOpcode_start 23 #define GFX12_MI_STORE_REGISTER_MEM_MICommandOpcode_start 23 #define GFX11_MI_STORE_REGISTER_MEM_MICommandOpcode_start 23 #define GFX9_MI_STORE_REGISTER_MEM_MICommandOpcode_start 23 #define GFX8_MI_STORE_REGISTER_MEM_MICommandOpcode_start 23 #define GFX75_MI_STORE_REGISTER_MEM_MICommandOpcode_start 23 #define GFX7_MI_STORE_REGISTER_MEM_MICommandOpcode_start 23 #define GFX6_MI_STORE_REGISTER_MEM_MICommandOpcode_start 23 #define GFX5_MI_STORE_REGISTER_MEM_MICommandOpcode_start 23 #define GFX45_MI_STORE_REGISTER_MEM_MICommandOpcode_start 23 #define GFX4_MI_STORE_REGISTER_MEM_MICommandOpcode_start 23 static inline uint32_t ATTRIBUTE_PURE MI_STORE_REGISTER_MEM_MICommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 23; case 120: return 23; case 110: return 23; case 90: return 23; case 80: return 23; case 75: return 23; case 70: return 23; case 60: return 23; case 50: return 23; case 45: return 23; case 40: return 23; default: unreachable("Invalid hardware generation"); } } /* MI_STORE_REGISTER_MEM::Memory Address */ #define GFX125_MI_STORE_REGISTER_MEM_MemoryAddress_bits 62 #define GFX12_MI_STORE_REGISTER_MEM_MemoryAddress_bits 62 #define GFX11_MI_STORE_REGISTER_MEM_MemoryAddress_bits 62 #define GFX9_MI_STORE_REGISTER_MEM_MemoryAddress_bits 62 #define GFX8_MI_STORE_REGISTER_MEM_MemoryAddress_bits 62 #define GFX75_MI_STORE_REGISTER_MEM_MemoryAddress_bits 30 #define GFX7_MI_STORE_REGISTER_MEM_MemoryAddress_bits 30 #define GFX6_MI_STORE_REGISTER_MEM_MemoryAddress_bits 30 #define GFX5_MI_STORE_REGISTER_MEM_MemoryAddress_bits 30 #define GFX45_MI_STORE_REGISTER_MEM_MemoryAddress_bits 30 #define GFX4_MI_STORE_REGISTER_MEM_MemoryAddress_bits 30 static inline uint32_t ATTRIBUTE_PURE MI_STORE_REGISTER_MEM_MemoryAddress_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 62; case 120: return 62; case 110: return 62; case 90: return 62; case 80: return 62; case 75: return 30; case 70: return 30; case 60: return 30; case 50: return 30; case 45: return 30; case 40: return 30; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_STORE_REGISTER_MEM_MemoryAddress_start 66 #define GFX12_MI_STORE_REGISTER_MEM_MemoryAddress_start 66 #define GFX11_MI_STORE_REGISTER_MEM_MemoryAddress_start 66 #define GFX9_MI_STORE_REGISTER_MEM_MemoryAddress_start 66 #define GFX8_MI_STORE_REGISTER_MEM_MemoryAddress_start 66 #define GFX75_MI_STORE_REGISTER_MEM_MemoryAddress_start 66 #define GFX7_MI_STORE_REGISTER_MEM_MemoryAddress_start 66 #define GFX6_MI_STORE_REGISTER_MEM_MemoryAddress_start 66 #define GFX5_MI_STORE_REGISTER_MEM_MemoryAddress_start 66 #define GFX45_MI_STORE_REGISTER_MEM_MemoryAddress_start 66 #define GFX4_MI_STORE_REGISTER_MEM_MemoryAddress_start 66 static inline uint32_t ATTRIBUTE_PURE MI_STORE_REGISTER_MEM_MemoryAddress_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 66; case 120: return 66; case 110: return 66; case 90: return 66; case 80: return 66; case 75: return 66; case 70: return 66; case 60: return 66; case 50: return 66; case 45: return 66; case 40: return 66; default: unreachable("Invalid hardware generation"); } } /* MI_STORE_REGISTER_MEM::Physical Start Address Extension */ #define GFX45_MI_STORE_REGISTER_MEM_PhysicalStartAddressExtension_bits 4 #define GFX4_MI_STORE_REGISTER_MEM_PhysicalStartAddressExtension_bits 4 static inline uint32_t ATTRIBUTE_PURE MI_STORE_REGISTER_MEM_PhysicalStartAddressExtension_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 4; case 40: return 4; default: unreachable("Invalid hardware generation"); } } #define GFX45_MI_STORE_REGISTER_MEM_PhysicalStartAddressExtension_start 60 #define GFX4_MI_STORE_REGISTER_MEM_PhysicalStartAddressExtension_start 60 static inline uint32_t ATTRIBUTE_PURE MI_STORE_REGISTER_MEM_PhysicalStartAddressExtension_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 60; case 40: return 60; default: unreachable("Invalid hardware generation"); } } /* MI_STORE_REGISTER_MEM::Predicate Enable */ #define GFX125_MI_STORE_REGISTER_MEM_PredicateEnable_bits 1 #define GFX12_MI_STORE_REGISTER_MEM_PredicateEnable_bits 1 #define GFX11_MI_STORE_REGISTER_MEM_PredicateEnable_bits 1 #define GFX9_MI_STORE_REGISTER_MEM_PredicateEnable_bits 1 #define GFX8_MI_STORE_REGISTER_MEM_PredicateEnable_bits 1 #define GFX75_MI_STORE_REGISTER_MEM_PredicateEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_STORE_REGISTER_MEM_PredicateEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_STORE_REGISTER_MEM_PredicateEnable_start 21 #define GFX12_MI_STORE_REGISTER_MEM_PredicateEnable_start 21 #define GFX11_MI_STORE_REGISTER_MEM_PredicateEnable_start 21 #define GFX9_MI_STORE_REGISTER_MEM_PredicateEnable_start 21 #define GFX8_MI_STORE_REGISTER_MEM_PredicateEnable_start 21 #define GFX75_MI_STORE_REGISTER_MEM_PredicateEnable_start 21 static inline uint32_t ATTRIBUTE_PURE MI_STORE_REGISTER_MEM_PredicateEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 21; case 120: return 21; case 110: return 21; case 90: return 21; case 80: return 21; case 75: return 21; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_STORE_REGISTER_MEM::Register Address */ #define GFX125_MI_STORE_REGISTER_MEM_RegisterAddress_bits 21 #define GFX12_MI_STORE_REGISTER_MEM_RegisterAddress_bits 21 #define GFX11_MI_STORE_REGISTER_MEM_RegisterAddress_bits 21 #define GFX9_MI_STORE_REGISTER_MEM_RegisterAddress_bits 21 #define GFX8_MI_STORE_REGISTER_MEM_RegisterAddress_bits 21 #define GFX75_MI_STORE_REGISTER_MEM_RegisterAddress_bits 21 #define GFX7_MI_STORE_REGISTER_MEM_RegisterAddress_bits 21 #define GFX6_MI_STORE_REGISTER_MEM_RegisterAddress_bits 21 #define GFX5_MI_STORE_REGISTER_MEM_RegisterAddress_bits 24 #define GFX45_MI_STORE_REGISTER_MEM_RegisterAddress_bits 21 #define GFX4_MI_STORE_REGISTER_MEM_RegisterAddress_bits 21 static inline uint32_t ATTRIBUTE_PURE MI_STORE_REGISTER_MEM_RegisterAddress_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 21; case 120: return 21; case 110: return 21; case 90: return 21; case 80: return 21; case 75: return 21; case 70: return 21; case 60: return 21; case 50: return 24; case 45: return 21; case 40: return 21; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_STORE_REGISTER_MEM_RegisterAddress_start 34 #define GFX12_MI_STORE_REGISTER_MEM_RegisterAddress_start 34 #define GFX11_MI_STORE_REGISTER_MEM_RegisterAddress_start 34 #define GFX9_MI_STORE_REGISTER_MEM_RegisterAddress_start 34 #define GFX8_MI_STORE_REGISTER_MEM_RegisterAddress_start 34 #define GFX75_MI_STORE_REGISTER_MEM_RegisterAddress_start 34 #define GFX7_MI_STORE_REGISTER_MEM_RegisterAddress_start 34 #define GFX6_MI_STORE_REGISTER_MEM_RegisterAddress_start 34 #define GFX5_MI_STORE_REGISTER_MEM_RegisterAddress_start 34 #define GFX45_MI_STORE_REGISTER_MEM_RegisterAddress_start 34 #define GFX4_MI_STORE_REGISTER_MEM_RegisterAddress_start 34 static inline uint32_t ATTRIBUTE_PURE MI_STORE_REGISTER_MEM_RegisterAddress_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 34; case 120: return 34; case 110: return 34; case 90: return 34; case 80: return 34; case 75: return 34; case 70: return 34; case 60: return 34; case 50: return 34; case 45: return 34; case 40: return 34; default: unreachable("Invalid hardware generation"); } } /* MI_STORE_REGISTER_MEM::Use Global GTT */ #define GFX125_MI_STORE_REGISTER_MEM_UseGlobalGTT_bits 1 #define GFX12_MI_STORE_REGISTER_MEM_UseGlobalGTT_bits 1 #define GFX11_MI_STORE_REGISTER_MEM_UseGlobalGTT_bits 1 #define GFX9_MI_STORE_REGISTER_MEM_UseGlobalGTT_bits 1 #define GFX8_MI_STORE_REGISTER_MEM_UseGlobalGTT_bits 1 #define GFX75_MI_STORE_REGISTER_MEM_UseGlobalGTT_bits 1 #define GFX7_MI_STORE_REGISTER_MEM_UseGlobalGTT_bits 1 #define GFX6_MI_STORE_REGISTER_MEM_UseGlobalGTT_bits 1 #define GFX5_MI_STORE_REGISTER_MEM_UseGlobalGTT_bits 1 #define GFX45_MI_STORE_REGISTER_MEM_UseGlobalGTT_bits 1 #define GFX4_MI_STORE_REGISTER_MEM_UseGlobalGTT_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_STORE_REGISTER_MEM_UseGlobalGTT_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_STORE_REGISTER_MEM_UseGlobalGTT_start 22 #define GFX12_MI_STORE_REGISTER_MEM_UseGlobalGTT_start 22 #define GFX11_MI_STORE_REGISTER_MEM_UseGlobalGTT_start 22 #define GFX9_MI_STORE_REGISTER_MEM_UseGlobalGTT_start 22 #define GFX8_MI_STORE_REGISTER_MEM_UseGlobalGTT_start 22 #define GFX75_MI_STORE_REGISTER_MEM_UseGlobalGTT_start 22 #define GFX7_MI_STORE_REGISTER_MEM_UseGlobalGTT_start 22 #define GFX6_MI_STORE_REGISTER_MEM_UseGlobalGTT_start 22 #define GFX5_MI_STORE_REGISTER_MEM_UseGlobalGTT_start 22 #define GFX45_MI_STORE_REGISTER_MEM_UseGlobalGTT_start 22 #define GFX4_MI_STORE_REGISTER_MEM_UseGlobalGTT_start 22 static inline uint32_t ATTRIBUTE_PURE MI_STORE_REGISTER_MEM_UseGlobalGTT_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 22; case 120: return 22; case 110: return 22; case 90: return 22; case 80: return 22; case 75: return 22; case 70: return 22; case 60: return 22; case 50: return 22; case 45: return 22; case 40: return 22; default: unreachable("Invalid hardware generation"); } } /* MI_STORE_URB_MEM */ #define GFX9_MI_STORE_URB_MEM_length 4 #define GFX8_MI_STORE_URB_MEM_length 4 #define GFX75_MI_STORE_URB_MEM_length 3 static inline uint32_t ATTRIBUTE_PURE MI_STORE_URB_MEM_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 4; case 80: return 4; case 75: return 3; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_STORE_URB_MEM::Command Type */ #define GFX9_MI_STORE_URB_MEM_CommandType_bits 3 #define GFX8_MI_STORE_URB_MEM_CommandType_bits 3 #define GFX75_MI_STORE_URB_MEM_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE MI_STORE_URB_MEM_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_MI_STORE_URB_MEM_CommandType_start 29 #define GFX8_MI_STORE_URB_MEM_CommandType_start 29 #define GFX75_MI_STORE_URB_MEM_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE MI_STORE_URB_MEM_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_STORE_URB_MEM::DWord Length */ #define GFX9_MI_STORE_URB_MEM_DWordLength_bits 8 #define GFX8_MI_STORE_URB_MEM_DWordLength_bits 8 #define GFX75_MI_STORE_URB_MEM_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE MI_STORE_URB_MEM_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_MI_STORE_URB_MEM_DWordLength_start 0 #define GFX8_MI_STORE_URB_MEM_DWordLength_start 0 #define GFX75_MI_STORE_URB_MEM_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE MI_STORE_URB_MEM_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_STORE_URB_MEM::MI Command Opcode */ #define GFX9_MI_STORE_URB_MEM_MICommandOpcode_bits 6 #define GFX8_MI_STORE_URB_MEM_MICommandOpcode_bits 6 #define GFX75_MI_STORE_URB_MEM_MICommandOpcode_bits 6 static inline uint32_t ATTRIBUTE_PURE MI_STORE_URB_MEM_MICommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_MI_STORE_URB_MEM_MICommandOpcode_start 23 #define GFX8_MI_STORE_URB_MEM_MICommandOpcode_start 23 #define GFX75_MI_STORE_URB_MEM_MICommandOpcode_start 23 static inline uint32_t ATTRIBUTE_PURE MI_STORE_URB_MEM_MICommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 23; case 80: return 23; case 75: return 23; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_STORE_URB_MEM::Memory Address */ #define GFX9_MI_STORE_URB_MEM_MemoryAddress_bits 58 #define GFX8_MI_STORE_URB_MEM_MemoryAddress_bits 58 #define GFX75_MI_STORE_URB_MEM_MemoryAddress_bits 26 static inline uint32_t ATTRIBUTE_PURE MI_STORE_URB_MEM_MemoryAddress_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 58; case 80: return 58; case 75: return 26; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_MI_STORE_URB_MEM_MemoryAddress_start 70 #define GFX8_MI_STORE_URB_MEM_MemoryAddress_start 70 #define GFX75_MI_STORE_URB_MEM_MemoryAddress_start 70 static inline uint32_t ATTRIBUTE_PURE MI_STORE_URB_MEM_MemoryAddress_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 70; case 80: return 70; case 75: return 70; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_STORE_URB_MEM::URB Address */ #define GFX9_MI_STORE_URB_MEM_URBAddress_bits 13 #define GFX8_MI_STORE_URB_MEM_URBAddress_bits 13 #define GFX75_MI_STORE_URB_MEM_URBAddress_bits 13 static inline uint32_t ATTRIBUTE_PURE MI_STORE_URB_MEM_URBAddress_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 13; case 80: return 13; case 75: return 13; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_MI_STORE_URB_MEM_URBAddress_start 34 #define GFX8_MI_STORE_URB_MEM_URBAddress_start 34 #define GFX75_MI_STORE_URB_MEM_URBAddress_start 34 static inline uint32_t ATTRIBUTE_PURE MI_STORE_URB_MEM_URBAddress_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 34; case 80: return 34; case 75: return 34; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_SUSPEND_FLUSH */ #define GFX125_MI_SUSPEND_FLUSH_length 1 #define GFX12_MI_SUSPEND_FLUSH_length 1 #define GFX11_MI_SUSPEND_FLUSH_length 1 #define GFX9_MI_SUSPEND_FLUSH_length 1 #define GFX8_MI_SUSPEND_FLUSH_length 1 #define GFX75_MI_SUSPEND_FLUSH_length 1 #define GFX7_MI_SUSPEND_FLUSH_length 1 #define GFX6_MI_SUSPEND_FLUSH_length 1 static inline uint32_t ATTRIBUTE_PURE MI_SUSPEND_FLUSH_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_SUSPEND_FLUSH::Command Type */ #define GFX125_MI_SUSPEND_FLUSH_CommandType_bits 3 #define GFX12_MI_SUSPEND_FLUSH_CommandType_bits 3 #define GFX11_MI_SUSPEND_FLUSH_CommandType_bits 3 #define GFX9_MI_SUSPEND_FLUSH_CommandType_bits 3 #define GFX8_MI_SUSPEND_FLUSH_CommandType_bits 3 #define GFX75_MI_SUSPEND_FLUSH_CommandType_bits 3 #define GFX7_MI_SUSPEND_FLUSH_CommandType_bits 3 #define GFX6_MI_SUSPEND_FLUSH_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE MI_SUSPEND_FLUSH_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_SUSPEND_FLUSH_CommandType_start 29 #define GFX12_MI_SUSPEND_FLUSH_CommandType_start 29 #define GFX11_MI_SUSPEND_FLUSH_CommandType_start 29 #define GFX9_MI_SUSPEND_FLUSH_CommandType_start 29 #define GFX8_MI_SUSPEND_FLUSH_CommandType_start 29 #define GFX75_MI_SUSPEND_FLUSH_CommandType_start 29 #define GFX7_MI_SUSPEND_FLUSH_CommandType_start 29 #define GFX6_MI_SUSPEND_FLUSH_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE MI_SUSPEND_FLUSH_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 29; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_SUSPEND_FLUSH::MI Command Opcode */ #define GFX125_MI_SUSPEND_FLUSH_MICommandOpcode_bits 6 #define GFX12_MI_SUSPEND_FLUSH_MICommandOpcode_bits 6 #define GFX11_MI_SUSPEND_FLUSH_MICommandOpcode_bits 6 #define GFX9_MI_SUSPEND_FLUSH_MICommandOpcode_bits 6 #define GFX8_MI_SUSPEND_FLUSH_MICommandOpcode_bits 6 #define GFX75_MI_SUSPEND_FLUSH_MICommandOpcode_bits 6 #define GFX7_MI_SUSPEND_FLUSH_MICommandOpcode_bits 6 #define GFX6_MI_SUSPEND_FLUSH_MICommandOpcode_bits 6 static inline uint32_t ATTRIBUTE_PURE MI_SUSPEND_FLUSH_MICommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 6; case 60: return 6; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_SUSPEND_FLUSH_MICommandOpcode_start 23 #define GFX12_MI_SUSPEND_FLUSH_MICommandOpcode_start 23 #define GFX11_MI_SUSPEND_FLUSH_MICommandOpcode_start 23 #define GFX9_MI_SUSPEND_FLUSH_MICommandOpcode_start 23 #define GFX8_MI_SUSPEND_FLUSH_MICommandOpcode_start 23 #define GFX75_MI_SUSPEND_FLUSH_MICommandOpcode_start 23 #define GFX7_MI_SUSPEND_FLUSH_MICommandOpcode_start 23 #define GFX6_MI_SUSPEND_FLUSH_MICommandOpcode_start 23 static inline uint32_t ATTRIBUTE_PURE MI_SUSPEND_FLUSH_MICommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 23; case 120: return 23; case 110: return 23; case 90: return 23; case 80: return 23; case 75: return 23; case 70: return 23; case 60: return 23; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_SUSPEND_FLUSH::Suspend Flush */ #define GFX125_MI_SUSPEND_FLUSH_SuspendFlush_bits 1 #define GFX12_MI_SUSPEND_FLUSH_SuspendFlush_bits 1 #define GFX11_MI_SUSPEND_FLUSH_SuspendFlush_bits 1 #define GFX9_MI_SUSPEND_FLUSH_SuspendFlush_bits 1 #define GFX8_MI_SUSPEND_FLUSH_SuspendFlush_bits 1 #define GFX75_MI_SUSPEND_FLUSH_SuspendFlush_bits 1 #define GFX7_MI_SUSPEND_FLUSH_SuspendFlush_bits 1 #define GFX6_MI_SUSPEND_FLUSH_SuspendFlush_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_SUSPEND_FLUSH_SuspendFlush_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_SUSPEND_FLUSH_SuspendFlush_start 0 #define GFX12_MI_SUSPEND_FLUSH_SuspendFlush_start 0 #define GFX11_MI_SUSPEND_FLUSH_SuspendFlush_start 0 #define GFX9_MI_SUSPEND_FLUSH_SuspendFlush_start 0 #define GFX8_MI_SUSPEND_FLUSH_SuspendFlush_start 0 #define GFX75_MI_SUSPEND_FLUSH_SuspendFlush_start 0 #define GFX7_MI_SUSPEND_FLUSH_SuspendFlush_start 0 #define GFX6_MI_SUSPEND_FLUSH_SuspendFlush_start 0 static inline uint32_t ATTRIBUTE_PURE MI_SUSPEND_FLUSH_SuspendFlush_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_TOPOLOGY_FILTER */ #define GFX125_MI_TOPOLOGY_FILTER_length 1 #define GFX12_MI_TOPOLOGY_FILTER_length 1 #define GFX11_MI_TOPOLOGY_FILTER_length 1 #define GFX9_MI_TOPOLOGY_FILTER_length 1 #define GFX8_MI_TOPOLOGY_FILTER_length 1 #define GFX75_MI_TOPOLOGY_FILTER_length 1 #define GFX7_MI_TOPOLOGY_FILTER_length 1 static inline uint32_t ATTRIBUTE_PURE MI_TOPOLOGY_FILTER_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_TOPOLOGY_FILTER::Command Type */ #define GFX125_MI_TOPOLOGY_FILTER_CommandType_bits 3 #define GFX12_MI_TOPOLOGY_FILTER_CommandType_bits 3 #define GFX11_MI_TOPOLOGY_FILTER_CommandType_bits 3 #define GFX9_MI_TOPOLOGY_FILTER_CommandType_bits 3 #define GFX8_MI_TOPOLOGY_FILTER_CommandType_bits 3 #define GFX75_MI_TOPOLOGY_FILTER_CommandType_bits 3 #define GFX7_MI_TOPOLOGY_FILTER_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE MI_TOPOLOGY_FILTER_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_TOPOLOGY_FILTER_CommandType_start 29 #define GFX12_MI_TOPOLOGY_FILTER_CommandType_start 29 #define GFX11_MI_TOPOLOGY_FILTER_CommandType_start 29 #define GFX9_MI_TOPOLOGY_FILTER_CommandType_start 29 #define GFX8_MI_TOPOLOGY_FILTER_CommandType_start 29 #define GFX75_MI_TOPOLOGY_FILTER_CommandType_start 29 #define GFX7_MI_TOPOLOGY_FILTER_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE MI_TOPOLOGY_FILTER_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_TOPOLOGY_FILTER::MI Command Opcode */ #define GFX125_MI_TOPOLOGY_FILTER_MICommandOpcode_bits 6 #define GFX12_MI_TOPOLOGY_FILTER_MICommandOpcode_bits 6 #define GFX11_MI_TOPOLOGY_FILTER_MICommandOpcode_bits 6 #define GFX9_MI_TOPOLOGY_FILTER_MICommandOpcode_bits 6 #define GFX8_MI_TOPOLOGY_FILTER_MICommandOpcode_bits 6 #define GFX75_MI_TOPOLOGY_FILTER_MICommandOpcode_bits 6 #define GFX7_MI_TOPOLOGY_FILTER_MICommandOpcode_bits 6 static inline uint32_t ATTRIBUTE_PURE MI_TOPOLOGY_FILTER_MICommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 6; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_TOPOLOGY_FILTER_MICommandOpcode_start 23 #define GFX12_MI_TOPOLOGY_FILTER_MICommandOpcode_start 23 #define GFX11_MI_TOPOLOGY_FILTER_MICommandOpcode_start 23 #define GFX9_MI_TOPOLOGY_FILTER_MICommandOpcode_start 23 #define GFX8_MI_TOPOLOGY_FILTER_MICommandOpcode_start 23 #define GFX75_MI_TOPOLOGY_FILTER_MICommandOpcode_start 23 #define GFX7_MI_TOPOLOGY_FILTER_MICommandOpcode_start 23 static inline uint32_t ATTRIBUTE_PURE MI_TOPOLOGY_FILTER_MICommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 23; case 120: return 23; case 110: return 23; case 90: return 23; case 80: return 23; case 75: return 23; case 70: return 23; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_TOPOLOGY_FILTER::Topology Filter Value */ #define GFX125_MI_TOPOLOGY_FILTER_TopologyFilterValue_bits 6 #define GFX12_MI_TOPOLOGY_FILTER_TopologyFilterValue_bits 6 #define GFX11_MI_TOPOLOGY_FILTER_TopologyFilterValue_bits 6 #define GFX9_MI_TOPOLOGY_FILTER_TopologyFilterValue_bits 6 #define GFX8_MI_TOPOLOGY_FILTER_TopologyFilterValue_bits 6 #define GFX75_MI_TOPOLOGY_FILTER_TopologyFilterValue_bits 6 #define GFX7_MI_TOPOLOGY_FILTER_TopologyFilterValue_bits 6 static inline uint32_t ATTRIBUTE_PURE MI_TOPOLOGY_FILTER_TopologyFilterValue_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 6; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_TOPOLOGY_FILTER_TopologyFilterValue_start 0 #define GFX12_MI_TOPOLOGY_FILTER_TopologyFilterValue_start 0 #define GFX11_MI_TOPOLOGY_FILTER_TopologyFilterValue_start 0 #define GFX9_MI_TOPOLOGY_FILTER_TopologyFilterValue_start 0 #define GFX8_MI_TOPOLOGY_FILTER_TopologyFilterValue_start 0 #define GFX75_MI_TOPOLOGY_FILTER_TopologyFilterValue_start 0 #define GFX7_MI_TOPOLOGY_FILTER_TopologyFilterValue_start 0 static inline uint32_t ATTRIBUTE_PURE MI_TOPOLOGY_FILTER_TopologyFilterValue_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_URB_ATOMIC_ALLOC */ #define GFX9_MI_URB_ATOMIC_ALLOC_length 1 #define GFX8_MI_URB_ATOMIC_ALLOC_length 1 #define GFX75_MI_URB_ATOMIC_ALLOC_length 1 static inline uint32_t ATTRIBUTE_PURE MI_URB_ATOMIC_ALLOC_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_URB_ATOMIC_ALLOC::Command Type */ #define GFX9_MI_URB_ATOMIC_ALLOC_CommandType_bits 3 #define GFX8_MI_URB_ATOMIC_ALLOC_CommandType_bits 3 #define GFX75_MI_URB_ATOMIC_ALLOC_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE MI_URB_ATOMIC_ALLOC_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_MI_URB_ATOMIC_ALLOC_CommandType_start 29 #define GFX8_MI_URB_ATOMIC_ALLOC_CommandType_start 29 #define GFX75_MI_URB_ATOMIC_ALLOC_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE MI_URB_ATOMIC_ALLOC_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_URB_ATOMIC_ALLOC::MI Command Opcode */ #define GFX9_MI_URB_ATOMIC_ALLOC_MICommandOpcode_bits 6 #define GFX8_MI_URB_ATOMIC_ALLOC_MICommandOpcode_bits 6 #define GFX75_MI_URB_ATOMIC_ALLOC_MICommandOpcode_bits 6 static inline uint32_t ATTRIBUTE_PURE MI_URB_ATOMIC_ALLOC_MICommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_MI_URB_ATOMIC_ALLOC_MICommandOpcode_start 23 #define GFX8_MI_URB_ATOMIC_ALLOC_MICommandOpcode_start 23 #define GFX75_MI_URB_ATOMIC_ALLOC_MICommandOpcode_start 23 static inline uint32_t ATTRIBUTE_PURE MI_URB_ATOMIC_ALLOC_MICommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 23; case 80: return 23; case 75: return 23; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_URB_ATOMIC_ALLOC::URB Atomic Storage Offset */ #define GFX9_MI_URB_ATOMIC_ALLOC_URBAtomicStorageOffset_bits 8 #define GFX8_MI_URB_ATOMIC_ALLOC_URBAtomicStorageOffset_bits 8 #define GFX75_MI_URB_ATOMIC_ALLOC_URBAtomicStorageOffset_bits 8 static inline uint32_t ATTRIBUTE_PURE MI_URB_ATOMIC_ALLOC_URBAtomicStorageOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_MI_URB_ATOMIC_ALLOC_URBAtomicStorageOffset_start 12 #define GFX8_MI_URB_ATOMIC_ALLOC_URBAtomicStorageOffset_start 12 #define GFX75_MI_URB_ATOMIC_ALLOC_URBAtomicStorageOffset_start 12 static inline uint32_t ATTRIBUTE_PURE MI_URB_ATOMIC_ALLOC_URBAtomicStorageOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 12; case 80: return 12; case 75: return 12; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_URB_ATOMIC_ALLOC::URB Atomic Storage Size */ #define GFX9_MI_URB_ATOMIC_ALLOC_URBAtomicStorageSize_bits 9 #define GFX8_MI_URB_ATOMIC_ALLOC_URBAtomicStorageSize_bits 9 #define GFX75_MI_URB_ATOMIC_ALLOC_URBAtomicStorageSize_bits 9 static inline uint32_t ATTRIBUTE_PURE MI_URB_ATOMIC_ALLOC_URBAtomicStorageSize_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 9; case 80: return 9; case 75: return 9; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_MI_URB_ATOMIC_ALLOC_URBAtomicStorageSize_start 0 #define GFX8_MI_URB_ATOMIC_ALLOC_URBAtomicStorageSize_start 0 #define GFX75_MI_URB_ATOMIC_ALLOC_URBAtomicStorageSize_start 0 static inline uint32_t ATTRIBUTE_PURE MI_URB_ATOMIC_ALLOC_URBAtomicStorageSize_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_URB_CLEAR */ #define GFX8_MI_URB_CLEAR_length 2 #define GFX75_MI_URB_CLEAR_length 2 #define GFX7_MI_URB_CLEAR_length 2 #define GFX6_MI_URB_CLEAR_length 2 static inline uint32_t ATTRIBUTE_PURE MI_URB_CLEAR_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_URB_CLEAR::Command Type */ #define GFX8_MI_URB_CLEAR_CommandType_bits 3 #define GFX75_MI_URB_CLEAR_CommandType_bits 3 #define GFX7_MI_URB_CLEAR_CommandType_bits 3 #define GFX6_MI_URB_CLEAR_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE MI_URB_CLEAR_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX8_MI_URB_CLEAR_CommandType_start 29 #define GFX75_MI_URB_CLEAR_CommandType_start 29 #define GFX7_MI_URB_CLEAR_CommandType_start 29 #define GFX6_MI_URB_CLEAR_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE MI_URB_CLEAR_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 29; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_URB_CLEAR::DWord Length */ #define GFX8_MI_URB_CLEAR_DWordLength_bits 8 #define GFX75_MI_URB_CLEAR_DWordLength_bits 8 #define GFX7_MI_URB_CLEAR_DWordLength_bits 8 #define GFX6_MI_URB_CLEAR_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE MI_URB_CLEAR_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX8_MI_URB_CLEAR_DWordLength_start 0 #define GFX75_MI_URB_CLEAR_DWordLength_start 0 #define GFX7_MI_URB_CLEAR_DWordLength_start 0 #define GFX6_MI_URB_CLEAR_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE MI_URB_CLEAR_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_URB_CLEAR::MI Command Opcode */ #define GFX8_MI_URB_CLEAR_MICommandOpcode_bits 6 #define GFX75_MI_URB_CLEAR_MICommandOpcode_bits 6 #define GFX7_MI_URB_CLEAR_MICommandOpcode_bits 6 #define GFX6_MI_URB_CLEAR_MICommandOpcode_bits 6 static inline uint32_t ATTRIBUTE_PURE MI_URB_CLEAR_MICommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 6; case 75: return 6; case 70: return 6; case 60: return 6; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX8_MI_URB_CLEAR_MICommandOpcode_start 23 #define GFX75_MI_URB_CLEAR_MICommandOpcode_start 23 #define GFX7_MI_URB_CLEAR_MICommandOpcode_start 23 #define GFX6_MI_URB_CLEAR_MICommandOpcode_start 23 static inline uint32_t ATTRIBUTE_PURE MI_URB_CLEAR_MICommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 23; case 75: return 23; case 70: return 23; case 60: return 23; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_URB_CLEAR::URB Address */ #define GFX8_MI_URB_CLEAR_URBAddress_bits 15 #define GFX75_MI_URB_CLEAR_URBAddress_bits 15 #define GFX7_MI_URB_CLEAR_URBAddress_bits 14 #define GFX6_MI_URB_CLEAR_URBAddress_bits 14 static inline uint32_t ATTRIBUTE_PURE MI_URB_CLEAR_URBAddress_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 15; case 75: return 15; case 70: return 14; case 60: return 14; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX8_MI_URB_CLEAR_URBAddress_start 32 #define GFX75_MI_URB_CLEAR_URBAddress_start 32 #define GFX7_MI_URB_CLEAR_URBAddress_start 32 #define GFX6_MI_URB_CLEAR_URBAddress_start 32 static inline uint32_t ATTRIBUTE_PURE MI_URB_CLEAR_URBAddress_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 32; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_URB_CLEAR::URB Clear Length */ #define GFX8_MI_URB_CLEAR_URBClearLength_bits 14 #define GFX75_MI_URB_CLEAR_URBClearLength_bits 14 #define GFX7_MI_URB_CLEAR_URBClearLength_bits 13 #define GFX6_MI_URB_CLEAR_URBClearLength_bits 13 static inline uint32_t ATTRIBUTE_PURE MI_URB_CLEAR_URBClearLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 14; case 75: return 14; case 70: return 13; case 60: return 13; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX8_MI_URB_CLEAR_URBClearLength_start 48 #define GFX75_MI_URB_CLEAR_URBClearLength_start 48 #define GFX7_MI_URB_CLEAR_URBClearLength_start 48 #define GFX6_MI_URB_CLEAR_URBClearLength_start 48 static inline uint32_t ATTRIBUTE_PURE MI_URB_CLEAR_URBClearLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 48; case 75: return 48; case 70: return 48; case 60: return 48; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_USER_INTERRUPT */ #define GFX125_MI_USER_INTERRUPT_length 1 #define GFX12_MI_USER_INTERRUPT_length 1 #define GFX11_MI_USER_INTERRUPT_length 1 #define GFX9_MI_USER_INTERRUPT_length 1 #define GFX8_MI_USER_INTERRUPT_length 1 #define GFX75_MI_USER_INTERRUPT_length 1 #define GFX7_MI_USER_INTERRUPT_length 1 #define GFX6_MI_USER_INTERRUPT_length 1 static inline uint32_t ATTRIBUTE_PURE MI_USER_INTERRUPT_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_USER_INTERRUPT::Command Type */ #define GFX125_MI_USER_INTERRUPT_CommandType_bits 3 #define GFX12_MI_USER_INTERRUPT_CommandType_bits 3 #define GFX11_MI_USER_INTERRUPT_CommandType_bits 3 #define GFX9_MI_USER_INTERRUPT_CommandType_bits 3 #define GFX8_MI_USER_INTERRUPT_CommandType_bits 3 #define GFX75_MI_USER_INTERRUPT_CommandType_bits 3 #define GFX7_MI_USER_INTERRUPT_CommandType_bits 3 #define GFX6_MI_USER_INTERRUPT_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE MI_USER_INTERRUPT_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_USER_INTERRUPT_CommandType_start 29 #define GFX12_MI_USER_INTERRUPT_CommandType_start 29 #define GFX11_MI_USER_INTERRUPT_CommandType_start 29 #define GFX9_MI_USER_INTERRUPT_CommandType_start 29 #define GFX8_MI_USER_INTERRUPT_CommandType_start 29 #define GFX75_MI_USER_INTERRUPT_CommandType_start 29 #define GFX7_MI_USER_INTERRUPT_CommandType_start 29 #define GFX6_MI_USER_INTERRUPT_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE MI_USER_INTERRUPT_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 29; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_USER_INTERRUPT::MI Command Opcode */ #define GFX125_MI_USER_INTERRUPT_MICommandOpcode_bits 6 #define GFX12_MI_USER_INTERRUPT_MICommandOpcode_bits 6 #define GFX11_MI_USER_INTERRUPT_MICommandOpcode_bits 6 #define GFX9_MI_USER_INTERRUPT_MICommandOpcode_bits 6 #define GFX8_MI_USER_INTERRUPT_MICommandOpcode_bits 6 #define GFX75_MI_USER_INTERRUPT_MICommandOpcode_bits 6 #define GFX7_MI_USER_INTERRUPT_MICommandOpcode_bits 6 #define GFX6_MI_USER_INTERRUPT_MICommandOpcode_bits 6 static inline uint32_t ATTRIBUTE_PURE MI_USER_INTERRUPT_MICommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 6; case 60: return 6; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_USER_INTERRUPT_MICommandOpcode_start 23 #define GFX12_MI_USER_INTERRUPT_MICommandOpcode_start 23 #define GFX11_MI_USER_INTERRUPT_MICommandOpcode_start 23 #define GFX9_MI_USER_INTERRUPT_MICommandOpcode_start 23 #define GFX8_MI_USER_INTERRUPT_MICommandOpcode_start 23 #define GFX75_MI_USER_INTERRUPT_MICommandOpcode_start 23 #define GFX7_MI_USER_INTERRUPT_MICommandOpcode_start 23 #define GFX6_MI_USER_INTERRUPT_MICommandOpcode_start 23 static inline uint32_t ATTRIBUTE_PURE MI_USER_INTERRUPT_MICommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 23; case 120: return 23; case 110: return 23; case 90: return 23; case 80: return 23; case 75: return 23; case 70: return 23; case 60: return 23; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_WAIT_FOR_EVENT */ #define GFX125_MI_WAIT_FOR_EVENT_length 1 #define GFX12_MI_WAIT_FOR_EVENT_length 1 #define GFX11_MI_WAIT_FOR_EVENT_length 1 #define GFX9_MI_WAIT_FOR_EVENT_length 1 #define GFX8_MI_WAIT_FOR_EVENT_length 1 #define GFX75_MI_WAIT_FOR_EVENT_length 1 #define GFX7_MI_WAIT_FOR_EVENT_length 1 #define GFX6_MI_WAIT_FOR_EVENT_length 1 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_WAIT_FOR_EVENT::Command Type */ #define GFX125_MI_WAIT_FOR_EVENT_CommandType_bits 3 #define GFX12_MI_WAIT_FOR_EVENT_CommandType_bits 3 #define GFX11_MI_WAIT_FOR_EVENT_CommandType_bits 3 #define GFX9_MI_WAIT_FOR_EVENT_CommandType_bits 3 #define GFX8_MI_WAIT_FOR_EVENT_CommandType_bits 3 #define GFX75_MI_WAIT_FOR_EVENT_CommandType_bits 3 #define GFX7_MI_WAIT_FOR_EVENT_CommandType_bits 3 #define GFX6_MI_WAIT_FOR_EVENT_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_WAIT_FOR_EVENT_CommandType_start 29 #define GFX12_MI_WAIT_FOR_EVENT_CommandType_start 29 #define GFX11_MI_WAIT_FOR_EVENT_CommandType_start 29 #define GFX9_MI_WAIT_FOR_EVENT_CommandType_start 29 #define GFX8_MI_WAIT_FOR_EVENT_CommandType_start 29 #define GFX75_MI_WAIT_FOR_EVENT_CommandType_start 29 #define GFX7_MI_WAIT_FOR_EVENT_CommandType_start 29 #define GFX6_MI_WAIT_FOR_EVENT_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 29; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_WAIT_FOR_EVENT::Condition Code Wait Select */ #define GFX75_MI_WAIT_FOR_EVENT_ConditionCodeWaitSelect_bits 4 #define GFX7_MI_WAIT_FOR_EVENT_ConditionCodeWaitSelect_bits 4 #define GFX6_MI_WAIT_FOR_EVENT_ConditionCodeWaitSelect_bits 4 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_ConditionCodeWaitSelect_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 4; case 70: return 4; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_MI_WAIT_FOR_EVENT_ConditionCodeWaitSelect_start 16 #define GFX7_MI_WAIT_FOR_EVENT_ConditionCodeWaitSelect_start 16 #define GFX6_MI_WAIT_FOR_EVENT_ConditionCodeWaitSelect_start 16 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_ConditionCodeWaitSelect_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 16; case 70: return 16; case 60: return 16; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_WAIT_FOR_EVENT::Display Pipe A Horizontal Blank Wait Enable */ #define GFX75_MI_WAIT_FOR_EVENT_DisplayPipeAHorizontalBlankWaitEnable_bits 1 #define GFX7_MI_WAIT_FOR_EVENT_DisplayPipeAHorizontalBlankWaitEnable_bits 1 #define GFX6_MI_WAIT_FOR_EVENT_DisplayPipeAHorizontalBlankWaitEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_DisplayPipeAHorizontalBlankWaitEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_MI_WAIT_FOR_EVENT_DisplayPipeAHorizontalBlankWaitEnable_start 5 #define GFX7_MI_WAIT_FOR_EVENT_DisplayPipeAHorizontalBlankWaitEnable_start 5 #define GFX6_MI_WAIT_FOR_EVENT_DisplayPipeAHorizontalBlankWaitEnable_start 5 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_DisplayPipeAHorizontalBlankWaitEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 5; case 70: return 5; case 60: return 5; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_WAIT_FOR_EVENT::Display Pipe A Scan Line Wait Enable */ #define GFX8_MI_WAIT_FOR_EVENT_DisplayPipeAScanLineWaitEnable_bits 1 #define GFX75_MI_WAIT_FOR_EVENT_DisplayPipeAScanLineWaitEnable_bits 1 #define GFX7_MI_WAIT_FOR_EVENT_DisplayPipeAScanLineWaitEnable_bits 1 #define GFX6_MI_WAIT_FOR_EVENT_DisplayPipeAScanLineWaitEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_DisplayPipeAScanLineWaitEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX8_MI_WAIT_FOR_EVENT_DisplayPipeAScanLineWaitEnable_start 0 #define GFX75_MI_WAIT_FOR_EVENT_DisplayPipeAScanLineWaitEnable_start 0 #define GFX7_MI_WAIT_FOR_EVENT_DisplayPipeAScanLineWaitEnable_start 0 #define GFX6_MI_WAIT_FOR_EVENT_DisplayPipeAScanLineWaitEnable_start 0 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_DisplayPipeAScanLineWaitEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_WAIT_FOR_EVENT::Display Pipe A Vertical Blank Wait Enable */ #define GFX8_MI_WAIT_FOR_EVENT_DisplayPipeAVerticalBlankWaitEnable_bits 1 #define GFX75_MI_WAIT_FOR_EVENT_DisplayPipeAVerticalBlankWaitEnable_bits 1 #define GFX7_MI_WAIT_FOR_EVENT_DisplayPipeAVerticalBlankWaitEnable_bits 1 #define GFX6_MI_WAIT_FOR_EVENT_DisplayPipeAVerticalBlankWaitEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_DisplayPipeAVerticalBlankWaitEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX8_MI_WAIT_FOR_EVENT_DisplayPipeAVerticalBlankWaitEnable_start 3 #define GFX75_MI_WAIT_FOR_EVENT_DisplayPipeAVerticalBlankWaitEnable_start 3 #define GFX7_MI_WAIT_FOR_EVENT_DisplayPipeAVerticalBlankWaitEnable_start 3 #define GFX6_MI_WAIT_FOR_EVENT_DisplayPipeAVerticalBlankWaitEnable_start 3 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_DisplayPipeAVerticalBlankWaitEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_WAIT_FOR_EVENT::Display Pipe B Horizontal Blank Wait Enable */ #define GFX75_MI_WAIT_FOR_EVENT_DisplayPipeBHorizontalBlankWaitEnable_bits 1 #define GFX7_MI_WAIT_FOR_EVENT_DisplayPipeBHorizontalBlankWaitEnable_bits 1 #define GFX6_MI_WAIT_FOR_EVENT_DisplayPipeBHorizontalBlankWaitEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_DisplayPipeBHorizontalBlankWaitEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_MI_WAIT_FOR_EVENT_DisplayPipeBHorizontalBlankWaitEnable_start 13 #define GFX7_MI_WAIT_FOR_EVENT_DisplayPipeBHorizontalBlankWaitEnable_start 13 #define GFX6_MI_WAIT_FOR_EVENT_DisplayPipeBHorizontalBlankWaitEnable_start 13 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_DisplayPipeBHorizontalBlankWaitEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 13; case 70: return 13; case 60: return 13; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_WAIT_FOR_EVENT::Display Pipe B Scan Line Wait Enable */ #define GFX8_MI_WAIT_FOR_EVENT_DisplayPipeBScanLineWaitEnable_bits 1 #define GFX75_MI_WAIT_FOR_EVENT_DisplayPipeBScanLineWaitEnable_bits 1 #define GFX7_MI_WAIT_FOR_EVENT_DisplayPipeBScanLineWaitEnable_bits 1 #define GFX6_MI_WAIT_FOR_EVENT_DisplayPipeBScanLineWaitEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_DisplayPipeBScanLineWaitEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX8_MI_WAIT_FOR_EVENT_DisplayPipeBScanLineWaitEnable_start 8 #define GFX75_MI_WAIT_FOR_EVENT_DisplayPipeBScanLineWaitEnable_start 8 #define GFX7_MI_WAIT_FOR_EVENT_DisplayPipeBScanLineWaitEnable_start 8 #define GFX6_MI_WAIT_FOR_EVENT_DisplayPipeBScanLineWaitEnable_start 8 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_DisplayPipeBScanLineWaitEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_WAIT_FOR_EVENT::Display Pipe B Vertical Blank Wait Enable */ #define GFX8_MI_WAIT_FOR_EVENT_DisplayPipeBVerticalBlankWaitEnable_bits 1 #define GFX75_MI_WAIT_FOR_EVENT_DisplayPipeBVerticalBlankWaitEnable_bits 1 #define GFX7_MI_WAIT_FOR_EVENT_DisplayPipeBVerticalBlankWaitEnable_bits 1 #define GFX6_MI_WAIT_FOR_EVENT_DisplayPipeBVerticalBlankWaitEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_DisplayPipeBVerticalBlankWaitEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX8_MI_WAIT_FOR_EVENT_DisplayPipeBVerticalBlankWaitEnable_start 11 #define GFX75_MI_WAIT_FOR_EVENT_DisplayPipeBVerticalBlankWaitEnable_start 11 #define GFX7_MI_WAIT_FOR_EVENT_DisplayPipeBVerticalBlankWaitEnable_start 11 #define GFX6_MI_WAIT_FOR_EVENT_DisplayPipeBVerticalBlankWaitEnable_start 11 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_DisplayPipeBVerticalBlankWaitEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 11; case 75: return 11; case 70: return 11; case 60: return 11; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_WAIT_FOR_EVENT::Display Pipe C Horizontal Blank Wait Enable */ #define GFX75_MI_WAIT_FOR_EVENT_DisplayPipeCHorizontalBlankWaitEnable_bits 1 #define GFX7_MI_WAIT_FOR_EVENT_DisplayPipeCHorizontalBlankWaitEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_DisplayPipeCHorizontalBlankWaitEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_MI_WAIT_FOR_EVENT_DisplayPipeCHorizontalBlankWaitEnable_start 22 #define GFX7_MI_WAIT_FOR_EVENT_DisplayPipeCHorizontalBlankWaitEnable_start 22 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_DisplayPipeCHorizontalBlankWaitEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 22; case 70: return 22; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_WAIT_FOR_EVENT::Display Pipe C Scan Line Wait Enable */ #define GFX8_MI_WAIT_FOR_EVENT_DisplayPipeCScanLineWaitEnable_bits 1 #define GFX75_MI_WAIT_FOR_EVENT_DisplayPipeCScanLineWaitEnable_bits 1 #define GFX7_MI_WAIT_FOR_EVENT_DisplayPipeCScanLineWaitEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_DisplayPipeCScanLineWaitEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX8_MI_WAIT_FOR_EVENT_DisplayPipeCScanLineWaitEnable_start 14 #define GFX75_MI_WAIT_FOR_EVENT_DisplayPipeCScanLineWaitEnable_start 14 #define GFX7_MI_WAIT_FOR_EVENT_DisplayPipeCScanLineWaitEnable_start 14 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_DisplayPipeCScanLineWaitEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 14; case 75: return 14; case 70: return 14; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_WAIT_FOR_EVENT::Display Pipe C Vertical Blank Wait Enable */ #define GFX8_MI_WAIT_FOR_EVENT_DisplayPipeCVerticalBlankWaitEnable_bits 1 #define GFX75_MI_WAIT_FOR_EVENT_DisplayPipeCVerticalBlankWaitEnable_bits 1 #define GFX7_MI_WAIT_FOR_EVENT_DisplayPipeCVerticalBlankWaitEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_DisplayPipeCVerticalBlankWaitEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX8_MI_WAIT_FOR_EVENT_DisplayPipeCVerticalBlankWaitEnable_start 21 #define GFX75_MI_WAIT_FOR_EVENT_DisplayPipeCVerticalBlankWaitEnable_start 21 #define GFX7_MI_WAIT_FOR_EVENT_DisplayPipeCVerticalBlankWaitEnable_start 21 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_DisplayPipeCVerticalBlankWaitEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 21; case 75: return 21; case 70: return 21; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_WAIT_FOR_EVENT::Display Plane 10 Flip Pending Wait Enable */ #define GFX125_MI_WAIT_FOR_EVENT_DisplayPlane10FlipPendingWaitEnable_bits 1 #define GFX12_MI_WAIT_FOR_EVENT_DisplayPlane10FlipPendingWaitEnable_bits 1 #define GFX11_MI_WAIT_FOR_EVENT_DisplayPlane10FlipPendingWaitEnable_bits 1 #define GFX9_MI_WAIT_FOR_EVENT_DisplayPlane10FlipPendingWaitEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_DisplayPlane10FlipPendingWaitEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_WAIT_FOR_EVENT_DisplayPlane10FlipPendingWaitEnable_start 17 #define GFX12_MI_WAIT_FOR_EVENT_DisplayPlane10FlipPendingWaitEnable_start 17 #define GFX11_MI_WAIT_FOR_EVENT_DisplayPlane10FlipPendingWaitEnable_start 17 #define GFX9_MI_WAIT_FOR_EVENT_DisplayPlane10FlipPendingWaitEnable_start 17 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_DisplayPlane10FlipPendingWaitEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 17; case 120: return 17; case 110: return 17; case 90: return 17; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_WAIT_FOR_EVENT::Display Plane 11 Flip Pending Wait Enable */ #define GFX125_MI_WAIT_FOR_EVENT_DisplayPlane11FlipPendingWaitEnable_bits 1 #define GFX12_MI_WAIT_FOR_EVENT_DisplayPlane11FlipPendingWaitEnable_bits 1 #define GFX11_MI_WAIT_FOR_EVENT_DisplayPlane11FlipPendingWaitEnable_bits 1 #define GFX9_MI_WAIT_FOR_EVENT_DisplayPlane11FlipPendingWaitEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_DisplayPlane11FlipPendingWaitEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_WAIT_FOR_EVENT_DisplayPlane11FlipPendingWaitEnable_start 18 #define GFX12_MI_WAIT_FOR_EVENT_DisplayPlane11FlipPendingWaitEnable_start 18 #define GFX11_MI_WAIT_FOR_EVENT_DisplayPlane11FlipPendingWaitEnable_start 18 #define GFX9_MI_WAIT_FOR_EVENT_DisplayPlane11FlipPendingWaitEnable_start 18 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_DisplayPlane11FlipPendingWaitEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 18; case 120: return 18; case 110: return 18; case 90: return 18; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_WAIT_FOR_EVENT::Display Plane 12 Flip Pending Wait Enable */ #define GFX125_MI_WAIT_FOR_EVENT_DisplayPlane12FlipPendingWaitEnable_bits 1 #define GFX12_MI_WAIT_FOR_EVENT_DisplayPlane12FlipPendingWaitEnable_bits 1 #define GFX11_MI_WAIT_FOR_EVENT_DisplayPlane12FlipPendingWaitEnable_bits 1 #define GFX9_MI_WAIT_FOR_EVENT_DisplayPlane12FlipPendingWaitEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_DisplayPlane12FlipPendingWaitEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_WAIT_FOR_EVENT_DisplayPlane12FlipPendingWaitEnable_start 19 #define GFX12_MI_WAIT_FOR_EVENT_DisplayPlane12FlipPendingWaitEnable_start 19 #define GFX11_MI_WAIT_FOR_EVENT_DisplayPlane12FlipPendingWaitEnable_start 19 #define GFX9_MI_WAIT_FOR_EVENT_DisplayPlane12FlipPendingWaitEnable_start 19 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_DisplayPlane12FlipPendingWaitEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 19; case 120: return 19; case 110: return 19; case 90: return 19; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_WAIT_FOR_EVENT::Display Plane 1 A Vertical Blank Wait Enable */ #define GFX125_MI_WAIT_FOR_EVENT_DisplayPlane1AVerticalBlankWaitEnable_bits 1 #define GFX12_MI_WAIT_FOR_EVENT_DisplayPlane1AVerticalBlankWaitEnable_bits 1 #define GFX11_MI_WAIT_FOR_EVENT_DisplayPlane1AVerticalBlankWaitEnable_bits 1 #define GFX9_MI_WAIT_FOR_EVENT_DisplayPlane1AVerticalBlankWaitEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_DisplayPlane1AVerticalBlankWaitEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_WAIT_FOR_EVENT_DisplayPlane1AVerticalBlankWaitEnable_start 3 #define GFX12_MI_WAIT_FOR_EVENT_DisplayPlane1AVerticalBlankWaitEnable_start 3 #define GFX11_MI_WAIT_FOR_EVENT_DisplayPlane1AVerticalBlankWaitEnable_start 3 #define GFX9_MI_WAIT_FOR_EVENT_DisplayPlane1AVerticalBlankWaitEnable_start 3 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_DisplayPlane1AVerticalBlankWaitEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_WAIT_FOR_EVENT::Display Plane 1 B Scan Line Wait Enable */ #define GFX125_MI_WAIT_FOR_EVENT_DisplayPlane1BScanLineWaitEnable_bits 1 #define GFX12_MI_WAIT_FOR_EVENT_DisplayPlane1BScanLineWaitEnable_bits 1 #define GFX11_MI_WAIT_FOR_EVENT_DisplayPlane1BScanLineWaitEnable_bits 1 #define GFX9_MI_WAIT_FOR_EVENT_DisplayPlane1BScanLineWaitEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_DisplayPlane1BScanLineWaitEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_WAIT_FOR_EVENT_DisplayPlane1BScanLineWaitEnable_start 8 #define GFX12_MI_WAIT_FOR_EVENT_DisplayPlane1BScanLineWaitEnable_start 8 #define GFX11_MI_WAIT_FOR_EVENT_DisplayPlane1BScanLineWaitEnable_start 8 #define GFX9_MI_WAIT_FOR_EVENT_DisplayPlane1BScanLineWaitEnable_start 8 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_DisplayPlane1BScanLineWaitEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_WAIT_FOR_EVENT::Display Plane 1 B Vertical Blank Wait Enable */ #define GFX125_MI_WAIT_FOR_EVENT_DisplayPlane1BVerticalBlankWaitEnable_bits 1 #define GFX12_MI_WAIT_FOR_EVENT_DisplayPlane1BVerticalBlankWaitEnable_bits 1 #define GFX11_MI_WAIT_FOR_EVENT_DisplayPlane1BVerticalBlankWaitEnable_bits 1 #define GFX9_MI_WAIT_FOR_EVENT_DisplayPlane1BVerticalBlankWaitEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_DisplayPlane1BVerticalBlankWaitEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_WAIT_FOR_EVENT_DisplayPlane1BVerticalBlankWaitEnable_start 11 #define GFX12_MI_WAIT_FOR_EVENT_DisplayPlane1BVerticalBlankWaitEnable_start 11 #define GFX11_MI_WAIT_FOR_EVENT_DisplayPlane1BVerticalBlankWaitEnable_start 11 #define GFX9_MI_WAIT_FOR_EVENT_DisplayPlane1BVerticalBlankWaitEnable_start 11 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_DisplayPlane1BVerticalBlankWaitEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 11; case 120: return 11; case 110: return 11; case 90: return 11; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_WAIT_FOR_EVENT::Display Plane 1 C Scan Line Wait Enable */ #define GFX125_MI_WAIT_FOR_EVENT_DisplayPlane1CScanLineWaitEnable_bits 1 #define GFX12_MI_WAIT_FOR_EVENT_DisplayPlane1CScanLineWaitEnable_bits 1 #define GFX11_MI_WAIT_FOR_EVENT_DisplayPlane1CScanLineWaitEnable_bits 1 #define GFX9_MI_WAIT_FOR_EVENT_DisplayPlane1CScanLineWaitEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_DisplayPlane1CScanLineWaitEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_WAIT_FOR_EVENT_DisplayPlane1CScanLineWaitEnable_start 14 #define GFX12_MI_WAIT_FOR_EVENT_DisplayPlane1CScanLineWaitEnable_start 14 #define GFX11_MI_WAIT_FOR_EVENT_DisplayPlane1CScanLineWaitEnable_start 14 #define GFX9_MI_WAIT_FOR_EVENT_DisplayPlane1CScanLineWaitEnable_start 14 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_DisplayPlane1CScanLineWaitEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 14; case 120: return 14; case 110: return 14; case 90: return 14; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_WAIT_FOR_EVENT::Display Plane 1 C Vertical Blank Wait Enable */ #define GFX125_MI_WAIT_FOR_EVENT_DisplayPlane1CVerticalBlankWaitEnable_bits 1 #define GFX12_MI_WAIT_FOR_EVENT_DisplayPlane1CVerticalBlankWaitEnable_bits 1 #define GFX11_MI_WAIT_FOR_EVENT_DisplayPlane1CVerticalBlankWaitEnable_bits 1 #define GFX9_MI_WAIT_FOR_EVENT_DisplayPlane1CVerticalBlankWaitEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_DisplayPlane1CVerticalBlankWaitEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_WAIT_FOR_EVENT_DisplayPlane1CVerticalBlankWaitEnable_start 21 #define GFX12_MI_WAIT_FOR_EVENT_DisplayPlane1CVerticalBlankWaitEnable_start 21 #define GFX11_MI_WAIT_FOR_EVENT_DisplayPlane1CVerticalBlankWaitEnable_start 21 #define GFX9_MI_WAIT_FOR_EVENT_DisplayPlane1CVerticalBlankWaitEnable_start 21 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_DisplayPlane1CVerticalBlankWaitEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 21; case 120: return 21; case 110: return 21; case 90: return 21; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_WAIT_FOR_EVENT::Display Plane 1 Flip Pending Wait Enable */ #define GFX125_MI_WAIT_FOR_EVENT_DisplayPlane1FlipPendingWaitEnable_bits 1 #define GFX12_MI_WAIT_FOR_EVENT_DisplayPlane1FlipPendingWaitEnable_bits 1 #define GFX11_MI_WAIT_FOR_EVENT_DisplayPlane1FlipPendingWaitEnable_bits 1 #define GFX9_MI_WAIT_FOR_EVENT_DisplayPlane1FlipPendingWaitEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_DisplayPlane1FlipPendingWaitEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_WAIT_FOR_EVENT_DisplayPlane1FlipPendingWaitEnable_start 1 #define GFX12_MI_WAIT_FOR_EVENT_DisplayPlane1FlipPendingWaitEnable_start 1 #define GFX11_MI_WAIT_FOR_EVENT_DisplayPlane1FlipPendingWaitEnable_start 1 #define GFX9_MI_WAIT_FOR_EVENT_DisplayPlane1FlipPendingWaitEnable_start 1 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_DisplayPlane1FlipPendingWaitEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_WAIT_FOR_EVENT::Display Plane 2 Flip Pending Wait Enable */ #define GFX125_MI_WAIT_FOR_EVENT_DisplayPlane2FlipPendingWaitEnable_bits 1 #define GFX12_MI_WAIT_FOR_EVENT_DisplayPlane2FlipPendingWaitEnable_bits 1 #define GFX11_MI_WAIT_FOR_EVENT_DisplayPlane2FlipPendingWaitEnable_bits 1 #define GFX9_MI_WAIT_FOR_EVENT_DisplayPlane2FlipPendingWaitEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_DisplayPlane2FlipPendingWaitEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_WAIT_FOR_EVENT_DisplayPlane2FlipPendingWaitEnable_start 9 #define GFX12_MI_WAIT_FOR_EVENT_DisplayPlane2FlipPendingWaitEnable_start 9 #define GFX11_MI_WAIT_FOR_EVENT_DisplayPlane2FlipPendingWaitEnable_start 9 #define GFX9_MI_WAIT_FOR_EVENT_DisplayPlane2FlipPendingWaitEnable_start 9 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_DisplayPlane2FlipPendingWaitEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 9; case 120: return 9; case 110: return 9; case 90: return 9; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_WAIT_FOR_EVENT::Display Plane 3 Flip Pending Wait Enable */ #define GFX125_MI_WAIT_FOR_EVENT_DisplayPlane3FlipPendingWaitEnable_bits 1 #define GFX12_MI_WAIT_FOR_EVENT_DisplayPlane3FlipPendingWaitEnable_bits 1 #define GFX11_MI_WAIT_FOR_EVENT_DisplayPlane3FlipPendingWaitEnable_bits 1 #define GFX9_MI_WAIT_FOR_EVENT_DisplayPlane3FlipPendingWaitEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_DisplayPlane3FlipPendingWaitEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_WAIT_FOR_EVENT_DisplayPlane3FlipPendingWaitEnable_start 15 #define GFX12_MI_WAIT_FOR_EVENT_DisplayPlane3FlipPendingWaitEnable_start 15 #define GFX11_MI_WAIT_FOR_EVENT_DisplayPlane3FlipPendingWaitEnable_start 15 #define GFX9_MI_WAIT_FOR_EVENT_DisplayPlane3FlipPendingWaitEnable_start 15 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_DisplayPlane3FlipPendingWaitEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 15; case 120: return 15; case 110: return 15; case 90: return 15; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_WAIT_FOR_EVENT::Display Plane 4 Flip Pending Wait Enable */ #define GFX125_MI_WAIT_FOR_EVENT_DisplayPlane4FlipPendingWaitEnable_bits 1 #define GFX12_MI_WAIT_FOR_EVENT_DisplayPlane4FlipPendingWaitEnable_bits 1 #define GFX11_MI_WAIT_FOR_EVENT_DisplayPlane4FlipPendingWaitEnable_bits 1 #define GFX9_MI_WAIT_FOR_EVENT_DisplayPlane4FlipPendingWaitEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_DisplayPlane4FlipPendingWaitEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_WAIT_FOR_EVENT_DisplayPlane4FlipPendingWaitEnable_start 2 #define GFX12_MI_WAIT_FOR_EVENT_DisplayPlane4FlipPendingWaitEnable_start 2 #define GFX11_MI_WAIT_FOR_EVENT_DisplayPlane4FlipPendingWaitEnable_start 2 #define GFX9_MI_WAIT_FOR_EVENT_DisplayPlane4FlipPendingWaitEnable_start 2 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_DisplayPlane4FlipPendingWaitEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_WAIT_FOR_EVENT::Display Plane 5 Flip Pending Wait Enable */ #define GFX125_MI_WAIT_FOR_EVENT_DisplayPlane5FlipPendingWaitEnable_bits 1 #define GFX12_MI_WAIT_FOR_EVENT_DisplayPlane5FlipPendingWaitEnable_bits 1 #define GFX11_MI_WAIT_FOR_EVENT_DisplayPlane5FlipPendingWaitEnable_bits 1 #define GFX9_MI_WAIT_FOR_EVENT_DisplayPlane5FlipPendingWaitEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_DisplayPlane5FlipPendingWaitEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_WAIT_FOR_EVENT_DisplayPlane5FlipPendingWaitEnable_start 10 #define GFX12_MI_WAIT_FOR_EVENT_DisplayPlane5FlipPendingWaitEnable_start 10 #define GFX11_MI_WAIT_FOR_EVENT_DisplayPlane5FlipPendingWaitEnable_start 10 #define GFX9_MI_WAIT_FOR_EVENT_DisplayPlane5FlipPendingWaitEnable_start 10 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_DisplayPlane5FlipPendingWaitEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 10; case 120: return 10; case 110: return 10; case 90: return 10; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_WAIT_FOR_EVENT::Display Plane 6 Flip Pending Wait Enable */ #define GFX125_MI_WAIT_FOR_EVENT_DisplayPlane6FlipPendingWaitEnable_bits 1 #define GFX12_MI_WAIT_FOR_EVENT_DisplayPlane6FlipPendingWaitEnable_bits 1 #define GFX11_MI_WAIT_FOR_EVENT_DisplayPlane6FlipPendingWaitEnable_bits 1 #define GFX9_MI_WAIT_FOR_EVENT_DisplayPlane6FlipPendingWaitEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_DisplayPlane6FlipPendingWaitEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_WAIT_FOR_EVENT_DisplayPlane6FlipPendingWaitEnable_start 20 #define GFX12_MI_WAIT_FOR_EVENT_DisplayPlane6FlipPendingWaitEnable_start 20 #define GFX11_MI_WAIT_FOR_EVENT_DisplayPlane6FlipPendingWaitEnable_start 20 #define GFX9_MI_WAIT_FOR_EVENT_DisplayPlane6FlipPendingWaitEnable_start 20 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_DisplayPlane6FlipPendingWaitEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 20; case 120: return 20; case 110: return 20; case 90: return 20; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_WAIT_FOR_EVENT::Display Plane 7 Flip Pending Wait Enable */ #define GFX125_MI_WAIT_FOR_EVENT_DisplayPlane7FlipPendingWaitEnable_bits 1 #define GFX12_MI_WAIT_FOR_EVENT_DisplayPlane7FlipPendingWaitEnable_bits 1 #define GFX11_MI_WAIT_FOR_EVENT_DisplayPlane7FlipPendingWaitEnable_bits 1 #define GFX9_MI_WAIT_FOR_EVENT_DisplayPlane7FlipPendingWaitEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_DisplayPlane7FlipPendingWaitEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_WAIT_FOR_EVENT_DisplayPlane7FlipPendingWaitEnable_start 6 #define GFX12_MI_WAIT_FOR_EVENT_DisplayPlane7FlipPendingWaitEnable_start 6 #define GFX11_MI_WAIT_FOR_EVENT_DisplayPlane7FlipPendingWaitEnable_start 6 #define GFX9_MI_WAIT_FOR_EVENT_DisplayPlane7FlipPendingWaitEnable_start 6 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_DisplayPlane7FlipPendingWaitEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_WAIT_FOR_EVENT::Display Plane 8 Flip Pending Wait Enable */ #define GFX125_MI_WAIT_FOR_EVENT_DisplayPlane8FlipPendingWaitEnable_bits 1 #define GFX12_MI_WAIT_FOR_EVENT_DisplayPlane8FlipPendingWaitEnable_bits 1 #define GFX11_MI_WAIT_FOR_EVENT_DisplayPlane8FlipPendingWaitEnable_bits 1 #define GFX9_MI_WAIT_FOR_EVENT_DisplayPlane8FlipPendingWaitEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_DisplayPlane8FlipPendingWaitEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_WAIT_FOR_EVENT_DisplayPlane8FlipPendingWaitEnable_start 7 #define GFX12_MI_WAIT_FOR_EVENT_DisplayPlane8FlipPendingWaitEnable_start 7 #define GFX11_MI_WAIT_FOR_EVENT_DisplayPlane8FlipPendingWaitEnable_start 7 #define GFX9_MI_WAIT_FOR_EVENT_DisplayPlane8FlipPendingWaitEnable_start 7 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_DisplayPlane8FlipPendingWaitEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 7; case 120: return 7; case 110: return 7; case 90: return 7; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_WAIT_FOR_EVENT::Display Plane 9 Flip Pending Wait Enable */ #define GFX125_MI_WAIT_FOR_EVENT_DisplayPlane9FlipPendingWaitEnable_bits 1 #define GFX12_MI_WAIT_FOR_EVENT_DisplayPlane9FlipPendingWaitEnable_bits 1 #define GFX11_MI_WAIT_FOR_EVENT_DisplayPlane9FlipPendingWaitEnable_bits 1 #define GFX9_MI_WAIT_FOR_EVENT_DisplayPlane9FlipPendingWaitEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_DisplayPlane9FlipPendingWaitEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_WAIT_FOR_EVENT_DisplayPlane9FlipPendingWaitEnable_start 16 #define GFX12_MI_WAIT_FOR_EVENT_DisplayPlane9FlipPendingWaitEnable_start 16 #define GFX11_MI_WAIT_FOR_EVENT_DisplayPlane9FlipPendingWaitEnable_start 16 #define GFX9_MI_WAIT_FOR_EVENT_DisplayPlane9FlipPendingWaitEnable_start 16 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_DisplayPlane9FlipPendingWaitEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_WAIT_FOR_EVENT::Display Plane A Flip Pending Wait Enable */ #define GFX8_MI_WAIT_FOR_EVENT_DisplayPlaneAFlipPendingWaitEnable_bits 1 #define GFX75_MI_WAIT_FOR_EVENT_DisplayPlaneAFlipPendingWaitEnable_bits 1 #define GFX7_MI_WAIT_FOR_EVENT_DisplayPlaneAFlipPendingWaitEnable_bits 1 #define GFX6_MI_WAIT_FOR_EVENT_DisplayPlaneAFlipPendingWaitEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_DisplayPlaneAFlipPendingWaitEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX8_MI_WAIT_FOR_EVENT_DisplayPlaneAFlipPendingWaitEnable_start 1 #define GFX75_MI_WAIT_FOR_EVENT_DisplayPlaneAFlipPendingWaitEnable_start 1 #define GFX7_MI_WAIT_FOR_EVENT_DisplayPlaneAFlipPendingWaitEnable_start 1 #define GFX6_MI_WAIT_FOR_EVENT_DisplayPlaneAFlipPendingWaitEnable_start 1 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_DisplayPlaneAFlipPendingWaitEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_WAIT_FOR_EVENT::Display Plane B Flip Pending Wait Enable */ #define GFX8_MI_WAIT_FOR_EVENT_DisplayPlaneBFlipPendingWaitEnable_bits 1 #define GFX75_MI_WAIT_FOR_EVENT_DisplayPlaneBFlipPendingWaitEnable_bits 1 #define GFX7_MI_WAIT_FOR_EVENT_DisplayPlaneBFlipPendingWaitEnable_bits 1 #define GFX6_MI_WAIT_FOR_EVENT_DisplayPlaneBFlipPendingWaitEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_DisplayPlaneBFlipPendingWaitEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX8_MI_WAIT_FOR_EVENT_DisplayPlaneBFlipPendingWaitEnable_start 9 #define GFX75_MI_WAIT_FOR_EVENT_DisplayPlaneBFlipPendingWaitEnable_start 9 #define GFX7_MI_WAIT_FOR_EVENT_DisplayPlaneBFlipPendingWaitEnable_start 9 #define GFX6_MI_WAIT_FOR_EVENT_DisplayPlaneBFlipPendingWaitEnable_start 9 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_DisplayPlaneBFlipPendingWaitEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 9; case 75: return 9; case 70: return 9; case 60: return 9; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_WAIT_FOR_EVENT::Display Plane C Flip Pending Wait Enable */ #define GFX8_MI_WAIT_FOR_EVENT_DisplayPlaneCFlipPendingWaitEnable_bits 1 #define GFX75_MI_WAIT_FOR_EVENT_DisplayPlaneCFlipPendingWaitEnable_bits 1 #define GFX7_MI_WAIT_FOR_EVENT_DisplayPlaneCFlipPendingWaitEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_DisplayPlaneCFlipPendingWaitEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX8_MI_WAIT_FOR_EVENT_DisplayPlaneCFlipPendingWaitEnable_start 15 #define GFX75_MI_WAIT_FOR_EVENT_DisplayPlaneCFlipPendingWaitEnable_start 15 #define GFX7_MI_WAIT_FOR_EVENT_DisplayPlaneCFlipPendingWaitEnable_start 15 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_DisplayPlaneCFlipPendingWaitEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 15; case 75: return 15; case 70: return 15; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_WAIT_FOR_EVENT::Display Plnae 1 A Scan Line Wait Enable */ #define GFX125_MI_WAIT_FOR_EVENT_DisplayPlnae1AScanLineWaitEnable_bits 1 #define GFX12_MI_WAIT_FOR_EVENT_DisplayPlnae1AScanLineWaitEnable_bits 1 #define GFX11_MI_WAIT_FOR_EVENT_DisplayPlnae1AScanLineWaitEnable_bits 1 #define GFX9_MI_WAIT_FOR_EVENT_DisplayPlnae1AScanLineWaitEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_DisplayPlnae1AScanLineWaitEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_WAIT_FOR_EVENT_DisplayPlnae1AScanLineWaitEnable_start 0 #define GFX12_MI_WAIT_FOR_EVENT_DisplayPlnae1AScanLineWaitEnable_start 0 #define GFX11_MI_WAIT_FOR_EVENT_DisplayPlnae1AScanLineWaitEnable_start 0 #define GFX9_MI_WAIT_FOR_EVENT_DisplayPlnae1AScanLineWaitEnable_start 0 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_DisplayPlnae1AScanLineWaitEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_WAIT_FOR_EVENT::Display Sprite A Flip Pending Wait Enable */ #define GFX8_MI_WAIT_FOR_EVENT_DisplaySpriteAFlipPendingWaitEnable_bits 1 #define GFX75_MI_WAIT_FOR_EVENT_DisplaySpriteAFlipPendingWaitEnable_bits 1 #define GFX7_MI_WAIT_FOR_EVENT_DisplaySpriteAFlipPendingWaitEnable_bits 1 #define GFX6_MI_WAIT_FOR_EVENT_DisplaySpriteAFlipPendingWaitEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_DisplaySpriteAFlipPendingWaitEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX8_MI_WAIT_FOR_EVENT_DisplaySpriteAFlipPendingWaitEnable_start 2 #define GFX75_MI_WAIT_FOR_EVENT_DisplaySpriteAFlipPendingWaitEnable_start 2 #define GFX7_MI_WAIT_FOR_EVENT_DisplaySpriteAFlipPendingWaitEnable_start 2 #define GFX6_MI_WAIT_FOR_EVENT_DisplaySpriteAFlipPendingWaitEnable_start 2 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_DisplaySpriteAFlipPendingWaitEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_WAIT_FOR_EVENT::Display Sprite B Flip Pending Wait Enable */ #define GFX8_MI_WAIT_FOR_EVENT_DisplaySpriteBFlipPendingWaitEnable_bits 1 #define GFX75_MI_WAIT_FOR_EVENT_DisplaySpriteBFlipPendingWaitEnable_bits 1 #define GFX7_MI_WAIT_FOR_EVENT_DisplaySpriteBFlipPendingWaitEnable_bits 1 #define GFX6_MI_WAIT_FOR_EVENT_DisplaySpriteBFlipPendingWaitEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_DisplaySpriteBFlipPendingWaitEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX8_MI_WAIT_FOR_EVENT_DisplaySpriteBFlipPendingWaitEnable_start 10 #define GFX75_MI_WAIT_FOR_EVENT_DisplaySpriteBFlipPendingWaitEnable_start 10 #define GFX7_MI_WAIT_FOR_EVENT_DisplaySpriteBFlipPendingWaitEnable_start 10 #define GFX6_MI_WAIT_FOR_EVENT_DisplaySpriteBFlipPendingWaitEnable_start 10 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_DisplaySpriteBFlipPendingWaitEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 10; case 75: return 10; case 70: return 10; case 60: return 10; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_WAIT_FOR_EVENT::Display Sprite C Flip Pending Wait Enable */ #define GFX8_MI_WAIT_FOR_EVENT_DisplaySpriteCFlipPendingWaitEnable_bits 1 #define GFX75_MI_WAIT_FOR_EVENT_DisplaySpriteCFlipPendingWaitEnable_bits 1 #define GFX7_MI_WAIT_FOR_EVENT_DisplaySpriteCFlipPendingWaitEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_DisplaySpriteCFlipPendingWaitEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX8_MI_WAIT_FOR_EVENT_DisplaySpriteCFlipPendingWaitEnable_start 20 #define GFX75_MI_WAIT_FOR_EVENT_DisplaySpriteCFlipPendingWaitEnable_start 20 #define GFX7_MI_WAIT_FOR_EVENT_DisplaySpriteCFlipPendingWaitEnable_start 20 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_DisplaySpriteCFlipPendingWaitEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 20; case 75: return 20; case 70: return 20; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_WAIT_FOR_EVENT::MI Command Opcode */ #define GFX125_MI_WAIT_FOR_EVENT_MICommandOpcode_bits 6 #define GFX12_MI_WAIT_FOR_EVENT_MICommandOpcode_bits 6 #define GFX11_MI_WAIT_FOR_EVENT_MICommandOpcode_bits 6 #define GFX9_MI_WAIT_FOR_EVENT_MICommandOpcode_bits 6 #define GFX8_MI_WAIT_FOR_EVENT_MICommandOpcode_bits 6 #define GFX75_MI_WAIT_FOR_EVENT_MICommandOpcode_bits 6 #define GFX7_MI_WAIT_FOR_EVENT_MICommandOpcode_bits 6 #define GFX6_MI_WAIT_FOR_EVENT_MICommandOpcode_bits 6 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_MICommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 6; case 60: return 6; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_WAIT_FOR_EVENT_MICommandOpcode_start 23 #define GFX12_MI_WAIT_FOR_EVENT_MICommandOpcode_start 23 #define GFX11_MI_WAIT_FOR_EVENT_MICommandOpcode_start 23 #define GFX9_MI_WAIT_FOR_EVENT_MICommandOpcode_start 23 #define GFX8_MI_WAIT_FOR_EVENT_MICommandOpcode_start 23 #define GFX75_MI_WAIT_FOR_EVENT_MICommandOpcode_start 23 #define GFX7_MI_WAIT_FOR_EVENT_MICommandOpcode_start 23 #define GFX6_MI_WAIT_FOR_EVENT_MICommandOpcode_start 23 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_MICommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 23; case 120: return 23; case 110: return 23; case 90: return 23; case 80: return 23; case 75: return 23; case 70: return 23; case 60: return 23; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_WAIT_FOR_EVENT_2 */ #define GFX125_MI_WAIT_FOR_EVENT_2_length 1 #define GFX12_MI_WAIT_FOR_EVENT_2_length 1 #define GFX11_MI_WAIT_FOR_EVENT_2_length 1 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_2_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_WAIT_FOR_EVENT_2::Command Type */ #define GFX125_MI_WAIT_FOR_EVENT_2_CommandType_bits 3 #define GFX12_MI_WAIT_FOR_EVENT_2_CommandType_bits 3 #define GFX11_MI_WAIT_FOR_EVENT_2_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_2_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_WAIT_FOR_EVENT_2_CommandType_start 29 #define GFX12_MI_WAIT_FOR_EVENT_2_CommandType_start 29 #define GFX11_MI_WAIT_FOR_EVENT_2_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_2_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_WAIT_FOR_EVENT_2::Display Pipe Scan Line Wait Enable */ #define GFX125_MI_WAIT_FOR_EVENT_2_DisplayPipeScanLineWaitEnable_bits 3 #define GFX12_MI_WAIT_FOR_EVENT_2_DisplayPipeScanLineWaitEnable_bits 3 #define GFX11_MI_WAIT_FOR_EVENT_2_DisplayPipeScanLineWaitEnable_bits 3 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_2_DisplayPipeScanLineWaitEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_WAIT_FOR_EVENT_2_DisplayPipeScanLineWaitEnable_start 12 #define GFX12_MI_WAIT_FOR_EVENT_2_DisplayPipeScanLineWaitEnable_start 12 #define GFX11_MI_WAIT_FOR_EVENT_2_DisplayPipeScanLineWaitEnable_start 12 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_2_DisplayPipeScanLineWaitEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 12; case 120: return 12; case 110: return 12; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_WAIT_FOR_EVENT_2::Display Pipe Vertical Blank Wait Enable */ #define GFX125_MI_WAIT_FOR_EVENT_2_DisplayPipeVerticalBlankWaitEnable_bits 3 #define GFX12_MI_WAIT_FOR_EVENT_2_DisplayPipeVerticalBlankWaitEnable_bits 3 #define GFX11_MI_WAIT_FOR_EVENT_2_DisplayPipeVerticalBlankWaitEnable_bits 3 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_2_DisplayPipeVerticalBlankWaitEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_WAIT_FOR_EVENT_2_DisplayPipeVerticalBlankWaitEnable_start 8 #define GFX12_MI_WAIT_FOR_EVENT_2_DisplayPipeVerticalBlankWaitEnable_start 8 #define GFX11_MI_WAIT_FOR_EVENT_2_DisplayPipeVerticalBlankWaitEnable_start 8 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_2_DisplayPipeVerticalBlankWaitEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_WAIT_FOR_EVENT_2::Display Plane Flip Pending Wait Enable */ #define GFX125_MI_WAIT_FOR_EVENT_2_DisplayPlaneFlipPendingWaitEnable_bits 6 #define GFX12_MI_WAIT_FOR_EVENT_2_DisplayPlaneFlipPendingWaitEnable_bits 6 #define GFX11_MI_WAIT_FOR_EVENT_2_DisplayPlaneFlipPendingWaitEnable_bits 6 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_2_DisplayPlaneFlipPendingWaitEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_WAIT_FOR_EVENT_2_DisplayPlaneFlipPendingWaitEnable_start 0 #define GFX12_MI_WAIT_FOR_EVENT_2_DisplayPlaneFlipPendingWaitEnable_start 0 #define GFX11_MI_WAIT_FOR_EVENT_2_DisplayPlaneFlipPendingWaitEnable_start 0 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_2_DisplayPlaneFlipPendingWaitEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* MI_WAIT_FOR_EVENT_2::MI Command Opcode */ #define GFX125_MI_WAIT_FOR_EVENT_2_MICommandOpcode_bits 6 #define GFX12_MI_WAIT_FOR_EVENT_2_MICommandOpcode_bits 6 #define GFX11_MI_WAIT_FOR_EVENT_2_MICommandOpcode_bits 6 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_2_MICommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_MI_WAIT_FOR_EVENT_2_MICommandOpcode_start 23 #define GFX12_MI_WAIT_FOR_EVENT_2_MICommandOpcode_start 23 #define GFX11_MI_WAIT_FOR_EVENT_2_MICommandOpcode_start 23 static inline uint32_t ATTRIBUTE_PURE MI_WAIT_FOR_EVENT_2_MICommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 23; case 120: return 23; case 110: return 23; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* PALETTE_ENTRY */ #define GFX125_PALETTE_ENTRY_length 1 #define GFX12_PALETTE_ENTRY_length 1 #define GFX11_PALETTE_ENTRY_length 1 #define GFX9_PALETTE_ENTRY_length 1 #define GFX8_PALETTE_ENTRY_length 1 #define GFX75_PALETTE_ENTRY_length 1 #define GFX7_PALETTE_ENTRY_length 1 #define GFX6_PALETTE_ENTRY_length 1 static inline uint32_t ATTRIBUTE_PURE PALETTE_ENTRY_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* PALETTE_ENTRY::Alpha */ #define GFX125_PALETTE_ENTRY_Alpha_bits 8 #define GFX12_PALETTE_ENTRY_Alpha_bits 8 #define GFX11_PALETTE_ENTRY_Alpha_bits 8 #define GFX9_PALETTE_ENTRY_Alpha_bits 8 #define GFX8_PALETTE_ENTRY_Alpha_bits 8 #define GFX75_PALETTE_ENTRY_Alpha_bits 8 #define GFX7_PALETTE_ENTRY_Alpha_bits 8 #define GFX6_PALETTE_ENTRY_Alpha_bits 8 static inline uint32_t ATTRIBUTE_PURE PALETTE_ENTRY_Alpha_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_PALETTE_ENTRY_Alpha_start 24 #define GFX12_PALETTE_ENTRY_Alpha_start 24 #define GFX11_PALETTE_ENTRY_Alpha_start 24 #define GFX9_PALETTE_ENTRY_Alpha_start 24 #define GFX8_PALETTE_ENTRY_Alpha_start 24 #define GFX75_PALETTE_ENTRY_Alpha_start 24 #define GFX7_PALETTE_ENTRY_Alpha_start 24 #define GFX6_PALETTE_ENTRY_Alpha_start 24 static inline uint32_t ATTRIBUTE_PURE PALETTE_ENTRY_Alpha_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 24; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* PALETTE_ENTRY::Blue */ #define GFX125_PALETTE_ENTRY_Blue_bits 8 #define GFX12_PALETTE_ENTRY_Blue_bits 8 #define GFX11_PALETTE_ENTRY_Blue_bits 8 #define GFX9_PALETTE_ENTRY_Blue_bits 8 #define GFX8_PALETTE_ENTRY_Blue_bits 8 #define GFX75_PALETTE_ENTRY_Blue_bits 8 #define GFX7_PALETTE_ENTRY_Blue_bits 8 #define GFX6_PALETTE_ENTRY_Blue_bits 8 static inline uint32_t ATTRIBUTE_PURE PALETTE_ENTRY_Blue_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_PALETTE_ENTRY_Blue_start 0 #define GFX12_PALETTE_ENTRY_Blue_start 0 #define GFX11_PALETTE_ENTRY_Blue_start 0 #define GFX9_PALETTE_ENTRY_Blue_start 0 #define GFX8_PALETTE_ENTRY_Blue_start 0 #define GFX75_PALETTE_ENTRY_Blue_start 0 #define GFX7_PALETTE_ENTRY_Blue_start 0 #define GFX6_PALETTE_ENTRY_Blue_start 0 static inline uint32_t ATTRIBUTE_PURE PALETTE_ENTRY_Blue_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* PALETTE_ENTRY::Green */ #define GFX125_PALETTE_ENTRY_Green_bits 8 #define GFX12_PALETTE_ENTRY_Green_bits 8 #define GFX11_PALETTE_ENTRY_Green_bits 8 #define GFX9_PALETTE_ENTRY_Green_bits 8 #define GFX8_PALETTE_ENTRY_Green_bits 8 #define GFX75_PALETTE_ENTRY_Green_bits 8 #define GFX7_PALETTE_ENTRY_Green_bits 8 #define GFX6_PALETTE_ENTRY_Green_bits 8 static inline uint32_t ATTRIBUTE_PURE PALETTE_ENTRY_Green_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_PALETTE_ENTRY_Green_start 8 #define GFX12_PALETTE_ENTRY_Green_start 8 #define GFX11_PALETTE_ENTRY_Green_start 8 #define GFX9_PALETTE_ENTRY_Green_start 8 #define GFX8_PALETTE_ENTRY_Green_start 8 #define GFX75_PALETTE_ENTRY_Green_start 8 #define GFX7_PALETTE_ENTRY_Green_start 8 #define GFX6_PALETTE_ENTRY_Green_start 8 static inline uint32_t ATTRIBUTE_PURE PALETTE_ENTRY_Green_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* PALETTE_ENTRY::Red */ #define GFX125_PALETTE_ENTRY_Red_bits 8 #define GFX12_PALETTE_ENTRY_Red_bits 8 #define GFX11_PALETTE_ENTRY_Red_bits 8 #define GFX9_PALETTE_ENTRY_Red_bits 8 #define GFX8_PALETTE_ENTRY_Red_bits 8 #define GFX75_PALETTE_ENTRY_Red_bits 8 #define GFX7_PALETTE_ENTRY_Red_bits 8 #define GFX6_PALETTE_ENTRY_Red_bits 8 static inline uint32_t ATTRIBUTE_PURE PALETTE_ENTRY_Red_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_PALETTE_ENTRY_Red_start 16 #define GFX12_PALETTE_ENTRY_Red_start 16 #define GFX11_PALETTE_ENTRY_Red_start 16 #define GFX9_PALETTE_ENTRY_Red_start 16 #define GFX8_PALETTE_ENTRY_Red_start 16 #define GFX75_PALETTE_ENTRY_Red_start 16 #define GFX7_PALETTE_ENTRY_Red_start 16 #define GFX6_PALETTE_ENTRY_Red_start 16 static inline uint32_t ATTRIBUTE_PURE PALETTE_ENTRY_Red_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 16; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* PERFCNT1 */ #define GFX11_PERFCNT1_length 2 #define GFX9_PERFCNT1_length 2 #define GFX8_PERFCNT1_length 2 #define GFX75_PERFCNT1_length 2 static inline uint32_t ATTRIBUTE_PURE PERFCNT1_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* PERFCNT1::Counter Clear */ #define GFX11_PERFCNT1_CounterClear_bits 1 #define GFX9_PERFCNT1_CounterClear_bits 1 #define GFX8_PERFCNT1_CounterClear_bits 1 #define GFX75_PERFCNT1_CounterClear_bits 1 static inline uint32_t ATTRIBUTE_PURE PERFCNT1_CounterClear_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX11_PERFCNT1_CounterClear_start 60 #define GFX9_PERFCNT1_CounterClear_start 60 #define GFX8_PERFCNT1_CounterClear_start 60 #define GFX75_PERFCNT1_CounterClear_start 60 static inline uint32_t ATTRIBUTE_PURE PERFCNT1_CounterClear_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 60; case 90: return 60; case 80: return 60; case 75: return 60; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* PERFCNT1::Counter Enable */ #define GFX11_PERFCNT1_CounterEnable_bits 1 #define GFX9_PERFCNT1_CounterEnable_bits 1 #define GFX8_PERFCNT1_CounterEnable_bits 1 #define GFX75_PERFCNT1_CounterEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE PERFCNT1_CounterEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX11_PERFCNT1_CounterEnable_start 63 #define GFX9_PERFCNT1_CounterEnable_start 63 #define GFX8_PERFCNT1_CounterEnable_start 63 #define GFX75_PERFCNT1_CounterEnable_start 63 static inline uint32_t ATTRIBUTE_PURE PERFCNT1_CounterEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 63; case 90: return 63; case 80: return 63; case 75: return 63; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* PERFCNT1::Edge Detect */ #define GFX11_PERFCNT1_EdgeDetect_bits 1 #define GFX9_PERFCNT1_EdgeDetect_bits 1 #define GFX8_PERFCNT1_EdgeDetect_bits 1 #define GFX75_PERFCNT1_EdgeDetect_bits 1 static inline uint32_t ATTRIBUTE_PURE PERFCNT1_EdgeDetect_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX11_PERFCNT1_EdgeDetect_start 61 #define GFX9_PERFCNT1_EdgeDetect_start 61 #define GFX8_PERFCNT1_EdgeDetect_start 61 #define GFX75_PERFCNT1_EdgeDetect_start 61 static inline uint32_t ATTRIBUTE_PURE PERFCNT1_EdgeDetect_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 61; case 90: return 61; case 80: return 61; case 75: return 61; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* PERFCNT1::Event Selection */ #define GFX11_PERFCNT1_EventSelection_bits 8 #define GFX9_PERFCNT1_EventSelection_bits 8 #define GFX8_PERFCNT1_EventSelection_bits 8 #define GFX75_PERFCNT1_EventSelection_bits 8 static inline uint32_t ATTRIBUTE_PURE PERFCNT1_EventSelection_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX11_PERFCNT1_EventSelection_start 52 #define GFX9_PERFCNT1_EventSelection_start 52 #define GFX8_PERFCNT1_EventSelection_start 52 #define GFX75_PERFCNT1_EventSelection_start 52 static inline uint32_t ATTRIBUTE_PURE PERFCNT1_EventSelection_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 52; case 90: return 52; case 80: return 52; case 75: return 52; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* PERFCNT1::Overflow Enable */ #define GFX11_PERFCNT1_OverflowEnable_bits 1 #define GFX9_PERFCNT1_OverflowEnable_bits 1 #define GFX8_PERFCNT1_OverflowEnable_bits 1 #define GFX75_PERFCNT1_OverflowEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE PERFCNT1_OverflowEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX11_PERFCNT1_OverflowEnable_start 62 #define GFX9_PERFCNT1_OverflowEnable_start 62 #define GFX8_PERFCNT1_OverflowEnable_start 62 #define GFX75_PERFCNT1_OverflowEnable_start 62 static inline uint32_t ATTRIBUTE_PURE PERFCNT1_OverflowEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 62; case 90: return 62; case 80: return 62; case 75: return 62; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* PERFCNT1::Value */ #define GFX11_PERFCNT1_Value_bits 44 #define GFX9_PERFCNT1_Value_bits 44 #define GFX8_PERFCNT1_Value_bits 44 #define GFX75_PERFCNT1_Value_bits 44 static inline uint32_t ATTRIBUTE_PURE PERFCNT1_Value_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 44; case 90: return 44; case 80: return 44; case 75: return 44; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX11_PERFCNT1_Value_start 0 #define GFX9_PERFCNT1_Value_start 0 #define GFX8_PERFCNT1_Value_start 0 #define GFX75_PERFCNT1_Value_start 0 static inline uint32_t ATTRIBUTE_PURE PERFCNT1_Value_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* PERFCNT2 */ #define GFX11_PERFCNT2_length 2 #define GFX9_PERFCNT2_length 2 #define GFX8_PERFCNT2_length 2 #define GFX75_PERFCNT2_length 2 static inline uint32_t ATTRIBUTE_PURE PERFCNT2_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* PERFCNT2::Counter Clear */ #define GFX11_PERFCNT2_CounterClear_bits 1 #define GFX9_PERFCNT2_CounterClear_bits 1 #define GFX8_PERFCNT2_CounterClear_bits 1 #define GFX75_PERFCNT2_CounterClear_bits 1 static inline uint32_t ATTRIBUTE_PURE PERFCNT2_CounterClear_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX11_PERFCNT2_CounterClear_start 60 #define GFX9_PERFCNT2_CounterClear_start 60 #define GFX8_PERFCNT2_CounterClear_start 60 #define GFX75_PERFCNT2_CounterClear_start 60 static inline uint32_t ATTRIBUTE_PURE PERFCNT2_CounterClear_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 60; case 90: return 60; case 80: return 60; case 75: return 60; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* PERFCNT2::Counter Enable */ #define GFX11_PERFCNT2_CounterEnable_bits 1 #define GFX9_PERFCNT2_CounterEnable_bits 1 #define GFX8_PERFCNT2_CounterEnable_bits 1 #define GFX75_PERFCNT2_CounterEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE PERFCNT2_CounterEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX11_PERFCNT2_CounterEnable_start 63 #define GFX9_PERFCNT2_CounterEnable_start 63 #define GFX8_PERFCNT2_CounterEnable_start 63 #define GFX75_PERFCNT2_CounterEnable_start 63 static inline uint32_t ATTRIBUTE_PURE PERFCNT2_CounterEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 63; case 90: return 63; case 80: return 63; case 75: return 63; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* PERFCNT2::Edge Detect */ #define GFX11_PERFCNT2_EdgeDetect_bits 1 #define GFX9_PERFCNT2_EdgeDetect_bits 1 #define GFX8_PERFCNT2_EdgeDetect_bits 1 #define GFX75_PERFCNT2_EdgeDetect_bits 1 static inline uint32_t ATTRIBUTE_PURE PERFCNT2_EdgeDetect_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX11_PERFCNT2_EdgeDetect_start 61 #define GFX9_PERFCNT2_EdgeDetect_start 61 #define GFX8_PERFCNT2_EdgeDetect_start 61 #define GFX75_PERFCNT2_EdgeDetect_start 61 static inline uint32_t ATTRIBUTE_PURE PERFCNT2_EdgeDetect_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 61; case 90: return 61; case 80: return 61; case 75: return 61; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* PERFCNT2::Event Selection */ #define GFX11_PERFCNT2_EventSelection_bits 8 #define GFX9_PERFCNT2_EventSelection_bits 8 #define GFX8_PERFCNT2_EventSelection_bits 8 #define GFX75_PERFCNT2_EventSelection_bits 8 static inline uint32_t ATTRIBUTE_PURE PERFCNT2_EventSelection_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX11_PERFCNT2_EventSelection_start 52 #define GFX9_PERFCNT2_EventSelection_start 52 #define GFX8_PERFCNT2_EventSelection_start 52 #define GFX75_PERFCNT2_EventSelection_start 52 static inline uint32_t ATTRIBUTE_PURE PERFCNT2_EventSelection_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 52; case 90: return 52; case 80: return 52; case 75: return 52; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* PERFCNT2::Overflow Enable */ #define GFX11_PERFCNT2_OverflowEnable_bits 1 #define GFX9_PERFCNT2_OverflowEnable_bits 1 #define GFX8_PERFCNT2_OverflowEnable_bits 1 #define GFX75_PERFCNT2_OverflowEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE PERFCNT2_OverflowEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX11_PERFCNT2_OverflowEnable_start 62 #define GFX9_PERFCNT2_OverflowEnable_start 62 #define GFX8_PERFCNT2_OverflowEnable_start 62 #define GFX75_PERFCNT2_OverflowEnable_start 62 static inline uint32_t ATTRIBUTE_PURE PERFCNT2_OverflowEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 62; case 90: return 62; case 80: return 62; case 75: return 62; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* PERFCNT2::Value */ #define GFX11_PERFCNT2_Value_bits 44 #define GFX9_PERFCNT2_Value_bits 44 #define GFX8_PERFCNT2_Value_bits 44 #define GFX75_PERFCNT2_Value_bits 44 static inline uint32_t ATTRIBUTE_PURE PERFCNT2_Value_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 44; case 90: return 44; case 80: return 44; case 75: return 44; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX11_PERFCNT2_Value_start 0 #define GFX9_PERFCNT2_Value_start 0 #define GFX8_PERFCNT2_Value_start 0 #define GFX75_PERFCNT2_Value_start 0 static inline uint32_t ATTRIBUTE_PURE PERFCNT2_Value_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* PIPELINE_SELECT */ #define GFX125_PIPELINE_SELECT_length 1 #define GFX12_PIPELINE_SELECT_length 1 #define GFX11_PIPELINE_SELECT_length 1 #define GFX9_PIPELINE_SELECT_length 1 #define GFX8_PIPELINE_SELECT_length 1 #define GFX75_PIPELINE_SELECT_length 1 #define GFX7_PIPELINE_SELECT_length 1 #define GFX6_PIPELINE_SELECT_length 1 #define GFX5_PIPELINE_SELECT_length 1 #define GFX45_PIPELINE_SELECT_length 1 #define GFX4_PIPELINE_SELECT_length 1 static inline uint32_t ATTRIBUTE_PURE PIPELINE_SELECT_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } /* PIPELINE_SELECT::3D Command Opcode */ #define GFX125_PIPELINE_SELECT_3DCommandOpcode_bits 3 #define GFX12_PIPELINE_SELECT_3DCommandOpcode_bits 3 #define GFX11_PIPELINE_SELECT_3DCommandOpcode_bits 3 #define GFX9_PIPELINE_SELECT_3DCommandOpcode_bits 3 #define GFX8_PIPELINE_SELECT_3DCommandOpcode_bits 3 #define GFX75_PIPELINE_SELECT_3DCommandOpcode_bits 3 #define GFX7_PIPELINE_SELECT_3DCommandOpcode_bits 3 #define GFX6_PIPELINE_SELECT_3DCommandOpcode_bits 3 #define GFX5_PIPELINE_SELECT_3DCommandOpcode_bits 3 #define GFX45_PIPELINE_SELECT_3DCommandOpcode_bits 3 #define GFX4_PIPELINE_SELECT_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE PIPELINE_SELECT_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX125_PIPELINE_SELECT_3DCommandOpcode_start 24 #define GFX12_PIPELINE_SELECT_3DCommandOpcode_start 24 #define GFX11_PIPELINE_SELECT_3DCommandOpcode_start 24 #define GFX9_PIPELINE_SELECT_3DCommandOpcode_start 24 #define GFX8_PIPELINE_SELECT_3DCommandOpcode_start 24 #define GFX75_PIPELINE_SELECT_3DCommandOpcode_start 24 #define GFX7_PIPELINE_SELECT_3DCommandOpcode_start 24 #define GFX6_PIPELINE_SELECT_3DCommandOpcode_start 24 #define GFX5_PIPELINE_SELECT_3DCommandOpcode_start 24 #define GFX45_PIPELINE_SELECT_3DCommandOpcode_start 24 #define GFX4_PIPELINE_SELECT_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE PIPELINE_SELECT_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 24; case 50: return 24; case 45: return 24; case 40: return 24; default: unreachable("Invalid hardware generation"); } } /* PIPELINE_SELECT::3D Command Sub Opcode */ #define GFX125_PIPELINE_SELECT_3DCommandSubOpcode_bits 8 #define GFX12_PIPELINE_SELECT_3DCommandSubOpcode_bits 8 #define GFX11_PIPELINE_SELECT_3DCommandSubOpcode_bits 8 #define GFX9_PIPELINE_SELECT_3DCommandSubOpcode_bits 8 #define GFX8_PIPELINE_SELECT_3DCommandSubOpcode_bits 8 #define GFX75_PIPELINE_SELECT_3DCommandSubOpcode_bits 8 #define GFX7_PIPELINE_SELECT_3DCommandSubOpcode_bits 8 #define GFX6_PIPELINE_SELECT_3DCommandSubOpcode_bits 8 #define GFX5_PIPELINE_SELECT_3DCommandSubOpcode_bits 8 #define GFX45_PIPELINE_SELECT_3DCommandSubOpcode_bits 8 #define GFX4_PIPELINE_SELECT_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE PIPELINE_SELECT_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 8; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } #define GFX125_PIPELINE_SELECT_3DCommandSubOpcode_start 16 #define GFX12_PIPELINE_SELECT_3DCommandSubOpcode_start 16 #define GFX11_PIPELINE_SELECT_3DCommandSubOpcode_start 16 #define GFX9_PIPELINE_SELECT_3DCommandSubOpcode_start 16 #define GFX8_PIPELINE_SELECT_3DCommandSubOpcode_start 16 #define GFX75_PIPELINE_SELECT_3DCommandSubOpcode_start 16 #define GFX7_PIPELINE_SELECT_3DCommandSubOpcode_start 16 #define GFX6_PIPELINE_SELECT_3DCommandSubOpcode_start 16 #define GFX5_PIPELINE_SELECT_3DCommandSubOpcode_start 16 #define GFX45_PIPELINE_SELECT_3DCommandSubOpcode_start 16 #define GFX4_PIPELINE_SELECT_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE PIPELINE_SELECT_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 16; case 50: return 16; case 45: return 16; case 40: return 16; default: unreachable("Invalid hardware generation"); } } /* PIPELINE_SELECT::Command SubType */ #define GFX125_PIPELINE_SELECT_CommandSubType_bits 2 #define GFX12_PIPELINE_SELECT_CommandSubType_bits 2 #define GFX11_PIPELINE_SELECT_CommandSubType_bits 2 #define GFX9_PIPELINE_SELECT_CommandSubType_bits 2 #define GFX8_PIPELINE_SELECT_CommandSubType_bits 2 #define GFX75_PIPELINE_SELECT_CommandSubType_bits 2 #define GFX7_PIPELINE_SELECT_CommandSubType_bits 2 #define GFX6_PIPELINE_SELECT_CommandSubType_bits 2 #define GFX5_PIPELINE_SELECT_CommandSubType_bits 2 #define GFX45_PIPELINE_SELECT_CommandSubType_bits 2 #define GFX4_PIPELINE_SELECT_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE PIPELINE_SELECT_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 2; case 45: return 2; case 40: return 2; default: unreachable("Invalid hardware generation"); } } #define GFX125_PIPELINE_SELECT_CommandSubType_start 27 #define GFX12_PIPELINE_SELECT_CommandSubType_start 27 #define GFX11_PIPELINE_SELECT_CommandSubType_start 27 #define GFX9_PIPELINE_SELECT_CommandSubType_start 27 #define GFX8_PIPELINE_SELECT_CommandSubType_start 27 #define GFX75_PIPELINE_SELECT_CommandSubType_start 27 #define GFX7_PIPELINE_SELECT_CommandSubType_start 27 #define GFX6_PIPELINE_SELECT_CommandSubType_start 27 #define GFX5_PIPELINE_SELECT_CommandSubType_start 27 #define GFX45_PIPELINE_SELECT_CommandSubType_start 27 #define GFX4_PIPELINE_SELECT_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE PIPELINE_SELECT_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 27; case 50: return 27; case 45: return 27; case 40: return 27; default: unreachable("Invalid hardware generation"); } } /* PIPELINE_SELECT::Command Type */ #define GFX125_PIPELINE_SELECT_CommandType_bits 3 #define GFX12_PIPELINE_SELECT_CommandType_bits 3 #define GFX11_PIPELINE_SELECT_CommandType_bits 3 #define GFX9_PIPELINE_SELECT_CommandType_bits 3 #define GFX8_PIPELINE_SELECT_CommandType_bits 3 #define GFX75_PIPELINE_SELECT_CommandType_bits 3 #define GFX7_PIPELINE_SELECT_CommandType_bits 3 #define GFX6_PIPELINE_SELECT_CommandType_bits 3 #define GFX5_PIPELINE_SELECT_CommandType_bits 3 #define GFX45_PIPELINE_SELECT_CommandType_bits 3 #define GFX4_PIPELINE_SELECT_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE PIPELINE_SELECT_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX125_PIPELINE_SELECT_CommandType_start 29 #define GFX12_PIPELINE_SELECT_CommandType_start 29 #define GFX11_PIPELINE_SELECT_CommandType_start 29 #define GFX9_PIPELINE_SELECT_CommandType_start 29 #define GFX8_PIPELINE_SELECT_CommandType_start 29 #define GFX75_PIPELINE_SELECT_CommandType_start 29 #define GFX7_PIPELINE_SELECT_CommandType_start 29 #define GFX6_PIPELINE_SELECT_CommandType_start 29 #define GFX5_PIPELINE_SELECT_CommandType_start 29 #define GFX45_PIPELINE_SELECT_CommandType_start 29 #define GFX4_PIPELINE_SELECT_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE PIPELINE_SELECT_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 29; case 50: return 29; case 45: return 29; case 40: return 29; default: unreachable("Invalid hardware generation"); } } /* PIPELINE_SELECT::Force Media Awake */ #define GFX125_PIPELINE_SELECT_ForceMediaAwake_bits 1 #define GFX12_PIPELINE_SELECT_ForceMediaAwake_bits 1 #define GFX11_PIPELINE_SELECT_ForceMediaAwake_bits 1 #define GFX9_PIPELINE_SELECT_ForceMediaAwake_bits 1 static inline uint32_t ATTRIBUTE_PURE PIPELINE_SELECT_ForceMediaAwake_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_PIPELINE_SELECT_ForceMediaAwake_start 5 #define GFX12_PIPELINE_SELECT_ForceMediaAwake_start 5 #define GFX11_PIPELINE_SELECT_ForceMediaAwake_start 5 #define GFX9_PIPELINE_SELECT_ForceMediaAwake_start 5 static inline uint32_t ATTRIBUTE_PURE PIPELINE_SELECT_ForceMediaAwake_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 5; case 110: return 5; case 90: return 5; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* PIPELINE_SELECT::Mask Bits */ #define GFX125_PIPELINE_SELECT_MaskBits_bits 8 #define GFX12_PIPELINE_SELECT_MaskBits_bits 8 #define GFX11_PIPELINE_SELECT_MaskBits_bits 8 #define GFX9_PIPELINE_SELECT_MaskBits_bits 8 static inline uint32_t ATTRIBUTE_PURE PIPELINE_SELECT_MaskBits_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_PIPELINE_SELECT_MaskBits_start 8 #define GFX12_PIPELINE_SELECT_MaskBits_start 8 #define GFX11_PIPELINE_SELECT_MaskBits_start 8 #define GFX9_PIPELINE_SELECT_MaskBits_start 8 static inline uint32_t ATTRIBUTE_PURE PIPELINE_SELECT_MaskBits_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* PIPELINE_SELECT::Media Sampler DOP Clock Gate Enable */ #define GFX125_PIPELINE_SELECT_MediaSamplerDOPClockGateEnable_bits 1 #define GFX12_PIPELINE_SELECT_MediaSamplerDOPClockGateEnable_bits 1 #define GFX11_PIPELINE_SELECT_MediaSamplerDOPClockGateEnable_bits 1 #define GFX9_PIPELINE_SELECT_MediaSamplerDOPClockGateEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE PIPELINE_SELECT_MediaSamplerDOPClockGateEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_PIPELINE_SELECT_MediaSamplerDOPClockGateEnable_start 4 #define GFX12_PIPELINE_SELECT_MediaSamplerDOPClockGateEnable_start 4 #define GFX11_PIPELINE_SELECT_MediaSamplerDOPClockGateEnable_start 4 #define GFX9_PIPELINE_SELECT_MediaSamplerDOPClockGateEnable_start 4 static inline uint32_t ATTRIBUTE_PURE PIPELINE_SELECT_MediaSamplerDOPClockGateEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* PIPELINE_SELECT::Pipeline Selection */ #define GFX125_PIPELINE_SELECT_PipelineSelection_bits 2 #define GFX12_PIPELINE_SELECT_PipelineSelection_bits 2 #define GFX11_PIPELINE_SELECT_PipelineSelection_bits 2 #define GFX9_PIPELINE_SELECT_PipelineSelection_bits 2 #define GFX8_PIPELINE_SELECT_PipelineSelection_bits 2 #define GFX75_PIPELINE_SELECT_PipelineSelection_bits 2 #define GFX7_PIPELINE_SELECT_PipelineSelection_bits 2 #define GFX6_PIPELINE_SELECT_PipelineSelection_bits 2 #define GFX5_PIPELINE_SELECT_PipelineSelection_bits 2 #define GFX45_PIPELINE_SELECT_PipelineSelection_bits 2 #define GFX4_PIPELINE_SELECT_PipelineSelection_bits 1 static inline uint32_t ATTRIBUTE_PURE PIPELINE_SELECT_PipelineSelection_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 2; case 45: return 2; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX125_PIPELINE_SELECT_PipelineSelection_start 0 #define GFX12_PIPELINE_SELECT_PipelineSelection_start 0 #define GFX11_PIPELINE_SELECT_PipelineSelection_start 0 #define GFX9_PIPELINE_SELECT_PipelineSelection_start 0 #define GFX8_PIPELINE_SELECT_PipelineSelection_start 0 #define GFX75_PIPELINE_SELECT_PipelineSelection_start 0 #define GFX7_PIPELINE_SELECT_PipelineSelection_start 0 #define GFX6_PIPELINE_SELECT_PipelineSelection_start 0 #define GFX5_PIPELINE_SELECT_PipelineSelection_start 0 #define GFX45_PIPELINE_SELECT_PipelineSelection_start 0 #define GFX4_PIPELINE_SELECT_PipelineSelection_start 0 static inline uint32_t ATTRIBUTE_PURE PIPELINE_SELECT_PipelineSelection_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* PIPE_CONTROL */ #define GFX125_PIPE_CONTROL_length 6 #define GFX12_PIPE_CONTROL_length 6 #define GFX11_PIPE_CONTROL_length 6 #define GFX9_PIPE_CONTROL_length 6 #define GFX8_PIPE_CONTROL_length 6 #define GFX75_PIPE_CONTROL_length 5 #define GFX7_PIPE_CONTROL_length 5 #define GFX6_PIPE_CONTROL_length 5 #define GFX5_PIPE_CONTROL_length 4 #define GFX45_PIPE_CONTROL_length 4 #define GFX4_PIPE_CONTROL_length 4 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 5; case 70: return 5; case 60: return 5; case 50: return 4; case 45: return 4; case 40: return 4; default: unreachable("Invalid hardware generation"); } } /* PIPE_CONTROL::3D Command Opcode */ #define GFX125_PIPE_CONTROL_3DCommandOpcode_bits 3 #define GFX12_PIPE_CONTROL_3DCommandOpcode_bits 3 #define GFX11_PIPE_CONTROL_3DCommandOpcode_bits 3 #define GFX9_PIPE_CONTROL_3DCommandOpcode_bits 3 #define GFX8_PIPE_CONTROL_3DCommandOpcode_bits 3 #define GFX75_PIPE_CONTROL_3DCommandOpcode_bits 3 #define GFX7_PIPE_CONTROL_3DCommandOpcode_bits 3 #define GFX6_PIPE_CONTROL_3DCommandOpcode_bits 3 #define GFX5_PIPE_CONTROL_3DCommandOpcode_bits 3 #define GFX45_PIPE_CONTROL_3DCommandOpcode_bits 3 #define GFX4_PIPE_CONTROL_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX125_PIPE_CONTROL_3DCommandOpcode_start 24 #define GFX12_PIPE_CONTROL_3DCommandOpcode_start 24 #define GFX11_PIPE_CONTROL_3DCommandOpcode_start 24 #define GFX9_PIPE_CONTROL_3DCommandOpcode_start 24 #define GFX8_PIPE_CONTROL_3DCommandOpcode_start 24 #define GFX75_PIPE_CONTROL_3DCommandOpcode_start 24 #define GFX7_PIPE_CONTROL_3DCommandOpcode_start 24 #define GFX6_PIPE_CONTROL_3DCommandOpcode_start 24 #define GFX5_PIPE_CONTROL_3DCommandOpcode_start 24 #define GFX45_PIPE_CONTROL_3DCommandOpcode_start 24 #define GFX4_PIPE_CONTROL_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 24; case 50: return 24; case 45: return 24; case 40: return 24; default: unreachable("Invalid hardware generation"); } } /* PIPE_CONTROL::3D Command Sub Opcode */ #define GFX125_PIPE_CONTROL_3DCommandSubOpcode_bits 8 #define GFX12_PIPE_CONTROL_3DCommandSubOpcode_bits 8 #define GFX11_PIPE_CONTROL_3DCommandSubOpcode_bits 8 #define GFX9_PIPE_CONTROL_3DCommandSubOpcode_bits 8 #define GFX8_PIPE_CONTROL_3DCommandSubOpcode_bits 8 #define GFX75_PIPE_CONTROL_3DCommandSubOpcode_bits 8 #define GFX7_PIPE_CONTROL_3DCommandSubOpcode_bits 8 #define GFX6_PIPE_CONTROL_3DCommandSubOpcode_bits 8 #define GFX5_PIPE_CONTROL_3DCommandSubOpcode_bits 8 #define GFX45_PIPE_CONTROL_3DCommandSubOpcode_bits 8 #define GFX4_PIPE_CONTROL_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 8; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } #define GFX125_PIPE_CONTROL_3DCommandSubOpcode_start 16 #define GFX12_PIPE_CONTROL_3DCommandSubOpcode_start 16 #define GFX11_PIPE_CONTROL_3DCommandSubOpcode_start 16 #define GFX9_PIPE_CONTROL_3DCommandSubOpcode_start 16 #define GFX8_PIPE_CONTROL_3DCommandSubOpcode_start 16 #define GFX75_PIPE_CONTROL_3DCommandSubOpcode_start 16 #define GFX7_PIPE_CONTROL_3DCommandSubOpcode_start 16 #define GFX6_PIPE_CONTROL_3DCommandSubOpcode_start 16 #define GFX5_PIPE_CONTROL_3DCommandSubOpcode_start 16 #define GFX45_PIPE_CONTROL_3DCommandSubOpcode_start 16 #define GFX4_PIPE_CONTROL_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 16; case 50: return 16; case 45: return 16; case 40: return 16; default: unreachable("Invalid hardware generation"); } } /* PIPE_CONTROL::Address */ #define GFX125_PIPE_CONTROL_Address_bits 46 #define GFX12_PIPE_CONTROL_Address_bits 46 #define GFX11_PIPE_CONTROL_Address_bits 46 #define GFX9_PIPE_CONTROL_Address_bits 46 #define GFX8_PIPE_CONTROL_Address_bits 46 #define GFX75_PIPE_CONTROL_Address_bits 30 #define GFX7_PIPE_CONTROL_Address_bits 30 #define GFX6_PIPE_CONTROL_Address_bits 29 #define GFX5_PIPE_CONTROL_Address_bits 29 #define GFX45_PIPE_CONTROL_Address_bits 29 #define GFX4_PIPE_CONTROL_Address_bits 29 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_Address_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 46; case 120: return 46; case 110: return 46; case 90: return 46; case 80: return 46; case 75: return 30; case 70: return 30; case 60: return 29; case 50: return 29; case 45: return 29; case 40: return 29; default: unreachable("Invalid hardware generation"); } } #define GFX125_PIPE_CONTROL_Address_start 66 #define GFX12_PIPE_CONTROL_Address_start 66 #define GFX11_PIPE_CONTROL_Address_start 66 #define GFX9_PIPE_CONTROL_Address_start 66 #define GFX8_PIPE_CONTROL_Address_start 66 #define GFX75_PIPE_CONTROL_Address_start 66 #define GFX7_PIPE_CONTROL_Address_start 66 #define GFX6_PIPE_CONTROL_Address_start 67 #define GFX5_PIPE_CONTROL_Address_start 35 #define GFX45_PIPE_CONTROL_Address_start 35 #define GFX4_PIPE_CONTROL_Address_start 35 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_Address_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 66; case 120: return 66; case 110: return 66; case 90: return 66; case 80: return 66; case 75: return 66; case 70: return 66; case 60: return 67; case 50: return 35; case 45: return 35; case 40: return 35; default: unreachable("Invalid hardware generation"); } } /* PIPE_CONTROL::Command Cache Invalidate Enable */ #define GFX125_PIPE_CONTROL_CommandCacheInvalidateEnable_bits 1 #define GFX12_PIPE_CONTROL_CommandCacheInvalidateEnable_bits 1 #define GFX11_PIPE_CONTROL_CommandCacheInvalidateEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_CommandCacheInvalidateEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_PIPE_CONTROL_CommandCacheInvalidateEnable_start 61 #define GFX12_PIPE_CONTROL_CommandCacheInvalidateEnable_start 61 #define GFX11_PIPE_CONTROL_CommandCacheInvalidateEnable_start 61 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_CommandCacheInvalidateEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 61; case 120: return 61; case 110: return 61; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* PIPE_CONTROL::Command Streamer Stall Enable */ #define GFX125_PIPE_CONTROL_CommandStreamerStallEnable_bits 1 #define GFX12_PIPE_CONTROL_CommandStreamerStallEnable_bits 1 #define GFX11_PIPE_CONTROL_CommandStreamerStallEnable_bits 1 #define GFX9_PIPE_CONTROL_CommandStreamerStallEnable_bits 1 #define GFX8_PIPE_CONTROL_CommandStreamerStallEnable_bits 1 #define GFX75_PIPE_CONTROL_CommandStreamerStallEnable_bits 1 #define GFX7_PIPE_CONTROL_CommandStreamerStallEnable_bits 1 #define GFX6_PIPE_CONTROL_CommandStreamerStallEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_CommandStreamerStallEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_PIPE_CONTROL_CommandStreamerStallEnable_start 52 #define GFX12_PIPE_CONTROL_CommandStreamerStallEnable_start 52 #define GFX11_PIPE_CONTROL_CommandStreamerStallEnable_start 52 #define GFX9_PIPE_CONTROL_CommandStreamerStallEnable_start 52 #define GFX8_PIPE_CONTROL_CommandStreamerStallEnable_start 52 #define GFX75_PIPE_CONTROL_CommandStreamerStallEnable_start 52 #define GFX7_PIPE_CONTROL_CommandStreamerStallEnable_start 52 #define GFX6_PIPE_CONTROL_CommandStreamerStallEnable_start 52 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_CommandStreamerStallEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 52; case 120: return 52; case 110: return 52; case 90: return 52; case 80: return 52; case 75: return 52; case 70: return 52; case 60: return 52; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* PIPE_CONTROL::Command SubType */ #define GFX125_PIPE_CONTROL_CommandSubType_bits 2 #define GFX12_PIPE_CONTROL_CommandSubType_bits 2 #define GFX11_PIPE_CONTROL_CommandSubType_bits 2 #define GFX9_PIPE_CONTROL_CommandSubType_bits 2 #define GFX8_PIPE_CONTROL_CommandSubType_bits 2 #define GFX75_PIPE_CONTROL_CommandSubType_bits 2 #define GFX7_PIPE_CONTROL_CommandSubType_bits 2 #define GFX6_PIPE_CONTROL_CommandSubType_bits 2 #define GFX5_PIPE_CONTROL_CommandSubType_bits 2 #define GFX45_PIPE_CONTROL_CommandSubType_bits 2 #define GFX4_PIPE_CONTROL_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 2; case 45: return 2; case 40: return 2; default: unreachable("Invalid hardware generation"); } } #define GFX125_PIPE_CONTROL_CommandSubType_start 27 #define GFX12_PIPE_CONTROL_CommandSubType_start 27 #define GFX11_PIPE_CONTROL_CommandSubType_start 27 #define GFX9_PIPE_CONTROL_CommandSubType_start 27 #define GFX8_PIPE_CONTROL_CommandSubType_start 27 #define GFX75_PIPE_CONTROL_CommandSubType_start 27 #define GFX7_PIPE_CONTROL_CommandSubType_start 27 #define GFX6_PIPE_CONTROL_CommandSubType_start 27 #define GFX5_PIPE_CONTROL_CommandSubType_start 27 #define GFX45_PIPE_CONTROL_CommandSubType_start 27 #define GFX4_PIPE_CONTROL_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 27; case 50: return 27; case 45: return 27; case 40: return 27; default: unreachable("Invalid hardware generation"); } } /* PIPE_CONTROL::Command Type */ #define GFX125_PIPE_CONTROL_CommandType_bits 3 #define GFX12_PIPE_CONTROL_CommandType_bits 3 #define GFX11_PIPE_CONTROL_CommandType_bits 3 #define GFX9_PIPE_CONTROL_CommandType_bits 3 #define GFX8_PIPE_CONTROL_CommandType_bits 3 #define GFX75_PIPE_CONTROL_CommandType_bits 3 #define GFX7_PIPE_CONTROL_CommandType_bits 3 #define GFX6_PIPE_CONTROL_CommandType_bits 3 #define GFX5_PIPE_CONTROL_CommandType_bits 3 #define GFX45_PIPE_CONTROL_CommandType_bits 3 #define GFX4_PIPE_CONTROL_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX125_PIPE_CONTROL_CommandType_start 29 #define GFX12_PIPE_CONTROL_CommandType_start 29 #define GFX11_PIPE_CONTROL_CommandType_start 29 #define GFX9_PIPE_CONTROL_CommandType_start 29 #define GFX8_PIPE_CONTROL_CommandType_start 29 #define GFX75_PIPE_CONTROL_CommandType_start 29 #define GFX7_PIPE_CONTROL_CommandType_start 29 #define GFX6_PIPE_CONTROL_CommandType_start 29 #define GFX5_PIPE_CONTROL_CommandType_start 29 #define GFX45_PIPE_CONTROL_CommandType_start 29 #define GFX4_PIPE_CONTROL_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 29; case 50: return 29; case 45: return 29; case 40: return 29; default: unreachable("Invalid hardware generation"); } } /* PIPE_CONTROL::Constant Cache Invalidation Enable */ #define GFX125_PIPE_CONTROL_ConstantCacheInvalidationEnable_bits 1 #define GFX12_PIPE_CONTROL_ConstantCacheInvalidationEnable_bits 1 #define GFX11_PIPE_CONTROL_ConstantCacheInvalidationEnable_bits 1 #define GFX9_PIPE_CONTROL_ConstantCacheInvalidationEnable_bits 1 #define GFX8_PIPE_CONTROL_ConstantCacheInvalidationEnable_bits 1 #define GFX75_PIPE_CONTROL_ConstantCacheInvalidationEnable_bits 1 #define GFX7_PIPE_CONTROL_ConstantCacheInvalidationEnable_bits 1 #define GFX6_PIPE_CONTROL_ConstantCacheInvalidationEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_ConstantCacheInvalidationEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_PIPE_CONTROL_ConstantCacheInvalidationEnable_start 35 #define GFX12_PIPE_CONTROL_ConstantCacheInvalidationEnable_start 35 #define GFX11_PIPE_CONTROL_ConstantCacheInvalidationEnable_start 35 #define GFX9_PIPE_CONTROL_ConstantCacheInvalidationEnable_start 35 #define GFX8_PIPE_CONTROL_ConstantCacheInvalidationEnable_start 35 #define GFX75_PIPE_CONTROL_ConstantCacheInvalidationEnable_start 35 #define GFX7_PIPE_CONTROL_ConstantCacheInvalidationEnable_start 35 #define GFX6_PIPE_CONTROL_ConstantCacheInvalidationEnable_start 35 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_ConstantCacheInvalidationEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 35; case 120: return 35; case 110: return 35; case 90: return 35; case 80: return 35; case 75: return 35; case 70: return 35; case 60: return 35; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* PIPE_CONTROL::DC Flush Enable */ #define GFX125_PIPE_CONTROL_DCFlushEnable_bits 1 #define GFX12_PIPE_CONTROL_DCFlushEnable_bits 1 #define GFX11_PIPE_CONTROL_DCFlushEnable_bits 1 #define GFX9_PIPE_CONTROL_DCFlushEnable_bits 1 #define GFX8_PIPE_CONTROL_DCFlushEnable_bits 1 #define GFX75_PIPE_CONTROL_DCFlushEnable_bits 1 #define GFX7_PIPE_CONTROL_DCFlushEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_DCFlushEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_PIPE_CONTROL_DCFlushEnable_start 37 #define GFX12_PIPE_CONTROL_DCFlushEnable_start 37 #define GFX11_PIPE_CONTROL_DCFlushEnable_start 37 #define GFX9_PIPE_CONTROL_DCFlushEnable_start 37 #define GFX8_PIPE_CONTROL_DCFlushEnable_start 37 #define GFX75_PIPE_CONTROL_DCFlushEnable_start 37 #define GFX7_PIPE_CONTROL_DCFlushEnable_start 37 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_DCFlushEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 37; case 120: return 37; case 110: return 37; case 90: return 37; case 80: return 37; case 75: return 37; case 70: return 37; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* PIPE_CONTROL::DWord Length */ #define GFX125_PIPE_CONTROL_DWordLength_bits 8 #define GFX12_PIPE_CONTROL_DWordLength_bits 8 #define GFX11_PIPE_CONTROL_DWordLength_bits 8 #define GFX9_PIPE_CONTROL_DWordLength_bits 8 #define GFX8_PIPE_CONTROL_DWordLength_bits 8 #define GFX75_PIPE_CONTROL_DWordLength_bits 8 #define GFX7_PIPE_CONTROL_DWordLength_bits 8 #define GFX6_PIPE_CONTROL_DWordLength_bits 8 #define GFX5_PIPE_CONTROL_DWordLength_bits 8 #define GFX45_PIPE_CONTROL_DWordLength_bits 8 #define GFX4_PIPE_CONTROL_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 8; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } #define GFX125_PIPE_CONTROL_DWordLength_start 0 #define GFX12_PIPE_CONTROL_DWordLength_start 0 #define GFX11_PIPE_CONTROL_DWordLength_start 0 #define GFX9_PIPE_CONTROL_DWordLength_start 0 #define GFX8_PIPE_CONTROL_DWordLength_start 0 #define GFX75_PIPE_CONTROL_DWordLength_start 0 #define GFX7_PIPE_CONTROL_DWordLength_start 0 #define GFX6_PIPE_CONTROL_DWordLength_start 0 #define GFX5_PIPE_CONTROL_DWordLength_start 0 #define GFX45_PIPE_CONTROL_DWordLength_start 0 #define GFX4_PIPE_CONTROL_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* PIPE_CONTROL::Depth Cache Flush Enable */ #define GFX125_PIPE_CONTROL_DepthCacheFlushEnable_bits 1 #define GFX12_PIPE_CONTROL_DepthCacheFlushEnable_bits 1 #define GFX11_PIPE_CONTROL_DepthCacheFlushEnable_bits 1 #define GFX9_PIPE_CONTROL_DepthCacheFlushEnable_bits 1 #define GFX8_PIPE_CONTROL_DepthCacheFlushEnable_bits 1 #define GFX75_PIPE_CONTROL_DepthCacheFlushEnable_bits 1 #define GFX7_PIPE_CONTROL_DepthCacheFlushEnable_bits 1 #define GFX6_PIPE_CONTROL_DepthCacheFlushEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_DepthCacheFlushEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_PIPE_CONTROL_DepthCacheFlushEnable_start 32 #define GFX12_PIPE_CONTROL_DepthCacheFlushEnable_start 32 #define GFX11_PIPE_CONTROL_DepthCacheFlushEnable_start 32 #define GFX9_PIPE_CONTROL_DepthCacheFlushEnable_start 32 #define GFX8_PIPE_CONTROL_DepthCacheFlushEnable_start 32 #define GFX75_PIPE_CONTROL_DepthCacheFlushEnable_start 32 #define GFX7_PIPE_CONTROL_DepthCacheFlushEnable_start 32 #define GFX6_PIPE_CONTROL_DepthCacheFlushEnable_start 32 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_DepthCacheFlushEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 32; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* PIPE_CONTROL::Depth Cache Flush Inhibit */ #define GFX5_PIPE_CONTROL_DepthCacheFlushInhibit_bits 1 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_DepthCacheFlushInhibit_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX5_PIPE_CONTROL_DepthCacheFlushInhibit_start 32 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_DepthCacheFlushInhibit_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 32; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* PIPE_CONTROL::Depth Stall Enable */ #define GFX125_PIPE_CONTROL_DepthStallEnable_bits 1 #define GFX12_PIPE_CONTROL_DepthStallEnable_bits 1 #define GFX11_PIPE_CONTROL_DepthStallEnable_bits 1 #define GFX9_PIPE_CONTROL_DepthStallEnable_bits 1 #define GFX8_PIPE_CONTROL_DepthStallEnable_bits 1 #define GFX75_PIPE_CONTROL_DepthStallEnable_bits 1 #define GFX7_PIPE_CONTROL_DepthStallEnable_bits 1 #define GFX6_PIPE_CONTROL_DepthStallEnable_bits 1 #define GFX5_PIPE_CONTROL_DepthStallEnable_bits 1 #define GFX45_PIPE_CONTROL_DepthStallEnable_bits 1 #define GFX4_PIPE_CONTROL_DepthStallEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_DepthStallEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX125_PIPE_CONTROL_DepthStallEnable_start 45 #define GFX12_PIPE_CONTROL_DepthStallEnable_start 45 #define GFX11_PIPE_CONTROL_DepthStallEnable_start 45 #define GFX9_PIPE_CONTROL_DepthStallEnable_start 45 #define GFX8_PIPE_CONTROL_DepthStallEnable_start 45 #define GFX75_PIPE_CONTROL_DepthStallEnable_start 45 #define GFX7_PIPE_CONTROL_DepthStallEnable_start 45 #define GFX6_PIPE_CONTROL_DepthStallEnable_start 45 #define GFX5_PIPE_CONTROL_DepthStallEnable_start 13 #define GFX45_PIPE_CONTROL_DepthStallEnable_start 13 #define GFX4_PIPE_CONTROL_DepthStallEnable_start 13 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_DepthStallEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 45; case 120: return 45; case 110: return 45; case 90: return 45; case 80: return 45; case 75: return 45; case 70: return 45; case 60: return 45; case 50: return 13; case 45: return 13; case 40: return 13; default: unreachable("Invalid hardware generation"); } } /* PIPE_CONTROL::Destination Address Type */ #define GFX125_PIPE_CONTROL_DestinationAddressType_bits 1 #define GFX12_PIPE_CONTROL_DestinationAddressType_bits 1 #define GFX11_PIPE_CONTROL_DestinationAddressType_bits 1 #define GFX9_PIPE_CONTROL_DestinationAddressType_bits 1 #define GFX8_PIPE_CONTROL_DestinationAddressType_bits 1 #define GFX75_PIPE_CONTROL_DestinationAddressType_bits 1 #define GFX7_PIPE_CONTROL_DestinationAddressType_bits 1 #define GFX6_PIPE_CONTROL_DestinationAddressType_bits 1 #define GFX5_PIPE_CONTROL_DestinationAddressType_bits 1 #define GFX45_PIPE_CONTROL_DestinationAddressType_bits 1 #define GFX4_PIPE_CONTROL_DestinationAddressType_bits 1 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_DestinationAddressType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX125_PIPE_CONTROL_DestinationAddressType_start 56 #define GFX12_PIPE_CONTROL_DestinationAddressType_start 56 #define GFX11_PIPE_CONTROL_DestinationAddressType_start 56 #define GFX9_PIPE_CONTROL_DestinationAddressType_start 56 #define GFX8_PIPE_CONTROL_DestinationAddressType_start 56 #define GFX75_PIPE_CONTROL_DestinationAddressType_start 56 #define GFX7_PIPE_CONTROL_DestinationAddressType_start 56 #define GFX6_PIPE_CONTROL_DestinationAddressType_start 66 #define GFX5_PIPE_CONTROL_DestinationAddressType_start 34 #define GFX45_PIPE_CONTROL_DestinationAddressType_start 34 #define GFX4_PIPE_CONTROL_DestinationAddressType_start 34 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_DestinationAddressType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 56; case 120: return 56; case 110: return 56; case 90: return 56; case 80: return 56; case 75: return 56; case 70: return 56; case 60: return 66; case 50: return 34; case 45: return 34; case 40: return 34; default: unreachable("Invalid hardware generation"); } } /* PIPE_CONTROL::Flush LLC */ #define GFX125_PIPE_CONTROL_FlushLLC_bits 1 #define GFX12_PIPE_CONTROL_FlushLLC_bits 1 #define GFX11_PIPE_CONTROL_FlushLLC_bits 1 #define GFX9_PIPE_CONTROL_FlushLLC_bits 1 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_FlushLLC_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_PIPE_CONTROL_FlushLLC_start 58 #define GFX12_PIPE_CONTROL_FlushLLC_start 58 #define GFX11_PIPE_CONTROL_FlushLLC_start 58 #define GFX9_PIPE_CONTROL_FlushLLC_start 58 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_FlushLLC_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 58; case 120: return 58; case 110: return 58; case 90: return 58; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* PIPE_CONTROL::Generic Media State Clear */ #define GFX125_PIPE_CONTROL_GenericMediaStateClear_bits 1 #define GFX12_PIPE_CONTROL_GenericMediaStateClear_bits 1 #define GFX11_PIPE_CONTROL_GenericMediaStateClear_bits 1 #define GFX9_PIPE_CONTROL_GenericMediaStateClear_bits 1 #define GFX8_PIPE_CONTROL_GenericMediaStateClear_bits 1 #define GFX75_PIPE_CONTROL_GenericMediaStateClear_bits 1 #define GFX7_PIPE_CONTROL_GenericMediaStateClear_bits 1 #define GFX6_PIPE_CONTROL_GenericMediaStateClear_bits 1 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_GenericMediaStateClear_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_PIPE_CONTROL_GenericMediaStateClear_start 48 #define GFX12_PIPE_CONTROL_GenericMediaStateClear_start 48 #define GFX11_PIPE_CONTROL_GenericMediaStateClear_start 48 #define GFX9_PIPE_CONTROL_GenericMediaStateClear_start 48 #define GFX8_PIPE_CONTROL_GenericMediaStateClear_start 48 #define GFX75_PIPE_CONTROL_GenericMediaStateClear_start 48 #define GFX7_PIPE_CONTROL_GenericMediaStateClear_start 48 #define GFX6_PIPE_CONTROL_GenericMediaStateClear_start 48 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_GenericMediaStateClear_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 48; case 120: return 48; case 110: return 48; case 90: return 48; case 80: return 48; case 75: return 48; case 70: return 48; case 60: return 48; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* PIPE_CONTROL::Global Snapshot Count Reset */ #define GFX125_PIPE_CONTROL_GlobalSnapshotCountReset_bits 1 #define GFX12_PIPE_CONTROL_GlobalSnapshotCountReset_bits 1 #define GFX11_PIPE_CONTROL_GlobalSnapshotCountReset_bits 1 #define GFX9_PIPE_CONTROL_GlobalSnapshotCountReset_bits 1 #define GFX8_PIPE_CONTROL_GlobalSnapshotCountReset_bits 1 #define GFX75_PIPE_CONTROL_GlobalSnapshotCountReset_bits 1 #define GFX7_PIPE_CONTROL_GlobalSnapshotCountReset_bits 1 #define GFX6_PIPE_CONTROL_GlobalSnapshotCountReset_bits 1 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_GlobalSnapshotCountReset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_PIPE_CONTROL_GlobalSnapshotCountReset_start 51 #define GFX12_PIPE_CONTROL_GlobalSnapshotCountReset_start 51 #define GFX11_PIPE_CONTROL_GlobalSnapshotCountReset_start 51 #define GFX9_PIPE_CONTROL_GlobalSnapshotCountReset_start 51 #define GFX8_PIPE_CONTROL_GlobalSnapshotCountReset_start 51 #define GFX75_PIPE_CONTROL_GlobalSnapshotCountReset_start 51 #define GFX7_PIPE_CONTROL_GlobalSnapshotCountReset_start 51 #define GFX6_PIPE_CONTROL_GlobalSnapshotCountReset_start 51 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_GlobalSnapshotCountReset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 51; case 120: return 51; case 110: return 51; case 90: return 51; case 80: return 51; case 75: return 51; case 70: return 51; case 60: return 51; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* PIPE_CONTROL::HDC Pipeline Flush Enable */ #define GFX125_PIPE_CONTROL_HDCPipelineFlushEnable_bits 1 #define GFX12_PIPE_CONTROL_HDCPipelineFlushEnable_bits 1 #define GFX11_PIPE_CONTROL_HDCPipelineFlushEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_HDCPipelineFlushEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_PIPE_CONTROL_HDCPipelineFlushEnable_start 9 #define GFX12_PIPE_CONTROL_HDCPipelineFlushEnable_start 9 #define GFX11_PIPE_CONTROL_HDCPipelineFlushEnable_start 9 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_HDCPipelineFlushEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 9; case 120: return 9; case 110: return 9; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* PIPE_CONTROL::Immediate Data */ #define GFX125_PIPE_CONTROL_ImmediateData_bits 64 #define GFX12_PIPE_CONTROL_ImmediateData_bits 64 #define GFX11_PIPE_CONTROL_ImmediateData_bits 64 #define GFX9_PIPE_CONTROL_ImmediateData_bits 64 #define GFX8_PIPE_CONTROL_ImmediateData_bits 64 #define GFX75_PIPE_CONTROL_ImmediateData_bits 64 #define GFX7_PIPE_CONTROL_ImmediateData_bits 64 #define GFX6_PIPE_CONTROL_ImmediateData_bits 64 #define GFX5_PIPE_CONTROL_ImmediateData_bits 64 #define GFX45_PIPE_CONTROL_ImmediateData_bits 64 #define GFX4_PIPE_CONTROL_ImmediateData_bits 64 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_ImmediateData_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 64; case 80: return 64; case 75: return 64; case 70: return 64; case 60: return 64; case 50: return 64; case 45: return 64; case 40: return 64; default: unreachable("Invalid hardware generation"); } } #define GFX125_PIPE_CONTROL_ImmediateData_start 128 #define GFX12_PIPE_CONTROL_ImmediateData_start 128 #define GFX11_PIPE_CONTROL_ImmediateData_start 128 #define GFX9_PIPE_CONTROL_ImmediateData_start 128 #define GFX8_PIPE_CONTROL_ImmediateData_start 128 #define GFX75_PIPE_CONTROL_ImmediateData_start 96 #define GFX7_PIPE_CONTROL_ImmediateData_start 96 #define GFX6_PIPE_CONTROL_ImmediateData_start 96 #define GFX5_PIPE_CONTROL_ImmediateData_start 64 #define GFX45_PIPE_CONTROL_ImmediateData_start 64 #define GFX4_PIPE_CONTROL_ImmediateData_start 64 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_ImmediateData_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 128; case 120: return 128; case 110: return 128; case 90: return 128; case 80: return 128; case 75: return 96; case 70: return 96; case 60: return 96; case 50: return 64; case 45: return 64; case 40: return 64; default: unreachable("Invalid hardware generation"); } } /* PIPE_CONTROL::Indirect State Pointers Disable */ #define GFX125_PIPE_CONTROL_IndirectStatePointersDisable_bits 1 #define GFX12_PIPE_CONTROL_IndirectStatePointersDisable_bits 1 #define GFX11_PIPE_CONTROL_IndirectStatePointersDisable_bits 1 #define GFX9_PIPE_CONTROL_IndirectStatePointersDisable_bits 1 #define GFX8_PIPE_CONTROL_IndirectStatePointersDisable_bits 1 #define GFX75_PIPE_CONTROL_IndirectStatePointersDisable_bits 1 #define GFX7_PIPE_CONTROL_IndirectStatePointersDisable_bits 1 #define GFX6_PIPE_CONTROL_IndirectStatePointersDisable_bits 1 #define GFX5_PIPE_CONTROL_IndirectStatePointersDisable_bits 1 #define GFX45_PIPE_CONTROL_IndirectStatePointersDisable_bits 1 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_IndirectStatePointersDisable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 1; case 45: return 1; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_PIPE_CONTROL_IndirectStatePointersDisable_start 41 #define GFX12_PIPE_CONTROL_IndirectStatePointersDisable_start 41 #define GFX11_PIPE_CONTROL_IndirectStatePointersDisable_start 41 #define GFX9_PIPE_CONTROL_IndirectStatePointersDisable_start 41 #define GFX8_PIPE_CONTROL_IndirectStatePointersDisable_start 41 #define GFX75_PIPE_CONTROL_IndirectStatePointersDisable_start 41 #define GFX7_PIPE_CONTROL_IndirectStatePointersDisable_start 41 #define GFX6_PIPE_CONTROL_IndirectStatePointersDisable_start 41 #define GFX5_PIPE_CONTROL_IndirectStatePointersDisable_start 9 #define GFX45_PIPE_CONTROL_IndirectStatePointersDisable_start 9 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_IndirectStatePointersDisable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 41; case 120: return 41; case 110: return 41; case 90: return 41; case 80: return 41; case 75: return 41; case 70: return 41; case 60: return 41; case 50: return 9; case 45: return 9; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* PIPE_CONTROL::Instruction Cache Invalidate Enable */ #define GFX125_PIPE_CONTROL_InstructionCacheInvalidateEnable_bits 1 #define GFX12_PIPE_CONTROL_InstructionCacheInvalidateEnable_bits 1 #define GFX11_PIPE_CONTROL_InstructionCacheInvalidateEnable_bits 1 #define GFX9_PIPE_CONTROL_InstructionCacheInvalidateEnable_bits 1 #define GFX8_PIPE_CONTROL_InstructionCacheInvalidateEnable_bits 1 #define GFX75_PIPE_CONTROL_InstructionCacheInvalidateEnable_bits 1 #define GFX7_PIPE_CONTROL_InstructionCacheInvalidateEnable_bits 1 #define GFX6_PIPE_CONTROL_InstructionCacheInvalidateEnable_bits 1 #define GFX5_PIPE_CONTROL_InstructionCacheInvalidateEnable_bits 1 #define GFX45_PIPE_CONTROL_InstructionCacheInvalidateEnable_bits 1 #define GFX4_PIPE_CONTROL_InstructionCacheInvalidateEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_InstructionCacheInvalidateEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX125_PIPE_CONTROL_InstructionCacheInvalidateEnable_start 43 #define GFX12_PIPE_CONTROL_InstructionCacheInvalidateEnable_start 43 #define GFX11_PIPE_CONTROL_InstructionCacheInvalidateEnable_start 43 #define GFX9_PIPE_CONTROL_InstructionCacheInvalidateEnable_start 43 #define GFX8_PIPE_CONTROL_InstructionCacheInvalidateEnable_start 43 #define GFX75_PIPE_CONTROL_InstructionCacheInvalidateEnable_start 43 #define GFX7_PIPE_CONTROL_InstructionCacheInvalidateEnable_start 43 #define GFX6_PIPE_CONTROL_InstructionCacheInvalidateEnable_start 43 #define GFX5_PIPE_CONTROL_InstructionCacheInvalidateEnable_start 11 #define GFX45_PIPE_CONTROL_InstructionCacheInvalidateEnable_start 11 #define GFX4_PIPE_CONTROL_InstructionCacheInvalidateEnable_start 11 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_InstructionCacheInvalidateEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 43; case 120: return 43; case 110: return 43; case 90: return 43; case 80: return 43; case 75: return 43; case 70: return 43; case 60: return 43; case 50: return 11; case 45: return 11; case 40: return 11; default: unreachable("Invalid hardware generation"); } } /* PIPE_CONTROL::L3 Read Only Cache Invalidation Enable */ #define GFX125_PIPE_CONTROL_L3ReadOnlyCacheInvalidationEnable_bits 1 #define GFX12_PIPE_CONTROL_L3ReadOnlyCacheInvalidationEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_L3ReadOnlyCacheInvalidationEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_PIPE_CONTROL_L3ReadOnlyCacheInvalidationEnable_start 10 #define GFX12_PIPE_CONTROL_L3ReadOnlyCacheInvalidationEnable_start 10 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_L3ReadOnlyCacheInvalidationEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 10; case 120: return 10; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* PIPE_CONTROL::LRI Post Sync Operation */ #define GFX125_PIPE_CONTROL_LRIPostSyncOperation_bits 1 #define GFX12_PIPE_CONTROL_LRIPostSyncOperation_bits 1 #define GFX11_PIPE_CONTROL_LRIPostSyncOperation_bits 1 #define GFX9_PIPE_CONTROL_LRIPostSyncOperation_bits 1 #define GFX8_PIPE_CONTROL_LRIPostSyncOperation_bits 1 #define GFX75_PIPE_CONTROL_LRIPostSyncOperation_bits 1 #define GFX7_PIPE_CONTROL_LRIPostSyncOperation_bits 1 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_LRIPostSyncOperation_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_PIPE_CONTROL_LRIPostSyncOperation_start 55 #define GFX12_PIPE_CONTROL_LRIPostSyncOperation_start 55 #define GFX11_PIPE_CONTROL_LRIPostSyncOperation_start 55 #define GFX9_PIPE_CONTROL_LRIPostSyncOperation_start 55 #define GFX8_PIPE_CONTROL_LRIPostSyncOperation_start 55 #define GFX75_PIPE_CONTROL_LRIPostSyncOperation_start 55 #define GFX7_PIPE_CONTROL_LRIPostSyncOperation_start 55 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_LRIPostSyncOperation_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 55; case 120: return 55; case 110: return 55; case 90: return 55; case 80: return 55; case 75: return 55; case 70: return 55; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* PIPE_CONTROL::Notify Enable */ #define GFX125_PIPE_CONTROL_NotifyEnable_bits 1 #define GFX12_PIPE_CONTROL_NotifyEnable_bits 1 #define GFX11_PIPE_CONTROL_NotifyEnable_bits 1 #define GFX9_PIPE_CONTROL_NotifyEnable_bits 1 #define GFX8_PIPE_CONTROL_NotifyEnable_bits 1 #define GFX75_PIPE_CONTROL_NotifyEnable_bits 1 #define GFX7_PIPE_CONTROL_NotifyEnable_bits 1 #define GFX6_PIPE_CONTROL_NotifyEnable_bits 1 #define GFX5_PIPE_CONTROL_NotifyEnable_bits 1 #define GFX45_PIPE_CONTROL_NotifyEnable_bits 1 #define GFX4_PIPE_CONTROL_NotifyEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_NotifyEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX125_PIPE_CONTROL_NotifyEnable_start 40 #define GFX12_PIPE_CONTROL_NotifyEnable_start 40 #define GFX11_PIPE_CONTROL_NotifyEnable_start 40 #define GFX9_PIPE_CONTROL_NotifyEnable_start 40 #define GFX8_PIPE_CONTROL_NotifyEnable_start 40 #define GFX75_PIPE_CONTROL_NotifyEnable_start 40 #define GFX7_PIPE_CONTROL_NotifyEnable_start 40 #define GFX6_PIPE_CONTROL_NotifyEnable_start 40 #define GFX5_PIPE_CONTROL_NotifyEnable_start 8 #define GFX45_PIPE_CONTROL_NotifyEnable_start 8 #define GFX4_PIPE_CONTROL_NotifyEnable_start 8 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_NotifyEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 40; case 120: return 40; case 110: return 40; case 90: return 40; case 80: return 40; case 75: return 40; case 70: return 40; case 60: return 40; case 50: return 8; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } /* PIPE_CONTROL::PSD Sync Enable */ #define GFX125_PIPE_CONTROL_PSDSyncEnable_bits 1 #define GFX12_PIPE_CONTROL_PSDSyncEnable_bits 1 #define GFX11_PIPE_CONTROL_PSDSyncEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_PSDSyncEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_PIPE_CONTROL_PSDSyncEnable_start 49 #define GFX12_PIPE_CONTROL_PSDSyncEnable_start 49 #define GFX11_PIPE_CONTROL_PSDSyncEnable_start 49 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_PSDSyncEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 49; case 120: return 49; case 110: return 49; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* PIPE_CONTROL::Pipe Control Flush Enable */ #define GFX125_PIPE_CONTROL_PipeControlFlushEnable_bits 1 #define GFX12_PIPE_CONTROL_PipeControlFlushEnable_bits 1 #define GFX11_PIPE_CONTROL_PipeControlFlushEnable_bits 1 #define GFX9_PIPE_CONTROL_PipeControlFlushEnable_bits 1 #define GFX8_PIPE_CONTROL_PipeControlFlushEnable_bits 1 #define GFX75_PIPE_CONTROL_PipeControlFlushEnable_bits 1 #define GFX7_PIPE_CONTROL_PipeControlFlushEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_PipeControlFlushEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_PIPE_CONTROL_PipeControlFlushEnable_start 39 #define GFX12_PIPE_CONTROL_PipeControlFlushEnable_start 39 #define GFX11_PIPE_CONTROL_PipeControlFlushEnable_start 39 #define GFX9_PIPE_CONTROL_PipeControlFlushEnable_start 39 #define GFX8_PIPE_CONTROL_PipeControlFlushEnable_start 39 #define GFX75_PIPE_CONTROL_PipeControlFlushEnable_start 39 #define GFX7_PIPE_CONTROL_PipeControlFlushEnable_start 39 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_PipeControlFlushEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 39; case 120: return 39; case 110: return 39; case 90: return 39; case 80: return 39; case 75: return 39; case 70: return 39; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* PIPE_CONTROL::Post Sync Operation */ #define GFX125_PIPE_CONTROL_PostSyncOperation_bits 2 #define GFX12_PIPE_CONTROL_PostSyncOperation_bits 2 #define GFX11_PIPE_CONTROL_PostSyncOperation_bits 2 #define GFX9_PIPE_CONTROL_PostSyncOperation_bits 2 #define GFX8_PIPE_CONTROL_PostSyncOperation_bits 2 #define GFX75_PIPE_CONTROL_PostSyncOperation_bits 2 #define GFX7_PIPE_CONTROL_PostSyncOperation_bits 2 #define GFX6_PIPE_CONTROL_PostSyncOperation_bits 2 #define GFX5_PIPE_CONTROL_PostSyncOperation_bits 2 #define GFX45_PIPE_CONTROL_PostSyncOperation_bits 2 #define GFX4_PIPE_CONTROL_PostSyncOperation_bits 2 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_PostSyncOperation_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 2; case 45: return 2; case 40: return 2; default: unreachable("Invalid hardware generation"); } } #define GFX125_PIPE_CONTROL_PostSyncOperation_start 46 #define GFX12_PIPE_CONTROL_PostSyncOperation_start 46 #define GFX11_PIPE_CONTROL_PostSyncOperation_start 46 #define GFX9_PIPE_CONTROL_PostSyncOperation_start 46 #define GFX8_PIPE_CONTROL_PostSyncOperation_start 46 #define GFX75_PIPE_CONTROL_PostSyncOperation_start 46 #define GFX7_PIPE_CONTROL_PostSyncOperation_start 46 #define GFX6_PIPE_CONTROL_PostSyncOperation_start 46 #define GFX5_PIPE_CONTROL_PostSyncOperation_start 14 #define GFX45_PIPE_CONTROL_PostSyncOperation_start 14 #define GFX4_PIPE_CONTROL_PostSyncOperation_start 14 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_PostSyncOperation_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 46; case 120: return 46; case 110: return 46; case 90: return 46; case 80: return 46; case 75: return 46; case 70: return 46; case 60: return 46; case 50: return 14; case 45: return 14; case 40: return 14; default: unreachable("Invalid hardware generation"); } } /* PIPE_CONTROL::Protected Memory Disable */ #define GFX125_PIPE_CONTROL_ProtectedMemoryDisable_bits 1 #define GFX12_PIPE_CONTROL_ProtectedMemoryDisable_bits 1 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_ProtectedMemoryDisable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_PIPE_CONTROL_ProtectedMemoryDisable_start 59 #define GFX12_PIPE_CONTROL_ProtectedMemoryDisable_start 59 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_ProtectedMemoryDisable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 59; case 120: return 59; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* PIPE_CONTROL::Protected Memory Enable */ #define GFX125_PIPE_CONTROL_ProtectedMemoryEnable_bits 1 #define GFX12_PIPE_CONTROL_ProtectedMemoryEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_ProtectedMemoryEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_PIPE_CONTROL_ProtectedMemoryEnable_start 54 #define GFX12_PIPE_CONTROL_ProtectedMemoryEnable_start 54 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_ProtectedMemoryEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 54; case 120: return 54; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* PIPE_CONTROL::Render Target Cache Flush Enable */ #define GFX125_PIPE_CONTROL_RenderTargetCacheFlushEnable_bits 1 #define GFX12_PIPE_CONTROL_RenderTargetCacheFlushEnable_bits 1 #define GFX11_PIPE_CONTROL_RenderTargetCacheFlushEnable_bits 1 #define GFX9_PIPE_CONTROL_RenderTargetCacheFlushEnable_bits 1 #define GFX8_PIPE_CONTROL_RenderTargetCacheFlushEnable_bits 1 #define GFX75_PIPE_CONTROL_RenderTargetCacheFlushEnable_bits 1 #define GFX7_PIPE_CONTROL_RenderTargetCacheFlushEnable_bits 1 #define GFX6_PIPE_CONTROL_RenderTargetCacheFlushEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_RenderTargetCacheFlushEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_PIPE_CONTROL_RenderTargetCacheFlushEnable_start 44 #define GFX12_PIPE_CONTROL_RenderTargetCacheFlushEnable_start 44 #define GFX11_PIPE_CONTROL_RenderTargetCacheFlushEnable_start 44 #define GFX9_PIPE_CONTROL_RenderTargetCacheFlushEnable_start 44 #define GFX8_PIPE_CONTROL_RenderTargetCacheFlushEnable_start 44 #define GFX75_PIPE_CONTROL_RenderTargetCacheFlushEnable_start 44 #define GFX7_PIPE_CONTROL_RenderTargetCacheFlushEnable_start 44 #define GFX6_PIPE_CONTROL_RenderTargetCacheFlushEnable_start 44 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_RenderTargetCacheFlushEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 44; case 120: return 44; case 110: return 44; case 90: return 44; case 80: return 44; case 75: return 44; case 70: return 44; case 60: return 44; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* PIPE_CONTROL::Stall At Pixel Scoreboard */ #define GFX125_PIPE_CONTROL_StallAtPixelScoreboard_bits 1 #define GFX12_PIPE_CONTROL_StallAtPixelScoreboard_bits 1 #define GFX11_PIPE_CONTROL_StallAtPixelScoreboard_bits 1 #define GFX9_PIPE_CONTROL_StallAtPixelScoreboard_bits 1 #define GFX8_PIPE_CONTROL_StallAtPixelScoreboard_bits 1 #define GFX75_PIPE_CONTROL_StallAtPixelScoreboard_bits 1 #define GFX7_PIPE_CONTROL_StallAtPixelScoreboard_bits 1 #define GFX6_PIPE_CONTROL_StallAtPixelScoreboard_bits 1 #define GFX5_PIPE_CONTROL_StallAtPixelScoreboard_bits 1 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_StallAtPixelScoreboard_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 1; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_PIPE_CONTROL_StallAtPixelScoreboard_start 33 #define GFX12_PIPE_CONTROL_StallAtPixelScoreboard_start 33 #define GFX11_PIPE_CONTROL_StallAtPixelScoreboard_start 33 #define GFX9_PIPE_CONTROL_StallAtPixelScoreboard_start 33 #define GFX8_PIPE_CONTROL_StallAtPixelScoreboard_start 33 #define GFX75_PIPE_CONTROL_StallAtPixelScoreboard_start 33 #define GFX7_PIPE_CONTROL_StallAtPixelScoreboard_start 33 #define GFX6_PIPE_CONTROL_StallAtPixelScoreboard_start 33 #define GFX5_PIPE_CONTROL_StallAtPixelScoreboard_start 33 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_StallAtPixelScoreboard_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 33; case 120: return 33; case 110: return 33; case 90: return 33; case 80: return 33; case 75: return 33; case 70: return 33; case 60: return 33; case 50: return 33; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* PIPE_CONTROL::State Cache Invalidation Enable */ #define GFX125_PIPE_CONTROL_StateCacheInvalidationEnable_bits 1 #define GFX12_PIPE_CONTROL_StateCacheInvalidationEnable_bits 1 #define GFX11_PIPE_CONTROL_StateCacheInvalidationEnable_bits 1 #define GFX9_PIPE_CONTROL_StateCacheInvalidationEnable_bits 1 #define GFX8_PIPE_CONTROL_StateCacheInvalidationEnable_bits 1 #define GFX75_PIPE_CONTROL_StateCacheInvalidationEnable_bits 1 #define GFX7_PIPE_CONTROL_StateCacheInvalidationEnable_bits 1 #define GFX6_PIPE_CONTROL_StateCacheInvalidationEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_StateCacheInvalidationEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_PIPE_CONTROL_StateCacheInvalidationEnable_start 34 #define GFX12_PIPE_CONTROL_StateCacheInvalidationEnable_start 34 #define GFX11_PIPE_CONTROL_StateCacheInvalidationEnable_start 34 #define GFX9_PIPE_CONTROL_StateCacheInvalidationEnable_start 34 #define GFX8_PIPE_CONTROL_StateCacheInvalidationEnable_start 34 #define GFX75_PIPE_CONTROL_StateCacheInvalidationEnable_start 34 #define GFX7_PIPE_CONTROL_StateCacheInvalidationEnable_start 34 #define GFX6_PIPE_CONTROL_StateCacheInvalidationEnable_start 34 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_StateCacheInvalidationEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 34; case 120: return 34; case 110: return 34; case 90: return 34; case 80: return 34; case 75: return 34; case 70: return 34; case 60: return 34; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* PIPE_CONTROL::Store Data Index */ #define GFX125_PIPE_CONTROL_StoreDataIndex_bits 1 #define GFX12_PIPE_CONTROL_StoreDataIndex_bits 1 #define GFX11_PIPE_CONTROL_StoreDataIndex_bits 1 #define GFX9_PIPE_CONTROL_StoreDataIndex_bits 1 #define GFX8_PIPE_CONTROL_StoreDataIndex_bits 1 #define GFX75_PIPE_CONTROL_StoreDataIndex_bits 1 #define GFX7_PIPE_CONTROL_StoreDataIndex_bits 1 #define GFX6_PIPE_CONTROL_StoreDataIndex_bits 1 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_StoreDataIndex_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_PIPE_CONTROL_StoreDataIndex_start 53 #define GFX12_PIPE_CONTROL_StoreDataIndex_start 53 #define GFX11_PIPE_CONTROL_StoreDataIndex_start 53 #define GFX9_PIPE_CONTROL_StoreDataIndex_start 53 #define GFX8_PIPE_CONTROL_StoreDataIndex_start 53 #define GFX75_PIPE_CONTROL_StoreDataIndex_start 53 #define GFX7_PIPE_CONTROL_StoreDataIndex_start 53 #define GFX6_PIPE_CONTROL_StoreDataIndex_start 53 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_StoreDataIndex_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 53; case 120: return 53; case 110: return 53; case 90: return 53; case 80: return 53; case 75: return 53; case 70: return 53; case 60: return 53; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* PIPE_CONTROL::Synchronize GFDT Surface */ #define GFX6_PIPE_CONTROL_SynchronizeGFDTSurface_bits 1 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_SynchronizeGFDTSurface_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_PIPE_CONTROL_SynchronizeGFDTSurface_start 49 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_SynchronizeGFDTSurface_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 49; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* PIPE_CONTROL::TLB Invalidate */ #define GFX125_PIPE_CONTROL_TLBInvalidate_bits 1 #define GFX12_PIPE_CONTROL_TLBInvalidate_bits 1 #define GFX11_PIPE_CONTROL_TLBInvalidate_bits 1 #define GFX9_PIPE_CONTROL_TLBInvalidate_bits 1 #define GFX8_PIPE_CONTROL_TLBInvalidate_bits 1 #define GFX75_PIPE_CONTROL_TLBInvalidate_bits 1 #define GFX7_PIPE_CONTROL_TLBInvalidate_bits 1 #define GFX6_PIPE_CONTROL_TLBInvalidate_bits 1 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_TLBInvalidate_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_PIPE_CONTROL_TLBInvalidate_start 50 #define GFX12_PIPE_CONTROL_TLBInvalidate_start 50 #define GFX11_PIPE_CONTROL_TLBInvalidate_start 50 #define GFX9_PIPE_CONTROL_TLBInvalidate_start 50 #define GFX8_PIPE_CONTROL_TLBInvalidate_start 50 #define GFX75_PIPE_CONTROL_TLBInvalidate_start 50 #define GFX7_PIPE_CONTROL_TLBInvalidate_start 50 #define GFX6_PIPE_CONTROL_TLBInvalidate_start 50 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_TLBInvalidate_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 50; case 120: return 50; case 110: return 50; case 90: return 50; case 80: return 50; case 75: return 50; case 70: return 50; case 60: return 50; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* PIPE_CONTROL::Texture Cache Flush Enable */ #define GFX5_PIPE_CONTROL_TextureCacheFlushEnable_bits 1 #define GFX45_PIPE_CONTROL_TextureCacheFlushEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_TextureCacheFlushEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX5_PIPE_CONTROL_TextureCacheFlushEnable_start 10 #define GFX45_PIPE_CONTROL_TextureCacheFlushEnable_start 10 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_TextureCacheFlushEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 10; case 45: return 10; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* PIPE_CONTROL::Texture Cache Invalidation Enable */ #define GFX125_PIPE_CONTROL_TextureCacheInvalidationEnable_bits 1 #define GFX12_PIPE_CONTROL_TextureCacheInvalidationEnable_bits 1 #define GFX11_PIPE_CONTROL_TextureCacheInvalidationEnable_bits 1 #define GFX9_PIPE_CONTROL_TextureCacheInvalidationEnable_bits 1 #define GFX8_PIPE_CONTROL_TextureCacheInvalidationEnable_bits 1 #define GFX75_PIPE_CONTROL_TextureCacheInvalidationEnable_bits 1 #define GFX7_PIPE_CONTROL_TextureCacheInvalidationEnable_bits 1 #define GFX6_PIPE_CONTROL_TextureCacheInvalidationEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_TextureCacheInvalidationEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_PIPE_CONTROL_TextureCacheInvalidationEnable_start 42 #define GFX12_PIPE_CONTROL_TextureCacheInvalidationEnable_start 42 #define GFX11_PIPE_CONTROL_TextureCacheInvalidationEnable_start 42 #define GFX9_PIPE_CONTROL_TextureCacheInvalidationEnable_start 42 #define GFX8_PIPE_CONTROL_TextureCacheInvalidationEnable_start 42 #define GFX75_PIPE_CONTROL_TextureCacheInvalidationEnable_start 42 #define GFX7_PIPE_CONTROL_TextureCacheInvalidationEnable_start 42 #define GFX6_PIPE_CONTROL_TextureCacheInvalidationEnable_start 42 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_TextureCacheInvalidationEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 42; case 120: return 42; case 110: return 42; case 90: return 42; case 80: return 42; case 75: return 42; case 70: return 42; case 60: return 42; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* PIPE_CONTROL::Tile Cache Flush Enable */ #define GFX125_PIPE_CONTROL_TileCacheFlushEnable_bits 1 #define GFX12_PIPE_CONTROL_TileCacheFlushEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_TileCacheFlushEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_PIPE_CONTROL_TileCacheFlushEnable_start 60 #define GFX12_PIPE_CONTROL_TileCacheFlushEnable_start 60 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_TileCacheFlushEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 60; case 120: return 60; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* PIPE_CONTROL::VF Cache Invalidation Enable */ #define GFX125_PIPE_CONTROL_VFCacheInvalidationEnable_bits 1 #define GFX12_PIPE_CONTROL_VFCacheInvalidationEnable_bits 1 #define GFX11_PIPE_CONTROL_VFCacheInvalidationEnable_bits 1 #define GFX9_PIPE_CONTROL_VFCacheInvalidationEnable_bits 1 #define GFX8_PIPE_CONTROL_VFCacheInvalidationEnable_bits 1 #define GFX75_PIPE_CONTROL_VFCacheInvalidationEnable_bits 1 #define GFX7_PIPE_CONTROL_VFCacheInvalidationEnable_bits 1 #define GFX6_PIPE_CONTROL_VFCacheInvalidationEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_VFCacheInvalidationEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_PIPE_CONTROL_VFCacheInvalidationEnable_start 36 #define GFX12_PIPE_CONTROL_VFCacheInvalidationEnable_start 36 #define GFX11_PIPE_CONTROL_VFCacheInvalidationEnable_start 36 #define GFX9_PIPE_CONTROL_VFCacheInvalidationEnable_start 36 #define GFX8_PIPE_CONTROL_VFCacheInvalidationEnable_start 36 #define GFX75_PIPE_CONTROL_VFCacheInvalidationEnable_start 36 #define GFX7_PIPE_CONTROL_VFCacheInvalidationEnable_start 36 #define GFX6_PIPE_CONTROL_VFCacheInvalidationEnable_start 36 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_VFCacheInvalidationEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 36; case 120: return 36; case 110: return 36; case 90: return 36; case 80: return 36; case 75: return 36; case 70: return 36; case 60: return 36; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* PIPE_CONTROL::Write Cache Flush */ #define GFX5_PIPE_CONTROL_WriteCacheFlush_bits 1 #define GFX45_PIPE_CONTROL_WriteCacheFlush_bits 1 #define GFX4_PIPE_CONTROL_WriteCacheFlush_bits 1 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_WriteCacheFlush_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_PIPE_CONTROL_WriteCacheFlush_start 12 #define GFX45_PIPE_CONTROL_WriteCacheFlush_start 12 #define GFX4_PIPE_CONTROL_WriteCacheFlush_start 12 static inline uint32_t ATTRIBUTE_PURE PIPE_CONTROL_WriteCacheFlush_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 12; case 45: return 12; case 40: return 12; default: unreachable("Invalid hardware generation"); } } /* POSTSYNC_DATA */ #define GFX125_POSTSYNC_DATA_length 5 static inline uint32_t ATTRIBUTE_PURE POSTSYNC_DATA_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* POSTSYNC_DATA::Destination Address */ #define GFX125_POSTSYNC_DATA_DestinationAddress_bits 64 static inline uint32_t ATTRIBUTE_PURE POSTSYNC_DATA_DestinationAddress_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_POSTSYNC_DATA_DestinationAddress_start 32 static inline uint32_t ATTRIBUTE_PURE POSTSYNC_DATA_DestinationAddress_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* POSTSYNC_DATA::Immediate Data */ #define GFX125_POSTSYNC_DATA_ImmediateData_bits 64 static inline uint32_t ATTRIBUTE_PURE POSTSYNC_DATA_ImmediateData_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_POSTSYNC_DATA_ImmediateData_start 96 static inline uint32_t ATTRIBUTE_PURE POSTSYNC_DATA_ImmediateData_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 96; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* PS_INVOCATION_COUNT */ #define GFX125_PS_INVOCATION_COUNT_length 2 #define GFX12_PS_INVOCATION_COUNT_length 2 #define GFX11_PS_INVOCATION_COUNT_length 2 #define GFX9_PS_INVOCATION_COUNT_length 2 #define GFX8_PS_INVOCATION_COUNT_length 2 #define GFX75_PS_INVOCATION_COUNT_length 2 #define GFX7_PS_INVOCATION_COUNT_length 2 static inline uint32_t ATTRIBUTE_PURE PS_INVOCATION_COUNT_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* PS_INVOCATION_COUNT::PS Invocation Count Report */ #define GFX125_PS_INVOCATION_COUNT_PSInvocationCountReport_bits 64 #define GFX12_PS_INVOCATION_COUNT_PSInvocationCountReport_bits 64 #define GFX11_PS_INVOCATION_COUNT_PSInvocationCountReport_bits 64 #define GFX9_PS_INVOCATION_COUNT_PSInvocationCountReport_bits 64 #define GFX8_PS_INVOCATION_COUNT_PSInvocationCountReport_bits 64 #define GFX75_PS_INVOCATION_COUNT_PSInvocationCountReport_bits 64 #define GFX7_PS_INVOCATION_COUNT_PSInvocationCountReport_bits 64 static inline uint32_t ATTRIBUTE_PURE PS_INVOCATION_COUNT_PSInvocationCountReport_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 64; case 80: return 64; case 75: return 64; case 70: return 64; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_PS_INVOCATION_COUNT_PSInvocationCountReport_start 0 #define GFX12_PS_INVOCATION_COUNT_PSInvocationCountReport_start 0 #define GFX11_PS_INVOCATION_COUNT_PSInvocationCountReport_start 0 #define GFX9_PS_INVOCATION_COUNT_PSInvocationCountReport_start 0 #define GFX8_PS_INVOCATION_COUNT_PSInvocationCountReport_start 0 #define GFX75_PS_INVOCATION_COUNT_PSInvocationCountReport_start 0 #define GFX7_PS_INVOCATION_COUNT_PSInvocationCountReport_start 0 static inline uint32_t ATTRIBUTE_PURE PS_INVOCATION_COUNT_PSInvocationCountReport_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RCS_FAULT_REG */ #define GFX75_RCS_FAULT_REG_length 1 #define GFX7_RCS_FAULT_REG_length 1 #define GFX6_RCS_FAULT_REG_length 1 static inline uint32_t ATTRIBUTE_PURE RCS_FAULT_REG_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RCS_FAULT_REG::Fault Type */ #define GFX75_RCS_FAULT_REG_FaultType_bits 2 #define GFX7_RCS_FAULT_REG_FaultType_bits 2 #define GFX6_RCS_FAULT_REG_FaultType_bits 2 static inline uint32_t ATTRIBUTE_PURE RCS_FAULT_REG_FaultType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_RCS_FAULT_REG_FaultType_start 1 #define GFX7_RCS_FAULT_REG_FaultType_start 1 #define GFX6_RCS_FAULT_REG_FaultType_start 1 static inline uint32_t ATTRIBUTE_PURE RCS_FAULT_REG_FaultType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RCS_FAULT_REG::GTTSEL */ #define GFX75_RCS_FAULT_REG_GTTSEL_bits 1 #define GFX7_RCS_FAULT_REG_GTTSEL_bits 1 #define GFX6_RCS_FAULT_REG_GTTSEL_bits 1 static inline uint32_t ATTRIBUTE_PURE RCS_FAULT_REG_GTTSEL_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_RCS_FAULT_REG_GTTSEL_start 11 #define GFX7_RCS_FAULT_REG_GTTSEL_start 11 #define GFX6_RCS_FAULT_REG_GTTSEL_start 11 static inline uint32_t ATTRIBUTE_PURE RCS_FAULT_REG_GTTSEL_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 11; case 70: return 11; case 60: return 11; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RCS_FAULT_REG::SRCID of Fault */ #define GFX75_RCS_FAULT_REG_SRCIDofFault_bits 8 #define GFX7_RCS_FAULT_REG_SRCIDofFault_bits 8 #define GFX6_RCS_FAULT_REG_SRCIDofFault_bits 8 static inline uint32_t ATTRIBUTE_PURE RCS_FAULT_REG_SRCIDofFault_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_RCS_FAULT_REG_SRCIDofFault_start 3 #define GFX7_RCS_FAULT_REG_SRCIDofFault_start 3 #define GFX6_RCS_FAULT_REG_SRCIDofFault_start 3 static inline uint32_t ATTRIBUTE_PURE RCS_FAULT_REG_SRCIDofFault_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RCS_FAULT_REG::Valid Bit */ #define GFX75_RCS_FAULT_REG_ValidBit_bits 1 #define GFX7_RCS_FAULT_REG_ValidBit_bits 1 #define GFX6_RCS_FAULT_REG_ValidBit_bits 1 static inline uint32_t ATTRIBUTE_PURE RCS_FAULT_REG_ValidBit_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_RCS_FAULT_REG_ValidBit_start 0 #define GFX7_RCS_FAULT_REG_ValidBit_start 0 #define GFX6_RCS_FAULT_REG_ValidBit_start 0 static inline uint32_t ATTRIBUTE_PURE RCS_FAULT_REG_ValidBit_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RCS_FAULT_REG::Virtual Address of Fault */ #define GFX75_RCS_FAULT_REG_VirtualAddressofFault_bits 20 #define GFX7_RCS_FAULT_REG_VirtualAddressofFault_bits 20 #define GFX6_RCS_FAULT_REG_VirtualAddressofFault_bits 20 static inline uint32_t ATTRIBUTE_PURE RCS_FAULT_REG_VirtualAddressofFault_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 20; case 70: return 20; case 60: return 20; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_RCS_FAULT_REG_VirtualAddressofFault_start 12 #define GFX7_RCS_FAULT_REG_VirtualAddressofFault_start 12 #define GFX6_RCS_FAULT_REG_VirtualAddressofFault_start 12 static inline uint32_t ATTRIBUTE_PURE RCS_FAULT_REG_VirtualAddressofFault_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 12; case 70: return 12; case 60: return 12; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RCS_RING_BUFFER_CTL */ #define GFX9_RCS_RING_BUFFER_CTL_length 1 #define GFX8_RCS_RING_BUFFER_CTL_length 1 #define GFX75_RCS_RING_BUFFER_CTL_length 1 #define GFX7_RCS_RING_BUFFER_CTL_length 1 #define GFX6_RCS_RING_BUFFER_CTL_length 1 static inline uint32_t ATTRIBUTE_PURE RCS_RING_BUFFER_CTL_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RCS_RING_BUFFER_CTL::Automatic Report Head Pointer */ #define GFX9_RCS_RING_BUFFER_CTL_AutomaticReportHeadPointer_bits 2 #define GFX8_RCS_RING_BUFFER_CTL_AutomaticReportHeadPointer_bits 2 #define GFX75_RCS_RING_BUFFER_CTL_AutomaticReportHeadPointer_bits 2 #define GFX7_RCS_RING_BUFFER_CTL_AutomaticReportHeadPointer_bits 2 #define GFX6_RCS_RING_BUFFER_CTL_AutomaticReportHeadPointer_bits 2 static inline uint32_t ATTRIBUTE_PURE RCS_RING_BUFFER_CTL_AutomaticReportHeadPointer_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_RCS_RING_BUFFER_CTL_AutomaticReportHeadPointer_start 1 #define GFX8_RCS_RING_BUFFER_CTL_AutomaticReportHeadPointer_start 1 #define GFX75_RCS_RING_BUFFER_CTL_AutomaticReportHeadPointer_start 1 #define GFX7_RCS_RING_BUFFER_CTL_AutomaticReportHeadPointer_start 1 #define GFX6_RCS_RING_BUFFER_CTL_AutomaticReportHeadPointer_start 1 static inline uint32_t ATTRIBUTE_PURE RCS_RING_BUFFER_CTL_AutomaticReportHeadPointer_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RCS_RING_BUFFER_CTL::Buffer Length (in pages - 1) */ #define GFX9_RCS_RING_BUFFER_CTL_BufferLengthinpages1_bits 9 #define GFX8_RCS_RING_BUFFER_CTL_BufferLengthinpages1_bits 9 #define GFX75_RCS_RING_BUFFER_CTL_BufferLengthinpages1_bits 9 #define GFX7_RCS_RING_BUFFER_CTL_BufferLengthinpages1_bits 9 #define GFX6_RCS_RING_BUFFER_CTL_BufferLengthinpages1_bits 9 static inline uint32_t ATTRIBUTE_PURE RCS_RING_BUFFER_CTL_BufferLengthinpages1_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 9; case 80: return 9; case 75: return 9; case 70: return 9; case 60: return 9; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_RCS_RING_BUFFER_CTL_BufferLengthinpages1_start 12 #define GFX8_RCS_RING_BUFFER_CTL_BufferLengthinpages1_start 12 #define GFX75_RCS_RING_BUFFER_CTL_BufferLengthinpages1_start 12 #define GFX7_RCS_RING_BUFFER_CTL_BufferLengthinpages1_start 12 #define GFX6_RCS_RING_BUFFER_CTL_BufferLengthinpages1_start 12 static inline uint32_t ATTRIBUTE_PURE RCS_RING_BUFFER_CTL_BufferLengthinpages1_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 12; case 80: return 12; case 75: return 12; case 70: return 12; case 60: return 12; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RCS_RING_BUFFER_CTL::RBWait */ #define GFX9_RCS_RING_BUFFER_CTL_RBWait_bits 1 #define GFX8_RCS_RING_BUFFER_CTL_RBWait_bits 1 #define GFX75_RCS_RING_BUFFER_CTL_RBWait_bits 1 #define GFX7_RCS_RING_BUFFER_CTL_RBWait_bits 1 #define GFX6_RCS_RING_BUFFER_CTL_RBWait_bits 1 static inline uint32_t ATTRIBUTE_PURE RCS_RING_BUFFER_CTL_RBWait_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_RCS_RING_BUFFER_CTL_RBWait_start 11 #define GFX8_RCS_RING_BUFFER_CTL_RBWait_start 11 #define GFX75_RCS_RING_BUFFER_CTL_RBWait_start 11 #define GFX7_RCS_RING_BUFFER_CTL_RBWait_start 11 #define GFX6_RCS_RING_BUFFER_CTL_RBWait_start 11 static inline uint32_t ATTRIBUTE_PURE RCS_RING_BUFFER_CTL_RBWait_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 11; case 80: return 11; case 75: return 11; case 70: return 11; case 60: return 11; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RCS_RING_BUFFER_CTL::Ring Buffer Enable */ #define GFX9_RCS_RING_BUFFER_CTL_RingBufferEnable_bits 1 #define GFX8_RCS_RING_BUFFER_CTL_RingBufferEnable_bits 1 #define GFX75_RCS_RING_BUFFER_CTL_RingBufferEnable_bits 1 #define GFX7_RCS_RING_BUFFER_CTL_RingBufferEnable_bits 1 #define GFX6_RCS_RING_BUFFER_CTL_RingBufferEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE RCS_RING_BUFFER_CTL_RingBufferEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_RCS_RING_BUFFER_CTL_RingBufferEnable_start 0 #define GFX8_RCS_RING_BUFFER_CTL_RingBufferEnable_start 0 #define GFX75_RCS_RING_BUFFER_CTL_RingBufferEnable_start 0 #define GFX7_RCS_RING_BUFFER_CTL_RingBufferEnable_start 0 #define GFX6_RCS_RING_BUFFER_CTL_RingBufferEnable_start 0 static inline uint32_t ATTRIBUTE_PURE RCS_RING_BUFFER_CTL_RingBufferEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RCS_RING_BUFFER_CTL::Semaphore Wait */ #define GFX9_RCS_RING_BUFFER_CTL_SemaphoreWait_bits 1 #define GFX8_RCS_RING_BUFFER_CTL_SemaphoreWait_bits 1 #define GFX75_RCS_RING_BUFFER_CTL_SemaphoreWait_bits 1 #define GFX7_RCS_RING_BUFFER_CTL_SemaphoreWait_bits 1 #define GFX6_RCS_RING_BUFFER_CTL_SemaphoreWait_bits 1 static inline uint32_t ATTRIBUTE_PURE RCS_RING_BUFFER_CTL_SemaphoreWait_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_RCS_RING_BUFFER_CTL_SemaphoreWait_start 10 #define GFX8_RCS_RING_BUFFER_CTL_SemaphoreWait_start 10 #define GFX75_RCS_RING_BUFFER_CTL_SemaphoreWait_start 10 #define GFX7_RCS_RING_BUFFER_CTL_SemaphoreWait_start 10 #define GFX6_RCS_RING_BUFFER_CTL_SemaphoreWait_start 10 static inline uint32_t ATTRIBUTE_PURE RCS_RING_BUFFER_CTL_SemaphoreWait_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 10; case 80: return 10; case 75: return 10; case 70: return 10; case 60: return 10; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE */ #define GFX125_RENDER_SURFACE_STATE_length 16 #define GFX12_RENDER_SURFACE_STATE_length 16 #define GFX11_RENDER_SURFACE_STATE_length 16 #define GFX9_RENDER_SURFACE_STATE_length 16 #define GFX8_RENDER_SURFACE_STATE_length 16 #define GFX75_RENDER_SURFACE_STATE_length 8 #define GFX7_RENDER_SURFACE_STATE_length 8 #define GFX6_RENDER_SURFACE_STATE_length 6 #define GFX5_RENDER_SURFACE_STATE_length 6 #define GFX45_RENDER_SURFACE_STATE_length 6 #define GFX4_RENDER_SURFACE_STATE_length 5 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 8; case 70: return 8; case 60: return 6; case 50: return 6; case 45: return 6; case 40: return 5; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Alpha Clear Color */ #define GFX11_RENDER_SURFACE_STATE_AlphaClearColor_bits 32 #define GFX9_RENDER_SURFACE_STATE_AlphaClearColor_bits 32 #define GFX8_RENDER_SURFACE_STATE_AlphaClearColor_bits 1 #define GFX75_RENDER_SURFACE_STATE_AlphaClearColor_bits 1 #define GFX7_RENDER_SURFACE_STATE_AlphaClearColor_bits 1 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_AlphaClearColor_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 32; case 90: return 32; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX11_RENDER_SURFACE_STATE_AlphaClearColor_start 480 #define GFX9_RENDER_SURFACE_STATE_AlphaClearColor_start 480 #define GFX8_RENDER_SURFACE_STATE_AlphaClearColor_start 252 #define GFX75_RENDER_SURFACE_STATE_AlphaClearColor_start 252 #define GFX7_RENDER_SURFACE_STATE_AlphaClearColor_start 252 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_AlphaClearColor_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 480; case 90: return 480; case 80: return 252; case 75: return 252; case 70: return 252; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Append Counter Address */ #define GFX75_RENDER_SURFACE_STATE_AppendCounterAddress_bits 26 #define GFX7_RENDER_SURFACE_STATE_AppendCounterAddress_bits 26 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_AppendCounterAddress_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 26; case 70: return 26; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_RENDER_SURFACE_STATE_AppendCounterAddress_start 198 #define GFX7_RENDER_SURFACE_STATE_AppendCounterAddress_start 198 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_AppendCounterAddress_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 198; case 70: return 198; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Append Counter Enable */ #define GFX75_RENDER_SURFACE_STATE_AppendCounterEnable_bits 1 #define GFX7_RENDER_SURFACE_STATE_AppendCounterEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_AppendCounterEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_RENDER_SURFACE_STATE_AppendCounterEnable_start 193 #define GFX7_RENDER_SURFACE_STATE_AppendCounterEnable_start 193 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_AppendCounterEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 193; case 70: return 193; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Auxiliary Surface Base Address */ #define GFX125_RENDER_SURFACE_STATE_AuxiliarySurfaceBaseAddress_bits 52 #define GFX12_RENDER_SURFACE_STATE_AuxiliarySurfaceBaseAddress_bits 52 #define GFX11_RENDER_SURFACE_STATE_AuxiliarySurfaceBaseAddress_bits 52 #define GFX9_RENDER_SURFACE_STATE_AuxiliarySurfaceBaseAddress_bits 52 #define GFX8_RENDER_SURFACE_STATE_AuxiliarySurfaceBaseAddress_bits 52 #define GFX75_RENDER_SURFACE_STATE_AuxiliarySurfaceBaseAddress_bits 20 #define GFX7_RENDER_SURFACE_STATE_AuxiliarySurfaceBaseAddress_bits 20 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_AuxiliarySurfaceBaseAddress_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 52; case 120: return 52; case 110: return 52; case 90: return 52; case 80: return 52; case 75: return 20; case 70: return 20; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_RENDER_SURFACE_STATE_AuxiliarySurfaceBaseAddress_start 332 #define GFX12_RENDER_SURFACE_STATE_AuxiliarySurfaceBaseAddress_start 332 #define GFX11_RENDER_SURFACE_STATE_AuxiliarySurfaceBaseAddress_start 332 #define GFX9_RENDER_SURFACE_STATE_AuxiliarySurfaceBaseAddress_start 332 #define GFX8_RENDER_SURFACE_STATE_AuxiliarySurfaceBaseAddress_start 332 #define GFX75_RENDER_SURFACE_STATE_AuxiliarySurfaceBaseAddress_start 204 #define GFX7_RENDER_SURFACE_STATE_AuxiliarySurfaceBaseAddress_start 204 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_AuxiliarySurfaceBaseAddress_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 332; case 120: return 332; case 110: return 332; case 90: return 332; case 80: return 332; case 75: return 204; case 70: return 204; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Auxiliary Surface Mode */ #define GFX125_RENDER_SURFACE_STATE_AuxiliarySurfaceMode_bits 3 #define GFX12_RENDER_SURFACE_STATE_AuxiliarySurfaceMode_bits 3 #define GFX11_RENDER_SURFACE_STATE_AuxiliarySurfaceMode_bits 3 #define GFX9_RENDER_SURFACE_STATE_AuxiliarySurfaceMode_bits 3 #define GFX8_RENDER_SURFACE_STATE_AuxiliarySurfaceMode_bits 3 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_AuxiliarySurfaceMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_RENDER_SURFACE_STATE_AuxiliarySurfaceMode_start 192 #define GFX12_RENDER_SURFACE_STATE_AuxiliarySurfaceMode_start 192 #define GFX11_RENDER_SURFACE_STATE_AuxiliarySurfaceMode_start 192 #define GFX9_RENDER_SURFACE_STATE_AuxiliarySurfaceMode_start 192 #define GFX8_RENDER_SURFACE_STATE_AuxiliarySurfaceMode_start 192 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_AuxiliarySurfaceMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 192; case 120: return 192; case 110: return 192; case 90: return 192; case 80: return 192; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Auxiliary Surface Pitch */ #define GFX125_RENDER_SURFACE_STATE_AuxiliarySurfacePitch_bits 9 #define GFX12_RENDER_SURFACE_STATE_AuxiliarySurfacePitch_bits 9 #define GFX11_RENDER_SURFACE_STATE_AuxiliarySurfacePitch_bits 9 #define GFX9_RENDER_SURFACE_STATE_AuxiliarySurfacePitch_bits 9 #define GFX8_RENDER_SURFACE_STATE_AuxiliarySurfacePitch_bits 9 #define GFX75_RENDER_SURFACE_STATE_AuxiliarySurfacePitch_bits 9 #define GFX7_RENDER_SURFACE_STATE_AuxiliarySurfacePitch_bits 9 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_AuxiliarySurfacePitch_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 9; case 120: return 9; case 110: return 9; case 90: return 9; case 80: return 9; case 75: return 9; case 70: return 9; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_RENDER_SURFACE_STATE_AuxiliarySurfacePitch_start 195 #define GFX12_RENDER_SURFACE_STATE_AuxiliarySurfacePitch_start 195 #define GFX11_RENDER_SURFACE_STATE_AuxiliarySurfacePitch_start 195 #define GFX9_RENDER_SURFACE_STATE_AuxiliarySurfacePitch_start 195 #define GFX8_RENDER_SURFACE_STATE_AuxiliarySurfacePitch_start 195 #define GFX75_RENDER_SURFACE_STATE_AuxiliarySurfacePitch_start 195 #define GFX7_RENDER_SURFACE_STATE_AuxiliarySurfacePitch_start 195 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_AuxiliarySurfacePitch_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 195; case 120: return 195; case 110: return 195; case 90: return 195; case 80: return 195; case 75: return 195; case 70: return 195; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Auxiliary Surface QPitch */ #define GFX125_RENDER_SURFACE_STATE_AuxiliarySurfaceQPitch_bits 15 #define GFX12_RENDER_SURFACE_STATE_AuxiliarySurfaceQPitch_bits 15 #define GFX11_RENDER_SURFACE_STATE_AuxiliarySurfaceQPitch_bits 15 #define GFX9_RENDER_SURFACE_STATE_AuxiliarySurfaceQPitch_bits 15 #define GFX8_RENDER_SURFACE_STATE_AuxiliarySurfaceQPitch_bits 15 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_AuxiliarySurfaceQPitch_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 15; case 120: return 15; case 110: return 15; case 90: return 15; case 80: return 15; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_RENDER_SURFACE_STATE_AuxiliarySurfaceQPitch_start 208 #define GFX12_RENDER_SURFACE_STATE_AuxiliarySurfaceQPitch_start 208 #define GFX11_RENDER_SURFACE_STATE_AuxiliarySurfaceQPitch_start 208 #define GFX9_RENDER_SURFACE_STATE_AuxiliarySurfaceQPitch_start 208 #define GFX8_RENDER_SURFACE_STATE_AuxiliarySurfaceQPitch_start 208 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_AuxiliarySurfaceQPitch_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 208; case 120: return 208; case 110: return 208; case 90: return 208; case 80: return 208; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Auxiliary Table Index for Media Compressed Surface */ #define GFX11_RENDER_SURFACE_STATE_AuxiliaryTableIndexforMediaCompressedSurface_bits 11 #define GFX9_RENDER_SURFACE_STATE_AuxiliaryTableIndexforMediaCompressedSurface_bits 11 #define GFX8_RENDER_SURFACE_STATE_AuxiliaryTableIndexforMediaCompressedSurface_bits 11 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_AuxiliaryTableIndexforMediaCompressedSurface_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 11; case 90: return 11; case 80: return 11; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX11_RENDER_SURFACE_STATE_AuxiliaryTableIndexforMediaCompressedSurface_start 341 #define GFX9_RENDER_SURFACE_STATE_AuxiliaryTableIndexforMediaCompressedSurface_start 341 #define GFX8_RENDER_SURFACE_STATE_AuxiliaryTableIndexforMediaCompressedSurface_start 341 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_AuxiliaryTableIndexforMediaCompressedSurface_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 341; case 90: return 341; case 80: return 341; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Base Mip Level */ #define GFX125_RENDER_SURFACE_STATE_BaseMipLevel_bits 5 #define GFX12_RENDER_SURFACE_STATE_BaseMipLevel_bits 5 #define GFX11_RENDER_SURFACE_STATE_BaseMipLevel_bits 5 #define GFX9_RENDER_SURFACE_STATE_BaseMipLevel_bits 5 #define GFX8_RENDER_SURFACE_STATE_BaseMipLevel_bits 5 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_BaseMipLevel_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 5; case 110: return 5; case 90: return 5; case 80: return 5; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_RENDER_SURFACE_STATE_BaseMipLevel_start 51 #define GFX12_RENDER_SURFACE_STATE_BaseMipLevel_start 51 #define GFX11_RENDER_SURFACE_STATE_BaseMipLevel_start 51 #define GFX9_RENDER_SURFACE_STATE_BaseMipLevel_start 51 #define GFX8_RENDER_SURFACE_STATE_BaseMipLevel_start 51 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_BaseMipLevel_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 51; case 120: return 51; case 110: return 51; case 90: return 51; case 80: return 51; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Blue Clear Color */ #define GFX11_RENDER_SURFACE_STATE_BlueClearColor_bits 32 #define GFX9_RENDER_SURFACE_STATE_BlueClearColor_bits 32 #define GFX8_RENDER_SURFACE_STATE_BlueClearColor_bits 1 #define GFX75_RENDER_SURFACE_STATE_BlueClearColor_bits 1 #define GFX7_RENDER_SURFACE_STATE_BlueClearColor_bits 1 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_BlueClearColor_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 32; case 90: return 32; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX11_RENDER_SURFACE_STATE_BlueClearColor_start 448 #define GFX9_RENDER_SURFACE_STATE_BlueClearColor_start 448 #define GFX8_RENDER_SURFACE_STATE_BlueClearColor_start 253 #define GFX75_RENDER_SURFACE_STATE_BlueClearColor_start 253 #define GFX7_RENDER_SURFACE_STATE_BlueClearColor_start 253 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_BlueClearColor_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 448; case 90: return 448; case 80: return 253; case 75: return 253; case 70: return 253; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Caching Expanded Formats */ #define GFX125_RENDER_SURFACE_STATE_CachingExpandedFormats_bits 1 #define GFX12_RENDER_SURFACE_STATE_CachingExpandedFormats_bits 1 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_CachingExpandedFormats_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_RENDER_SURFACE_STATE_CachingExpandedFormats_start 331 #define GFX12_RENDER_SURFACE_STATE_CachingExpandedFormats_start 331 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_CachingExpandedFormats_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 331; case 120: return 331; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Clear Color Conversion Enable */ #define GFX11_RENDER_SURFACE_STATE_ClearColorConversionEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_ClearColorConversionEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX11_RENDER_SURFACE_STATE_ClearColorConversionEnable_start 389 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_ClearColorConversionEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 389; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Clear Value Address */ #define GFX125_RENDER_SURFACE_STATE_ClearValueAddress_bits 42 #define GFX12_RENDER_SURFACE_STATE_ClearValueAddress_bits 42 #define GFX11_RENDER_SURFACE_STATE_ClearValueAddress_bits 42 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_ClearValueAddress_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 42; case 120: return 42; case 110: return 42; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_RENDER_SURFACE_STATE_ClearValueAddress_start 390 #define GFX12_RENDER_SURFACE_STATE_ClearValueAddress_start 390 #define GFX11_RENDER_SURFACE_STATE_ClearValueAddress_start 390 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_ClearValueAddress_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 390; case 120: return 390; case 110: return 390; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Clear Value Address Enable */ #define GFX125_RENDER_SURFACE_STATE_ClearValueAddressEnable_bits 1 #define GFX12_RENDER_SURFACE_STATE_ClearValueAddressEnable_bits 1 #define GFX11_RENDER_SURFACE_STATE_ClearValueAddressEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_ClearValueAddressEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_RENDER_SURFACE_STATE_ClearValueAddressEnable_start 330 #define GFX12_RENDER_SURFACE_STATE_ClearValueAddressEnable_start 330 #define GFX11_RENDER_SURFACE_STATE_ClearValueAddressEnable_start 330 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_ClearValueAddressEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 330; case 120: return 330; case 110: return 330; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Coherency Type */ #define GFX125_RENDER_SURFACE_STATE_CoherencyType_bits 1 #define GFX12_RENDER_SURFACE_STATE_CoherencyType_bits 1 #define GFX11_RENDER_SURFACE_STATE_CoherencyType_bits 1 #define GFX9_RENDER_SURFACE_STATE_CoherencyType_bits 1 #define GFX8_RENDER_SURFACE_STATE_CoherencyType_bits 1 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_CoherencyType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_RENDER_SURFACE_STATE_CoherencyType_start 174 #define GFX12_RENDER_SURFACE_STATE_CoherencyType_start 174 #define GFX11_RENDER_SURFACE_STATE_CoherencyType_start 174 #define GFX9_RENDER_SURFACE_STATE_CoherencyType_start 174 #define GFX8_RENDER_SURFACE_STATE_CoherencyType_start 174 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_CoherencyType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 174; case 120: return 174; case 110: return 174; case 90: return 174; case 80: return 174; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Color Blend Enable */ #define GFX5_RENDER_SURFACE_STATE_ColorBlendEnable_bits 1 #define GFX45_RENDER_SURFACE_STATE_ColorBlendEnable_bits 1 #define GFX4_RENDER_SURFACE_STATE_ColorBlendEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_ColorBlendEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_RENDER_SURFACE_STATE_ColorBlendEnable_start 13 #define GFX45_RENDER_SURFACE_STATE_ColorBlendEnable_start 13 #define GFX4_RENDER_SURFACE_STATE_ColorBlendEnable_start 13 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_ColorBlendEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 13; case 45: return 13; case 40: return 13; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Color Buffer Component Write Disables */ #define GFX5_RENDER_SURFACE_STATE_ColorBufferComponentWriteDisables_bits 4 #define GFX45_RENDER_SURFACE_STATE_ColorBufferComponentWriteDisables_bits 4 #define GFX4_RENDER_SURFACE_STATE_ColorBufferComponentWriteDisables_bits 4 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_ColorBufferComponentWriteDisables_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 4; case 45: return 4; case 40: return 4; default: unreachable("Invalid hardware generation"); } } #define GFX5_RENDER_SURFACE_STATE_ColorBufferComponentWriteDisables_start 14 #define GFX45_RENDER_SURFACE_STATE_ColorBufferComponentWriteDisables_start 14 #define GFX4_RENDER_SURFACE_STATE_ColorBufferComponentWriteDisables_start 14 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_ColorBufferComponentWriteDisables_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 14; case 45: return 14; case 40: return 14; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Corner Texel Mode */ #define GFX125_RENDER_SURFACE_STATE_CornerTexelMode_bits 1 #define GFX12_RENDER_SURFACE_STATE_CornerTexelMode_bits 1 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_CornerTexelMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_RENDER_SURFACE_STATE_CornerTexelMode_start 50 #define GFX12_RENDER_SURFACE_STATE_CornerTexelMode_start 50 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_CornerTexelMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 50; case 120: return 50; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Cube Face Enable - Negative X */ #define GFX125_RENDER_SURFACE_STATE_CubeFaceEnableNegativeX_bits 1 #define GFX12_RENDER_SURFACE_STATE_CubeFaceEnableNegativeX_bits 1 #define GFX11_RENDER_SURFACE_STATE_CubeFaceEnableNegativeX_bits 1 #define GFX9_RENDER_SURFACE_STATE_CubeFaceEnableNegativeX_bits 1 #define GFX8_RENDER_SURFACE_STATE_CubeFaceEnableNegativeX_bits 1 #define GFX75_RENDER_SURFACE_STATE_CubeFaceEnableNegativeX_bits 1 #define GFX7_RENDER_SURFACE_STATE_CubeFaceEnableNegativeX_bits 1 #define GFX6_RENDER_SURFACE_STATE_CubeFaceEnableNegativeX_bits 1 #define GFX5_RENDER_SURFACE_STATE_CubeFaceEnableNegativeX_bits 1 #define GFX45_RENDER_SURFACE_STATE_CubeFaceEnableNegativeX_bits 1 #define GFX4_RENDER_SURFACE_STATE_CubeFaceEnableNegativeX_bits 1 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_CubeFaceEnableNegativeX_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX125_RENDER_SURFACE_STATE_CubeFaceEnableNegativeX_start 5 #define GFX12_RENDER_SURFACE_STATE_CubeFaceEnableNegativeX_start 5 #define GFX11_RENDER_SURFACE_STATE_CubeFaceEnableNegativeX_start 5 #define GFX9_RENDER_SURFACE_STATE_CubeFaceEnableNegativeX_start 5 #define GFX8_RENDER_SURFACE_STATE_CubeFaceEnableNegativeX_start 5 #define GFX75_RENDER_SURFACE_STATE_CubeFaceEnableNegativeX_start 5 #define GFX7_RENDER_SURFACE_STATE_CubeFaceEnableNegativeX_start 5 #define GFX6_RENDER_SURFACE_STATE_CubeFaceEnableNegativeX_start 5 #define GFX5_RENDER_SURFACE_STATE_CubeFaceEnableNegativeX_start 5 #define GFX45_RENDER_SURFACE_STATE_CubeFaceEnableNegativeX_start 5 #define GFX4_RENDER_SURFACE_STATE_CubeFaceEnableNegativeX_start 5 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_CubeFaceEnableNegativeX_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 5; case 110: return 5; case 90: return 5; case 80: return 5; case 75: return 5; case 70: return 5; case 60: return 5; case 50: return 5; case 45: return 5; case 40: return 5; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Cube Face Enable - Negative Y */ #define GFX125_RENDER_SURFACE_STATE_CubeFaceEnableNegativeY_bits 1 #define GFX12_RENDER_SURFACE_STATE_CubeFaceEnableNegativeY_bits 1 #define GFX11_RENDER_SURFACE_STATE_CubeFaceEnableNegativeY_bits 1 #define GFX9_RENDER_SURFACE_STATE_CubeFaceEnableNegativeY_bits 1 #define GFX8_RENDER_SURFACE_STATE_CubeFaceEnableNegativeY_bits 1 #define GFX75_RENDER_SURFACE_STATE_CubeFaceEnableNegativeY_bits 1 #define GFX7_RENDER_SURFACE_STATE_CubeFaceEnableNegativeY_bits 1 #define GFX6_RENDER_SURFACE_STATE_CubeFaceEnableNegativeY_bits 1 #define GFX5_RENDER_SURFACE_STATE_CubeFaceEnableNegativeY_bits 1 #define GFX45_RENDER_SURFACE_STATE_CubeFaceEnableNegativeY_bits 1 #define GFX4_RENDER_SURFACE_STATE_CubeFaceEnableNegativeY_bits 1 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_CubeFaceEnableNegativeY_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX125_RENDER_SURFACE_STATE_CubeFaceEnableNegativeY_start 3 #define GFX12_RENDER_SURFACE_STATE_CubeFaceEnableNegativeY_start 3 #define GFX11_RENDER_SURFACE_STATE_CubeFaceEnableNegativeY_start 3 #define GFX9_RENDER_SURFACE_STATE_CubeFaceEnableNegativeY_start 3 #define GFX8_RENDER_SURFACE_STATE_CubeFaceEnableNegativeY_start 3 #define GFX75_RENDER_SURFACE_STATE_CubeFaceEnableNegativeY_start 3 #define GFX7_RENDER_SURFACE_STATE_CubeFaceEnableNegativeY_start 3 #define GFX6_RENDER_SURFACE_STATE_CubeFaceEnableNegativeY_start 3 #define GFX5_RENDER_SURFACE_STATE_CubeFaceEnableNegativeY_start 3 #define GFX45_RENDER_SURFACE_STATE_CubeFaceEnableNegativeY_start 3 #define GFX4_RENDER_SURFACE_STATE_CubeFaceEnableNegativeY_start 3 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_CubeFaceEnableNegativeY_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Cube Face Enable - Negative Z */ #define GFX125_RENDER_SURFACE_STATE_CubeFaceEnableNegativeZ_bits 1 #define GFX12_RENDER_SURFACE_STATE_CubeFaceEnableNegativeZ_bits 1 #define GFX11_RENDER_SURFACE_STATE_CubeFaceEnableNegativeZ_bits 1 #define GFX9_RENDER_SURFACE_STATE_CubeFaceEnableNegativeZ_bits 1 #define GFX8_RENDER_SURFACE_STATE_CubeFaceEnableNegativeZ_bits 1 #define GFX75_RENDER_SURFACE_STATE_CubeFaceEnableNegativeZ_bits 1 #define GFX7_RENDER_SURFACE_STATE_CubeFaceEnableNegativeZ_bits 1 #define GFX6_RENDER_SURFACE_STATE_CubeFaceEnableNegativeZ_bits 1 #define GFX5_RENDER_SURFACE_STATE_CubeFaceEnableNegativeZ_bits 1 #define GFX45_RENDER_SURFACE_STATE_CubeFaceEnableNegativeZ_bits 1 #define GFX4_RENDER_SURFACE_STATE_CubeFaceEnableNegativeZ_bits 1 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_CubeFaceEnableNegativeZ_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX125_RENDER_SURFACE_STATE_CubeFaceEnableNegativeZ_start 1 #define GFX12_RENDER_SURFACE_STATE_CubeFaceEnableNegativeZ_start 1 #define GFX11_RENDER_SURFACE_STATE_CubeFaceEnableNegativeZ_start 1 #define GFX9_RENDER_SURFACE_STATE_CubeFaceEnableNegativeZ_start 1 #define GFX8_RENDER_SURFACE_STATE_CubeFaceEnableNegativeZ_start 1 #define GFX75_RENDER_SURFACE_STATE_CubeFaceEnableNegativeZ_start 1 #define GFX7_RENDER_SURFACE_STATE_CubeFaceEnableNegativeZ_start 1 #define GFX6_RENDER_SURFACE_STATE_CubeFaceEnableNegativeZ_start 1 #define GFX5_RENDER_SURFACE_STATE_CubeFaceEnableNegativeZ_start 1 #define GFX45_RENDER_SURFACE_STATE_CubeFaceEnableNegativeZ_start 1 #define GFX4_RENDER_SURFACE_STATE_CubeFaceEnableNegativeZ_start 1 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_CubeFaceEnableNegativeZ_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Cube Face Enable - Positive X */ #define GFX125_RENDER_SURFACE_STATE_CubeFaceEnablePositiveX_bits 1 #define GFX12_RENDER_SURFACE_STATE_CubeFaceEnablePositiveX_bits 1 #define GFX11_RENDER_SURFACE_STATE_CubeFaceEnablePositiveX_bits 1 #define GFX9_RENDER_SURFACE_STATE_CubeFaceEnablePositiveX_bits 1 #define GFX8_RENDER_SURFACE_STATE_CubeFaceEnablePositiveX_bits 1 #define GFX75_RENDER_SURFACE_STATE_CubeFaceEnablePositiveX_bits 1 #define GFX7_RENDER_SURFACE_STATE_CubeFaceEnablePositiveX_bits 1 #define GFX6_RENDER_SURFACE_STATE_CubeFaceEnablePositiveX_bits 1 #define GFX5_RENDER_SURFACE_STATE_CubeFaceEnablePositiveX_bits 1 #define GFX45_RENDER_SURFACE_STATE_CubeFaceEnablePositiveX_bits 1 #define GFX4_RENDER_SURFACE_STATE_CubeFaceEnablePositiveX_bits 1 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_CubeFaceEnablePositiveX_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX125_RENDER_SURFACE_STATE_CubeFaceEnablePositiveX_start 4 #define GFX12_RENDER_SURFACE_STATE_CubeFaceEnablePositiveX_start 4 #define GFX11_RENDER_SURFACE_STATE_CubeFaceEnablePositiveX_start 4 #define GFX9_RENDER_SURFACE_STATE_CubeFaceEnablePositiveX_start 4 #define GFX8_RENDER_SURFACE_STATE_CubeFaceEnablePositiveX_start 4 #define GFX75_RENDER_SURFACE_STATE_CubeFaceEnablePositiveX_start 4 #define GFX7_RENDER_SURFACE_STATE_CubeFaceEnablePositiveX_start 4 #define GFX6_RENDER_SURFACE_STATE_CubeFaceEnablePositiveX_start 4 #define GFX5_RENDER_SURFACE_STATE_CubeFaceEnablePositiveX_start 4 #define GFX45_RENDER_SURFACE_STATE_CubeFaceEnablePositiveX_start 4 #define GFX4_RENDER_SURFACE_STATE_CubeFaceEnablePositiveX_start 4 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_CubeFaceEnablePositiveX_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 4; case 70: return 4; case 60: return 4; case 50: return 4; case 45: return 4; case 40: return 4; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Cube Face Enable - Positive Y */ #define GFX125_RENDER_SURFACE_STATE_CubeFaceEnablePositiveY_bits 1 #define GFX12_RENDER_SURFACE_STATE_CubeFaceEnablePositiveY_bits 1 #define GFX11_RENDER_SURFACE_STATE_CubeFaceEnablePositiveY_bits 1 #define GFX9_RENDER_SURFACE_STATE_CubeFaceEnablePositiveY_bits 1 #define GFX8_RENDER_SURFACE_STATE_CubeFaceEnablePositiveY_bits 1 #define GFX75_RENDER_SURFACE_STATE_CubeFaceEnablePositiveY_bits 1 #define GFX7_RENDER_SURFACE_STATE_CubeFaceEnablePositiveY_bits 1 #define GFX6_RENDER_SURFACE_STATE_CubeFaceEnablePositiveY_bits 1 #define GFX5_RENDER_SURFACE_STATE_CubeFaceEnablePositiveY_bits 1 #define GFX45_RENDER_SURFACE_STATE_CubeFaceEnablePositiveY_bits 1 #define GFX4_RENDER_SURFACE_STATE_CubeFaceEnablePositiveY_bits 1 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_CubeFaceEnablePositiveY_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX125_RENDER_SURFACE_STATE_CubeFaceEnablePositiveY_start 2 #define GFX12_RENDER_SURFACE_STATE_CubeFaceEnablePositiveY_start 2 #define GFX11_RENDER_SURFACE_STATE_CubeFaceEnablePositiveY_start 2 #define GFX9_RENDER_SURFACE_STATE_CubeFaceEnablePositiveY_start 2 #define GFX8_RENDER_SURFACE_STATE_CubeFaceEnablePositiveY_start 2 #define GFX75_RENDER_SURFACE_STATE_CubeFaceEnablePositiveY_start 2 #define GFX7_RENDER_SURFACE_STATE_CubeFaceEnablePositiveY_start 2 #define GFX6_RENDER_SURFACE_STATE_CubeFaceEnablePositiveY_start 2 #define GFX5_RENDER_SURFACE_STATE_CubeFaceEnablePositiveY_start 2 #define GFX45_RENDER_SURFACE_STATE_CubeFaceEnablePositiveY_start 2 #define GFX4_RENDER_SURFACE_STATE_CubeFaceEnablePositiveY_start 2 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_CubeFaceEnablePositiveY_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 2; case 45: return 2; case 40: return 2; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Cube Face Enable - Positive Z */ #define GFX125_RENDER_SURFACE_STATE_CubeFaceEnablePositiveZ_bits 1 #define GFX12_RENDER_SURFACE_STATE_CubeFaceEnablePositiveZ_bits 1 #define GFX11_RENDER_SURFACE_STATE_CubeFaceEnablePositiveZ_bits 1 #define GFX9_RENDER_SURFACE_STATE_CubeFaceEnablePositiveZ_bits 1 #define GFX8_RENDER_SURFACE_STATE_CubeFaceEnablePositiveZ_bits 1 #define GFX75_RENDER_SURFACE_STATE_CubeFaceEnablePositiveZ_bits 1 #define GFX7_RENDER_SURFACE_STATE_CubeFaceEnablePositiveZ_bits 1 #define GFX6_RENDER_SURFACE_STATE_CubeFaceEnablePositiveZ_bits 1 #define GFX5_RENDER_SURFACE_STATE_CubeFaceEnablePositiveZ_bits 1 #define GFX45_RENDER_SURFACE_STATE_CubeFaceEnablePositiveZ_bits 1 #define GFX4_RENDER_SURFACE_STATE_CubeFaceEnablePositiveZ_bits 1 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_CubeFaceEnablePositiveZ_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX125_RENDER_SURFACE_STATE_CubeFaceEnablePositiveZ_start 0 #define GFX12_RENDER_SURFACE_STATE_CubeFaceEnablePositiveZ_start 0 #define GFX11_RENDER_SURFACE_STATE_CubeFaceEnablePositiveZ_start 0 #define GFX9_RENDER_SURFACE_STATE_CubeFaceEnablePositiveZ_start 0 #define GFX8_RENDER_SURFACE_STATE_CubeFaceEnablePositiveZ_start 0 #define GFX75_RENDER_SURFACE_STATE_CubeFaceEnablePositiveZ_start 0 #define GFX7_RENDER_SURFACE_STATE_CubeFaceEnablePositiveZ_start 0 #define GFX6_RENDER_SURFACE_STATE_CubeFaceEnablePositiveZ_start 0 #define GFX5_RENDER_SURFACE_STATE_CubeFaceEnablePositiveZ_start 0 #define GFX45_RENDER_SURFACE_STATE_CubeFaceEnablePositiveZ_start 0 #define GFX4_RENDER_SURFACE_STATE_CubeFaceEnablePositiveZ_start 0 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_CubeFaceEnablePositiveZ_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Cube Map Corner Mode */ #define GFX6_RENDER_SURFACE_STATE_CubeMapCornerMode_bits 1 #define GFX5_RENDER_SURFACE_STATE_CubeMapCornerMode_bits 1 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_CubeMapCornerMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 1; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_RENDER_SURFACE_STATE_CubeMapCornerMode_start 9 #define GFX5_RENDER_SURFACE_STATE_CubeMapCornerMode_start 9 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_CubeMapCornerMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 9; case 50: return 9; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Data Return Format */ #define GFX6_RENDER_SURFACE_STATE_DataReturnFormat_bits 1 #define GFX5_RENDER_SURFACE_STATE_DataReturnFormat_bits 1 #define GFX45_RENDER_SURFACE_STATE_DataReturnFormat_bits 1 #define GFX4_RENDER_SURFACE_STATE_DataReturnFormat_bits 1 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_DataReturnFormat_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX6_RENDER_SURFACE_STATE_DataReturnFormat_start 27 #define GFX5_RENDER_SURFACE_STATE_DataReturnFormat_start 27 #define GFX45_RENDER_SURFACE_STATE_DataReturnFormat_start 27 #define GFX4_RENDER_SURFACE_STATE_DataReturnFormat_start 27 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_DataReturnFormat_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 27; case 50: return 27; case 45: return 27; case 40: return 27; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Depth */ #define GFX125_RENDER_SURFACE_STATE_Depth_bits 11 #define GFX12_RENDER_SURFACE_STATE_Depth_bits 11 #define GFX11_RENDER_SURFACE_STATE_Depth_bits 11 #define GFX9_RENDER_SURFACE_STATE_Depth_bits 11 #define GFX8_RENDER_SURFACE_STATE_Depth_bits 11 #define GFX75_RENDER_SURFACE_STATE_Depth_bits 11 #define GFX7_RENDER_SURFACE_STATE_Depth_bits 11 #define GFX6_RENDER_SURFACE_STATE_Depth_bits 11 #define GFX5_RENDER_SURFACE_STATE_Depth_bits 11 #define GFX45_RENDER_SURFACE_STATE_Depth_bits 11 #define GFX4_RENDER_SURFACE_STATE_Depth_bits 11 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_Depth_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 11; case 120: return 11; case 110: return 11; case 90: return 11; case 80: return 11; case 75: return 11; case 70: return 11; case 60: return 11; case 50: return 11; case 45: return 11; case 40: return 11; default: unreachable("Invalid hardware generation"); } } #define GFX125_RENDER_SURFACE_STATE_Depth_start 117 #define GFX12_RENDER_SURFACE_STATE_Depth_start 117 #define GFX11_RENDER_SURFACE_STATE_Depth_start 117 #define GFX9_RENDER_SURFACE_STATE_Depth_start 117 #define GFX8_RENDER_SURFACE_STATE_Depth_start 117 #define GFX75_RENDER_SURFACE_STATE_Depth_start 117 #define GFX7_RENDER_SURFACE_STATE_Depth_start 117 #define GFX6_RENDER_SURFACE_STATE_Depth_start 117 #define GFX5_RENDER_SURFACE_STATE_Depth_start 117 #define GFX45_RENDER_SURFACE_STATE_Depth_start 117 #define GFX4_RENDER_SURFACE_STATE_Depth_start 117 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_Depth_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 117; case 120: return 117; case 110: return 117; case 90: return 117; case 80: return 117; case 75: return 117; case 70: return 117; case 60: return 117; case 50: return 117; case 45: return 117; case 40: return 117; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Depth Stencil Resource */ #define GFX125_RENDER_SURFACE_STATE_DepthStencilResource_bits 1 #define GFX12_RENDER_SURFACE_STATE_DepthStencilResource_bits 1 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_DepthStencilResource_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_RENDER_SURFACE_STATE_DepthStencilResource_start 95 #define GFX12_RENDER_SURFACE_STATE_DepthStencilResource_start 95 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_DepthStencilResource_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 95; case 120: return 95; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Double Fetch Disable */ #define GFX125_RENDER_SURFACE_STATE_DoubleFetchDisable_bits 1 #define GFX12_RENDER_SURFACE_STATE_DoubleFetchDisable_bits 1 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_DoubleFetchDisable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_RENDER_SURFACE_STATE_DoubleFetchDisable_start 49 #define GFX12_RENDER_SURFACE_STATE_DoubleFetchDisable_start 49 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_DoubleFetchDisable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 49; case 120: return 49; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::EWA Disable For Cube */ #define GFX125_RENDER_SURFACE_STATE_EWADisableForCube_bits 1 #define GFX12_RENDER_SURFACE_STATE_EWADisableForCube_bits 1 #define GFX11_RENDER_SURFACE_STATE_EWADisableForCube_bits 1 #define GFX9_RENDER_SURFACE_STATE_EWADisableForCube_bits 1 #define GFX8_RENDER_SURFACE_STATE_EWADisableForCube_bits 1 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_EWADisableForCube_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_RENDER_SURFACE_STATE_EWADisableForCube_start 180 #define GFX12_RENDER_SURFACE_STATE_EWADisableForCube_start 180 #define GFX11_RENDER_SURFACE_STATE_EWADisableForCube_start 180 #define GFX9_RENDER_SURFACE_STATE_EWADisableForCube_start 180 #define GFX8_RENDER_SURFACE_STATE_EWADisableForCube_start 180 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_EWADisableForCube_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 180; case 120: return 180; case 110: return 180; case 90: return 180; case 80: return 180; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Enable Unorm Path In Color Pipe */ #define GFX125_RENDER_SURFACE_STATE_EnableUnormPathInColorPipe_bits 1 #define GFX12_RENDER_SURFACE_STATE_EnableUnormPathInColorPipe_bits 1 #define GFX11_RENDER_SURFACE_STATE_EnableUnormPathInColorPipe_bits 1 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_EnableUnormPathInColorPipe_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_RENDER_SURFACE_STATE_EnableUnormPathInColorPipe_start 63 #define GFX12_RENDER_SURFACE_STATE_EnableUnormPathInColorPipe_start 63 #define GFX11_RENDER_SURFACE_STATE_EnableUnormPathInColorPipe_start 63 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_EnableUnormPathInColorPipe_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 63; case 120: return 63; case 110: return 63; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Green Clear Color */ #define GFX11_RENDER_SURFACE_STATE_GreenClearColor_bits 32 #define GFX9_RENDER_SURFACE_STATE_GreenClearColor_bits 32 #define GFX8_RENDER_SURFACE_STATE_GreenClearColor_bits 1 #define GFX75_RENDER_SURFACE_STATE_GreenClearColor_bits 1 #define GFX7_RENDER_SURFACE_STATE_GreenClearColor_bits 1 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_GreenClearColor_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 32; case 90: return 32; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX11_RENDER_SURFACE_STATE_GreenClearColor_start 416 #define GFX9_RENDER_SURFACE_STATE_GreenClearColor_start 416 #define GFX8_RENDER_SURFACE_STATE_GreenClearColor_start 254 #define GFX75_RENDER_SURFACE_STATE_GreenClearColor_start 254 #define GFX7_RENDER_SURFACE_STATE_GreenClearColor_start 254 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_GreenClearColor_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 416; case 90: return 416; case 80: return 254; case 75: return 254; case 70: return 254; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Half Pitch for Chroma */ #define GFX125_RENDER_SURFACE_STATE_HalfPitchforChroma_bits 1 #define GFX12_RENDER_SURFACE_STATE_HalfPitchforChroma_bits 1 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_HalfPitchforChroma_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_RENDER_SURFACE_STATE_HalfPitchforChroma_start 222 #define GFX12_RENDER_SURFACE_STATE_HalfPitchforChroma_start 222 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_HalfPitchforChroma_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 222; case 120: return 222; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Height */ #define GFX125_RENDER_SURFACE_STATE_Height_bits 14 #define GFX12_RENDER_SURFACE_STATE_Height_bits 14 #define GFX11_RENDER_SURFACE_STATE_Height_bits 14 #define GFX9_RENDER_SURFACE_STATE_Height_bits 14 #define GFX8_RENDER_SURFACE_STATE_Height_bits 14 #define GFX75_RENDER_SURFACE_STATE_Height_bits 14 #define GFX7_RENDER_SURFACE_STATE_Height_bits 14 #define GFX6_RENDER_SURFACE_STATE_Height_bits 13 #define GFX5_RENDER_SURFACE_STATE_Height_bits 13 #define GFX45_RENDER_SURFACE_STATE_Height_bits 13 #define GFX4_RENDER_SURFACE_STATE_Height_bits 13 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_Height_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 14; case 120: return 14; case 110: return 14; case 90: return 14; case 80: return 14; case 75: return 14; case 70: return 14; case 60: return 13; case 50: return 13; case 45: return 13; case 40: return 13; default: unreachable("Invalid hardware generation"); } } #define GFX125_RENDER_SURFACE_STATE_Height_start 80 #define GFX12_RENDER_SURFACE_STATE_Height_start 80 #define GFX11_RENDER_SURFACE_STATE_Height_start 80 #define GFX9_RENDER_SURFACE_STATE_Height_start 80 #define GFX8_RENDER_SURFACE_STATE_Height_start 80 #define GFX75_RENDER_SURFACE_STATE_Height_start 80 #define GFX7_RENDER_SURFACE_STATE_Height_start 80 #define GFX6_RENDER_SURFACE_STATE_Height_start 83 #define GFX5_RENDER_SURFACE_STATE_Height_start 83 #define GFX45_RENDER_SURFACE_STATE_Height_start 83 #define GFX4_RENDER_SURFACE_STATE_Height_start 83 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_Height_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 80; case 120: return 80; case 110: return 80; case 90: return 80; case 80: return 80; case 75: return 80; case 70: return 80; case 60: return 83; case 50: return 83; case 45: return 83; case 40: return 83; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Hierarchical Depth Clear Value */ #define GFX9_RENDER_SURFACE_STATE_HierarchicalDepthClearValue_bits 32 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_HierarchicalDepthClearValue_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 32; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_RENDER_SURFACE_STATE_HierarchicalDepthClearValue_start 384 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_HierarchicalDepthClearValue_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 384; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Integer Surface Format */ #define GFX75_RENDER_SURFACE_STATE_IntegerSurfaceFormat_bits 3 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_IntegerSurfaceFormat_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 3; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_RENDER_SURFACE_STATE_IntegerSurfaceFormat_start 114 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_IntegerSurfaceFormat_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 114; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::MCS Enable */ #define GFX75_RENDER_SURFACE_STATE_MCSEnable_bits 1 #define GFX7_RENDER_SURFACE_STATE_MCSEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_MCSEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_RENDER_SURFACE_STATE_MCSEnable_start 192 #define GFX7_RENDER_SURFACE_STATE_MCSEnable_start 192 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_MCSEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 192; case 70: return 192; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::MIP Count / LOD */ #define GFX125_RENDER_SURFACE_STATE_MIPCountLOD_bits 4 #define GFX12_RENDER_SURFACE_STATE_MIPCountLOD_bits 4 #define GFX11_RENDER_SURFACE_STATE_MIPCountLOD_bits 4 #define GFX9_RENDER_SURFACE_STATE_MIPCountLOD_bits 4 #define GFX8_RENDER_SURFACE_STATE_MIPCountLOD_bits 4 #define GFX75_RENDER_SURFACE_STATE_MIPCountLOD_bits 4 #define GFX7_RENDER_SURFACE_STATE_MIPCountLOD_bits 4 #define GFX6_RENDER_SURFACE_STATE_MIPCountLOD_bits 4 #define GFX5_RENDER_SURFACE_STATE_MIPCountLOD_bits 4 #define GFX45_RENDER_SURFACE_STATE_MIPCountLOD_bits 4 #define GFX4_RENDER_SURFACE_STATE_MIPCountLOD_bits 4 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_MIPCountLOD_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 4; case 70: return 4; case 60: return 4; case 50: return 4; case 45: return 4; case 40: return 4; default: unreachable("Invalid hardware generation"); } } #define GFX125_RENDER_SURFACE_STATE_MIPCountLOD_start 160 #define GFX12_RENDER_SURFACE_STATE_MIPCountLOD_start 160 #define GFX11_RENDER_SURFACE_STATE_MIPCountLOD_start 160 #define GFX9_RENDER_SURFACE_STATE_MIPCountLOD_start 160 #define GFX8_RENDER_SURFACE_STATE_MIPCountLOD_start 160 #define GFX75_RENDER_SURFACE_STATE_MIPCountLOD_start 160 #define GFX7_RENDER_SURFACE_STATE_MIPCountLOD_start 160 #define GFX6_RENDER_SURFACE_STATE_MIPCountLOD_start 66 #define GFX5_RENDER_SURFACE_STATE_MIPCountLOD_start 66 #define GFX45_RENDER_SURFACE_STATE_MIPCountLOD_start 66 #define GFX4_RENDER_SURFACE_STATE_MIPCountLOD_start 66 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_MIPCountLOD_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 160; case 120: return 160; case 110: return 160; case 90: return 160; case 80: return 160; case 75: return 160; case 70: return 160; case 60: return 66; case 50: return 66; case 45: return 66; case 40: return 66; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::MIP Map Layout Mode */ #define GFX6_RENDER_SURFACE_STATE_MIPMapLayoutMode_bits 1 #define GFX5_RENDER_SURFACE_STATE_MIPMapLayoutMode_bits 1 #define GFX45_RENDER_SURFACE_STATE_MIPMapLayoutMode_bits 1 #define GFX4_RENDER_SURFACE_STATE_MIPMapLayoutMode_bits 1 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_MIPMapLayoutMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX6_RENDER_SURFACE_STATE_MIPMapLayoutMode_start 10 #define GFX5_RENDER_SURFACE_STATE_MIPMapLayoutMode_start 10 #define GFX45_RENDER_SURFACE_STATE_MIPMapLayoutMode_start 10 #define GFX4_RENDER_SURFACE_STATE_MIPMapLayoutMode_start 10 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_MIPMapLayoutMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 10; case 50: return 10; case 45: return 10; case 40: return 10; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::MOCS */ #define GFX125_RENDER_SURFACE_STATE_MOCS_bits 7 #define GFX12_RENDER_SURFACE_STATE_MOCS_bits 7 #define GFX11_RENDER_SURFACE_STATE_MOCS_bits 7 #define GFX9_RENDER_SURFACE_STATE_MOCS_bits 7 #define GFX8_RENDER_SURFACE_STATE_MOCS_bits 7 #define GFX75_RENDER_SURFACE_STATE_MOCS_bits 4 #define GFX7_RENDER_SURFACE_STATE_MOCS_bits 4 #define GFX6_RENDER_SURFACE_STATE_MOCS_bits 4 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_MOCS_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 7; case 120: return 7; case 110: return 7; case 90: return 7; case 80: return 7; case 75: return 4; case 70: return 4; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_RENDER_SURFACE_STATE_MOCS_start 56 #define GFX12_RENDER_SURFACE_STATE_MOCS_start 56 #define GFX11_RENDER_SURFACE_STATE_MOCS_start 56 #define GFX9_RENDER_SURFACE_STATE_MOCS_start 56 #define GFX8_RENDER_SURFACE_STATE_MOCS_start 56 #define GFX75_RENDER_SURFACE_STATE_MOCS_start 176 #define GFX7_RENDER_SURFACE_STATE_MOCS_start 176 #define GFX6_RENDER_SURFACE_STATE_MOCS_start 176 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_MOCS_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 56; case 120: return 56; case 110: return 56; case 90: return 56; case 80: return 56; case 75: return 176; case 70: return 176; case 60: return 176; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Media Boundary Pixel Mode */ #define GFX125_RENDER_SURFACE_STATE_MediaBoundaryPixelMode_bits 2 #define GFX12_RENDER_SURFACE_STATE_MediaBoundaryPixelMode_bits 2 #define GFX11_RENDER_SURFACE_STATE_MediaBoundaryPixelMode_bits 2 #define GFX9_RENDER_SURFACE_STATE_MediaBoundaryPixelMode_bits 2 #define GFX8_RENDER_SURFACE_STATE_MediaBoundaryPixelMode_bits 2 #define GFX75_RENDER_SURFACE_STATE_MediaBoundaryPixelMode_bits 2 #define GFX7_RENDER_SURFACE_STATE_MediaBoundaryPixelMode_bits 2 #define GFX6_RENDER_SURFACE_STATE_MediaBoundaryPixelMode_bits 2 #define GFX5_RENDER_SURFACE_STATE_MediaBoundaryPixelMode_bits 2 #define GFX45_RENDER_SURFACE_STATE_MediaBoundaryPixelMode_bits 2 #define GFX4_RENDER_SURFACE_STATE_MediaBoundaryPixelMode_bits 2 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_MediaBoundaryPixelMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 2; case 45: return 2; case 40: return 2; default: unreachable("Invalid hardware generation"); } } #define GFX125_RENDER_SURFACE_STATE_MediaBoundaryPixelMode_start 6 #define GFX12_RENDER_SURFACE_STATE_MediaBoundaryPixelMode_start 6 #define GFX11_RENDER_SURFACE_STATE_MediaBoundaryPixelMode_start 6 #define GFX9_RENDER_SURFACE_STATE_MediaBoundaryPixelMode_start 6 #define GFX8_RENDER_SURFACE_STATE_MediaBoundaryPixelMode_start 6 #define GFX75_RENDER_SURFACE_STATE_MediaBoundaryPixelMode_start 6 #define GFX7_RENDER_SURFACE_STATE_MediaBoundaryPixelMode_start 6 #define GFX6_RENDER_SURFACE_STATE_MediaBoundaryPixelMode_start 6 #define GFX5_RENDER_SURFACE_STATE_MediaBoundaryPixelMode_start 6 #define GFX45_RENDER_SURFACE_STATE_MediaBoundaryPixelMode_start 6 #define GFX4_RENDER_SURFACE_STATE_MediaBoundaryPixelMode_start 6 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_MediaBoundaryPixelMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 6; case 60: return 6; case 50: return 6; case 45: return 6; case 40: return 6; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Memory Compression Enable */ #define GFX125_RENDER_SURFACE_STATE_MemoryCompressionEnable_bits 1 #define GFX12_RENDER_SURFACE_STATE_MemoryCompressionEnable_bits 1 #define GFX11_RENDER_SURFACE_STATE_MemoryCompressionEnable_bits 1 #define GFX9_RENDER_SURFACE_STATE_MemoryCompressionEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_MemoryCompressionEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_RENDER_SURFACE_STATE_MemoryCompressionEnable_start 254 #define GFX12_RENDER_SURFACE_STATE_MemoryCompressionEnable_start 254 #define GFX11_RENDER_SURFACE_STATE_MemoryCompressionEnable_start 254 #define GFX9_RENDER_SURFACE_STATE_MemoryCompressionEnable_start 254 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_MemoryCompressionEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 254; case 120: return 254; case 110: return 254; case 90: return 254; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Memory Compression Mode */ #define GFX125_RENDER_SURFACE_STATE_MemoryCompressionMode_bits 1 #define GFX12_RENDER_SURFACE_STATE_MemoryCompressionMode_bits 1 #define GFX11_RENDER_SURFACE_STATE_MemoryCompressionMode_bits 1 #define GFX9_RENDER_SURFACE_STATE_MemoryCompressionMode_bits 1 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_MemoryCompressionMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_RENDER_SURFACE_STATE_MemoryCompressionMode_start 255 #define GFX12_RENDER_SURFACE_STATE_MemoryCompressionMode_start 255 #define GFX11_RENDER_SURFACE_STATE_MemoryCompressionMode_start 255 #define GFX9_RENDER_SURFACE_STATE_MemoryCompressionMode_start 255 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_MemoryCompressionMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 255; case 120: return 255; case 110: return 255; case 90: return 255; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Minimum Array Element */ #define GFX125_RENDER_SURFACE_STATE_MinimumArrayElement_bits 11 #define GFX12_RENDER_SURFACE_STATE_MinimumArrayElement_bits 11 #define GFX11_RENDER_SURFACE_STATE_MinimumArrayElement_bits 11 #define GFX9_RENDER_SURFACE_STATE_MinimumArrayElement_bits 11 #define GFX8_RENDER_SURFACE_STATE_MinimumArrayElement_bits 11 #define GFX75_RENDER_SURFACE_STATE_MinimumArrayElement_bits 11 #define GFX7_RENDER_SURFACE_STATE_MinimumArrayElement_bits 11 #define GFX6_RENDER_SURFACE_STATE_MinimumArrayElement_bits 11 #define GFX5_RENDER_SURFACE_STATE_MinimumArrayElement_bits 11 #define GFX45_RENDER_SURFACE_STATE_MinimumArrayElement_bits 11 #define GFX4_RENDER_SURFACE_STATE_MinimumArrayElement_bits 11 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_MinimumArrayElement_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 11; case 120: return 11; case 110: return 11; case 90: return 11; case 80: return 11; case 75: return 11; case 70: return 11; case 60: return 11; case 50: return 11; case 45: return 11; case 40: return 11; default: unreachable("Invalid hardware generation"); } } #define GFX125_RENDER_SURFACE_STATE_MinimumArrayElement_start 146 #define GFX12_RENDER_SURFACE_STATE_MinimumArrayElement_start 146 #define GFX11_RENDER_SURFACE_STATE_MinimumArrayElement_start 146 #define GFX9_RENDER_SURFACE_STATE_MinimumArrayElement_start 146 #define GFX8_RENDER_SURFACE_STATE_MinimumArrayElement_start 146 #define GFX75_RENDER_SURFACE_STATE_MinimumArrayElement_start 146 #define GFX7_RENDER_SURFACE_STATE_MinimumArrayElement_start 146 #define GFX6_RENDER_SURFACE_STATE_MinimumArrayElement_start 145 #define GFX5_RENDER_SURFACE_STATE_MinimumArrayElement_start 145 #define GFX45_RENDER_SURFACE_STATE_MinimumArrayElement_start 145 #define GFX4_RENDER_SURFACE_STATE_MinimumArrayElement_start 145 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_MinimumArrayElement_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 146; case 120: return 146; case 110: return 146; case 90: return 146; case 80: return 146; case 75: return 146; case 70: return 146; case 60: return 145; case 50: return 145; case 45: return 145; case 40: return 145; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Mip Tail Start LOD */ #define GFX125_RENDER_SURFACE_STATE_MipTailStartLOD_bits 4 #define GFX12_RENDER_SURFACE_STATE_MipTailStartLOD_bits 4 #define GFX11_RENDER_SURFACE_STATE_MipTailStartLOD_bits 4 #define GFX9_RENDER_SURFACE_STATE_MipTailStartLOD_bits 4 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_MipTailStartLOD_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_RENDER_SURFACE_STATE_MipTailStartLOD_start 168 #define GFX12_RENDER_SURFACE_STATE_MipTailStartLOD_start 168 #define GFX11_RENDER_SURFACE_STATE_MipTailStartLOD_start 168 #define GFX9_RENDER_SURFACE_STATE_MipTailStartLOD_start 168 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_MipTailStartLOD_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 168; case 120: return 168; case 110: return 168; case 90: return 168; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Multisample Position Palette Index */ #define GFX125_RENDER_SURFACE_STATE_MultisamplePositionPaletteIndex_bits 3 #define GFX12_RENDER_SURFACE_STATE_MultisamplePositionPaletteIndex_bits 3 #define GFX11_RENDER_SURFACE_STATE_MultisamplePositionPaletteIndex_bits 3 #define GFX9_RENDER_SURFACE_STATE_MultisamplePositionPaletteIndex_bits 3 #define GFX8_RENDER_SURFACE_STATE_MultisamplePositionPaletteIndex_bits 3 #define GFX75_RENDER_SURFACE_STATE_MultisamplePositionPaletteIndex_bits 3 #define GFX7_RENDER_SURFACE_STATE_MultisamplePositionPaletteIndex_bits 3 #define GFX6_RENDER_SURFACE_STATE_MultisamplePositionPaletteIndex_bits 3 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_MultisamplePositionPaletteIndex_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_RENDER_SURFACE_STATE_MultisamplePositionPaletteIndex_start 128 #define GFX12_RENDER_SURFACE_STATE_MultisamplePositionPaletteIndex_start 128 #define GFX11_RENDER_SURFACE_STATE_MultisamplePositionPaletteIndex_start 128 #define GFX9_RENDER_SURFACE_STATE_MultisamplePositionPaletteIndex_start 128 #define GFX8_RENDER_SURFACE_STATE_MultisamplePositionPaletteIndex_start 128 #define GFX75_RENDER_SURFACE_STATE_MultisamplePositionPaletteIndex_start 128 #define GFX7_RENDER_SURFACE_STATE_MultisamplePositionPaletteIndex_start 128 #define GFX6_RENDER_SURFACE_STATE_MultisamplePositionPaletteIndex_start 128 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_MultisamplePositionPaletteIndex_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 128; case 120: return 128; case 110: return 128; case 90: return 128; case 80: return 128; case 75: return 128; case 70: return 128; case 60: return 128; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Multisampled Surface Storage Format */ #define GFX125_RENDER_SURFACE_STATE_MultisampledSurfaceStorageFormat_bits 1 #define GFX12_RENDER_SURFACE_STATE_MultisampledSurfaceStorageFormat_bits 1 #define GFX11_RENDER_SURFACE_STATE_MultisampledSurfaceStorageFormat_bits 1 #define GFX9_RENDER_SURFACE_STATE_MultisampledSurfaceStorageFormat_bits 1 #define GFX8_RENDER_SURFACE_STATE_MultisampledSurfaceStorageFormat_bits 1 #define GFX75_RENDER_SURFACE_STATE_MultisampledSurfaceStorageFormat_bits 1 #define GFX7_RENDER_SURFACE_STATE_MultisampledSurfaceStorageFormat_bits 1 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_MultisampledSurfaceStorageFormat_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_RENDER_SURFACE_STATE_MultisampledSurfaceStorageFormat_start 134 #define GFX12_RENDER_SURFACE_STATE_MultisampledSurfaceStorageFormat_start 134 #define GFX11_RENDER_SURFACE_STATE_MultisampledSurfaceStorageFormat_start 134 #define GFX9_RENDER_SURFACE_STATE_MultisampledSurfaceStorageFormat_start 134 #define GFX8_RENDER_SURFACE_STATE_MultisampledSurfaceStorageFormat_start 134 #define GFX75_RENDER_SURFACE_STATE_MultisampledSurfaceStorageFormat_start 134 #define GFX7_RENDER_SURFACE_STATE_MultisampledSurfaceStorageFormat_start 134 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_MultisampledSurfaceStorageFormat_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 134; case 120: return 134; case 110: return 134; case 90: return 134; case 80: return 134; case 75: return 134; case 70: return 134; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Null Probing Enable */ #define GFX125_RENDER_SURFACE_STATE_NullProbingEnable_bits 1 #define GFX12_RENDER_SURFACE_STATE_NullProbingEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_NullProbingEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_RENDER_SURFACE_STATE_NullProbingEnable_start 114 #define GFX12_RENDER_SURFACE_STATE_NullProbingEnable_start 114 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_NullProbingEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 114; case 120: return 114; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Number of Multisamples */ #define GFX125_RENDER_SURFACE_STATE_NumberofMultisamples_bits 3 #define GFX12_RENDER_SURFACE_STATE_NumberofMultisamples_bits 3 #define GFX11_RENDER_SURFACE_STATE_NumberofMultisamples_bits 3 #define GFX9_RENDER_SURFACE_STATE_NumberofMultisamples_bits 3 #define GFX8_RENDER_SURFACE_STATE_NumberofMultisamples_bits 3 #define GFX75_RENDER_SURFACE_STATE_NumberofMultisamples_bits 3 #define GFX7_RENDER_SURFACE_STATE_NumberofMultisamples_bits 3 #define GFX6_RENDER_SURFACE_STATE_NumberofMultisamples_bits 3 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_NumberofMultisamples_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_RENDER_SURFACE_STATE_NumberofMultisamples_start 131 #define GFX12_RENDER_SURFACE_STATE_NumberofMultisamples_start 131 #define GFX11_RENDER_SURFACE_STATE_NumberofMultisamples_start 131 #define GFX9_RENDER_SURFACE_STATE_NumberofMultisamples_start 131 #define GFX8_RENDER_SURFACE_STATE_NumberofMultisamples_start 131 #define GFX75_RENDER_SURFACE_STATE_NumberofMultisamples_start 131 #define GFX7_RENDER_SURFACE_STATE_NumberofMultisamples_start 131 #define GFX6_RENDER_SURFACE_STATE_NumberofMultisamples_start 132 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_NumberofMultisamples_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 131; case 120: return 131; case 110: return 131; case 90: return 131; case 80: return 131; case 75: return 131; case 70: return 131; case 60: return 132; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Quilt Height */ #define GFX125_RENDER_SURFACE_STATE_QuiltHeight_bits 5 #define GFX12_RENDER_SURFACE_STATE_QuiltHeight_bits 5 #define GFX11_RENDER_SURFACE_STATE_QuiltHeight_bits 5 #define GFX9_RENDER_SURFACE_STATE_QuiltHeight_bits 5 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_QuiltHeight_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 5; case 110: return 5; case 90: return 5; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_RENDER_SURFACE_STATE_QuiltHeight_start 325 #define GFX12_RENDER_SURFACE_STATE_QuiltHeight_start 325 #define GFX11_RENDER_SURFACE_STATE_QuiltHeight_start 325 #define GFX9_RENDER_SURFACE_STATE_QuiltHeight_start 325 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_QuiltHeight_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 325; case 120: return 325; case 110: return 325; case 90: return 325; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Quilt Width */ #define GFX125_RENDER_SURFACE_STATE_QuiltWidth_bits 5 #define GFX12_RENDER_SURFACE_STATE_QuiltWidth_bits 5 #define GFX11_RENDER_SURFACE_STATE_QuiltWidth_bits 5 #define GFX9_RENDER_SURFACE_STATE_QuiltWidth_bits 5 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_QuiltWidth_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 5; case 110: return 5; case 90: return 5; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_RENDER_SURFACE_STATE_QuiltWidth_start 320 #define GFX12_RENDER_SURFACE_STATE_QuiltWidth_start 320 #define GFX11_RENDER_SURFACE_STATE_QuiltWidth_start 320 #define GFX9_RENDER_SURFACE_STATE_QuiltWidth_start 320 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_QuiltWidth_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 320; case 120: return 320; case 110: return 320; case 90: return 320; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Red Clear Color */ #define GFX11_RENDER_SURFACE_STATE_RedClearColor_bits 32 #define GFX9_RENDER_SURFACE_STATE_RedClearColor_bits 32 #define GFX8_RENDER_SURFACE_STATE_RedClearColor_bits 1 #define GFX75_RENDER_SURFACE_STATE_RedClearColor_bits 1 #define GFX7_RENDER_SURFACE_STATE_RedClearColor_bits 1 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_RedClearColor_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 32; case 90: return 32; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX11_RENDER_SURFACE_STATE_RedClearColor_start 384 #define GFX9_RENDER_SURFACE_STATE_RedClearColor_start 384 #define GFX8_RENDER_SURFACE_STATE_RedClearColor_start 255 #define GFX75_RENDER_SURFACE_STATE_RedClearColor_start 255 #define GFX7_RENDER_SURFACE_STATE_RedClearColor_start 255 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_RedClearColor_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 384; case 90: return 384; case 80: return 255; case 75: return 255; case 70: return 255; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Render Cache Read Write Mode */ #define GFX125_RENDER_SURFACE_STATE_RenderCacheReadWriteMode_bits 1 #define GFX12_RENDER_SURFACE_STATE_RenderCacheReadWriteMode_bits 1 #define GFX11_RENDER_SURFACE_STATE_RenderCacheReadWriteMode_bits 1 #define GFX9_RENDER_SURFACE_STATE_RenderCacheReadWriteMode_bits 1 #define GFX8_RENDER_SURFACE_STATE_RenderCacheReadWriteMode_bits 1 #define GFX75_RENDER_SURFACE_STATE_RenderCacheReadWriteMode_bits 1 #define GFX7_RENDER_SURFACE_STATE_RenderCacheReadWriteMode_bits 1 #define GFX6_RENDER_SURFACE_STATE_RenderCacheReadWriteMode_bits 1 #define GFX5_RENDER_SURFACE_STATE_RenderCacheReadWriteMode_bits 1 #define GFX45_RENDER_SURFACE_STATE_RenderCacheReadWriteMode_bits 1 #define GFX4_RENDER_SURFACE_STATE_RenderCacheReadWriteMode_bits 1 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_RenderCacheReadWriteMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX125_RENDER_SURFACE_STATE_RenderCacheReadWriteMode_start 8 #define GFX12_RENDER_SURFACE_STATE_RenderCacheReadWriteMode_start 8 #define GFX11_RENDER_SURFACE_STATE_RenderCacheReadWriteMode_start 8 #define GFX9_RENDER_SURFACE_STATE_RenderCacheReadWriteMode_start 8 #define GFX8_RENDER_SURFACE_STATE_RenderCacheReadWriteMode_start 8 #define GFX75_RENDER_SURFACE_STATE_RenderCacheReadWriteMode_start 8 #define GFX7_RENDER_SURFACE_STATE_RenderCacheReadWriteMode_start 8 #define GFX6_RENDER_SURFACE_STATE_RenderCacheReadWriteMode_start 8 #define GFX5_RENDER_SURFACE_STATE_RenderCacheReadWriteMode_start 8 #define GFX45_RENDER_SURFACE_STATE_RenderCacheReadWriteMode_start 8 #define GFX4_RENDER_SURFACE_STATE_RenderCacheReadWriteMode_start 8 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_RenderCacheReadWriteMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 8; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Render Compression Format */ #define GFX125_RENDER_SURFACE_STATE_RenderCompressionFormat_bits 5 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_RenderCompressionFormat_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_RENDER_SURFACE_STATE_RenderCompressionFormat_start 384 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_RenderCompressionFormat_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 384; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Render Target And Sample Unorm Rotation */ #define GFX125_RENDER_SURFACE_STATE_RenderTargetAndSampleUnormRotation_bits 2 #define GFX12_RENDER_SURFACE_STATE_RenderTargetAndSampleUnormRotation_bits 2 #define GFX11_RENDER_SURFACE_STATE_RenderTargetAndSampleUnormRotation_bits 2 #define GFX9_RENDER_SURFACE_STATE_RenderTargetAndSampleUnormRotation_bits 2 #define GFX8_RENDER_SURFACE_STATE_RenderTargetAndSampleUnormRotation_bits 2 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_RenderTargetAndSampleUnormRotation_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_RENDER_SURFACE_STATE_RenderTargetAndSampleUnormRotation_start 157 #define GFX12_RENDER_SURFACE_STATE_RenderTargetAndSampleUnormRotation_start 157 #define GFX11_RENDER_SURFACE_STATE_RenderTargetAndSampleUnormRotation_start 157 #define GFX9_RENDER_SURFACE_STATE_RenderTargetAndSampleUnormRotation_start 157 #define GFX8_RENDER_SURFACE_STATE_RenderTargetAndSampleUnormRotation_start 157 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_RenderTargetAndSampleUnormRotation_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 157; case 120: return 157; case 110: return 157; case 90: return 157; case 80: return 157; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Render Target Rotation */ #define GFX75_RENDER_SURFACE_STATE_RenderTargetRotation_bits 2 #define GFX7_RENDER_SURFACE_STATE_RenderTargetRotation_bits 2 #define GFX6_RENDER_SURFACE_STATE_RenderTargetRotation_bits 2 #define GFX5_RENDER_SURFACE_STATE_RenderTargetRotation_bits 2 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_RenderTargetRotation_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 2; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_RENDER_SURFACE_STATE_RenderTargetRotation_start 157 #define GFX7_RENDER_SURFACE_STATE_RenderTargetRotation_start 157 #define GFX6_RENDER_SURFACE_STATE_RenderTargetRotation_start 64 #define GFX5_RENDER_SURFACE_STATE_RenderTargetRotation_start 64 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_RenderTargetRotation_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 157; case 70: return 157; case 60: return 64; case 50: return 64; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Render Target View Extent */ #define GFX125_RENDER_SURFACE_STATE_RenderTargetViewExtent_bits 11 #define GFX12_RENDER_SURFACE_STATE_RenderTargetViewExtent_bits 11 #define GFX11_RENDER_SURFACE_STATE_RenderTargetViewExtent_bits 11 #define GFX9_RENDER_SURFACE_STATE_RenderTargetViewExtent_bits 11 #define GFX8_RENDER_SURFACE_STATE_RenderTargetViewExtent_bits 11 #define GFX75_RENDER_SURFACE_STATE_RenderTargetViewExtent_bits 11 #define GFX7_RENDER_SURFACE_STATE_RenderTargetViewExtent_bits 11 #define GFX6_RENDER_SURFACE_STATE_RenderTargetViewExtent_bits 9 #define GFX5_RENDER_SURFACE_STATE_RenderTargetViewExtent_bits 9 #define GFX45_RENDER_SURFACE_STATE_RenderTargetViewExtent_bits 9 #define GFX4_RENDER_SURFACE_STATE_RenderTargetViewExtent_bits 9 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_RenderTargetViewExtent_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 11; case 120: return 11; case 110: return 11; case 90: return 11; case 80: return 11; case 75: return 11; case 70: return 11; case 60: return 9; case 50: return 9; case 45: return 9; case 40: return 9; default: unreachable("Invalid hardware generation"); } } #define GFX125_RENDER_SURFACE_STATE_RenderTargetViewExtent_start 135 #define GFX12_RENDER_SURFACE_STATE_RenderTargetViewExtent_start 135 #define GFX11_RENDER_SURFACE_STATE_RenderTargetViewExtent_start 135 #define GFX9_RENDER_SURFACE_STATE_RenderTargetViewExtent_start 135 #define GFX8_RENDER_SURFACE_STATE_RenderTargetViewExtent_start 135 #define GFX75_RENDER_SURFACE_STATE_RenderTargetViewExtent_start 135 #define GFX7_RENDER_SURFACE_STATE_RenderTargetViewExtent_start 135 #define GFX6_RENDER_SURFACE_STATE_RenderTargetViewExtent_start 136 #define GFX5_RENDER_SURFACE_STATE_RenderTargetViewExtent_start 136 #define GFX45_RENDER_SURFACE_STATE_RenderTargetViewExtent_start 136 #define GFX4_RENDER_SURFACE_STATE_RenderTargetViewExtent_start 136 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_RenderTargetViewExtent_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 135; case 120: return 135; case 110: return 135; case 90: return 135; case 80: return 135; case 75: return 135; case 70: return 135; case 60: return 136; case 50: return 136; case 45: return 136; case 40: return 136; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Reserved: MBZ */ #define GFX75_RENDER_SURFACE_STATE_ReservedMBZ_bits 2 #define GFX7_RENDER_SURFACE_STATE_ReservedMBZ_bits 2 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_ReservedMBZ_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_RENDER_SURFACE_STATE_ReservedMBZ_start 222 #define GFX7_RENDER_SURFACE_STATE_ReservedMBZ_start 222 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_ReservedMBZ_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 222; case 70: return 222; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Resource Min LOD */ #define GFX125_RENDER_SURFACE_STATE_ResourceMinLOD_bits 12 #define GFX12_RENDER_SURFACE_STATE_ResourceMinLOD_bits 12 #define GFX11_RENDER_SURFACE_STATE_ResourceMinLOD_bits 12 #define GFX9_RENDER_SURFACE_STATE_ResourceMinLOD_bits 12 #define GFX8_RENDER_SURFACE_STATE_ResourceMinLOD_bits 12 #define GFX75_RENDER_SURFACE_STATE_ResourceMinLOD_bits 12 #define GFX7_RENDER_SURFACE_STATE_ResourceMinLOD_bits 12 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_ResourceMinLOD_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 12; case 120: return 12; case 110: return 12; case 90: return 12; case 80: return 12; case 75: return 12; case 70: return 12; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_RENDER_SURFACE_STATE_ResourceMinLOD_start 224 #define GFX12_RENDER_SURFACE_STATE_ResourceMinLOD_start 224 #define GFX11_RENDER_SURFACE_STATE_ResourceMinLOD_start 224 #define GFX9_RENDER_SURFACE_STATE_ResourceMinLOD_start 224 #define GFX8_RENDER_SURFACE_STATE_ResourceMinLOD_start 224 #define GFX75_RENDER_SURFACE_STATE_ResourceMinLOD_start 224 #define GFX7_RENDER_SURFACE_STATE_ResourceMinLOD_start 224 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_ResourceMinLOD_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 224; case 120: return 224; case 110: return 224; case 90: return 224; case 80: return 224; case 75: return 224; case 70: return 224; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Sample Tap Discard Disable */ #define GFX125_RENDER_SURFACE_STATE_SampleTapDiscardDisable_bits 1 #define GFX12_RENDER_SURFACE_STATE_SampleTapDiscardDisable_bits 1 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_SampleTapDiscardDisable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_RENDER_SURFACE_STATE_SampleTapDiscardDisable_start 47 #define GFX12_RENDER_SURFACE_STATE_SampleTapDiscardDisable_start 47 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_SampleTapDiscardDisable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 47; case 120: return 47; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Sampler L2 Bypass Mode Disable */ #define GFX125_RENDER_SURFACE_STATE_SamplerL2BypassModeDisable_bits 1 #define GFX12_RENDER_SURFACE_STATE_SamplerL2BypassModeDisable_bits 1 #define GFX11_RENDER_SURFACE_STATE_SamplerL2BypassModeDisable_bits 1 #define GFX9_RENDER_SURFACE_STATE_SamplerL2BypassModeDisable_bits 1 #define GFX8_RENDER_SURFACE_STATE_SamplerL2BypassModeDisable_bits 1 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_SamplerL2BypassModeDisable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_RENDER_SURFACE_STATE_SamplerL2BypassModeDisable_start 9 #define GFX12_RENDER_SURFACE_STATE_SamplerL2BypassModeDisable_start 9 #define GFX11_RENDER_SURFACE_STATE_SamplerL2BypassModeDisable_start 9 #define GFX9_RENDER_SURFACE_STATE_SamplerL2BypassModeDisable_start 9 #define GFX8_RENDER_SURFACE_STATE_SamplerL2BypassModeDisable_start 9 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_SamplerL2BypassModeDisable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 9; case 120: return 9; case 110: return 9; case 90: return 9; case 80: return 9; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Separate UV Plane Enable */ #define GFX125_RENDER_SURFACE_STATE_SeparateUVPlaneEnable_bits 1 #define GFX12_RENDER_SURFACE_STATE_SeparateUVPlaneEnable_bits 1 #define GFX11_RENDER_SURFACE_STATE_SeparateUVPlaneEnable_bits 1 #define GFX9_RENDER_SURFACE_STATE_SeparateUVPlaneEnable_bits 1 #define GFX8_RENDER_SURFACE_STATE_SeparateUVPlaneEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_SeparateUVPlaneEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_RENDER_SURFACE_STATE_SeparateUVPlaneEnable_start 223 #define GFX12_RENDER_SURFACE_STATE_SeparateUVPlaneEnable_start 223 #define GFX11_RENDER_SURFACE_STATE_SeparateUVPlaneEnable_start 223 #define GFX9_RENDER_SURFACE_STATE_SeparateUVPlaneEnable_start 223 #define GFX8_RENDER_SURFACE_STATE_SeparateUVPlaneEnable_start 223 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_SeparateUVPlaneEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 223; case 120: return 223; case 110: return 223; case 90: return 223; case 80: return 223; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Shader Channel Select Alpha */ #define GFX125_RENDER_SURFACE_STATE_ShaderChannelSelectAlpha_bits 3 #define GFX12_RENDER_SURFACE_STATE_ShaderChannelSelectAlpha_bits 3 #define GFX11_RENDER_SURFACE_STATE_ShaderChannelSelectAlpha_bits 3 #define GFX9_RENDER_SURFACE_STATE_ShaderChannelSelectAlpha_bits 3 #define GFX8_RENDER_SURFACE_STATE_ShaderChannelSelectAlpha_bits 3 #define GFX75_RENDER_SURFACE_STATE_ShaderChannelSelectAlpha_bits 3 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_ShaderChannelSelectAlpha_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_RENDER_SURFACE_STATE_ShaderChannelSelectAlpha_start 240 #define GFX12_RENDER_SURFACE_STATE_ShaderChannelSelectAlpha_start 240 #define GFX11_RENDER_SURFACE_STATE_ShaderChannelSelectAlpha_start 240 #define GFX9_RENDER_SURFACE_STATE_ShaderChannelSelectAlpha_start 240 #define GFX8_RENDER_SURFACE_STATE_ShaderChannelSelectAlpha_start 240 #define GFX75_RENDER_SURFACE_STATE_ShaderChannelSelectAlpha_start 240 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_ShaderChannelSelectAlpha_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 240; case 120: return 240; case 110: return 240; case 90: return 240; case 80: return 240; case 75: return 240; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Shader Channel Select Blue */ #define GFX125_RENDER_SURFACE_STATE_ShaderChannelSelectBlue_bits 3 #define GFX12_RENDER_SURFACE_STATE_ShaderChannelSelectBlue_bits 3 #define GFX11_RENDER_SURFACE_STATE_ShaderChannelSelectBlue_bits 3 #define GFX9_RENDER_SURFACE_STATE_ShaderChannelSelectBlue_bits 3 #define GFX8_RENDER_SURFACE_STATE_ShaderChannelSelectBlue_bits 3 #define GFX75_RENDER_SURFACE_STATE_ShaderChannelSelectBlue_bits 3 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_ShaderChannelSelectBlue_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_RENDER_SURFACE_STATE_ShaderChannelSelectBlue_start 243 #define GFX12_RENDER_SURFACE_STATE_ShaderChannelSelectBlue_start 243 #define GFX11_RENDER_SURFACE_STATE_ShaderChannelSelectBlue_start 243 #define GFX9_RENDER_SURFACE_STATE_ShaderChannelSelectBlue_start 243 #define GFX8_RENDER_SURFACE_STATE_ShaderChannelSelectBlue_start 243 #define GFX75_RENDER_SURFACE_STATE_ShaderChannelSelectBlue_start 243 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_ShaderChannelSelectBlue_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 243; case 120: return 243; case 110: return 243; case 90: return 243; case 80: return 243; case 75: return 243; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Shader Channel Select Green */ #define GFX125_RENDER_SURFACE_STATE_ShaderChannelSelectGreen_bits 3 #define GFX12_RENDER_SURFACE_STATE_ShaderChannelSelectGreen_bits 3 #define GFX11_RENDER_SURFACE_STATE_ShaderChannelSelectGreen_bits 3 #define GFX9_RENDER_SURFACE_STATE_ShaderChannelSelectGreen_bits 3 #define GFX8_RENDER_SURFACE_STATE_ShaderChannelSelectGreen_bits 3 #define GFX75_RENDER_SURFACE_STATE_ShaderChannelSelectGreen_bits 3 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_ShaderChannelSelectGreen_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_RENDER_SURFACE_STATE_ShaderChannelSelectGreen_start 246 #define GFX12_RENDER_SURFACE_STATE_ShaderChannelSelectGreen_start 246 #define GFX11_RENDER_SURFACE_STATE_ShaderChannelSelectGreen_start 246 #define GFX9_RENDER_SURFACE_STATE_ShaderChannelSelectGreen_start 246 #define GFX8_RENDER_SURFACE_STATE_ShaderChannelSelectGreen_start 246 #define GFX75_RENDER_SURFACE_STATE_ShaderChannelSelectGreen_start 246 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_ShaderChannelSelectGreen_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 246; case 120: return 246; case 110: return 246; case 90: return 246; case 80: return 246; case 75: return 246; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Shader Channel Select Red */ #define GFX125_RENDER_SURFACE_STATE_ShaderChannelSelectRed_bits 3 #define GFX12_RENDER_SURFACE_STATE_ShaderChannelSelectRed_bits 3 #define GFX11_RENDER_SURFACE_STATE_ShaderChannelSelectRed_bits 3 #define GFX9_RENDER_SURFACE_STATE_ShaderChannelSelectRed_bits 3 #define GFX8_RENDER_SURFACE_STATE_ShaderChannelSelectRed_bits 3 #define GFX75_RENDER_SURFACE_STATE_ShaderChannelSelectRed_bits 3 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_ShaderChannelSelectRed_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_RENDER_SURFACE_STATE_ShaderChannelSelectRed_start 249 #define GFX12_RENDER_SURFACE_STATE_ShaderChannelSelectRed_start 249 #define GFX11_RENDER_SURFACE_STATE_ShaderChannelSelectRed_start 249 #define GFX9_RENDER_SURFACE_STATE_ShaderChannelSelectRed_start 249 #define GFX8_RENDER_SURFACE_STATE_ShaderChannelSelectRed_start 249 #define GFX75_RENDER_SURFACE_STATE_ShaderChannelSelectRed_start 249 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_ShaderChannelSelectRed_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 249; case 120: return 249; case 110: return 249; case 90: return 249; case 80: return 249; case 75: return 249; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Standard Tiling Mode Extensions */ #define GFX125_RENDER_SURFACE_STATE_StandardTilingModeExtensions_bits 1 #define GFX12_RENDER_SURFACE_STATE_StandardTilingModeExtensions_bits 1 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_StandardTilingModeExtensions_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_RENDER_SURFACE_STATE_StandardTilingModeExtensions_start 115 #define GFX12_RENDER_SURFACE_STATE_StandardTilingModeExtensions_start 115 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_StandardTilingModeExtensions_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 115; case 120: return 115; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Strbuf Minimum Array Element */ #define GFX75_RENDER_SURFACE_STATE_StrbufMinimumArrayElement_bits 27 #define GFX7_RENDER_SURFACE_STATE_StrbufMinimumArrayElement_bits 27 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_StrbufMinimumArrayElement_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 27; case 70: return 27; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_RENDER_SURFACE_STATE_StrbufMinimumArrayElement_start 128 #define GFX7_RENDER_SURFACE_STATE_StrbufMinimumArrayElement_start 128 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_StrbufMinimumArrayElement_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 128; case 70: return 128; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Surface Array */ #define GFX125_RENDER_SURFACE_STATE_SurfaceArray_bits 1 #define GFX12_RENDER_SURFACE_STATE_SurfaceArray_bits 1 #define GFX11_RENDER_SURFACE_STATE_SurfaceArray_bits 1 #define GFX9_RENDER_SURFACE_STATE_SurfaceArray_bits 1 #define GFX8_RENDER_SURFACE_STATE_SurfaceArray_bits 1 #define GFX75_RENDER_SURFACE_STATE_SurfaceArray_bits 1 #define GFX7_RENDER_SURFACE_STATE_SurfaceArray_bits 1 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_SurfaceArray_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_RENDER_SURFACE_STATE_SurfaceArray_start 28 #define GFX12_RENDER_SURFACE_STATE_SurfaceArray_start 28 #define GFX11_RENDER_SURFACE_STATE_SurfaceArray_start 28 #define GFX9_RENDER_SURFACE_STATE_SurfaceArray_start 28 #define GFX8_RENDER_SURFACE_STATE_SurfaceArray_start 28 #define GFX75_RENDER_SURFACE_STATE_SurfaceArray_start 28 #define GFX7_RENDER_SURFACE_STATE_SurfaceArray_start 28 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_SurfaceArray_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 28; case 120: return 28; case 110: return 28; case 90: return 28; case 80: return 28; case 75: return 28; case 70: return 28; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Surface Array Spacing */ #define GFX75_RENDER_SURFACE_STATE_SurfaceArraySpacing_bits 1 #define GFX7_RENDER_SURFACE_STATE_SurfaceArraySpacing_bits 1 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_SurfaceArraySpacing_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_RENDER_SURFACE_STATE_SurfaceArraySpacing_start 10 #define GFX7_RENDER_SURFACE_STATE_SurfaceArraySpacing_start 10 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_SurfaceArraySpacing_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 10; case 70: return 10; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Surface Base Address */ #define GFX125_RENDER_SURFACE_STATE_SurfaceBaseAddress_bits 64 #define GFX12_RENDER_SURFACE_STATE_SurfaceBaseAddress_bits 64 #define GFX11_RENDER_SURFACE_STATE_SurfaceBaseAddress_bits 64 #define GFX9_RENDER_SURFACE_STATE_SurfaceBaseAddress_bits 64 #define GFX8_RENDER_SURFACE_STATE_SurfaceBaseAddress_bits 64 #define GFX75_RENDER_SURFACE_STATE_SurfaceBaseAddress_bits 32 #define GFX7_RENDER_SURFACE_STATE_SurfaceBaseAddress_bits 32 #define GFX6_RENDER_SURFACE_STATE_SurfaceBaseAddress_bits 32 #define GFX5_RENDER_SURFACE_STATE_SurfaceBaseAddress_bits 32 #define GFX45_RENDER_SURFACE_STATE_SurfaceBaseAddress_bits 32 #define GFX4_RENDER_SURFACE_STATE_SurfaceBaseAddress_bits 32 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_SurfaceBaseAddress_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 64; case 80: return 64; case 75: return 32; case 70: return 32; case 60: return 32; case 50: return 32; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } #define GFX125_RENDER_SURFACE_STATE_SurfaceBaseAddress_start 256 #define GFX12_RENDER_SURFACE_STATE_SurfaceBaseAddress_start 256 #define GFX11_RENDER_SURFACE_STATE_SurfaceBaseAddress_start 256 #define GFX9_RENDER_SURFACE_STATE_SurfaceBaseAddress_start 256 #define GFX8_RENDER_SURFACE_STATE_SurfaceBaseAddress_start 256 #define GFX75_RENDER_SURFACE_STATE_SurfaceBaseAddress_start 32 #define GFX7_RENDER_SURFACE_STATE_SurfaceBaseAddress_start 32 #define GFX6_RENDER_SURFACE_STATE_SurfaceBaseAddress_start 32 #define GFX5_RENDER_SURFACE_STATE_SurfaceBaseAddress_start 32 #define GFX45_RENDER_SURFACE_STATE_SurfaceBaseAddress_start 32 #define GFX4_RENDER_SURFACE_STATE_SurfaceBaseAddress_start 32 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_SurfaceBaseAddress_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 256; case 120: return 256; case 110: return 256; case 90: return 256; case 80: return 256; case 75: return 32; case 70: return 32; case 60: return 32; case 50: return 32; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Surface Format */ #define GFX125_RENDER_SURFACE_STATE_SurfaceFormat_bits 9 #define GFX12_RENDER_SURFACE_STATE_SurfaceFormat_bits 10 #define GFX11_RENDER_SURFACE_STATE_SurfaceFormat_bits 10 #define GFX9_RENDER_SURFACE_STATE_SurfaceFormat_bits 10 #define GFX8_RENDER_SURFACE_STATE_SurfaceFormat_bits 9 #define GFX75_RENDER_SURFACE_STATE_SurfaceFormat_bits 9 #define GFX7_RENDER_SURFACE_STATE_SurfaceFormat_bits 9 #define GFX6_RENDER_SURFACE_STATE_SurfaceFormat_bits 9 #define GFX5_RENDER_SURFACE_STATE_SurfaceFormat_bits 9 #define GFX45_RENDER_SURFACE_STATE_SurfaceFormat_bits 9 #define GFX4_RENDER_SURFACE_STATE_SurfaceFormat_bits 9 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_SurfaceFormat_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 9; case 120: return 10; case 110: return 10; case 90: return 10; case 80: return 9; case 75: return 9; case 70: return 9; case 60: return 9; case 50: return 9; case 45: return 9; case 40: return 9; default: unreachable("Invalid hardware generation"); } } #define GFX125_RENDER_SURFACE_STATE_SurfaceFormat_start 18 #define GFX12_RENDER_SURFACE_STATE_SurfaceFormat_start 18 #define GFX11_RENDER_SURFACE_STATE_SurfaceFormat_start 18 #define GFX9_RENDER_SURFACE_STATE_SurfaceFormat_start 18 #define GFX8_RENDER_SURFACE_STATE_SurfaceFormat_start 18 #define GFX75_RENDER_SURFACE_STATE_SurfaceFormat_start 18 #define GFX7_RENDER_SURFACE_STATE_SurfaceFormat_start 18 #define GFX6_RENDER_SURFACE_STATE_SurfaceFormat_start 18 #define GFX5_RENDER_SURFACE_STATE_SurfaceFormat_start 18 #define GFX45_RENDER_SURFACE_STATE_SurfaceFormat_start 18 #define GFX4_RENDER_SURFACE_STATE_SurfaceFormat_start 18 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_SurfaceFormat_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 18; case 120: return 18; case 110: return 18; case 90: return 18; case 80: return 18; case 75: return 18; case 70: return 18; case 60: return 18; case 50: return 18; case 45: return 18; case 40: return 18; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Surface Horizontal Alignment */ #define GFX125_RENDER_SURFACE_STATE_SurfaceHorizontalAlignment_bits 2 #define GFX12_RENDER_SURFACE_STATE_SurfaceHorizontalAlignment_bits 2 #define GFX11_RENDER_SURFACE_STATE_SurfaceHorizontalAlignment_bits 2 #define GFX9_RENDER_SURFACE_STATE_SurfaceHorizontalAlignment_bits 2 #define GFX8_RENDER_SURFACE_STATE_SurfaceHorizontalAlignment_bits 2 #define GFX75_RENDER_SURFACE_STATE_SurfaceHorizontalAlignment_bits 1 #define GFX7_RENDER_SURFACE_STATE_SurfaceHorizontalAlignment_bits 1 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_SurfaceHorizontalAlignment_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_RENDER_SURFACE_STATE_SurfaceHorizontalAlignment_start 14 #define GFX12_RENDER_SURFACE_STATE_SurfaceHorizontalAlignment_start 14 #define GFX11_RENDER_SURFACE_STATE_SurfaceHorizontalAlignment_start 14 #define GFX9_RENDER_SURFACE_STATE_SurfaceHorizontalAlignment_start 14 #define GFX8_RENDER_SURFACE_STATE_SurfaceHorizontalAlignment_start 14 #define GFX75_RENDER_SURFACE_STATE_SurfaceHorizontalAlignment_start 15 #define GFX7_RENDER_SURFACE_STATE_SurfaceHorizontalAlignment_start 15 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_SurfaceHorizontalAlignment_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 14; case 120: return 14; case 110: return 14; case 90: return 14; case 80: return 14; case 75: return 15; case 70: return 15; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Surface Min LOD */ #define GFX125_RENDER_SURFACE_STATE_SurfaceMinLOD_bits 4 #define GFX12_RENDER_SURFACE_STATE_SurfaceMinLOD_bits 4 #define GFX11_RENDER_SURFACE_STATE_SurfaceMinLOD_bits 4 #define GFX9_RENDER_SURFACE_STATE_SurfaceMinLOD_bits 4 #define GFX8_RENDER_SURFACE_STATE_SurfaceMinLOD_bits 4 #define GFX75_RENDER_SURFACE_STATE_SurfaceMinLOD_bits 4 #define GFX7_RENDER_SURFACE_STATE_SurfaceMinLOD_bits 4 #define GFX6_RENDER_SURFACE_STATE_SurfaceMinLOD_bits 4 #define GFX5_RENDER_SURFACE_STATE_SurfaceMinLOD_bits 4 #define GFX45_RENDER_SURFACE_STATE_SurfaceMinLOD_bits 4 #define GFX4_RENDER_SURFACE_STATE_SurfaceMinLOD_bits 4 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_SurfaceMinLOD_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 4; case 70: return 4; case 60: return 4; case 50: return 4; case 45: return 4; case 40: return 4; default: unreachable("Invalid hardware generation"); } } #define GFX125_RENDER_SURFACE_STATE_SurfaceMinLOD_start 164 #define GFX12_RENDER_SURFACE_STATE_SurfaceMinLOD_start 164 #define GFX11_RENDER_SURFACE_STATE_SurfaceMinLOD_start 164 #define GFX9_RENDER_SURFACE_STATE_SurfaceMinLOD_start 164 #define GFX8_RENDER_SURFACE_STATE_SurfaceMinLOD_start 164 #define GFX75_RENDER_SURFACE_STATE_SurfaceMinLOD_start 164 #define GFX7_RENDER_SURFACE_STATE_SurfaceMinLOD_start 164 #define GFX6_RENDER_SURFACE_STATE_SurfaceMinLOD_start 156 #define GFX5_RENDER_SURFACE_STATE_SurfaceMinLOD_start 156 #define GFX45_RENDER_SURFACE_STATE_SurfaceMinLOD_start 156 #define GFX4_RENDER_SURFACE_STATE_SurfaceMinLOD_start 156 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_SurfaceMinLOD_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 164; case 120: return 164; case 110: return 164; case 90: return 164; case 80: return 164; case 75: return 164; case 70: return 164; case 60: return 156; case 50: return 156; case 45: return 156; case 40: return 156; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Surface Pitch */ #define GFX125_RENDER_SURFACE_STATE_SurfacePitch_bits 18 #define GFX12_RENDER_SURFACE_STATE_SurfacePitch_bits 18 #define GFX11_RENDER_SURFACE_STATE_SurfacePitch_bits 18 #define GFX9_RENDER_SURFACE_STATE_SurfacePitch_bits 18 #define GFX8_RENDER_SURFACE_STATE_SurfacePitch_bits 18 #define GFX75_RENDER_SURFACE_STATE_SurfacePitch_bits 18 #define GFX7_RENDER_SURFACE_STATE_SurfacePitch_bits 18 #define GFX6_RENDER_SURFACE_STATE_SurfacePitch_bits 17 #define GFX5_RENDER_SURFACE_STATE_SurfacePitch_bits 17 #define GFX45_RENDER_SURFACE_STATE_SurfacePitch_bits 17 #define GFX4_RENDER_SURFACE_STATE_SurfacePitch_bits 17 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_SurfacePitch_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 18; case 120: return 18; case 110: return 18; case 90: return 18; case 80: return 18; case 75: return 18; case 70: return 18; case 60: return 17; case 50: return 17; case 45: return 17; case 40: return 17; default: unreachable("Invalid hardware generation"); } } #define GFX125_RENDER_SURFACE_STATE_SurfacePitch_start 96 #define GFX12_RENDER_SURFACE_STATE_SurfacePitch_start 96 #define GFX11_RENDER_SURFACE_STATE_SurfacePitch_start 96 #define GFX9_RENDER_SURFACE_STATE_SurfacePitch_start 96 #define GFX8_RENDER_SURFACE_STATE_SurfacePitch_start 96 #define GFX75_RENDER_SURFACE_STATE_SurfacePitch_start 96 #define GFX7_RENDER_SURFACE_STATE_SurfacePitch_start 96 #define GFX6_RENDER_SURFACE_STATE_SurfacePitch_start 99 #define GFX5_RENDER_SURFACE_STATE_SurfacePitch_start 99 #define GFX45_RENDER_SURFACE_STATE_SurfacePitch_start 99 #define GFX4_RENDER_SURFACE_STATE_SurfacePitch_start 99 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_SurfacePitch_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 96; case 120: return 96; case 110: return 96; case 90: return 96; case 80: return 96; case 75: return 96; case 70: return 96; case 60: return 99; case 50: return 99; case 45: return 99; case 40: return 99; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Surface QPitch */ #define GFX125_RENDER_SURFACE_STATE_SurfaceQPitch_bits 15 #define GFX12_RENDER_SURFACE_STATE_SurfaceQPitch_bits 15 #define GFX11_RENDER_SURFACE_STATE_SurfaceQPitch_bits 15 #define GFX9_RENDER_SURFACE_STATE_SurfaceQPitch_bits 15 #define GFX8_RENDER_SURFACE_STATE_SurfaceQPitch_bits 15 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_SurfaceQPitch_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 15; case 120: return 15; case 110: return 15; case 90: return 15; case 80: return 15; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_RENDER_SURFACE_STATE_SurfaceQPitch_start 32 #define GFX12_RENDER_SURFACE_STATE_SurfaceQPitch_start 32 #define GFX11_RENDER_SURFACE_STATE_SurfaceQPitch_start 32 #define GFX9_RENDER_SURFACE_STATE_SurfaceQPitch_start 32 #define GFX8_RENDER_SURFACE_STATE_SurfaceQPitch_start 32 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_SurfaceQPitch_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Surface Type */ #define GFX125_RENDER_SURFACE_STATE_SurfaceType_bits 3 #define GFX12_RENDER_SURFACE_STATE_SurfaceType_bits 3 #define GFX11_RENDER_SURFACE_STATE_SurfaceType_bits 3 #define GFX9_RENDER_SURFACE_STATE_SurfaceType_bits 3 #define GFX8_RENDER_SURFACE_STATE_SurfaceType_bits 3 #define GFX75_RENDER_SURFACE_STATE_SurfaceType_bits 3 #define GFX7_RENDER_SURFACE_STATE_SurfaceType_bits 3 #define GFX6_RENDER_SURFACE_STATE_SurfaceType_bits 3 #define GFX5_RENDER_SURFACE_STATE_SurfaceType_bits 3 #define GFX45_RENDER_SURFACE_STATE_SurfaceType_bits 3 #define GFX4_RENDER_SURFACE_STATE_SurfaceType_bits 3 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_SurfaceType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX125_RENDER_SURFACE_STATE_SurfaceType_start 29 #define GFX12_RENDER_SURFACE_STATE_SurfaceType_start 29 #define GFX11_RENDER_SURFACE_STATE_SurfaceType_start 29 #define GFX9_RENDER_SURFACE_STATE_SurfaceType_start 29 #define GFX8_RENDER_SURFACE_STATE_SurfaceType_start 29 #define GFX75_RENDER_SURFACE_STATE_SurfaceType_start 29 #define GFX7_RENDER_SURFACE_STATE_SurfaceType_start 29 #define GFX6_RENDER_SURFACE_STATE_SurfaceType_start 29 #define GFX5_RENDER_SURFACE_STATE_SurfaceType_start 29 #define GFX45_RENDER_SURFACE_STATE_SurfaceType_start 29 #define GFX4_RENDER_SURFACE_STATE_SurfaceType_start 29 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_SurfaceType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 29; case 50: return 29; case 45: return 29; case 40: return 29; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Surface Vertical Alignment */ #define GFX125_RENDER_SURFACE_STATE_SurfaceVerticalAlignment_bits 2 #define GFX12_RENDER_SURFACE_STATE_SurfaceVerticalAlignment_bits 2 #define GFX11_RENDER_SURFACE_STATE_SurfaceVerticalAlignment_bits 2 #define GFX9_RENDER_SURFACE_STATE_SurfaceVerticalAlignment_bits 2 #define GFX8_RENDER_SURFACE_STATE_SurfaceVerticalAlignment_bits 2 #define GFX75_RENDER_SURFACE_STATE_SurfaceVerticalAlignment_bits 2 #define GFX7_RENDER_SURFACE_STATE_SurfaceVerticalAlignment_bits 2 #define GFX6_RENDER_SURFACE_STATE_SurfaceVerticalAlignment_bits 1 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_SurfaceVerticalAlignment_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_RENDER_SURFACE_STATE_SurfaceVerticalAlignment_start 16 #define GFX12_RENDER_SURFACE_STATE_SurfaceVerticalAlignment_start 16 #define GFX11_RENDER_SURFACE_STATE_SurfaceVerticalAlignment_start 16 #define GFX9_RENDER_SURFACE_STATE_SurfaceVerticalAlignment_start 16 #define GFX8_RENDER_SURFACE_STATE_SurfaceVerticalAlignment_start 16 #define GFX75_RENDER_SURFACE_STATE_SurfaceVerticalAlignment_start 16 #define GFX7_RENDER_SURFACE_STATE_SurfaceVerticalAlignment_start 16 #define GFX6_RENDER_SURFACE_STATE_SurfaceVerticalAlignment_start 184 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_SurfaceVerticalAlignment_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 184; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Tile Address Mapping Mode */ #define GFX125_RENDER_SURFACE_STATE_TileAddressMappingMode_bits 1 #define GFX12_RENDER_SURFACE_STATE_TileAddressMappingMode_bits 1 #define GFX11_RENDER_SURFACE_STATE_TileAddressMappingMode_bits 1 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_TileAddressMappingMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_RENDER_SURFACE_STATE_TileAddressMappingMode_start 116 #define GFX12_RENDER_SURFACE_STATE_TileAddressMappingMode_start 116 #define GFX11_RENDER_SURFACE_STATE_TileAddressMappingMode_start 116 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_TileAddressMappingMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 116; case 120: return 116; case 110: return 116; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Tile Mode */ #define GFX125_RENDER_SURFACE_STATE_TileMode_bits 2 #define GFX12_RENDER_SURFACE_STATE_TileMode_bits 2 #define GFX11_RENDER_SURFACE_STATE_TileMode_bits 2 #define GFX9_RENDER_SURFACE_STATE_TileMode_bits 2 #define GFX8_RENDER_SURFACE_STATE_TileMode_bits 2 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_TileMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_RENDER_SURFACE_STATE_TileMode_start 12 #define GFX12_RENDER_SURFACE_STATE_TileMode_start 12 #define GFX11_RENDER_SURFACE_STATE_TileMode_start 12 #define GFX9_RENDER_SURFACE_STATE_TileMode_start 12 #define GFX8_RENDER_SURFACE_STATE_TileMode_start 12 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_TileMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 12; case 120: return 12; case 110: return 12; case 90: return 12; case 80: return 12; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Tile Walk */ #define GFX75_RENDER_SURFACE_STATE_TileWalk_bits 1 #define GFX7_RENDER_SURFACE_STATE_TileWalk_bits 1 #define GFX6_RENDER_SURFACE_STATE_TileWalk_bits 1 #define GFX5_RENDER_SURFACE_STATE_TileWalk_bits 1 #define GFX45_RENDER_SURFACE_STATE_TileWalk_bits 1 #define GFX4_RENDER_SURFACE_STATE_TileWalk_bits 1 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_TileWalk_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX75_RENDER_SURFACE_STATE_TileWalk_start 13 #define GFX7_RENDER_SURFACE_STATE_TileWalk_start 13 #define GFX6_RENDER_SURFACE_STATE_TileWalk_start 96 #define GFX5_RENDER_SURFACE_STATE_TileWalk_start 96 #define GFX45_RENDER_SURFACE_STATE_TileWalk_start 96 #define GFX4_RENDER_SURFACE_STATE_TileWalk_start 96 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_TileWalk_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 13; case 70: return 13; case 60: return 96; case 50: return 96; case 45: return 96; case 40: return 96; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Tiled Resource Mode */ #define GFX125_RENDER_SURFACE_STATE_TiledResourceMode_bits 2 #define GFX12_RENDER_SURFACE_STATE_TiledResourceMode_bits 2 #define GFX11_RENDER_SURFACE_STATE_TiledResourceMode_bits 2 #define GFX9_RENDER_SURFACE_STATE_TiledResourceMode_bits 2 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_TiledResourceMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_RENDER_SURFACE_STATE_TiledResourceMode_start 178 #define GFX12_RENDER_SURFACE_STATE_TiledResourceMode_start 178 #define GFX11_RENDER_SURFACE_STATE_TiledResourceMode_start 178 #define GFX9_RENDER_SURFACE_STATE_TiledResourceMode_start 178 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_TiledResourceMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 178; case 120: return 178; case 110: return 178; case 90: return 178; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Tiled Surface */ #define GFX75_RENDER_SURFACE_STATE_TiledSurface_bits 1 #define GFX7_RENDER_SURFACE_STATE_TiledSurface_bits 1 #define GFX6_RENDER_SURFACE_STATE_TiledSurface_bits 1 #define GFX5_RENDER_SURFACE_STATE_TiledSurface_bits 1 #define GFX45_RENDER_SURFACE_STATE_TiledSurface_bits 1 #define GFX4_RENDER_SURFACE_STATE_TiledSurface_bits 1 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_TiledSurface_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX75_RENDER_SURFACE_STATE_TiledSurface_start 14 #define GFX7_RENDER_SURFACE_STATE_TiledSurface_start 14 #define GFX6_RENDER_SURFACE_STATE_TiledSurface_start 97 #define GFX5_RENDER_SURFACE_STATE_TiledSurface_start 97 #define GFX45_RENDER_SURFACE_STATE_TiledSurface_start 97 #define GFX4_RENDER_SURFACE_STATE_TiledSurface_start 97 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_TiledSurface_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 14; case 70: return 14; case 60: return 97; case 50: return 97; case 45: return 97; case 40: return 97; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Vertical Line Stride */ #define GFX125_RENDER_SURFACE_STATE_VerticalLineStride_bits 1 #define GFX12_RENDER_SURFACE_STATE_VerticalLineStride_bits 1 #define GFX11_RENDER_SURFACE_STATE_VerticalLineStride_bits 1 #define GFX9_RENDER_SURFACE_STATE_VerticalLineStride_bits 1 #define GFX8_RENDER_SURFACE_STATE_VerticalLineStride_bits 1 #define GFX75_RENDER_SURFACE_STATE_VerticalLineStride_bits 1 #define GFX7_RENDER_SURFACE_STATE_VerticalLineStride_bits 1 #define GFX6_RENDER_SURFACE_STATE_VerticalLineStride_bits 1 #define GFX5_RENDER_SURFACE_STATE_VerticalLineStride_bits 1 #define GFX45_RENDER_SURFACE_STATE_VerticalLineStride_bits 1 #define GFX4_RENDER_SURFACE_STATE_VerticalLineStride_bits 1 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_VerticalLineStride_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX125_RENDER_SURFACE_STATE_VerticalLineStride_start 11 #define GFX12_RENDER_SURFACE_STATE_VerticalLineStride_start 11 #define GFX11_RENDER_SURFACE_STATE_VerticalLineStride_start 11 #define GFX9_RENDER_SURFACE_STATE_VerticalLineStride_start 11 #define GFX8_RENDER_SURFACE_STATE_VerticalLineStride_start 11 #define GFX75_RENDER_SURFACE_STATE_VerticalLineStride_start 12 #define GFX7_RENDER_SURFACE_STATE_VerticalLineStride_start 12 #define GFX6_RENDER_SURFACE_STATE_VerticalLineStride_start 12 #define GFX5_RENDER_SURFACE_STATE_VerticalLineStride_start 12 #define GFX45_RENDER_SURFACE_STATE_VerticalLineStride_start 12 #define GFX4_RENDER_SURFACE_STATE_VerticalLineStride_start 12 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_VerticalLineStride_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 11; case 120: return 11; case 110: return 11; case 90: return 11; case 80: return 11; case 75: return 12; case 70: return 12; case 60: return 12; case 50: return 12; case 45: return 12; case 40: return 12; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Vertical Line Stride Offset */ #define GFX125_RENDER_SURFACE_STATE_VerticalLineStrideOffset_bits 1 #define GFX12_RENDER_SURFACE_STATE_VerticalLineStrideOffset_bits 1 #define GFX11_RENDER_SURFACE_STATE_VerticalLineStrideOffset_bits 1 #define GFX9_RENDER_SURFACE_STATE_VerticalLineStrideOffset_bits 1 #define GFX8_RENDER_SURFACE_STATE_VerticalLineStrideOffset_bits 1 #define GFX75_RENDER_SURFACE_STATE_VerticalLineStrideOffset_bits 1 #define GFX7_RENDER_SURFACE_STATE_VerticalLineStrideOffset_bits 1 #define GFX6_RENDER_SURFACE_STATE_VerticalLineStrideOffset_bits 1 #define GFX5_RENDER_SURFACE_STATE_VerticalLineStrideOffset_bits 1 #define GFX45_RENDER_SURFACE_STATE_VerticalLineStrideOffset_bits 1 #define GFX4_RENDER_SURFACE_STATE_VerticalLineStrideOffset_bits 1 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_VerticalLineStrideOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX125_RENDER_SURFACE_STATE_VerticalLineStrideOffset_start 10 #define GFX12_RENDER_SURFACE_STATE_VerticalLineStrideOffset_start 10 #define GFX11_RENDER_SURFACE_STATE_VerticalLineStrideOffset_start 10 #define GFX9_RENDER_SURFACE_STATE_VerticalLineStrideOffset_start 10 #define GFX8_RENDER_SURFACE_STATE_VerticalLineStrideOffset_start 10 #define GFX75_RENDER_SURFACE_STATE_VerticalLineStrideOffset_start 11 #define GFX7_RENDER_SURFACE_STATE_VerticalLineStrideOffset_start 11 #define GFX6_RENDER_SURFACE_STATE_VerticalLineStrideOffset_start 11 #define GFX5_RENDER_SURFACE_STATE_VerticalLineStrideOffset_start 11 #define GFX45_RENDER_SURFACE_STATE_VerticalLineStrideOffset_start 11 #define GFX4_RENDER_SURFACE_STATE_VerticalLineStrideOffset_start 11 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_VerticalLineStrideOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 10; case 120: return 10; case 110: return 10; case 90: return 10; case 80: return 10; case 75: return 11; case 70: return 11; case 60: return 11; case 50: return 11; case 45: return 11; case 40: return 11; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Width */ #define GFX125_RENDER_SURFACE_STATE_Width_bits 14 #define GFX12_RENDER_SURFACE_STATE_Width_bits 14 #define GFX11_RENDER_SURFACE_STATE_Width_bits 14 #define GFX9_RENDER_SURFACE_STATE_Width_bits 14 #define GFX8_RENDER_SURFACE_STATE_Width_bits 14 #define GFX75_RENDER_SURFACE_STATE_Width_bits 14 #define GFX7_RENDER_SURFACE_STATE_Width_bits 14 #define GFX6_RENDER_SURFACE_STATE_Width_bits 13 #define GFX5_RENDER_SURFACE_STATE_Width_bits 13 #define GFX45_RENDER_SURFACE_STATE_Width_bits 13 #define GFX4_RENDER_SURFACE_STATE_Width_bits 13 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_Width_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 14; case 120: return 14; case 110: return 14; case 90: return 14; case 80: return 14; case 75: return 14; case 70: return 14; case 60: return 13; case 50: return 13; case 45: return 13; case 40: return 13; default: unreachable("Invalid hardware generation"); } } #define GFX125_RENDER_SURFACE_STATE_Width_start 64 #define GFX12_RENDER_SURFACE_STATE_Width_start 64 #define GFX11_RENDER_SURFACE_STATE_Width_start 64 #define GFX9_RENDER_SURFACE_STATE_Width_start 64 #define GFX8_RENDER_SURFACE_STATE_Width_start 64 #define GFX75_RENDER_SURFACE_STATE_Width_start 64 #define GFX7_RENDER_SURFACE_STATE_Width_start 64 #define GFX6_RENDER_SURFACE_STATE_Width_start 70 #define GFX5_RENDER_SURFACE_STATE_Width_start 70 #define GFX45_RENDER_SURFACE_STATE_Width_start 70 #define GFX4_RENDER_SURFACE_STATE_Width_start 70 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_Width_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 64; case 80: return 64; case 75: return 64; case 70: return 64; case 60: return 70; case 50: return 70; case 45: return 70; case 40: return 70; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::X Offset */ #define GFX125_RENDER_SURFACE_STATE_XOffset_bits 7 #define GFX12_RENDER_SURFACE_STATE_XOffset_bits 7 #define GFX11_RENDER_SURFACE_STATE_XOffset_bits 7 #define GFX9_RENDER_SURFACE_STATE_XOffset_bits 7 #define GFX8_RENDER_SURFACE_STATE_XOffset_bits 7 #define GFX75_RENDER_SURFACE_STATE_XOffset_bits 7 #define GFX7_RENDER_SURFACE_STATE_XOffset_bits 7 #define GFX6_RENDER_SURFACE_STATE_XOffset_bits 7 #define GFX5_RENDER_SURFACE_STATE_XOffset_bits 7 #define GFX45_RENDER_SURFACE_STATE_XOffset_bits 7 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_XOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 7; case 120: return 7; case 110: return 7; case 90: return 7; case 80: return 7; case 75: return 7; case 70: return 7; case 60: return 7; case 50: return 7; case 45: return 7; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_RENDER_SURFACE_STATE_XOffset_start 185 #define GFX12_RENDER_SURFACE_STATE_XOffset_start 185 #define GFX11_RENDER_SURFACE_STATE_XOffset_start 185 #define GFX9_RENDER_SURFACE_STATE_XOffset_start 185 #define GFX8_RENDER_SURFACE_STATE_XOffset_start 185 #define GFX75_RENDER_SURFACE_STATE_XOffset_start 185 #define GFX7_RENDER_SURFACE_STATE_XOffset_start 185 #define GFX6_RENDER_SURFACE_STATE_XOffset_start 185 #define GFX5_RENDER_SURFACE_STATE_XOffset_start 185 #define GFX45_RENDER_SURFACE_STATE_XOffset_start 185 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_XOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 185; case 120: return 185; case 110: return 185; case 90: return 185; case 80: return 185; case 75: return 185; case 70: return 185; case 60: return 185; case 50: return 185; case 45: return 185; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::X Offset for UV Plane */ #define GFX75_RENDER_SURFACE_STATE_XOffsetforUVPlane_bits 14 #define GFX7_RENDER_SURFACE_STATE_XOffsetforUVPlane_bits 14 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_XOffsetforUVPlane_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 14; case 70: return 14; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_RENDER_SURFACE_STATE_XOffsetforUVPlane_start 208 #define GFX7_RENDER_SURFACE_STATE_XOffsetforUVPlane_start 208 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_XOffsetforUVPlane_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 208; case 70: return 208; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::X Offset for U or UV Plane */ #define GFX125_RENDER_SURFACE_STATE_XOffsetforUorUVPlane_bits 14 #define GFX12_RENDER_SURFACE_STATE_XOffsetforUorUVPlane_bits 14 #define GFX11_RENDER_SURFACE_STATE_XOffsetforUorUVPlane_bits 14 #define GFX9_RENDER_SURFACE_STATE_XOffsetforUorUVPlane_bits 14 #define GFX8_RENDER_SURFACE_STATE_XOffsetforUorUVPlane_bits 14 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_XOffsetforUorUVPlane_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 14; case 120: return 14; case 110: return 14; case 90: return 14; case 80: return 14; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_RENDER_SURFACE_STATE_XOffsetforUorUVPlane_start 208 #define GFX12_RENDER_SURFACE_STATE_XOffsetforUorUVPlane_start 208 #define GFX11_RENDER_SURFACE_STATE_XOffsetforUorUVPlane_start 208 #define GFX9_RENDER_SURFACE_STATE_XOffsetforUorUVPlane_start 208 #define GFX8_RENDER_SURFACE_STATE_XOffsetforUorUVPlane_start 208 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_XOffsetforUorUVPlane_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 208; case 120: return 208; case 110: return 208; case 90: return 208; case 80: return 208; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::X Offset for V Plane */ #define GFX11_RENDER_SURFACE_STATE_XOffsetforVPlane_bits 14 #define GFX9_RENDER_SURFACE_STATE_XOffsetforVPlane_bits 14 #define GFX8_RENDER_SURFACE_STATE_XOffsetforVPlane_bits 14 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_XOffsetforVPlane_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 14; case 90: return 14; case 80: return 14; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX11_RENDER_SURFACE_STATE_XOffsetforVPlane_start 368 #define GFX9_RENDER_SURFACE_STATE_XOffsetforVPlane_start 368 #define GFX8_RENDER_SURFACE_STATE_XOffsetforVPlane_start 368 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_XOffsetforVPlane_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 368; case 90: return 368; case 80: return 368; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Y Offset */ #define GFX125_RENDER_SURFACE_STATE_YOffset_bits 3 #define GFX12_RENDER_SURFACE_STATE_YOffset_bits 3 #define GFX11_RENDER_SURFACE_STATE_YOffset_bits 3 #define GFX9_RENDER_SURFACE_STATE_YOffset_bits 3 #define GFX8_RENDER_SURFACE_STATE_YOffset_bits 3 #define GFX75_RENDER_SURFACE_STATE_YOffset_bits 4 #define GFX7_RENDER_SURFACE_STATE_YOffset_bits 4 #define GFX6_RENDER_SURFACE_STATE_YOffset_bits 4 #define GFX5_RENDER_SURFACE_STATE_YOffset_bits 4 #define GFX45_RENDER_SURFACE_STATE_YOffset_bits 4 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_YOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 4; case 70: return 4; case 60: return 4; case 50: return 4; case 45: return 4; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_RENDER_SURFACE_STATE_YOffset_start 181 #define GFX12_RENDER_SURFACE_STATE_YOffset_start 181 #define GFX11_RENDER_SURFACE_STATE_YOffset_start 181 #define GFX9_RENDER_SURFACE_STATE_YOffset_start 181 #define GFX8_RENDER_SURFACE_STATE_YOffset_start 181 #define GFX75_RENDER_SURFACE_STATE_YOffset_start 180 #define GFX7_RENDER_SURFACE_STATE_YOffset_start 180 #define GFX6_RENDER_SURFACE_STATE_YOffset_start 180 #define GFX5_RENDER_SURFACE_STATE_YOffset_start 180 #define GFX45_RENDER_SURFACE_STATE_YOffset_start 180 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_YOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 181; case 120: return 181; case 110: return 181; case 90: return 181; case 80: return 181; case 75: return 180; case 70: return 180; case 60: return 180; case 50: return 180; case 45: return 180; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Y Offset for UV Plane */ #define GFX75_RENDER_SURFACE_STATE_YOffsetforUVPlane_bits 14 #define GFX7_RENDER_SURFACE_STATE_YOffsetforUVPlane_bits 14 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_YOffsetforUVPlane_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 14; case 70: return 14; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_RENDER_SURFACE_STATE_YOffsetforUVPlane_start 192 #define GFX7_RENDER_SURFACE_STATE_YOffsetforUVPlane_start 192 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_YOffsetforUVPlane_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 192; case 70: return 192; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Y Offset for U or UV Plane */ #define GFX125_RENDER_SURFACE_STATE_YOffsetforUorUVPlane_bits 14 #define GFX12_RENDER_SURFACE_STATE_YOffsetforUorUVPlane_bits 14 #define GFX11_RENDER_SURFACE_STATE_YOffsetforUorUVPlane_bits 14 #define GFX9_RENDER_SURFACE_STATE_YOffsetforUorUVPlane_bits 14 #define GFX8_RENDER_SURFACE_STATE_YOffsetforUorUVPlane_bits 14 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_YOffsetforUorUVPlane_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 14; case 120: return 14; case 110: return 14; case 90: return 14; case 80: return 14; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_RENDER_SURFACE_STATE_YOffsetforUorUVPlane_start 192 #define GFX12_RENDER_SURFACE_STATE_YOffsetforUorUVPlane_start 192 #define GFX11_RENDER_SURFACE_STATE_YOffsetforUorUVPlane_start 192 #define GFX9_RENDER_SURFACE_STATE_YOffsetforUorUVPlane_start 192 #define GFX8_RENDER_SURFACE_STATE_YOffsetforUorUVPlane_start 192 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_YOffsetforUorUVPlane_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 192; case 120: return 192; case 110: return 192; case 90: return 192; case 80: return 192; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::Y Offset for V Plane */ #define GFX11_RENDER_SURFACE_STATE_YOffsetforVPlane_bits 14 #define GFX9_RENDER_SURFACE_STATE_YOffsetforVPlane_bits 14 #define GFX8_RENDER_SURFACE_STATE_YOffsetforVPlane_bits 14 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_YOffsetforVPlane_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 14; case 90: return 14; case 80: return 14; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX11_RENDER_SURFACE_STATE_YOffsetforVPlane_start 352 #define GFX9_RENDER_SURFACE_STATE_YOffsetforVPlane_start 352 #define GFX8_RENDER_SURFACE_STATE_YOffsetforVPlane_start 352 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_YOffsetforVPlane_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 352; case 90: return 352; case 80: return 352; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RENDER_SURFACE_STATE::YUV Interpolation Enable */ #define GFX125_RENDER_SURFACE_STATE_YUVInterpolationEnable_bits 1 #define GFX12_RENDER_SURFACE_STATE_YUVInterpolationEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_YUVInterpolationEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_RENDER_SURFACE_STATE_YUVInterpolationEnable_start 207 #define GFX12_RENDER_SURFACE_STATE_YUVInterpolationEnable_start 207 static inline uint32_t ATTRIBUTE_PURE RENDER_SURFACE_STATE_YUVInterpolationEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 207; case 120: return 207; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* ROUNDINGPRECISIONTABLE_3_BITS */ #define GFX125_ROUNDINGPRECISIONTABLE_3_BITS_length 1 #define GFX12_ROUNDINGPRECISIONTABLE_3_BITS_length 1 #define GFX11_ROUNDINGPRECISIONTABLE_3_BITS_length 1 #define GFX9_ROUNDINGPRECISIONTABLE_3_BITS_length 1 static inline uint32_t ATTRIBUTE_PURE ROUNDINGPRECISIONTABLE_3_BITS_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* ROUNDINGPRECISIONTABLE_3_BITS::Rounding Precision */ #define GFX125_ROUNDINGPRECISIONTABLE_3_BITS_RoundingPrecision_bits 3 #define GFX12_ROUNDINGPRECISIONTABLE_3_BITS_RoundingPrecision_bits 3 #define GFX11_ROUNDINGPRECISIONTABLE_3_BITS_RoundingPrecision_bits 3 #define GFX9_ROUNDINGPRECISIONTABLE_3_BITS_RoundingPrecision_bits 3 static inline uint32_t ATTRIBUTE_PURE ROUNDINGPRECISIONTABLE_3_BITS_RoundingPrecision_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_ROUNDINGPRECISIONTABLE_3_BITS_RoundingPrecision_start 0 #define GFX12_ROUNDINGPRECISIONTABLE_3_BITS_RoundingPrecision_start 0 #define GFX11_ROUNDINGPRECISIONTABLE_3_BITS_RoundingPrecision_start 0 #define GFX9_ROUNDINGPRECISIONTABLE_3_BITS_RoundingPrecision_start 0 static inline uint32_t ATTRIBUTE_PURE ROUNDINGPRECISIONTABLE_3_BITS_RoundingPrecision_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* ROW_INSTDONE */ #define GFX125_ROW_INSTDONE_length 1 #define GFX12_ROW_INSTDONE_length 1 #define GFX11_ROW_INSTDONE_length 1 #define GFX9_ROW_INSTDONE_length 1 #define GFX8_ROW_INSTDONE_length 1 #define GFX75_ROW_INSTDONE_length 1 #define GFX7_ROW_INSTDONE_length 1 static inline uint32_t ATTRIBUTE_PURE ROW_INSTDONE_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* ROW_INSTDONE::BC Done */ #define GFX125_ROW_INSTDONE_BCDone_bits 1 #define GFX12_ROW_INSTDONE_BCDone_bits 1 #define GFX11_ROW_INSTDONE_BCDone_bits 1 #define GFX9_ROW_INSTDONE_BCDone_bits 1 #define GFX8_ROW_INSTDONE_BCDone_bits 1 #define GFX75_ROW_INSTDONE_BCDone_bits 1 #define GFX7_ROW_INSTDONE_BCDone_bits 1 static inline uint32_t ATTRIBUTE_PURE ROW_INSTDONE_BCDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_ROW_INSTDONE_BCDone_start 0 #define GFX12_ROW_INSTDONE_BCDone_start 0 #define GFX11_ROW_INSTDONE_BCDone_start 0 #define GFX9_ROW_INSTDONE_BCDone_start 0 #define GFX8_ROW_INSTDONE_BCDone_start 0 #define GFX75_ROW_INSTDONE_BCDone_start 0 #define GFX7_ROW_INSTDONE_BCDone_start 0 static inline uint32_t ATTRIBUTE_PURE ROW_INSTDONE_BCDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* ROW_INSTDONE::BTD DONE COMPUTE */ #define GFX125_ROW_INSTDONE_BTDDONECOMPUTE_bits 1 static inline uint32_t ATTRIBUTE_PURE ROW_INSTDONE_BTDDONECOMPUTE_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_ROW_INSTDONE_BTDDONECOMPUTE_start 20 static inline uint32_t ATTRIBUTE_PURE ROW_INSTDONE_BTDDONECOMPUTE_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 20; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* ROW_INSTDONE::BTD DONE RENDER */ #define GFX125_ROW_INSTDONE_BTDDONERENDER_bits 1 static inline uint32_t ATTRIBUTE_PURE ROW_INSTDONE_BTDDONERENDER_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_ROW_INSTDONE_BTDDONERENDER_start 13 static inline uint32_t ATTRIBUTE_PURE ROW_INSTDONE_BTDDONERENDER_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 13; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* ROW_INSTDONE::CPSS Done */ #define GFX125_ROW_INSTDONE_CPSSDone_bits 1 #define GFX12_ROW_INSTDONE_CPSSDone_bits 1 static inline uint32_t ATTRIBUTE_PURE ROW_INSTDONE_CPSSDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_ROW_INSTDONE_CPSSDone_start 4 #define GFX12_ROW_INSTDONE_CPSSDone_start 4 static inline uint32_t ATTRIBUTE_PURE ROW_INSTDONE_CPSSDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* ROW_INSTDONE::DAPR Done */ #define GFX125_ROW_INSTDONE_DAPRDone_bits 1 #define GFX12_ROW_INSTDONE_DAPRDone_bits 1 #define GFX11_ROW_INSTDONE_DAPRDone_bits 1 #define GFX9_ROW_INSTDONE_DAPRDone_bits 1 #define GFX8_ROW_INSTDONE_DAPRDone_bits 1 #define GFX75_ROW_INSTDONE_DAPRDone_bits 1 #define GFX7_ROW_INSTDONE_DAPRDone_bits 1 static inline uint32_t ATTRIBUTE_PURE ROW_INSTDONE_DAPRDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_ROW_INSTDONE_DAPRDone_start 3 #define GFX12_ROW_INSTDONE_DAPRDone_start 3 #define GFX11_ROW_INSTDONE_DAPRDone_start 3 #define GFX9_ROW_INSTDONE_DAPRDone_start 3 #define GFX8_ROW_INSTDONE_DAPRDone_start 3 #define GFX75_ROW_INSTDONE_DAPRDone_start 3 #define GFX7_ROW_INSTDONE_DAPRDone_start 3 static inline uint32_t ATTRIBUTE_PURE ROW_INSTDONE_DAPRDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* ROW_INSTDONE::DC Done */ #define GFX75_ROW_INSTDONE_DCDone_bits 1 #define GFX7_ROW_INSTDONE_DCDone_bits 1 static inline uint32_t ATTRIBUTE_PURE ROW_INSTDONE_DCDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_ROW_INSTDONE_DCDone_start 2 #define GFX7_ROW_INSTDONE_DCDone_start 2 static inline uint32_t ATTRIBUTE_PURE ROW_INSTDONE_DCDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* ROW_INSTDONE::EU00 Done SS0 */ #define GFX125_ROW_INSTDONE_EU00DoneSS0_bits 1 #define GFX12_ROW_INSTDONE_EU00DoneSS0_bits 1 #define GFX11_ROW_INSTDONE_EU00DoneSS0_bits 1 #define GFX9_ROW_INSTDONE_EU00DoneSS0_bits 1 #define GFX8_ROW_INSTDONE_EU00DoneSS0_bits 1 #define GFX75_ROW_INSTDONE_EU00DoneSS0_bits 1 #define GFX7_ROW_INSTDONE_EU00DoneSS0_bits 1 static inline uint32_t ATTRIBUTE_PURE ROW_INSTDONE_EU00DoneSS0_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_ROW_INSTDONE_EU00DoneSS0_start 16 #define GFX12_ROW_INSTDONE_EU00DoneSS0_start 16 #define GFX11_ROW_INSTDONE_EU00DoneSS0_start 16 #define GFX9_ROW_INSTDONE_EU00DoneSS0_start 16 #define GFX8_ROW_INSTDONE_EU00DoneSS0_start 16 #define GFX75_ROW_INSTDONE_EU00DoneSS0_start 16 #define GFX7_ROW_INSTDONE_EU00DoneSS0_start 16 static inline uint32_t ATTRIBUTE_PURE ROW_INSTDONE_EU00DoneSS0_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* ROW_INSTDONE::EU00 done SS1 */ #define GFX125_ROW_INSTDONE_EU00doneSS1_bits 1 #define GFX12_ROW_INSTDONE_EU00doneSS1_bits 1 static inline uint32_t ATTRIBUTE_PURE ROW_INSTDONE_EU00doneSS1_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_ROW_INSTDONE_EU00doneSS1_start 7 #define GFX12_ROW_INSTDONE_EU00doneSS1_start 7 static inline uint32_t ATTRIBUTE_PURE ROW_INSTDONE_EU00doneSS1_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 7; case 120: return 7; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* ROW_INSTDONE::EU01 Done SS0 */ #define GFX125_ROW_INSTDONE_EU01DoneSS0_bits 1 #define GFX12_ROW_INSTDONE_EU01DoneSS0_bits 1 #define GFX11_ROW_INSTDONE_EU01DoneSS0_bits 1 #define GFX9_ROW_INSTDONE_EU01DoneSS0_bits 1 #define GFX8_ROW_INSTDONE_EU01DoneSS0_bits 1 #define GFX75_ROW_INSTDONE_EU01DoneSS0_bits 1 #define GFX7_ROW_INSTDONE_EU01DoneSS0_bits 1 static inline uint32_t ATTRIBUTE_PURE ROW_INSTDONE_EU01DoneSS0_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_ROW_INSTDONE_EU01DoneSS0_start 17 #define GFX12_ROW_INSTDONE_EU01DoneSS0_start 17 #define GFX11_ROW_INSTDONE_EU01DoneSS0_start 17 #define GFX9_ROW_INSTDONE_EU01DoneSS0_start 17 #define GFX8_ROW_INSTDONE_EU01DoneSS0_start 17 #define GFX75_ROW_INSTDONE_EU01DoneSS0_start 17 #define GFX7_ROW_INSTDONE_EU01DoneSS0_start 17 static inline uint32_t ATTRIBUTE_PURE ROW_INSTDONE_EU01DoneSS0_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 17; case 120: return 17; case 110: return 17; case 90: return 17; case 80: return 17; case 75: return 17; case 70: return 17; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* ROW_INSTDONE::EU01 done SS1 */ #define GFX125_ROW_INSTDONE_EU01doneSS1_bits 1 #define GFX12_ROW_INSTDONE_EU01doneSS1_bits 1 static inline uint32_t ATTRIBUTE_PURE ROW_INSTDONE_EU01doneSS1_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_ROW_INSTDONE_EU01doneSS1_start 8 #define GFX12_ROW_INSTDONE_EU01doneSS1_start 8 static inline uint32_t ATTRIBUTE_PURE ROW_INSTDONE_EU01doneSS1_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* ROW_INSTDONE::EU02 Done SS0 */ #define GFX125_ROW_INSTDONE_EU02DoneSS0_bits 1 #define GFX12_ROW_INSTDONE_EU02DoneSS0_bits 1 #define GFX11_ROW_INSTDONE_EU02DoneSS0_bits 1 #define GFX9_ROW_INSTDONE_EU02DoneSS0_bits 1 #define GFX8_ROW_INSTDONE_EU02DoneSS0_bits 1 #define GFX75_ROW_INSTDONE_EU02DoneSS0_bits 1 #define GFX7_ROW_INSTDONE_EU02DoneSS0_bits 1 static inline uint32_t ATTRIBUTE_PURE ROW_INSTDONE_EU02DoneSS0_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_ROW_INSTDONE_EU02DoneSS0_start 18 #define GFX12_ROW_INSTDONE_EU02DoneSS0_start 18 #define GFX11_ROW_INSTDONE_EU02DoneSS0_start 18 #define GFX9_ROW_INSTDONE_EU02DoneSS0_start 18 #define GFX8_ROW_INSTDONE_EU02DoneSS0_start 18 #define GFX75_ROW_INSTDONE_EU02DoneSS0_start 18 #define GFX7_ROW_INSTDONE_EU02DoneSS0_start 18 static inline uint32_t ATTRIBUTE_PURE ROW_INSTDONE_EU02DoneSS0_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 18; case 120: return 18; case 110: return 18; case 90: return 18; case 80: return 18; case 75: return 18; case 70: return 18; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* ROW_INSTDONE::EU02 done SS1 */ #define GFX125_ROW_INSTDONE_EU02doneSS1_bits 1 #define GFX12_ROW_INSTDONE_EU02doneSS1_bits 1 static inline uint32_t ATTRIBUTE_PURE ROW_INSTDONE_EU02doneSS1_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_ROW_INSTDONE_EU02doneSS1_start 9 #define GFX12_ROW_INSTDONE_EU02doneSS1_start 9 static inline uint32_t ATTRIBUTE_PURE ROW_INSTDONE_EU02doneSS1_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 9; case 120: return 9; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* ROW_INSTDONE::EU03 Done SS0 */ #define GFX125_ROW_INSTDONE_EU03DoneSS0_bits 1 #define GFX12_ROW_INSTDONE_EU03DoneSS0_bits 1 #define GFX11_ROW_INSTDONE_EU03DoneSS0_bits 1 #define GFX9_ROW_INSTDONE_EU03DoneSS0_bits 1 #define GFX8_ROW_INSTDONE_EU03DoneSS0_bits 1 #define GFX75_ROW_INSTDONE_EU03DoneSS0_bits 1 #define GFX7_ROW_INSTDONE_EU03DoneSS0_bits 1 static inline uint32_t ATTRIBUTE_PURE ROW_INSTDONE_EU03DoneSS0_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_ROW_INSTDONE_EU03DoneSS0_start 19 #define GFX12_ROW_INSTDONE_EU03DoneSS0_start 19 #define GFX11_ROW_INSTDONE_EU03DoneSS0_start 19 #define GFX9_ROW_INSTDONE_EU03DoneSS0_start 19 #define GFX8_ROW_INSTDONE_EU03DoneSS0_start 19 #define GFX75_ROW_INSTDONE_EU03DoneSS0_start 19 #define GFX7_ROW_INSTDONE_EU03DoneSS0_start 19 static inline uint32_t ATTRIBUTE_PURE ROW_INSTDONE_EU03DoneSS0_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 19; case 120: return 19; case 110: return 19; case 90: return 19; case 80: return 19; case 75: return 19; case 70: return 19; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* ROW_INSTDONE::EU03 done SS1 */ #define GFX125_ROW_INSTDONE_EU03doneSS1_bits 1 #define GFX12_ROW_INSTDONE_EU03doneSS1_bits 1 static inline uint32_t ATTRIBUTE_PURE ROW_INSTDONE_EU03doneSS1_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_ROW_INSTDONE_EU03doneSS1_start 10 #define GFX12_ROW_INSTDONE_EU03doneSS1_start 10 static inline uint32_t ATTRIBUTE_PURE ROW_INSTDONE_EU03doneSS1_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 10; case 120: return 10; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* ROW_INSTDONE::EU04 Done SS0 */ #define GFX75_ROW_INSTDONE_EU04DoneSS0_bits 1 static inline uint32_t ATTRIBUTE_PURE ROW_INSTDONE_EU04DoneSS0_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_ROW_INSTDONE_EU04DoneSS0_start 20 static inline uint32_t ATTRIBUTE_PURE ROW_INSTDONE_EU04DoneSS0_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 20; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* ROW_INSTDONE::EU10 Done SS0 */ #define GFX125_ROW_INSTDONE_EU10DoneSS0_bits 1 #define GFX12_ROW_INSTDONE_EU10DoneSS0_bits 1 #define GFX11_ROW_INSTDONE_EU10DoneSS0_bits 1 #define GFX9_ROW_INSTDONE_EU10DoneSS0_bits 1 #define GFX8_ROW_INSTDONE_EU10DoneSS0_bits 1 #define GFX75_ROW_INSTDONE_EU10DoneSS0_bits 1 #define GFX7_ROW_INSTDONE_EU10DoneSS0_bits 1 static inline uint32_t ATTRIBUTE_PURE ROW_INSTDONE_EU10DoneSS0_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_ROW_INSTDONE_EU10DoneSS0_start 21 #define GFX12_ROW_INSTDONE_EU10DoneSS0_start 21 #define GFX11_ROW_INSTDONE_EU10DoneSS0_start 21 #define GFX9_ROW_INSTDONE_EU10DoneSS0_start 21 #define GFX8_ROW_INSTDONE_EU10DoneSS0_start 21 #define GFX75_ROW_INSTDONE_EU10DoneSS0_start 21 #define GFX7_ROW_INSTDONE_EU10DoneSS0_start 21 static inline uint32_t ATTRIBUTE_PURE ROW_INSTDONE_EU10DoneSS0_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 21; case 120: return 21; case 110: return 21; case 90: return 21; case 80: return 21; case 75: return 21; case 70: return 21; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* ROW_INSTDONE::EU10 Done SS1 */ #define GFX125_ROW_INSTDONE_EU10DoneSS1_bits 1 #define GFX12_ROW_INSTDONE_EU10DoneSS1_bits 1 static inline uint32_t ATTRIBUTE_PURE ROW_INSTDONE_EU10DoneSS1_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_ROW_INSTDONE_EU10DoneSS1_start 27 #define GFX12_ROW_INSTDONE_EU10DoneSS1_start 27 static inline uint32_t ATTRIBUTE_PURE ROW_INSTDONE_EU10DoneSS1_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* ROW_INSTDONE::EU11 Done SS0 */ #define GFX125_ROW_INSTDONE_EU11DoneSS0_bits 1 #define GFX12_ROW_INSTDONE_EU11DoneSS0_bits 1 #define GFX11_ROW_INSTDONE_EU11DoneSS0_bits 1 #define GFX9_ROW_INSTDONE_EU11DoneSS0_bits 1 #define GFX8_ROW_INSTDONE_EU11DoneSS0_bits 1 #define GFX75_ROW_INSTDONE_EU11DoneSS0_bits 1 #define GFX7_ROW_INSTDONE_EU11DoneSS0_bits 1 static inline uint32_t ATTRIBUTE_PURE ROW_INSTDONE_EU11DoneSS0_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_ROW_INSTDONE_EU11DoneSS0_start 22 #define GFX12_ROW_INSTDONE_EU11DoneSS0_start 22 #define GFX11_ROW_INSTDONE_EU11DoneSS0_start 22 #define GFX9_ROW_INSTDONE_EU11DoneSS0_start 22 #define GFX8_ROW_INSTDONE_EU11DoneSS0_start 22 #define GFX75_ROW_INSTDONE_EU11DoneSS0_start 22 #define GFX7_ROW_INSTDONE_EU11DoneSS0_start 22 static inline uint32_t ATTRIBUTE_PURE ROW_INSTDONE_EU11DoneSS0_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 22; case 120: return 22; case 110: return 22; case 90: return 22; case 80: return 22; case 75: return 22; case 70: return 22; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* ROW_INSTDONE::EU11 Done SS1 */ #define GFX125_ROW_INSTDONE_EU11DoneSS1_bits 1 #define GFX12_ROW_INSTDONE_EU11DoneSS1_bits 1 static inline uint32_t ATTRIBUTE_PURE ROW_INSTDONE_EU11DoneSS1_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_ROW_INSTDONE_EU11DoneSS1_start 28 #define GFX12_ROW_INSTDONE_EU11DoneSS1_start 28 static inline uint32_t ATTRIBUTE_PURE ROW_INSTDONE_EU11DoneSS1_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 28; case 120: return 28; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* ROW_INSTDONE::EU12 Done SS0 */ #define GFX125_ROW_INSTDONE_EU12DoneSS0_bits 1 #define GFX12_ROW_INSTDONE_EU12DoneSS0_bits 1 #define GFX11_ROW_INSTDONE_EU12DoneSS0_bits 1 #define GFX9_ROW_INSTDONE_EU12DoneSS0_bits 1 #define GFX8_ROW_INSTDONE_EU12DoneSS0_bits 1 #define GFX75_ROW_INSTDONE_EU12DoneSS0_bits 1 #define GFX7_ROW_INSTDONE_EU12DoneSS0_bits 1 static inline uint32_t ATTRIBUTE_PURE ROW_INSTDONE_EU12DoneSS0_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_ROW_INSTDONE_EU12DoneSS0_start 23 #define GFX12_ROW_INSTDONE_EU12DoneSS0_start 23 #define GFX11_ROW_INSTDONE_EU12DoneSS0_start 23 #define GFX9_ROW_INSTDONE_EU12DoneSS0_start 23 #define GFX8_ROW_INSTDONE_EU12DoneSS0_start 23 #define GFX75_ROW_INSTDONE_EU12DoneSS0_start 23 #define GFX7_ROW_INSTDONE_EU12DoneSS0_start 23 static inline uint32_t ATTRIBUTE_PURE ROW_INSTDONE_EU12DoneSS0_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 23; case 120: return 23; case 110: return 23; case 90: return 23; case 80: return 23; case 75: return 23; case 70: return 23; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* ROW_INSTDONE::EU12 Done SS1 */ #define GFX125_ROW_INSTDONE_EU12DoneSS1_bits 1 #define GFX12_ROW_INSTDONE_EU12DoneSS1_bits 1 static inline uint32_t ATTRIBUTE_PURE ROW_INSTDONE_EU12DoneSS1_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_ROW_INSTDONE_EU12DoneSS1_start 29 #define GFX12_ROW_INSTDONE_EU12DoneSS1_start 29 static inline uint32_t ATTRIBUTE_PURE ROW_INSTDONE_EU12DoneSS1_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* ROW_INSTDONE::EU13 Done SS0 */ #define GFX125_ROW_INSTDONE_EU13DoneSS0_bits 1 #define GFX12_ROW_INSTDONE_EU13DoneSS0_bits 1 #define GFX11_ROW_INSTDONE_EU13DoneSS0_bits 1 #define GFX9_ROW_INSTDONE_EU13DoneSS0_bits 1 #define GFX8_ROW_INSTDONE_EU13DoneSS0_bits 1 #define GFX75_ROW_INSTDONE_EU13DoneSS0_bits 1 #define GFX7_ROW_INSTDONE_EU13DoneSS0_bits 1 static inline uint32_t ATTRIBUTE_PURE ROW_INSTDONE_EU13DoneSS0_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_ROW_INSTDONE_EU13DoneSS0_start 24 #define GFX12_ROW_INSTDONE_EU13DoneSS0_start 24 #define GFX11_ROW_INSTDONE_EU13DoneSS0_start 24 #define GFX9_ROW_INSTDONE_EU13DoneSS0_start 24 #define GFX8_ROW_INSTDONE_EU13DoneSS0_start 24 #define GFX75_ROW_INSTDONE_EU13DoneSS0_start 24 #define GFX7_ROW_INSTDONE_EU13DoneSS0_start 24 static inline uint32_t ATTRIBUTE_PURE ROW_INSTDONE_EU13DoneSS0_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* ROW_INSTDONE::EU13 Done SS1 */ #define GFX125_ROW_INSTDONE_EU13DoneSS1_bits 1 #define GFX12_ROW_INSTDONE_EU13DoneSS1_bits 1 static inline uint32_t ATTRIBUTE_PURE ROW_INSTDONE_EU13DoneSS1_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_ROW_INSTDONE_EU13DoneSS1_start 30 #define GFX12_ROW_INSTDONE_EU13DoneSS1_start 30 static inline uint32_t ATTRIBUTE_PURE ROW_INSTDONE_EU13DoneSS1_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 30; case 120: return 30; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* ROW_INSTDONE::EU14 Done SS0 */ #define GFX75_ROW_INSTDONE_EU14DoneSS0_bits 1 static inline uint32_t ATTRIBUTE_PURE ROW_INSTDONE_EU14DoneSS0_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_ROW_INSTDONE_EU14DoneSS0_start 25 static inline uint32_t ATTRIBUTE_PURE ROW_INSTDONE_EU14DoneSS0_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 25; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* ROW_INSTDONE::GW Done */ #define GFX75_ROW_INSTDONE_GWDone_bits 1 #define GFX7_ROW_INSTDONE_GWDone_bits 1 static inline uint32_t ATTRIBUTE_PURE ROW_INSTDONE_GWDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_ROW_INSTDONE_GWDone_start 8 #define GFX7_ROW_INSTDONE_GWDone_start 8 static inline uint32_t ATTRIBUTE_PURE ROW_INSTDONE_GWDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* ROW_INSTDONE::IC Done */ #define GFX125_ROW_INSTDONE_ICDone_bits 1 #define GFX12_ROW_INSTDONE_ICDone_bits 1 #define GFX11_ROW_INSTDONE_ICDone_bits 1 #define GFX9_ROW_INSTDONE_ICDone_bits 1 #define GFX8_ROW_INSTDONE_ICDone_bits 1 #define GFX75_ROW_INSTDONE_ICDone_bits 1 #define GFX7_ROW_INSTDONE_ICDone_bits 1 static inline uint32_t ATTRIBUTE_PURE ROW_INSTDONE_ICDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_ROW_INSTDONE_ICDone_start 12 #define GFX12_ROW_INSTDONE_ICDone_start 12 #define GFX11_ROW_INSTDONE_ICDone_start 12 #define GFX9_ROW_INSTDONE_ICDone_start 12 #define GFX8_ROW_INSTDONE_ICDone_start 12 #define GFX75_ROW_INSTDONE_ICDone_start 12 #define GFX7_ROW_INSTDONE_ICDone_start 12 static inline uint32_t ATTRIBUTE_PURE ROW_INSTDONE_ICDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 12; case 120: return 12; case 110: return 12; case 90: return 12; case 80: return 12; case 75: return 12; case 70: return 12; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* ROW_INSTDONE::MA0 Done */ #define GFX11_ROW_INSTDONE_MA0Done_bits 1 #define GFX9_ROW_INSTDONE_MA0Done_bits 1 #define GFX8_ROW_INSTDONE_MA0Done_bits 1 #define GFX75_ROW_INSTDONE_MA0Done_bits 1 static inline uint32_t ATTRIBUTE_PURE ROW_INSTDONE_MA0Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX11_ROW_INSTDONE_MA0Done_start 15 #define GFX9_ROW_INSTDONE_MA0Done_start 15 #define GFX8_ROW_INSTDONE_MA0Done_start 15 #define GFX75_ROW_INSTDONE_MA0Done_start 15 static inline uint32_t ATTRIBUTE_PURE ROW_INSTDONE_MA0Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 15; case 90: return 15; case 80: return 15; case 75: return 15; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* ROW_INSTDONE::MA0 Done SS0 */ #define GFX125_ROW_INSTDONE_MA0DoneSS0_bits 1 #define GFX12_ROW_INSTDONE_MA0DoneSS0_bits 1 #define GFX7_ROW_INSTDONE_MA0DoneSS0_bits 1 static inline uint32_t ATTRIBUTE_PURE ROW_INSTDONE_MA0DoneSS0_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_ROW_INSTDONE_MA0DoneSS0_start 15 #define GFX12_ROW_INSTDONE_MA0DoneSS0_start 15 #define GFX7_ROW_INSTDONE_MA0DoneSS0_start 20 static inline uint32_t ATTRIBUTE_PURE ROW_INSTDONE_MA0DoneSS0_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 15; case 120: return 15; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 20; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* ROW_INSTDONE::MA0 done SS1 */ #define GFX125_ROW_INSTDONE_MA0doneSS1_bits 1 #define GFX12_ROW_INSTDONE_MA0doneSS1_bits 1 static inline uint32_t ATTRIBUTE_PURE ROW_INSTDONE_MA0doneSS1_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_ROW_INSTDONE_MA0doneSS1_start 11 #define GFX12_ROW_INSTDONE_MA0doneSS1_start 11 static inline uint32_t ATTRIBUTE_PURE ROW_INSTDONE_MA0doneSS1_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 11; case 120: return 11; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* ROW_INSTDONE::MA1 Done */ #define GFX7_ROW_INSTDONE_MA1Done_bits 1 static inline uint32_t ATTRIBUTE_PURE ROW_INSTDONE_MA1Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX7_ROW_INSTDONE_MA1Done_start 25 static inline uint32_t ATTRIBUTE_PURE ROW_INSTDONE_MA1Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 25; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* ROW_INSTDONE::MA1 Done SS0 */ #define GFX11_ROW_INSTDONE_MA1DoneSS0_bits 1 #define GFX9_ROW_INSTDONE_MA1DoneSS0_bits 1 #define GFX8_ROW_INSTDONE_MA1DoneSS0_bits 1 #define GFX75_ROW_INSTDONE_MA1DoneSS0_bits 1 static inline uint32_t ATTRIBUTE_PURE ROW_INSTDONE_MA1DoneSS0_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX11_ROW_INSTDONE_MA1DoneSS0_start 26 #define GFX9_ROW_INSTDONE_MA1DoneSS0_start 26 #define GFX8_ROW_INSTDONE_MA1DoneSS0_start 26 #define GFX75_ROW_INSTDONE_MA1DoneSS0_start 26 static inline uint32_t ATTRIBUTE_PURE ROW_INSTDONE_MA1DoneSS0_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 26; case 90: return 26; case 80: return 26; case 75: return 26; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* ROW_INSTDONE::PSD Done */ #define GFX125_ROW_INSTDONE_PSDDone_bits 1 #define GFX12_ROW_INSTDONE_PSDDone_bits 1 #define GFX11_ROW_INSTDONE_PSDDone_bits 1 #define GFX9_ROW_INSTDONE_PSDDone_bits 1 #define GFX8_ROW_INSTDONE_PSDDone_bits 1 #define GFX75_ROW_INSTDONE_PSDDone_bits 1 #define GFX7_ROW_INSTDONE_PSDDone_bits 1 static inline uint32_t ATTRIBUTE_PURE ROW_INSTDONE_PSDDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_ROW_INSTDONE_PSDDone_start 1 #define GFX12_ROW_INSTDONE_PSDDone_start 1 #define GFX11_ROW_INSTDONE_PSDDone_start 1 #define GFX9_ROW_INSTDONE_PSDDone_start 1 #define GFX8_ROW_INSTDONE_PSDDone_start 1 #define GFX75_ROW_INSTDONE_PSDDone_start 1 #define GFX7_ROW_INSTDONE_PSDDone_start 1 static inline uint32_t ATTRIBUTE_PURE ROW_INSTDONE_PSDDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* ROW_INSTDONE::RT DONE COMPUTE */ #define GFX125_ROW_INSTDONE_RTDONECOMPUTE_bits 1 static inline uint32_t ATTRIBUTE_PURE ROW_INSTDONE_RTDONECOMPUTE_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_ROW_INSTDONE_RTDONECOMPUTE_start 14 static inline uint32_t ATTRIBUTE_PURE ROW_INSTDONE_RTDONECOMPUTE_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 14; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* ROW_INSTDONE::RT DONE RENDER */ #define GFX125_ROW_INSTDONE_RTDONERENDER_bits 1 static inline uint32_t ATTRIBUTE_PURE ROW_INSTDONE_RTDONERENDER_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_ROW_INSTDONE_RTDONERENDER_start 5 static inline uint32_t ATTRIBUTE_PURE ROW_INSTDONE_RTDONERENDER_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* ROW_INSTDONE::TDL Done */ #define GFX125_ROW_INSTDONE_TDLDone_bits 1 #define GFX12_ROW_INSTDONE_TDLDone_bits 1 #define GFX11_ROW_INSTDONE_TDLDone_bits 1 #define GFX9_ROW_INSTDONE_TDLDone_bits 1 #define GFX8_ROW_INSTDONE_TDLDone_bits 1 #define GFX75_ROW_INSTDONE_TDLDone_bits 1 #define GFX7_ROW_INSTDONE_TDLDone_bits 1 static inline uint32_t ATTRIBUTE_PURE ROW_INSTDONE_TDLDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_ROW_INSTDONE_TDLDone_start 6 #define GFX12_ROW_INSTDONE_TDLDone_start 6 #define GFX11_ROW_INSTDONE_TDLDone_start 6 #define GFX9_ROW_INSTDONE_TDLDone_start 6 #define GFX8_ROW_INSTDONE_TDLDone_start 6 #define GFX75_ROW_INSTDONE_TDLDone_start 6 #define GFX7_ROW_INSTDONE_TDLDone_start 6 static inline uint32_t ATTRIBUTE_PURE ROW_INSTDONE_TDLDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 6; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* ROW_INSTDONE::TDP Done */ #define GFX125_ROW_INSTDONE_TDPDone_bits 1 #define GFX12_ROW_INSTDONE_TDPDone_bits 1 static inline uint32_t ATTRIBUTE_PURE ROW_INSTDONE_TDPDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_ROW_INSTDONE_TDPDone_start 2 #define GFX12_ROW_INSTDONE_TDPDone_start 2 static inline uint32_t ATTRIBUTE_PURE ROW_INSTDONE_TDPDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* ROW_INSTDONE::TSL Done */ #define GFX125_ROW_INSTDONE_TSLDone_bits 1 static inline uint32_t ATTRIBUTE_PURE ROW_INSTDONE_TSLDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_ROW_INSTDONE_TSLDone_start 26 static inline uint32_t ATTRIBUTE_PURE ROW_INSTDONE_TSLDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 26; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RPSTAT0 */ #define GFX125_RPSTAT0_length 1 #define GFX12_RPSTAT0_length 1 #define GFX11_RPSTAT0_length 1 #define GFX9_RPSTAT0_length 1 static inline uint32_t ATTRIBUTE_PURE RPSTAT0_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RPSTAT0::Current GT Frequency */ #define GFX125_RPSTAT0_CurrentGTFrequency_bits 9 #define GFX12_RPSTAT0_CurrentGTFrequency_bits 9 #define GFX11_RPSTAT0_CurrentGTFrequency_bits 9 #define GFX9_RPSTAT0_CurrentGTFrequency_bits 9 static inline uint32_t ATTRIBUTE_PURE RPSTAT0_CurrentGTFrequency_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 9; case 120: return 9; case 110: return 9; case 90: return 9; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_RPSTAT0_CurrentGTFrequency_start 23 #define GFX12_RPSTAT0_CurrentGTFrequency_start 23 #define GFX11_RPSTAT0_CurrentGTFrequency_start 23 #define GFX9_RPSTAT0_CurrentGTFrequency_start 23 static inline uint32_t ATTRIBUTE_PURE RPSTAT0_CurrentGTFrequency_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 23; case 120: return 23; case 110: return 23; case 90: return 23; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RPSTAT0::Previous GT Frequency */ #define GFX125_RPSTAT0_PreviousGTFrequency_bits 9 #define GFX12_RPSTAT0_PreviousGTFrequency_bits 9 #define GFX11_RPSTAT0_PreviousGTFrequency_bits 9 #define GFX9_RPSTAT0_PreviousGTFrequency_bits 9 static inline uint32_t ATTRIBUTE_PURE RPSTAT0_PreviousGTFrequency_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 9; case 120: return 9; case 110: return 9; case 90: return 9; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_RPSTAT0_PreviousGTFrequency_start 0 #define GFX12_RPSTAT0_PreviousGTFrequency_start 0 #define GFX11_RPSTAT0_PreviousGTFrequency_start 0 #define GFX9_RPSTAT0_PreviousGTFrequency_start 0 static inline uint32_t ATTRIBUTE_PURE RPSTAT0_PreviousGTFrequency_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RPSTAT1 */ #define GFX8_RPSTAT1_length 1 #define GFX75_RPSTAT1_length 1 #define GFX7_RPSTAT1_length 1 #define GFX6_RPSTAT1_length 1 static inline uint32_t ATTRIBUTE_PURE RPSTAT1_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RPSTAT1::Current GT Frequency */ #define GFX8_RPSTAT1_CurrentGTFrequency_bits 8 #define GFX75_RPSTAT1_CurrentGTFrequency_bits 8 #define GFX7_RPSTAT1_CurrentGTFrequency_bits 8 #define GFX6_RPSTAT1_CurrentGTFrequency_bits 8 static inline uint32_t ATTRIBUTE_PURE RPSTAT1_CurrentGTFrequency_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX8_RPSTAT1_CurrentGTFrequency_start 7 #define GFX75_RPSTAT1_CurrentGTFrequency_start 7 #define GFX7_RPSTAT1_CurrentGTFrequency_start 7 #define GFX6_RPSTAT1_CurrentGTFrequency_start 7 static inline uint32_t ATTRIBUTE_PURE RPSTAT1_CurrentGTFrequency_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 7; case 75: return 7; case 70: return 7; case 60: return 7; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* RPSTAT1::Previous GT Frequency */ #define GFX8_RPSTAT1_PreviousGTFrequency_bits 7 #define GFX75_RPSTAT1_PreviousGTFrequency_bits 7 #define GFX7_RPSTAT1_PreviousGTFrequency_bits 7 #define GFX6_RPSTAT1_PreviousGTFrequency_bits 7 static inline uint32_t ATTRIBUTE_PURE RPSTAT1_PreviousGTFrequency_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 7; case 75: return 7; case 70: return 7; case 60: return 7; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX8_RPSTAT1_PreviousGTFrequency_start 0 #define GFX75_RPSTAT1_PreviousGTFrequency_start 0 #define GFX7_RPSTAT1_PreviousGTFrequency_start 0 #define GFX6_RPSTAT1_PreviousGTFrequency_start 0 static inline uint32_t ATTRIBUTE_PURE RPSTAT1_PreviousGTFrequency_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_BORDER_COLOR_STATE */ #define GFX125_SAMPLER_BORDER_COLOR_STATE_length 4 #define GFX12_SAMPLER_BORDER_COLOR_STATE_length 4 #define GFX11_SAMPLER_BORDER_COLOR_STATE_length 4 #define GFX9_SAMPLER_BORDER_COLOR_STATE_length 4 #define GFX8_SAMPLER_BORDER_COLOR_STATE_length 4 #define GFX75_SAMPLER_BORDER_COLOR_STATE_length 20 #define GFX7_SAMPLER_BORDER_COLOR_STATE_length 4 #define GFX6_SAMPLER_BORDER_COLOR_STATE_length 12 #define GFX5_SAMPLER_BORDER_COLOR_STATE_length 12 #define GFX45_SAMPLER_BORDER_COLOR_STATE_length 12 #define GFX4_SAMPLER_BORDER_COLOR_STATE_length 12 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 20; case 70: return 4; case 60: return 12; case 50: return 12; case 45: return 12; case 40: return 12; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_BORDER_COLOR_STATE::Border Color 16bit Alpha */ #define GFX75_SAMPLER_BORDER_COLOR_STATE_BorderColor16bitAlpha_bits 16 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColor16bitAlpha_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 16; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_SAMPLER_BORDER_COLOR_STATE_BorderColor16bitAlpha_start 592 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColor16bitAlpha_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 592; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_BORDER_COLOR_STATE::Border Color 16bit Blue */ #define GFX75_SAMPLER_BORDER_COLOR_STATE_BorderColor16bitBlue_bits 16 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColor16bitBlue_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 16; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_SAMPLER_BORDER_COLOR_STATE_BorderColor16bitBlue_start 576 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColor16bitBlue_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 576; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_BORDER_COLOR_STATE::Border Color 16bit Green */ #define GFX75_SAMPLER_BORDER_COLOR_STATE_BorderColor16bitGreen_bits 16 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColor16bitGreen_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 16; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_SAMPLER_BORDER_COLOR_STATE_BorderColor16bitGreen_start 528 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColor16bitGreen_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 528; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_BORDER_COLOR_STATE::Border Color 16bit Red */ #define GFX75_SAMPLER_BORDER_COLOR_STATE_BorderColor16bitRed_bits 16 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColor16bitRed_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 16; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_SAMPLER_BORDER_COLOR_STATE_BorderColor16bitRed_start 512 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColor16bitRed_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 512; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_BORDER_COLOR_STATE::Border Color 32bit Alpha */ #define GFX125_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitAlpha_bits 32 #define GFX12_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitAlpha_bits 32 #define GFX11_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitAlpha_bits 32 #define GFX9_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitAlpha_bits 32 #define GFX8_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitAlpha_bits 32 #define GFX75_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitAlpha_bits 32 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColor32bitAlpha_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitAlpha_start 96 #define GFX12_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitAlpha_start 96 #define GFX11_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitAlpha_start 96 #define GFX9_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitAlpha_start 96 #define GFX8_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitAlpha_start 96 #define GFX75_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitAlpha_start 608 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColor32bitAlpha_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 96; case 120: return 96; case 110: return 96; case 90: return 96; case 80: return 96; case 75: return 608; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_BORDER_COLOR_STATE::Border Color 32bit Blue */ #define GFX125_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitBlue_bits 32 #define GFX12_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitBlue_bits 32 #define GFX11_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitBlue_bits 32 #define GFX9_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitBlue_bits 32 #define GFX8_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitBlue_bits 32 #define GFX75_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitBlue_bits 32 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColor32bitBlue_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitBlue_start 64 #define GFX12_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitBlue_start 64 #define GFX11_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitBlue_start 64 #define GFX9_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitBlue_start 64 #define GFX8_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitBlue_start 64 #define GFX75_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitBlue_start 576 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColor32bitBlue_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 64; case 80: return 64; case 75: return 576; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_BORDER_COLOR_STATE::Border Color 32bit Green */ #define GFX125_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitGreen_bits 32 #define GFX12_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitGreen_bits 32 #define GFX11_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitGreen_bits 32 #define GFX9_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitGreen_bits 32 #define GFX8_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitGreen_bits 32 #define GFX75_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitGreen_bits 32 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColor32bitGreen_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitGreen_start 32 #define GFX12_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitGreen_start 32 #define GFX11_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitGreen_start 32 #define GFX9_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitGreen_start 32 #define GFX8_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitGreen_start 32 #define GFX75_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitGreen_start 544 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColor32bitGreen_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 544; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_BORDER_COLOR_STATE::Border Color 32bit Red */ #define GFX125_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitRed_bits 32 #define GFX12_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitRed_bits 32 #define GFX11_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitRed_bits 32 #define GFX9_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitRed_bits 32 #define GFX8_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitRed_bits 32 #define GFX75_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitRed_bits 32 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColor32bitRed_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitRed_start 0 #define GFX12_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitRed_start 0 #define GFX11_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitRed_start 0 #define GFX9_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitRed_start 0 #define GFX8_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitRed_start 0 #define GFX75_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitRed_start 512 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColor32bitRed_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 512; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_BORDER_COLOR_STATE::Border Color 8bit Alpha */ #define GFX75_SAMPLER_BORDER_COLOR_STATE_BorderColor8bitAlpha_bits 8 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColor8bitAlpha_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 8; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_SAMPLER_BORDER_COLOR_STATE_BorderColor8bitAlpha_start 536 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColor8bitAlpha_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 536; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_BORDER_COLOR_STATE::Border Color 8bit Blue */ #define GFX75_SAMPLER_BORDER_COLOR_STATE_BorderColor8bitBlue_bits 8 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColor8bitBlue_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 8; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_SAMPLER_BORDER_COLOR_STATE_BorderColor8bitBlue_start 528 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColor8bitBlue_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 528; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_BORDER_COLOR_STATE::Border Color 8bit Green */ #define GFX75_SAMPLER_BORDER_COLOR_STATE_BorderColor8bitGreen_bits 8 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColor8bitGreen_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 8; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_SAMPLER_BORDER_COLOR_STATE_BorderColor8bitGreen_start 520 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColor8bitGreen_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 520; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_BORDER_COLOR_STATE::Border Color 8bit Red */ #define GFX75_SAMPLER_BORDER_COLOR_STATE_BorderColor8bitRed_bits 8 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColor8bitRed_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 8; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_SAMPLER_BORDER_COLOR_STATE_BorderColor8bitRed_start 512 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColor8bitRed_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 512; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_BORDER_COLOR_STATE::Border Color Alpha */ #define GFX45_SAMPLER_BORDER_COLOR_STATE_BorderColorAlpha_bits 32 #define GFX4_SAMPLER_BORDER_COLOR_STATE_BorderColorAlpha_bits 32 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColorAlpha_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } #define GFX45_SAMPLER_BORDER_COLOR_STATE_BorderColorAlpha_start 96 #define GFX4_SAMPLER_BORDER_COLOR_STATE_BorderColorAlpha_start 96 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColorAlpha_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 96; case 40: return 96; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_BORDER_COLOR_STATE::Border Color Blue */ #define GFX45_SAMPLER_BORDER_COLOR_STATE_BorderColorBlue_bits 32 #define GFX4_SAMPLER_BORDER_COLOR_STATE_BorderColorBlue_bits 32 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColorBlue_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } #define GFX45_SAMPLER_BORDER_COLOR_STATE_BorderColorBlue_start 64 #define GFX4_SAMPLER_BORDER_COLOR_STATE_BorderColorBlue_start 64 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColorBlue_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 64; case 40: return 64; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_BORDER_COLOR_STATE::Border Color Float16 Alpha */ #define GFX6_SAMPLER_BORDER_COLOR_STATE_BorderColorFloat16Alpha_bits 16 #define GFX5_SAMPLER_BORDER_COLOR_STATE_BorderColorFloat16Alpha_bits 16 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColorFloat16Alpha_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 16; case 50: return 16; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_SAMPLER_BORDER_COLOR_STATE_BorderColorFloat16Alpha_start 208 #define GFX5_SAMPLER_BORDER_COLOR_STATE_BorderColorFloat16Alpha_start 208 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColorFloat16Alpha_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 208; case 50: return 208; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_BORDER_COLOR_STATE::Border Color Float16 Blue */ #define GFX6_SAMPLER_BORDER_COLOR_STATE_BorderColorFloat16Blue_bits 16 #define GFX5_SAMPLER_BORDER_COLOR_STATE_BorderColorFloat16Blue_bits 16 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColorFloat16Blue_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 16; case 50: return 16; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_SAMPLER_BORDER_COLOR_STATE_BorderColorFloat16Blue_start 192 #define GFX5_SAMPLER_BORDER_COLOR_STATE_BorderColorFloat16Blue_start 192 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColorFloat16Blue_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 192; case 50: return 192; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_BORDER_COLOR_STATE::Border Color Float16 Green */ #define GFX6_SAMPLER_BORDER_COLOR_STATE_BorderColorFloat16Green_bits 16 #define GFX5_SAMPLER_BORDER_COLOR_STATE_BorderColorFloat16Green_bits 16 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColorFloat16Green_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 16; case 50: return 16; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_SAMPLER_BORDER_COLOR_STATE_BorderColorFloat16Green_start 176 #define GFX5_SAMPLER_BORDER_COLOR_STATE_BorderColorFloat16Green_start 176 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColorFloat16Green_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 176; case 50: return 176; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_BORDER_COLOR_STATE::Border Color Float16 Red */ #define GFX6_SAMPLER_BORDER_COLOR_STATE_BorderColorFloat16Red_bits 16 #define GFX5_SAMPLER_BORDER_COLOR_STATE_BorderColorFloat16Red_bits 16 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColorFloat16Red_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 16; case 50: return 16; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_SAMPLER_BORDER_COLOR_STATE_BorderColorFloat16Red_start 160 #define GFX5_SAMPLER_BORDER_COLOR_STATE_BorderColorFloat16Red_start 160 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColorFloat16Red_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 160; case 50: return 160; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_BORDER_COLOR_STATE::Border Color Float Alpha */ #define GFX125_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatAlpha_bits 32 #define GFX12_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatAlpha_bits 32 #define GFX11_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatAlpha_bits 32 #define GFX9_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatAlpha_bits 32 #define GFX8_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatAlpha_bits 32 #define GFX75_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatAlpha_bits 32 #define GFX7_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatAlpha_bits 32 #define GFX6_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatAlpha_bits 32 #define GFX5_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatAlpha_bits 32 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColorFloatAlpha_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 32; case 50: return 32; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatAlpha_start 96 #define GFX12_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatAlpha_start 96 #define GFX11_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatAlpha_start 96 #define GFX9_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatAlpha_start 96 #define GFX8_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatAlpha_start 96 #define GFX75_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatAlpha_start 96 #define GFX7_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatAlpha_start 96 #define GFX6_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatAlpha_start 128 #define GFX5_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatAlpha_start 128 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColorFloatAlpha_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 96; case 120: return 96; case 110: return 96; case 90: return 96; case 80: return 96; case 75: return 96; case 70: return 96; case 60: return 128; case 50: return 128; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_BORDER_COLOR_STATE::Border Color Float Blue */ #define GFX125_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatBlue_bits 32 #define GFX12_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatBlue_bits 32 #define GFX11_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatBlue_bits 32 #define GFX9_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatBlue_bits 32 #define GFX8_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatBlue_bits 32 #define GFX75_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatBlue_bits 32 #define GFX7_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatBlue_bits 32 #define GFX6_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatBlue_bits 32 #define GFX5_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatBlue_bits 32 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColorFloatBlue_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 32; case 50: return 32; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatBlue_start 64 #define GFX12_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatBlue_start 64 #define GFX11_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatBlue_start 64 #define GFX9_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatBlue_start 64 #define GFX8_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatBlue_start 64 #define GFX75_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatBlue_start 64 #define GFX7_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatBlue_start 64 #define GFX6_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatBlue_start 96 #define GFX5_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatBlue_start 96 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColorFloatBlue_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 64; case 80: return 64; case 75: return 64; case 70: return 64; case 60: return 96; case 50: return 96; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_BORDER_COLOR_STATE::Border Color Float Green */ #define GFX125_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatGreen_bits 32 #define GFX12_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatGreen_bits 32 #define GFX11_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatGreen_bits 32 #define GFX9_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatGreen_bits 32 #define GFX8_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatGreen_bits 32 #define GFX75_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatGreen_bits 32 #define GFX7_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatGreen_bits 32 #define GFX6_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatGreen_bits 32 #define GFX5_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatGreen_bits 32 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColorFloatGreen_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 32; case 50: return 32; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatGreen_start 32 #define GFX12_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatGreen_start 32 #define GFX11_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatGreen_start 32 #define GFX9_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatGreen_start 32 #define GFX8_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatGreen_start 32 #define GFX75_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatGreen_start 32 #define GFX7_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatGreen_start 32 #define GFX6_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatGreen_start 64 #define GFX5_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatGreen_start 64 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColorFloatGreen_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 64; case 50: return 64; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_BORDER_COLOR_STATE::Border Color Float Red */ #define GFX125_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatRed_bits 32 #define GFX12_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatRed_bits 32 #define GFX11_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatRed_bits 32 #define GFX9_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatRed_bits 32 #define GFX8_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatRed_bits 32 #define GFX75_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatRed_bits 32 #define GFX7_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatRed_bits 32 #define GFX6_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatRed_bits 32 #define GFX5_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatRed_bits 32 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColorFloatRed_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 32; case 50: return 32; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatRed_start 0 #define GFX12_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatRed_start 0 #define GFX11_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatRed_start 0 #define GFX9_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatRed_start 0 #define GFX8_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatRed_start 0 #define GFX75_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatRed_start 0 #define GFX7_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatRed_start 0 #define GFX6_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatRed_start 32 #define GFX5_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatRed_start 32 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColorFloatRed_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 32; case 50: return 32; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_BORDER_COLOR_STATE::Border Color Green */ #define GFX45_SAMPLER_BORDER_COLOR_STATE_BorderColorGreen_bits 32 #define GFX4_SAMPLER_BORDER_COLOR_STATE_BorderColorGreen_bits 32 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColorGreen_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } #define GFX45_SAMPLER_BORDER_COLOR_STATE_BorderColorGreen_start 32 #define GFX4_SAMPLER_BORDER_COLOR_STATE_BorderColorGreen_start 32 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColorGreen_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_BORDER_COLOR_STATE::Border Color Red */ #define GFX45_SAMPLER_BORDER_COLOR_STATE_BorderColorRed_bits 32 #define GFX4_SAMPLER_BORDER_COLOR_STATE_BorderColorRed_bits 32 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColorRed_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } #define GFX45_SAMPLER_BORDER_COLOR_STATE_BorderColorRed_start 0 #define GFX4_SAMPLER_BORDER_COLOR_STATE_BorderColorRed_start 0 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColorRed_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_BORDER_COLOR_STATE::Border Color Snorm16 Alpha */ #define GFX6_SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm16Alpha_bits 16 #define GFX5_SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm16Alpha_bits 16 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm16Alpha_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 16; case 50: return 16; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm16Alpha_start 336 #define GFX5_SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm16Alpha_start 336 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm16Alpha_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 336; case 50: return 336; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_BORDER_COLOR_STATE::Border Color Snorm16 Blue */ #define GFX6_SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm16Blue_bits 16 #define GFX5_SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm16Blue_bits 16 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm16Blue_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 16; case 50: return 16; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm16Blue_start 320 #define GFX5_SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm16Blue_start 320 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm16Blue_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 320; case 50: return 320; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_BORDER_COLOR_STATE::Border Color Snorm16 Green */ #define GFX6_SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm16Green_bits 16 #define GFX5_SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm16Green_bits 16 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm16Green_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 16; case 50: return 16; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm16Green_start 304 #define GFX5_SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm16Green_start 304 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm16Green_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 304; case 50: return 304; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_BORDER_COLOR_STATE::Border Color Snorm16 Red */ #define GFX6_SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm16Red_bits 16 #define GFX5_SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm16Red_bits 16 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm16Red_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 16; case 50: return 16; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm16Red_start 288 #define GFX5_SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm16Red_start 288 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm16Red_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 288; case 50: return 288; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_BORDER_COLOR_STATE::Border Color Snorm8 Alpha */ #define GFX6_SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm8Alpha_bits 8 #define GFX5_SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm8Alpha_bits 8 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm8Alpha_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 8; case 50: return 8; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm8Alpha_start 376 #define GFX5_SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm8Alpha_start 376 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm8Alpha_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 376; case 50: return 376; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_BORDER_COLOR_STATE::Border Color Snorm8 Blue */ #define GFX6_SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm8Blue_bits 8 #define GFX5_SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm8Blue_bits 8 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm8Blue_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 8; case 50: return 8; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm8Blue_start 368 #define GFX5_SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm8Blue_start 368 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm8Blue_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 368; case 50: return 368; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_BORDER_COLOR_STATE::Border Color Snorm8 Green */ #define GFX6_SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm8Green_bits 8 #define GFX5_SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm8Green_bits 8 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm8Green_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 8; case 50: return 8; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm8Green_start 360 #define GFX5_SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm8Green_start 360 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm8Green_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 360; case 50: return 360; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_BORDER_COLOR_STATE::Border Color Snorm8 Red */ #define GFX6_SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm8Red_bits 8 #define GFX5_SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm8Red_bits 8 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm8Red_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 8; case 50: return 8; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm8Red_start 352 #define GFX5_SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm8Red_start 352 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm8Red_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 352; case 50: return 352; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_BORDER_COLOR_STATE::Border Color Unorm16 Alpha */ #define GFX6_SAMPLER_BORDER_COLOR_STATE_BorderColorUnorm16Alpha_bits 16 #define GFX5_SAMPLER_BORDER_COLOR_STATE_BorderColorUnorm16Alpha_bits 16 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColorUnorm16Alpha_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 16; case 50: return 16; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_SAMPLER_BORDER_COLOR_STATE_BorderColorUnorm16Alpha_start 272 #define GFX5_SAMPLER_BORDER_COLOR_STATE_BorderColorUnorm16Alpha_start 272 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColorUnorm16Alpha_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 272; case 50: return 272; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_BORDER_COLOR_STATE::Border Color Unorm16 Blue */ #define GFX6_SAMPLER_BORDER_COLOR_STATE_BorderColorUnorm16Blue_bits 16 #define GFX5_SAMPLER_BORDER_COLOR_STATE_BorderColorUnorm16Blue_bits 16 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColorUnorm16Blue_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 16; case 50: return 16; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_SAMPLER_BORDER_COLOR_STATE_BorderColorUnorm16Blue_start 256 #define GFX5_SAMPLER_BORDER_COLOR_STATE_BorderColorUnorm16Blue_start 256 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColorUnorm16Blue_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 256; case 50: return 256; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_BORDER_COLOR_STATE::Border Color Unorm16 Green */ #define GFX6_SAMPLER_BORDER_COLOR_STATE_BorderColorUnorm16Green_bits 16 #define GFX5_SAMPLER_BORDER_COLOR_STATE_BorderColorUnorm16Green_bits 16 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColorUnorm16Green_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 16; case 50: return 16; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_SAMPLER_BORDER_COLOR_STATE_BorderColorUnorm16Green_start 240 #define GFX5_SAMPLER_BORDER_COLOR_STATE_BorderColorUnorm16Green_start 240 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColorUnorm16Green_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 240; case 50: return 240; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_BORDER_COLOR_STATE::Border Color Unorm16 Red */ #define GFX6_SAMPLER_BORDER_COLOR_STATE_BorderColorUnorm16Red_bits 16 #define GFX5_SAMPLER_BORDER_COLOR_STATE_BorderColorUnorm16Red_bits 16 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColorUnorm16Red_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 16; case 50: return 16; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_SAMPLER_BORDER_COLOR_STATE_BorderColorUnorm16Red_start 224 #define GFX5_SAMPLER_BORDER_COLOR_STATE_BorderColorUnorm16Red_start 224 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColorUnorm16Red_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 224; case 50: return 224; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_BORDER_COLOR_STATE::Border Color Unorm Alpha */ #define GFX7_SAMPLER_BORDER_COLOR_STATE_BorderColorUnormAlpha_bits 8 #define GFX6_SAMPLER_BORDER_COLOR_STATE_BorderColorUnormAlpha_bits 8 #define GFX5_SAMPLER_BORDER_COLOR_STATE_BorderColorUnormAlpha_bits 8 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColorUnormAlpha_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 8; case 60: return 8; case 50: return 8; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX7_SAMPLER_BORDER_COLOR_STATE_BorderColorUnormAlpha_start 24 #define GFX6_SAMPLER_BORDER_COLOR_STATE_BorderColorUnormAlpha_start 24 #define GFX5_SAMPLER_BORDER_COLOR_STATE_BorderColorUnormAlpha_start 24 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColorUnormAlpha_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 24; case 60: return 24; case 50: return 24; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_BORDER_COLOR_STATE::Border Color Unorm Blue */ #define GFX7_SAMPLER_BORDER_COLOR_STATE_BorderColorUnormBlue_bits 8 #define GFX6_SAMPLER_BORDER_COLOR_STATE_BorderColorUnormBlue_bits 8 #define GFX5_SAMPLER_BORDER_COLOR_STATE_BorderColorUnormBlue_bits 8 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColorUnormBlue_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 8; case 60: return 8; case 50: return 8; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX7_SAMPLER_BORDER_COLOR_STATE_BorderColorUnormBlue_start 16 #define GFX6_SAMPLER_BORDER_COLOR_STATE_BorderColorUnormBlue_start 16 #define GFX5_SAMPLER_BORDER_COLOR_STATE_BorderColorUnormBlue_start 16 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColorUnormBlue_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 16; case 60: return 16; case 50: return 16; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_BORDER_COLOR_STATE::Border Color Unorm Green */ #define GFX7_SAMPLER_BORDER_COLOR_STATE_BorderColorUnormGreen_bits 8 #define GFX6_SAMPLER_BORDER_COLOR_STATE_BorderColorUnormGreen_bits 8 #define GFX5_SAMPLER_BORDER_COLOR_STATE_BorderColorUnormGreen_bits 8 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColorUnormGreen_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 8; case 60: return 8; case 50: return 8; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX7_SAMPLER_BORDER_COLOR_STATE_BorderColorUnormGreen_start 8 #define GFX6_SAMPLER_BORDER_COLOR_STATE_BorderColorUnormGreen_start 8 #define GFX5_SAMPLER_BORDER_COLOR_STATE_BorderColorUnormGreen_start 8 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColorUnormGreen_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 8; case 60: return 8; case 50: return 8; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_BORDER_COLOR_STATE::Border Color Unorm Red */ #define GFX7_SAMPLER_BORDER_COLOR_STATE_BorderColorUnormRed_bits 8 #define GFX6_SAMPLER_BORDER_COLOR_STATE_BorderColorUnormRed_bits 8 #define GFX5_SAMPLER_BORDER_COLOR_STATE_BorderColorUnormRed_bits 8 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColorUnormRed_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 8; case 60: return 8; case 50: return 8; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX7_SAMPLER_BORDER_COLOR_STATE_BorderColorUnormRed_start 0 #define GFX6_SAMPLER_BORDER_COLOR_STATE_BorderColorUnormRed_start 0 #define GFX5_SAMPLER_BORDER_COLOR_STATE_BorderColorUnormRed_start 0 static inline uint32_t ATTRIBUTE_PURE SAMPLER_BORDER_COLOR_STATE_BorderColorUnormRed_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INDIRECT_STATE_BORDER_COLOR */ #define GFX125_SAMPLER_INDIRECT_STATE_BORDER_COLOR_length 4 #define GFX12_SAMPLER_INDIRECT_STATE_BORDER_COLOR_length 4 #define GFX11_SAMPLER_INDIRECT_STATE_BORDER_COLOR_length 4 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INDIRECT_STATE_BORDER_COLOR_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INDIRECT_STATE_BORDER_COLOR::Border Color Alpha As Float */ #define GFX125_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorAlphaAsFloat_bits 32 #define GFX12_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorAlphaAsFloat_bits 32 #define GFX11_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorAlphaAsFloat_bits 32 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorAlphaAsFloat_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorAlphaAsFloat_start 96 #define GFX12_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorAlphaAsFloat_start 96 #define GFX11_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorAlphaAsFloat_start 96 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorAlphaAsFloat_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 96; case 120: return 96; case 110: return 96; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INDIRECT_STATE_BORDER_COLOR::Border Color Alpha As S31 */ #define GFX125_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorAlphaAsS31_bits 32 #define GFX12_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorAlphaAsS31_bits 32 #define GFX11_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorAlphaAsS31_bits 32 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorAlphaAsS31_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorAlphaAsS31_start 96 #define GFX12_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorAlphaAsS31_start 96 #define GFX11_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorAlphaAsS31_start 96 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorAlphaAsS31_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 96; case 120: return 96; case 110: return 96; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INDIRECT_STATE_BORDER_COLOR::Border Color Alpha As U32 */ #define GFX125_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorAlphaAsU32_bits 32 #define GFX12_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorAlphaAsU32_bits 32 #define GFX11_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorAlphaAsU32_bits 32 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorAlphaAsU32_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorAlphaAsU32_start 96 #define GFX12_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorAlphaAsU32_start 96 #define GFX11_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorAlphaAsU32_start 96 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorAlphaAsU32_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 96; case 120: return 96; case 110: return 96; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INDIRECT_STATE_BORDER_COLOR::Border Color Alpha As U8 */ #define GFX125_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorAlphaAsU8_bits 8 #define GFX12_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorAlphaAsU8_bits 8 #define GFX11_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorAlphaAsU8_bits 8 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorAlphaAsU8_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorAlphaAsU8_start 24 #define GFX12_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorAlphaAsU8_start 24 #define GFX11_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorAlphaAsU8_start 24 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorAlphaAsU8_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INDIRECT_STATE_BORDER_COLOR::Border Color Blue As Float */ #define GFX125_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorBlueAsFloat_bits 32 #define GFX12_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorBlueAsFloat_bits 32 #define GFX11_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorBlueAsFloat_bits 32 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorBlueAsFloat_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorBlueAsFloat_start 64 #define GFX12_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorBlueAsFloat_start 64 #define GFX11_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorBlueAsFloat_start 64 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorBlueAsFloat_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INDIRECT_STATE_BORDER_COLOR::Border Color Blue As S31 */ #define GFX125_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorBlueAsS31_bits 32 #define GFX12_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorBlueAsS31_bits 32 #define GFX11_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorBlueAsS31_bits 32 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorBlueAsS31_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorBlueAsS31_start 64 #define GFX12_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorBlueAsS31_start 64 #define GFX11_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorBlueAsS31_start 64 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorBlueAsS31_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INDIRECT_STATE_BORDER_COLOR::Border Color Blue As U32 */ #define GFX125_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorBlueAsU32_bits 32 #define GFX12_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorBlueAsU32_bits 32 #define GFX11_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorBlueAsU32_bits 32 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorBlueAsU32_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorBlueAsU32_start 64 #define GFX12_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorBlueAsU32_start 64 #define GFX11_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorBlueAsU32_start 64 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorBlueAsU32_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INDIRECT_STATE_BORDER_COLOR::Border Color Blue As U8 */ #define GFX125_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorBlueAsU8_bits 8 #define GFX12_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorBlueAsU8_bits 8 #define GFX11_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorBlueAsU8_bits 8 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorBlueAsU8_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorBlueAsU8_start 16 #define GFX12_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorBlueAsU8_start 16 #define GFX11_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorBlueAsU8_start 16 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorBlueAsU8_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INDIRECT_STATE_BORDER_COLOR::Border Color Green As Float */ #define GFX125_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorGreenAsFloat_bits 32 #define GFX12_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorGreenAsFloat_bits 32 #define GFX11_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorGreenAsFloat_bits 32 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorGreenAsFloat_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorGreenAsFloat_start 32 #define GFX12_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorGreenAsFloat_start 32 #define GFX11_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorGreenAsFloat_start 32 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorGreenAsFloat_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INDIRECT_STATE_BORDER_COLOR::Border Color Green As S31 */ #define GFX125_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorGreenAsS31_bits 32 #define GFX12_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorGreenAsS31_bits 32 #define GFX11_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorGreenAsS31_bits 32 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorGreenAsS31_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorGreenAsS31_start 32 #define GFX12_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorGreenAsS31_start 32 #define GFX11_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorGreenAsS31_start 32 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorGreenAsS31_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INDIRECT_STATE_BORDER_COLOR::Border Color Green As U32 */ #define GFX125_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorGreenAsU32_bits 32 #define GFX12_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorGreenAsU32_bits 32 #define GFX11_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorGreenAsU32_bits 32 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorGreenAsU32_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorGreenAsU32_start 32 #define GFX12_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorGreenAsU32_start 32 #define GFX11_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorGreenAsU32_start 32 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorGreenAsU32_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INDIRECT_STATE_BORDER_COLOR::Border Color Green As U8 */ #define GFX125_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorGreenAsU8_bits 8 #define GFX12_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorGreenAsU8_bits 8 #define GFX11_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorGreenAsU8_bits 8 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorGreenAsU8_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorGreenAsU8_start 8 #define GFX12_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorGreenAsU8_start 8 #define GFX11_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorGreenAsU8_start 8 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorGreenAsU8_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INDIRECT_STATE_BORDER_COLOR::Border Color Red As Float */ #define GFX125_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorRedAsFloat_bits 32 #define GFX12_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorRedAsFloat_bits 32 #define GFX11_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorRedAsFloat_bits 32 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorRedAsFloat_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorRedAsFloat_start 0 #define GFX12_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorRedAsFloat_start 0 #define GFX11_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorRedAsFloat_start 0 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorRedAsFloat_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INDIRECT_STATE_BORDER_COLOR::Border Color Red As S31 */ #define GFX125_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorRedAsS31_bits 32 #define GFX12_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorRedAsS31_bits 32 #define GFX11_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorRedAsS31_bits 32 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorRedAsS31_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorRedAsS31_start 0 #define GFX12_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorRedAsS31_start 0 #define GFX11_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorRedAsS31_start 0 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorRedAsS31_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INDIRECT_STATE_BORDER_COLOR::Border Color Red As U32 */ #define GFX125_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorRedAsU32_bits 32 #define GFX12_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorRedAsU32_bits 32 #define GFX11_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorRedAsU32_bits 32 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorRedAsU32_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorRedAsU32_start 0 #define GFX12_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorRedAsU32_start 0 #define GFX11_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorRedAsU32_start 0 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorRedAsU32_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INDIRECT_STATE_BORDER_COLOR::Border Color Red As U8 */ #define GFX125_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorRedAsU8_bits 8 #define GFX12_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorRedAsU8_bits 8 #define GFX11_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorRedAsU8_bits 8 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorRedAsU8_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorRedAsU8_start 0 #define GFX12_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorRedAsU8_start 0 #define GFX11_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorRedAsU8_start 0 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorRedAsU8_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INSTDONE */ #define GFX125_SAMPLER_INSTDONE_length 1 #define GFX12_SAMPLER_INSTDONE_length 1 #define GFX11_SAMPLER_INSTDONE_length 1 #define GFX9_SAMPLER_INSTDONE_length 1 #define GFX8_SAMPLER_INSTDONE_length 1 #define GFX75_SAMPLER_INSTDONE_length 1 #define GFX7_SAMPLER_INSTDONE_length 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INSTDONE::AVS Done */ #define GFX12_SAMPLER_INSTDONE_AVSDone_bits 1 #define GFX11_SAMPLER_INSTDONE_AVSDone_bits 1 #define GFX9_SAMPLER_INSTDONE_AVSDone_bits 1 #define GFX8_SAMPLER_INSTDONE_AVSDone_bits 1 #define GFX75_SAMPLER_INSTDONE_AVSDone_bits 1 #define GFX7_SAMPLER_INSTDONE_AVSDone_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_AVSDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_SAMPLER_INSTDONE_AVSDone_start 12 #define GFX11_SAMPLER_INSTDONE_AVSDone_start 12 #define GFX9_SAMPLER_INSTDONE_AVSDone_start 12 #define GFX8_SAMPLER_INSTDONE_AVSDone_start 12 #define GFX75_SAMPLER_INSTDONE_AVSDone_start 12 #define GFX7_SAMPLER_INSTDONE_AVSDone_start 12 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_AVSDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 12; case 110: return 12; case 90: return 12; case 80: return 12; case 75: return 12; case 70: return 12; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INSTDONE::BDM Done */ #define GFX125_SAMPLER_INSTDONE_BDMDone_bits 1 #define GFX12_SAMPLER_INSTDONE_BDMDone_bits 1 #define GFX11_SAMPLER_INSTDONE_BDMDone_bits 1 #define GFX9_SAMPLER_INSTDONE_BDMDone_bits 1 #define GFX8_SAMPLER_INSTDONE_BDMDone_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_BDMDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_INSTDONE_BDMDone_start 13 #define GFX12_SAMPLER_INSTDONE_BDMDone_start 19 #define GFX11_SAMPLER_INSTDONE_BDMDone_start 19 #define GFX9_SAMPLER_INSTDONE_BDMDone_start 19 #define GFX8_SAMPLER_INSTDONE_BDMDone_start 19 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_BDMDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 13; case 120: return 19; case 110: return 19; case 90: return 19; case 80: return 19; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INSTDONE::CRE Done */ #define GFX12_SAMPLER_INSTDONE_CREDone_bits 1 #define GFX11_SAMPLER_INSTDONE_CREDone_bits 1 #define GFX9_SAMPLER_INSTDONE_CREDone_bits 1 #define GFX8_SAMPLER_INSTDONE_CREDone_bits 1 #define GFX75_SAMPLER_INSTDONE_CREDone_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_CREDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_SAMPLER_INSTDONE_CREDone_start 14 #define GFX11_SAMPLER_INSTDONE_CREDone_start 14 #define GFX9_SAMPLER_INSTDONE_CREDone_start 14 #define GFX8_SAMPLER_INSTDONE_CREDone_start 14 #define GFX75_SAMPLER_INSTDONE_CREDone_start 14 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_CREDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 14; case 110: return 14; case 90: return 14; case 80: return 14; case 75: return 14; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INSTDONE::DG0 Done */ #define GFX12_SAMPLER_INSTDONE_DG0Done_bits 1 #define GFX11_SAMPLER_INSTDONE_DG0Done_bits 1 #define GFX9_SAMPLER_INSTDONE_DG0Done_bits 1 #define GFX8_SAMPLER_INSTDONE_DG0Done_bits 1 #define GFX75_SAMPLER_INSTDONE_DG0Done_bits 1 #define GFX7_SAMPLER_INSTDONE_DG0Done_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_DG0Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_SAMPLER_INSTDONE_DG0Done_start 3 #define GFX11_SAMPLER_INSTDONE_DG0Done_start 3 #define GFX9_SAMPLER_INSTDONE_DG0Done_start 3 #define GFX8_SAMPLER_INSTDONE_DG0Done_start 3 #define GFX75_SAMPLER_INSTDONE_DG0Done_start 3 #define GFX7_SAMPLER_INSTDONE_DG0Done_start 3 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_DG0Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INSTDONE::DG1 Done */ #define GFX12_SAMPLER_INSTDONE_DG1Done_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_DG1Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_SAMPLER_INSTDONE_DG1Done_start 24 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_DG1Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 24; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INSTDONE::DG Done */ #define GFX125_SAMPLER_INSTDONE_DGDone_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_DGDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_INSTDONE_DGDone_start 5 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_DGDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INSTDONE::DM0 Done */ #define GFX12_SAMPLER_INSTDONE_DM0Done_bits 1 #define GFX11_SAMPLER_INSTDONE_DM0Done_bits 1 #define GFX9_SAMPLER_INSTDONE_DM0Done_bits 1 #define GFX8_SAMPLER_INSTDONE_DM0Done_bits 1 #define GFX75_SAMPLER_INSTDONE_DM0Done_bits 1 #define GFX7_SAMPLER_INSTDONE_DM0Done_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_DM0Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_SAMPLER_INSTDONE_DM0Done_start 5 #define GFX11_SAMPLER_INSTDONE_DM0Done_start 5 #define GFX9_SAMPLER_INSTDONE_DM0Done_start 5 #define GFX8_SAMPLER_INSTDONE_DM0Done_start 5 #define GFX75_SAMPLER_INSTDONE_DM0Done_start 5 #define GFX7_SAMPLER_INSTDONE_DM0Done_start 5 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_DM0Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 5; case 110: return 5; case 90: return 5; case 80: return 5; case 75: return 5; case 70: return 5; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INSTDONE::DM1 Done */ #define GFX75_SAMPLER_INSTDONE_DM1Done_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_DM1Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_SAMPLER_INSTDONE_DM1Done_start 20 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_DM1Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 20; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INSTDONE::DM Done */ #define GFX125_SAMPLER_INSTDONE_DMDone_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_DMDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_INSTDONE_DMDone_start 12 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_DMDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 12; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INSTDONE::FL0 Done */ #define GFX12_SAMPLER_INSTDONE_FL0Done_bits 1 #define GFX11_SAMPLER_INSTDONE_FL0Done_bits 1 #define GFX9_SAMPLER_INSTDONE_FL0Done_bits 1 #define GFX8_SAMPLER_INSTDONE_FL0Done_bits 1 #define GFX75_SAMPLER_INSTDONE_FL0Done_bits 1 #define GFX7_SAMPLER_INSTDONE_FL0Done_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_FL0Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_SAMPLER_INSTDONE_FL0Done_start 7 #define GFX11_SAMPLER_INSTDONE_FL0Done_start 7 #define GFX9_SAMPLER_INSTDONE_FL0Done_start 7 #define GFX8_SAMPLER_INSTDONE_FL0Done_start 7 #define GFX75_SAMPLER_INSTDONE_FL0Done_start 7 #define GFX7_SAMPLER_INSTDONE_FL0Done_start 7 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_FL0Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 7; case 110: return 7; case 90: return 7; case 80: return 7; case 75: return 7; case 70: return 7; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INSTDONE::FL1 Done */ #define GFX12_SAMPLER_INSTDONE_FL1Done_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_FL1Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_SAMPLER_INSTDONE_FL1Done_start 23 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_FL1Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 23; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INSTDONE::FL Done */ #define GFX125_SAMPLER_INSTDONE_FLDone_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_FLDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_INSTDONE_FLDone_start 15 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_FLDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 15; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INSTDONE::FT0 Done */ #define GFX12_SAMPLER_INSTDONE_FT0Done_bits 1 #define GFX11_SAMPLER_INSTDONE_FT0Done_bits 1 #define GFX9_SAMPLER_INSTDONE_FT0Done_bits 1 #define GFX8_SAMPLER_INSTDONE_FT0Done_bits 1 #define GFX75_SAMPLER_INSTDONE_FT0Done_bits 1 #define GFX7_SAMPLER_INSTDONE_FT0Done_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_FT0Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_SAMPLER_INSTDONE_FT0Done_start 4 #define GFX11_SAMPLER_INSTDONE_FT0Done_start 4 #define GFX9_SAMPLER_INSTDONE_FT0Done_start 4 #define GFX8_SAMPLER_INSTDONE_FT0Done_start 4 #define GFX75_SAMPLER_INSTDONE_FT0Done_start 4 #define GFX7_SAMPLER_INSTDONE_FT0Done_start 4 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_FT0Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 4; case 70: return 4; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INSTDONE::FT1 Done */ #define GFX75_SAMPLER_INSTDONE_FT1Done_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_FT1Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_SAMPLER_INSTDONE_FT1Done_start 19 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_FT1Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 19; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INSTDONE::FT Done */ #define GFX125_SAMPLER_INSTDONE_FTDone_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_FTDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_INSTDONE_FTDone_start 9 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_FTDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 9; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INSTDONE::IEF Done */ #define GFX11_SAMPLER_INSTDONE_IEFDone_bits 1 #define GFX9_SAMPLER_INSTDONE_IEFDone_bits 1 #define GFX8_SAMPLER_INSTDONE_IEFDone_bits 1 #define GFX75_SAMPLER_INSTDONE_IEFDone_bits 1 #define GFX7_SAMPLER_INSTDONE_IEFDone_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_IEFDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX11_SAMPLER_INSTDONE_IEFDone_start 13 #define GFX9_SAMPLER_INSTDONE_IEFDone_start 13 #define GFX8_SAMPLER_INSTDONE_IEFDone_start 13 #define GFX75_SAMPLER_INSTDONE_IEFDone_start 13 #define GFX7_SAMPLER_INSTDONE_IEFDone_start 13 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_IEFDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 13; case 90: return 13; case 80: return 13; case 75: return 13; case 70: return 13; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INSTDONE::IME Done */ #define GFX12_SAMPLER_INSTDONE_IMEDone_bits 1 #define GFX11_SAMPLER_INSTDONE_IMEDone_bits 1 #define GFX9_SAMPLER_INSTDONE_IMEDone_bits 1 #define GFX8_SAMPLER_INSTDONE_IMEDone_bits 1 #define GFX75_SAMPLER_INSTDONE_IMEDone_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_IMEDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_SAMPLER_INSTDONE_IMEDone_start 0 #define GFX11_SAMPLER_INSTDONE_IMEDone_start 0 #define GFX9_SAMPLER_INSTDONE_IMEDone_start 0 #define GFX8_SAMPLER_INSTDONE_IMEDone_start 0 #define GFX75_SAMPLER_INSTDONE_IMEDone_start 0 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_IMEDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INSTDONE::LSC L1BANK0 Idle */ #define GFX125_SAMPLER_INSTDONE_LSCL1BANK0Idle_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_LSCL1BANK0Idle_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_INSTDONE_LSCL1BANK0Idle_start 18 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_LSCL1BANK0Idle_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 18; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INSTDONE::LSC L1BANK1 Idle */ #define GFX125_SAMPLER_INSTDONE_LSCL1BANK1Idle_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_LSCL1BANK1Idle_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_INSTDONE_LSCL1BANK1Idle_start 19 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_LSCL1BANK1Idle_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 19; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INSTDONE::LSC L1BANK2 Idle */ #define GFX125_SAMPLER_INSTDONE_LSCL1BANK2Idle_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_LSCL1BANK2Idle_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_INSTDONE_LSCL1BANK2Idle_start 20 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_LSCL1BANK2Idle_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 20; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INSTDONE::LSC L1BANK3 Idle */ #define GFX125_SAMPLER_INSTDONE_LSCL1BANK3Idle_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_LSCL1BANK3Idle_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_INSTDONE_LSCL1BANK3Idle_start 21 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_LSCL1BANK3Idle_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 21; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INSTDONE::LSC L3 INTF Idle */ #define GFX125_SAMPLER_INSTDONE_LSCL3INTFIdle_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_LSCL3INTFIdle_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_INSTDONE_LSCL3INTFIdle_start 27 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_LSCL3INTFIdle_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INSTDONE::LSC SEQ0 Idle */ #define GFX125_SAMPLER_INSTDONE_LSCSEQ0Idle_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_LSCSEQ0Idle_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_INSTDONE_LSCSEQ0Idle_start 22 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_LSCSEQ0Idle_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 22; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INSTDONE::LSC SEQ1 Idle */ #define GFX125_SAMPLER_INSTDONE_LSCSEQ1Idle_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_LSCSEQ1Idle_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_INSTDONE_LSCSEQ1Idle_start 23 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_LSCSEQ1Idle_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 23; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INSTDONE::LSC SEQ2 Idle */ #define GFX125_SAMPLER_INSTDONE_LSCSEQ2Idle_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_LSCSEQ2Idle_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_INSTDONE_LSCSEQ2Idle_start 24 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_LSCSEQ2Idle_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INSTDONE::LSC SEQ3 Idle */ #define GFX125_SAMPLER_INSTDONE_LSCSEQ3Idle_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_LSCSEQ3Idle_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_INSTDONE_LSCSEQ3Idle_start 25 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_LSCSEQ3Idle_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 25; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INSTDONE::LSC SEQ INTF Idle */ #define GFX125_SAMPLER_INSTDONE_LSCSEQINTFIdle_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_LSCSEQINTFIdle_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_INSTDONE_LSCSEQINTFIdle_start 26 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_LSCSEQINTFIdle_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 26; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INSTDONE::MEDIASAMPLER ARB1 */ #define GFX12_SAMPLER_INSTDONE_MEDIASAMPLERARB1_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_MEDIASAMPLERARB1_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_SAMPLER_INSTDONE_MEDIASAMPLERARB1_start 28 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_MEDIASAMPLERARB1_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 28; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INSTDONE::MEDIASAMPLER ARB2 */ #define GFX12_SAMPLER_INSTDONE_MEDIASAMPLERARB2_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_MEDIASAMPLERARB2_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_SAMPLER_INSTDONE_MEDIASAMPLERARB2_start 27 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_MEDIASAMPLERARB2_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 27; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INSTDONE::MS SUBSLICED FORK */ #define GFX12_SAMPLER_INSTDONE_MSSUBSLICEDFORK_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_MSSUBSLICEDFORK_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_SAMPLER_INSTDONE_MSSUBSLICEDFORK_start 29 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_MSSUBSLICEDFORK_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 29; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INSTDONE::MT0 Done */ #define GFX12_SAMPLER_INSTDONE_MT0Done_bits 1 #define GFX11_SAMPLER_INSTDONE_MT0Done_bits 1 #define GFX9_SAMPLER_INSTDONE_MT0Done_bits 1 #define GFX8_SAMPLER_INSTDONE_MT0Done_bits 1 #define GFX75_SAMPLER_INSTDONE_MT0Done_bits 1 #define GFX7_SAMPLER_INSTDONE_MT0Done_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_MT0Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_SAMPLER_INSTDONE_MT0Done_start 11 #define GFX11_SAMPLER_INSTDONE_MT0Done_start 11 #define GFX9_SAMPLER_INSTDONE_MT0Done_start 11 #define GFX8_SAMPLER_INSTDONE_MT0Done_start 11 #define GFX75_SAMPLER_INSTDONE_MT0Done_start 11 #define GFX7_SAMPLER_INSTDONE_MT0Done_start 11 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_MT0Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 11; case 110: return 11; case 90: return 11; case 80: return 11; case 75: return 11; case 70: return 11; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INSTDONE::MT1 Done */ #define GFX75_SAMPLER_INSTDONE_MT1Done_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_MT1Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_SAMPLER_INSTDONE_MT1Done_start 21 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_MT1Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 21; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INSTDONE::MT Done */ #define GFX125_SAMPLER_INSTDONE_MTDone_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_MTDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_INSTDONE_MTDone_start 11 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_MTDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 11; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INSTDONE::Media Sampler Arb Done */ #define GFX12_SAMPLER_INSTDONE_MediaSamplerArbDone_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_MediaSamplerArbDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_SAMPLER_INSTDONE_MediaSamplerArbDone_start 15 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_MediaSamplerArbDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 15; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INSTDONE::PL0 Done */ #define GFX12_SAMPLER_INSTDONE_PL0Done_bits 1 #define GFX11_SAMPLER_INSTDONE_PL0Done_bits 1 #define GFX9_SAMPLER_INSTDONE_PL0Done_bits 1 #define GFX8_SAMPLER_INSTDONE_PL0Done_bits 1 #define GFX75_SAMPLER_INSTDONE_PL0Done_bits 1 #define GFX7_SAMPLER_INSTDONE_PL0Done_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_PL0Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_SAMPLER_INSTDONE_PL0Done_start 1 #define GFX11_SAMPLER_INSTDONE_PL0Done_start 1 #define GFX9_SAMPLER_INSTDONE_PL0Done_start 1 #define GFX8_SAMPLER_INSTDONE_PL0Done_start 1 #define GFX75_SAMPLER_INSTDONE_PL0Done_start 1 #define GFX7_SAMPLER_INSTDONE_PL0Done_start 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_PL0Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INSTDONE::PL1 Done */ #define GFX12_SAMPLER_INSTDONE_PL1Done_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_PL1Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_SAMPLER_INSTDONE_PL1Done_start 25 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_PL1Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 25; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INSTDONE::PL Done */ #define GFX125_SAMPLER_INSTDONE_PLDone_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_PLDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_INSTDONE_PLDone_start 4 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_PLDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INSTDONE::QC Done */ #define GFX11_SAMPLER_INSTDONE_QCDone_bits 1 #define GFX9_SAMPLER_INSTDONE_QCDone_bits 1 #define GFX8_SAMPLER_INSTDONE_QCDone_bits 1 #define GFX75_SAMPLER_INSTDONE_QCDone_bits 1 #define GFX7_SAMPLER_INSTDONE_QCDone_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_QCDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX11_SAMPLER_INSTDONE_QCDone_start 8 #define GFX9_SAMPLER_INSTDONE_QCDone_start 8 #define GFX8_SAMPLER_INSTDONE_QCDone_start 8 #define GFX75_SAMPLER_INSTDONE_QCDone_start 8 #define GFX7_SAMPLER_INSTDONE_QCDone_start 8 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_QCDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INSTDONE::RDE Done */ #define GFX12_SAMPLER_INSTDONE_RDEDone_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_RDEDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_SAMPLER_INSTDONE_RDEDone_start 31 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_RDEDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 31; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INSTDONE::SC Done */ #define GFX125_SAMPLER_INSTDONE_SCDone_bits 1 #define GFX12_SAMPLER_INSTDONE_SCDone_bits 1 #define GFX11_SAMPLER_INSTDONE_SCDone_bits 1 #define GFX9_SAMPLER_INSTDONE_SCDone_bits 1 #define GFX8_SAMPLER_INSTDONE_SCDone_bits 1 #define GFX75_SAMPLER_INSTDONE_SCDone_bits 1 #define GFX7_SAMPLER_INSTDONE_SCDone_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_SCDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_INSTDONE_SCDone_start 14 #define GFX12_SAMPLER_INSTDONE_SCDone_start 6 #define GFX11_SAMPLER_INSTDONE_SCDone_start 6 #define GFX9_SAMPLER_INSTDONE_SCDone_start 6 #define GFX8_SAMPLER_INSTDONE_SCDone_start 6 #define GFX75_SAMPLER_INSTDONE_SCDone_start 6 #define GFX7_SAMPLER_INSTDONE_SCDone_start 6 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_SCDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 14; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 6; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INSTDONE::SI0 Done */ #define GFX12_SAMPLER_INSTDONE_SI0Done_bits 1 #define GFX11_SAMPLER_INSTDONE_SI0Done_bits 1 #define GFX9_SAMPLER_INSTDONE_SI0Done_bits 1 #define GFX8_SAMPLER_INSTDONE_SI0Done_bits 1 #define GFX75_SAMPLER_INSTDONE_SI0Done_bits 1 #define GFX7_SAMPLER_INSTDONE_SI0Done_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_SI0Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_SAMPLER_INSTDONE_SI0Done_start 10 #define GFX11_SAMPLER_INSTDONE_SI0Done_start 10 #define GFX9_SAMPLER_INSTDONE_SI0Done_start 10 #define GFX8_SAMPLER_INSTDONE_SI0Done_start 10 #define GFX75_SAMPLER_INSTDONE_SI0Done_start 10 #define GFX7_SAMPLER_INSTDONE_SI0Done_start 10 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_SI0Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 10; case 110: return 10; case 90: return 10; case 80: return 10; case 75: return 10; case 70: return 10; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INSTDONE::SI1 Done */ #define GFX12_SAMPLER_INSTDONE_SI1Done_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_SI1Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_SAMPLER_INSTDONE_SI1Done_start 26 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_SI1Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 26; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INSTDONE::SI Done */ #define GFX125_SAMPLER_INSTDONE_SIDone_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_SIDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_INSTDONE_SIDone_start 0 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_SIDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INSTDONE::SO0 Done */ #define GFX12_SAMPLER_INSTDONE_SO0Done_bits 1 #define GFX11_SAMPLER_INSTDONE_SO0Done_bits 1 #define GFX9_SAMPLER_INSTDONE_SO0Done_bits 1 #define GFX8_SAMPLER_INSTDONE_SO0Done_bits 1 #define GFX75_SAMPLER_INSTDONE_SO0Done_bits 1 #define GFX7_SAMPLER_INSTDONE_SO0Done_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_SO0Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_SAMPLER_INSTDONE_SO0Done_start 2 #define GFX11_SAMPLER_INSTDONE_SO0Done_start 2 #define GFX9_SAMPLER_INSTDONE_SO0Done_start 2 #define GFX8_SAMPLER_INSTDONE_SO0Done_start 2 #define GFX75_SAMPLER_INSTDONE_SO0Done_start 2 #define GFX7_SAMPLER_INSTDONE_SO0Done_start 2 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_SO0Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INSTDONE::SO1 Done */ #define GFX12_SAMPLER_INSTDONE_SO1Done_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_SO1Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_SAMPLER_INSTDONE_SO1Done_start 22 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_SO1Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 22; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INSTDONE::SO Done */ #define GFX125_SAMPLER_INSTDONE_SODone_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_SODone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_INSTDONE_SODone_start 16 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_SODone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INSTDONE::SSLA Done */ #define GFX125_SAMPLER_INSTDONE_SSLADone_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_SSLADone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_INSTDONE_SSLADone_start 6 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_SSLADone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INSTDONE::ST ARB Done */ #define GFX125_SAMPLER_INSTDONE_STARBDone_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_STARBDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_INSTDONE_STARBDone_start 7 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_STARBDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 7; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INSTDONE::ST Done */ #define GFX125_SAMPLER_INSTDONE_STDone_bits 1 #define GFX12_SAMPLER_INSTDONE_STDone_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_STDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_INSTDONE_STDone_start 8 #define GFX12_SAMPLER_INSTDONE_STDone_start 8 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_STDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INSTDONE::SVSM ADAPTER Done */ #define GFX125_SAMPLER_INSTDONE_SVSMADAPTERDone_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_SVSMADAPTERDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_INSTDONE_SVSMADAPTERDone_start 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_SVSMADAPTERDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INSTDONE::SVSM ARB1 */ #define GFX12_SAMPLER_INSTDONE_SVSMARB1_bits 1 #define GFX11_SAMPLER_INSTDONE_SVSMARB1_bits 1 #define GFX9_SAMPLER_INSTDONE_SVSMARB1_bits 1 #define GFX8_SAMPLER_INSTDONE_SVSMARB1_bits 1 #define GFX75_SAMPLER_INSTDONE_SVSMARB1_bits 1 #define GFX7_SAMPLER_INSTDONE_SVSMARB1_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_SVSMARB1_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_SAMPLER_INSTDONE_SVSMARB1_start 17 #define GFX11_SAMPLER_INSTDONE_SVSMARB1_start 17 #define GFX9_SAMPLER_INSTDONE_SVSMARB1_start 17 #define GFX8_SAMPLER_INSTDONE_SVSMARB1_start 17 #define GFX75_SAMPLER_INSTDONE_SVSMARB1_start 17 #define GFX7_SAMPLER_INSTDONE_SVSMARB1_start 17 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_SVSMARB1_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 17; case 110: return 17; case 90: return 17; case 80: return 17; case 75: return 17; case 70: return 17; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INSTDONE::SVSM ARB2 */ #define GFX12_SAMPLER_INSTDONE_SVSMARB2_bits 1 #define GFX11_SAMPLER_INSTDONE_SVSMARB2_bits 1 #define GFX9_SAMPLER_INSTDONE_SVSMARB2_bits 1 #define GFX8_SAMPLER_INSTDONE_SVSMARB2_bits 1 #define GFX75_SAMPLER_INSTDONE_SVSMARB2_bits 1 #define GFX7_SAMPLER_INSTDONE_SVSMARB2_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_SVSMARB2_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_SAMPLER_INSTDONE_SVSMARB2_start 16 #define GFX11_SAMPLER_INSTDONE_SVSMARB2_start 16 #define GFX9_SAMPLER_INSTDONE_SVSMARB2_start 16 #define GFX8_SAMPLER_INSTDONE_SVSMARB2_start 16 #define GFX75_SAMPLER_INSTDONE_SVSMARB2_start 16 #define GFX7_SAMPLER_INSTDONE_SVSMARB2_start 16 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_SVSMARB2_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INSTDONE::SVSM ARB3 */ #define GFX9_SAMPLER_INSTDONE_SVSMARB3_bits 1 #define GFX8_SAMPLER_INSTDONE_SVSMARB3_bits 1 #define GFX75_SAMPLER_INSTDONE_SVSMARB3_bits 1 #define GFX7_SAMPLER_INSTDONE_SVSMARB3_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_SVSMARB3_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_SAMPLER_INSTDONE_SVSMARB3_start 15 #define GFX8_SAMPLER_INSTDONE_SVSMARB3_start 15 #define GFX75_SAMPLER_INSTDONE_SVSMARB3_start 15 #define GFX7_SAMPLER_INSTDONE_SVSMARB3_start 15 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_SVSMARB3_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 15; case 80: return 15; case 75: return 15; case 70: return 15; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INSTDONE::SVSM ARB Done */ #define GFX125_SAMPLER_INSTDONE_SVSMARBDone_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_SVSMARBDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_INSTDONE_SVSMARBDone_start 2 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_SVSMARBDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INSTDONE::SVSM Adapter */ #define GFX12_SAMPLER_INSTDONE_SVSMAdapter_bits 1 #define GFX11_SAMPLER_INSTDONE_SVSMAdapter_bits 1 #define GFX9_SAMPLER_INSTDONE_SVSMAdapter_bits 1 #define GFX8_SAMPLER_INSTDONE_SVSMAdapter_bits 1 #define GFX75_SAMPLER_INSTDONE_SVSMAdapter_bits 1 #define GFX7_SAMPLER_INSTDONE_SVSMAdapter_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_SVSMAdapter_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_SAMPLER_INSTDONE_SVSMAdapter_start 18 #define GFX11_SAMPLER_INSTDONE_SVSMAdapter_start 18 #define GFX9_SAMPLER_INSTDONE_SVSMAdapter_start 18 #define GFX8_SAMPLER_INSTDONE_SVSMAdapter_start 18 #define GFX75_SAMPLER_INSTDONE_SVSMAdapter_start 18 #define GFX7_SAMPLER_INSTDONE_SVSMAdapter_start 18 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_SVSMAdapter_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 18; case 110: return 18; case 90: return 18; case 80: return 18; case 75: return 18; case 70: return 18; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INSTDONE::SVSM Done */ #define GFX125_SAMPLER_INSTDONE_SVSMDone_bits 1 #define GFX12_SAMPLER_INSTDONE_SVSMDone_bits 1 #define GFX11_SAMPLER_INSTDONE_SVSMDone_bits 1 #define GFX9_SAMPLER_INSTDONE_SVSMDone_bits 1 #define GFX8_SAMPLER_INSTDONE_SVSMDone_bits 1 #define GFX75_SAMPLER_INSTDONE_SVSMDone_bits 1 #define GFX7_SAMPLER_INSTDONE_SVSMDone_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_SVSMDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_INSTDONE_SVSMDone_start 3 #define GFX12_SAMPLER_INSTDONE_SVSMDone_start 9 #define GFX11_SAMPLER_INSTDONE_SVSMDone_start 9 #define GFX9_SAMPLER_INSTDONE_SVSMDone_start 9 #define GFX8_SAMPLER_INSTDONE_SVSMDone_start 9 #define GFX75_SAMPLER_INSTDONE_SVSMDone_start 9 #define GFX7_SAMPLER_INSTDONE_SVSMDone_start 9 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_SVSMDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 9; case 110: return 9; case 90: return 9; case 80: return 9; case 75: return 9; case 70: return 9; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INSTDONE::SVSM_ARB_SIFM */ #define GFX11_SAMPLER_INSTDONE_SVSM_ARB_SIFM_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_SVSM_ARB_SIFM_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX11_SAMPLER_INSTDONE_SVSM_ARB_SIFM_start 15 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_SVSM_ARB_SIFM_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 15; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INSTDONE::VAFE Done */ #define GFX12_SAMPLER_INSTDONE_VAFEDone_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_VAFEDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_SAMPLER_INSTDONE_VAFEDone_start 13 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_VAFEDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 13; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INSTDONE::VDI Done */ #define GFX7_SAMPLER_INSTDONE_VDIDone_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_VDIDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX7_SAMPLER_INSTDONE_VDIDone_start 14 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_VDIDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 14; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INSTDONE::VME Done */ #define GFX7_SAMPLER_INSTDONE_VMEDone_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_VMEDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX7_SAMPLER_INSTDONE_VMEDone_start 0 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_VMEDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INSTDONE::VMEM L3REQARB0 Done */ #define GFX125_SAMPLER_INSTDONE_VMEML3REQARB0Done_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_VMEML3REQARB0Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_INSTDONE_VMEML3REQARB0Done_start 30 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_VMEML3REQARB0Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 30; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INSTDONE::VMEM L3REQARB1 Done */ #define GFX125_SAMPLER_INSTDONE_VMEML3REQARB1Done_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_VMEML3REQARB1Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_INSTDONE_VMEML3REQARB1Done_start 31 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_VMEML3REQARB1Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 31; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INSTDONE::VMEM SOARB0 Done */ #define GFX125_SAMPLER_INSTDONE_VMEMSOARB0Done_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_VMEMSOARB0Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_INSTDONE_VMEMSOARB0Done_start 28 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_VMEMSOARB0Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 28; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INSTDONE::VMEM SOARB1 Done */ #define GFX125_SAMPLER_INSTDONE_VMEMSOARB1Done_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_VMEMSOARB1Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_INSTDONE_VMEMSOARB1Done_start 29 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_VMEMSOARB1Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_INSTDONE::VMESC Done */ #define GFX12_SAMPLER_INSTDONE_VMESCDone_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_VMESCDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_SAMPLER_INSTDONE_VMESCDone_start 30 static inline uint32_t ATTRIBUTE_PURE SAMPLER_INSTDONE_VMESCDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 30; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_MODE */ #define GFX125_SAMPLER_MODE_length 1 #define GFX12_SAMPLER_MODE_length 1 #define GFX11_SAMPLER_MODE_length 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_MODE_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_MODE::Headerless Message for Pre-emptable Contexts */ #define GFX125_SAMPLER_MODE_HeaderlessMessageforPreemptableContexts_bits 1 #define GFX12_SAMPLER_MODE_HeaderlessMessageforPreemptableContexts_bits 1 #define GFX11_SAMPLER_MODE_HeaderlessMessageforPreemptableContexts_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_MODE_HeaderlessMessageforPreemptableContexts_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_MODE_HeaderlessMessageforPreemptableContexts_start 5 #define GFX12_SAMPLER_MODE_HeaderlessMessageforPreemptableContexts_start 5 #define GFX11_SAMPLER_MODE_HeaderlessMessageforPreemptableContexts_start 5 static inline uint32_t ATTRIBUTE_PURE SAMPLER_MODE_HeaderlessMessageforPreemptableContexts_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 5; case 110: return 5; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_MODE::Headerless Message for Pre-emptable Contexts Mask */ #define GFX125_SAMPLER_MODE_HeaderlessMessageforPreemptableContextsMask_bits 1 #define GFX12_SAMPLER_MODE_HeaderlessMessageforPreemptableContextsMask_bits 1 #define GFX11_SAMPLER_MODE_HeaderlessMessageforPreemptableContextsMask_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_MODE_HeaderlessMessageforPreemptableContextsMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_MODE_HeaderlessMessageforPreemptableContextsMask_start 21 #define GFX12_SAMPLER_MODE_HeaderlessMessageforPreemptableContextsMask_start 21 #define GFX11_SAMPLER_MODE_HeaderlessMessageforPreemptableContextsMask_start 21 static inline uint32_t ATTRIBUTE_PURE SAMPLER_MODE_HeaderlessMessageforPreemptableContextsMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 21; case 120: return 21; case 110: return 21; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_STATE */ #define GFX125_SAMPLER_STATE_length 4 #define GFX12_SAMPLER_STATE_length 4 #define GFX11_SAMPLER_STATE_length 4 #define GFX9_SAMPLER_STATE_length 4 #define GFX8_SAMPLER_STATE_length 4 #define GFX75_SAMPLER_STATE_length 4 #define GFX7_SAMPLER_STATE_length 4 #define GFX6_SAMPLER_STATE_length 4 #define GFX5_SAMPLER_STATE_length 4 #define GFX45_SAMPLER_STATE_length 4 #define GFX4_SAMPLER_STATE_length 4 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 4; case 70: return 4; case 60: return 4; case 50: return 4; case 45: return 4; case 40: return 4; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_STATE::Anisotropic Algorithm */ #define GFX125_SAMPLER_STATE_AnisotropicAlgorithm_bits 1 #define GFX12_SAMPLER_STATE_AnisotropicAlgorithm_bits 1 #define GFX11_SAMPLER_STATE_AnisotropicAlgorithm_bits 1 #define GFX9_SAMPLER_STATE_AnisotropicAlgorithm_bits 1 #define GFX8_SAMPLER_STATE_AnisotropicAlgorithm_bits 1 #define GFX75_SAMPLER_STATE_AnisotropicAlgorithm_bits 1 #define GFX7_SAMPLER_STATE_AnisotropicAlgorithm_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_AnisotropicAlgorithm_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_STATE_AnisotropicAlgorithm_start 0 #define GFX12_SAMPLER_STATE_AnisotropicAlgorithm_start 0 #define GFX11_SAMPLER_STATE_AnisotropicAlgorithm_start 0 #define GFX9_SAMPLER_STATE_AnisotropicAlgorithm_start 0 #define GFX8_SAMPLER_STATE_AnisotropicAlgorithm_start 0 #define GFX75_SAMPLER_STATE_AnisotropicAlgorithm_start 0 #define GFX7_SAMPLER_STATE_AnisotropicAlgorithm_start 0 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_AnisotropicAlgorithm_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_STATE::Base Mip Level */ #define GFX8_SAMPLER_STATE_BaseMipLevel_bits 5 #define GFX75_SAMPLER_STATE_BaseMipLevel_bits 5 #define GFX7_SAMPLER_STATE_BaseMipLevel_bits 5 #define GFX6_SAMPLER_STATE_BaseMipLevel_bits 5 #define GFX5_SAMPLER_STATE_BaseMipLevel_bits 5 #define GFX45_SAMPLER_STATE_BaseMipLevel_bits 5 #define GFX4_SAMPLER_STATE_BaseMipLevel_bits 5 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_BaseMipLevel_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 5; case 75: return 5; case 70: return 5; case 60: return 5; case 50: return 5; case 45: return 5; case 40: return 5; default: unreachable("Invalid hardware generation"); } } #define GFX8_SAMPLER_STATE_BaseMipLevel_start 22 #define GFX75_SAMPLER_STATE_BaseMipLevel_start 22 #define GFX7_SAMPLER_STATE_BaseMipLevel_start 22 #define GFX6_SAMPLER_STATE_BaseMipLevel_start 22 #define GFX5_SAMPLER_STATE_BaseMipLevel_start 22 #define GFX45_SAMPLER_STATE_BaseMipLevel_start 22 #define GFX4_SAMPLER_STATE_BaseMipLevel_start 22 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_BaseMipLevel_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 22; case 75: return 22; case 70: return 22; case 60: return 22; case 50: return 22; case 45: return 22; case 40: return 22; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_STATE::Border Color Pointer */ #define GFX125_SAMPLER_STATE_BorderColorPointer_bits 18 #define GFX12_SAMPLER_STATE_BorderColorPointer_bits 18 #define GFX11_SAMPLER_STATE_BorderColorPointer_bits 18 #define GFX9_SAMPLER_STATE_BorderColorPointer_bits 18 #define GFX8_SAMPLER_STATE_BorderColorPointer_bits 18 #define GFX75_SAMPLER_STATE_BorderColorPointer_bits 27 #define GFX7_SAMPLER_STATE_BorderColorPointer_bits 27 #define GFX6_SAMPLER_STATE_BorderColorPointer_bits 27 #define GFX5_SAMPLER_STATE_BorderColorPointer_bits 27 #define GFX45_SAMPLER_STATE_BorderColorPointer_bits 27 #define GFX4_SAMPLER_STATE_BorderColorPointer_bits 27 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_BorderColorPointer_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 18; case 120: return 18; case 110: return 18; case 90: return 18; case 80: return 18; case 75: return 27; case 70: return 27; case 60: return 27; case 50: return 27; case 45: return 27; case 40: return 27; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_STATE_BorderColorPointer_start 70 #define GFX12_SAMPLER_STATE_BorderColorPointer_start 70 #define GFX11_SAMPLER_STATE_BorderColorPointer_start 70 #define GFX9_SAMPLER_STATE_BorderColorPointer_start 70 #define GFX8_SAMPLER_STATE_BorderColorPointer_start 70 #define GFX75_SAMPLER_STATE_BorderColorPointer_start 69 #define GFX7_SAMPLER_STATE_BorderColorPointer_start 69 #define GFX6_SAMPLER_STATE_BorderColorPointer_start 69 #define GFX5_SAMPLER_STATE_BorderColorPointer_start 69 #define GFX45_SAMPLER_STATE_BorderColorPointer_start 69 #define GFX4_SAMPLER_STATE_BorderColorPointer_start 69 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_BorderColorPointer_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 70; case 120: return 70; case 110: return 70; case 90: return 70; case 80: return 70; case 75: return 69; case 70: return 69; case 60: return 69; case 50: return 69; case 45: return 69; case 40: return 69; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_STATE::CPS LOD Compensation Enable */ #define GFX125_SAMPLER_STATE_CPSLODCompensationEnable_bits 1 #define GFX12_SAMPLER_STATE_CPSLODCompensationEnable_bits 1 #define GFX11_SAMPLER_STATE_CPSLODCompensationEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_CPSLODCompensationEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_STATE_CPSLODCompensationEnable_start 30 #define GFX12_SAMPLER_STATE_CPSLODCompensationEnable_start 30 #define GFX11_SAMPLER_STATE_CPSLODCompensationEnable_start 30 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_CPSLODCompensationEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 30; case 120: return 30; case 110: return 30; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_STATE::ChromaKey Enable */ #define GFX125_SAMPLER_STATE_ChromaKeyEnable_bits 1 #define GFX12_SAMPLER_STATE_ChromaKeyEnable_bits 1 #define GFX11_SAMPLER_STATE_ChromaKeyEnable_bits 1 #define GFX9_SAMPLER_STATE_ChromaKeyEnable_bits 1 #define GFX8_SAMPLER_STATE_ChromaKeyEnable_bits 1 #define GFX75_SAMPLER_STATE_ChromaKeyEnable_bits 1 #define GFX7_SAMPLER_STATE_ChromaKeyEnable_bits 1 #define GFX6_SAMPLER_STATE_ChromaKeyEnable_bits 1 #define GFX5_SAMPLER_STATE_ChromaKeyEnable_bits 1 #define GFX45_SAMPLER_STATE_ChromaKeyEnable_bits 1 #define GFX4_SAMPLER_STATE_ChromaKeyEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_ChromaKeyEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_STATE_ChromaKeyEnable_start 39 #define GFX12_SAMPLER_STATE_ChromaKeyEnable_start 39 #define GFX11_SAMPLER_STATE_ChromaKeyEnable_start 39 #define GFX9_SAMPLER_STATE_ChromaKeyEnable_start 39 #define GFX8_SAMPLER_STATE_ChromaKeyEnable_start 39 #define GFX75_SAMPLER_STATE_ChromaKeyEnable_start 121 #define GFX7_SAMPLER_STATE_ChromaKeyEnable_start 121 #define GFX6_SAMPLER_STATE_ChromaKeyEnable_start 121 #define GFX5_SAMPLER_STATE_ChromaKeyEnable_start 121 #define GFX45_SAMPLER_STATE_ChromaKeyEnable_start 121 #define GFX4_SAMPLER_STATE_ChromaKeyEnable_start 121 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_ChromaKeyEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 39; case 120: return 39; case 110: return 39; case 90: return 39; case 80: return 39; case 75: return 121; case 70: return 121; case 60: return 121; case 50: return 121; case 45: return 121; case 40: return 121; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_STATE::ChromaKey Index */ #define GFX125_SAMPLER_STATE_ChromaKeyIndex_bits 2 #define GFX12_SAMPLER_STATE_ChromaKeyIndex_bits 2 #define GFX11_SAMPLER_STATE_ChromaKeyIndex_bits 2 #define GFX9_SAMPLER_STATE_ChromaKeyIndex_bits 2 #define GFX8_SAMPLER_STATE_ChromaKeyIndex_bits 2 #define GFX75_SAMPLER_STATE_ChromaKeyIndex_bits 2 #define GFX7_SAMPLER_STATE_ChromaKeyIndex_bits 2 #define GFX6_SAMPLER_STATE_ChromaKeyIndex_bits 2 #define GFX5_SAMPLER_STATE_ChromaKeyIndex_bits 2 #define GFX45_SAMPLER_STATE_ChromaKeyIndex_bits 2 #define GFX4_SAMPLER_STATE_ChromaKeyIndex_bits 2 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_ChromaKeyIndex_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 2; case 45: return 2; case 40: return 2; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_STATE_ChromaKeyIndex_start 37 #define GFX12_SAMPLER_STATE_ChromaKeyIndex_start 37 #define GFX11_SAMPLER_STATE_ChromaKeyIndex_start 37 #define GFX9_SAMPLER_STATE_ChromaKeyIndex_start 37 #define GFX8_SAMPLER_STATE_ChromaKeyIndex_start 37 #define GFX75_SAMPLER_STATE_ChromaKeyIndex_start 119 #define GFX7_SAMPLER_STATE_ChromaKeyIndex_start 119 #define GFX6_SAMPLER_STATE_ChromaKeyIndex_start 119 #define GFX5_SAMPLER_STATE_ChromaKeyIndex_start 119 #define GFX45_SAMPLER_STATE_ChromaKeyIndex_start 119 #define GFX4_SAMPLER_STATE_ChromaKeyIndex_start 119 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_ChromaKeyIndex_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 37; case 120: return 37; case 110: return 37; case 90: return 37; case 80: return 37; case 75: return 119; case 70: return 119; case 60: return 119; case 50: return 119; case 45: return 119; case 40: return 119; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_STATE::ChromaKey Mode */ #define GFX125_SAMPLER_STATE_ChromaKeyMode_bits 1 #define GFX12_SAMPLER_STATE_ChromaKeyMode_bits 1 #define GFX11_SAMPLER_STATE_ChromaKeyMode_bits 1 #define GFX9_SAMPLER_STATE_ChromaKeyMode_bits 1 #define GFX8_SAMPLER_STATE_ChromaKeyMode_bits 1 #define GFX75_SAMPLER_STATE_ChromaKeyMode_bits 1 #define GFX7_SAMPLER_STATE_ChromaKeyMode_bits 1 #define GFX6_SAMPLER_STATE_ChromaKeyMode_bits 1 #define GFX5_SAMPLER_STATE_ChromaKeyMode_bits 1 #define GFX45_SAMPLER_STATE_ChromaKeyMode_bits 1 #define GFX4_SAMPLER_STATE_ChromaKeyMode_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_ChromaKeyMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_STATE_ChromaKeyMode_start 36 #define GFX12_SAMPLER_STATE_ChromaKeyMode_start 36 #define GFX11_SAMPLER_STATE_ChromaKeyMode_start 36 #define GFX9_SAMPLER_STATE_ChromaKeyMode_start 36 #define GFX8_SAMPLER_STATE_ChromaKeyMode_start 36 #define GFX75_SAMPLER_STATE_ChromaKeyMode_start 118 #define GFX7_SAMPLER_STATE_ChromaKeyMode_start 118 #define GFX6_SAMPLER_STATE_ChromaKeyMode_start 118 #define GFX5_SAMPLER_STATE_ChromaKeyMode_start 118 #define GFX45_SAMPLER_STATE_ChromaKeyMode_start 118 #define GFX4_SAMPLER_STATE_ChromaKeyMode_start 118 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_ChromaKeyMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 36; case 120: return 36; case 110: return 36; case 90: return 36; case 80: return 36; case 75: return 118; case 70: return 118; case 60: return 118; case 50: return 118; case 45: return 118; case 40: return 118; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_STATE::Coarse LOD Quality Mode */ #define GFX125_SAMPLER_STATE_CoarseLODQualityMode_bits 5 #define GFX12_SAMPLER_STATE_CoarseLODQualityMode_bits 5 #define GFX11_SAMPLER_STATE_CoarseLODQualityMode_bits 5 #define GFX9_SAMPLER_STATE_CoarseLODQualityMode_bits 5 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_CoarseLODQualityMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 5; case 110: return 5; case 90: return 5; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_STATE_CoarseLODQualityMode_start 22 #define GFX12_SAMPLER_STATE_CoarseLODQualityMode_start 22 #define GFX11_SAMPLER_STATE_CoarseLODQualityMode_start 22 #define GFX9_SAMPLER_STATE_CoarseLODQualityMode_start 22 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_CoarseLODQualityMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 22; case 120: return 22; case 110: return 22; case 90: return 22; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_STATE::Cube Surface Control Mode */ #define GFX125_SAMPLER_STATE_CubeSurfaceControlMode_bits 1 #define GFX12_SAMPLER_STATE_CubeSurfaceControlMode_bits 1 #define GFX11_SAMPLER_STATE_CubeSurfaceControlMode_bits 1 #define GFX9_SAMPLER_STATE_CubeSurfaceControlMode_bits 1 #define GFX8_SAMPLER_STATE_CubeSurfaceControlMode_bits 1 #define GFX75_SAMPLER_STATE_CubeSurfaceControlMode_bits 1 #define GFX7_SAMPLER_STATE_CubeSurfaceControlMode_bits 1 #define GFX6_SAMPLER_STATE_CubeSurfaceControlMode_bits 1 #define GFX5_SAMPLER_STATE_CubeSurfaceControlMode_bits 1 #define GFX45_SAMPLER_STATE_CubeSurfaceControlMode_bits 1 #define GFX4_SAMPLER_STATE_CubeSurfaceControlMode_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_CubeSurfaceControlMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_STATE_CubeSurfaceControlMode_start 32 #define GFX12_SAMPLER_STATE_CubeSurfaceControlMode_start 32 #define GFX11_SAMPLER_STATE_CubeSurfaceControlMode_start 32 #define GFX9_SAMPLER_STATE_CubeSurfaceControlMode_start 32 #define GFX8_SAMPLER_STATE_CubeSurfaceControlMode_start 32 #define GFX75_SAMPLER_STATE_CubeSurfaceControlMode_start 32 #define GFX7_SAMPLER_STATE_CubeSurfaceControlMode_start 32 #define GFX6_SAMPLER_STATE_CubeSurfaceControlMode_start 41 #define GFX5_SAMPLER_STATE_CubeSurfaceControlMode_start 41 #define GFX45_SAMPLER_STATE_CubeSurfaceControlMode_start 41 #define GFX4_SAMPLER_STATE_CubeSurfaceControlMode_start 41 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_CubeSurfaceControlMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 41; case 50: return 41; case 45: return 41; case 40: return 41; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_STATE::Force gather4 Behavior */ #define GFX125_SAMPLER_STATE_Forcegather4Behavior_bits 1 #define GFX12_SAMPLER_STATE_Forcegather4Behavior_bits 1 #define GFX11_SAMPLER_STATE_Forcegather4Behavior_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_Forcegather4Behavior_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_STATE_Forcegather4Behavior_start 69 #define GFX12_SAMPLER_STATE_Forcegather4Behavior_start 69 #define GFX11_SAMPLER_STATE_Forcegather4Behavior_start 69 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_Forcegather4Behavior_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 69; case 120: return 69; case 110: return 69; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_STATE::LOD Clamp Magnification Mode */ #define GFX125_SAMPLER_STATE_LODClampMagnificationMode_bits 1 #define GFX12_SAMPLER_STATE_LODClampMagnificationMode_bits 1 #define GFX11_SAMPLER_STATE_LODClampMagnificationMode_bits 1 #define GFX9_SAMPLER_STATE_LODClampMagnificationMode_bits 1 #define GFX8_SAMPLER_STATE_LODClampMagnificationMode_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_LODClampMagnificationMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_STATE_LODClampMagnificationMode_start 64 #define GFX12_SAMPLER_STATE_LODClampMagnificationMode_start 64 #define GFX11_SAMPLER_STATE_LODClampMagnificationMode_start 64 #define GFX9_SAMPLER_STATE_LODClampMagnificationMode_start 64 #define GFX8_SAMPLER_STATE_LODClampMagnificationMode_start 64 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_LODClampMagnificationMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 64; case 80: return 64; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_STATE::LOD PreClamp Enable */ #define GFX75_SAMPLER_STATE_LODPreClampEnable_bits 1 #define GFX7_SAMPLER_STATE_LODPreClampEnable_bits 1 #define GFX6_SAMPLER_STATE_LODPreClampEnable_bits 1 #define GFX5_SAMPLER_STATE_LODPreClampEnable_bits 1 #define GFX45_SAMPLER_STATE_LODPreClampEnable_bits 1 #define GFX4_SAMPLER_STATE_LODPreClampEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_LODPreClampEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX75_SAMPLER_STATE_LODPreClampEnable_start 28 #define GFX7_SAMPLER_STATE_LODPreClampEnable_start 28 #define GFX6_SAMPLER_STATE_LODPreClampEnable_start 28 #define GFX5_SAMPLER_STATE_LODPreClampEnable_start 28 #define GFX45_SAMPLER_STATE_LODPreClampEnable_start 28 #define GFX4_SAMPLER_STATE_LODPreClampEnable_start 28 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_LODPreClampEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 28; case 70: return 28; case 60: return 28; case 50: return 28; case 45: return 28; case 40: return 28; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_STATE::LOD PreClamp Mode */ #define GFX125_SAMPLER_STATE_LODPreClampMode_bits 2 #define GFX12_SAMPLER_STATE_LODPreClampMode_bits 2 #define GFX11_SAMPLER_STATE_LODPreClampMode_bits 2 #define GFX9_SAMPLER_STATE_LODPreClampMode_bits 2 #define GFX8_SAMPLER_STATE_LODPreClampMode_bits 2 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_LODPreClampMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_STATE_LODPreClampMode_start 27 #define GFX12_SAMPLER_STATE_LODPreClampMode_start 27 #define GFX11_SAMPLER_STATE_LODPreClampMode_start 27 #define GFX9_SAMPLER_STATE_LODPreClampMode_start 27 #define GFX8_SAMPLER_STATE_LODPreClampMode_start 27 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_LODPreClampMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_STATE::Mag Mode Filter */ #define GFX125_SAMPLER_STATE_MagModeFilter_bits 3 #define GFX12_SAMPLER_STATE_MagModeFilter_bits 3 #define GFX11_SAMPLER_STATE_MagModeFilter_bits 3 #define GFX9_SAMPLER_STATE_MagModeFilter_bits 3 #define GFX8_SAMPLER_STATE_MagModeFilter_bits 3 #define GFX75_SAMPLER_STATE_MagModeFilter_bits 3 #define GFX7_SAMPLER_STATE_MagModeFilter_bits 3 #define GFX6_SAMPLER_STATE_MagModeFilter_bits 3 #define GFX5_SAMPLER_STATE_MagModeFilter_bits 3 #define GFX45_SAMPLER_STATE_MagModeFilter_bits 3 #define GFX4_SAMPLER_STATE_MagModeFilter_bits 3 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_MagModeFilter_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_STATE_MagModeFilter_start 17 #define GFX12_SAMPLER_STATE_MagModeFilter_start 17 #define GFX11_SAMPLER_STATE_MagModeFilter_start 17 #define GFX9_SAMPLER_STATE_MagModeFilter_start 17 #define GFX8_SAMPLER_STATE_MagModeFilter_start 17 #define GFX75_SAMPLER_STATE_MagModeFilter_start 17 #define GFX7_SAMPLER_STATE_MagModeFilter_start 17 #define GFX6_SAMPLER_STATE_MagModeFilter_start 17 #define GFX5_SAMPLER_STATE_MagModeFilter_start 17 #define GFX45_SAMPLER_STATE_MagModeFilter_start 17 #define GFX4_SAMPLER_STATE_MagModeFilter_start 17 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_MagModeFilter_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 17; case 120: return 17; case 110: return 17; case 90: return 17; case 80: return 17; case 75: return 17; case 70: return 17; case 60: return 17; case 50: return 17; case 45: return 17; case 40: return 17; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_STATE::Max LOD */ #define GFX125_SAMPLER_STATE_MaxLOD_bits 12 #define GFX12_SAMPLER_STATE_MaxLOD_bits 12 #define GFX11_SAMPLER_STATE_MaxLOD_bits 12 #define GFX9_SAMPLER_STATE_MaxLOD_bits 12 #define GFX8_SAMPLER_STATE_MaxLOD_bits 12 #define GFX75_SAMPLER_STATE_MaxLOD_bits 12 #define GFX7_SAMPLER_STATE_MaxLOD_bits 12 #define GFX6_SAMPLER_STATE_MaxLOD_bits 10 #define GFX5_SAMPLER_STATE_MaxLOD_bits 10 #define GFX45_SAMPLER_STATE_MaxLOD_bits 10 #define GFX4_SAMPLER_STATE_MaxLOD_bits 10 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_MaxLOD_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 12; case 120: return 12; case 110: return 12; case 90: return 12; case 80: return 12; case 75: return 12; case 70: return 12; case 60: return 10; case 50: return 10; case 45: return 10; case 40: return 10; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_STATE_MaxLOD_start 40 #define GFX12_SAMPLER_STATE_MaxLOD_start 40 #define GFX11_SAMPLER_STATE_MaxLOD_start 40 #define GFX9_SAMPLER_STATE_MaxLOD_start 40 #define GFX8_SAMPLER_STATE_MaxLOD_start 40 #define GFX75_SAMPLER_STATE_MaxLOD_start 40 #define GFX7_SAMPLER_STATE_MaxLOD_start 40 #define GFX6_SAMPLER_STATE_MaxLOD_start 44 #define GFX5_SAMPLER_STATE_MaxLOD_start 44 #define GFX45_SAMPLER_STATE_MaxLOD_start 44 #define GFX4_SAMPLER_STATE_MaxLOD_start 44 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_MaxLOD_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 40; case 120: return 40; case 110: return 40; case 90: return 40; case 80: return 40; case 75: return 40; case 70: return 40; case 60: return 44; case 50: return 44; case 45: return 44; case 40: return 44; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_STATE::Maximum Anisotropy */ #define GFX125_SAMPLER_STATE_MaximumAnisotropy_bits 3 #define GFX12_SAMPLER_STATE_MaximumAnisotropy_bits 3 #define GFX11_SAMPLER_STATE_MaximumAnisotropy_bits 3 #define GFX9_SAMPLER_STATE_MaximumAnisotropy_bits 3 #define GFX8_SAMPLER_STATE_MaximumAnisotropy_bits 3 #define GFX75_SAMPLER_STATE_MaximumAnisotropy_bits 3 #define GFX7_SAMPLER_STATE_MaximumAnisotropy_bits 3 #define GFX6_SAMPLER_STATE_MaximumAnisotropy_bits 3 #define GFX5_SAMPLER_STATE_MaximumAnisotropy_bits 3 #define GFX45_SAMPLER_STATE_MaximumAnisotropy_bits 3 #define GFX4_SAMPLER_STATE_MaximumAnisotropy_bits 3 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_MaximumAnisotropy_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_STATE_MaximumAnisotropy_start 115 #define GFX12_SAMPLER_STATE_MaximumAnisotropy_start 115 #define GFX11_SAMPLER_STATE_MaximumAnisotropy_start 115 #define GFX9_SAMPLER_STATE_MaximumAnisotropy_start 115 #define GFX8_SAMPLER_STATE_MaximumAnisotropy_start 115 #define GFX75_SAMPLER_STATE_MaximumAnisotropy_start 115 #define GFX7_SAMPLER_STATE_MaximumAnisotropy_start 115 #define GFX6_SAMPLER_STATE_MaximumAnisotropy_start 115 #define GFX5_SAMPLER_STATE_MaximumAnisotropy_start 115 #define GFX45_SAMPLER_STATE_MaximumAnisotropy_start 115 #define GFX4_SAMPLER_STATE_MaximumAnisotropy_start 115 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_MaximumAnisotropy_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 115; case 120: return 115; case 110: return 115; case 90: return 115; case 80: return 115; case 75: return 115; case 70: return 115; case 60: return 115; case 50: return 115; case 45: return 115; case 40: return 115; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_STATE::Min LOD */ #define GFX125_SAMPLER_STATE_MinLOD_bits 12 #define GFX12_SAMPLER_STATE_MinLOD_bits 12 #define GFX11_SAMPLER_STATE_MinLOD_bits 12 #define GFX9_SAMPLER_STATE_MinLOD_bits 12 #define GFX8_SAMPLER_STATE_MinLOD_bits 12 #define GFX75_SAMPLER_STATE_MinLOD_bits 12 #define GFX7_SAMPLER_STATE_MinLOD_bits 12 #define GFX6_SAMPLER_STATE_MinLOD_bits 10 #define GFX5_SAMPLER_STATE_MinLOD_bits 10 #define GFX45_SAMPLER_STATE_MinLOD_bits 10 #define GFX4_SAMPLER_STATE_MinLOD_bits 10 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_MinLOD_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 12; case 120: return 12; case 110: return 12; case 90: return 12; case 80: return 12; case 75: return 12; case 70: return 12; case 60: return 10; case 50: return 10; case 45: return 10; case 40: return 10; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_STATE_MinLOD_start 52 #define GFX12_SAMPLER_STATE_MinLOD_start 52 #define GFX11_SAMPLER_STATE_MinLOD_start 52 #define GFX9_SAMPLER_STATE_MinLOD_start 52 #define GFX8_SAMPLER_STATE_MinLOD_start 52 #define GFX75_SAMPLER_STATE_MinLOD_start 52 #define GFX7_SAMPLER_STATE_MinLOD_start 52 #define GFX6_SAMPLER_STATE_MinLOD_start 54 #define GFX5_SAMPLER_STATE_MinLOD_start 54 #define GFX45_SAMPLER_STATE_MinLOD_start 54 #define GFX4_SAMPLER_STATE_MinLOD_start 54 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_MinLOD_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 52; case 120: return 52; case 110: return 52; case 90: return 52; case 80: return 52; case 75: return 52; case 70: return 52; case 60: return 54; case 50: return 54; case 45: return 54; case 40: return 54; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_STATE::Min Mode Filter */ #define GFX125_SAMPLER_STATE_MinModeFilter_bits 3 #define GFX12_SAMPLER_STATE_MinModeFilter_bits 3 #define GFX11_SAMPLER_STATE_MinModeFilter_bits 3 #define GFX9_SAMPLER_STATE_MinModeFilter_bits 3 #define GFX8_SAMPLER_STATE_MinModeFilter_bits 3 #define GFX75_SAMPLER_STATE_MinModeFilter_bits 3 #define GFX7_SAMPLER_STATE_MinModeFilter_bits 3 #define GFX6_SAMPLER_STATE_MinModeFilter_bits 3 #define GFX5_SAMPLER_STATE_MinModeFilter_bits 3 #define GFX45_SAMPLER_STATE_MinModeFilter_bits 3 #define GFX4_SAMPLER_STATE_MinModeFilter_bits 3 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_MinModeFilter_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_STATE_MinModeFilter_start 14 #define GFX12_SAMPLER_STATE_MinModeFilter_start 14 #define GFX11_SAMPLER_STATE_MinModeFilter_start 14 #define GFX9_SAMPLER_STATE_MinModeFilter_start 14 #define GFX8_SAMPLER_STATE_MinModeFilter_start 14 #define GFX75_SAMPLER_STATE_MinModeFilter_start 14 #define GFX7_SAMPLER_STATE_MinModeFilter_start 14 #define GFX6_SAMPLER_STATE_MinModeFilter_start 14 #define GFX5_SAMPLER_STATE_MinModeFilter_start 14 #define GFX45_SAMPLER_STATE_MinModeFilter_start 14 #define GFX4_SAMPLER_STATE_MinModeFilter_start 14 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_MinModeFilter_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 14; case 120: return 14; case 110: return 14; case 90: return 14; case 80: return 14; case 75: return 14; case 70: return 14; case 60: return 14; case 50: return 14; case 45: return 14; case 40: return 14; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_STATE::Min and Mag State Not Equal */ #define GFX6_SAMPLER_STATE_MinandMagStateNotEqual_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_MinandMagStateNotEqual_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_SAMPLER_STATE_MinandMagStateNotEqual_start 27 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_MinandMagStateNotEqual_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 27; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_STATE::Mip Mode Filter */ #define GFX125_SAMPLER_STATE_MipModeFilter_bits 2 #define GFX12_SAMPLER_STATE_MipModeFilter_bits 2 #define GFX11_SAMPLER_STATE_MipModeFilter_bits 2 #define GFX9_SAMPLER_STATE_MipModeFilter_bits 2 #define GFX8_SAMPLER_STATE_MipModeFilter_bits 2 #define GFX75_SAMPLER_STATE_MipModeFilter_bits 2 #define GFX7_SAMPLER_STATE_MipModeFilter_bits 2 #define GFX6_SAMPLER_STATE_MipModeFilter_bits 2 #define GFX5_SAMPLER_STATE_MipModeFilter_bits 2 #define GFX45_SAMPLER_STATE_MipModeFilter_bits 2 #define GFX4_SAMPLER_STATE_MipModeFilter_bits 2 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_MipModeFilter_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 2; case 45: return 2; case 40: return 2; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_STATE_MipModeFilter_start 20 #define GFX12_SAMPLER_STATE_MipModeFilter_start 20 #define GFX11_SAMPLER_STATE_MipModeFilter_start 20 #define GFX9_SAMPLER_STATE_MipModeFilter_start 20 #define GFX8_SAMPLER_STATE_MipModeFilter_start 20 #define GFX75_SAMPLER_STATE_MipModeFilter_start 20 #define GFX7_SAMPLER_STATE_MipModeFilter_start 20 #define GFX6_SAMPLER_STATE_MipModeFilter_start 20 #define GFX5_SAMPLER_STATE_MipModeFilter_start 20 #define GFX45_SAMPLER_STATE_MipModeFilter_start 20 #define GFX4_SAMPLER_STATE_MipModeFilter_start 20 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_MipModeFilter_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 20; case 120: return 20; case 110: return 20; case 90: return 20; case 80: return 20; case 75: return 20; case 70: return 20; case 60: return 20; case 50: return 20; case 45: return 20; case 40: return 20; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_STATE::Monochrome Filter Height */ #define GFX5_SAMPLER_STATE_MonochromeFilterHeight_bits 3 #define GFX45_SAMPLER_STATE_MonochromeFilterHeight_bits 3 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_MonochromeFilterHeight_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 3; case 45: return 3; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX5_SAMPLER_STATE_MonochromeFilterHeight_start 125 #define GFX45_SAMPLER_STATE_MonochromeFilterHeight_start 125 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_MonochromeFilterHeight_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 125; case 45: return 125; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_STATE::Monochrome Filter Height: Reserved */ #define GFX6_SAMPLER_STATE_MonochromeFilterHeightReserved_bits 3 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_MonochromeFilterHeightReserved_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_SAMPLER_STATE_MonochromeFilterHeightReserved_start 125 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_MonochromeFilterHeightReserved_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 125; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_STATE::Monochrome Filter Width */ #define GFX6_SAMPLER_STATE_MonochromeFilterWidth_bits 3 #define GFX5_SAMPLER_STATE_MonochromeFilterWidth_bits 3 #define GFX45_SAMPLER_STATE_MonochromeFilterWidth_bits 3 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_MonochromeFilterWidth_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 3; case 50: return 3; case 45: return 3; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX6_SAMPLER_STATE_MonochromeFilterWidth_start 122 #define GFX5_SAMPLER_STATE_MonochromeFilterWidth_start 122 #define GFX45_SAMPLER_STATE_MonochromeFilterWidth_start 122 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_MonochromeFilterWidth_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 122; case 50: return 122; case 45: return 122; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_STATE::Non-normalized Coordinate Enable */ #define GFX125_SAMPLER_STATE_NonnormalizedCoordinateEnable_bits 1 #define GFX12_SAMPLER_STATE_NonnormalizedCoordinateEnable_bits 1 #define GFX11_SAMPLER_STATE_NonnormalizedCoordinateEnable_bits 1 #define GFX9_SAMPLER_STATE_NonnormalizedCoordinateEnable_bits 1 #define GFX8_SAMPLER_STATE_NonnormalizedCoordinateEnable_bits 1 #define GFX75_SAMPLER_STATE_NonnormalizedCoordinateEnable_bits 1 #define GFX7_SAMPLER_STATE_NonnormalizedCoordinateEnable_bits 1 #define GFX6_SAMPLER_STATE_NonnormalizedCoordinateEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_NonnormalizedCoordinateEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_STATE_NonnormalizedCoordinateEnable_start 106 #define GFX12_SAMPLER_STATE_NonnormalizedCoordinateEnable_start 106 #define GFX11_SAMPLER_STATE_NonnormalizedCoordinateEnable_start 106 #define GFX9_SAMPLER_STATE_NonnormalizedCoordinateEnable_start 106 #define GFX8_SAMPLER_STATE_NonnormalizedCoordinateEnable_start 106 #define GFX75_SAMPLER_STATE_NonnormalizedCoordinateEnable_start 106 #define GFX7_SAMPLER_STATE_NonnormalizedCoordinateEnable_start 106 #define GFX6_SAMPLER_STATE_NonnormalizedCoordinateEnable_start 96 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_NonnormalizedCoordinateEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 106; case 120: return 106; case 110: return 106; case 90: return 106; case 80: return 106; case 75: return 106; case 70: return 106; case 60: return 96; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_STATE::R Address Mag Filter Rounding Enable */ #define GFX125_SAMPLER_STATE_RAddressMagFilterRoundingEnable_bits 1 #define GFX12_SAMPLER_STATE_RAddressMagFilterRoundingEnable_bits 1 #define GFX11_SAMPLER_STATE_RAddressMagFilterRoundingEnable_bits 1 #define GFX9_SAMPLER_STATE_RAddressMagFilterRoundingEnable_bits 1 #define GFX8_SAMPLER_STATE_RAddressMagFilterRoundingEnable_bits 1 #define GFX75_SAMPLER_STATE_RAddressMagFilterRoundingEnable_bits 1 #define GFX7_SAMPLER_STATE_RAddressMagFilterRoundingEnable_bits 1 #define GFX6_SAMPLER_STATE_RAddressMagFilterRoundingEnable_bits 1 #define GFX5_SAMPLER_STATE_RAddressMagFilterRoundingEnable_bits 1 #define GFX45_SAMPLER_STATE_RAddressMagFilterRoundingEnable_bits 1 #define GFX4_SAMPLER_STATE_RAddressMagFilterRoundingEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_RAddressMagFilterRoundingEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_STATE_RAddressMagFilterRoundingEnable_start 110 #define GFX12_SAMPLER_STATE_RAddressMagFilterRoundingEnable_start 110 #define GFX11_SAMPLER_STATE_RAddressMagFilterRoundingEnable_start 110 #define GFX9_SAMPLER_STATE_RAddressMagFilterRoundingEnable_start 110 #define GFX8_SAMPLER_STATE_RAddressMagFilterRoundingEnable_start 110 #define GFX75_SAMPLER_STATE_RAddressMagFilterRoundingEnable_start 110 #define GFX7_SAMPLER_STATE_RAddressMagFilterRoundingEnable_start 110 #define GFX6_SAMPLER_STATE_RAddressMagFilterRoundingEnable_start 110 #define GFX5_SAMPLER_STATE_RAddressMagFilterRoundingEnable_start 110 #define GFX45_SAMPLER_STATE_RAddressMagFilterRoundingEnable_start 110 #define GFX4_SAMPLER_STATE_RAddressMagFilterRoundingEnable_start 110 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_RAddressMagFilterRoundingEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 110; case 120: return 110; case 110: return 110; case 90: return 110; case 80: return 110; case 75: return 110; case 70: return 110; case 60: return 110; case 50: return 110; case 45: return 110; case 40: return 110; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_STATE::R Address Min Filter Rounding Enable */ #define GFX125_SAMPLER_STATE_RAddressMinFilterRoundingEnable_bits 1 #define GFX12_SAMPLER_STATE_RAddressMinFilterRoundingEnable_bits 1 #define GFX11_SAMPLER_STATE_RAddressMinFilterRoundingEnable_bits 1 #define GFX9_SAMPLER_STATE_RAddressMinFilterRoundingEnable_bits 1 #define GFX8_SAMPLER_STATE_RAddressMinFilterRoundingEnable_bits 1 #define GFX75_SAMPLER_STATE_RAddressMinFilterRoundingEnable_bits 1 #define GFX7_SAMPLER_STATE_RAddressMinFilterRoundingEnable_bits 1 #define GFX6_SAMPLER_STATE_RAddressMinFilterRoundingEnable_bits 1 #define GFX5_SAMPLER_STATE_RAddressMinFilterRoundingEnable_bits 1 #define GFX45_SAMPLER_STATE_RAddressMinFilterRoundingEnable_bits 1 #define GFX4_SAMPLER_STATE_RAddressMinFilterRoundingEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_RAddressMinFilterRoundingEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_STATE_RAddressMinFilterRoundingEnable_start 109 #define GFX12_SAMPLER_STATE_RAddressMinFilterRoundingEnable_start 109 #define GFX11_SAMPLER_STATE_RAddressMinFilterRoundingEnable_start 109 #define GFX9_SAMPLER_STATE_RAddressMinFilterRoundingEnable_start 109 #define GFX8_SAMPLER_STATE_RAddressMinFilterRoundingEnable_start 109 #define GFX75_SAMPLER_STATE_RAddressMinFilterRoundingEnable_start 109 #define GFX7_SAMPLER_STATE_RAddressMinFilterRoundingEnable_start 109 #define GFX6_SAMPLER_STATE_RAddressMinFilterRoundingEnable_start 109 #define GFX5_SAMPLER_STATE_RAddressMinFilterRoundingEnable_start 109 #define GFX45_SAMPLER_STATE_RAddressMinFilterRoundingEnable_start 109 #define GFX4_SAMPLER_STATE_RAddressMinFilterRoundingEnable_start 109 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_RAddressMinFilterRoundingEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 109; case 120: return 109; case 110: return 109; case 90: return 109; case 80: return 109; case 75: return 109; case 70: return 109; case 60: return 109; case 50: return 109; case 45: return 109; case 40: return 109; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_STATE::Reduction Type */ #define GFX125_SAMPLER_STATE_ReductionType_bits 2 #define GFX12_SAMPLER_STATE_ReductionType_bits 2 #define GFX11_SAMPLER_STATE_ReductionType_bits 2 #define GFX9_SAMPLER_STATE_ReductionType_bits 2 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_ReductionType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_STATE_ReductionType_start 118 #define GFX12_SAMPLER_STATE_ReductionType_start 118 #define GFX11_SAMPLER_STATE_ReductionType_start 118 #define GFX9_SAMPLER_STATE_ReductionType_start 118 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_ReductionType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 118; case 120: return 118; case 110: return 118; case 90: return 118; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_STATE::Reduction Type Enable */ #define GFX125_SAMPLER_STATE_ReductionTypeEnable_bits 1 #define GFX12_SAMPLER_STATE_ReductionTypeEnable_bits 1 #define GFX11_SAMPLER_STATE_ReductionTypeEnable_bits 1 #define GFX9_SAMPLER_STATE_ReductionTypeEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_ReductionTypeEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_STATE_ReductionTypeEnable_start 105 #define GFX12_SAMPLER_STATE_ReductionTypeEnable_start 105 #define GFX11_SAMPLER_STATE_ReductionTypeEnable_start 105 #define GFX9_SAMPLER_STATE_ReductionTypeEnable_start 105 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_ReductionTypeEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 105; case 120: return 105; case 110: return 105; case 90: return 105; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_STATE::Return Filter Weight for Border Texels */ #define GFX125_SAMPLER_STATE_ReturnFilterWeightforBorderTexels_bits 1 #define GFX12_SAMPLER_STATE_ReturnFilterWeightforBorderTexels_bits 1 #define GFX11_SAMPLER_STATE_ReturnFilterWeightforBorderTexels_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_ReturnFilterWeightforBorderTexels_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_STATE_ReturnFilterWeightforBorderTexels_start 67 #define GFX12_SAMPLER_STATE_ReturnFilterWeightforBorderTexels_start 67 #define GFX11_SAMPLER_STATE_ReturnFilterWeightforBorderTexels_start 67 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_ReturnFilterWeightforBorderTexels_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 67; case 120: return 67; case 110: return 67; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_STATE::Return Filter Weight for Null Texels */ #define GFX125_SAMPLER_STATE_ReturnFilterWeightforNullTexels_bits 1 #define GFX12_SAMPLER_STATE_ReturnFilterWeightforNullTexels_bits 1 #define GFX11_SAMPLER_STATE_ReturnFilterWeightforNullTexels_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_ReturnFilterWeightforNullTexels_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_STATE_ReturnFilterWeightforNullTexels_start 66 #define GFX12_SAMPLER_STATE_ReturnFilterWeightforNullTexels_start 66 #define GFX11_SAMPLER_STATE_ReturnFilterWeightforNullTexels_start 66 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_ReturnFilterWeightforNullTexels_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 66; case 120: return 66; case 110: return 66; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_STATE::SRGB DECODE */ #define GFX125_SAMPLER_STATE_SRGBDECODE_bits 1 #define GFX12_SAMPLER_STATE_SRGBDECODE_bits 1 #define GFX11_SAMPLER_STATE_SRGBDECODE_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_SRGBDECODE_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_STATE_SRGBDECODE_start 65 #define GFX12_SAMPLER_STATE_SRGBDECODE_start 65 #define GFX11_SAMPLER_STATE_SRGBDECODE_start 65 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_SRGBDECODE_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 65; case 120: return 65; case 110: return 65; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_STATE::Sampler Disable */ #define GFX125_SAMPLER_STATE_SamplerDisable_bits 1 #define GFX12_SAMPLER_STATE_SamplerDisable_bits 1 #define GFX11_SAMPLER_STATE_SamplerDisable_bits 1 #define GFX9_SAMPLER_STATE_SamplerDisable_bits 1 #define GFX8_SAMPLER_STATE_SamplerDisable_bits 1 #define GFX75_SAMPLER_STATE_SamplerDisable_bits 1 #define GFX7_SAMPLER_STATE_SamplerDisable_bits 1 #define GFX6_SAMPLER_STATE_SamplerDisable_bits 1 #define GFX5_SAMPLER_STATE_SamplerDisable_bits 1 #define GFX45_SAMPLER_STATE_SamplerDisable_bits 1 #define GFX4_SAMPLER_STATE_SamplerDisable_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_SamplerDisable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_STATE_SamplerDisable_start 31 #define GFX12_SAMPLER_STATE_SamplerDisable_start 31 #define GFX11_SAMPLER_STATE_SamplerDisable_start 31 #define GFX9_SAMPLER_STATE_SamplerDisable_start 31 #define GFX8_SAMPLER_STATE_SamplerDisable_start 31 #define GFX75_SAMPLER_STATE_SamplerDisable_start 31 #define GFX7_SAMPLER_STATE_SamplerDisable_start 31 #define GFX6_SAMPLER_STATE_SamplerDisable_start 31 #define GFX5_SAMPLER_STATE_SamplerDisable_start 31 #define GFX45_SAMPLER_STATE_SamplerDisable_start 31 #define GFX4_SAMPLER_STATE_SamplerDisable_start 31 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_SamplerDisable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 31; case 120: return 31; case 110: return 31; case 90: return 31; case 80: return 31; case 75: return 31; case 70: return 31; case 60: return 31; case 50: return 31; case 45: return 31; case 40: return 31; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_STATE::Shadow Function */ #define GFX125_SAMPLER_STATE_ShadowFunction_bits 3 #define GFX12_SAMPLER_STATE_ShadowFunction_bits 3 #define GFX11_SAMPLER_STATE_ShadowFunction_bits 3 #define GFX9_SAMPLER_STATE_ShadowFunction_bits 3 #define GFX8_SAMPLER_STATE_ShadowFunction_bits 3 #define GFX75_SAMPLER_STATE_ShadowFunction_bits 3 #define GFX7_SAMPLER_STATE_ShadowFunction_bits 3 #define GFX6_SAMPLER_STATE_ShadowFunction_bits 3 #define GFX5_SAMPLER_STATE_ShadowFunction_bits 3 #define GFX45_SAMPLER_STATE_ShadowFunction_bits 3 #define GFX4_SAMPLER_STATE_ShadowFunction_bits 3 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_ShadowFunction_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_STATE_ShadowFunction_start 33 #define GFX12_SAMPLER_STATE_ShadowFunction_start 33 #define GFX11_SAMPLER_STATE_ShadowFunction_start 33 #define GFX9_SAMPLER_STATE_ShadowFunction_start 33 #define GFX8_SAMPLER_STATE_ShadowFunction_start 33 #define GFX75_SAMPLER_STATE_ShadowFunction_start 33 #define GFX7_SAMPLER_STATE_ShadowFunction_start 33 #define GFX6_SAMPLER_STATE_ShadowFunction_start 0 #define GFX5_SAMPLER_STATE_ShadowFunction_start 0 #define GFX45_SAMPLER_STATE_ShadowFunction_start 0 #define GFX4_SAMPLER_STATE_ShadowFunction_start 0 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_ShadowFunction_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 33; case 120: return 33; case 110: return 33; case 90: return 33; case 80: return 33; case 75: return 33; case 70: return 33; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_STATE::TCX Address Control Mode */ #define GFX125_SAMPLER_STATE_TCXAddressControlMode_bits 3 #define GFX12_SAMPLER_STATE_TCXAddressControlMode_bits 3 #define GFX11_SAMPLER_STATE_TCXAddressControlMode_bits 3 #define GFX9_SAMPLER_STATE_TCXAddressControlMode_bits 3 #define GFX8_SAMPLER_STATE_TCXAddressControlMode_bits 3 #define GFX75_SAMPLER_STATE_TCXAddressControlMode_bits 3 #define GFX7_SAMPLER_STATE_TCXAddressControlMode_bits 3 #define GFX6_SAMPLER_STATE_TCXAddressControlMode_bits 3 #define GFX5_SAMPLER_STATE_TCXAddressControlMode_bits 3 #define GFX45_SAMPLER_STATE_TCXAddressControlMode_bits 3 #define GFX4_SAMPLER_STATE_TCXAddressControlMode_bits 3 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_TCXAddressControlMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_STATE_TCXAddressControlMode_start 102 #define GFX12_SAMPLER_STATE_TCXAddressControlMode_start 102 #define GFX11_SAMPLER_STATE_TCXAddressControlMode_start 102 #define GFX9_SAMPLER_STATE_TCXAddressControlMode_start 102 #define GFX8_SAMPLER_STATE_TCXAddressControlMode_start 102 #define GFX75_SAMPLER_STATE_TCXAddressControlMode_start 102 #define GFX7_SAMPLER_STATE_TCXAddressControlMode_start 102 #define GFX6_SAMPLER_STATE_TCXAddressControlMode_start 38 #define GFX5_SAMPLER_STATE_TCXAddressControlMode_start 38 #define GFX45_SAMPLER_STATE_TCXAddressControlMode_start 38 #define GFX4_SAMPLER_STATE_TCXAddressControlMode_start 38 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_TCXAddressControlMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 102; case 120: return 102; case 110: return 102; case 90: return 102; case 80: return 102; case 75: return 102; case 70: return 102; case 60: return 38; case 50: return 38; case 45: return 38; case 40: return 38; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_STATE::TCY Address Control Mode */ #define GFX125_SAMPLER_STATE_TCYAddressControlMode_bits 3 #define GFX12_SAMPLER_STATE_TCYAddressControlMode_bits 3 #define GFX11_SAMPLER_STATE_TCYAddressControlMode_bits 3 #define GFX9_SAMPLER_STATE_TCYAddressControlMode_bits 3 #define GFX8_SAMPLER_STATE_TCYAddressControlMode_bits 3 #define GFX75_SAMPLER_STATE_TCYAddressControlMode_bits 3 #define GFX7_SAMPLER_STATE_TCYAddressControlMode_bits 3 #define GFX6_SAMPLER_STATE_TCYAddressControlMode_bits 3 #define GFX5_SAMPLER_STATE_TCYAddressControlMode_bits 3 #define GFX45_SAMPLER_STATE_TCYAddressControlMode_bits 3 #define GFX4_SAMPLER_STATE_TCYAddressControlMode_bits 3 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_TCYAddressControlMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_STATE_TCYAddressControlMode_start 99 #define GFX12_SAMPLER_STATE_TCYAddressControlMode_start 99 #define GFX11_SAMPLER_STATE_TCYAddressControlMode_start 99 #define GFX9_SAMPLER_STATE_TCYAddressControlMode_start 99 #define GFX8_SAMPLER_STATE_TCYAddressControlMode_start 99 #define GFX75_SAMPLER_STATE_TCYAddressControlMode_start 99 #define GFX7_SAMPLER_STATE_TCYAddressControlMode_start 99 #define GFX6_SAMPLER_STATE_TCYAddressControlMode_start 35 #define GFX5_SAMPLER_STATE_TCYAddressControlMode_start 35 #define GFX45_SAMPLER_STATE_TCYAddressControlMode_start 35 #define GFX4_SAMPLER_STATE_TCYAddressControlMode_start 35 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_TCYAddressControlMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 99; case 120: return 99; case 110: return 99; case 90: return 99; case 80: return 99; case 75: return 99; case 70: return 99; case 60: return 35; case 50: return 35; case 45: return 35; case 40: return 35; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_STATE::TCZ Address Control Mode */ #define GFX125_SAMPLER_STATE_TCZAddressControlMode_bits 3 #define GFX12_SAMPLER_STATE_TCZAddressControlMode_bits 3 #define GFX11_SAMPLER_STATE_TCZAddressControlMode_bits 3 #define GFX9_SAMPLER_STATE_TCZAddressControlMode_bits 3 #define GFX8_SAMPLER_STATE_TCZAddressControlMode_bits 3 #define GFX75_SAMPLER_STATE_TCZAddressControlMode_bits 3 #define GFX7_SAMPLER_STATE_TCZAddressControlMode_bits 3 #define GFX6_SAMPLER_STATE_TCZAddressControlMode_bits 3 #define GFX5_SAMPLER_STATE_TCZAddressControlMode_bits 3 #define GFX45_SAMPLER_STATE_TCZAddressControlMode_bits 3 #define GFX4_SAMPLER_STATE_TCZAddressControlMode_bits 3 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_TCZAddressControlMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_STATE_TCZAddressControlMode_start 96 #define GFX12_SAMPLER_STATE_TCZAddressControlMode_start 96 #define GFX11_SAMPLER_STATE_TCZAddressControlMode_start 96 #define GFX9_SAMPLER_STATE_TCZAddressControlMode_start 96 #define GFX8_SAMPLER_STATE_TCZAddressControlMode_start 96 #define GFX75_SAMPLER_STATE_TCZAddressControlMode_start 96 #define GFX7_SAMPLER_STATE_TCZAddressControlMode_start 96 #define GFX6_SAMPLER_STATE_TCZAddressControlMode_start 32 #define GFX5_SAMPLER_STATE_TCZAddressControlMode_start 32 #define GFX45_SAMPLER_STATE_TCZAddressControlMode_start 32 #define GFX4_SAMPLER_STATE_TCZAddressControlMode_start 32 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_TCZAddressControlMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 96; case 120: return 96; case 110: return 96; case 90: return 96; case 80: return 96; case 75: return 96; case 70: return 96; case 60: return 32; case 50: return 32; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_STATE::Texture Border Color Mode */ #define GFX125_SAMPLER_STATE_TextureBorderColorMode_bits 1 #define GFX12_SAMPLER_STATE_TextureBorderColorMode_bits 1 #define GFX11_SAMPLER_STATE_TextureBorderColorMode_bits 1 #define GFX9_SAMPLER_STATE_TextureBorderColorMode_bits 1 #define GFX8_SAMPLER_STATE_TextureBorderColorMode_bits 1 #define GFX75_SAMPLER_STATE_TextureBorderColorMode_bits 1 #define GFX7_SAMPLER_STATE_TextureBorderColorMode_bits 1 #define GFX6_SAMPLER_STATE_TextureBorderColorMode_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_TextureBorderColorMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_STATE_TextureBorderColorMode_start 29 #define GFX12_SAMPLER_STATE_TextureBorderColorMode_start 29 #define GFX11_SAMPLER_STATE_TextureBorderColorMode_start 29 #define GFX9_SAMPLER_STATE_TextureBorderColorMode_start 29 #define GFX8_SAMPLER_STATE_TextureBorderColorMode_start 29 #define GFX75_SAMPLER_STATE_TextureBorderColorMode_start 29 #define GFX7_SAMPLER_STATE_TextureBorderColorMode_start 29 #define GFX6_SAMPLER_STATE_TextureBorderColorMode_start 29 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_TextureBorderColorMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 29; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_STATE::Texture LOD Bias */ #define GFX125_SAMPLER_STATE_TextureLODBias_bits 13 #define GFX12_SAMPLER_STATE_TextureLODBias_bits 13 #define GFX11_SAMPLER_STATE_TextureLODBias_bits 13 #define GFX9_SAMPLER_STATE_TextureLODBias_bits 13 #define GFX8_SAMPLER_STATE_TextureLODBias_bits 13 #define GFX75_SAMPLER_STATE_TextureLODBias_bits 13 #define GFX7_SAMPLER_STATE_TextureLODBias_bits 13 #define GFX6_SAMPLER_STATE_TextureLODBias_bits 11 #define GFX5_SAMPLER_STATE_TextureLODBias_bits 11 #define GFX45_SAMPLER_STATE_TextureLODBias_bits 11 #define GFX4_SAMPLER_STATE_TextureLODBias_bits 11 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_TextureLODBias_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 13; case 120: return 13; case 110: return 13; case 90: return 13; case 80: return 13; case 75: return 13; case 70: return 13; case 60: return 11; case 50: return 11; case 45: return 11; case 40: return 11; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_STATE_TextureLODBias_start 1 #define GFX12_SAMPLER_STATE_TextureLODBias_start 1 #define GFX11_SAMPLER_STATE_TextureLODBias_start 1 #define GFX9_SAMPLER_STATE_TextureLODBias_start 1 #define GFX8_SAMPLER_STATE_TextureLODBias_start 1 #define GFX75_SAMPLER_STATE_TextureLODBias_start 1 #define GFX7_SAMPLER_STATE_TextureLODBias_start 1 #define GFX6_SAMPLER_STATE_TextureLODBias_start 3 #define GFX5_SAMPLER_STATE_TextureLODBias_start 3 #define GFX45_SAMPLER_STATE_TextureLODBias_start 3 #define GFX4_SAMPLER_STATE_TextureLODBias_start 3 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_TextureLODBias_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 3; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_STATE::Trilinear Filter Quality */ #define GFX125_SAMPLER_STATE_TrilinearFilterQuality_bits 2 #define GFX12_SAMPLER_STATE_TrilinearFilterQuality_bits 2 #define GFX11_SAMPLER_STATE_TrilinearFilterQuality_bits 2 #define GFX9_SAMPLER_STATE_TrilinearFilterQuality_bits 2 #define GFX8_SAMPLER_STATE_TrilinearFilterQuality_bits 2 #define GFX75_SAMPLER_STATE_TrilinearFilterQuality_bits 2 #define GFX7_SAMPLER_STATE_TrilinearFilterQuality_bits 2 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_TrilinearFilterQuality_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_STATE_TrilinearFilterQuality_start 107 #define GFX12_SAMPLER_STATE_TrilinearFilterQuality_start 107 #define GFX11_SAMPLER_STATE_TrilinearFilterQuality_start 107 #define GFX9_SAMPLER_STATE_TrilinearFilterQuality_start 107 #define GFX8_SAMPLER_STATE_TrilinearFilterQuality_start 107 #define GFX75_SAMPLER_STATE_TrilinearFilterQuality_start 107 #define GFX7_SAMPLER_STATE_TrilinearFilterQuality_start 107 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_TrilinearFilterQuality_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 107; case 120: return 107; case 110: return 107; case 90: return 107; case 80: return 107; case 75: return 107; case 70: return 107; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_STATE::U Address Mag Filter Rounding Enable */ #define GFX125_SAMPLER_STATE_UAddressMagFilterRoundingEnable_bits 1 #define GFX12_SAMPLER_STATE_UAddressMagFilterRoundingEnable_bits 1 #define GFX11_SAMPLER_STATE_UAddressMagFilterRoundingEnable_bits 1 #define GFX9_SAMPLER_STATE_UAddressMagFilterRoundingEnable_bits 1 #define GFX8_SAMPLER_STATE_UAddressMagFilterRoundingEnable_bits 1 #define GFX75_SAMPLER_STATE_UAddressMagFilterRoundingEnable_bits 1 #define GFX7_SAMPLER_STATE_UAddressMagFilterRoundingEnable_bits 1 #define GFX6_SAMPLER_STATE_UAddressMagFilterRoundingEnable_bits 1 #define GFX5_SAMPLER_STATE_UAddressMagFilterRoundingEnable_bits 1 #define GFX45_SAMPLER_STATE_UAddressMagFilterRoundingEnable_bits 1 #define GFX4_SAMPLER_STATE_UAddressMagFilterRoundingEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_UAddressMagFilterRoundingEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_STATE_UAddressMagFilterRoundingEnable_start 114 #define GFX12_SAMPLER_STATE_UAddressMagFilterRoundingEnable_start 114 #define GFX11_SAMPLER_STATE_UAddressMagFilterRoundingEnable_start 114 #define GFX9_SAMPLER_STATE_UAddressMagFilterRoundingEnable_start 114 #define GFX8_SAMPLER_STATE_UAddressMagFilterRoundingEnable_start 114 #define GFX75_SAMPLER_STATE_UAddressMagFilterRoundingEnable_start 114 #define GFX7_SAMPLER_STATE_UAddressMagFilterRoundingEnable_start 114 #define GFX6_SAMPLER_STATE_UAddressMagFilterRoundingEnable_start 114 #define GFX5_SAMPLER_STATE_UAddressMagFilterRoundingEnable_start 114 #define GFX45_SAMPLER_STATE_UAddressMagFilterRoundingEnable_start 114 #define GFX4_SAMPLER_STATE_UAddressMagFilterRoundingEnable_start 114 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_UAddressMagFilterRoundingEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 114; case 120: return 114; case 110: return 114; case 90: return 114; case 80: return 114; case 75: return 114; case 70: return 114; case 60: return 114; case 50: return 114; case 45: return 114; case 40: return 114; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_STATE::U Address Min Filter Rounding Enable */ #define GFX125_SAMPLER_STATE_UAddressMinFilterRoundingEnable_bits 1 #define GFX12_SAMPLER_STATE_UAddressMinFilterRoundingEnable_bits 1 #define GFX11_SAMPLER_STATE_UAddressMinFilterRoundingEnable_bits 1 #define GFX9_SAMPLER_STATE_UAddressMinFilterRoundingEnable_bits 1 #define GFX8_SAMPLER_STATE_UAddressMinFilterRoundingEnable_bits 1 #define GFX75_SAMPLER_STATE_UAddressMinFilterRoundingEnable_bits 1 #define GFX7_SAMPLER_STATE_UAddressMinFilterRoundingEnable_bits 1 #define GFX6_SAMPLER_STATE_UAddressMinFilterRoundingEnable_bits 1 #define GFX5_SAMPLER_STATE_UAddressMinFilterRoundingEnable_bits 1 #define GFX45_SAMPLER_STATE_UAddressMinFilterRoundingEnable_bits 1 #define GFX4_SAMPLER_STATE_UAddressMinFilterRoundingEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_UAddressMinFilterRoundingEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_STATE_UAddressMinFilterRoundingEnable_start 113 #define GFX12_SAMPLER_STATE_UAddressMinFilterRoundingEnable_start 113 #define GFX11_SAMPLER_STATE_UAddressMinFilterRoundingEnable_start 113 #define GFX9_SAMPLER_STATE_UAddressMinFilterRoundingEnable_start 113 #define GFX8_SAMPLER_STATE_UAddressMinFilterRoundingEnable_start 113 #define GFX75_SAMPLER_STATE_UAddressMinFilterRoundingEnable_start 113 #define GFX7_SAMPLER_STATE_UAddressMinFilterRoundingEnable_start 113 #define GFX6_SAMPLER_STATE_UAddressMinFilterRoundingEnable_start 113 #define GFX5_SAMPLER_STATE_UAddressMinFilterRoundingEnable_start 113 #define GFX45_SAMPLER_STATE_UAddressMinFilterRoundingEnable_start 113 #define GFX4_SAMPLER_STATE_UAddressMinFilterRoundingEnable_start 113 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_UAddressMinFilterRoundingEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 113; case 120: return 113; case 110: return 113; case 90: return 113; case 80: return 113; case 75: return 113; case 70: return 113; case 60: return 113; case 50: return 113; case 45: return 113; case 40: return 113; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_STATE::V Address Mag Filter Rounding Enable */ #define GFX125_SAMPLER_STATE_VAddressMagFilterRoundingEnable_bits 1 #define GFX12_SAMPLER_STATE_VAddressMagFilterRoundingEnable_bits 1 #define GFX11_SAMPLER_STATE_VAddressMagFilterRoundingEnable_bits 1 #define GFX9_SAMPLER_STATE_VAddressMagFilterRoundingEnable_bits 1 #define GFX8_SAMPLER_STATE_VAddressMagFilterRoundingEnable_bits 1 #define GFX75_SAMPLER_STATE_VAddressMagFilterRoundingEnable_bits 1 #define GFX7_SAMPLER_STATE_VAddressMagFilterRoundingEnable_bits 1 #define GFX6_SAMPLER_STATE_VAddressMagFilterRoundingEnable_bits 1 #define GFX5_SAMPLER_STATE_VAddressMagFilterRoundingEnable_bits 1 #define GFX45_SAMPLER_STATE_VAddressMagFilterRoundingEnable_bits 1 #define GFX4_SAMPLER_STATE_VAddressMagFilterRoundingEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_VAddressMagFilterRoundingEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_STATE_VAddressMagFilterRoundingEnable_start 112 #define GFX12_SAMPLER_STATE_VAddressMagFilterRoundingEnable_start 112 #define GFX11_SAMPLER_STATE_VAddressMagFilterRoundingEnable_start 112 #define GFX9_SAMPLER_STATE_VAddressMagFilterRoundingEnable_start 112 #define GFX8_SAMPLER_STATE_VAddressMagFilterRoundingEnable_start 112 #define GFX75_SAMPLER_STATE_VAddressMagFilterRoundingEnable_start 112 #define GFX7_SAMPLER_STATE_VAddressMagFilterRoundingEnable_start 112 #define GFX6_SAMPLER_STATE_VAddressMagFilterRoundingEnable_start 112 #define GFX5_SAMPLER_STATE_VAddressMagFilterRoundingEnable_start 112 #define GFX45_SAMPLER_STATE_VAddressMagFilterRoundingEnable_start 112 #define GFX4_SAMPLER_STATE_VAddressMagFilterRoundingEnable_start 112 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_VAddressMagFilterRoundingEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 112; case 120: return 112; case 110: return 112; case 90: return 112; case 80: return 112; case 75: return 112; case 70: return 112; case 60: return 112; case 50: return 112; case 45: return 112; case 40: return 112; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_STATE::V Address Min Filter Rounding Enable */ #define GFX125_SAMPLER_STATE_VAddressMinFilterRoundingEnable_bits 1 #define GFX12_SAMPLER_STATE_VAddressMinFilterRoundingEnable_bits 1 #define GFX11_SAMPLER_STATE_VAddressMinFilterRoundingEnable_bits 1 #define GFX9_SAMPLER_STATE_VAddressMinFilterRoundingEnable_bits 1 #define GFX8_SAMPLER_STATE_VAddressMinFilterRoundingEnable_bits 1 #define GFX75_SAMPLER_STATE_VAddressMinFilterRoundingEnable_bits 1 #define GFX7_SAMPLER_STATE_VAddressMinFilterRoundingEnable_bits 1 #define GFX6_SAMPLER_STATE_VAddressMinFilterRoundingEnable_bits 1 #define GFX5_SAMPLER_STATE_VAddressMinFilterRoundingEnable_bits 1 #define GFX45_SAMPLER_STATE_VAddressMinFilterRoundingEnable_bits 1 #define GFX4_SAMPLER_STATE_VAddressMinFilterRoundingEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_VAddressMinFilterRoundingEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX125_SAMPLER_STATE_VAddressMinFilterRoundingEnable_start 111 #define GFX12_SAMPLER_STATE_VAddressMinFilterRoundingEnable_start 111 #define GFX11_SAMPLER_STATE_VAddressMinFilterRoundingEnable_start 111 #define GFX9_SAMPLER_STATE_VAddressMinFilterRoundingEnable_start 111 #define GFX8_SAMPLER_STATE_VAddressMinFilterRoundingEnable_start 111 #define GFX75_SAMPLER_STATE_VAddressMinFilterRoundingEnable_start 111 #define GFX7_SAMPLER_STATE_VAddressMinFilterRoundingEnable_start 111 #define GFX6_SAMPLER_STATE_VAddressMinFilterRoundingEnable_start 111 #define GFX5_SAMPLER_STATE_VAddressMinFilterRoundingEnable_start 111 #define GFX45_SAMPLER_STATE_VAddressMinFilterRoundingEnable_start 111 #define GFX4_SAMPLER_STATE_VAddressMinFilterRoundingEnable_start 111 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_VAddressMinFilterRoundingEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 111; case 120: return 111; case 110: return 111; case 90: return 111; case 80: return 111; case 75: return 111; case 70: return 111; case 60: return 111; case 50: return 111; case 45: return 111; case 40: return 111; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_STATE_8X8_AVS_COEFFICIENTS */ #define GFX125_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_length 8 #define GFX12_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_length 8 #define GFX11_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_length 8 #define GFX9_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_length 8 #define GFX8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_length 8 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_8X8_AVS_COEFFICIENTS_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_STATE_8X8_AVS_COEFFICIENTS::Table 0X Filter Coefficient[n,0] */ #define GFX8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn0_bits 8 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn0_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn0_start 0 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn0_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_STATE_8X8_AVS_COEFFICIENTS::Table 0X Filter Coefficient[n,1] */ #define GFX8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn1_bits 8 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn1_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn1_start 16 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn1_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 16; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_STATE_8X8_AVS_COEFFICIENTS::Table 0X Filter Coefficient[n,2] */ #define GFX8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn2_bits 8 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn2_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn2_start 32 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn2_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 32; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_STATE_8X8_AVS_COEFFICIENTS::Table 0X Filter Coefficient[n,3] */ #define GFX8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn3_bits 8 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn3_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn3_start 48 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn3_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 48; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_STATE_8X8_AVS_COEFFICIENTS::Table 0X Filter Coefficient[n,4] */ #define GFX8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn4_bits 8 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn4_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn4_start 64 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn4_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 64; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_STATE_8X8_AVS_COEFFICIENTS::Table 0X Filter Coefficient[n,5] */ #define GFX8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn5_bits 8 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn5_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn5_start 80 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn5_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 80; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_STATE_8X8_AVS_COEFFICIENTS::Table 0X Filter Coefficient[n,6] */ #define GFX8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn6_bits 8 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn6_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn6_start 96 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn6_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 96; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_STATE_8X8_AVS_COEFFICIENTS::Table 0X Filter Coefficient[n,7] */ #define GFX8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn7_bits 8 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn7_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn7_start 112 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn7_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 112; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_STATE_8X8_AVS_COEFFICIENTS::Table 0Y Filter Coefficient[n,0] */ #define GFX8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn0_bits 8 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn0_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn0_start 8 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn0_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_STATE_8X8_AVS_COEFFICIENTS::Table 0Y Filter Coefficient[n,1] */ #define GFX8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn1_bits 8 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn1_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn1_start 24 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn1_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 24; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_STATE_8X8_AVS_COEFFICIENTS::Table 0Y Filter Coefficient[n,2] */ #define GFX8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn2_bits 8 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn2_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn2_start 40 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn2_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 40; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_STATE_8X8_AVS_COEFFICIENTS::Table 0Y Filter Coefficient[n,3] */ #define GFX8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn3_bits 8 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn3_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn3_start 56 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn3_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 56; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_STATE_8X8_AVS_COEFFICIENTS::Table 0Y Filter Coefficient[n,4] */ #define GFX8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn4_bits 8 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn4_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn4_start 72 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn4_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 72; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_STATE_8X8_AVS_COEFFICIENTS::Table 0Y Filter Coefficient[n,5] */ #define GFX8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn5_bits 8 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn5_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn5_start 88 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn5_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 88; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_STATE_8X8_AVS_COEFFICIENTS::Table 0Y Filter Coefficient[n,6] */ #define GFX8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn6_bits 8 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn6_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn6_start 104 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn6_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 104; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_STATE_8X8_AVS_COEFFICIENTS::Table 0Y Filter Coefficient[n,7] */ #define GFX8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn7_bits 8 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn7_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn7_start 120 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn7_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 120; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_STATE_8X8_AVS_COEFFICIENTS::Table 1X Filter Coefficient[n,2] */ #define GFX8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1XFilterCoefficientn2_bits 8 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1XFilterCoefficientn2_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1XFilterCoefficientn2_start 144 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1XFilterCoefficientn2_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 144; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_STATE_8X8_AVS_COEFFICIENTS::Table 1X Filter Coefficient[n,3] */ #define GFX8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1XFilterCoefficientn3_bits 8 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1XFilterCoefficientn3_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1XFilterCoefficientn3_start 152 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1XFilterCoefficientn3_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 152; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_STATE_8X8_AVS_COEFFICIENTS::Table 1X Filter Coefficient[n,4] */ #define GFX8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1XFilterCoefficientn4_bits 8 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1XFilterCoefficientn4_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1XFilterCoefficientn4_start 160 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1XFilterCoefficientn4_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 160; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_STATE_8X8_AVS_COEFFICIENTS::Table 1X Filter Coefficient[n,5] */ #define GFX8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1XFilterCoefficientn5_bits 8 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1XFilterCoefficientn5_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1XFilterCoefficientn5_start 168 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1XFilterCoefficientn5_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 168; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_STATE_8X8_AVS_COEFFICIENTS::Table 1Y Filter Coefficient[n,2] */ #define GFX8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1YFilterCoefficientn2_bits 8 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1YFilterCoefficientn2_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1YFilterCoefficientn2_start 208 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1YFilterCoefficientn2_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 208; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_STATE_8X8_AVS_COEFFICIENTS::Table 1Y Filter Coefficient[n,3] */ #define GFX8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1YFilterCoefficientn3_bits 8 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1YFilterCoefficientn3_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1YFilterCoefficientn3_start 216 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1YFilterCoefficientn3_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 216; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_STATE_8X8_AVS_COEFFICIENTS::Table 1Y Filter Coefficient[n,4] */ #define GFX8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1YFilterCoefficientn4_bits 8 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1YFilterCoefficientn4_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1YFilterCoefficientn4_start 224 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1YFilterCoefficientn4_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 224; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SAMPLER_STATE_8X8_AVS_COEFFICIENTS::Table 1Y Filter Coefficient[n,5] */ #define GFX8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1YFilterCoefficientn5_bits 8 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1YFilterCoefficientn5_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1YFilterCoefficientn5_start 232 static inline uint32_t ATTRIBUTE_PURE SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1YFilterCoefficientn5_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 232; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SCISSOR_RECT */ #define GFX125_SCISSOR_RECT_length 2 #define GFX12_SCISSOR_RECT_length 2 #define GFX11_SCISSOR_RECT_length 2 #define GFX9_SCISSOR_RECT_length 2 #define GFX8_SCISSOR_RECT_length 2 #define GFX75_SCISSOR_RECT_length 2 #define GFX7_SCISSOR_RECT_length 2 #define GFX6_SCISSOR_RECT_length 2 #define GFX5_SCISSOR_RECT_length 2 #define GFX45_SCISSOR_RECT_length 2 #define GFX4_SCISSOR_RECT_length 2 static inline uint32_t ATTRIBUTE_PURE SCISSOR_RECT_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 2; case 45: return 2; case 40: return 2; default: unreachable("Invalid hardware generation"); } } /* SCISSOR_RECT::Scissor Rectangle X Max */ #define GFX125_SCISSOR_RECT_ScissorRectangleXMax_bits 16 #define GFX12_SCISSOR_RECT_ScissorRectangleXMax_bits 16 #define GFX11_SCISSOR_RECT_ScissorRectangleXMax_bits 16 #define GFX9_SCISSOR_RECT_ScissorRectangleXMax_bits 16 #define GFX8_SCISSOR_RECT_ScissorRectangleXMax_bits 16 #define GFX75_SCISSOR_RECT_ScissorRectangleXMax_bits 16 #define GFX7_SCISSOR_RECT_ScissorRectangleXMax_bits 16 #define GFX6_SCISSOR_RECT_ScissorRectangleXMax_bits 16 #define GFX5_SCISSOR_RECT_ScissorRectangleXMax_bits 16 #define GFX45_SCISSOR_RECT_ScissorRectangleXMax_bits 16 #define GFX4_SCISSOR_RECT_ScissorRectangleXMax_bits 16 static inline uint32_t ATTRIBUTE_PURE SCISSOR_RECT_ScissorRectangleXMax_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 16; case 50: return 16; case 45: return 16; case 40: return 16; default: unreachable("Invalid hardware generation"); } } #define GFX125_SCISSOR_RECT_ScissorRectangleXMax_start 32 #define GFX12_SCISSOR_RECT_ScissorRectangleXMax_start 32 #define GFX11_SCISSOR_RECT_ScissorRectangleXMax_start 32 #define GFX9_SCISSOR_RECT_ScissorRectangleXMax_start 32 #define GFX8_SCISSOR_RECT_ScissorRectangleXMax_start 32 #define GFX75_SCISSOR_RECT_ScissorRectangleXMax_start 32 #define GFX7_SCISSOR_RECT_ScissorRectangleXMax_start 32 #define GFX6_SCISSOR_RECT_ScissorRectangleXMax_start 32 #define GFX5_SCISSOR_RECT_ScissorRectangleXMax_start 32 #define GFX45_SCISSOR_RECT_ScissorRectangleXMax_start 32 #define GFX4_SCISSOR_RECT_ScissorRectangleXMax_start 32 static inline uint32_t ATTRIBUTE_PURE SCISSOR_RECT_ScissorRectangleXMax_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 32; case 50: return 32; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } /* SCISSOR_RECT::Scissor Rectangle X Min */ #define GFX125_SCISSOR_RECT_ScissorRectangleXMin_bits 16 #define GFX12_SCISSOR_RECT_ScissorRectangleXMin_bits 16 #define GFX11_SCISSOR_RECT_ScissorRectangleXMin_bits 16 #define GFX9_SCISSOR_RECT_ScissorRectangleXMin_bits 16 #define GFX8_SCISSOR_RECT_ScissorRectangleXMin_bits 16 #define GFX75_SCISSOR_RECT_ScissorRectangleXMin_bits 16 #define GFX7_SCISSOR_RECT_ScissorRectangleXMin_bits 16 #define GFX6_SCISSOR_RECT_ScissorRectangleXMin_bits 16 #define GFX5_SCISSOR_RECT_ScissorRectangleXMin_bits 16 #define GFX45_SCISSOR_RECT_ScissorRectangleXMin_bits 16 #define GFX4_SCISSOR_RECT_ScissorRectangleXMin_bits 16 static inline uint32_t ATTRIBUTE_PURE SCISSOR_RECT_ScissorRectangleXMin_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 16; case 50: return 16; case 45: return 16; case 40: return 16; default: unreachable("Invalid hardware generation"); } } #define GFX125_SCISSOR_RECT_ScissorRectangleXMin_start 0 #define GFX12_SCISSOR_RECT_ScissorRectangleXMin_start 0 #define GFX11_SCISSOR_RECT_ScissorRectangleXMin_start 0 #define GFX9_SCISSOR_RECT_ScissorRectangleXMin_start 0 #define GFX8_SCISSOR_RECT_ScissorRectangleXMin_start 0 #define GFX75_SCISSOR_RECT_ScissorRectangleXMin_start 0 #define GFX7_SCISSOR_RECT_ScissorRectangleXMin_start 0 #define GFX6_SCISSOR_RECT_ScissorRectangleXMin_start 0 #define GFX5_SCISSOR_RECT_ScissorRectangleXMin_start 0 #define GFX45_SCISSOR_RECT_ScissorRectangleXMin_start 0 #define GFX4_SCISSOR_RECT_ScissorRectangleXMin_start 0 static inline uint32_t ATTRIBUTE_PURE SCISSOR_RECT_ScissorRectangleXMin_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SCISSOR_RECT::Scissor Rectangle Y Max */ #define GFX125_SCISSOR_RECT_ScissorRectangleYMax_bits 16 #define GFX12_SCISSOR_RECT_ScissorRectangleYMax_bits 16 #define GFX11_SCISSOR_RECT_ScissorRectangleYMax_bits 16 #define GFX9_SCISSOR_RECT_ScissorRectangleYMax_bits 16 #define GFX8_SCISSOR_RECT_ScissorRectangleYMax_bits 16 #define GFX75_SCISSOR_RECT_ScissorRectangleYMax_bits 16 #define GFX7_SCISSOR_RECT_ScissorRectangleYMax_bits 16 #define GFX6_SCISSOR_RECT_ScissorRectangleYMax_bits 16 #define GFX5_SCISSOR_RECT_ScissorRectangleYMax_bits 16 #define GFX45_SCISSOR_RECT_ScissorRectangleYMax_bits 16 #define GFX4_SCISSOR_RECT_ScissorRectangleYMax_bits 16 static inline uint32_t ATTRIBUTE_PURE SCISSOR_RECT_ScissorRectangleYMax_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 16; case 50: return 16; case 45: return 16; case 40: return 16; default: unreachable("Invalid hardware generation"); } } #define GFX125_SCISSOR_RECT_ScissorRectangleYMax_start 48 #define GFX12_SCISSOR_RECT_ScissorRectangleYMax_start 48 #define GFX11_SCISSOR_RECT_ScissorRectangleYMax_start 48 #define GFX9_SCISSOR_RECT_ScissorRectangleYMax_start 48 #define GFX8_SCISSOR_RECT_ScissorRectangleYMax_start 48 #define GFX75_SCISSOR_RECT_ScissorRectangleYMax_start 48 #define GFX7_SCISSOR_RECT_ScissorRectangleYMax_start 48 #define GFX6_SCISSOR_RECT_ScissorRectangleYMax_start 48 #define GFX5_SCISSOR_RECT_ScissorRectangleYMax_start 48 #define GFX45_SCISSOR_RECT_ScissorRectangleYMax_start 48 #define GFX4_SCISSOR_RECT_ScissorRectangleYMax_start 48 static inline uint32_t ATTRIBUTE_PURE SCISSOR_RECT_ScissorRectangleYMax_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 48; case 120: return 48; case 110: return 48; case 90: return 48; case 80: return 48; case 75: return 48; case 70: return 48; case 60: return 48; case 50: return 48; case 45: return 48; case 40: return 48; default: unreachable("Invalid hardware generation"); } } /* SCISSOR_RECT::Scissor Rectangle Y Min */ #define GFX125_SCISSOR_RECT_ScissorRectangleYMin_bits 16 #define GFX12_SCISSOR_RECT_ScissorRectangleYMin_bits 16 #define GFX11_SCISSOR_RECT_ScissorRectangleYMin_bits 16 #define GFX9_SCISSOR_RECT_ScissorRectangleYMin_bits 16 #define GFX8_SCISSOR_RECT_ScissorRectangleYMin_bits 16 #define GFX75_SCISSOR_RECT_ScissorRectangleYMin_bits 16 #define GFX7_SCISSOR_RECT_ScissorRectangleYMin_bits 16 #define GFX6_SCISSOR_RECT_ScissorRectangleYMin_bits 16 #define GFX5_SCISSOR_RECT_ScissorRectangleYMin_bits 16 #define GFX45_SCISSOR_RECT_ScissorRectangleYMin_bits 16 #define GFX4_SCISSOR_RECT_ScissorRectangleYMin_bits 16 static inline uint32_t ATTRIBUTE_PURE SCISSOR_RECT_ScissorRectangleYMin_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 16; case 50: return 16; case 45: return 16; case 40: return 16; default: unreachable("Invalid hardware generation"); } } #define GFX125_SCISSOR_RECT_ScissorRectangleYMin_start 16 #define GFX12_SCISSOR_RECT_ScissorRectangleYMin_start 16 #define GFX11_SCISSOR_RECT_ScissorRectangleYMin_start 16 #define GFX9_SCISSOR_RECT_ScissorRectangleYMin_start 16 #define GFX8_SCISSOR_RECT_ScissorRectangleYMin_start 16 #define GFX75_SCISSOR_RECT_ScissorRectangleYMin_start 16 #define GFX7_SCISSOR_RECT_ScissorRectangleYMin_start 16 #define GFX6_SCISSOR_RECT_ScissorRectangleYMin_start 16 #define GFX5_SCISSOR_RECT_ScissorRectangleYMin_start 16 #define GFX45_SCISSOR_RECT_ScissorRectangleYMin_start 16 #define GFX4_SCISSOR_RECT_ScissorRectangleYMin_start 16 static inline uint32_t ATTRIBUTE_PURE SCISSOR_RECT_ScissorRectangleYMin_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 16; case 50: return 16; case 45: return 16; case 40: return 16; default: unreachable("Invalid hardware generation"); } } /* SCRATCH1 */ #define GFX75_SCRATCH1_length 1 static inline uint32_t ATTRIBUTE_PURE SCRATCH1_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SCRATCH1::L3 Atomic Disable */ #define GFX75_SCRATCH1_L3AtomicDisable_bits 1 static inline uint32_t ATTRIBUTE_PURE SCRATCH1_L3AtomicDisable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_SCRATCH1_L3AtomicDisable_start 27 static inline uint32_t ATTRIBUTE_PURE SCRATCH1_L3AtomicDisable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 27; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SC_INSTDONE */ #define GFX125_SC_INSTDONE_length 1 #define GFX12_SC_INSTDONE_length 1 #define GFX11_SC_INSTDONE_length 1 #define GFX9_SC_INSTDONE_length 1 #define GFX8_SC_INSTDONE_length 1 #define GFX75_SC_INSTDONE_length 1 #define GFX7_SC_INSTDONE_length 1 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SC_INSTDONE::AMFS Done */ #define GFX125_SC_INSTDONE_AMFSDone_bits 1 #define GFX12_SC_INSTDONE_AMFSDone_bits 1 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_AMFSDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SC_INSTDONE_AMFSDone_start 27 #define GFX12_SC_INSTDONE_AMFSDone_start 27 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_AMFSDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SC_INSTDONE::DAPB Done */ #define GFX125_SC_INSTDONE_DAPBDone_bits 1 #define GFX12_SC_INSTDONE_DAPBDone_bits 1 #define GFX11_SC_INSTDONE_DAPBDone_bits 1 #define GFX9_SC_INSTDONE_DAPBDone_bits 1 #define GFX8_SC_INSTDONE_DAPBDone_bits 1 #define GFX75_SC_INSTDONE_DAPBDone_bits 1 #define GFX7_SC_INSTDONE_DAPBDone_bits 1 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_DAPBDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SC_INSTDONE_DAPBDone_start 12 #define GFX12_SC_INSTDONE_DAPBDone_start 12 #define GFX11_SC_INSTDONE_DAPBDone_start 12 #define GFX9_SC_INSTDONE_DAPBDone_start 12 #define GFX8_SC_INSTDONE_DAPBDone_start 12 #define GFX75_SC_INSTDONE_DAPBDone_start 12 #define GFX7_SC_INSTDONE_DAPBDone_start 12 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_DAPBDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 12; case 120: return 12; case 110: return 12; case 90: return 12; case 80: return 12; case 75: return 12; case 70: return 12; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SC_INSTDONE::DAPRBE Done */ #define GFX125_SC_INSTDONE_DAPRBEDone_bits 1 #define GFX12_SC_INSTDONE_DAPRBEDone_bits 1 #define GFX11_SC_INSTDONE_DAPRBEDone_bits 1 #define GFX9_SC_INSTDONE_DAPRBEDone_bits 1 #define GFX8_SC_INSTDONE_DAPRBEDone_bits 1 #define GFX75_SC_INSTDONE_DAPRBEDone_bits 1 #define GFX7_SC_INSTDONE_DAPRBEDone_bits 1 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_DAPRBEDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SC_INSTDONE_DAPRBEDone_start 13 #define GFX12_SC_INSTDONE_DAPRBEDone_start 13 #define GFX11_SC_INSTDONE_DAPRBEDone_start 13 #define GFX9_SC_INSTDONE_DAPRBEDone_start 13 #define GFX8_SC_INSTDONE_DAPRBEDone_start 13 #define GFX75_SC_INSTDONE_DAPRBEDone_start 13 #define GFX7_SC_INSTDONE_DAPRBEDone_start 13 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_DAPRBEDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 13; case 120: return 13; case 110: return 13; case 90: return 13; case 80: return 13; case 75: return 13; case 70: return 13; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SC_INSTDONE::DC0 Done */ #define GFX125_SC_INSTDONE_DC0Done_bits 1 #define GFX12_SC_INSTDONE_DC0Done_bits 1 #define GFX11_SC_INSTDONE_DC0Done_bits 1 #define GFX9_SC_INSTDONE_DC0Done_bits 1 #define GFX8_SC_INSTDONE_DC0Done_bits 1 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_DC0Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SC_INSTDONE_DC0Done_start 16 #define GFX12_SC_INSTDONE_DC0Done_start 16 #define GFX11_SC_INSTDONE_DC0Done_start 16 #define GFX9_SC_INSTDONE_DC0Done_start 16 #define GFX8_SC_INSTDONE_DC0Done_start 16 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_DC0Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SC_INSTDONE::DC1 Done */ #define GFX125_SC_INSTDONE_DC1Done_bits 1 #define GFX12_SC_INSTDONE_DC1Done_bits 1 #define GFX11_SC_INSTDONE_DC1Done_bits 1 #define GFX9_SC_INSTDONE_DC1Done_bits 1 #define GFX8_SC_INSTDONE_DC1Done_bits 1 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_DC1Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SC_INSTDONE_DC1Done_start 17 #define GFX12_SC_INSTDONE_DC1Done_start 17 #define GFX11_SC_INSTDONE_DC1Done_start 17 #define GFX9_SC_INSTDONE_DC1Done_start 17 #define GFX8_SC_INSTDONE_DC1Done_start 17 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_DC1Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 17; case 120: return 17; case 110: return 17; case 90: return 17; case 80: return 17; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SC_INSTDONE::DC2 Done */ #define GFX125_SC_INSTDONE_DC2Done_bits 1 #define GFX12_SC_INSTDONE_DC2Done_bits 1 #define GFX11_SC_INSTDONE_DC2Done_bits 1 #define GFX9_SC_INSTDONE_DC2Done_bits 1 #define GFX8_SC_INSTDONE_DC2Done_bits 1 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_DC2Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SC_INSTDONE_DC2Done_start 18 #define GFX12_SC_INSTDONE_DC2Done_start 18 #define GFX11_SC_INSTDONE_DC2Done_start 18 #define GFX9_SC_INSTDONE_DC2Done_start 18 #define GFX8_SC_INSTDONE_DC2Done_start 18 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_DC2Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 18; case 120: return 18; case 110: return 18; case 90: return 18; case 80: return 18; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SC_INSTDONE::DC3 Done */ #define GFX125_SC_INSTDONE_DC3Done_bits 1 #define GFX11_SC_INSTDONE_DC3Done_bits 1 #define GFX9_SC_INSTDONE_DC3Done_bits 1 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_DC3Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SC_INSTDONE_DC3Done_start 19 #define GFX11_SC_INSTDONE_DC3Done_start 19 #define GFX9_SC_INSTDONE_DC3Done_start 19 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_DC3Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 19; case 120: return 0; case 110: return 19; case 90: return 19; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SC_INSTDONE::GW0 Done */ #define GFX125_SC_INSTDONE_GW0Done_bits 1 #define GFX12_SC_INSTDONE_GW0Done_bits 1 #define GFX11_SC_INSTDONE_GW0Done_bits 1 #define GFX9_SC_INSTDONE_GW0Done_bits 1 #define GFX8_SC_INSTDONE_GW0Done_bits 1 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_GW0Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SC_INSTDONE_GW0Done_start 20 #define GFX12_SC_INSTDONE_GW0Done_start 20 #define GFX11_SC_INSTDONE_GW0Done_start 20 #define GFX9_SC_INSTDONE_GW0Done_start 20 #define GFX8_SC_INSTDONE_GW0Done_start 20 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_GW0Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 20; case 120: return 20; case 110: return 20; case 90: return 20; case 80: return 20; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SC_INSTDONE::GW1 Done */ #define GFX125_SC_INSTDONE_GW1Done_bits 1 #define GFX12_SC_INSTDONE_GW1Done_bits 1 #define GFX11_SC_INSTDONE_GW1Done_bits 1 #define GFX9_SC_INSTDONE_GW1Done_bits 1 #define GFX8_SC_INSTDONE_GW1Done_bits 1 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_GW1Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SC_INSTDONE_GW1Done_start 21 #define GFX12_SC_INSTDONE_GW1Done_start 21 #define GFX11_SC_INSTDONE_GW1Done_start 21 #define GFX9_SC_INSTDONE_GW1Done_start 21 #define GFX8_SC_INSTDONE_GW1Done_start 21 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_GW1Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 21; case 120: return 21; case 110: return 21; case 90: return 21; case 80: return 21; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SC_INSTDONE::GW2 Done */ #define GFX125_SC_INSTDONE_GW2Done_bits 1 #define GFX12_SC_INSTDONE_GW2Done_bits 1 #define GFX11_SC_INSTDONE_GW2Done_bits 1 #define GFX9_SC_INSTDONE_GW2Done_bits 1 #define GFX8_SC_INSTDONE_GW2Done_bits 1 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_GW2Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SC_INSTDONE_GW2Done_start 22 #define GFX12_SC_INSTDONE_GW2Done_start 22 #define GFX11_SC_INSTDONE_GW2Done_start 22 #define GFX9_SC_INSTDONE_GW2Done_start 22 #define GFX8_SC_INSTDONE_GW2Done_start 22 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_GW2Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 22; case 120: return 22; case 110: return 22; case 90: return 22; case 80: return 22; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SC_INSTDONE::GW3 Done */ #define GFX125_SC_INSTDONE_GW3Done_bits 1 #define GFX11_SC_INSTDONE_GW3Done_bits 1 #define GFX9_SC_INSTDONE_GW3Done_bits 1 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_GW3Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SC_INSTDONE_GW3Done_start 23 #define GFX11_SC_INSTDONE_GW3Done_start 23 #define GFX9_SC_INSTDONE_GW3Done_start 23 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_GW3Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 23; case 120: return 0; case 110: return 23; case 90: return 23; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SC_INSTDONE::HIZ Done */ #define GFX125_SC_INSTDONE_HIZDone_bits 1 #define GFX12_SC_INSTDONE_HIZDone_bits 1 #define GFX11_SC_INSTDONE_HIZDone_bits 1 #define GFX9_SC_INSTDONE_HIZDone_bits 1 #define GFX8_SC_INSTDONE_HIZDone_bits 1 #define GFX75_SC_INSTDONE_HIZDone_bits 1 #define GFX7_SC_INSTDONE_HIZDone_bits 1 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_HIZDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SC_INSTDONE_HIZDone_start 3 #define GFX12_SC_INSTDONE_HIZDone_start 3 #define GFX11_SC_INSTDONE_HIZDone_start 3 #define GFX9_SC_INSTDONE_HIZDone_start 3 #define GFX8_SC_INSTDONE_HIZDone_start 3 #define GFX75_SC_INSTDONE_HIZDone_start 3 #define GFX7_SC_INSTDONE_HIZDone_start 3 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_HIZDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SC_INSTDONE::IECP Done */ #define GFX7_SC_INSTDONE_IECPDone_bits 1 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_IECPDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX7_SC_INSTDONE_IECPDone_start 14 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_IECPDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 14; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SC_INSTDONE::IZBE Done 0 */ #define GFX12_SC_INSTDONE_IZBEDone0_bits 1 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_IZBEDone0_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_SC_INSTDONE_IZBEDone0_start 4 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_IZBEDone0_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 4; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SC_INSTDONE::IZ Done */ #define GFX11_SC_INSTDONE_IZDone_bits 1 #define GFX9_SC_INSTDONE_IZDone_bits 1 #define GFX8_SC_INSTDONE_IZDone_bits 1 #define GFX75_SC_INSTDONE_IZDone_bits 1 #define GFX7_SC_INSTDONE_IZDone_bits 1 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_IZDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX11_SC_INSTDONE_IZDone_start 5 #define GFX9_SC_INSTDONE_IZDone_start 5 #define GFX8_SC_INSTDONE_IZDone_start 5 #define GFX75_SC_INSTDONE_IZDone_start 5 #define GFX7_SC_INSTDONE_IZDone_start 5 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_IZDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 5; case 90: return 5; case 80: return 5; case 75: return 5; case 70: return 5; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SC_INSTDONE::IZFE Done */ #define GFX125_SC_INSTDONE_IZFEDone_bits 1 #define GFX12_SC_INSTDONE_IZFEDone_bits 1 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_IZFEDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SC_INSTDONE_IZFEDone_start 5 #define GFX12_SC_INSTDONE_IZFEDone_start 5 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_IZFEDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 5; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SC_INSTDONE::PSS Done */ #define GFX12_SC_INSTDONE_PSSDone_bits 1 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_PSSDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX12_SC_INSTDONE_PSSDone_start 26 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_PSSDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 26; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SC_INSTDONE::RCC Done */ #define GFX125_SC_INSTDONE_RCCDone_bits 1 #define GFX12_SC_INSTDONE_RCCDone_bits 1 #define GFX11_SC_INSTDONE_RCCDone_bits 1 #define GFX9_SC_INSTDONE_RCCDone_bits 1 #define GFX8_SC_INSTDONE_RCCDone_bits 1 #define GFX75_SC_INSTDONE_RCCDone_bits 1 #define GFX7_SC_INSTDONE_RCCDone_bits 1 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_RCCDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SC_INSTDONE_RCCDone_start 9 #define GFX12_SC_INSTDONE_RCCDone_start 9 #define GFX11_SC_INSTDONE_RCCDone_start 9 #define GFX9_SC_INSTDONE_RCCDone_start 9 #define GFX8_SC_INSTDONE_RCCDone_start 9 #define GFX75_SC_INSTDONE_RCCDone_start 9 #define GFX7_SC_INSTDONE_RCCDone_start 9 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_RCCDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 9; case 120: return 9; case 110: return 9; case 90: return 9; case 80: return 9; case 75: return 9; case 70: return 9; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SC_INSTDONE::RCPBE Done */ #define GFX125_SC_INSTDONE_RCPBEDone_bits 1 #define GFX12_SC_INSTDONE_RCPBEDone_bits 1 #define GFX11_SC_INSTDONE_RCPBEDone_bits 1 #define GFX9_SC_INSTDONE_RCPBEDone_bits 1 #define GFX8_SC_INSTDONE_RCPBEDone_bits 1 #define GFX75_SC_INSTDONE_RCPBEDone_bits 1 #define GFX7_SC_INSTDONE_RCPBEDone_bits 1 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_RCPBEDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SC_INSTDONE_RCPBEDone_start 10 #define GFX12_SC_INSTDONE_RCPBEDone_start 10 #define GFX11_SC_INSTDONE_RCPBEDone_start 10 #define GFX9_SC_INSTDONE_RCPBEDone_start 10 #define GFX8_SC_INSTDONE_RCPBEDone_start 10 #define GFX75_SC_INSTDONE_RCPBEDone_start 10 #define GFX7_SC_INSTDONE_RCPBEDone_start 10 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_RCPBEDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 10; case 120: return 10; case 110: return 10; case 90: return 10; case 80: return 10; case 75: return 10; case 70: return 10; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SC_INSTDONE::RCPFE Done */ #define GFX125_SC_INSTDONE_RCPFEDone_bits 1 #define GFX12_SC_INSTDONE_RCPFEDone_bits 1 #define GFX11_SC_INSTDONE_RCPFEDone_bits 1 #define GFX9_SC_INSTDONE_RCPFEDone_bits 1 #define GFX8_SC_INSTDONE_RCPFEDone_bits 1 #define GFX75_SC_INSTDONE_RCPFEDone_bits 1 #define GFX7_SC_INSTDONE_RCPFEDone_bits 1 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_RCPFEDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SC_INSTDONE_RCPFEDone_start 11 #define GFX12_SC_INSTDONE_RCPFEDone_start 11 #define GFX11_SC_INSTDONE_RCPFEDone_start 11 #define GFX9_SC_INSTDONE_RCPFEDone_start 11 #define GFX8_SC_INSTDONE_RCPFEDone_start 11 #define GFX75_SC_INSTDONE_RCPFEDone_start 11 #define GFX7_SC_INSTDONE_RCPFEDone_start 11 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_RCPFEDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 11; case 120: return 11; case 110: return 11; case 90: return 11; case 80: return 11; case 75: return 11; case 70: return 11; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SC_INSTDONE::RCZ Done */ #define GFX11_SC_INSTDONE_RCZDone_bits 1 #define GFX9_SC_INSTDONE_RCZDone_bits 1 #define GFX8_SC_INSTDONE_RCZDone_bits 1 #define GFX75_SC_INSTDONE_RCZDone_bits 1 #define GFX7_SC_INSTDONE_RCZDone_bits 1 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_RCZDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX11_SC_INSTDONE_RCZDone_start 8 #define GFX9_SC_INSTDONE_RCZDone_start 8 #define GFX8_SC_INSTDONE_RCZDone_start 8 #define GFX75_SC_INSTDONE_RCZDone_start 8 #define GFX7_SC_INSTDONE_RCZDone_start 8 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_RCZDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SC_INSTDONE::SARB Done */ #define GFX125_SC_INSTDONE_SARBDone_bits 1 #define GFX12_SC_INSTDONE_SARBDone_bits 1 #define GFX11_SC_INSTDONE_SARBDone_bits 1 #define GFX9_SC_INSTDONE_SARBDone_bits 1 #define GFX8_SC_INSTDONE_SARBDone_bits 1 #define GFX75_SC_INSTDONE_SARBDone_bits 1 #define GFX7_SC_INSTDONE_SARBDone_bits 1 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_SARBDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SC_INSTDONE_SARBDone_start 15 #define GFX12_SC_INSTDONE_SARBDone_start 15 #define GFX11_SC_INSTDONE_SARBDone_start 15 #define GFX9_SC_INSTDONE_SARBDone_start 15 #define GFX8_SC_INSTDONE_SARBDone_start 15 #define GFX75_SC_INSTDONE_SARBDone_start 15 #define GFX7_SC_INSTDONE_SARBDone_start 15 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_SARBDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 15; case 120: return 15; case 110: return 15; case 90: return 15; case 80: return 15; case 75: return 15; case 70: return 15; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SC_INSTDONE::SBE Done */ #define GFX125_SC_INSTDONE_SBEDone_bits 1 #define GFX12_SC_INSTDONE_SBEDone_bits 1 #define GFX11_SC_INSTDONE_SBEDone_bits 1 #define GFX9_SC_INSTDONE_SBEDone_bits 1 #define GFX8_SC_INSTDONE_SBEDone_bits 1 #define GFX75_SC_INSTDONE_SBEDone_bits 1 #define GFX7_SC_INSTDONE_SBEDone_bits 1 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_SBEDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SC_INSTDONE_SBEDone_start 6 #define GFX12_SC_INSTDONE_SBEDone_start 6 #define GFX11_SC_INSTDONE_SBEDone_start 6 #define GFX9_SC_INSTDONE_SBEDone_start 6 #define GFX8_SC_INSTDONE_SBEDone_start 6 #define GFX75_SC_INSTDONE_SBEDone_start 6 #define GFX7_SC_INSTDONE_SBEDone_start 6 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_SBEDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 6; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SC_INSTDONE::SFBE Done */ #define GFX125_SC_INSTDONE_SFBEDone_bits 1 #define GFX12_SC_INSTDONE_SFBEDone_bits 1 #define GFX11_SC_INSTDONE_SFBEDone_bits 1 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_SFBEDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SC_INSTDONE_SFBEDone_start 25 #define GFX12_SC_INSTDONE_SFBEDone_start 25 #define GFX11_SC_INSTDONE_SFBEDone_start 25 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_SFBEDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 25; case 120: return 25; case 110: return 25; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SC_INSTDONE::STC Done */ #define GFX11_SC_INSTDONE_STCDone_bits 1 #define GFX9_SC_INSTDONE_STCDone_bits 1 #define GFX8_SC_INSTDONE_STCDone_bits 1 #define GFX75_SC_INSTDONE_STCDone_bits 1 #define GFX7_SC_INSTDONE_STCDone_bits 1 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_STCDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX11_SC_INSTDONE_STCDone_start 4 #define GFX9_SC_INSTDONE_STCDone_start 4 #define GFX8_SC_INSTDONE_STCDone_start 4 #define GFX75_SC_INSTDONE_STCDone_start 4 #define GFX7_SC_INSTDONE_STCDone_start 4 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_STCDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 4; case 70: return 4; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SC_INSTDONE::SVL Done */ #define GFX125_SC_INSTDONE_SVLDone_bits 1 #define GFX12_SC_INSTDONE_SVLDone_bits 1 #define GFX11_SC_INSTDONE_SVLDone_bits 1 #define GFX9_SC_INSTDONE_SVLDone_bits 1 #define GFX8_SC_INSTDONE_SVLDone_bits 1 #define GFX75_SC_INSTDONE_SVLDone_bits 1 #define GFX7_SC_INSTDONE_SVLDone_bits 1 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_SVLDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SC_INSTDONE_SVLDone_start 0 #define GFX12_SC_INSTDONE_SVLDone_start 0 #define GFX11_SC_INSTDONE_SVLDone_start 0 #define GFX9_SC_INSTDONE_SVLDone_start 0 #define GFX8_SC_INSTDONE_SVLDone_start 0 #define GFX75_SC_INSTDONE_SVLDone_start 0 #define GFX7_SC_INSTDONE_SVLDone_start 0 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_SVLDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SC_INSTDONE::TDC Done */ #define GFX125_SC_INSTDONE_TDCDone_bits 1 #define GFX12_SC_INSTDONE_TDCDone_bits 1 #define GFX11_SC_INSTDONE_TDCDone_bits 1 #define GFX9_SC_INSTDONE_TDCDone_bits 1 #define GFX8_SC_INSTDONE_TDCDone_bits 1 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_TDCDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SC_INSTDONE_TDCDone_start 24 #define GFX12_SC_INSTDONE_TDCDone_start 24 #define GFX11_SC_INSTDONE_TDCDone_start 24 #define GFX9_SC_INSTDONE_TDCDone_start 24 #define GFX8_SC_INSTDONE_TDCDone_start 24 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_TDCDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SC_INSTDONE::VSC Done */ #define GFX7_SC_INSTDONE_VSCDone_bits 1 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_VSCDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX7_SC_INSTDONE_VSCDone_start 16 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_VSCDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 16; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SC_INSTDONE::WMBE Done */ #define GFX125_SC_INSTDONE_WMBEDone_bits 1 #define GFX12_SC_INSTDONE_WMBEDone_bits 1 #define GFX11_SC_INSTDONE_WMBEDone_bits 1 #define GFX9_SC_INSTDONE_WMBEDone_bits 1 #define GFX8_SC_INSTDONE_WMBEDone_bits 1 #define GFX75_SC_INSTDONE_WMBEDone_bits 1 #define GFX7_SC_INSTDONE_WMBEDone_bits 1 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_WMBEDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SC_INSTDONE_WMBEDone_start 2 #define GFX12_SC_INSTDONE_WMBEDone_start 2 #define GFX11_SC_INSTDONE_WMBEDone_start 2 #define GFX9_SC_INSTDONE_WMBEDone_start 2 #define GFX8_SC_INSTDONE_WMBEDone_start 2 #define GFX75_SC_INSTDONE_WMBEDone_start 2 #define GFX7_SC_INSTDONE_WMBEDone_start 2 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_WMBEDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SC_INSTDONE::WMFE Done */ #define GFX125_SC_INSTDONE_WMFEDone_bits 1 #define GFX12_SC_INSTDONE_WMFEDone_bits 1 #define GFX11_SC_INSTDONE_WMFEDone_bits 1 #define GFX9_SC_INSTDONE_WMFEDone_bits 1 #define GFX8_SC_INSTDONE_WMFEDone_bits 1 #define GFX75_SC_INSTDONE_WMFEDone_bits 1 #define GFX7_SC_INSTDONE_WMFEDone_bits 1 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_WMFEDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SC_INSTDONE_WMFEDone_start 1 #define GFX12_SC_INSTDONE_WMFEDone_start 1 #define GFX11_SC_INSTDONE_WMFEDone_start 1 #define GFX9_SC_INSTDONE_WMFEDone_start 1 #define GFX8_SC_INSTDONE_WMFEDone_start 1 #define GFX75_SC_INSTDONE_WMFEDone_start 1 #define GFX7_SC_INSTDONE_WMFEDone_start 1 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_WMFEDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SC_INSTDONE_EXTRA */ #define GFX125_SC_INSTDONE_EXTRA_length 1 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_EXTRA_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SC_INSTDONE_EXTRA::DAPB1 Done */ #define GFX125_SC_INSTDONE_EXTRA_DAPB1Done_bits 1 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_EXTRA_DAPB1Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SC_INSTDONE_EXTRA_DAPB1Done_start 12 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_EXTRA_DAPB1Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 12; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SC_INSTDONE_EXTRA::DAPRBE1 Done */ #define GFX125_SC_INSTDONE_EXTRA_DAPRBE1Done_bits 1 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_EXTRA_DAPRBE1Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SC_INSTDONE_EXTRA_DAPRBE1Done_start 13 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_EXTRA_DAPRBE1Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 13; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SC_INSTDONE_EXTRA::DC4 Done */ #define GFX125_SC_INSTDONE_EXTRA_DC4Done_bits 1 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_EXTRA_DC4Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SC_INSTDONE_EXTRA_DC4Done_start 16 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_EXTRA_DC4Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SC_INSTDONE_EXTRA::DC5 Done */ #define GFX125_SC_INSTDONE_EXTRA_DC5Done_bits 1 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_EXTRA_DC5Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SC_INSTDONE_EXTRA_DC5Done_start 17 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_EXTRA_DC5Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 17; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SC_INSTDONE_EXTRA::DC6 Done */ #define GFX125_SC_INSTDONE_EXTRA_DC6Done_bits 1 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_EXTRA_DC6Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SC_INSTDONE_EXTRA_DC6Done_start 18 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_EXTRA_DC6Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 18; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SC_INSTDONE_EXTRA::DC7 Done */ #define GFX125_SC_INSTDONE_EXTRA_DC7Done_bits 1 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_EXTRA_DC7Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SC_INSTDONE_EXTRA_DC7Done_start 19 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_EXTRA_DC7Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 19; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SC_INSTDONE_EXTRA::GW4 Done */ #define GFX125_SC_INSTDONE_EXTRA_GW4Done_bits 1 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_EXTRA_GW4Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SC_INSTDONE_EXTRA_GW4Done_start 20 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_EXTRA_GW4Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 20; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SC_INSTDONE_EXTRA::GW5 Done */ #define GFX125_SC_INSTDONE_EXTRA_GW5Done_bits 1 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_EXTRA_GW5Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SC_INSTDONE_EXTRA_GW5Done_start 21 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_EXTRA_GW5Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 21; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SC_INSTDONE_EXTRA::GW6 Done */ #define GFX125_SC_INSTDONE_EXTRA_GW6Done_bits 1 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_EXTRA_GW6Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SC_INSTDONE_EXTRA_GW6Done_start 22 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_EXTRA_GW6Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 22; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SC_INSTDONE_EXTRA::GW7 Done */ #define GFX125_SC_INSTDONE_EXTRA_GW7Done_bits 1 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_EXTRA_GW7Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SC_INSTDONE_EXTRA_GW7Done_start 23 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_EXTRA_GW7Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 23; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SC_INSTDONE_EXTRA::RCC1 Done */ #define GFX125_SC_INSTDONE_EXTRA_RCC1Done_bits 1 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_EXTRA_RCC1Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SC_INSTDONE_EXTRA_RCC1Done_start 9 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_EXTRA_RCC1Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 9; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SC_INSTDONE_EXTRA::RCPBE1 Done */ #define GFX125_SC_INSTDONE_EXTRA_RCPBE1Done_bits 1 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_EXTRA_RCPBE1Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SC_INSTDONE_EXTRA_RCPBE1Done_start 10 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_EXTRA_RCPBE1Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 10; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SC_INSTDONE_EXTRA::RCPFE1 Done */ #define GFX125_SC_INSTDONE_EXTRA_RCPFE1Done_bits 1 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_EXTRA_RCPFE1Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SC_INSTDONE_EXTRA_RCPFE1Done_start 11 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_EXTRA_RCPFE1Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 11; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SC_INSTDONE_EXTRA::TDC1 Done */ #define GFX125_SC_INSTDONE_EXTRA_TDC1Done_bits 1 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_EXTRA_TDC1Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SC_INSTDONE_EXTRA_TDC1Done_start 24 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_EXTRA_TDC1Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SC_INSTDONE_EXTRA2 */ #define GFX125_SC_INSTDONE_EXTRA2_length 1 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_EXTRA2_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SC_INSTDONE_EXTRA2::DAPB2 Done */ #define GFX125_SC_INSTDONE_EXTRA2_DAPB2Done_bits 1 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_EXTRA2_DAPB2Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SC_INSTDONE_EXTRA2_DAPB2Done_start 12 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_EXTRA2_DAPB2Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 12; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SC_INSTDONE_EXTRA2::DAPRBE2 Done */ #define GFX125_SC_INSTDONE_EXTRA2_DAPRBE2Done_bits 1 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_EXTRA2_DAPRBE2Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SC_INSTDONE_EXTRA2_DAPRBE2Done_start 13 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_EXTRA2_DAPRBE2Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 13; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SC_INSTDONE_EXTRA2::RCC2 Done */ #define GFX125_SC_INSTDONE_EXTRA2_RCC2Done_bits 1 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_EXTRA2_RCC2Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SC_INSTDONE_EXTRA2_RCC2Done_start 9 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_EXTRA2_RCC2Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 9; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SC_INSTDONE_EXTRA2::RCPBE2 Done */ #define GFX125_SC_INSTDONE_EXTRA2_RCPBE2Done_bits 1 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_EXTRA2_RCPBE2Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SC_INSTDONE_EXTRA2_RCPBE2Done_start 10 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_EXTRA2_RCPBE2Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 10; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SC_INSTDONE_EXTRA2::RCPFE2 Done */ #define GFX125_SC_INSTDONE_EXTRA2_RCPFE2Done_bits 1 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_EXTRA2_RCPFE2Done_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SC_INSTDONE_EXTRA2_RCPFE2Done_start 11 static inline uint32_t ATTRIBUTE_PURE SC_INSTDONE_EXTRA2_RCPFE2Done_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 11; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_AVS_CHROMA_COEFF_TABLE_BODY */ #define GFX125_SFC_AVS_CHROMA_COEFF_TABLE_BODY_length 64 #define GFX12_SFC_AVS_CHROMA_COEFF_TABLE_BODY_length 64 #define GFX11_SFC_AVS_CHROMA_COEFF_TABLE_BODY_length 64 #define GFX9_SFC_AVS_CHROMA_COEFF_TABLE_BODY_length 64 static inline uint32_t ATTRIBUTE_PURE SFC_AVS_CHROMA_COEFF_TABLE_BODY_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 64; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_AVS_CHROMA_COEFF_TABLE_BODY::Table 1X Filter Coefficient[[n],2] */ #define GFX125_SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1XFilterCoefficientn2_bits 8 #define GFX12_SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1XFilterCoefficientn2_bits 8 #define GFX11_SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1XFilterCoefficientn2_bits 8 #define GFX9_SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1XFilterCoefficientn2_bits 8 static inline uint32_t ATTRIBUTE_PURE SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1XFilterCoefficientn2_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1XFilterCoefficientn2_start 0 #define GFX12_SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1XFilterCoefficientn2_start 0 #define GFX11_SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1XFilterCoefficientn2_start 0 #define GFX9_SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1XFilterCoefficientn2_start 0 static inline uint32_t ATTRIBUTE_PURE SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1XFilterCoefficientn2_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_AVS_CHROMA_COEFF_TABLE_BODY::Table 1X Filter Coefficient[[n],3] */ #define GFX125_SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1XFilterCoefficientn3_bits 8 #define GFX12_SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1XFilterCoefficientn3_bits 8 #define GFX11_SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1XFilterCoefficientn3_bits 8 #define GFX9_SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1XFilterCoefficientn3_bits 8 static inline uint32_t ATTRIBUTE_PURE SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1XFilterCoefficientn3_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1XFilterCoefficientn3_start 16 #define GFX12_SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1XFilterCoefficientn3_start 16 #define GFX11_SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1XFilterCoefficientn3_start 16 #define GFX9_SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1XFilterCoefficientn3_start 16 static inline uint32_t ATTRIBUTE_PURE SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1XFilterCoefficientn3_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_AVS_CHROMA_COEFF_TABLE_BODY::Table 1X Filter Coefficient[[n],4] */ #define GFX125_SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1XFilterCoefficientn4_bits 8 #define GFX12_SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1XFilterCoefficientn4_bits 8 #define GFX11_SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1XFilterCoefficientn4_bits 8 #define GFX9_SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1XFilterCoefficientn4_bits 8 static inline uint32_t ATTRIBUTE_PURE SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1XFilterCoefficientn4_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1XFilterCoefficientn4_start 32 #define GFX12_SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1XFilterCoefficientn4_start 32 #define GFX11_SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1XFilterCoefficientn4_start 32 #define GFX9_SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1XFilterCoefficientn4_start 32 static inline uint32_t ATTRIBUTE_PURE SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1XFilterCoefficientn4_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_AVS_CHROMA_COEFF_TABLE_BODY::Table 1X Filter Coefficient[[n],5] */ #define GFX125_SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1XFilterCoefficientn5_bits 8 #define GFX12_SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1XFilterCoefficientn5_bits 8 #define GFX11_SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1XFilterCoefficientn5_bits 8 #define GFX9_SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1XFilterCoefficientn5_bits 8 static inline uint32_t ATTRIBUTE_PURE SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1XFilterCoefficientn5_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1XFilterCoefficientn5_start 48 #define GFX12_SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1XFilterCoefficientn5_start 48 #define GFX11_SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1XFilterCoefficientn5_start 48 #define GFX9_SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1XFilterCoefficientn5_start 48 static inline uint32_t ATTRIBUTE_PURE SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1XFilterCoefficientn5_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 48; case 120: return 48; case 110: return 48; case 90: return 48; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_AVS_CHROMA_COEFF_TABLE_BODY::Table 1Y Filter Coefficient[[n],2] */ #define GFX125_SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1YFilterCoefficientn2_bits 8 #define GFX12_SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1YFilterCoefficientn2_bits 8 #define GFX11_SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1YFilterCoefficientn2_bits 8 #define GFX9_SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1YFilterCoefficientn2_bits 8 static inline uint32_t ATTRIBUTE_PURE SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1YFilterCoefficientn2_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1YFilterCoefficientn2_start 8 #define GFX12_SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1YFilterCoefficientn2_start 8 #define GFX11_SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1YFilterCoefficientn2_start 8 #define GFX9_SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1YFilterCoefficientn2_start 8 static inline uint32_t ATTRIBUTE_PURE SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1YFilterCoefficientn2_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_AVS_CHROMA_COEFF_TABLE_BODY::Table 1Y Filter Coefficient[[n],3] */ #define GFX125_SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1YFilterCoefficientn3_bits 8 #define GFX12_SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1YFilterCoefficientn3_bits 8 #define GFX11_SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1YFilterCoefficientn3_bits 8 #define GFX9_SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1YFilterCoefficientn3_bits 8 static inline uint32_t ATTRIBUTE_PURE SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1YFilterCoefficientn3_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1YFilterCoefficientn3_start 24 #define GFX12_SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1YFilterCoefficientn3_start 24 #define GFX11_SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1YFilterCoefficientn3_start 24 #define GFX9_SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1YFilterCoefficientn3_start 24 static inline uint32_t ATTRIBUTE_PURE SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1YFilterCoefficientn3_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_AVS_CHROMA_COEFF_TABLE_BODY::Table 1Y Filter Coefficient[[n],4] */ #define GFX125_SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1YFilterCoefficientn4_bits 8 #define GFX12_SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1YFilterCoefficientn4_bits 8 #define GFX11_SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1YFilterCoefficientn4_bits 8 #define GFX9_SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1YFilterCoefficientn4_bits 8 static inline uint32_t ATTRIBUTE_PURE SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1YFilterCoefficientn4_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1YFilterCoefficientn4_start 40 #define GFX12_SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1YFilterCoefficientn4_start 40 #define GFX11_SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1YFilterCoefficientn4_start 40 #define GFX9_SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1YFilterCoefficientn4_start 40 static inline uint32_t ATTRIBUTE_PURE SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1YFilterCoefficientn4_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 40; case 120: return 40; case 110: return 40; case 90: return 40; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_AVS_CHROMA_COEFF_TABLE_BODY::Table 1Y Filter Coefficient[[n],5] */ #define GFX125_SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1YFilterCoefficientn5_bits 8 #define GFX12_SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1YFilterCoefficientn5_bits 8 #define GFX11_SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1YFilterCoefficientn5_bits 8 #define GFX9_SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1YFilterCoefficientn5_bits 8 static inline uint32_t ATTRIBUTE_PURE SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1YFilterCoefficientn5_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1YFilterCoefficientn5_start 56 #define GFX12_SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1YFilterCoefficientn5_start 56 #define GFX11_SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1YFilterCoefficientn5_start 56 #define GFX9_SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1YFilterCoefficientn5_start 56 static inline uint32_t ATTRIBUTE_PURE SFC_AVS_CHROMA_COEFF_TABLE_BODY_Table1YFilterCoefficientn5_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 56; case 120: return 56; case 110: return 56; case 90: return 56; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_AVS_LUMA_COEFF_TABLE_BODY */ #define GFX125_SFC_AVS_LUMA_COEFF_TABLE_BODY_length 128 #define GFX12_SFC_AVS_LUMA_COEFF_TABLE_BODY_length 128 #define GFX11_SFC_AVS_LUMA_COEFF_TABLE_BODY_length 128 #define GFX9_SFC_AVS_LUMA_COEFF_TABLE_BODY_length 128 static inline uint32_t ATTRIBUTE_PURE SFC_AVS_LUMA_COEFF_TABLE_BODY_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 128; case 120: return 128; case 110: return 128; case 90: return 128; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_AVS_LUMA_COEFF_TABLE_BODY::Table 0X Filter Coefficient[[n],0] */ #define GFX125_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn0_bits 8 #define GFX12_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn0_bits 8 #define GFX11_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn0_bits 8 #define GFX9_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn0_bits 8 static inline uint32_t ATTRIBUTE_PURE SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn0_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn0_start 0 #define GFX12_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn0_start 0 #define GFX11_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn0_start 0 #define GFX9_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn0_start 0 static inline uint32_t ATTRIBUTE_PURE SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn0_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_AVS_LUMA_COEFF_TABLE_BODY::Table 0X Filter Coefficient[[n],1] */ #define GFX125_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn1_bits 8 #define GFX12_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn1_bits 8 #define GFX11_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn1_bits 8 #define GFX9_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn1_bits 8 static inline uint32_t ATTRIBUTE_PURE SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn1_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn1_start 16 #define GFX12_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn1_start 16 #define GFX11_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn1_start 16 #define GFX9_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn1_start 16 static inline uint32_t ATTRIBUTE_PURE SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn1_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_AVS_LUMA_COEFF_TABLE_BODY::Table 0X Filter Coefficient[[n],2] */ #define GFX125_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn2_bits 8 #define GFX12_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn2_bits 8 #define GFX11_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn2_bits 8 #define GFX9_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn2_bits 8 static inline uint32_t ATTRIBUTE_PURE SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn2_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn2_start 32 #define GFX12_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn2_start 32 #define GFX11_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn2_start 32 #define GFX9_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn2_start 32 static inline uint32_t ATTRIBUTE_PURE SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn2_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_AVS_LUMA_COEFF_TABLE_BODY::Table 0X Filter Coefficient[[n],3] */ #define GFX125_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn3_bits 8 #define GFX12_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn3_bits 8 #define GFX11_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn3_bits 8 #define GFX9_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn3_bits 8 static inline uint32_t ATTRIBUTE_PURE SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn3_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn3_start 48 #define GFX12_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn3_start 48 #define GFX11_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn3_start 48 #define GFX9_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn3_start 48 static inline uint32_t ATTRIBUTE_PURE SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn3_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 48; case 120: return 48; case 110: return 48; case 90: return 48; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_AVS_LUMA_COEFF_TABLE_BODY::Table 0X Filter Coefficient[[n],4] */ #define GFX125_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn4_bits 8 #define GFX12_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn4_bits 8 #define GFX11_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn4_bits 8 #define GFX9_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn4_bits 8 static inline uint32_t ATTRIBUTE_PURE SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn4_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn4_start 64 #define GFX12_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn4_start 64 #define GFX11_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn4_start 64 #define GFX9_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn4_start 64 static inline uint32_t ATTRIBUTE_PURE SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn4_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 64; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_AVS_LUMA_COEFF_TABLE_BODY::Table 0X Filter Coefficient[[n],5] */ #define GFX125_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn5_bits 8 #define GFX12_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn5_bits 8 #define GFX11_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn5_bits 8 #define GFX9_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn5_bits 8 static inline uint32_t ATTRIBUTE_PURE SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn5_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn5_start 80 #define GFX12_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn5_start 80 #define GFX11_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn5_start 80 #define GFX9_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn5_start 80 static inline uint32_t ATTRIBUTE_PURE SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn5_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 80; case 120: return 80; case 110: return 80; case 90: return 80; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_AVS_LUMA_COEFF_TABLE_BODY::Table 0X Filter Coefficient[[n],6] */ #define GFX125_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn6_bits 8 #define GFX12_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn6_bits 8 #define GFX11_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn6_bits 8 #define GFX9_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn6_bits 8 static inline uint32_t ATTRIBUTE_PURE SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn6_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn6_start 96 #define GFX12_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn6_start 96 #define GFX11_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn6_start 96 #define GFX9_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn6_start 96 static inline uint32_t ATTRIBUTE_PURE SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn6_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 96; case 120: return 96; case 110: return 96; case 90: return 96; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_AVS_LUMA_COEFF_TABLE_BODY::Table 0X Filter Coefficient[[n],7] */ #define GFX125_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn7_bits 8 #define GFX12_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn7_bits 8 #define GFX11_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn7_bits 8 #define GFX9_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn7_bits 8 static inline uint32_t ATTRIBUTE_PURE SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn7_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn7_start 112 #define GFX12_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn7_start 112 #define GFX11_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn7_start 112 #define GFX9_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn7_start 112 static inline uint32_t ATTRIBUTE_PURE SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0XFilterCoefficientn7_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 112; case 120: return 112; case 110: return 112; case 90: return 112; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_AVS_LUMA_COEFF_TABLE_BODY::Table 0Y Filter Coefficient[[n],0] */ #define GFX125_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn0_bits 8 #define GFX12_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn0_bits 8 #define GFX11_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn0_bits 8 #define GFX9_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn0_bits 8 static inline uint32_t ATTRIBUTE_PURE SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn0_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn0_start 8 #define GFX12_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn0_start 8 #define GFX11_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn0_start 8 #define GFX9_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn0_start 8 static inline uint32_t ATTRIBUTE_PURE SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn0_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_AVS_LUMA_COEFF_TABLE_BODY::Table 0Y Filter Coefficient[[n],1] */ #define GFX125_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn1_bits 8 #define GFX12_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn1_bits 8 #define GFX11_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn1_bits 8 #define GFX9_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn1_bits 8 static inline uint32_t ATTRIBUTE_PURE SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn1_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn1_start 24 #define GFX12_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn1_start 24 #define GFX11_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn1_start 24 #define GFX9_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn1_start 24 static inline uint32_t ATTRIBUTE_PURE SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn1_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_AVS_LUMA_COEFF_TABLE_BODY::Table 0Y Filter Coefficient[[n],2] */ #define GFX125_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn2_bits 8 #define GFX12_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn2_bits 8 #define GFX11_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn2_bits 8 #define GFX9_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn2_bits 8 static inline uint32_t ATTRIBUTE_PURE SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn2_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn2_start 40 #define GFX12_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn2_start 40 #define GFX11_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn2_start 40 #define GFX9_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn2_start 40 static inline uint32_t ATTRIBUTE_PURE SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn2_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 40; case 120: return 40; case 110: return 40; case 90: return 40; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_AVS_LUMA_COEFF_TABLE_BODY::Table 0Y Filter Coefficient[[n],3] */ #define GFX125_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn3_bits 8 #define GFX12_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn3_bits 8 #define GFX11_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn3_bits 8 #define GFX9_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn3_bits 8 static inline uint32_t ATTRIBUTE_PURE SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn3_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn3_start 56 #define GFX12_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn3_start 56 #define GFX11_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn3_start 56 #define GFX9_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn3_start 56 static inline uint32_t ATTRIBUTE_PURE SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn3_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 56; case 120: return 56; case 110: return 56; case 90: return 56; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_AVS_LUMA_COEFF_TABLE_BODY::Table 0Y Filter Coefficient[[n],4] */ #define GFX125_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn4_bits 8 #define GFX12_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn4_bits 8 #define GFX11_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn4_bits 8 #define GFX9_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn4_bits 8 static inline uint32_t ATTRIBUTE_PURE SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn4_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn4_start 72 #define GFX12_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn4_start 72 #define GFX11_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn4_start 72 #define GFX9_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn4_start 72 static inline uint32_t ATTRIBUTE_PURE SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn4_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 72; case 120: return 72; case 110: return 72; case 90: return 72; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_AVS_LUMA_COEFF_TABLE_BODY::Table 0Y Filter Coefficient[[n],5] */ #define GFX125_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn5_bits 8 #define GFX12_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn5_bits 8 #define GFX11_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn5_bits 8 #define GFX9_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn5_bits 8 static inline uint32_t ATTRIBUTE_PURE SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn5_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn5_start 88 #define GFX12_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn5_start 88 #define GFX11_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn5_start 88 #define GFX9_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn5_start 88 static inline uint32_t ATTRIBUTE_PURE SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn5_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 88; case 120: return 88; case 110: return 88; case 90: return 88; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_AVS_LUMA_COEFF_TABLE_BODY::Table 0Y Filter Coefficient[[n],6] */ #define GFX125_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn6_bits 8 #define GFX12_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn6_bits 8 #define GFX11_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn6_bits 8 #define GFX9_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn6_bits 8 static inline uint32_t ATTRIBUTE_PURE SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn6_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn6_start 104 #define GFX12_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn6_start 104 #define GFX11_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn6_start 104 #define GFX9_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn6_start 104 static inline uint32_t ATTRIBUTE_PURE SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn6_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 104; case 120: return 104; case 110: return 104; case 90: return 104; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_AVS_LUMA_COEFF_TABLE_BODY::Table 0Y Filter Coefficient[[n],7] */ #define GFX125_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn7_bits 8 #define GFX12_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn7_bits 8 #define GFX11_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn7_bits 8 #define GFX9_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn7_bits 8 static inline uint32_t ATTRIBUTE_PURE SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn7_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn7_start 120 #define GFX12_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn7_start 120 #define GFX11_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn7_start 120 #define GFX9_SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn7_start 120 static inline uint32_t ATTRIBUTE_PURE SFC_AVS_LUMA_COEFF_TABLE_BODY_Table0YFilterCoefficientn7_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 120; case 120: return 120; case 110: return 120; case 90: return 120; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_AVS_STATE_BODY */ #define GFX125_SFC_AVS_STATE_BODY_length 3 #define GFX12_SFC_AVS_STATE_BODY_length 3 #define GFX11_SFC_AVS_STATE_BODY_length 3 #define GFX9_SFC_AVS_STATE_BODY_length 2 static inline uint32_t ATTRIBUTE_PURE SFC_AVS_STATE_BODY_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 2; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_AVS_STATE_BODY::Input Vertical Siting */ #define GFX125_SFC_AVS_STATE_BODY_InputVerticalSiting_bits 4 #define GFX12_SFC_AVS_STATE_BODY_InputVerticalSiting_bits 4 #define GFX11_SFC_AVS_STATE_BODY_InputVerticalSiting_bits 4 static inline uint32_t ATTRIBUTE_PURE SFC_AVS_STATE_BODY_InputVerticalSiting_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_AVS_STATE_BODY_InputVerticalSiting_start 64 #define GFX12_SFC_AVS_STATE_BODY_InputVerticalSiting_start 64 #define GFX11_SFC_AVS_STATE_BODY_InputVerticalSiting_start 64 static inline uint32_t ATTRIBUTE_PURE SFC_AVS_STATE_BODY_InputVerticalSiting_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_AVS_STATE_BODY::Max Derivative 4 Pixels */ #define GFX125_SFC_AVS_STATE_BODY_MaxDerivative4Pixels_bits 8 #define GFX12_SFC_AVS_STATE_BODY_MaxDerivative4Pixels_bits 8 #define GFX11_SFC_AVS_STATE_BODY_MaxDerivative4Pixels_bits 8 #define GFX9_SFC_AVS_STATE_BODY_MaxDerivative4Pixels_bits 8 static inline uint32_t ATTRIBUTE_PURE SFC_AVS_STATE_BODY_MaxDerivative4Pixels_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_AVS_STATE_BODY_MaxDerivative4Pixels_start 48 #define GFX12_SFC_AVS_STATE_BODY_MaxDerivative4Pixels_start 48 #define GFX11_SFC_AVS_STATE_BODY_MaxDerivative4Pixels_start 48 #define GFX9_SFC_AVS_STATE_BODY_MaxDerivative4Pixels_start 48 static inline uint32_t ATTRIBUTE_PURE SFC_AVS_STATE_BODY_MaxDerivative4Pixels_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 48; case 120: return 48; case 110: return 48; case 90: return 48; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_AVS_STATE_BODY::Max Derivative 8 Pixels */ #define GFX125_SFC_AVS_STATE_BODY_MaxDerivative8Pixels_bits 8 #define GFX12_SFC_AVS_STATE_BODY_MaxDerivative8Pixels_bits 8 #define GFX11_SFC_AVS_STATE_BODY_MaxDerivative8Pixels_bits 8 #define GFX9_SFC_AVS_STATE_BODY_MaxDerivative8Pixels_bits 8 static inline uint32_t ATTRIBUTE_PURE SFC_AVS_STATE_BODY_MaxDerivative8Pixels_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_AVS_STATE_BODY_MaxDerivative8Pixels_start 32 #define GFX12_SFC_AVS_STATE_BODY_MaxDerivative8Pixels_start 32 #define GFX11_SFC_AVS_STATE_BODY_MaxDerivative8Pixels_start 32 #define GFX9_SFC_AVS_STATE_BODY_MaxDerivative8Pixels_start 32 static inline uint32_t ATTRIBUTE_PURE SFC_AVS_STATE_BODY_MaxDerivative8Pixels_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_AVS_STATE_BODY::Sharpness Level */ #define GFX125_SFC_AVS_STATE_BODY_SharpnessLevel_bits 8 #define GFX12_SFC_AVS_STATE_BODY_SharpnessLevel_bits 8 #define GFX11_SFC_AVS_STATE_BODY_SharpnessLevel_bits 8 #define GFX9_SFC_AVS_STATE_BODY_SharpnessLevel_bits 8 static inline uint32_t ATTRIBUTE_PURE SFC_AVS_STATE_BODY_SharpnessLevel_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_AVS_STATE_BODY_SharpnessLevel_start 24 #define GFX12_SFC_AVS_STATE_BODY_SharpnessLevel_start 24 #define GFX11_SFC_AVS_STATE_BODY_SharpnessLevel_start 24 #define GFX9_SFC_AVS_STATE_BODY_SharpnessLevel_start 24 static inline uint32_t ATTRIBUTE_PURE SFC_AVS_STATE_BODY_SharpnessLevel_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_AVS_STATE_BODY::Transition Area with 4 Pixels */ #define GFX125_SFC_AVS_STATE_BODY_TransitionAreawith4Pixels_bits 3 #define GFX12_SFC_AVS_STATE_BODY_TransitionAreawith4Pixels_bits 3 #define GFX11_SFC_AVS_STATE_BODY_TransitionAreawith4Pixels_bits 3 #define GFX9_SFC_AVS_STATE_BODY_TransitionAreawith4Pixels_bits 3 static inline uint32_t ATTRIBUTE_PURE SFC_AVS_STATE_BODY_TransitionAreawith4Pixels_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_AVS_STATE_BODY_TransitionAreawith4Pixels_start 4 #define GFX12_SFC_AVS_STATE_BODY_TransitionAreawith4Pixels_start 4 #define GFX11_SFC_AVS_STATE_BODY_TransitionAreawith4Pixels_start 4 #define GFX9_SFC_AVS_STATE_BODY_TransitionAreawith4Pixels_start 4 static inline uint32_t ATTRIBUTE_PURE SFC_AVS_STATE_BODY_TransitionAreawith4Pixels_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_AVS_STATE_BODY::Transition Area with 8 Pixels */ #define GFX125_SFC_AVS_STATE_BODY_TransitionAreawith8Pixels_bits 3 #define GFX12_SFC_AVS_STATE_BODY_TransitionAreawith8Pixels_bits 3 #define GFX11_SFC_AVS_STATE_BODY_TransitionAreawith8Pixels_bits 3 #define GFX9_SFC_AVS_STATE_BODY_TransitionAreawith8Pixels_bits 3 static inline uint32_t ATTRIBUTE_PURE SFC_AVS_STATE_BODY_TransitionAreawith8Pixels_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_AVS_STATE_BODY_TransitionAreawith8Pixels_start 0 #define GFX12_SFC_AVS_STATE_BODY_TransitionAreawith8Pixels_start 0 #define GFX11_SFC_AVS_STATE_BODY_TransitionAreawith8Pixels_start 0 #define GFX9_SFC_AVS_STATE_BODY_TransitionAreawith8Pixels_start 0 static inline uint32_t ATTRIBUTE_PURE SFC_AVS_STATE_BODY_TransitionAreawith8Pixels_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY */ #define GFX125_SFC_IEF_STATE_BODY_length 23 #define GFX12_SFC_IEF_STATE_BODY_length 23 #define GFX11_SFC_IEF_STATE_BODY_length 23 #define GFX9_SFC_IEF_STATE_BODY_length 23 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 23; case 120: return 23; case 110: return 23; case 90: return 23; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY::B0L */ #define GFX125_SFC_IEF_STATE_BODY_B0L_bits 8 #define GFX12_SFC_IEF_STATE_BODY_B0L_bits 8 #define GFX11_SFC_IEF_STATE_BODY_B0L_bits 8 #define GFX9_SFC_IEF_STATE_BODY_B0L_bits 8 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_B0L_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_IEF_STATE_BODY_B0L_start 272 #define GFX12_SFC_IEF_STATE_BODY_B0L_start 272 #define GFX11_SFC_IEF_STATE_BODY_B0L_start 272 #define GFX9_SFC_IEF_STATE_BODY_B0L_start 272 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_B0L_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 272; case 120: return 272; case 110: return 272; case 90: return 272; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY::B0U */ #define GFX125_SFC_IEF_STATE_BODY_B0U_bits 8 #define GFX12_SFC_IEF_STATE_BODY_B0U_bits 8 #define GFX11_SFC_IEF_STATE_BODY_B0U_bits 8 #define GFX9_SFC_IEF_STATE_BODY_B0U_bits 8 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_B0U_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_IEF_STATE_BODY_B0U_start 400 #define GFX12_SFC_IEF_STATE_BODY_B0U_start 400 #define GFX11_SFC_IEF_STATE_BODY_B0U_start 400 #define GFX9_SFC_IEF_STATE_BODY_B0U_start 400 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_B0U_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 400; case 120: return 400; case 110: return 400; case 90: return 400; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY::B1L */ #define GFX125_SFC_IEF_STATE_BODY_B1L_bits 8 #define GFX12_SFC_IEF_STATE_BODY_B1L_bits 8 #define GFX11_SFC_IEF_STATE_BODY_B1L_bits 8 #define GFX9_SFC_IEF_STATE_BODY_B1L_bits 8 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_B1L_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_IEF_STATE_BODY_B1L_start 280 #define GFX12_SFC_IEF_STATE_BODY_B1L_start 280 #define GFX11_SFC_IEF_STATE_BODY_B1L_start 280 #define GFX9_SFC_IEF_STATE_BODY_B1L_start 280 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_B1L_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 280; case 120: return 280; case 110: return 280; case 90: return 280; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY::B1U */ #define GFX125_SFC_IEF_STATE_BODY_B1U_bits 8 #define GFX12_SFC_IEF_STATE_BODY_B1U_bits 8 #define GFX11_SFC_IEF_STATE_BODY_B1U_bits 8 #define GFX9_SFC_IEF_STATE_BODY_B1U_bits 8 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_B1U_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_IEF_STATE_BODY_B1U_start 408 #define GFX12_SFC_IEF_STATE_BODY_B1U_start 408 #define GFX11_SFC_IEF_STATE_BODY_B1U_start 408 #define GFX9_SFC_IEF_STATE_BODY_B1U_start 408 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_B1U_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 408; case 120: return 408; case 110: return 408; case 90: return 408; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY::B2L */ #define GFX125_SFC_IEF_STATE_BODY_B2L_bits 8 #define GFX12_SFC_IEF_STATE_BODY_B2L_bits 8 #define GFX11_SFC_IEF_STATE_BODY_B2L_bits 8 #define GFX9_SFC_IEF_STATE_BODY_B2L_bits 8 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_B2L_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_IEF_STATE_BODY_B2L_start 288 #define GFX12_SFC_IEF_STATE_BODY_B2L_start 288 #define GFX11_SFC_IEF_STATE_BODY_B2L_start 288 #define GFX9_SFC_IEF_STATE_BODY_B2L_start 288 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_B2L_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 288; case 120: return 288; case 110: return 288; case 90: return 288; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY::B2U */ #define GFX125_SFC_IEF_STATE_BODY_B2U_bits 8 #define GFX12_SFC_IEF_STATE_BODY_B2U_bits 8 #define GFX11_SFC_IEF_STATE_BODY_B2U_bits 8 #define GFX9_SFC_IEF_STATE_BODY_B2U_bits 8 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_B2U_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_IEF_STATE_BODY_B2U_start 416 #define GFX12_SFC_IEF_STATE_BODY_B2U_start 416 #define GFX11_SFC_IEF_STATE_BODY_B2U_start 416 #define GFX9_SFC_IEF_STATE_BODY_B2U_start 416 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_B2U_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 416; case 120: return 416; case 110: return 416; case 90: return 416; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY::B3L */ #define GFX125_SFC_IEF_STATE_BODY_B3L_bits 8 #define GFX12_SFC_IEF_STATE_BODY_B3L_bits 8 #define GFX11_SFC_IEF_STATE_BODY_B3L_bits 8 #define GFX9_SFC_IEF_STATE_BODY_B3L_bits 8 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_B3L_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_IEF_STATE_BODY_B3L_start 296 #define GFX12_SFC_IEF_STATE_BODY_B3L_start 296 #define GFX11_SFC_IEF_STATE_BODY_B3L_start 296 #define GFX9_SFC_IEF_STATE_BODY_B3L_start 296 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_B3L_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 296; case 120: return 296; case 110: return 296; case 90: return 296; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY::B3U */ #define GFX125_SFC_IEF_STATE_BODY_B3U_bits 8 #define GFX12_SFC_IEF_STATE_BODY_B3U_bits 8 #define GFX11_SFC_IEF_STATE_BODY_B3U_bits 8 #define GFX9_SFC_IEF_STATE_BODY_B3U_bits 8 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_B3U_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_IEF_STATE_BODY_B3U_start 424 #define GFX12_SFC_IEF_STATE_BODY_B3U_start 424 #define GFX11_SFC_IEF_STATE_BODY_B3U_start 424 #define GFX9_SFC_IEF_STATE_BODY_B3U_start 424 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_B3U_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 424; case 120: return 424; case 110: return 424; case 90: return 424; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY::C0 */ #define GFX125_SFC_IEF_STATE_BODY_C0_bits 13 #define GFX12_SFC_IEF_STATE_BODY_C0_bits 13 #define GFX11_SFC_IEF_STATE_BODY_C0_bits 13 #define GFX9_SFC_IEF_STATE_BODY_C0_bits 13 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_C0_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 13; case 120: return 13; case 110: return 13; case 90: return 13; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_IEF_STATE_BODY_C0_start 483 #define GFX12_SFC_IEF_STATE_BODY_C0_start 483 #define GFX11_SFC_IEF_STATE_BODY_C0_start 483 #define GFX9_SFC_IEF_STATE_BODY_C0_start 483 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_C0_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 483; case 120: return 483; case 110: return 483; case 90: return 483; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY::C1 */ #define GFX125_SFC_IEF_STATE_BODY_C1_bits 13 #define GFX12_SFC_IEF_STATE_BODY_C1_bits 13 #define GFX11_SFC_IEF_STATE_BODY_C1_bits 13 #define GFX9_SFC_IEF_STATE_BODY_C1_bits 13 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_C1_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 13; case 120: return 13; case 110: return 13; case 90: return 13; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_IEF_STATE_BODY_C1_start 496 #define GFX12_SFC_IEF_STATE_BODY_C1_start 496 #define GFX11_SFC_IEF_STATE_BODY_C1_start 496 #define GFX9_SFC_IEF_STATE_BODY_C1_start 496 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_C1_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 496; case 120: return 496; case 110: return 496; case 90: return 496; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY::C2 */ #define GFX125_SFC_IEF_STATE_BODY_C2_bits 13 #define GFX12_SFC_IEF_STATE_BODY_C2_bits 13 #define GFX11_SFC_IEF_STATE_BODY_C2_bits 13 #define GFX9_SFC_IEF_STATE_BODY_C2_bits 13 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_C2_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 13; case 120: return 13; case 110: return 13; case 90: return 13; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_IEF_STATE_BODY_C2_start 512 #define GFX12_SFC_IEF_STATE_BODY_C2_start 512 #define GFX11_SFC_IEF_STATE_BODY_C2_start 512 #define GFX9_SFC_IEF_STATE_BODY_C2_start 512 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_C2_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 512; case 120: return 512; case 110: return 512; case 90: return 512; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY::C3 */ #define GFX125_SFC_IEF_STATE_BODY_C3_bits 13 #define GFX12_SFC_IEF_STATE_BODY_C3_bits 13 #define GFX11_SFC_IEF_STATE_BODY_C3_bits 13 #define GFX9_SFC_IEF_STATE_BODY_C3_bits 13 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_C3_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 13; case 120: return 13; case 110: return 13; case 90: return 13; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_IEF_STATE_BODY_C3_start 525 #define GFX12_SFC_IEF_STATE_BODY_C3_start 525 #define GFX11_SFC_IEF_STATE_BODY_C3_start 525 #define GFX9_SFC_IEF_STATE_BODY_C3_start 525 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_C3_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 525; case 120: return 525; case 110: return 525; case 90: return 525; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY::C4 */ #define GFX125_SFC_IEF_STATE_BODY_C4_bits 13 #define GFX12_SFC_IEF_STATE_BODY_C4_bits 13 #define GFX11_SFC_IEF_STATE_BODY_C4_bits 13 #define GFX9_SFC_IEF_STATE_BODY_C4_bits 13 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_C4_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 13; case 120: return 13; case 110: return 13; case 90: return 13; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_IEF_STATE_BODY_C4_start 544 #define GFX12_SFC_IEF_STATE_BODY_C4_start 544 #define GFX11_SFC_IEF_STATE_BODY_C4_start 544 #define GFX9_SFC_IEF_STATE_BODY_C4_start 544 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_C4_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 544; case 120: return 544; case 110: return 544; case 90: return 544; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY::C5 */ #define GFX125_SFC_IEF_STATE_BODY_C5_bits 13 #define GFX12_SFC_IEF_STATE_BODY_C5_bits 13 #define GFX11_SFC_IEF_STATE_BODY_C5_bits 13 #define GFX9_SFC_IEF_STATE_BODY_C5_bits 13 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_C5_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 13; case 120: return 13; case 110: return 13; case 90: return 13; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_IEF_STATE_BODY_C5_start 557 #define GFX12_SFC_IEF_STATE_BODY_C5_start 557 #define GFX11_SFC_IEF_STATE_BODY_C5_start 557 #define GFX9_SFC_IEF_STATE_BODY_C5_start 557 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_C5_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 557; case 120: return 557; case 110: return 557; case 90: return 557; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY::C6 */ #define GFX125_SFC_IEF_STATE_BODY_C6_bits 13 #define GFX12_SFC_IEF_STATE_BODY_C6_bits 13 #define GFX11_SFC_IEF_STATE_BODY_C6_bits 13 #define GFX9_SFC_IEF_STATE_BODY_C6_bits 13 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_C6_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 13; case 120: return 13; case 110: return 13; case 90: return 13; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_IEF_STATE_BODY_C6_start 576 #define GFX12_SFC_IEF_STATE_BODY_C6_start 576 #define GFX11_SFC_IEF_STATE_BODY_C6_start 576 #define GFX9_SFC_IEF_STATE_BODY_C6_start 576 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_C6_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 576; case 120: return 576; case 110: return 576; case 90: return 576; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY::C7 */ #define GFX125_SFC_IEF_STATE_BODY_C7_bits 13 #define GFX12_SFC_IEF_STATE_BODY_C7_bits 13 #define GFX11_SFC_IEF_STATE_BODY_C7_bits 13 #define GFX9_SFC_IEF_STATE_BODY_C7_bits 13 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_C7_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 13; case 120: return 13; case 110: return 13; case 90: return 13; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_IEF_STATE_BODY_C7_start 589 #define GFX12_SFC_IEF_STATE_BODY_C7_start 589 #define GFX11_SFC_IEF_STATE_BODY_C7_start 589 #define GFX9_SFC_IEF_STATE_BODY_C7_start 589 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_C7_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 589; case 120: return 589; case 110: return 589; case 90: return 589; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY::C8 */ #define GFX125_SFC_IEF_STATE_BODY_C8_bits 13 #define GFX12_SFC_IEF_STATE_BODY_C8_bits 13 #define GFX11_SFC_IEF_STATE_BODY_C8_bits 13 #define GFX9_SFC_IEF_STATE_BODY_C8_bits 13 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_C8_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 13; case 120: return 13; case 110: return 13; case 90: return 13; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_IEF_STATE_BODY_C8_start 608 #define GFX12_SFC_IEF_STATE_BODY_C8_start 608 #define GFX11_SFC_IEF_STATE_BODY_C8_start 608 #define GFX9_SFC_IEF_STATE_BODY_C8_start 608 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_C8_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 608; case 120: return 608; case 110: return 608; case 90: return 608; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY::Diamond Margin */ #define GFX125_SFC_IEF_STATE_BODY_DiamondMargin_bits 3 #define GFX12_SFC_IEF_STATE_BODY_DiamondMargin_bits 3 #define GFX11_SFC_IEF_STATE_BODY_DiamondMargin_bits 3 #define GFX9_SFC_IEF_STATE_BODY_DiamondMargin_bits 3 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_DiamondMargin_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_IEF_STATE_BODY_DiamondMargin_start 108 #define GFX12_SFC_IEF_STATE_BODY_DiamondMargin_start 108 #define GFX11_SFC_IEF_STATE_BODY_DiamondMargin_start 108 #define GFX9_SFC_IEF_STATE_BODY_DiamondMargin_start 108 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_DiamondMargin_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 108; case 120: return 108; case 110: return 108; case 90: return 108; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY::Diamond_Th */ #define GFX125_SFC_IEF_STATE_BODY_Diamond_Th_bits 6 #define GFX12_SFC_IEF_STATE_BODY_Diamond_Th_bits 6 #define GFX11_SFC_IEF_STATE_BODY_Diamond_Th_bits 6 #define GFX9_SFC_IEF_STATE_BODY_Diamond_Th_bits 6 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_Diamond_Th_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_IEF_STATE_BODY_Diamond_Th_start 135 #define GFX12_SFC_IEF_STATE_BODY_Diamond_Th_start 135 #define GFX11_SFC_IEF_STATE_BODY_Diamond_Th_start 135 #define GFX9_SFC_IEF_STATE_BODY_Diamond_Th_start 135 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_Diamond_Th_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 135; case 120: return 135; case 110: return 135; case 90: return 135; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY::Diamond_alpha */ #define GFX125_SFC_IEF_STATE_BODY_Diamond_alpha_bits 8 #define GFX12_SFC_IEF_STATE_BODY_Diamond_alpha_bits 8 #define GFX11_SFC_IEF_STATE_BODY_Diamond_alpha_bits 8 #define GFX9_SFC_IEF_STATE_BODY_Diamond_alpha_bits 8 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_Diamond_alpha_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_IEF_STATE_BODY_Diamond_alpha_start 141 #define GFX12_SFC_IEF_STATE_BODY_Diamond_alpha_start 141 #define GFX11_SFC_IEF_STATE_BODY_Diamond_alpha_start 141 #define GFX9_SFC_IEF_STATE_BODY_Diamond_alpha_start 141 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_Diamond_alpha_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 141; case 120: return 141; case 110: return 141; case 90: return 141; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY::Diamond_du */ #define GFX125_SFC_IEF_STATE_BODY_Diamond_du_bits 7 #define GFX12_SFC_IEF_STATE_BODY_Diamond_du_bits 7 #define GFX11_SFC_IEF_STATE_BODY_Diamond_du_bits 7 #define GFX9_SFC_IEF_STATE_BODY_Diamond_du_bits 7 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_Diamond_du_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 7; case 120: return 7; case 110: return 7; case 90: return 7; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_IEF_STATE_BODY_Diamond_du_start 152 #define GFX12_SFC_IEF_STATE_BODY_Diamond_du_start 152 #define GFX11_SFC_IEF_STATE_BODY_Diamond_du_start 152 #define GFX9_SFC_IEF_STATE_BODY_Diamond_du_start 152 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_Diamond_du_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 152; case 120: return 152; case 110: return 152; case 90: return 152; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY::Diamond_dv */ #define GFX125_SFC_IEF_STATE_BODY_Diamond_dv_bits 7 #define GFX12_SFC_IEF_STATE_BODY_Diamond_dv_bits 7 #define GFX11_SFC_IEF_STATE_BODY_Diamond_dv_bits 7 #define GFX9_SFC_IEF_STATE_BODY_Diamond_dv_bits 7 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_Diamond_dv_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 7; case 120: return 7; case 110: return 7; case 90: return 7; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_IEF_STATE_BODY_Diamond_dv_start 128 #define GFX12_SFC_IEF_STATE_BODY_Diamond_dv_start 128 #define GFX11_SFC_IEF_STATE_BODY_Diamond_dv_start 128 #define GFX9_SFC_IEF_STATE_BODY_Diamond_dv_start 128 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_Diamond_dv_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 128; case 120: return 128; case 110: return 128; case 90: return 128; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY::Gain Factor */ #define GFX125_SFC_IEF_STATE_BODY_GainFactor_bits 6 #define GFX12_SFC_IEF_STATE_BODY_GainFactor_bits 6 #define GFX11_SFC_IEF_STATE_BODY_GainFactor_bits 6 #define GFX9_SFC_IEF_STATE_BODY_GainFactor_bits 6 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_GainFactor_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_IEF_STATE_BODY_GainFactor_start 0 #define GFX12_SFC_IEF_STATE_BODY_GainFactor_start 0 #define GFX11_SFC_IEF_STATE_BODY_GainFactor_start 0 #define GFX9_SFC_IEF_STATE_BODY_GainFactor_start 0 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_GainFactor_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY::Global Noise Estimation */ #define GFX125_SFC_IEF_STATE_BODY_GlobalNoiseEstimation_bits 8 #define GFX12_SFC_IEF_STATE_BODY_GlobalNoiseEstimation_bits 8 #define GFX11_SFC_IEF_STATE_BODY_GlobalNoiseEstimation_bits 8 #define GFX9_SFC_IEF_STATE_BODY_GlobalNoiseEstimation_bits 8 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_GlobalNoiseEstimation_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_IEF_STATE_BODY_GlobalNoiseEstimation_start 32 #define GFX12_SFC_IEF_STATE_BODY_GlobalNoiseEstimation_start 32 #define GFX11_SFC_IEF_STATE_BODY_GlobalNoiseEstimation_start 32 #define GFX9_SFC_IEF_STATE_BODY_GlobalNoiseEstimation_start 32 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_GlobalNoiseEstimation_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY::HS_margin */ #define GFX125_SFC_IEF_STATE_BODY_HS_margin_bits 3 #define GFX12_SFC_IEF_STATE_BODY_HS_margin_bits 3 #define GFX11_SFC_IEF_STATE_BODY_HS_margin_bits 3 #define GFX9_SFC_IEF_STATE_BODY_HS_margin_bits 3 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_HS_margin_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_IEF_STATE_BODY_HS_margin_start 149 #define GFX12_SFC_IEF_STATE_BODY_HS_margin_start 149 #define GFX11_SFC_IEF_STATE_BODY_HS_margin_start 149 #define GFX9_SFC_IEF_STATE_BODY_HS_margin_start 149 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_HS_margin_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 149; case 120: return 149; case 110: return 149; case 90: return 149; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY::Hue_Max */ #define GFX125_SFC_IEF_STATE_BODY_Hue_Max_bits 6 #define GFX12_SFC_IEF_STATE_BODY_Hue_Max_bits 6 #define GFX11_SFC_IEF_STATE_BODY_Hue_Max_bits 6 #define GFX9_SFC_IEF_STATE_BODY_Hue_Max_bits 6 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_Hue_Max_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_IEF_STATE_BODY_Hue_Max_start 86 #define GFX12_SFC_IEF_STATE_BODY_Hue_Max_start 86 #define GFX11_SFC_IEF_STATE_BODY_Hue_Max_start 86 #define GFX9_SFC_IEF_STATE_BODY_Hue_Max_start 86 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_Hue_Max_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 86; case 120: return 86; case 110: return 86; case 90: return 86; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY::INV_Margin_VYL */ #define GFX125_SFC_IEF_STATE_BODY_INV_Margin_VYL_bits 16 #define GFX12_SFC_IEF_STATE_BODY_INV_Margin_VYL_bits 16 #define GFX11_SFC_IEF_STATE_BODY_INV_Margin_VYL_bits 16 #define GFX9_SFC_IEF_STATE_BODY_INV_Margin_VYL_bits 16 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_INV_Margin_VYL_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_IEF_STATE_BODY_INV_Margin_VYL_start 192 #define GFX12_SFC_IEF_STATE_BODY_INV_Margin_VYL_start 192 #define GFX11_SFC_IEF_STATE_BODY_INV_Margin_VYL_start 192 #define GFX9_SFC_IEF_STATE_BODY_INV_Margin_VYL_start 192 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_INV_Margin_VYL_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 192; case 120: return 192; case 110: return 192; case 90: return 192; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY::INV_Margin_VYU */ #define GFX125_SFC_IEF_STATE_BODY_INV_Margin_VYU_bits 16 #define GFX12_SFC_IEF_STATE_BODY_INV_Margin_VYU_bits 16 #define GFX11_SFC_IEF_STATE_BODY_INV_Margin_VYU_bits 16 #define GFX9_SFC_IEF_STATE_BODY_INV_Margin_VYU_bits 16 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_INV_Margin_VYU_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_IEF_STATE_BODY_INV_Margin_VYU_start 224 #define GFX12_SFC_IEF_STATE_BODY_INV_Margin_VYU_start 224 #define GFX11_SFC_IEF_STATE_BODY_INV_Margin_VYU_start 224 #define GFX9_SFC_IEF_STATE_BODY_INV_Margin_VYU_start 224 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_INV_Margin_VYU_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 224; case 120: return 224; case 110: return 224; case 90: return 224; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY::Non Edge Weight */ #define GFX125_SFC_IEF_STATE_BODY_NonEdgeWeight_bits 3 #define GFX12_SFC_IEF_STATE_BODY_NonEdgeWeight_bits 3 #define GFX11_SFC_IEF_STATE_BODY_NonEdgeWeight_bits 3 #define GFX9_SFC_IEF_STATE_BODY_NonEdgeWeight_bits 3 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_NonEdgeWeight_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_IEF_STATE_BODY_NonEdgeWeight_start 40 #define GFX12_SFC_IEF_STATE_BODY_NonEdgeWeight_start 40 #define GFX11_SFC_IEF_STATE_BODY_NonEdgeWeight_start 40 #define GFX9_SFC_IEF_STATE_BODY_NonEdgeWeight_start 40 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_NonEdgeWeight_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 40; case 120: return 40; case 110: return 40; case 90: return 40; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY::Offset In 1 */ #define GFX125_SFC_IEF_STATE_BODY_OffsetIn1_bits 11 #define GFX12_SFC_IEF_STATE_BODY_OffsetIn1_bits 11 #define GFX11_SFC_IEF_STATE_BODY_OffsetIn1_bits 11 #define GFX9_SFC_IEF_STATE_BODY_OffsetIn1_bits 11 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_OffsetIn1_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 11; case 120: return 11; case 110: return 11; case 90: return 11; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_IEF_STATE_BODY_OffsetIn1_start 640 #define GFX12_SFC_IEF_STATE_BODY_OffsetIn1_start 640 #define GFX11_SFC_IEF_STATE_BODY_OffsetIn1_start 640 #define GFX9_SFC_IEF_STATE_BODY_OffsetIn1_start 640 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_OffsetIn1_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 640; case 120: return 640; case 110: return 640; case 90: return 640; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY::Offset In 2 */ #define GFX125_SFC_IEF_STATE_BODY_OffsetIn2_bits 11 #define GFX12_SFC_IEF_STATE_BODY_OffsetIn2_bits 11 #define GFX11_SFC_IEF_STATE_BODY_OffsetIn2_bits 11 #define GFX9_SFC_IEF_STATE_BODY_OffsetIn2_bits 11 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_OffsetIn2_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 11; case 120: return 11; case 110: return 11; case 90: return 11; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_IEF_STATE_BODY_OffsetIn2_start 672 #define GFX12_SFC_IEF_STATE_BODY_OffsetIn2_start 672 #define GFX11_SFC_IEF_STATE_BODY_OffsetIn2_start 672 #define GFX9_SFC_IEF_STATE_BODY_OffsetIn2_start 672 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_OffsetIn2_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 672; case 120: return 672; case 110: return 672; case 90: return 672; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY::Offset In 3 */ #define GFX125_SFC_IEF_STATE_BODY_OffsetIn3_bits 11 #define GFX12_SFC_IEF_STATE_BODY_OffsetIn3_bits 11 #define GFX11_SFC_IEF_STATE_BODY_OffsetIn3_bits 11 #define GFX9_SFC_IEF_STATE_BODY_OffsetIn3_bits 11 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_OffsetIn3_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 11; case 120: return 11; case 110: return 11; case 90: return 11; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_IEF_STATE_BODY_OffsetIn3_start 704 #define GFX12_SFC_IEF_STATE_BODY_OffsetIn3_start 704 #define GFX11_SFC_IEF_STATE_BODY_OffsetIn3_start 704 #define GFX9_SFC_IEF_STATE_BODY_OffsetIn3_start 704 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_OffsetIn3_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 704; case 120: return 704; case 110: return 704; case 90: return 704; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY::Offset Out 1 */ #define GFX125_SFC_IEF_STATE_BODY_OffsetOut1_bits 11 #define GFX12_SFC_IEF_STATE_BODY_OffsetOut1_bits 11 #define GFX11_SFC_IEF_STATE_BODY_OffsetOut1_bits 11 #define GFX9_SFC_IEF_STATE_BODY_OffsetOut1_bits 11 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_OffsetOut1_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 11; case 120: return 11; case 110: return 11; case 90: return 11; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_IEF_STATE_BODY_OffsetOut1_start 651 #define GFX12_SFC_IEF_STATE_BODY_OffsetOut1_start 651 #define GFX11_SFC_IEF_STATE_BODY_OffsetOut1_start 651 #define GFX9_SFC_IEF_STATE_BODY_OffsetOut1_start 651 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_OffsetOut1_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 651; case 120: return 651; case 110: return 651; case 90: return 651; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY::Offset Out 2 */ #define GFX125_SFC_IEF_STATE_BODY_OffsetOut2_bits 11 #define GFX12_SFC_IEF_STATE_BODY_OffsetOut2_bits 11 #define GFX11_SFC_IEF_STATE_BODY_OffsetOut2_bits 11 #define GFX9_SFC_IEF_STATE_BODY_OffsetOut2_bits 11 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_OffsetOut2_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 11; case 120: return 11; case 110: return 11; case 90: return 11; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_IEF_STATE_BODY_OffsetOut2_start 683 #define GFX12_SFC_IEF_STATE_BODY_OffsetOut2_start 683 #define GFX11_SFC_IEF_STATE_BODY_OffsetOut2_start 683 #define GFX9_SFC_IEF_STATE_BODY_OffsetOut2_start 683 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_OffsetOut2_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 683; case 120: return 683; case 110: return 683; case 90: return 683; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY::Offset Out 3 */ #define GFX125_SFC_IEF_STATE_BODY_OffsetOut3_bits 11 #define GFX12_SFC_IEF_STATE_BODY_OffsetOut3_bits 11 #define GFX11_SFC_IEF_STATE_BODY_OffsetOut3_bits 11 #define GFX9_SFC_IEF_STATE_BODY_OffsetOut3_bits 11 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_OffsetOut3_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 11; case 120: return 11; case 110: return 11; case 90: return 11; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_IEF_STATE_BODY_OffsetOut3_start 715 #define GFX12_SFC_IEF_STATE_BODY_OffsetOut3_start 715 #define GFX11_SFC_IEF_STATE_BODY_OffsetOut3_start 715 #define GFX9_SFC_IEF_STATE_BODY_OffsetOut3_start 715 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_OffsetOut3_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 715; case 120: return 715; case 110: return 715; case 90: return 715; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY::P0L */ #define GFX125_SFC_IEF_STATE_BODY_P0L_bits 8 #define GFX12_SFC_IEF_STATE_BODY_P0L_bits 8 #define GFX11_SFC_IEF_STATE_BODY_P0L_bits 8 #define GFX9_SFC_IEF_STATE_BODY_P0L_bits 8 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_P0L_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_IEF_STATE_BODY_P0L_start 240 #define GFX12_SFC_IEF_STATE_BODY_P0L_start 240 #define GFX11_SFC_IEF_STATE_BODY_P0L_start 240 #define GFX9_SFC_IEF_STATE_BODY_P0L_start 240 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_P0L_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 240; case 120: return 240; case 110: return 240; case 90: return 240; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY::P0U */ #define GFX125_SFC_IEF_STATE_BODY_P0U_bits 8 #define GFX12_SFC_IEF_STATE_BODY_P0U_bits 8 #define GFX11_SFC_IEF_STATE_BODY_P0U_bits 8 #define GFX9_SFC_IEF_STATE_BODY_P0U_bits 8 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_P0U_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_IEF_STATE_BODY_P0U_start 363 #define GFX12_SFC_IEF_STATE_BODY_P0U_start 363 #define GFX11_SFC_IEF_STATE_BODY_P0U_start 363 #define GFX9_SFC_IEF_STATE_BODY_P0U_start 363 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_P0U_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 363; case 120: return 363; case 110: return 363; case 90: return 363; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY::P1L */ #define GFX125_SFC_IEF_STATE_BODY_P1L_bits 8 #define GFX12_SFC_IEF_STATE_BODY_P1L_bits 8 #define GFX11_SFC_IEF_STATE_BODY_P1L_bits 8 #define GFX9_SFC_IEF_STATE_BODY_P1L_bits 8 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_P1L_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_IEF_STATE_BODY_P1L_start 248 #define GFX12_SFC_IEF_STATE_BODY_P1L_start 248 #define GFX11_SFC_IEF_STATE_BODY_P1L_start 248 #define GFX9_SFC_IEF_STATE_BODY_P1L_start 248 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_P1L_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 248; case 120: return 248; case 110: return 248; case 90: return 248; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY::P1U */ #define GFX125_SFC_IEF_STATE_BODY_P1U_bits 8 #define GFX12_SFC_IEF_STATE_BODY_P1U_bits 8 #define GFX11_SFC_IEF_STATE_BODY_P1U_bits 8 #define GFX9_SFC_IEF_STATE_BODY_P1U_bits 8 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_P1U_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_IEF_STATE_BODY_P1U_start 371 #define GFX12_SFC_IEF_STATE_BODY_P1U_start 371 #define GFX11_SFC_IEF_STATE_BODY_P1U_start 371 #define GFX9_SFC_IEF_STATE_BODY_P1U_start 371 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_P1U_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 371; case 120: return 371; case 110: return 371; case 90: return 371; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY::P2L */ #define GFX125_SFC_IEF_STATE_BODY_P2L_bits 8 #define GFX12_SFC_IEF_STATE_BODY_P2L_bits 8 #define GFX11_SFC_IEF_STATE_BODY_P2L_bits 8 #define GFX9_SFC_IEF_STATE_BODY_P2L_bits 8 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_P2L_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_IEF_STATE_BODY_P2L_start 256 #define GFX12_SFC_IEF_STATE_BODY_P2L_start 256 #define GFX11_SFC_IEF_STATE_BODY_P2L_start 256 #define GFX9_SFC_IEF_STATE_BODY_P2L_start 256 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_P2L_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 256; case 120: return 256; case 110: return 256; case 90: return 256; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY::P2U */ #define GFX125_SFC_IEF_STATE_BODY_P2U_bits 8 #define GFX12_SFC_IEF_STATE_BODY_P2U_bits 8 #define GFX11_SFC_IEF_STATE_BODY_P2U_bits 8 #define GFX9_SFC_IEF_STATE_BODY_P2U_bits 8 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_P2U_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_IEF_STATE_BODY_P2U_start 384 #define GFX12_SFC_IEF_STATE_BODY_P2U_start 384 #define GFX11_SFC_IEF_STATE_BODY_P2U_start 384 #define GFX9_SFC_IEF_STATE_BODY_P2U_start 384 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_P2U_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 384; case 120: return 384; case 110: return 384; case 90: return 384; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY::P3L */ #define GFX125_SFC_IEF_STATE_BODY_P3L_bits 8 #define GFX12_SFC_IEF_STATE_BODY_P3L_bits 8 #define GFX11_SFC_IEF_STATE_BODY_P3L_bits 8 #define GFX9_SFC_IEF_STATE_BODY_P3L_bits 8 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_P3L_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_IEF_STATE_BODY_P3L_start 264 #define GFX12_SFC_IEF_STATE_BODY_P3L_start 264 #define GFX11_SFC_IEF_STATE_BODY_P3L_start 264 #define GFX9_SFC_IEF_STATE_BODY_P3L_start 264 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_P3L_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 264; case 120: return 264; case 110: return 264; case 90: return 264; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY::P3U */ #define GFX125_SFC_IEF_STATE_BODY_P3U_bits 8 #define GFX12_SFC_IEF_STATE_BODY_P3U_bits 8 #define GFX11_SFC_IEF_STATE_BODY_P3U_bits 8 #define GFX9_SFC_IEF_STATE_BODY_P3U_bits 8 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_P3U_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_IEF_STATE_BODY_P3U_start 392 #define GFX12_SFC_IEF_STATE_BODY_P3U_start 392 #define GFX11_SFC_IEF_STATE_BODY_P3U_start 392 #define GFX9_SFC_IEF_STATE_BODY_P3U_start 392 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_P3U_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 392; case 120: return 392; case 110: return 392; case 90: return 392; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY::R3c Coefficient */ #define GFX125_SFC_IEF_STATE_BODY_R3cCoefficient_bits 5 #define GFX12_SFC_IEF_STATE_BODY_R3cCoefficient_bits 5 #define GFX11_SFC_IEF_STATE_BODY_R3cCoefficient_bits 5 #define GFX9_SFC_IEF_STATE_BODY_R3cCoefficient_bits 5 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_R3cCoefficient_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 5; case 110: return 5; case 90: return 5; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_IEF_STATE_BODY_R3cCoefficient_start 23 #define GFX12_SFC_IEF_STATE_BODY_R3cCoefficient_start 23 #define GFX11_SFC_IEF_STATE_BODY_R3cCoefficient_start 23 #define GFX9_SFC_IEF_STATE_BODY_R3cCoefficient_start 23 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_R3cCoefficient_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 23; case 120: return 23; case 110: return 23; case 90: return 23; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY::R3x Coefficient */ #define GFX125_SFC_IEF_STATE_BODY_R3xCoefficient_bits 5 #define GFX12_SFC_IEF_STATE_BODY_R3xCoefficient_bits 5 #define GFX11_SFC_IEF_STATE_BODY_R3xCoefficient_bits 5 #define GFX9_SFC_IEF_STATE_BODY_R3xCoefficient_bits 5 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_R3xCoefficient_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 5; case 110: return 5; case 90: return 5; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_IEF_STATE_BODY_R3xCoefficient_start 18 #define GFX12_SFC_IEF_STATE_BODY_R3xCoefficient_start 18 #define GFX11_SFC_IEF_STATE_BODY_R3xCoefficient_start 18 #define GFX9_SFC_IEF_STATE_BODY_R3xCoefficient_start 18 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_R3xCoefficient_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 18; case 120: return 18; case 110: return 18; case 90: return 18; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY::R5c Coefficient */ #define GFX125_SFC_IEF_STATE_BODY_R5cCoefficient_bits 5 #define GFX12_SFC_IEF_STATE_BODY_R5cCoefficient_bits 5 #define GFX11_SFC_IEF_STATE_BODY_R5cCoefficient_bits 5 #define GFX9_SFC_IEF_STATE_BODY_R5cCoefficient_bits 5 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_R5cCoefficient_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 5; case 110: return 5; case 90: return 5; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_IEF_STATE_BODY_R5cCoefficient_start 59 #define GFX12_SFC_IEF_STATE_BODY_R5cCoefficient_start 59 #define GFX11_SFC_IEF_STATE_BODY_R5cCoefficient_start 59 #define GFX9_SFC_IEF_STATE_BODY_R5cCoefficient_start 59 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_R5cCoefficient_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 59; case 120: return 59; case 110: return 59; case 90: return 59; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY::R5cx Coefficient */ #define GFX125_SFC_IEF_STATE_BODY_R5cxCoefficient_bits 5 #define GFX12_SFC_IEF_STATE_BODY_R5cxCoefficient_bits 5 #define GFX11_SFC_IEF_STATE_BODY_R5cxCoefficient_bits 5 #define GFX9_SFC_IEF_STATE_BODY_R5cxCoefficient_bits 5 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_R5cxCoefficient_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 5; case 110: return 5; case 90: return 5; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_IEF_STATE_BODY_R5cxCoefficient_start 54 #define GFX12_SFC_IEF_STATE_BODY_R5cxCoefficient_start 54 #define GFX11_SFC_IEF_STATE_BODY_R5cxCoefficient_start 54 #define GFX9_SFC_IEF_STATE_BODY_R5cxCoefficient_start 54 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_R5cxCoefficient_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 54; case 120: return 54; case 110: return 54; case 90: return 54; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY::R5x Coefficient */ #define GFX125_SFC_IEF_STATE_BODY_R5xCoefficient_bits 5 #define GFX12_SFC_IEF_STATE_BODY_R5xCoefficient_bits 5 #define GFX11_SFC_IEF_STATE_BODY_R5xCoefficient_bits 5 #define GFX9_SFC_IEF_STATE_BODY_R5xCoefficient_bits 5 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_R5xCoefficient_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 5; case 110: return 5; case 90: return 5; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_IEF_STATE_BODY_R5xCoefficient_start 49 #define GFX12_SFC_IEF_STATE_BODY_R5xCoefficient_start 49 #define GFX11_SFC_IEF_STATE_BODY_R5xCoefficient_start 49 #define GFX9_SFC_IEF_STATE_BODY_R5xCoefficient_start 49 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_R5xCoefficient_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 49; case 120: return 49; case 110: return 49; case 90: return 49; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY::Regular Weight */ #define GFX125_SFC_IEF_STATE_BODY_RegularWeight_bits 3 #define GFX12_SFC_IEF_STATE_BODY_RegularWeight_bits 3 #define GFX11_SFC_IEF_STATE_BODY_RegularWeight_bits 3 #define GFX9_SFC_IEF_STATE_BODY_RegularWeight_bits 3 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_RegularWeight_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_IEF_STATE_BODY_RegularWeight_start 43 #define GFX12_SFC_IEF_STATE_BODY_RegularWeight_start 43 #define GFX11_SFC_IEF_STATE_BODY_RegularWeight_start 43 #define GFX9_SFC_IEF_STATE_BODY_RegularWeight_start 43 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_RegularWeight_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 43; case 120: return 43; case 110: return 43; case 90: return 43; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY::S0L */ #define GFX125_SFC_IEF_STATE_BODY_S0L_bits 11 #define GFX12_SFC_IEF_STATE_BODY_S0L_bits 11 #define GFX11_SFC_IEF_STATE_BODY_S0L_bits 11 #define GFX9_SFC_IEF_STATE_BODY_S0L_bits 11 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_S0L_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 11; case 120: return 11; case 110: return 11; case 90: return 11; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_IEF_STATE_BODY_S0L_start 304 #define GFX12_SFC_IEF_STATE_BODY_S0L_start 304 #define GFX11_SFC_IEF_STATE_BODY_S0L_start 304 #define GFX9_SFC_IEF_STATE_BODY_S0L_start 304 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_S0L_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 304; case 120: return 304; case 110: return 304; case 90: return 304; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY::S0U */ #define GFX125_SFC_IEF_STATE_BODY_S0U_bits 11 #define GFX12_SFC_IEF_STATE_BODY_S0U_bits 11 #define GFX11_SFC_IEF_STATE_BODY_S0U_bits 11 #define GFX9_SFC_IEF_STATE_BODY_S0U_bits 11 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_S0U_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 11; case 120: return 11; case 110: return 11; case 90: return 11; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_IEF_STATE_BODY_S0U_start 432 #define GFX12_SFC_IEF_STATE_BODY_S0U_start 432 #define GFX11_SFC_IEF_STATE_BODY_S0U_start 432 #define GFX9_SFC_IEF_STATE_BODY_S0U_start 432 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_S0U_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 432; case 120: return 432; case 110: return 432; case 90: return 432; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY::S1L */ #define GFX125_SFC_IEF_STATE_BODY_S1L_bits 11 #define GFX12_SFC_IEF_STATE_BODY_S1L_bits 11 #define GFX11_SFC_IEF_STATE_BODY_S1L_bits 11 #define GFX9_SFC_IEF_STATE_BODY_S1L_bits 11 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_S1L_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 11; case 120: return 11; case 110: return 11; case 90: return 11; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_IEF_STATE_BODY_S1L_start 320 #define GFX12_SFC_IEF_STATE_BODY_S1L_start 320 #define GFX11_SFC_IEF_STATE_BODY_S1L_start 320 #define GFX9_SFC_IEF_STATE_BODY_S1L_start 320 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_S1L_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 320; case 120: return 320; case 110: return 320; case 90: return 320; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY::S1U */ #define GFX125_SFC_IEF_STATE_BODY_S1U_bits 11 #define GFX12_SFC_IEF_STATE_BODY_S1U_bits 11 #define GFX11_SFC_IEF_STATE_BODY_S1U_bits 11 #define GFX9_SFC_IEF_STATE_BODY_S1U_bits 11 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_S1U_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 11; case 120: return 11; case 110: return 11; case 90: return 11; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_IEF_STATE_BODY_S1U_start 448 #define GFX12_SFC_IEF_STATE_BODY_S1U_start 448 #define GFX11_SFC_IEF_STATE_BODY_S1U_start 448 #define GFX9_SFC_IEF_STATE_BODY_S1U_start 448 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_S1U_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 448; case 120: return 448; case 110: return 448; case 90: return 448; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY::S2L */ #define GFX125_SFC_IEF_STATE_BODY_S2L_bits 11 #define GFX12_SFC_IEF_STATE_BODY_S2L_bits 11 #define GFX11_SFC_IEF_STATE_BODY_S2L_bits 11 #define GFX9_SFC_IEF_STATE_BODY_S2L_bits 11 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_S2L_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 11; case 120: return 11; case 110: return 11; case 90: return 11; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_IEF_STATE_BODY_S2L_start 331 #define GFX12_SFC_IEF_STATE_BODY_S2L_start 331 #define GFX11_SFC_IEF_STATE_BODY_S2L_start 331 #define GFX9_SFC_IEF_STATE_BODY_S2L_start 331 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_S2L_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 331; case 120: return 331; case 110: return 331; case 90: return 331; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY::S2U */ #define GFX125_SFC_IEF_STATE_BODY_S2U_bits 11 #define GFX12_SFC_IEF_STATE_BODY_S2U_bits 11 #define GFX11_SFC_IEF_STATE_BODY_S2U_bits 11 #define GFX9_SFC_IEF_STATE_BODY_S2U_bits 11 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_S2U_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 11; case 120: return 11; case 110: return 11; case 90: return 11; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_IEF_STATE_BODY_S2U_start 459 #define GFX12_SFC_IEF_STATE_BODY_S2U_start 459 #define GFX11_SFC_IEF_STATE_BODY_S2U_start 459 #define GFX9_SFC_IEF_STATE_BODY_S2U_start 459 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_S2U_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 459; case 120: return 459; case 110: return 459; case 90: return 459; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY::S3L */ #define GFX125_SFC_IEF_STATE_BODY_S3L_bits 11 #define GFX12_SFC_IEF_STATE_BODY_S3L_bits 11 #define GFX11_SFC_IEF_STATE_BODY_S3L_bits 11 #define GFX9_SFC_IEF_STATE_BODY_S3L_bits 11 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_S3L_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 11; case 120: return 11; case 110: return 11; case 90: return 11; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_IEF_STATE_BODY_S3L_start 352 #define GFX12_SFC_IEF_STATE_BODY_S3L_start 352 #define GFX11_SFC_IEF_STATE_BODY_S3L_start 352 #define GFX9_SFC_IEF_STATE_BODY_S3L_start 352 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_S3L_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 352; case 120: return 352; case 110: return 352; case 90: return 352; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY::S3U */ #define GFX125_SFC_IEF_STATE_BODY_S3U_bits 11 #define GFX12_SFC_IEF_STATE_BODY_S3U_bits 11 #define GFX11_SFC_IEF_STATE_BODY_S3U_bits 11 #define GFX9_SFC_IEF_STATE_BODY_S3U_bits 11 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_S3U_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 11; case 120: return 11; case 110: return 11; case 90: return 11; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_IEF_STATE_BODY_S3U_start 96 #define GFX12_SFC_IEF_STATE_BODY_S3U_start 96 #define GFX11_SFC_IEF_STATE_BODY_S3U_start 96 #define GFX9_SFC_IEF_STATE_BODY_S3U_start 96 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_S3U_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 96; case 120: return 96; case 110: return 96; case 90: return 96; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY::STD Cos(alpha) */ #define GFX125_SFC_IEF_STATE_BODY_STDCosalpha_bits 8 #define GFX12_SFC_IEF_STATE_BODY_STDCosalpha_bits 8 #define GFX11_SFC_IEF_STATE_BODY_STDCosalpha_bits 8 #define GFX9_SFC_IEF_STATE_BODY_STDCosalpha_bits 8 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_STDCosalpha_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_IEF_STATE_BODY_STDCosalpha_start 72 #define GFX12_SFC_IEF_STATE_BODY_STDCosalpha_start 72 #define GFX11_SFC_IEF_STATE_BODY_STDCosalpha_start 72 #define GFX9_SFC_IEF_STATE_BODY_STDCosalpha_start 72 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_STDCosalpha_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 72; case 120: return 72; case 110: return 72; case 90: return 72; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY::STD Sin(alpha) */ #define GFX125_SFC_IEF_STATE_BODY_STDSinalpha_bits 8 #define GFX12_SFC_IEF_STATE_BODY_STDSinalpha_bits 8 #define GFX11_SFC_IEF_STATE_BODY_STDSinalpha_bits 8 #define GFX9_SFC_IEF_STATE_BODY_STDSinalpha_bits 8 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_STDSinalpha_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_IEF_STATE_BODY_STDSinalpha_start 64 #define GFX12_SFC_IEF_STATE_BODY_STDSinalpha_start 64 #define GFX11_SFC_IEF_STATE_BODY_STDSinalpha_start 64 #define GFX9_SFC_IEF_STATE_BODY_STDSinalpha_start 64 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_STDSinalpha_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 64; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY::Sat_Max */ #define GFX125_SFC_IEF_STATE_BODY_Sat_Max_bits 6 #define GFX12_SFC_IEF_STATE_BODY_Sat_Max_bits 6 #define GFX11_SFC_IEF_STATE_BODY_Sat_Max_bits 6 #define GFX9_SFC_IEF_STATE_BODY_Sat_Max_bits 6 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_Sat_Max_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_IEF_STATE_BODY_Sat_Max_start 80 #define GFX12_SFC_IEF_STATE_BODY_Sat_Max_start 80 #define GFX11_SFC_IEF_STATE_BODY_Sat_Max_start 80 #define GFX9_SFC_IEF_STATE_BODY_Sat_Max_start 80 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_Sat_Max_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 80; case 120: return 80; case 110: return 80; case 90: return 80; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY::Skin Detail Factor */ #define GFX125_SFC_IEF_STATE_BODY_SkinDetailFactor_bits 1 #define GFX12_SFC_IEF_STATE_BODY_SkinDetailFactor_bits 1 #define GFX11_SFC_IEF_STATE_BODY_SkinDetailFactor_bits 1 #define GFX9_SFC_IEF_STATE_BODY_SkinDetailFactor_bits 1 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_SkinDetailFactor_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_IEF_STATE_BODY_SkinDetailFactor_start 159 #define GFX12_SFC_IEF_STATE_BODY_SkinDetailFactor_start 159 #define GFX11_SFC_IEF_STATE_BODY_SkinDetailFactor_start 159 #define GFX9_SFC_IEF_STATE_BODY_SkinDetailFactor_start 159 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_SkinDetailFactor_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 159; case 120: return 159; case 110: return 159; case 90: return 159; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY::Strong Edge Threshold */ #define GFX125_SFC_IEF_STATE_BODY_StrongEdgeThreshold_bits 6 #define GFX12_SFC_IEF_STATE_BODY_StrongEdgeThreshold_bits 6 #define GFX11_SFC_IEF_STATE_BODY_StrongEdgeThreshold_bits 6 #define GFX9_SFC_IEF_STATE_BODY_StrongEdgeThreshold_bits 6 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_StrongEdgeThreshold_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_IEF_STATE_BODY_StrongEdgeThreshold_start 12 #define GFX12_SFC_IEF_STATE_BODY_StrongEdgeThreshold_start 12 #define GFX11_SFC_IEF_STATE_BODY_StrongEdgeThreshold_start 12 #define GFX9_SFC_IEF_STATE_BODY_StrongEdgeThreshold_start 12 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_StrongEdgeThreshold_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 12; case 120: return 12; case 110: return 12; case 90: return 12; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY::Strong Edge Weight */ #define GFX125_SFC_IEF_STATE_BODY_StrongEdgeWeight_bits 3 #define GFX12_SFC_IEF_STATE_BODY_StrongEdgeWeight_bits 3 #define GFX11_SFC_IEF_STATE_BODY_StrongEdgeWeight_bits 3 #define GFX9_SFC_IEF_STATE_BODY_StrongEdgeWeight_bits 3 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_StrongEdgeWeight_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_IEF_STATE_BODY_StrongEdgeWeight_start 46 #define GFX12_SFC_IEF_STATE_BODY_StrongEdgeWeight_start 46 #define GFX11_SFC_IEF_STATE_BODY_StrongEdgeWeight_start 46 #define GFX9_SFC_IEF_STATE_BODY_StrongEdgeWeight_start 46 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_StrongEdgeWeight_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 46; case 120: return 46; case 110: return 46; case 90: return 46; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY::Transform Enable */ #define GFX125_SFC_IEF_STATE_BODY_TransformEnable_bits 1 #define GFX12_SFC_IEF_STATE_BODY_TransformEnable_bits 1 #define GFX11_SFC_IEF_STATE_BODY_TransformEnable_bits 1 #define GFX9_SFC_IEF_STATE_BODY_TransformEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_TransformEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_IEF_STATE_BODY_TransformEnable_start 480 #define GFX12_SFC_IEF_STATE_BODY_TransformEnable_start 480 #define GFX11_SFC_IEF_STATE_BODY_TransformEnable_start 480 #define GFX9_SFC_IEF_STATE_BODY_TransformEnable_start 480 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_TransformEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 480; case 120: return 480; case 110: return 480; case 90: return 480; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY::U_Mid */ #define GFX125_SFC_IEF_STATE_BODY_U_Mid_bits 8 #define GFX12_SFC_IEF_STATE_BODY_U_Mid_bits 8 #define GFX11_SFC_IEF_STATE_BODY_U_Mid_bits 8 #define GFX9_SFC_IEF_STATE_BODY_U_Mid_bits 8 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_U_Mid_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_IEF_STATE_BODY_U_Mid_start 112 #define GFX12_SFC_IEF_STATE_BODY_U_Mid_start 112 #define GFX11_SFC_IEF_STATE_BODY_U_Mid_start 112 #define GFX9_SFC_IEF_STATE_BODY_U_Mid_start 112 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_U_Mid_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 112; case 120: return 112; case 110: return 112; case 90: return 112; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY::VY_STD_Enable */ #define GFX125_SFC_IEF_STATE_BODY_VY_STD_Enable_bits 1 #define GFX12_SFC_IEF_STATE_BODY_VY_STD_Enable_bits 1 #define GFX11_SFC_IEF_STATE_BODY_VY_STD_Enable_bits 1 #define GFX9_SFC_IEF_STATE_BODY_VY_STD_Enable_bits 1 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_VY_STD_Enable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_IEF_STATE_BODY_VY_STD_Enable_start 111 #define GFX12_SFC_IEF_STATE_BODY_VY_STD_Enable_start 111 #define GFX11_SFC_IEF_STATE_BODY_VY_STD_Enable_start 111 #define GFX9_SFC_IEF_STATE_BODY_VY_STD_Enable_start 111 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_VY_STD_Enable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 111; case 120: return 111; case 110: return 111; case 90: return 111; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY::V_Mid */ #define GFX125_SFC_IEF_STATE_BODY_V_Mid_bits 8 #define GFX12_SFC_IEF_STATE_BODY_V_Mid_bits 8 #define GFX11_SFC_IEF_STATE_BODY_V_Mid_bits 8 #define GFX9_SFC_IEF_STATE_BODY_V_Mid_bits 8 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_V_Mid_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_IEF_STATE_BODY_V_Mid_start 120 #define GFX12_SFC_IEF_STATE_BODY_V_Mid_start 120 #define GFX11_SFC_IEF_STATE_BODY_V_Mid_start 120 #define GFX9_SFC_IEF_STATE_BODY_V_Mid_start 120 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_V_Mid_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 120; case 120: return 120; case 110: return 120; case 90: return 120; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY::Weak Edge Threshold */ #define GFX125_SFC_IEF_STATE_BODY_WeakEdgeThreshold_bits 6 #define GFX12_SFC_IEF_STATE_BODY_WeakEdgeThreshold_bits 6 #define GFX11_SFC_IEF_STATE_BODY_WeakEdgeThreshold_bits 6 #define GFX9_SFC_IEF_STATE_BODY_WeakEdgeThreshold_bits 6 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_WeakEdgeThreshold_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_IEF_STATE_BODY_WeakEdgeThreshold_start 6 #define GFX12_SFC_IEF_STATE_BODY_WeakEdgeThreshold_start 6 #define GFX11_SFC_IEF_STATE_BODY_WeakEdgeThreshold_start 6 #define GFX9_SFC_IEF_STATE_BODY_WeakEdgeThreshold_start 6 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_WeakEdgeThreshold_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY::YUV Channel Swap */ #define GFX125_SFC_IEF_STATE_BODY_YUVChannelSwap_bits 1 #define GFX12_SFC_IEF_STATE_BODY_YUVChannelSwap_bits 1 #define GFX11_SFC_IEF_STATE_BODY_YUVChannelSwap_bits 1 #define GFX9_SFC_IEF_STATE_BODY_YUVChannelSwap_bits 1 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_YUVChannelSwap_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_IEF_STATE_BODY_YUVChannelSwap_start 481 #define GFX12_SFC_IEF_STATE_BODY_YUVChannelSwap_start 481 #define GFX11_SFC_IEF_STATE_BODY_YUVChannelSwap_start 481 #define GFX9_SFC_IEF_STATE_BODY_YUVChannelSwap_start 481 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_YUVChannelSwap_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 481; case 120: return 481; case 110: return 481; case 90: return 481; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY::Y_Slope1 */ #define GFX125_SFC_IEF_STATE_BODY_Y_Slope1_bits 5 #define GFX12_SFC_IEF_STATE_BODY_Y_Slope1_bits 5 #define GFX11_SFC_IEF_STATE_BODY_Y_Slope1_bits 5 #define GFX9_SFC_IEF_STATE_BODY_Y_Slope1_bits 5 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_Y_Slope1_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 5; case 110: return 5; case 90: return 5; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_IEF_STATE_BODY_Y_Slope1_start 379 #define GFX12_SFC_IEF_STATE_BODY_Y_Slope1_start 379 #define GFX11_SFC_IEF_STATE_BODY_Y_Slope1_start 379 #define GFX9_SFC_IEF_STATE_BODY_Y_Slope1_start 379 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_Y_Slope1_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 379; case 120: return 379; case 110: return 379; case 90: return 379; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY::Y_Slope_2 */ #define GFX125_SFC_IEF_STATE_BODY_Y_Slope_2_bits 5 #define GFX12_SFC_IEF_STATE_BODY_Y_Slope_2_bits 5 #define GFX11_SFC_IEF_STATE_BODY_Y_Slope_2_bits 5 #define GFX9_SFC_IEF_STATE_BODY_Y_Slope_2_bits 5 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_Y_Slope_2_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 5; case 110: return 5; case 90: return 5; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_IEF_STATE_BODY_Y_Slope_2_start 315 #define GFX12_SFC_IEF_STATE_BODY_Y_Slope_2_start 315 #define GFX11_SFC_IEF_STATE_BODY_Y_Slope_2_start 315 #define GFX9_SFC_IEF_STATE_BODY_Y_Slope_2_start 315 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_Y_Slope_2_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 315; case 120: return 315; case 110: return 315; case 90: return 315; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY::Y_point_1 */ #define GFX125_SFC_IEF_STATE_BODY_Y_point_1_bits 8 #define GFX12_SFC_IEF_STATE_BODY_Y_point_1_bits 8 #define GFX11_SFC_IEF_STATE_BODY_Y_point_1_bits 8 #define GFX9_SFC_IEF_STATE_BODY_Y_point_1_bits 8 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_Y_point_1_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_IEF_STATE_BODY_Y_point_1_start 160 #define GFX12_SFC_IEF_STATE_BODY_Y_point_1_start 160 #define GFX11_SFC_IEF_STATE_BODY_Y_point_1_start 160 #define GFX9_SFC_IEF_STATE_BODY_Y_point_1_start 160 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_Y_point_1_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 160; case 120: return 160; case 110: return 160; case 90: return 160; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY::Y_point_2 */ #define GFX125_SFC_IEF_STATE_BODY_Y_point_2_bits 8 #define GFX12_SFC_IEF_STATE_BODY_Y_point_2_bits 8 #define GFX11_SFC_IEF_STATE_BODY_Y_point_2_bits 8 #define GFX9_SFC_IEF_STATE_BODY_Y_point_2_bits 8 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_Y_point_2_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_IEF_STATE_BODY_Y_point_2_start 168 #define GFX12_SFC_IEF_STATE_BODY_Y_point_2_start 168 #define GFX11_SFC_IEF_STATE_BODY_Y_point_2_start 168 #define GFX9_SFC_IEF_STATE_BODY_Y_point_2_start 168 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_Y_point_2_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 168; case 120: return 168; case 110: return 168; case 90: return 168; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY::Y_point_3 */ #define GFX125_SFC_IEF_STATE_BODY_Y_point_3_bits 8 #define GFX12_SFC_IEF_STATE_BODY_Y_point_3_bits 8 #define GFX11_SFC_IEF_STATE_BODY_Y_point_3_bits 8 #define GFX9_SFC_IEF_STATE_BODY_Y_point_3_bits 8 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_Y_point_3_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_IEF_STATE_BODY_Y_point_3_start 176 #define GFX12_SFC_IEF_STATE_BODY_Y_point_3_start 176 #define GFX11_SFC_IEF_STATE_BODY_Y_point_3_start 176 #define GFX9_SFC_IEF_STATE_BODY_Y_point_3_start 176 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_Y_point_3_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 176; case 120: return 176; case 110: return 176; case 90: return 176; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_IEF_STATE_BODY::Y_point_4 */ #define GFX125_SFC_IEF_STATE_BODY_Y_point_4_bits 8 #define GFX12_SFC_IEF_STATE_BODY_Y_point_4_bits 8 #define GFX11_SFC_IEF_STATE_BODY_Y_point_4_bits 8 #define GFX9_SFC_IEF_STATE_BODY_Y_point_4_bits 8 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_Y_point_4_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_IEF_STATE_BODY_Y_point_4_start 184 #define GFX12_SFC_IEF_STATE_BODY_Y_point_4_start 184 #define GFX11_SFC_IEF_STATE_BODY_Y_point_4_start 184 #define GFX9_SFC_IEF_STATE_BODY_Y_point_4_start 184 static inline uint32_t ATTRIBUTE_PURE SFC_IEF_STATE_BODY_Y_point_4_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 184; case 120: return 184; case 110: return 184; case 90: return 184; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_LOCK_BODY */ #define GFX125_SFC_LOCK_BODY_length 1 #define GFX12_SFC_LOCK_BODY_length 1 #define GFX11_SFC_LOCK_BODY_length 1 #define GFX9_SFC_LOCK_BODY_length 1 static inline uint32_t ATTRIBUTE_PURE SFC_LOCK_BODY_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_LOCK_BODY::Pre-Scaled Output Surface Output Enable */ #define GFX125_SFC_LOCK_BODY_PreScaledOutputSurfaceOutputEnable_bits 1 #define GFX12_SFC_LOCK_BODY_PreScaledOutputSurfaceOutputEnable_bits 1 #define GFX11_SFC_LOCK_BODY_PreScaledOutputSurfaceOutputEnable_bits 1 #define GFX9_SFC_LOCK_BODY_PreScaledOutputSurfaceOutputEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE SFC_LOCK_BODY_PreScaledOutputSurfaceOutputEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_LOCK_BODY_PreScaledOutputSurfaceOutputEnable_start 1 #define GFX12_SFC_LOCK_BODY_PreScaledOutputSurfaceOutputEnable_start 1 #define GFX11_SFC_LOCK_BODY_PreScaledOutputSurfaceOutputEnable_start 1 #define GFX9_SFC_LOCK_BODY_PreScaledOutputSurfaceOutputEnable_start 1 static inline uint32_t ATTRIBUTE_PURE SFC_LOCK_BODY_PreScaledOutputSurfaceOutputEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SFC_LOCK_BODY::VE-SFC Pipe Select */ #define GFX125_SFC_LOCK_BODY_VESFCPipeSelect_bits 1 #define GFX12_SFC_LOCK_BODY_VESFCPipeSelect_bits 1 #define GFX11_SFC_LOCK_BODY_VESFCPipeSelect_bits 1 #define GFX9_SFC_LOCK_BODY_VESFCPipeSelect_bits 1 static inline uint32_t ATTRIBUTE_PURE SFC_LOCK_BODY_VESFCPipeSelect_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SFC_LOCK_BODY_VESFCPipeSelect_start 0 #define GFX12_SFC_LOCK_BODY_VESFCPipeSelect_start 0 #define GFX11_SFC_LOCK_BODY_VESFCPipeSelect_start 0 #define GFX9_SFC_LOCK_BODY_VESFCPipeSelect_start 0 static inline uint32_t ATTRIBUTE_PURE SFC_LOCK_BODY_VESFCPipeSelect_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SF_CLIP_VIEWPORT */ #define GFX125_SF_CLIP_VIEWPORT_length 16 #define GFX12_SF_CLIP_VIEWPORT_length 16 #define GFX11_SF_CLIP_VIEWPORT_length 16 #define GFX9_SF_CLIP_VIEWPORT_length 16 #define GFX8_SF_CLIP_VIEWPORT_length 16 #define GFX75_SF_CLIP_VIEWPORT_length 16 #define GFX7_SF_CLIP_VIEWPORT_length 16 static inline uint32_t ATTRIBUTE_PURE SF_CLIP_VIEWPORT_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SF_CLIP_VIEWPORT::Viewport Matrix Element m00 */ #define GFX125_SF_CLIP_VIEWPORT_ViewportMatrixElementm00_bits 32 #define GFX12_SF_CLIP_VIEWPORT_ViewportMatrixElementm00_bits 32 #define GFX11_SF_CLIP_VIEWPORT_ViewportMatrixElementm00_bits 32 #define GFX9_SF_CLIP_VIEWPORT_ViewportMatrixElementm00_bits 32 #define GFX8_SF_CLIP_VIEWPORT_ViewportMatrixElementm00_bits 32 #define GFX75_SF_CLIP_VIEWPORT_ViewportMatrixElementm00_bits 32 #define GFX7_SF_CLIP_VIEWPORT_ViewportMatrixElementm00_bits 32 static inline uint32_t ATTRIBUTE_PURE SF_CLIP_VIEWPORT_ViewportMatrixElementm00_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SF_CLIP_VIEWPORT_ViewportMatrixElementm00_start 0 #define GFX12_SF_CLIP_VIEWPORT_ViewportMatrixElementm00_start 0 #define GFX11_SF_CLIP_VIEWPORT_ViewportMatrixElementm00_start 0 #define GFX9_SF_CLIP_VIEWPORT_ViewportMatrixElementm00_start 0 #define GFX8_SF_CLIP_VIEWPORT_ViewportMatrixElementm00_start 0 #define GFX75_SF_CLIP_VIEWPORT_ViewportMatrixElementm00_start 0 #define GFX7_SF_CLIP_VIEWPORT_ViewportMatrixElementm00_start 0 static inline uint32_t ATTRIBUTE_PURE SF_CLIP_VIEWPORT_ViewportMatrixElementm00_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SF_CLIP_VIEWPORT::Viewport Matrix Element m11 */ #define GFX125_SF_CLIP_VIEWPORT_ViewportMatrixElementm11_bits 32 #define GFX12_SF_CLIP_VIEWPORT_ViewportMatrixElementm11_bits 32 #define GFX11_SF_CLIP_VIEWPORT_ViewportMatrixElementm11_bits 32 #define GFX9_SF_CLIP_VIEWPORT_ViewportMatrixElementm11_bits 32 #define GFX8_SF_CLIP_VIEWPORT_ViewportMatrixElementm11_bits 32 #define GFX75_SF_CLIP_VIEWPORT_ViewportMatrixElementm11_bits 32 #define GFX7_SF_CLIP_VIEWPORT_ViewportMatrixElementm11_bits 32 static inline uint32_t ATTRIBUTE_PURE SF_CLIP_VIEWPORT_ViewportMatrixElementm11_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SF_CLIP_VIEWPORT_ViewportMatrixElementm11_start 32 #define GFX12_SF_CLIP_VIEWPORT_ViewportMatrixElementm11_start 32 #define GFX11_SF_CLIP_VIEWPORT_ViewportMatrixElementm11_start 32 #define GFX9_SF_CLIP_VIEWPORT_ViewportMatrixElementm11_start 32 #define GFX8_SF_CLIP_VIEWPORT_ViewportMatrixElementm11_start 32 #define GFX75_SF_CLIP_VIEWPORT_ViewportMatrixElementm11_start 32 #define GFX7_SF_CLIP_VIEWPORT_ViewportMatrixElementm11_start 32 static inline uint32_t ATTRIBUTE_PURE SF_CLIP_VIEWPORT_ViewportMatrixElementm11_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SF_CLIP_VIEWPORT::Viewport Matrix Element m22 */ #define GFX125_SF_CLIP_VIEWPORT_ViewportMatrixElementm22_bits 32 #define GFX12_SF_CLIP_VIEWPORT_ViewportMatrixElementm22_bits 32 #define GFX11_SF_CLIP_VIEWPORT_ViewportMatrixElementm22_bits 32 #define GFX9_SF_CLIP_VIEWPORT_ViewportMatrixElementm22_bits 32 #define GFX8_SF_CLIP_VIEWPORT_ViewportMatrixElementm22_bits 32 #define GFX75_SF_CLIP_VIEWPORT_ViewportMatrixElementm22_bits 32 #define GFX7_SF_CLIP_VIEWPORT_ViewportMatrixElementm22_bits 32 static inline uint32_t ATTRIBUTE_PURE SF_CLIP_VIEWPORT_ViewportMatrixElementm22_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SF_CLIP_VIEWPORT_ViewportMatrixElementm22_start 64 #define GFX12_SF_CLIP_VIEWPORT_ViewportMatrixElementm22_start 64 #define GFX11_SF_CLIP_VIEWPORT_ViewportMatrixElementm22_start 64 #define GFX9_SF_CLIP_VIEWPORT_ViewportMatrixElementm22_start 64 #define GFX8_SF_CLIP_VIEWPORT_ViewportMatrixElementm22_start 64 #define GFX75_SF_CLIP_VIEWPORT_ViewportMatrixElementm22_start 64 #define GFX7_SF_CLIP_VIEWPORT_ViewportMatrixElementm22_start 64 static inline uint32_t ATTRIBUTE_PURE SF_CLIP_VIEWPORT_ViewportMatrixElementm22_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 64; case 80: return 64; case 75: return 64; case 70: return 64; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SF_CLIP_VIEWPORT::Viewport Matrix Element m30 */ #define GFX125_SF_CLIP_VIEWPORT_ViewportMatrixElementm30_bits 32 #define GFX12_SF_CLIP_VIEWPORT_ViewportMatrixElementm30_bits 32 #define GFX11_SF_CLIP_VIEWPORT_ViewportMatrixElementm30_bits 32 #define GFX9_SF_CLIP_VIEWPORT_ViewportMatrixElementm30_bits 32 #define GFX8_SF_CLIP_VIEWPORT_ViewportMatrixElementm30_bits 32 #define GFX75_SF_CLIP_VIEWPORT_ViewportMatrixElementm30_bits 32 #define GFX7_SF_CLIP_VIEWPORT_ViewportMatrixElementm30_bits 32 static inline uint32_t ATTRIBUTE_PURE SF_CLIP_VIEWPORT_ViewportMatrixElementm30_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SF_CLIP_VIEWPORT_ViewportMatrixElementm30_start 96 #define GFX12_SF_CLIP_VIEWPORT_ViewportMatrixElementm30_start 96 #define GFX11_SF_CLIP_VIEWPORT_ViewportMatrixElementm30_start 96 #define GFX9_SF_CLIP_VIEWPORT_ViewportMatrixElementm30_start 96 #define GFX8_SF_CLIP_VIEWPORT_ViewportMatrixElementm30_start 96 #define GFX75_SF_CLIP_VIEWPORT_ViewportMatrixElementm30_start 96 #define GFX7_SF_CLIP_VIEWPORT_ViewportMatrixElementm30_start 96 static inline uint32_t ATTRIBUTE_PURE SF_CLIP_VIEWPORT_ViewportMatrixElementm30_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 96; case 120: return 96; case 110: return 96; case 90: return 96; case 80: return 96; case 75: return 96; case 70: return 96; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SF_CLIP_VIEWPORT::Viewport Matrix Element m31 */ #define GFX125_SF_CLIP_VIEWPORT_ViewportMatrixElementm31_bits 32 #define GFX12_SF_CLIP_VIEWPORT_ViewportMatrixElementm31_bits 32 #define GFX11_SF_CLIP_VIEWPORT_ViewportMatrixElementm31_bits 32 #define GFX9_SF_CLIP_VIEWPORT_ViewportMatrixElementm31_bits 32 #define GFX8_SF_CLIP_VIEWPORT_ViewportMatrixElementm31_bits 32 #define GFX75_SF_CLIP_VIEWPORT_ViewportMatrixElementm31_bits 32 #define GFX7_SF_CLIP_VIEWPORT_ViewportMatrixElementm31_bits 32 static inline uint32_t ATTRIBUTE_PURE SF_CLIP_VIEWPORT_ViewportMatrixElementm31_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SF_CLIP_VIEWPORT_ViewportMatrixElementm31_start 128 #define GFX12_SF_CLIP_VIEWPORT_ViewportMatrixElementm31_start 128 #define GFX11_SF_CLIP_VIEWPORT_ViewportMatrixElementm31_start 128 #define GFX9_SF_CLIP_VIEWPORT_ViewportMatrixElementm31_start 128 #define GFX8_SF_CLIP_VIEWPORT_ViewportMatrixElementm31_start 128 #define GFX75_SF_CLIP_VIEWPORT_ViewportMatrixElementm31_start 128 #define GFX7_SF_CLIP_VIEWPORT_ViewportMatrixElementm31_start 128 static inline uint32_t ATTRIBUTE_PURE SF_CLIP_VIEWPORT_ViewportMatrixElementm31_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 128; case 120: return 128; case 110: return 128; case 90: return 128; case 80: return 128; case 75: return 128; case 70: return 128; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SF_CLIP_VIEWPORT::Viewport Matrix Element m32 */ #define GFX125_SF_CLIP_VIEWPORT_ViewportMatrixElementm32_bits 32 #define GFX12_SF_CLIP_VIEWPORT_ViewportMatrixElementm32_bits 32 #define GFX11_SF_CLIP_VIEWPORT_ViewportMatrixElementm32_bits 32 #define GFX9_SF_CLIP_VIEWPORT_ViewportMatrixElementm32_bits 32 #define GFX8_SF_CLIP_VIEWPORT_ViewportMatrixElementm32_bits 32 #define GFX75_SF_CLIP_VIEWPORT_ViewportMatrixElementm32_bits 32 #define GFX7_SF_CLIP_VIEWPORT_ViewportMatrixElementm32_bits 32 static inline uint32_t ATTRIBUTE_PURE SF_CLIP_VIEWPORT_ViewportMatrixElementm32_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SF_CLIP_VIEWPORT_ViewportMatrixElementm32_start 160 #define GFX12_SF_CLIP_VIEWPORT_ViewportMatrixElementm32_start 160 #define GFX11_SF_CLIP_VIEWPORT_ViewportMatrixElementm32_start 160 #define GFX9_SF_CLIP_VIEWPORT_ViewportMatrixElementm32_start 160 #define GFX8_SF_CLIP_VIEWPORT_ViewportMatrixElementm32_start 160 #define GFX75_SF_CLIP_VIEWPORT_ViewportMatrixElementm32_start 160 #define GFX7_SF_CLIP_VIEWPORT_ViewportMatrixElementm32_start 160 static inline uint32_t ATTRIBUTE_PURE SF_CLIP_VIEWPORT_ViewportMatrixElementm32_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 160; case 120: return 160; case 110: return 160; case 90: return 160; case 80: return 160; case 75: return 160; case 70: return 160; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SF_CLIP_VIEWPORT::X Max Clip Guardband */ #define GFX125_SF_CLIP_VIEWPORT_XMaxClipGuardband_bits 32 #define GFX12_SF_CLIP_VIEWPORT_XMaxClipGuardband_bits 32 #define GFX11_SF_CLIP_VIEWPORT_XMaxClipGuardband_bits 32 #define GFX9_SF_CLIP_VIEWPORT_XMaxClipGuardband_bits 32 #define GFX8_SF_CLIP_VIEWPORT_XMaxClipGuardband_bits 32 #define GFX75_SF_CLIP_VIEWPORT_XMaxClipGuardband_bits 32 #define GFX7_SF_CLIP_VIEWPORT_XMaxClipGuardband_bits 32 static inline uint32_t ATTRIBUTE_PURE SF_CLIP_VIEWPORT_XMaxClipGuardband_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SF_CLIP_VIEWPORT_XMaxClipGuardband_start 288 #define GFX12_SF_CLIP_VIEWPORT_XMaxClipGuardband_start 288 #define GFX11_SF_CLIP_VIEWPORT_XMaxClipGuardband_start 288 #define GFX9_SF_CLIP_VIEWPORT_XMaxClipGuardband_start 288 #define GFX8_SF_CLIP_VIEWPORT_XMaxClipGuardband_start 288 #define GFX75_SF_CLIP_VIEWPORT_XMaxClipGuardband_start 288 #define GFX7_SF_CLIP_VIEWPORT_XMaxClipGuardband_start 288 static inline uint32_t ATTRIBUTE_PURE SF_CLIP_VIEWPORT_XMaxClipGuardband_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 288; case 120: return 288; case 110: return 288; case 90: return 288; case 80: return 288; case 75: return 288; case 70: return 288; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SF_CLIP_VIEWPORT::X Max ViewPort */ #define GFX125_SF_CLIP_VIEWPORT_XMaxViewPort_bits 32 #define GFX12_SF_CLIP_VIEWPORT_XMaxViewPort_bits 32 #define GFX11_SF_CLIP_VIEWPORT_XMaxViewPort_bits 32 #define GFX9_SF_CLIP_VIEWPORT_XMaxViewPort_bits 32 #define GFX8_SF_CLIP_VIEWPORT_XMaxViewPort_bits 32 static inline uint32_t ATTRIBUTE_PURE SF_CLIP_VIEWPORT_XMaxViewPort_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SF_CLIP_VIEWPORT_XMaxViewPort_start 416 #define GFX12_SF_CLIP_VIEWPORT_XMaxViewPort_start 416 #define GFX11_SF_CLIP_VIEWPORT_XMaxViewPort_start 416 #define GFX9_SF_CLIP_VIEWPORT_XMaxViewPort_start 416 #define GFX8_SF_CLIP_VIEWPORT_XMaxViewPort_start 416 static inline uint32_t ATTRIBUTE_PURE SF_CLIP_VIEWPORT_XMaxViewPort_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 416; case 120: return 416; case 110: return 416; case 90: return 416; case 80: return 416; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SF_CLIP_VIEWPORT::X Min Clip Guardband */ #define GFX125_SF_CLIP_VIEWPORT_XMinClipGuardband_bits 32 #define GFX12_SF_CLIP_VIEWPORT_XMinClipGuardband_bits 32 #define GFX11_SF_CLIP_VIEWPORT_XMinClipGuardband_bits 32 #define GFX9_SF_CLIP_VIEWPORT_XMinClipGuardband_bits 32 #define GFX8_SF_CLIP_VIEWPORT_XMinClipGuardband_bits 32 #define GFX75_SF_CLIP_VIEWPORT_XMinClipGuardband_bits 32 #define GFX7_SF_CLIP_VIEWPORT_XMinClipGuardband_bits 32 static inline uint32_t ATTRIBUTE_PURE SF_CLIP_VIEWPORT_XMinClipGuardband_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SF_CLIP_VIEWPORT_XMinClipGuardband_start 256 #define GFX12_SF_CLIP_VIEWPORT_XMinClipGuardband_start 256 #define GFX11_SF_CLIP_VIEWPORT_XMinClipGuardband_start 256 #define GFX9_SF_CLIP_VIEWPORT_XMinClipGuardband_start 256 #define GFX8_SF_CLIP_VIEWPORT_XMinClipGuardband_start 256 #define GFX75_SF_CLIP_VIEWPORT_XMinClipGuardband_start 256 #define GFX7_SF_CLIP_VIEWPORT_XMinClipGuardband_start 256 static inline uint32_t ATTRIBUTE_PURE SF_CLIP_VIEWPORT_XMinClipGuardband_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 256; case 120: return 256; case 110: return 256; case 90: return 256; case 80: return 256; case 75: return 256; case 70: return 256; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SF_CLIP_VIEWPORT::X Min ViewPort */ #define GFX125_SF_CLIP_VIEWPORT_XMinViewPort_bits 32 #define GFX12_SF_CLIP_VIEWPORT_XMinViewPort_bits 32 #define GFX11_SF_CLIP_VIEWPORT_XMinViewPort_bits 32 #define GFX9_SF_CLIP_VIEWPORT_XMinViewPort_bits 32 #define GFX8_SF_CLIP_VIEWPORT_XMinViewPort_bits 32 static inline uint32_t ATTRIBUTE_PURE SF_CLIP_VIEWPORT_XMinViewPort_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SF_CLIP_VIEWPORT_XMinViewPort_start 384 #define GFX12_SF_CLIP_VIEWPORT_XMinViewPort_start 384 #define GFX11_SF_CLIP_VIEWPORT_XMinViewPort_start 384 #define GFX9_SF_CLIP_VIEWPORT_XMinViewPort_start 384 #define GFX8_SF_CLIP_VIEWPORT_XMinViewPort_start 384 static inline uint32_t ATTRIBUTE_PURE SF_CLIP_VIEWPORT_XMinViewPort_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 384; case 120: return 384; case 110: return 384; case 90: return 384; case 80: return 384; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SF_CLIP_VIEWPORT::Y Max Clip Guardband */ #define GFX125_SF_CLIP_VIEWPORT_YMaxClipGuardband_bits 32 #define GFX12_SF_CLIP_VIEWPORT_YMaxClipGuardband_bits 32 #define GFX11_SF_CLIP_VIEWPORT_YMaxClipGuardband_bits 32 #define GFX9_SF_CLIP_VIEWPORT_YMaxClipGuardband_bits 32 #define GFX8_SF_CLIP_VIEWPORT_YMaxClipGuardband_bits 32 #define GFX75_SF_CLIP_VIEWPORT_YMaxClipGuardband_bits 32 #define GFX7_SF_CLIP_VIEWPORT_YMaxClipGuardband_bits 32 static inline uint32_t ATTRIBUTE_PURE SF_CLIP_VIEWPORT_YMaxClipGuardband_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SF_CLIP_VIEWPORT_YMaxClipGuardband_start 352 #define GFX12_SF_CLIP_VIEWPORT_YMaxClipGuardband_start 352 #define GFX11_SF_CLIP_VIEWPORT_YMaxClipGuardband_start 352 #define GFX9_SF_CLIP_VIEWPORT_YMaxClipGuardband_start 352 #define GFX8_SF_CLIP_VIEWPORT_YMaxClipGuardband_start 352 #define GFX75_SF_CLIP_VIEWPORT_YMaxClipGuardband_start 352 #define GFX7_SF_CLIP_VIEWPORT_YMaxClipGuardband_start 352 static inline uint32_t ATTRIBUTE_PURE SF_CLIP_VIEWPORT_YMaxClipGuardband_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 352; case 120: return 352; case 110: return 352; case 90: return 352; case 80: return 352; case 75: return 352; case 70: return 352; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SF_CLIP_VIEWPORT::Y Max ViewPort */ #define GFX125_SF_CLIP_VIEWPORT_YMaxViewPort_bits 32 #define GFX12_SF_CLIP_VIEWPORT_YMaxViewPort_bits 32 #define GFX11_SF_CLIP_VIEWPORT_YMaxViewPort_bits 32 #define GFX9_SF_CLIP_VIEWPORT_YMaxViewPort_bits 32 #define GFX8_SF_CLIP_VIEWPORT_YMaxViewPort_bits 32 static inline uint32_t ATTRIBUTE_PURE SF_CLIP_VIEWPORT_YMaxViewPort_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SF_CLIP_VIEWPORT_YMaxViewPort_start 480 #define GFX12_SF_CLIP_VIEWPORT_YMaxViewPort_start 480 #define GFX11_SF_CLIP_VIEWPORT_YMaxViewPort_start 480 #define GFX9_SF_CLIP_VIEWPORT_YMaxViewPort_start 480 #define GFX8_SF_CLIP_VIEWPORT_YMaxViewPort_start 480 static inline uint32_t ATTRIBUTE_PURE SF_CLIP_VIEWPORT_YMaxViewPort_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 480; case 120: return 480; case 110: return 480; case 90: return 480; case 80: return 480; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SF_CLIP_VIEWPORT::Y Min Clip Guardband */ #define GFX125_SF_CLIP_VIEWPORT_YMinClipGuardband_bits 32 #define GFX12_SF_CLIP_VIEWPORT_YMinClipGuardband_bits 32 #define GFX11_SF_CLIP_VIEWPORT_YMinClipGuardband_bits 32 #define GFX9_SF_CLIP_VIEWPORT_YMinClipGuardband_bits 32 #define GFX8_SF_CLIP_VIEWPORT_YMinClipGuardband_bits 32 #define GFX75_SF_CLIP_VIEWPORT_YMinClipGuardband_bits 32 #define GFX7_SF_CLIP_VIEWPORT_YMinClipGuardband_bits 32 static inline uint32_t ATTRIBUTE_PURE SF_CLIP_VIEWPORT_YMinClipGuardband_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SF_CLIP_VIEWPORT_YMinClipGuardband_start 320 #define GFX12_SF_CLIP_VIEWPORT_YMinClipGuardband_start 320 #define GFX11_SF_CLIP_VIEWPORT_YMinClipGuardband_start 320 #define GFX9_SF_CLIP_VIEWPORT_YMinClipGuardband_start 320 #define GFX8_SF_CLIP_VIEWPORT_YMinClipGuardband_start 320 #define GFX75_SF_CLIP_VIEWPORT_YMinClipGuardband_start 320 #define GFX7_SF_CLIP_VIEWPORT_YMinClipGuardband_start 320 static inline uint32_t ATTRIBUTE_PURE SF_CLIP_VIEWPORT_YMinClipGuardband_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 320; case 120: return 320; case 110: return 320; case 90: return 320; case 80: return 320; case 75: return 320; case 70: return 320; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SF_CLIP_VIEWPORT::Y Min ViewPort */ #define GFX125_SF_CLIP_VIEWPORT_YMinViewPort_bits 32 #define GFX12_SF_CLIP_VIEWPORT_YMinViewPort_bits 32 #define GFX11_SF_CLIP_VIEWPORT_YMinViewPort_bits 32 #define GFX9_SF_CLIP_VIEWPORT_YMinViewPort_bits 32 #define GFX8_SF_CLIP_VIEWPORT_YMinViewPort_bits 32 static inline uint32_t ATTRIBUTE_PURE SF_CLIP_VIEWPORT_YMinViewPort_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SF_CLIP_VIEWPORT_YMinViewPort_start 448 #define GFX12_SF_CLIP_VIEWPORT_YMinViewPort_start 448 #define GFX11_SF_CLIP_VIEWPORT_YMinViewPort_start 448 #define GFX9_SF_CLIP_VIEWPORT_YMinViewPort_start 448 #define GFX8_SF_CLIP_VIEWPORT_YMinViewPort_start 448 static inline uint32_t ATTRIBUTE_PURE SF_CLIP_VIEWPORT_YMinViewPort_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 448; case 120: return 448; case 110: return 448; case 90: return 448; case 80: return 448; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SF_OUTPUT_ATTRIBUTE_DETAIL */ #define GFX125_SF_OUTPUT_ATTRIBUTE_DETAIL_length 1 #define GFX12_SF_OUTPUT_ATTRIBUTE_DETAIL_length 1 #define GFX11_SF_OUTPUT_ATTRIBUTE_DETAIL_length 1 #define GFX9_SF_OUTPUT_ATTRIBUTE_DETAIL_length 1 #define GFX8_SF_OUTPUT_ATTRIBUTE_DETAIL_length 1 #define GFX75_SF_OUTPUT_ATTRIBUTE_DETAIL_length 1 #define GFX7_SF_OUTPUT_ATTRIBUTE_DETAIL_length 1 #define GFX6_SF_OUTPUT_ATTRIBUTE_DETAIL_length 1 static inline uint32_t ATTRIBUTE_PURE SF_OUTPUT_ATTRIBUTE_DETAIL_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SF_OUTPUT_ATTRIBUTE_DETAIL::Component Override W */ #define GFX125_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideW_bits 1 #define GFX12_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideW_bits 1 #define GFX11_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideW_bits 1 #define GFX9_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideW_bits 1 #define GFX8_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideW_bits 1 #define GFX75_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideW_bits 1 #define GFX7_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideW_bits 1 #define GFX6_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideW_bits 1 static inline uint32_t ATTRIBUTE_PURE SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideW_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideW_start 15 #define GFX12_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideW_start 15 #define GFX11_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideW_start 15 #define GFX9_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideW_start 15 #define GFX8_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideW_start 15 #define GFX75_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideW_start 15 #define GFX7_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideW_start 15 #define GFX6_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideW_start 15 static inline uint32_t ATTRIBUTE_PURE SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideW_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 15; case 120: return 15; case 110: return 15; case 90: return 15; case 80: return 15; case 75: return 15; case 70: return 15; case 60: return 15; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SF_OUTPUT_ATTRIBUTE_DETAIL::Component Override X */ #define GFX125_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideX_bits 1 #define GFX12_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideX_bits 1 #define GFX11_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideX_bits 1 #define GFX9_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideX_bits 1 #define GFX8_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideX_bits 1 #define GFX75_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideX_bits 1 #define GFX7_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideX_bits 1 #define GFX6_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideX_bits 1 static inline uint32_t ATTRIBUTE_PURE SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideX_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideX_start 12 #define GFX12_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideX_start 12 #define GFX11_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideX_start 12 #define GFX9_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideX_start 12 #define GFX8_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideX_start 12 #define GFX75_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideX_start 12 #define GFX7_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideX_start 12 #define GFX6_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideX_start 12 static inline uint32_t ATTRIBUTE_PURE SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideX_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 12; case 120: return 12; case 110: return 12; case 90: return 12; case 80: return 12; case 75: return 12; case 70: return 12; case 60: return 12; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SF_OUTPUT_ATTRIBUTE_DETAIL::Component Override Y */ #define GFX125_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideY_bits 1 #define GFX12_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideY_bits 1 #define GFX11_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideY_bits 1 #define GFX9_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideY_bits 1 #define GFX8_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideY_bits 1 #define GFX75_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideY_bits 1 #define GFX7_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideY_bits 1 #define GFX6_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideY_bits 1 static inline uint32_t ATTRIBUTE_PURE SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideY_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideY_start 13 #define GFX12_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideY_start 13 #define GFX11_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideY_start 13 #define GFX9_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideY_start 13 #define GFX8_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideY_start 13 #define GFX75_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideY_start 13 #define GFX7_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideY_start 13 #define GFX6_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideY_start 13 static inline uint32_t ATTRIBUTE_PURE SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideY_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 13; case 120: return 13; case 110: return 13; case 90: return 13; case 80: return 13; case 75: return 13; case 70: return 13; case 60: return 13; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SF_OUTPUT_ATTRIBUTE_DETAIL::Component Override Z */ #define GFX125_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideZ_bits 1 #define GFX12_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideZ_bits 1 #define GFX11_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideZ_bits 1 #define GFX9_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideZ_bits 1 #define GFX8_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideZ_bits 1 #define GFX75_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideZ_bits 1 #define GFX7_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideZ_bits 1 #define GFX6_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideZ_bits 1 static inline uint32_t ATTRIBUTE_PURE SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideZ_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideZ_start 14 #define GFX12_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideZ_start 14 #define GFX11_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideZ_start 14 #define GFX9_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideZ_start 14 #define GFX8_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideZ_start 14 #define GFX75_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideZ_start 14 #define GFX7_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideZ_start 14 #define GFX6_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideZ_start 14 static inline uint32_t ATTRIBUTE_PURE SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideZ_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 14; case 120: return 14; case 110: return 14; case 90: return 14; case 80: return 14; case 75: return 14; case 70: return 14; case 60: return 14; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SF_OUTPUT_ATTRIBUTE_DETAIL::Constant Source */ #define GFX125_SF_OUTPUT_ATTRIBUTE_DETAIL_ConstantSource_bits 2 #define GFX12_SF_OUTPUT_ATTRIBUTE_DETAIL_ConstantSource_bits 2 #define GFX11_SF_OUTPUT_ATTRIBUTE_DETAIL_ConstantSource_bits 2 #define GFX9_SF_OUTPUT_ATTRIBUTE_DETAIL_ConstantSource_bits 2 #define GFX8_SF_OUTPUT_ATTRIBUTE_DETAIL_ConstantSource_bits 2 #define GFX75_SF_OUTPUT_ATTRIBUTE_DETAIL_ConstantSource_bits 2 #define GFX7_SF_OUTPUT_ATTRIBUTE_DETAIL_ConstantSource_bits 2 #define GFX6_SF_OUTPUT_ATTRIBUTE_DETAIL_ConstantSource_bits 2 static inline uint32_t ATTRIBUTE_PURE SF_OUTPUT_ATTRIBUTE_DETAIL_ConstantSource_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SF_OUTPUT_ATTRIBUTE_DETAIL_ConstantSource_start 9 #define GFX12_SF_OUTPUT_ATTRIBUTE_DETAIL_ConstantSource_start 9 #define GFX11_SF_OUTPUT_ATTRIBUTE_DETAIL_ConstantSource_start 9 #define GFX9_SF_OUTPUT_ATTRIBUTE_DETAIL_ConstantSource_start 9 #define GFX8_SF_OUTPUT_ATTRIBUTE_DETAIL_ConstantSource_start 9 #define GFX75_SF_OUTPUT_ATTRIBUTE_DETAIL_ConstantSource_start 9 #define GFX7_SF_OUTPUT_ATTRIBUTE_DETAIL_ConstantSource_start 9 #define GFX6_SF_OUTPUT_ATTRIBUTE_DETAIL_ConstantSource_start 9 static inline uint32_t ATTRIBUTE_PURE SF_OUTPUT_ATTRIBUTE_DETAIL_ConstantSource_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 9; case 120: return 9; case 110: return 9; case 90: return 9; case 80: return 9; case 75: return 9; case 70: return 9; case 60: return 9; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SF_OUTPUT_ATTRIBUTE_DETAIL::Source Attribute */ #define GFX125_SF_OUTPUT_ATTRIBUTE_DETAIL_SourceAttribute_bits 5 #define GFX12_SF_OUTPUT_ATTRIBUTE_DETAIL_SourceAttribute_bits 5 #define GFX11_SF_OUTPUT_ATTRIBUTE_DETAIL_SourceAttribute_bits 5 #define GFX9_SF_OUTPUT_ATTRIBUTE_DETAIL_SourceAttribute_bits 5 #define GFX8_SF_OUTPUT_ATTRIBUTE_DETAIL_SourceAttribute_bits 5 #define GFX75_SF_OUTPUT_ATTRIBUTE_DETAIL_SourceAttribute_bits 5 #define GFX7_SF_OUTPUT_ATTRIBUTE_DETAIL_SourceAttribute_bits 5 #define GFX6_SF_OUTPUT_ATTRIBUTE_DETAIL_SourceAttribute_bits 5 static inline uint32_t ATTRIBUTE_PURE SF_OUTPUT_ATTRIBUTE_DETAIL_SourceAttribute_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 5; case 110: return 5; case 90: return 5; case 80: return 5; case 75: return 5; case 70: return 5; case 60: return 5; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SF_OUTPUT_ATTRIBUTE_DETAIL_SourceAttribute_start 0 #define GFX12_SF_OUTPUT_ATTRIBUTE_DETAIL_SourceAttribute_start 0 #define GFX11_SF_OUTPUT_ATTRIBUTE_DETAIL_SourceAttribute_start 0 #define GFX9_SF_OUTPUT_ATTRIBUTE_DETAIL_SourceAttribute_start 0 #define GFX8_SF_OUTPUT_ATTRIBUTE_DETAIL_SourceAttribute_start 0 #define GFX75_SF_OUTPUT_ATTRIBUTE_DETAIL_SourceAttribute_start 0 #define GFX7_SF_OUTPUT_ATTRIBUTE_DETAIL_SourceAttribute_start 0 #define GFX6_SF_OUTPUT_ATTRIBUTE_DETAIL_SourceAttribute_start 0 static inline uint32_t ATTRIBUTE_PURE SF_OUTPUT_ATTRIBUTE_DETAIL_SourceAttribute_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SF_OUTPUT_ATTRIBUTE_DETAIL::Swizzle Control Mode */ #define GFX125_SF_OUTPUT_ATTRIBUTE_DETAIL_SwizzleControlMode_bits 1 #define GFX12_SF_OUTPUT_ATTRIBUTE_DETAIL_SwizzleControlMode_bits 1 #define GFX11_SF_OUTPUT_ATTRIBUTE_DETAIL_SwizzleControlMode_bits 1 #define GFX9_SF_OUTPUT_ATTRIBUTE_DETAIL_SwizzleControlMode_bits 1 #define GFX8_SF_OUTPUT_ATTRIBUTE_DETAIL_SwizzleControlMode_bits 1 #define GFX75_SF_OUTPUT_ATTRIBUTE_DETAIL_SwizzleControlMode_bits 1 #define GFX7_SF_OUTPUT_ATTRIBUTE_DETAIL_SwizzleControlMode_bits 1 #define GFX6_SF_OUTPUT_ATTRIBUTE_DETAIL_SwizzleControlMode_bits 1 static inline uint32_t ATTRIBUTE_PURE SF_OUTPUT_ATTRIBUTE_DETAIL_SwizzleControlMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SF_OUTPUT_ATTRIBUTE_DETAIL_SwizzleControlMode_start 11 #define GFX12_SF_OUTPUT_ATTRIBUTE_DETAIL_SwizzleControlMode_start 11 #define GFX11_SF_OUTPUT_ATTRIBUTE_DETAIL_SwizzleControlMode_start 11 #define GFX9_SF_OUTPUT_ATTRIBUTE_DETAIL_SwizzleControlMode_start 11 #define GFX8_SF_OUTPUT_ATTRIBUTE_DETAIL_SwizzleControlMode_start 11 #define GFX75_SF_OUTPUT_ATTRIBUTE_DETAIL_SwizzleControlMode_start 11 #define GFX7_SF_OUTPUT_ATTRIBUTE_DETAIL_SwizzleControlMode_start 11 #define GFX6_SF_OUTPUT_ATTRIBUTE_DETAIL_SwizzleControlMode_start 11 static inline uint32_t ATTRIBUTE_PURE SF_OUTPUT_ATTRIBUTE_DETAIL_SwizzleControlMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 11; case 120: return 11; case 110: return 11; case 90: return 11; case 80: return 11; case 75: return 11; case 70: return 11; case 60: return 11; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SF_OUTPUT_ATTRIBUTE_DETAIL::Swizzle Select */ #define GFX125_SF_OUTPUT_ATTRIBUTE_DETAIL_SwizzleSelect_bits 2 #define GFX12_SF_OUTPUT_ATTRIBUTE_DETAIL_SwizzleSelect_bits 2 #define GFX11_SF_OUTPUT_ATTRIBUTE_DETAIL_SwizzleSelect_bits 2 #define GFX9_SF_OUTPUT_ATTRIBUTE_DETAIL_SwizzleSelect_bits 2 #define GFX8_SF_OUTPUT_ATTRIBUTE_DETAIL_SwizzleSelect_bits 2 #define GFX75_SF_OUTPUT_ATTRIBUTE_DETAIL_SwizzleSelect_bits 2 #define GFX7_SF_OUTPUT_ATTRIBUTE_DETAIL_SwizzleSelect_bits 2 #define GFX6_SF_OUTPUT_ATTRIBUTE_DETAIL_SwizzleSelect_bits 2 static inline uint32_t ATTRIBUTE_PURE SF_OUTPUT_ATTRIBUTE_DETAIL_SwizzleSelect_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SF_OUTPUT_ATTRIBUTE_DETAIL_SwizzleSelect_start 6 #define GFX12_SF_OUTPUT_ATTRIBUTE_DETAIL_SwizzleSelect_start 6 #define GFX11_SF_OUTPUT_ATTRIBUTE_DETAIL_SwizzleSelect_start 6 #define GFX9_SF_OUTPUT_ATTRIBUTE_DETAIL_SwizzleSelect_start 6 #define GFX8_SF_OUTPUT_ATTRIBUTE_DETAIL_SwizzleSelect_start 6 #define GFX75_SF_OUTPUT_ATTRIBUTE_DETAIL_SwizzleSelect_start 6 #define GFX7_SF_OUTPUT_ATTRIBUTE_DETAIL_SwizzleSelect_start 6 #define GFX6_SF_OUTPUT_ATTRIBUTE_DETAIL_SwizzleSelect_start 6 static inline uint32_t ATTRIBUTE_PURE SF_OUTPUT_ATTRIBUTE_DETAIL_SwizzleSelect_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 6; case 60: return 6; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SF_STATE */ #define GFX5_SF_STATE_length 8 #define GFX45_SF_STATE_length 8 #define GFX4_SF_STATE_length 8 static inline uint32_t ATTRIBUTE_PURE SF_STATE_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 8; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } /* SF_STATE::2x2 Pixel Triangle Filter Disable */ #define GFX5_SF_STATE_2x2PixelTriangleFilterDisable_bits 1 #define GFX45_SF_STATE_2x2PixelTriangleFilterDisable_bits 1 #define GFX4_SF_STATE_2x2PixelTriangleFilterDisable_bits 1 static inline uint32_t ATTRIBUTE_PURE SF_STATE_2x2PixelTriangleFilterDisable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_SF_STATE_2x2PixelTriangleFilterDisable_start 210 #define GFX45_SF_STATE_2x2PixelTriangleFilterDisable_start 210 #define GFX4_SF_STATE_2x2PixelTriangleFilterDisable_start 210 static inline uint32_t ATTRIBUTE_PURE SF_STATE_2x2PixelTriangleFilterDisable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 210; case 45: return 210; case 40: return 210; default: unreachable("Invalid hardware generation"); } } /* SF_STATE::AA Line Distance Mode */ #define GFX5_SF_STATE_AALineDistanceMode_bits 1 #define GFX45_SF_STATE_AALineDistanceMode_bits 1 static inline uint32_t ATTRIBUTE_PURE SF_STATE_AALineDistanceMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX5_SF_STATE_AALineDistanceMode_start 238 #define GFX45_SF_STATE_AALineDistanceMode_start 238 static inline uint32_t ATTRIBUTE_PURE SF_STATE_AALineDistanceMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 238; case 45: return 238; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SF_STATE::Antialiasing Enable */ #define GFX5_SF_STATE_AntialiasingEnable_bits 1 #define GFX45_SF_STATE_AntialiasingEnable_bits 1 #define GFX4_SF_STATE_AntialiasingEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE SF_STATE_AntialiasingEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_SF_STATE_AntialiasingEnable_start 223 #define GFX45_SF_STATE_AntialiasingEnable_start 223 #define GFX4_SF_STATE_AntialiasingEnable_start 223 static inline uint32_t ATTRIBUTE_PURE SF_STATE_AntialiasingEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 223; case 45: return 223; case 40: return 223; default: unreachable("Invalid hardware generation"); } } /* SF_STATE::Binding Table Entry Count */ #define GFX5_SF_STATE_BindingTableEntryCount_bits 8 #define GFX45_SF_STATE_BindingTableEntryCount_bits 8 #define GFX4_SF_STATE_BindingTableEntryCount_bits 8 static inline uint32_t ATTRIBUTE_PURE SF_STATE_BindingTableEntryCount_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 8; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } #define GFX5_SF_STATE_BindingTableEntryCount_start 50 #define GFX45_SF_STATE_BindingTableEntryCount_start 50 #define GFX4_SF_STATE_BindingTableEntryCount_start 50 static inline uint32_t ATTRIBUTE_PURE SF_STATE_BindingTableEntryCount_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 50; case 45: return 50; case 40: return 50; default: unreachable("Invalid hardware generation"); } } /* SF_STATE::Constant URB Entry Read Length */ #define GFX5_SF_STATE_ConstantURBEntryReadLength_bits 6 #define GFX45_SF_STATE_ConstantURBEntryReadLength_bits 6 #define GFX4_SF_STATE_ConstantURBEntryReadLength_bits 6 static inline uint32_t ATTRIBUTE_PURE SF_STATE_ConstantURBEntryReadLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 6; case 45: return 6; case 40: return 6; default: unreachable("Invalid hardware generation"); } } #define GFX5_SF_STATE_ConstantURBEntryReadLength_start 121 #define GFX45_SF_STATE_ConstantURBEntryReadLength_start 121 #define GFX4_SF_STATE_ConstantURBEntryReadLength_start 121 static inline uint32_t ATTRIBUTE_PURE SF_STATE_ConstantURBEntryReadLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 121; case 45: return 121; case 40: return 121; default: unreachable("Invalid hardware generation"); } } /* SF_STATE::Constant URB Entry Read Offset */ #define GFX5_SF_STATE_ConstantURBEntryReadOffset_bits 6 #define GFX45_SF_STATE_ConstantURBEntryReadOffset_bits 6 #define GFX4_SF_STATE_ConstantURBEntryReadOffset_bits 6 static inline uint32_t ATTRIBUTE_PURE SF_STATE_ConstantURBEntryReadOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 6; case 45: return 6; case 40: return 6; default: unreachable("Invalid hardware generation"); } } #define GFX5_SF_STATE_ConstantURBEntryReadOffset_start 114 #define GFX45_SF_STATE_ConstantURBEntryReadOffset_start 114 #define GFX4_SF_STATE_ConstantURBEntryReadOffset_start 114 static inline uint32_t ATTRIBUTE_PURE SF_STATE_ConstantURBEntryReadOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 114; case 45: return 114; case 40: return 114; default: unreachable("Invalid hardware generation"); } } /* SF_STATE::Cull Mode */ #define GFX5_SF_STATE_CullMode_bits 2 #define GFX45_SF_STATE_CullMode_bits 2 #define GFX4_SF_STATE_CullMode_bits 2 static inline uint32_t ATTRIBUTE_PURE SF_STATE_CullMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 2; case 45: return 2; case 40: return 2; default: unreachable("Invalid hardware generation"); } } #define GFX5_SF_STATE_CullMode_start 221 #define GFX45_SF_STATE_CullMode_start 221 #define GFX4_SF_STATE_CullMode_start 221 static inline uint32_t ATTRIBUTE_PURE SF_STATE_CullMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 221; case 45: return 221; case 40: return 221; default: unreachable("Invalid hardware generation"); } } /* SF_STATE::Destination Origin Horizontal Bias */ #define GFX5_SF_STATE_DestinationOriginHorizontalBias_bits 4 #define GFX45_SF_STATE_DestinationOriginHorizontalBias_bits 4 #define GFX4_SF_STATE_DestinationOriginHorizontalBias_bits 4 static inline uint32_t ATTRIBUTE_PURE SF_STATE_DestinationOriginHorizontalBias_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 4; case 45: return 4; case 40: return 4; default: unreachable("Invalid hardware generation"); } } #define GFX5_SF_STATE_DestinationOriginHorizontalBias_start 205 #define GFX45_SF_STATE_DestinationOriginHorizontalBias_start 205 #define GFX4_SF_STATE_DestinationOriginHorizontalBias_start 205 static inline uint32_t ATTRIBUTE_PURE SF_STATE_DestinationOriginHorizontalBias_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 205; case 45: return 205; case 40: return 205; default: unreachable("Invalid hardware generation"); } } /* SF_STATE::Destination Origin Vertical Bias */ #define GFX5_SF_STATE_DestinationOriginVerticalBias_bits 4 #define GFX45_SF_STATE_DestinationOriginVerticalBias_bits 4 #define GFX4_SF_STATE_DestinationOriginVerticalBias_bits 4 static inline uint32_t ATTRIBUTE_PURE SF_STATE_DestinationOriginVerticalBias_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 4; case 45: return 4; case 40: return 4; default: unreachable("Invalid hardware generation"); } } #define GFX5_SF_STATE_DestinationOriginVerticalBias_start 201 #define GFX45_SF_STATE_DestinationOriginVerticalBias_start 201 #define GFX4_SF_STATE_DestinationOriginVerticalBias_start 201 static inline uint32_t ATTRIBUTE_PURE SF_STATE_DestinationOriginVerticalBias_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 201; case 45: return 201; case 40: return 201; default: unreachable("Invalid hardware generation"); } } /* SF_STATE::Dispatch GRF Start Register For URB Data */ #define GFX5_SF_STATE_DispatchGRFStartRegisterForURBData_bits 4 #define GFX45_SF_STATE_DispatchGRFStartRegisterForURBData_bits 4 #define GFX4_SF_STATE_DispatchGRFStartRegisterForURBData_bits 4 static inline uint32_t ATTRIBUTE_PURE SF_STATE_DispatchGRFStartRegisterForURBData_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 4; case 45: return 4; case 40: return 4; default: unreachable("Invalid hardware generation"); } } #define GFX5_SF_STATE_DispatchGRFStartRegisterForURBData_start 96 #define GFX45_SF_STATE_DispatchGRFStartRegisterForURBData_start 96 #define GFX4_SF_STATE_DispatchGRFStartRegisterForURBData_start 96 static inline uint32_t ATTRIBUTE_PURE SF_STATE_DispatchGRFStartRegisterForURBData_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 96; case 45: return 96; case 40: return 96; default: unreachable("Invalid hardware generation"); } } /* SF_STATE::Fast Scissor Clip Disable */ #define GFX5_SF_STATE_FastScissorClipDisable_bits 1 #define GFX45_SF_STATE_FastScissorClipDisable_bits 1 #define GFX4_SF_STATE_FastScissorClipDisable_bits 1 static inline uint32_t ATTRIBUTE_PURE SF_STATE_FastScissorClipDisable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_SF_STATE_FastScissorClipDisable_start 220 #define GFX45_SF_STATE_FastScissorClipDisable_start 220 #define GFX4_SF_STATE_FastScissorClipDisable_start 220 static inline uint32_t ATTRIBUTE_PURE SF_STATE_FastScissorClipDisable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 220; case 45: return 220; case 40: return 220; default: unreachable("Invalid hardware generation"); } } /* SF_STATE::Floating Point Mode */ #define GFX5_SF_STATE_FloatingPointMode_bits 1 #define GFX45_SF_STATE_FloatingPointMode_bits 1 #define GFX4_SF_STATE_FloatingPointMode_bits 1 static inline uint32_t ATTRIBUTE_PURE SF_STATE_FloatingPointMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_SF_STATE_FloatingPointMode_start 48 #define GFX45_SF_STATE_FloatingPointMode_start 48 #define GFX4_SF_STATE_FloatingPointMode_start 48 static inline uint32_t ATTRIBUTE_PURE SF_STATE_FloatingPointMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 48; case 45: return 48; case 40: return 48; default: unreachable("Invalid hardware generation"); } } /* SF_STATE::Front Winding */ #define GFX5_SF_STATE_FrontWinding_bits 1 #define GFX45_SF_STATE_FrontWinding_bits 1 #define GFX4_SF_STATE_FrontWinding_bits 1 static inline uint32_t ATTRIBUTE_PURE SF_STATE_FrontWinding_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_SF_STATE_FrontWinding_start 160 #define GFX45_SF_STATE_FrontWinding_start 160 #define GFX4_SF_STATE_FrontWinding_start 160 static inline uint32_t ATTRIBUTE_PURE SF_STATE_FrontWinding_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 160; case 45: return 160; case 40: return 160; default: unreachable("Invalid hardware generation"); } } /* SF_STATE::GRF Register Count */ #define GFX5_SF_STATE_GRFRegisterCount_bits 3 #define GFX45_SF_STATE_GRFRegisterCount_bits 3 #define GFX4_SF_STATE_GRFRegisterCount_bits 3 static inline uint32_t ATTRIBUTE_PURE SF_STATE_GRFRegisterCount_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX5_SF_STATE_GRFRegisterCount_start 1 #define GFX45_SF_STATE_GRFRegisterCount_start 1 #define GFX4_SF_STATE_GRFRegisterCount_start 1 static inline uint32_t ATTRIBUTE_PURE SF_STATE_GRFRegisterCount_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } /* SF_STATE::Illegal Opcode Exception Enable */ #define GFX5_SF_STATE_IllegalOpcodeExceptionEnable_bits 1 #define GFX45_SF_STATE_IllegalOpcodeExceptionEnable_bits 1 #define GFX4_SF_STATE_IllegalOpcodeExceptionEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE SF_STATE_IllegalOpcodeExceptionEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_SF_STATE_IllegalOpcodeExceptionEnable_start 45 #define GFX45_SF_STATE_IllegalOpcodeExceptionEnable_start 45 #define GFX4_SF_STATE_IllegalOpcodeExceptionEnable_start 45 static inline uint32_t ATTRIBUTE_PURE SF_STATE_IllegalOpcodeExceptionEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 45; case 45: return 45; case 40: return 45; default: unreachable("Invalid hardware generation"); } } /* SF_STATE::Kernel Start Pointer */ #define GFX5_SF_STATE_KernelStartPointer_bits 26 #define GFX45_SF_STATE_KernelStartPointer_bits 26 #define GFX4_SF_STATE_KernelStartPointer_bits 26 static inline uint32_t ATTRIBUTE_PURE SF_STATE_KernelStartPointer_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 26; case 45: return 26; case 40: return 26; default: unreachable("Invalid hardware generation"); } } #define GFX5_SF_STATE_KernelStartPointer_start 6 #define GFX45_SF_STATE_KernelStartPointer_start 6 #define GFX4_SF_STATE_KernelStartPointer_start 6 static inline uint32_t ATTRIBUTE_PURE SF_STATE_KernelStartPointer_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 6; case 45: return 6; case 40: return 6; default: unreachable("Invalid hardware generation"); } } /* SF_STATE::Last Pixel Enable */ #define GFX5_SF_STATE_LastPixelEnable_bits 1 #define GFX45_SF_STATE_LastPixelEnable_bits 1 #define GFX4_SF_STATE_LastPixelEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE SF_STATE_LastPixelEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_SF_STATE_LastPixelEnable_start 255 #define GFX45_SF_STATE_LastPixelEnable_start 255 #define GFX4_SF_STATE_LastPixelEnable_start 255 static inline uint32_t ATTRIBUTE_PURE SF_STATE_LastPixelEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 255; case 45: return 255; case 40: return 255; default: unreachable("Invalid hardware generation"); } } /* SF_STATE::Line End Cap Antialiasing Region Width */ #define GFX5_SF_STATE_LineEndCapAntialiasingRegionWidth_bits 2 #define GFX45_SF_STATE_LineEndCapAntialiasingRegionWidth_bits 2 #define GFX4_SF_STATE_LineEndCapAntialiasingRegionWidth_bits 2 static inline uint32_t ATTRIBUTE_PURE SF_STATE_LineEndCapAntialiasingRegionWidth_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 2; case 45: return 2; case 40: return 2; default: unreachable("Invalid hardware generation"); } } #define GFX5_SF_STATE_LineEndCapAntialiasingRegionWidth_start 214 #define GFX45_SF_STATE_LineEndCapAntialiasingRegionWidth_start 214 #define GFX4_SF_STATE_LineEndCapAntialiasingRegionWidth_start 214 static inline uint32_t ATTRIBUTE_PURE SF_STATE_LineEndCapAntialiasingRegionWidth_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 214; case 45: return 214; case 40: return 214; default: unreachable("Invalid hardware generation"); } } /* SF_STATE::Line Strip/List Provoking Vertex Select */ #define GFX5_SF_STATE_LineStripListProvokingVertexSelect_bits 2 #define GFX45_SF_STATE_LineStripListProvokingVertexSelect_bits 2 #define GFX4_SF_STATE_LineStripListProvokingVertexSelect_bits 2 static inline uint32_t ATTRIBUTE_PURE SF_STATE_LineStripListProvokingVertexSelect_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 2; case 45: return 2; case 40: return 2; default: unreachable("Invalid hardware generation"); } } #define GFX5_SF_STATE_LineStripListProvokingVertexSelect_start 251 #define GFX45_SF_STATE_LineStripListProvokingVertexSelect_start 251 #define GFX4_SF_STATE_LineStripListProvokingVertexSelect_start 251 static inline uint32_t ATTRIBUTE_PURE SF_STATE_LineStripListProvokingVertexSelect_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 251; case 45: return 251; case 40: return 251; default: unreachable("Invalid hardware generation"); } } /* SF_STATE::Line Width */ #define GFX5_SF_STATE_LineWidth_bits 4 #define GFX45_SF_STATE_LineWidth_bits 4 #define GFX4_SF_STATE_LineWidth_bits 4 static inline uint32_t ATTRIBUTE_PURE SF_STATE_LineWidth_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 4; case 45: return 4; case 40: return 4; default: unreachable("Invalid hardware generation"); } } #define GFX5_SF_STATE_LineWidth_start 216 #define GFX45_SF_STATE_LineWidth_start 216 #define GFX4_SF_STATE_LineWidth_start 216 static inline uint32_t ATTRIBUTE_PURE SF_STATE_LineWidth_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 216; case 45: return 216; case 40: return 216; default: unreachable("Invalid hardware generation"); } } /* SF_STATE::Mask Stack Exception Enable */ #define GFX5_SF_STATE_MaskStackExceptionEnable_bits 1 #define GFX45_SF_STATE_MaskStackExceptionEnable_bits 1 #define GFX4_SF_STATE_MaskStackExceptionEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE SF_STATE_MaskStackExceptionEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_SF_STATE_MaskStackExceptionEnable_start 43 #define GFX45_SF_STATE_MaskStackExceptionEnable_start 43 #define GFX4_SF_STATE_MaskStackExceptionEnable_start 43 static inline uint32_t ATTRIBUTE_PURE SF_STATE_MaskStackExceptionEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 43; case 45: return 43; case 40: return 43; default: unreachable("Invalid hardware generation"); } } /* SF_STATE::Maximum Number of Threads */ #define GFX5_SF_STATE_MaximumNumberofThreads_bits 6 #define GFX45_SF_STATE_MaximumNumberofThreads_bits 6 #define GFX4_SF_STATE_MaximumNumberofThreads_bits 6 static inline uint32_t ATTRIBUTE_PURE SF_STATE_MaximumNumberofThreads_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 6; case 45: return 6; case 40: return 6; default: unreachable("Invalid hardware generation"); } } #define GFX5_SF_STATE_MaximumNumberofThreads_start 153 #define GFX45_SF_STATE_MaximumNumberofThreads_start 153 #define GFX4_SF_STATE_MaximumNumberofThreads_start 153 static inline uint32_t ATTRIBUTE_PURE SF_STATE_MaximumNumberofThreads_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 153; case 45: return 153; case 40: return 153; default: unreachable("Invalid hardware generation"); } } /* SF_STATE::Number of URB Entries */ #define GFX5_SF_STATE_NumberofURBEntries_bits 8 #define GFX45_SF_STATE_NumberofURBEntries_bits 8 #define GFX4_SF_STATE_NumberofURBEntries_bits 8 static inline uint32_t ATTRIBUTE_PURE SF_STATE_NumberofURBEntries_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 8; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } #define GFX5_SF_STATE_NumberofURBEntries_start 139 #define GFX45_SF_STATE_NumberofURBEntries_start 139 #define GFX4_SF_STATE_NumberofURBEntries_start 139 static inline uint32_t ATTRIBUTE_PURE SF_STATE_NumberofURBEntries_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 139; case 45: return 139; case 40: return 139; default: unreachable("Invalid hardware generation"); } } /* SF_STATE::Per-Thread Scratch Space */ #define GFX5_SF_STATE_PerThreadScratchSpace_bits 4 #define GFX45_SF_STATE_PerThreadScratchSpace_bits 4 #define GFX4_SF_STATE_PerThreadScratchSpace_bits 4 static inline uint32_t ATTRIBUTE_PURE SF_STATE_PerThreadScratchSpace_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 4; case 45: return 4; case 40: return 4; default: unreachable("Invalid hardware generation"); } } #define GFX5_SF_STATE_PerThreadScratchSpace_start 64 #define GFX45_SF_STATE_PerThreadScratchSpace_start 64 #define GFX4_SF_STATE_PerThreadScratchSpace_start 64 static inline uint32_t ATTRIBUTE_PURE SF_STATE_PerThreadScratchSpace_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 64; case 45: return 64; case 40: return 64; default: unreachable("Invalid hardware generation"); } } /* SF_STATE::Point Rasterization Rule */ #define GFX5_SF_STATE_PointRasterizationRule_bits 2 #define GFX45_SF_STATE_PointRasterizationRule_bits 2 #define GFX4_SF_STATE_PointRasterizationRule_bits 2 static inline uint32_t ATTRIBUTE_PURE SF_STATE_PointRasterizationRule_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 2; case 45: return 2; case 40: return 2; default: unreachable("Invalid hardware generation"); } } #define GFX5_SF_STATE_PointRasterizationRule_start 212 #define GFX45_SF_STATE_PointRasterizationRule_start 212 #define GFX4_SF_STATE_PointRasterizationRule_start 212 static inline uint32_t ATTRIBUTE_PURE SF_STATE_PointRasterizationRule_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 212; case 45: return 212; case 40: return 212; default: unreachable("Invalid hardware generation"); } } /* SF_STATE::Point Width */ #define GFX5_SF_STATE_PointWidth_bits 11 #define GFX45_SF_STATE_PointWidth_bits 11 #define GFX4_SF_STATE_PointWidth_bits 11 static inline uint32_t ATTRIBUTE_PURE SF_STATE_PointWidth_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 11; case 45: return 11; case 40: return 11; default: unreachable("Invalid hardware generation"); } } #define GFX5_SF_STATE_PointWidth_start 224 #define GFX45_SF_STATE_PointWidth_start 224 #define GFX4_SF_STATE_PointWidth_start 224 static inline uint32_t ATTRIBUTE_PURE SF_STATE_PointWidth_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 224; case 45: return 224; case 40: return 224; default: unreachable("Invalid hardware generation"); } } /* SF_STATE::Point Width Source */ #define GFX5_SF_STATE_PointWidthSource_bits 1 #define GFX45_SF_STATE_PointWidthSource_bits 1 #define GFX4_SF_STATE_PointWidthSource_bits 1 static inline uint32_t ATTRIBUTE_PURE SF_STATE_PointWidthSource_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_SF_STATE_PointWidthSource_start 235 #define GFX45_SF_STATE_PointWidthSource_start 235 #define GFX4_SF_STATE_PointWidthSource_start 235 static inline uint32_t ATTRIBUTE_PURE SF_STATE_PointWidthSource_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 235; case 45: return 235; case 40: return 235; default: unreachable("Invalid hardware generation"); } } /* SF_STATE::Scissor Rectangle Enable */ #define GFX5_SF_STATE_ScissorRectangleEnable_bits 1 #define GFX45_SF_STATE_ScissorRectangleEnable_bits 1 #define GFX4_SF_STATE_ScissorRectangleEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE SF_STATE_ScissorRectangleEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_SF_STATE_ScissorRectangleEnable_start 209 #define GFX45_SF_STATE_ScissorRectangleEnable_start 209 #define GFX4_SF_STATE_ScissorRectangleEnable_start 209 static inline uint32_t ATTRIBUTE_PURE SF_STATE_ScissorRectangleEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 209; case 45: return 209; case 40: return 209; default: unreachable("Invalid hardware generation"); } } /* SF_STATE::Scratch Space Base Pointer */ #define GFX5_SF_STATE_ScratchSpaceBasePointer_bits 22 #define GFX45_SF_STATE_ScratchSpaceBasePointer_bits 22 #define GFX4_SF_STATE_ScratchSpaceBasePointer_bits 22 static inline uint32_t ATTRIBUTE_PURE SF_STATE_ScratchSpaceBasePointer_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 22; case 45: return 22; case 40: return 22; default: unreachable("Invalid hardware generation"); } } #define GFX5_SF_STATE_ScratchSpaceBasePointer_start 74 #define GFX45_SF_STATE_ScratchSpaceBasePointer_start 74 #define GFX4_SF_STATE_ScratchSpaceBasePointer_start 74 static inline uint32_t ATTRIBUTE_PURE SF_STATE_ScratchSpaceBasePointer_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 74; case 45: return 74; case 40: return 74; default: unreachable("Invalid hardware generation"); } } /* SF_STATE::Setup Viewport State Offset */ #define GFX5_SF_STATE_SetupViewportStateOffset_bits 27 #define GFX45_SF_STATE_SetupViewportStateOffset_bits 27 #define GFX4_SF_STATE_SetupViewportStateOffset_bits 27 static inline uint32_t ATTRIBUTE_PURE SF_STATE_SetupViewportStateOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 27; case 45: return 27; case 40: return 27; default: unreachable("Invalid hardware generation"); } } #define GFX5_SF_STATE_SetupViewportStateOffset_start 165 #define GFX45_SF_STATE_SetupViewportStateOffset_start 165 #define GFX4_SF_STATE_SetupViewportStateOffset_start 165 static inline uint32_t ATTRIBUTE_PURE SF_STATE_SetupViewportStateOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 165; case 45: return 165; case 40: return 165; default: unreachable("Invalid hardware generation"); } } /* SF_STATE::Single Program Flow */ #define GFX5_SF_STATE_SingleProgramFlow_bits 1 #define GFX45_SF_STATE_SingleProgramFlow_bits 1 #define GFX4_SF_STATE_SingleProgramFlow_bits 1 static inline uint32_t ATTRIBUTE_PURE SF_STATE_SingleProgramFlow_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_SF_STATE_SingleProgramFlow_start 63 #define GFX45_SF_STATE_SingleProgramFlow_start 63 #define GFX4_SF_STATE_SingleProgramFlow_start 63 static inline uint32_t ATTRIBUTE_PURE SF_STATE_SingleProgramFlow_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 63; case 45: return 63; case 40: return 63; default: unreachable("Invalid hardware generation"); } } /* SF_STATE::Software Exception Enable */ #define GFX5_SF_STATE_SoftwareExceptionEnable_bits 1 #define GFX45_SF_STATE_SoftwareExceptionEnable_bits 1 #define GFX4_SF_STATE_SoftwareExceptionEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE SF_STATE_SoftwareExceptionEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_SF_STATE_SoftwareExceptionEnable_start 39 #define GFX45_SF_STATE_SoftwareExceptionEnable_start 39 #define GFX4_SF_STATE_SoftwareExceptionEnable_start 39 static inline uint32_t ATTRIBUTE_PURE SF_STATE_SoftwareExceptionEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 39; case 45: return 39; case 40: return 39; default: unreachable("Invalid hardware generation"); } } /* SF_STATE::Sprite Point Enable */ #define GFX5_SF_STATE_SpritePointEnable_bits 1 #define GFX45_SF_STATE_SpritePointEnable_bits 1 #define GFX4_SF_STATE_SpritePointEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE SF_STATE_SpritePointEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_SF_STATE_SpritePointEnable_start 237 #define GFX45_SF_STATE_SpritePointEnable_start 237 #define GFX4_SF_STATE_SpritePointEnable_start 237 static inline uint32_t ATTRIBUTE_PURE SF_STATE_SpritePointEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 237; case 45: return 237; case 40: return 237; default: unreachable("Invalid hardware generation"); } } /* SF_STATE::Statistics Enable */ #define GFX45_SF_STATE_StatisticsEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE SF_STATE_StatisticsEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 1; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX45_SF_STATE_StatisticsEnable_start 138 static inline uint32_t ATTRIBUTE_PURE SF_STATE_StatisticsEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 138; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SF_STATE::Thread Priority */ #define GFX5_SF_STATE_ThreadPriority_bits 1 #define GFX45_SF_STATE_ThreadPriority_bits 1 #define GFX4_SF_STATE_ThreadPriority_bits 1 static inline uint32_t ATTRIBUTE_PURE SF_STATE_ThreadPriority_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_SF_STATE_ThreadPriority_start 49 #define GFX45_SF_STATE_ThreadPriority_start 49 #define GFX4_SF_STATE_ThreadPriority_start 49 static inline uint32_t ATTRIBUTE_PURE SF_STATE_ThreadPriority_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 49; case 45: return 49; case 40: return 49; default: unreachable("Invalid hardware generation"); } } /* SF_STATE::Triangle Fan Provoking Vertex Select */ #define GFX5_SF_STATE_TriangleFanProvokingVertexSelect_bits 2 #define GFX45_SF_STATE_TriangleFanProvokingVertexSelect_bits 2 #define GFX4_SF_STATE_TriangleFanProvokingVertexSelect_bits 2 static inline uint32_t ATTRIBUTE_PURE SF_STATE_TriangleFanProvokingVertexSelect_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 2; case 45: return 2; case 40: return 2; default: unreachable("Invalid hardware generation"); } } #define GFX5_SF_STATE_TriangleFanProvokingVertexSelect_start 249 #define GFX45_SF_STATE_TriangleFanProvokingVertexSelect_start 249 #define GFX4_SF_STATE_TriangleFanProvokingVertexSelect_start 249 static inline uint32_t ATTRIBUTE_PURE SF_STATE_TriangleFanProvokingVertexSelect_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 249; case 45: return 249; case 40: return 249; default: unreachable("Invalid hardware generation"); } } /* SF_STATE::Triangle Strip/List Provoking Vertex Select */ #define GFX5_SF_STATE_TriangleStripListProvokingVertexSelect_bits 2 #define GFX45_SF_STATE_TriangleStripListProvokingVertexSelect_bits 2 #define GFX4_SF_STATE_TriangleStripListProvokingVertexSelect_bits 2 static inline uint32_t ATTRIBUTE_PURE SF_STATE_TriangleStripListProvokingVertexSelect_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 2; case 45: return 2; case 40: return 2; default: unreachable("Invalid hardware generation"); } } #define GFX5_SF_STATE_TriangleStripListProvokingVertexSelect_start 253 #define GFX45_SF_STATE_TriangleStripListProvokingVertexSelect_start 253 #define GFX4_SF_STATE_TriangleStripListProvokingVertexSelect_start 253 static inline uint32_t ATTRIBUTE_PURE SF_STATE_TriangleStripListProvokingVertexSelect_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 253; case 45: return 253; case 40: return 253; default: unreachable("Invalid hardware generation"); } } /* SF_STATE::URB Entry Allocation Size */ #define GFX5_SF_STATE_URBEntryAllocationSize_bits 5 #define GFX45_SF_STATE_URBEntryAllocationSize_bits 5 #define GFX4_SF_STATE_URBEntryAllocationSize_bits 5 static inline uint32_t ATTRIBUTE_PURE SF_STATE_URBEntryAllocationSize_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 5; case 45: return 5; case 40: return 5; default: unreachable("Invalid hardware generation"); } } #define GFX5_SF_STATE_URBEntryAllocationSize_start 147 #define GFX45_SF_STATE_URBEntryAllocationSize_start 147 #define GFX4_SF_STATE_URBEntryAllocationSize_start 147 static inline uint32_t ATTRIBUTE_PURE SF_STATE_URBEntryAllocationSize_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 147; case 45: return 147; case 40: return 147; default: unreachable("Invalid hardware generation"); } } /* SF_STATE::Vertex Sub Pixel Precision Select */ #define GFX5_SF_STATE_VertexSubPixelPrecisionSelect_bits 1 #define GFX45_SF_STATE_VertexSubPixelPrecisionSelect_bits 1 #define GFX4_SF_STATE_VertexSubPixelPrecisionSelect_bits 1 static inline uint32_t ATTRIBUTE_PURE SF_STATE_VertexSubPixelPrecisionSelect_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_SF_STATE_VertexSubPixelPrecisionSelect_start 236 #define GFX45_SF_STATE_VertexSubPixelPrecisionSelect_start 236 #define GFX4_SF_STATE_VertexSubPixelPrecisionSelect_start 236 static inline uint32_t ATTRIBUTE_PURE SF_STATE_VertexSubPixelPrecisionSelect_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 236; case 45: return 236; case 40: return 236; default: unreachable("Invalid hardware generation"); } } /* SF_STATE::Vertex URB Entry Read Length */ #define GFX5_SF_STATE_VertexURBEntryReadLength_bits 6 #define GFX45_SF_STATE_VertexURBEntryReadLength_bits 6 #define GFX4_SF_STATE_VertexURBEntryReadLength_bits 6 static inline uint32_t ATTRIBUTE_PURE SF_STATE_VertexURBEntryReadLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 6; case 45: return 6; case 40: return 6; default: unreachable("Invalid hardware generation"); } } #define GFX5_SF_STATE_VertexURBEntryReadLength_start 107 #define GFX45_SF_STATE_VertexURBEntryReadLength_start 107 #define GFX4_SF_STATE_VertexURBEntryReadLength_start 107 static inline uint32_t ATTRIBUTE_PURE SF_STATE_VertexURBEntryReadLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 107; case 45: return 107; case 40: return 107; default: unreachable("Invalid hardware generation"); } } /* SF_STATE::Vertex URB Entry Read Offset */ #define GFX5_SF_STATE_VertexURBEntryReadOffset_bits 6 #define GFX45_SF_STATE_VertexURBEntryReadOffset_bits 6 #define GFX4_SF_STATE_VertexURBEntryReadOffset_bits 6 static inline uint32_t ATTRIBUTE_PURE SF_STATE_VertexURBEntryReadOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 6; case 45: return 6; case 40: return 6; default: unreachable("Invalid hardware generation"); } } #define GFX5_SF_STATE_VertexURBEntryReadOffset_start 100 #define GFX45_SF_STATE_VertexURBEntryReadOffset_start 100 #define GFX4_SF_STATE_VertexURBEntryReadOffset_start 100 static inline uint32_t ATTRIBUTE_PURE SF_STATE_VertexURBEntryReadOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 100; case 45: return 100; case 40: return 100; default: unreachable("Invalid hardware generation"); } } /* SF_STATE::Viewport Transform Enable */ #define GFX5_SF_STATE_ViewportTransformEnable_bits 1 #define GFX45_SF_STATE_ViewportTransformEnable_bits 1 #define GFX4_SF_STATE_ViewportTransformEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE SF_STATE_ViewportTransformEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_SF_STATE_ViewportTransformEnable_start 161 #define GFX45_SF_STATE_ViewportTransformEnable_start 161 #define GFX4_SF_STATE_ViewportTransformEnable_start 161 static inline uint32_t ATTRIBUTE_PURE SF_STATE_ViewportTransformEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 161; case 45: return 161; case 40: return 161; default: unreachable("Invalid hardware generation"); } } /* SF_STATE::Zero Pixel Triangle Filter Disable */ #define GFX5_SF_STATE_ZeroPixelTriangleFilterDisable_bits 1 #define GFX45_SF_STATE_ZeroPixelTriangleFilterDisable_bits 1 #define GFX4_SF_STATE_ZeroPixelTriangleFilterDisable_bits 1 static inline uint32_t ATTRIBUTE_PURE SF_STATE_ZeroPixelTriangleFilterDisable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_SF_STATE_ZeroPixelTriangleFilterDisable_start 211 #define GFX45_SF_STATE_ZeroPixelTriangleFilterDisable_start 211 #define GFX4_SF_STATE_ZeroPixelTriangleFilterDisable_start 211 static inline uint32_t ATTRIBUTE_PURE SF_STATE_ZeroPixelTriangleFilterDisable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 211; case 45: return 211; case 40: return 211; default: unreachable("Invalid hardware generation"); } } /* SF_VIEWPORT */ #define GFX6_SF_VIEWPORT_length 8 #define GFX5_SF_VIEWPORT_length 8 #define GFX45_SF_VIEWPORT_length 8 #define GFX4_SF_VIEWPORT_length 8 static inline uint32_t ATTRIBUTE_PURE SF_VIEWPORT_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 8; case 50: return 8; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } /* SF_VIEWPORT::Scissor Rectangle */ #define GFX5_SF_VIEWPORT_ScissorRectangle_bits 64 #define GFX45_SF_VIEWPORT_ScissorRectangle_bits 64 #define GFX4_SF_VIEWPORT_ScissorRectangle_bits 64 static inline uint32_t ATTRIBUTE_PURE SF_VIEWPORT_ScissorRectangle_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 64; case 45: return 64; case 40: return 64; default: unreachable("Invalid hardware generation"); } } #define GFX5_SF_VIEWPORT_ScissorRectangle_start 192 #define GFX45_SF_VIEWPORT_ScissorRectangle_start 192 #define GFX4_SF_VIEWPORT_ScissorRectangle_start 192 static inline uint32_t ATTRIBUTE_PURE SF_VIEWPORT_ScissorRectangle_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 192; case 45: return 192; case 40: return 192; default: unreachable("Invalid hardware generation"); } } /* SF_VIEWPORT::Viewport Matrix Element m00 */ #define GFX6_SF_VIEWPORT_ViewportMatrixElementm00_bits 32 #define GFX5_SF_VIEWPORT_ViewportMatrixElementm00_bits 32 #define GFX45_SF_VIEWPORT_ViewportMatrixElementm00_bits 32 #define GFX4_SF_VIEWPORT_ViewportMatrixElementm00_bits 32 static inline uint32_t ATTRIBUTE_PURE SF_VIEWPORT_ViewportMatrixElementm00_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 32; case 50: return 32; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } #define GFX6_SF_VIEWPORT_ViewportMatrixElementm00_start 0 #define GFX5_SF_VIEWPORT_ViewportMatrixElementm00_start 0 #define GFX45_SF_VIEWPORT_ViewportMatrixElementm00_start 0 #define GFX4_SF_VIEWPORT_ViewportMatrixElementm00_start 0 static inline uint32_t ATTRIBUTE_PURE SF_VIEWPORT_ViewportMatrixElementm00_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SF_VIEWPORT::Viewport Matrix Element m11 */ #define GFX6_SF_VIEWPORT_ViewportMatrixElementm11_bits 32 #define GFX5_SF_VIEWPORT_ViewportMatrixElementm11_bits 32 #define GFX45_SF_VIEWPORT_ViewportMatrixElementm11_bits 32 #define GFX4_SF_VIEWPORT_ViewportMatrixElementm11_bits 32 static inline uint32_t ATTRIBUTE_PURE SF_VIEWPORT_ViewportMatrixElementm11_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 32; case 50: return 32; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } #define GFX6_SF_VIEWPORT_ViewportMatrixElementm11_start 32 #define GFX5_SF_VIEWPORT_ViewportMatrixElementm11_start 32 #define GFX45_SF_VIEWPORT_ViewportMatrixElementm11_start 32 #define GFX4_SF_VIEWPORT_ViewportMatrixElementm11_start 32 static inline uint32_t ATTRIBUTE_PURE SF_VIEWPORT_ViewportMatrixElementm11_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 32; case 50: return 32; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } /* SF_VIEWPORT::Viewport Matrix Element m22 */ #define GFX6_SF_VIEWPORT_ViewportMatrixElementm22_bits 32 #define GFX5_SF_VIEWPORT_ViewportMatrixElementm22_bits 32 #define GFX45_SF_VIEWPORT_ViewportMatrixElementm22_bits 32 #define GFX4_SF_VIEWPORT_ViewportMatrixElementm22_bits 32 static inline uint32_t ATTRIBUTE_PURE SF_VIEWPORT_ViewportMatrixElementm22_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 32; case 50: return 32; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } #define GFX6_SF_VIEWPORT_ViewportMatrixElementm22_start 64 #define GFX5_SF_VIEWPORT_ViewportMatrixElementm22_start 64 #define GFX45_SF_VIEWPORT_ViewportMatrixElementm22_start 64 #define GFX4_SF_VIEWPORT_ViewportMatrixElementm22_start 64 static inline uint32_t ATTRIBUTE_PURE SF_VIEWPORT_ViewportMatrixElementm22_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 64; case 50: return 64; case 45: return 64; case 40: return 64; default: unreachable("Invalid hardware generation"); } } /* SF_VIEWPORT::Viewport Matrix Element m30 */ #define GFX6_SF_VIEWPORT_ViewportMatrixElementm30_bits 32 #define GFX5_SF_VIEWPORT_ViewportMatrixElementm30_bits 32 #define GFX45_SF_VIEWPORT_ViewportMatrixElementm30_bits 32 #define GFX4_SF_VIEWPORT_ViewportMatrixElementm30_bits 32 static inline uint32_t ATTRIBUTE_PURE SF_VIEWPORT_ViewportMatrixElementm30_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 32; case 50: return 32; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } #define GFX6_SF_VIEWPORT_ViewportMatrixElementm30_start 96 #define GFX5_SF_VIEWPORT_ViewportMatrixElementm30_start 96 #define GFX45_SF_VIEWPORT_ViewportMatrixElementm30_start 96 #define GFX4_SF_VIEWPORT_ViewportMatrixElementm30_start 96 static inline uint32_t ATTRIBUTE_PURE SF_VIEWPORT_ViewportMatrixElementm30_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 96; case 50: return 96; case 45: return 96; case 40: return 96; default: unreachable("Invalid hardware generation"); } } /* SF_VIEWPORT::Viewport Matrix Element m31 */ #define GFX6_SF_VIEWPORT_ViewportMatrixElementm31_bits 32 #define GFX5_SF_VIEWPORT_ViewportMatrixElementm31_bits 32 #define GFX45_SF_VIEWPORT_ViewportMatrixElementm31_bits 32 #define GFX4_SF_VIEWPORT_ViewportMatrixElementm31_bits 32 static inline uint32_t ATTRIBUTE_PURE SF_VIEWPORT_ViewportMatrixElementm31_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 32; case 50: return 32; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } #define GFX6_SF_VIEWPORT_ViewportMatrixElementm31_start 128 #define GFX5_SF_VIEWPORT_ViewportMatrixElementm31_start 128 #define GFX45_SF_VIEWPORT_ViewportMatrixElementm31_start 128 #define GFX4_SF_VIEWPORT_ViewportMatrixElementm31_start 128 static inline uint32_t ATTRIBUTE_PURE SF_VIEWPORT_ViewportMatrixElementm31_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 128; case 50: return 128; case 45: return 128; case 40: return 128; default: unreachable("Invalid hardware generation"); } } /* SF_VIEWPORT::Viewport Matrix Element m32 */ #define GFX6_SF_VIEWPORT_ViewportMatrixElementm32_bits 32 #define GFX5_SF_VIEWPORT_ViewportMatrixElementm32_bits 32 #define GFX45_SF_VIEWPORT_ViewportMatrixElementm32_bits 32 #define GFX4_SF_VIEWPORT_ViewportMatrixElementm32_bits 32 static inline uint32_t ATTRIBUTE_PURE SF_VIEWPORT_ViewportMatrixElementm32_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 32; case 50: return 32; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } #define GFX6_SF_VIEWPORT_ViewportMatrixElementm32_start 160 #define GFX5_SF_VIEWPORT_ViewportMatrixElementm32_start 160 #define GFX45_SF_VIEWPORT_ViewportMatrixElementm32_start 160 #define GFX4_SF_VIEWPORT_ViewportMatrixElementm32_start 160 static inline uint32_t ATTRIBUTE_PURE SF_VIEWPORT_ViewportMatrixElementm32_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 160; case 50: return 160; case 45: return 160; case 40: return 160; default: unreachable("Invalid hardware generation"); } } /* SLICE_COMMON_ECO_CHICKEN1 */ #define GFX125_SLICE_COMMON_ECO_CHICKEN1_length 1 #define GFX12_SLICE_COMMON_ECO_CHICKEN1_length 1 #define GFX11_SLICE_COMMON_ECO_CHICKEN1_length 1 #define GFX9_SLICE_COMMON_ECO_CHICKEN1_length 1 static inline uint32_t ATTRIBUTE_PURE SLICE_COMMON_ECO_CHICKEN1_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SLICE_COMMON_ECO_CHICKEN1::GLK Barrier Mode */ #define GFX9_SLICE_COMMON_ECO_CHICKEN1_GLKBarrierMode_bits 1 static inline uint32_t ATTRIBUTE_PURE SLICE_COMMON_ECO_CHICKEN1_GLKBarrierMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_SLICE_COMMON_ECO_CHICKEN1_GLKBarrierMode_start 7 static inline uint32_t ATTRIBUTE_PURE SLICE_COMMON_ECO_CHICKEN1_GLKBarrierMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 7; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SLICE_COMMON_ECO_CHICKEN1::GLK Barrier Mode Mask */ #define GFX9_SLICE_COMMON_ECO_CHICKEN1_GLKBarrierModeMask_bits 1 static inline uint32_t ATTRIBUTE_PURE SLICE_COMMON_ECO_CHICKEN1_GLKBarrierModeMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_SLICE_COMMON_ECO_CHICKEN1_GLKBarrierModeMask_start 23 static inline uint32_t ATTRIBUTE_PURE SLICE_COMMON_ECO_CHICKEN1_GLKBarrierModeMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 23; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SLICE_COMMON_ECO_CHICKEN1::State Cache Redirect To CS Section Enable */ #define GFX125_SLICE_COMMON_ECO_CHICKEN1_StateCacheRedirectToCSSectionEnable_bits 1 #define GFX12_SLICE_COMMON_ECO_CHICKEN1_StateCacheRedirectToCSSectionEnable_bits 1 #define GFX11_SLICE_COMMON_ECO_CHICKEN1_StateCacheRedirectToCSSectionEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE SLICE_COMMON_ECO_CHICKEN1_StateCacheRedirectToCSSectionEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SLICE_COMMON_ECO_CHICKEN1_StateCacheRedirectToCSSectionEnable_start 11 #define GFX12_SLICE_COMMON_ECO_CHICKEN1_StateCacheRedirectToCSSectionEnable_start 11 #define GFX11_SLICE_COMMON_ECO_CHICKEN1_StateCacheRedirectToCSSectionEnable_start 11 static inline uint32_t ATTRIBUTE_PURE SLICE_COMMON_ECO_CHICKEN1_StateCacheRedirectToCSSectionEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 11; case 120: return 11; case 110: return 11; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SLICE_COMMON_ECO_CHICKEN1::State Cache Redirect To CS Section Enable Mask */ #define GFX125_SLICE_COMMON_ECO_CHICKEN1_StateCacheRedirectToCSSectionEnableMask_bits 1 #define GFX12_SLICE_COMMON_ECO_CHICKEN1_StateCacheRedirectToCSSectionEnableMask_bits 1 #define GFX11_SLICE_COMMON_ECO_CHICKEN1_StateCacheRedirectToCSSectionEnableMask_bits 1 static inline uint32_t ATTRIBUTE_PURE SLICE_COMMON_ECO_CHICKEN1_StateCacheRedirectToCSSectionEnableMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SLICE_COMMON_ECO_CHICKEN1_StateCacheRedirectToCSSectionEnableMask_start 27 #define GFX12_SLICE_COMMON_ECO_CHICKEN1_StateCacheRedirectToCSSectionEnableMask_start 27 #define GFX11_SLICE_COMMON_ECO_CHICKEN1_StateCacheRedirectToCSSectionEnableMask_start 27 static inline uint32_t ATTRIBUTE_PURE SLICE_COMMON_ECO_CHICKEN1_StateCacheRedirectToCSSectionEnableMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SLICE_HASH_TABLE */ #define GFX125_SLICE_HASH_TABLE_length 32 #define GFX12_SLICE_HASH_TABLE_length 32 #define GFX11_SLICE_HASH_TABLE_length 32 static inline uint32_t ATTRIBUTE_PURE SLICE_HASH_TABLE_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SO_DECL */ #define GFX125_SO_DECL_length 1 #define GFX12_SO_DECL_length 1 #define GFX11_SO_DECL_length 1 #define GFX9_SO_DECL_length 1 #define GFX8_SO_DECL_length 1 #define GFX75_SO_DECL_length 1 #define GFX7_SO_DECL_length 1 static inline uint32_t ATTRIBUTE_PURE SO_DECL_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SO_DECL::Component Mask */ #define GFX125_SO_DECL_ComponentMask_bits 4 #define GFX12_SO_DECL_ComponentMask_bits 4 #define GFX11_SO_DECL_ComponentMask_bits 4 #define GFX9_SO_DECL_ComponentMask_bits 4 #define GFX8_SO_DECL_ComponentMask_bits 4 #define GFX75_SO_DECL_ComponentMask_bits 4 #define GFX7_SO_DECL_ComponentMask_bits 4 static inline uint32_t ATTRIBUTE_PURE SO_DECL_ComponentMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 4; case 70: return 4; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SO_DECL_ComponentMask_start 0 #define GFX12_SO_DECL_ComponentMask_start 0 #define GFX11_SO_DECL_ComponentMask_start 0 #define GFX9_SO_DECL_ComponentMask_start 0 #define GFX8_SO_DECL_ComponentMask_start 0 #define GFX75_SO_DECL_ComponentMask_start 0 #define GFX7_SO_DECL_ComponentMask_start 0 static inline uint32_t ATTRIBUTE_PURE SO_DECL_ComponentMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SO_DECL::Hole Flag */ #define GFX125_SO_DECL_HoleFlag_bits 1 #define GFX12_SO_DECL_HoleFlag_bits 1 #define GFX11_SO_DECL_HoleFlag_bits 1 #define GFX9_SO_DECL_HoleFlag_bits 1 #define GFX8_SO_DECL_HoleFlag_bits 1 #define GFX75_SO_DECL_HoleFlag_bits 1 #define GFX7_SO_DECL_HoleFlag_bits 1 static inline uint32_t ATTRIBUTE_PURE SO_DECL_HoleFlag_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SO_DECL_HoleFlag_start 11 #define GFX12_SO_DECL_HoleFlag_start 11 #define GFX11_SO_DECL_HoleFlag_start 11 #define GFX9_SO_DECL_HoleFlag_start 11 #define GFX8_SO_DECL_HoleFlag_start 11 #define GFX75_SO_DECL_HoleFlag_start 11 #define GFX7_SO_DECL_HoleFlag_start 11 static inline uint32_t ATTRIBUTE_PURE SO_DECL_HoleFlag_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 11; case 120: return 11; case 110: return 11; case 90: return 11; case 80: return 11; case 75: return 11; case 70: return 11; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SO_DECL::Output Buffer Slot */ #define GFX125_SO_DECL_OutputBufferSlot_bits 2 #define GFX12_SO_DECL_OutputBufferSlot_bits 2 #define GFX11_SO_DECL_OutputBufferSlot_bits 2 #define GFX9_SO_DECL_OutputBufferSlot_bits 2 #define GFX8_SO_DECL_OutputBufferSlot_bits 2 #define GFX75_SO_DECL_OutputBufferSlot_bits 2 #define GFX7_SO_DECL_OutputBufferSlot_bits 2 static inline uint32_t ATTRIBUTE_PURE SO_DECL_OutputBufferSlot_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SO_DECL_OutputBufferSlot_start 12 #define GFX12_SO_DECL_OutputBufferSlot_start 12 #define GFX11_SO_DECL_OutputBufferSlot_start 12 #define GFX9_SO_DECL_OutputBufferSlot_start 12 #define GFX8_SO_DECL_OutputBufferSlot_start 12 #define GFX75_SO_DECL_OutputBufferSlot_start 12 #define GFX7_SO_DECL_OutputBufferSlot_start 12 static inline uint32_t ATTRIBUTE_PURE SO_DECL_OutputBufferSlot_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 12; case 120: return 12; case 110: return 12; case 90: return 12; case 80: return 12; case 75: return 12; case 70: return 12; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SO_DECL::Register Index */ #define GFX125_SO_DECL_RegisterIndex_bits 6 #define GFX12_SO_DECL_RegisterIndex_bits 6 #define GFX11_SO_DECL_RegisterIndex_bits 6 #define GFX9_SO_DECL_RegisterIndex_bits 6 #define GFX8_SO_DECL_RegisterIndex_bits 6 #define GFX75_SO_DECL_RegisterIndex_bits 6 #define GFX7_SO_DECL_RegisterIndex_bits 6 static inline uint32_t ATTRIBUTE_PURE SO_DECL_RegisterIndex_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 6; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SO_DECL_RegisterIndex_start 4 #define GFX12_SO_DECL_RegisterIndex_start 4 #define GFX11_SO_DECL_RegisterIndex_start 4 #define GFX9_SO_DECL_RegisterIndex_start 4 #define GFX8_SO_DECL_RegisterIndex_start 4 #define GFX75_SO_DECL_RegisterIndex_start 4 #define GFX7_SO_DECL_RegisterIndex_start 4 static inline uint32_t ATTRIBUTE_PURE SO_DECL_RegisterIndex_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 4; case 70: return 4; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SO_DECL_ENTRY */ #define GFX125_SO_DECL_ENTRY_length 2 #define GFX12_SO_DECL_ENTRY_length 2 #define GFX11_SO_DECL_ENTRY_length 2 #define GFX9_SO_DECL_ENTRY_length 2 #define GFX8_SO_DECL_ENTRY_length 2 #define GFX75_SO_DECL_ENTRY_length 2 #define GFX7_SO_DECL_ENTRY_length 2 static inline uint32_t ATTRIBUTE_PURE SO_DECL_ENTRY_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SO_DECL_ENTRY::Stream 0 Decl */ #define GFX125_SO_DECL_ENTRY_Stream0Decl_bits 16 #define GFX12_SO_DECL_ENTRY_Stream0Decl_bits 16 #define GFX11_SO_DECL_ENTRY_Stream0Decl_bits 16 #define GFX9_SO_DECL_ENTRY_Stream0Decl_bits 16 #define GFX8_SO_DECL_ENTRY_Stream0Decl_bits 16 #define GFX75_SO_DECL_ENTRY_Stream0Decl_bits 16 #define GFX7_SO_DECL_ENTRY_Stream0Decl_bits 16 static inline uint32_t ATTRIBUTE_PURE SO_DECL_ENTRY_Stream0Decl_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SO_DECL_ENTRY_Stream0Decl_start 0 #define GFX12_SO_DECL_ENTRY_Stream0Decl_start 0 #define GFX11_SO_DECL_ENTRY_Stream0Decl_start 0 #define GFX9_SO_DECL_ENTRY_Stream0Decl_start 0 #define GFX8_SO_DECL_ENTRY_Stream0Decl_start 0 #define GFX75_SO_DECL_ENTRY_Stream0Decl_start 0 #define GFX7_SO_DECL_ENTRY_Stream0Decl_start 0 static inline uint32_t ATTRIBUTE_PURE SO_DECL_ENTRY_Stream0Decl_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SO_DECL_ENTRY::Stream 1 Decl */ #define GFX125_SO_DECL_ENTRY_Stream1Decl_bits 16 #define GFX12_SO_DECL_ENTRY_Stream1Decl_bits 16 #define GFX11_SO_DECL_ENTRY_Stream1Decl_bits 16 #define GFX9_SO_DECL_ENTRY_Stream1Decl_bits 16 #define GFX8_SO_DECL_ENTRY_Stream1Decl_bits 16 #define GFX75_SO_DECL_ENTRY_Stream1Decl_bits 16 #define GFX7_SO_DECL_ENTRY_Stream1Decl_bits 16 static inline uint32_t ATTRIBUTE_PURE SO_DECL_ENTRY_Stream1Decl_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SO_DECL_ENTRY_Stream1Decl_start 16 #define GFX12_SO_DECL_ENTRY_Stream1Decl_start 16 #define GFX11_SO_DECL_ENTRY_Stream1Decl_start 16 #define GFX9_SO_DECL_ENTRY_Stream1Decl_start 16 #define GFX8_SO_DECL_ENTRY_Stream1Decl_start 16 #define GFX75_SO_DECL_ENTRY_Stream1Decl_start 16 #define GFX7_SO_DECL_ENTRY_Stream1Decl_start 16 static inline uint32_t ATTRIBUTE_PURE SO_DECL_ENTRY_Stream1Decl_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SO_DECL_ENTRY::Stream 2 Decl */ #define GFX125_SO_DECL_ENTRY_Stream2Decl_bits 16 #define GFX12_SO_DECL_ENTRY_Stream2Decl_bits 16 #define GFX11_SO_DECL_ENTRY_Stream2Decl_bits 16 #define GFX9_SO_DECL_ENTRY_Stream2Decl_bits 16 #define GFX8_SO_DECL_ENTRY_Stream2Decl_bits 16 #define GFX75_SO_DECL_ENTRY_Stream2Decl_bits 16 #define GFX7_SO_DECL_ENTRY_Stream2Decl_bits 16 static inline uint32_t ATTRIBUTE_PURE SO_DECL_ENTRY_Stream2Decl_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SO_DECL_ENTRY_Stream2Decl_start 32 #define GFX12_SO_DECL_ENTRY_Stream2Decl_start 32 #define GFX11_SO_DECL_ENTRY_Stream2Decl_start 32 #define GFX9_SO_DECL_ENTRY_Stream2Decl_start 32 #define GFX8_SO_DECL_ENTRY_Stream2Decl_start 32 #define GFX75_SO_DECL_ENTRY_Stream2Decl_start 32 #define GFX7_SO_DECL_ENTRY_Stream2Decl_start 32 static inline uint32_t ATTRIBUTE_PURE SO_DECL_ENTRY_Stream2Decl_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SO_DECL_ENTRY::Stream 3 Decl */ #define GFX125_SO_DECL_ENTRY_Stream3Decl_bits 16 #define GFX12_SO_DECL_ENTRY_Stream3Decl_bits 16 #define GFX11_SO_DECL_ENTRY_Stream3Decl_bits 16 #define GFX9_SO_DECL_ENTRY_Stream3Decl_bits 16 #define GFX8_SO_DECL_ENTRY_Stream3Decl_bits 16 #define GFX75_SO_DECL_ENTRY_Stream3Decl_bits 16 #define GFX7_SO_DECL_ENTRY_Stream3Decl_bits 16 static inline uint32_t ATTRIBUTE_PURE SO_DECL_ENTRY_Stream3Decl_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SO_DECL_ENTRY_Stream3Decl_start 48 #define GFX12_SO_DECL_ENTRY_Stream3Decl_start 48 #define GFX11_SO_DECL_ENTRY_Stream3Decl_start 48 #define GFX9_SO_DECL_ENTRY_Stream3Decl_start 48 #define GFX8_SO_DECL_ENTRY_Stream3Decl_start 48 #define GFX75_SO_DECL_ENTRY_Stream3Decl_start 48 #define GFX7_SO_DECL_ENTRY_Stream3Decl_start 48 static inline uint32_t ATTRIBUTE_PURE SO_DECL_ENTRY_Stream3Decl_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 48; case 120: return 48; case 110: return 48; case 90: return 48; case 80: return 48; case 75: return 48; case 70: return 48; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SO_NUM_PRIMS_WRITTEN0 */ #define GFX125_SO_NUM_PRIMS_WRITTEN0_length 2 #define GFX12_SO_NUM_PRIMS_WRITTEN0_length 2 #define GFX11_SO_NUM_PRIMS_WRITTEN0_length 2 #define GFX9_SO_NUM_PRIMS_WRITTEN0_length 2 #define GFX8_SO_NUM_PRIMS_WRITTEN0_length 2 #define GFX75_SO_NUM_PRIMS_WRITTEN0_length 2 #define GFX7_SO_NUM_PRIMS_WRITTEN0_length 2 static inline uint32_t ATTRIBUTE_PURE SO_NUM_PRIMS_WRITTEN0_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SO_NUM_PRIMS_WRITTEN0::Num Prims Written Count */ #define GFX125_SO_NUM_PRIMS_WRITTEN0_NumPrimsWrittenCount_bits 64 #define GFX12_SO_NUM_PRIMS_WRITTEN0_NumPrimsWrittenCount_bits 64 #define GFX11_SO_NUM_PRIMS_WRITTEN0_NumPrimsWrittenCount_bits 64 #define GFX9_SO_NUM_PRIMS_WRITTEN0_NumPrimsWrittenCount_bits 64 #define GFX8_SO_NUM_PRIMS_WRITTEN0_NumPrimsWrittenCount_bits 64 #define GFX75_SO_NUM_PRIMS_WRITTEN0_NumPrimsWrittenCount_bits 64 #define GFX7_SO_NUM_PRIMS_WRITTEN0_NumPrimsWrittenCount_bits 64 static inline uint32_t ATTRIBUTE_PURE SO_NUM_PRIMS_WRITTEN0_NumPrimsWrittenCount_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 64; case 80: return 64; case 75: return 64; case 70: return 64; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SO_NUM_PRIMS_WRITTEN0_NumPrimsWrittenCount_start 0 #define GFX12_SO_NUM_PRIMS_WRITTEN0_NumPrimsWrittenCount_start 0 #define GFX11_SO_NUM_PRIMS_WRITTEN0_NumPrimsWrittenCount_start 0 #define GFX9_SO_NUM_PRIMS_WRITTEN0_NumPrimsWrittenCount_start 0 #define GFX8_SO_NUM_PRIMS_WRITTEN0_NumPrimsWrittenCount_start 0 #define GFX75_SO_NUM_PRIMS_WRITTEN0_NumPrimsWrittenCount_start 0 #define GFX7_SO_NUM_PRIMS_WRITTEN0_NumPrimsWrittenCount_start 0 static inline uint32_t ATTRIBUTE_PURE SO_NUM_PRIMS_WRITTEN0_NumPrimsWrittenCount_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SO_NUM_PRIMS_WRITTEN1 */ #define GFX125_SO_NUM_PRIMS_WRITTEN1_length 2 #define GFX12_SO_NUM_PRIMS_WRITTEN1_length 2 #define GFX11_SO_NUM_PRIMS_WRITTEN1_length 2 #define GFX9_SO_NUM_PRIMS_WRITTEN1_length 2 #define GFX8_SO_NUM_PRIMS_WRITTEN1_length 2 #define GFX75_SO_NUM_PRIMS_WRITTEN1_length 2 #define GFX7_SO_NUM_PRIMS_WRITTEN1_length 2 static inline uint32_t ATTRIBUTE_PURE SO_NUM_PRIMS_WRITTEN1_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SO_NUM_PRIMS_WRITTEN1::Num Prims Written Count */ #define GFX125_SO_NUM_PRIMS_WRITTEN1_NumPrimsWrittenCount_bits 64 #define GFX12_SO_NUM_PRIMS_WRITTEN1_NumPrimsWrittenCount_bits 64 #define GFX11_SO_NUM_PRIMS_WRITTEN1_NumPrimsWrittenCount_bits 64 #define GFX9_SO_NUM_PRIMS_WRITTEN1_NumPrimsWrittenCount_bits 64 #define GFX8_SO_NUM_PRIMS_WRITTEN1_NumPrimsWrittenCount_bits 64 #define GFX75_SO_NUM_PRIMS_WRITTEN1_NumPrimsWrittenCount_bits 64 #define GFX7_SO_NUM_PRIMS_WRITTEN1_NumPrimsWrittenCount_bits 64 static inline uint32_t ATTRIBUTE_PURE SO_NUM_PRIMS_WRITTEN1_NumPrimsWrittenCount_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 64; case 80: return 64; case 75: return 64; case 70: return 64; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SO_NUM_PRIMS_WRITTEN1_NumPrimsWrittenCount_start 0 #define GFX12_SO_NUM_PRIMS_WRITTEN1_NumPrimsWrittenCount_start 0 #define GFX11_SO_NUM_PRIMS_WRITTEN1_NumPrimsWrittenCount_start 0 #define GFX9_SO_NUM_PRIMS_WRITTEN1_NumPrimsWrittenCount_start 0 #define GFX8_SO_NUM_PRIMS_WRITTEN1_NumPrimsWrittenCount_start 0 #define GFX75_SO_NUM_PRIMS_WRITTEN1_NumPrimsWrittenCount_start 0 #define GFX7_SO_NUM_PRIMS_WRITTEN1_NumPrimsWrittenCount_start 0 static inline uint32_t ATTRIBUTE_PURE SO_NUM_PRIMS_WRITTEN1_NumPrimsWrittenCount_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SO_NUM_PRIMS_WRITTEN2 */ #define GFX125_SO_NUM_PRIMS_WRITTEN2_length 2 #define GFX12_SO_NUM_PRIMS_WRITTEN2_length 2 #define GFX11_SO_NUM_PRIMS_WRITTEN2_length 2 #define GFX9_SO_NUM_PRIMS_WRITTEN2_length 2 #define GFX8_SO_NUM_PRIMS_WRITTEN2_length 2 #define GFX75_SO_NUM_PRIMS_WRITTEN2_length 2 #define GFX7_SO_NUM_PRIMS_WRITTEN2_length 2 static inline uint32_t ATTRIBUTE_PURE SO_NUM_PRIMS_WRITTEN2_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SO_NUM_PRIMS_WRITTEN2::Num Prims Written Count */ #define GFX125_SO_NUM_PRIMS_WRITTEN2_NumPrimsWrittenCount_bits 64 #define GFX12_SO_NUM_PRIMS_WRITTEN2_NumPrimsWrittenCount_bits 64 #define GFX11_SO_NUM_PRIMS_WRITTEN2_NumPrimsWrittenCount_bits 64 #define GFX9_SO_NUM_PRIMS_WRITTEN2_NumPrimsWrittenCount_bits 64 #define GFX8_SO_NUM_PRIMS_WRITTEN2_NumPrimsWrittenCount_bits 64 #define GFX75_SO_NUM_PRIMS_WRITTEN2_NumPrimsWrittenCount_bits 64 #define GFX7_SO_NUM_PRIMS_WRITTEN2_NumPrimsWrittenCount_bits 64 static inline uint32_t ATTRIBUTE_PURE SO_NUM_PRIMS_WRITTEN2_NumPrimsWrittenCount_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 64; case 80: return 64; case 75: return 64; case 70: return 64; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SO_NUM_PRIMS_WRITTEN2_NumPrimsWrittenCount_start 0 #define GFX12_SO_NUM_PRIMS_WRITTEN2_NumPrimsWrittenCount_start 0 #define GFX11_SO_NUM_PRIMS_WRITTEN2_NumPrimsWrittenCount_start 0 #define GFX9_SO_NUM_PRIMS_WRITTEN2_NumPrimsWrittenCount_start 0 #define GFX8_SO_NUM_PRIMS_WRITTEN2_NumPrimsWrittenCount_start 0 #define GFX75_SO_NUM_PRIMS_WRITTEN2_NumPrimsWrittenCount_start 0 #define GFX7_SO_NUM_PRIMS_WRITTEN2_NumPrimsWrittenCount_start 0 static inline uint32_t ATTRIBUTE_PURE SO_NUM_PRIMS_WRITTEN2_NumPrimsWrittenCount_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SO_NUM_PRIMS_WRITTEN3 */ #define GFX125_SO_NUM_PRIMS_WRITTEN3_length 2 #define GFX12_SO_NUM_PRIMS_WRITTEN3_length 2 #define GFX11_SO_NUM_PRIMS_WRITTEN3_length 2 #define GFX9_SO_NUM_PRIMS_WRITTEN3_length 2 #define GFX8_SO_NUM_PRIMS_WRITTEN3_length 2 #define GFX75_SO_NUM_PRIMS_WRITTEN3_length 2 #define GFX7_SO_NUM_PRIMS_WRITTEN3_length 2 static inline uint32_t ATTRIBUTE_PURE SO_NUM_PRIMS_WRITTEN3_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SO_NUM_PRIMS_WRITTEN3::Num Prims Written Count */ #define GFX125_SO_NUM_PRIMS_WRITTEN3_NumPrimsWrittenCount_bits 64 #define GFX12_SO_NUM_PRIMS_WRITTEN3_NumPrimsWrittenCount_bits 64 #define GFX11_SO_NUM_PRIMS_WRITTEN3_NumPrimsWrittenCount_bits 64 #define GFX9_SO_NUM_PRIMS_WRITTEN3_NumPrimsWrittenCount_bits 64 #define GFX8_SO_NUM_PRIMS_WRITTEN3_NumPrimsWrittenCount_bits 64 #define GFX75_SO_NUM_PRIMS_WRITTEN3_NumPrimsWrittenCount_bits 64 #define GFX7_SO_NUM_PRIMS_WRITTEN3_NumPrimsWrittenCount_bits 64 static inline uint32_t ATTRIBUTE_PURE SO_NUM_PRIMS_WRITTEN3_NumPrimsWrittenCount_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 64; case 80: return 64; case 75: return 64; case 70: return 64; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SO_NUM_PRIMS_WRITTEN3_NumPrimsWrittenCount_start 0 #define GFX12_SO_NUM_PRIMS_WRITTEN3_NumPrimsWrittenCount_start 0 #define GFX11_SO_NUM_PRIMS_WRITTEN3_NumPrimsWrittenCount_start 0 #define GFX9_SO_NUM_PRIMS_WRITTEN3_NumPrimsWrittenCount_start 0 #define GFX8_SO_NUM_PRIMS_WRITTEN3_NumPrimsWrittenCount_start 0 #define GFX75_SO_NUM_PRIMS_WRITTEN3_NumPrimsWrittenCount_start 0 #define GFX7_SO_NUM_PRIMS_WRITTEN3_NumPrimsWrittenCount_start 0 static inline uint32_t ATTRIBUTE_PURE SO_NUM_PRIMS_WRITTEN3_NumPrimsWrittenCount_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SO_PRIM_STORAGE_NEEDED0 */ #define GFX125_SO_PRIM_STORAGE_NEEDED0_length 2 #define GFX12_SO_PRIM_STORAGE_NEEDED0_length 2 #define GFX11_SO_PRIM_STORAGE_NEEDED0_length 2 #define GFX9_SO_PRIM_STORAGE_NEEDED0_length 2 #define GFX8_SO_PRIM_STORAGE_NEEDED0_length 2 #define GFX75_SO_PRIM_STORAGE_NEEDED0_length 2 #define GFX7_SO_PRIM_STORAGE_NEEDED0_length 2 static inline uint32_t ATTRIBUTE_PURE SO_PRIM_STORAGE_NEEDED0_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SO_PRIM_STORAGE_NEEDED0::Prim Storage Needed Count */ #define GFX125_SO_PRIM_STORAGE_NEEDED0_PrimStorageNeededCount_bits 64 #define GFX12_SO_PRIM_STORAGE_NEEDED0_PrimStorageNeededCount_bits 64 #define GFX11_SO_PRIM_STORAGE_NEEDED0_PrimStorageNeededCount_bits 64 #define GFX9_SO_PRIM_STORAGE_NEEDED0_PrimStorageNeededCount_bits 64 #define GFX8_SO_PRIM_STORAGE_NEEDED0_PrimStorageNeededCount_bits 64 #define GFX75_SO_PRIM_STORAGE_NEEDED0_PrimStorageNeededCount_bits 64 #define GFX7_SO_PRIM_STORAGE_NEEDED0_PrimStorageNeededCount_bits 64 static inline uint32_t ATTRIBUTE_PURE SO_PRIM_STORAGE_NEEDED0_PrimStorageNeededCount_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 64; case 80: return 64; case 75: return 64; case 70: return 64; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SO_PRIM_STORAGE_NEEDED0_PrimStorageNeededCount_start 0 #define GFX12_SO_PRIM_STORAGE_NEEDED0_PrimStorageNeededCount_start 0 #define GFX11_SO_PRIM_STORAGE_NEEDED0_PrimStorageNeededCount_start 0 #define GFX9_SO_PRIM_STORAGE_NEEDED0_PrimStorageNeededCount_start 0 #define GFX8_SO_PRIM_STORAGE_NEEDED0_PrimStorageNeededCount_start 0 #define GFX75_SO_PRIM_STORAGE_NEEDED0_PrimStorageNeededCount_start 0 #define GFX7_SO_PRIM_STORAGE_NEEDED0_PrimStorageNeededCount_start 0 static inline uint32_t ATTRIBUTE_PURE SO_PRIM_STORAGE_NEEDED0_PrimStorageNeededCount_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SO_PRIM_STORAGE_NEEDED1 */ #define GFX125_SO_PRIM_STORAGE_NEEDED1_length 2 #define GFX12_SO_PRIM_STORAGE_NEEDED1_length 2 #define GFX11_SO_PRIM_STORAGE_NEEDED1_length 2 #define GFX9_SO_PRIM_STORAGE_NEEDED1_length 2 #define GFX8_SO_PRIM_STORAGE_NEEDED1_length 2 #define GFX75_SO_PRIM_STORAGE_NEEDED1_length 2 #define GFX7_SO_PRIM_STORAGE_NEEDED1_length 2 static inline uint32_t ATTRIBUTE_PURE SO_PRIM_STORAGE_NEEDED1_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SO_PRIM_STORAGE_NEEDED1::Prim Storage Needed Count */ #define GFX125_SO_PRIM_STORAGE_NEEDED1_PrimStorageNeededCount_bits 64 #define GFX12_SO_PRIM_STORAGE_NEEDED1_PrimStorageNeededCount_bits 64 #define GFX11_SO_PRIM_STORAGE_NEEDED1_PrimStorageNeededCount_bits 64 #define GFX9_SO_PRIM_STORAGE_NEEDED1_PrimStorageNeededCount_bits 64 #define GFX8_SO_PRIM_STORAGE_NEEDED1_PrimStorageNeededCount_bits 64 #define GFX75_SO_PRIM_STORAGE_NEEDED1_PrimStorageNeededCount_bits 64 #define GFX7_SO_PRIM_STORAGE_NEEDED1_PrimStorageNeededCount_bits 64 static inline uint32_t ATTRIBUTE_PURE SO_PRIM_STORAGE_NEEDED1_PrimStorageNeededCount_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 64; case 80: return 64; case 75: return 64; case 70: return 64; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SO_PRIM_STORAGE_NEEDED1_PrimStorageNeededCount_start 0 #define GFX12_SO_PRIM_STORAGE_NEEDED1_PrimStorageNeededCount_start 0 #define GFX11_SO_PRIM_STORAGE_NEEDED1_PrimStorageNeededCount_start 0 #define GFX9_SO_PRIM_STORAGE_NEEDED1_PrimStorageNeededCount_start 0 #define GFX8_SO_PRIM_STORAGE_NEEDED1_PrimStorageNeededCount_start 0 #define GFX75_SO_PRIM_STORAGE_NEEDED1_PrimStorageNeededCount_start 0 #define GFX7_SO_PRIM_STORAGE_NEEDED1_PrimStorageNeededCount_start 0 static inline uint32_t ATTRIBUTE_PURE SO_PRIM_STORAGE_NEEDED1_PrimStorageNeededCount_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SO_PRIM_STORAGE_NEEDED2 */ #define GFX125_SO_PRIM_STORAGE_NEEDED2_length 2 #define GFX12_SO_PRIM_STORAGE_NEEDED2_length 2 #define GFX11_SO_PRIM_STORAGE_NEEDED2_length 2 #define GFX9_SO_PRIM_STORAGE_NEEDED2_length 2 #define GFX8_SO_PRIM_STORAGE_NEEDED2_length 2 #define GFX75_SO_PRIM_STORAGE_NEEDED2_length 2 #define GFX7_SO_PRIM_STORAGE_NEEDED2_length 2 static inline uint32_t ATTRIBUTE_PURE SO_PRIM_STORAGE_NEEDED2_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SO_PRIM_STORAGE_NEEDED2::Prim Storage Needed Count */ #define GFX125_SO_PRIM_STORAGE_NEEDED2_PrimStorageNeededCount_bits 64 #define GFX12_SO_PRIM_STORAGE_NEEDED2_PrimStorageNeededCount_bits 64 #define GFX11_SO_PRIM_STORAGE_NEEDED2_PrimStorageNeededCount_bits 64 #define GFX9_SO_PRIM_STORAGE_NEEDED2_PrimStorageNeededCount_bits 64 #define GFX8_SO_PRIM_STORAGE_NEEDED2_PrimStorageNeededCount_bits 64 #define GFX75_SO_PRIM_STORAGE_NEEDED2_PrimStorageNeededCount_bits 64 #define GFX7_SO_PRIM_STORAGE_NEEDED2_PrimStorageNeededCount_bits 64 static inline uint32_t ATTRIBUTE_PURE SO_PRIM_STORAGE_NEEDED2_PrimStorageNeededCount_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 64; case 80: return 64; case 75: return 64; case 70: return 64; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SO_PRIM_STORAGE_NEEDED2_PrimStorageNeededCount_start 0 #define GFX12_SO_PRIM_STORAGE_NEEDED2_PrimStorageNeededCount_start 0 #define GFX11_SO_PRIM_STORAGE_NEEDED2_PrimStorageNeededCount_start 0 #define GFX9_SO_PRIM_STORAGE_NEEDED2_PrimStorageNeededCount_start 0 #define GFX8_SO_PRIM_STORAGE_NEEDED2_PrimStorageNeededCount_start 0 #define GFX75_SO_PRIM_STORAGE_NEEDED2_PrimStorageNeededCount_start 0 #define GFX7_SO_PRIM_STORAGE_NEEDED2_PrimStorageNeededCount_start 0 static inline uint32_t ATTRIBUTE_PURE SO_PRIM_STORAGE_NEEDED2_PrimStorageNeededCount_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SO_PRIM_STORAGE_NEEDED3 */ #define GFX125_SO_PRIM_STORAGE_NEEDED3_length 2 #define GFX12_SO_PRIM_STORAGE_NEEDED3_length 2 #define GFX11_SO_PRIM_STORAGE_NEEDED3_length 2 #define GFX9_SO_PRIM_STORAGE_NEEDED3_length 2 #define GFX8_SO_PRIM_STORAGE_NEEDED3_length 2 #define GFX75_SO_PRIM_STORAGE_NEEDED3_length 2 #define GFX7_SO_PRIM_STORAGE_NEEDED3_length 2 static inline uint32_t ATTRIBUTE_PURE SO_PRIM_STORAGE_NEEDED3_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SO_PRIM_STORAGE_NEEDED3::Prim Storage Needed Count */ #define GFX125_SO_PRIM_STORAGE_NEEDED3_PrimStorageNeededCount_bits 64 #define GFX12_SO_PRIM_STORAGE_NEEDED3_PrimStorageNeededCount_bits 64 #define GFX11_SO_PRIM_STORAGE_NEEDED3_PrimStorageNeededCount_bits 64 #define GFX9_SO_PRIM_STORAGE_NEEDED3_PrimStorageNeededCount_bits 64 #define GFX8_SO_PRIM_STORAGE_NEEDED3_PrimStorageNeededCount_bits 64 #define GFX75_SO_PRIM_STORAGE_NEEDED3_PrimStorageNeededCount_bits 64 #define GFX7_SO_PRIM_STORAGE_NEEDED3_PrimStorageNeededCount_bits 64 static inline uint32_t ATTRIBUTE_PURE SO_PRIM_STORAGE_NEEDED3_PrimStorageNeededCount_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 64; case 80: return 64; case 75: return 64; case 70: return 64; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SO_PRIM_STORAGE_NEEDED3_PrimStorageNeededCount_start 0 #define GFX12_SO_PRIM_STORAGE_NEEDED3_PrimStorageNeededCount_start 0 #define GFX11_SO_PRIM_STORAGE_NEEDED3_PrimStorageNeededCount_start 0 #define GFX9_SO_PRIM_STORAGE_NEEDED3_PrimStorageNeededCount_start 0 #define GFX8_SO_PRIM_STORAGE_NEEDED3_PrimStorageNeededCount_start 0 #define GFX75_SO_PRIM_STORAGE_NEEDED3_PrimStorageNeededCount_start 0 #define GFX7_SO_PRIM_STORAGE_NEEDED3_PrimStorageNeededCount_start 0 static inline uint32_t ATTRIBUTE_PURE SO_PRIM_STORAGE_NEEDED3_PrimStorageNeededCount_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SO_WRITE_OFFSET0 */ #define GFX125_SO_WRITE_OFFSET0_length 1 #define GFX12_SO_WRITE_OFFSET0_length 1 #define GFX11_SO_WRITE_OFFSET0_length 1 #define GFX9_SO_WRITE_OFFSET0_length 1 #define GFX8_SO_WRITE_OFFSET0_length 1 #define GFX75_SO_WRITE_OFFSET0_length 1 #define GFX7_SO_WRITE_OFFSET0_length 1 static inline uint32_t ATTRIBUTE_PURE SO_WRITE_OFFSET0_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SO_WRITE_OFFSET0::Write Offset */ #define GFX125_SO_WRITE_OFFSET0_WriteOffset_bits 30 #define GFX12_SO_WRITE_OFFSET0_WriteOffset_bits 30 #define GFX11_SO_WRITE_OFFSET0_WriteOffset_bits 30 #define GFX9_SO_WRITE_OFFSET0_WriteOffset_bits 30 #define GFX8_SO_WRITE_OFFSET0_WriteOffset_bits 30 #define GFX75_SO_WRITE_OFFSET0_WriteOffset_bits 30 #define GFX7_SO_WRITE_OFFSET0_WriteOffset_bits 30 static inline uint32_t ATTRIBUTE_PURE SO_WRITE_OFFSET0_WriteOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 30; case 120: return 30; case 110: return 30; case 90: return 30; case 80: return 30; case 75: return 30; case 70: return 30; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SO_WRITE_OFFSET0_WriteOffset_start 2 #define GFX12_SO_WRITE_OFFSET0_WriteOffset_start 2 #define GFX11_SO_WRITE_OFFSET0_WriteOffset_start 2 #define GFX9_SO_WRITE_OFFSET0_WriteOffset_start 2 #define GFX8_SO_WRITE_OFFSET0_WriteOffset_start 2 #define GFX75_SO_WRITE_OFFSET0_WriteOffset_start 2 #define GFX7_SO_WRITE_OFFSET0_WriteOffset_start 2 static inline uint32_t ATTRIBUTE_PURE SO_WRITE_OFFSET0_WriteOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SO_WRITE_OFFSET1 */ #define GFX125_SO_WRITE_OFFSET1_length 1 #define GFX12_SO_WRITE_OFFSET1_length 1 #define GFX11_SO_WRITE_OFFSET1_length 1 #define GFX9_SO_WRITE_OFFSET1_length 1 #define GFX8_SO_WRITE_OFFSET1_length 1 #define GFX75_SO_WRITE_OFFSET1_length 1 #define GFX7_SO_WRITE_OFFSET1_length 1 static inline uint32_t ATTRIBUTE_PURE SO_WRITE_OFFSET1_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SO_WRITE_OFFSET1::Write Offset */ #define GFX125_SO_WRITE_OFFSET1_WriteOffset_bits 30 #define GFX12_SO_WRITE_OFFSET1_WriteOffset_bits 30 #define GFX11_SO_WRITE_OFFSET1_WriteOffset_bits 30 #define GFX9_SO_WRITE_OFFSET1_WriteOffset_bits 30 #define GFX8_SO_WRITE_OFFSET1_WriteOffset_bits 30 #define GFX75_SO_WRITE_OFFSET1_WriteOffset_bits 30 #define GFX7_SO_WRITE_OFFSET1_WriteOffset_bits 30 static inline uint32_t ATTRIBUTE_PURE SO_WRITE_OFFSET1_WriteOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 30; case 120: return 30; case 110: return 30; case 90: return 30; case 80: return 30; case 75: return 30; case 70: return 30; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SO_WRITE_OFFSET1_WriteOffset_start 2 #define GFX12_SO_WRITE_OFFSET1_WriteOffset_start 2 #define GFX11_SO_WRITE_OFFSET1_WriteOffset_start 2 #define GFX9_SO_WRITE_OFFSET1_WriteOffset_start 2 #define GFX8_SO_WRITE_OFFSET1_WriteOffset_start 2 #define GFX75_SO_WRITE_OFFSET1_WriteOffset_start 2 #define GFX7_SO_WRITE_OFFSET1_WriteOffset_start 2 static inline uint32_t ATTRIBUTE_PURE SO_WRITE_OFFSET1_WriteOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SO_WRITE_OFFSET2 */ #define GFX125_SO_WRITE_OFFSET2_length 1 #define GFX12_SO_WRITE_OFFSET2_length 1 #define GFX11_SO_WRITE_OFFSET2_length 1 #define GFX9_SO_WRITE_OFFSET2_length 1 #define GFX8_SO_WRITE_OFFSET2_length 1 #define GFX75_SO_WRITE_OFFSET2_length 1 #define GFX7_SO_WRITE_OFFSET2_length 1 static inline uint32_t ATTRIBUTE_PURE SO_WRITE_OFFSET2_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SO_WRITE_OFFSET2::Write Offset */ #define GFX125_SO_WRITE_OFFSET2_WriteOffset_bits 30 #define GFX12_SO_WRITE_OFFSET2_WriteOffset_bits 30 #define GFX11_SO_WRITE_OFFSET2_WriteOffset_bits 30 #define GFX9_SO_WRITE_OFFSET2_WriteOffset_bits 30 #define GFX8_SO_WRITE_OFFSET2_WriteOffset_bits 30 #define GFX75_SO_WRITE_OFFSET2_WriteOffset_bits 30 #define GFX7_SO_WRITE_OFFSET2_WriteOffset_bits 30 static inline uint32_t ATTRIBUTE_PURE SO_WRITE_OFFSET2_WriteOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 30; case 120: return 30; case 110: return 30; case 90: return 30; case 80: return 30; case 75: return 30; case 70: return 30; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SO_WRITE_OFFSET2_WriteOffset_start 2 #define GFX12_SO_WRITE_OFFSET2_WriteOffset_start 2 #define GFX11_SO_WRITE_OFFSET2_WriteOffset_start 2 #define GFX9_SO_WRITE_OFFSET2_WriteOffset_start 2 #define GFX8_SO_WRITE_OFFSET2_WriteOffset_start 2 #define GFX75_SO_WRITE_OFFSET2_WriteOffset_start 2 #define GFX7_SO_WRITE_OFFSET2_WriteOffset_start 2 static inline uint32_t ATTRIBUTE_PURE SO_WRITE_OFFSET2_WriteOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SO_WRITE_OFFSET3 */ #define GFX125_SO_WRITE_OFFSET3_length 1 #define GFX12_SO_WRITE_OFFSET3_length 1 #define GFX11_SO_WRITE_OFFSET3_length 1 #define GFX9_SO_WRITE_OFFSET3_length 1 #define GFX8_SO_WRITE_OFFSET3_length 1 #define GFX75_SO_WRITE_OFFSET3_length 1 #define GFX7_SO_WRITE_OFFSET3_length 1 static inline uint32_t ATTRIBUTE_PURE SO_WRITE_OFFSET3_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SO_WRITE_OFFSET3::Write Offset */ #define GFX125_SO_WRITE_OFFSET3_WriteOffset_bits 30 #define GFX12_SO_WRITE_OFFSET3_WriteOffset_bits 30 #define GFX11_SO_WRITE_OFFSET3_WriteOffset_bits 30 #define GFX9_SO_WRITE_OFFSET3_WriteOffset_bits 30 #define GFX8_SO_WRITE_OFFSET3_WriteOffset_bits 30 #define GFX75_SO_WRITE_OFFSET3_WriteOffset_bits 30 #define GFX7_SO_WRITE_OFFSET3_WriteOffset_bits 30 static inline uint32_t ATTRIBUTE_PURE SO_WRITE_OFFSET3_WriteOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 30; case 120: return 30; case 110: return 30; case 90: return 30; case 80: return 30; case 75: return 30; case 70: return 30; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_SO_WRITE_OFFSET3_WriteOffset_start 2 #define GFX12_SO_WRITE_OFFSET3_WriteOffset_start 2 #define GFX11_SO_WRITE_OFFSET3_WriteOffset_start 2 #define GFX9_SO_WRITE_OFFSET3_WriteOffset_start 2 #define GFX8_SO_WRITE_OFFSET3_WriteOffset_start 2 #define GFX75_SO_WRITE_OFFSET3_WriteOffset_start 2 #define GFX7_SO_WRITE_OFFSET3_WriteOffset_start 2 static inline uint32_t ATTRIBUTE_PURE SO_WRITE_OFFSET3_WriteOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* STATE_BASE_ADDRESS */ #define GFX125_STATE_BASE_ADDRESS_length 22 #define GFX12_STATE_BASE_ADDRESS_length 22 #define GFX11_STATE_BASE_ADDRESS_length 22 #define GFX9_STATE_BASE_ADDRESS_length 19 #define GFX8_STATE_BASE_ADDRESS_length 16 #define GFX75_STATE_BASE_ADDRESS_length 10 #define GFX7_STATE_BASE_ADDRESS_length 10 #define GFX6_STATE_BASE_ADDRESS_length 10 #define GFX5_STATE_BASE_ADDRESS_length 8 #define GFX45_STATE_BASE_ADDRESS_length 6 #define GFX4_STATE_BASE_ADDRESS_length 6 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 22; case 120: return 22; case 110: return 22; case 90: return 19; case 80: return 16; case 75: return 10; case 70: return 10; case 60: return 10; case 50: return 8; case 45: return 6; case 40: return 6; default: unreachable("Invalid hardware generation"); } } /* STATE_BASE_ADDRESS::3D Command Opcode */ #define GFX125_STATE_BASE_ADDRESS_3DCommandOpcode_bits 3 #define GFX12_STATE_BASE_ADDRESS_3DCommandOpcode_bits 3 #define GFX11_STATE_BASE_ADDRESS_3DCommandOpcode_bits 3 #define GFX9_STATE_BASE_ADDRESS_3DCommandOpcode_bits 3 #define GFX8_STATE_BASE_ADDRESS_3DCommandOpcode_bits 3 #define GFX75_STATE_BASE_ADDRESS_3DCommandOpcode_bits 3 #define GFX7_STATE_BASE_ADDRESS_3DCommandOpcode_bits 3 #define GFX6_STATE_BASE_ADDRESS_3DCommandOpcode_bits 3 #define GFX5_STATE_BASE_ADDRESS_3DCommandOpcode_bits 3 #define GFX45_STATE_BASE_ADDRESS_3DCommandOpcode_bits 3 #define GFX4_STATE_BASE_ADDRESS_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX125_STATE_BASE_ADDRESS_3DCommandOpcode_start 24 #define GFX12_STATE_BASE_ADDRESS_3DCommandOpcode_start 24 #define GFX11_STATE_BASE_ADDRESS_3DCommandOpcode_start 24 #define GFX9_STATE_BASE_ADDRESS_3DCommandOpcode_start 24 #define GFX8_STATE_BASE_ADDRESS_3DCommandOpcode_start 24 #define GFX75_STATE_BASE_ADDRESS_3DCommandOpcode_start 24 #define GFX7_STATE_BASE_ADDRESS_3DCommandOpcode_start 24 #define GFX6_STATE_BASE_ADDRESS_3DCommandOpcode_start 24 #define GFX5_STATE_BASE_ADDRESS_3DCommandOpcode_start 24 #define GFX45_STATE_BASE_ADDRESS_3DCommandOpcode_start 24 #define GFX4_STATE_BASE_ADDRESS_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 24; case 50: return 24; case 45: return 24; case 40: return 24; default: unreachable("Invalid hardware generation"); } } /* STATE_BASE_ADDRESS::3D Command Sub Opcode */ #define GFX125_STATE_BASE_ADDRESS_3DCommandSubOpcode_bits 8 #define GFX12_STATE_BASE_ADDRESS_3DCommandSubOpcode_bits 8 #define GFX11_STATE_BASE_ADDRESS_3DCommandSubOpcode_bits 8 #define GFX9_STATE_BASE_ADDRESS_3DCommandSubOpcode_bits 8 #define GFX8_STATE_BASE_ADDRESS_3DCommandSubOpcode_bits 8 #define GFX75_STATE_BASE_ADDRESS_3DCommandSubOpcode_bits 8 #define GFX7_STATE_BASE_ADDRESS_3DCommandSubOpcode_bits 8 #define GFX6_STATE_BASE_ADDRESS_3DCommandSubOpcode_bits 8 #define GFX5_STATE_BASE_ADDRESS_3DCommandSubOpcode_bits 8 #define GFX45_STATE_BASE_ADDRESS_3DCommandSubOpcode_bits 8 #define GFX4_STATE_BASE_ADDRESS_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 8; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } #define GFX125_STATE_BASE_ADDRESS_3DCommandSubOpcode_start 16 #define GFX12_STATE_BASE_ADDRESS_3DCommandSubOpcode_start 16 #define GFX11_STATE_BASE_ADDRESS_3DCommandSubOpcode_start 16 #define GFX9_STATE_BASE_ADDRESS_3DCommandSubOpcode_start 16 #define GFX8_STATE_BASE_ADDRESS_3DCommandSubOpcode_start 16 #define GFX75_STATE_BASE_ADDRESS_3DCommandSubOpcode_start 16 #define GFX7_STATE_BASE_ADDRESS_3DCommandSubOpcode_start 16 #define GFX6_STATE_BASE_ADDRESS_3DCommandSubOpcode_start 16 #define GFX5_STATE_BASE_ADDRESS_3DCommandSubOpcode_start 16 #define GFX45_STATE_BASE_ADDRESS_3DCommandSubOpcode_start 16 #define GFX4_STATE_BASE_ADDRESS_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 16; case 50: return 16; case 45: return 16; case 40: return 16; default: unreachable("Invalid hardware generation"); } } /* STATE_BASE_ADDRESS::Bindless Sampler State Base Address */ #define GFX125_STATE_BASE_ADDRESS_BindlessSamplerStateBaseAddress_bits 52 #define GFX12_STATE_BASE_ADDRESS_BindlessSamplerStateBaseAddress_bits 52 #define GFX11_STATE_BASE_ADDRESS_BindlessSamplerStateBaseAddress_bits 52 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_BindlessSamplerStateBaseAddress_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 52; case 120: return 52; case 110: return 52; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_STATE_BASE_ADDRESS_BindlessSamplerStateBaseAddress_start 620 #define GFX12_STATE_BASE_ADDRESS_BindlessSamplerStateBaseAddress_start 620 #define GFX11_STATE_BASE_ADDRESS_BindlessSamplerStateBaseAddress_start 620 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_BindlessSamplerStateBaseAddress_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 620; case 120: return 620; case 110: return 620; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* STATE_BASE_ADDRESS::Bindless Sampler State Base Address Modify Enable */ #define GFX125_STATE_BASE_ADDRESS_BindlessSamplerStateBaseAddressModifyEnable_bits 1 #define GFX12_STATE_BASE_ADDRESS_BindlessSamplerStateBaseAddressModifyEnable_bits 1 #define GFX11_STATE_BASE_ADDRESS_BindlessSamplerStateBaseAddressModifyEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_BindlessSamplerStateBaseAddressModifyEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_STATE_BASE_ADDRESS_BindlessSamplerStateBaseAddressModifyEnable_start 608 #define GFX12_STATE_BASE_ADDRESS_BindlessSamplerStateBaseAddressModifyEnable_start 608 #define GFX11_STATE_BASE_ADDRESS_BindlessSamplerStateBaseAddressModifyEnable_start 608 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_BindlessSamplerStateBaseAddressModifyEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 608; case 120: return 608; case 110: return 608; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* STATE_BASE_ADDRESS::Bindless Sampler State Buffer Size */ #define GFX125_STATE_BASE_ADDRESS_BindlessSamplerStateBufferSize_bits 20 #define GFX12_STATE_BASE_ADDRESS_BindlessSamplerStateBufferSize_bits 20 #define GFX11_STATE_BASE_ADDRESS_BindlessSamplerStateBufferSize_bits 20 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_BindlessSamplerStateBufferSize_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 20; case 120: return 20; case 110: return 20; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_STATE_BASE_ADDRESS_BindlessSamplerStateBufferSize_start 684 #define GFX12_STATE_BASE_ADDRESS_BindlessSamplerStateBufferSize_start 684 #define GFX11_STATE_BASE_ADDRESS_BindlessSamplerStateBufferSize_start 684 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_BindlessSamplerStateBufferSize_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 684; case 120: return 684; case 110: return 684; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* STATE_BASE_ADDRESS::Bindless Sampler State MOCS */ #define GFX125_STATE_BASE_ADDRESS_BindlessSamplerStateMOCS_bits 7 #define GFX12_STATE_BASE_ADDRESS_BindlessSamplerStateMOCS_bits 7 #define GFX11_STATE_BASE_ADDRESS_BindlessSamplerStateMOCS_bits 7 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_BindlessSamplerStateMOCS_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 7; case 120: return 7; case 110: return 7; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_STATE_BASE_ADDRESS_BindlessSamplerStateMOCS_start 612 #define GFX12_STATE_BASE_ADDRESS_BindlessSamplerStateMOCS_start 612 #define GFX11_STATE_BASE_ADDRESS_BindlessSamplerStateMOCS_start 612 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_BindlessSamplerStateMOCS_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 612; case 120: return 612; case 110: return 612; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* STATE_BASE_ADDRESS::Bindless Surface State Base Address */ #define GFX125_STATE_BASE_ADDRESS_BindlessSurfaceStateBaseAddress_bits 52 #define GFX12_STATE_BASE_ADDRESS_BindlessSurfaceStateBaseAddress_bits 52 #define GFX11_STATE_BASE_ADDRESS_BindlessSurfaceStateBaseAddress_bits 52 #define GFX9_STATE_BASE_ADDRESS_BindlessSurfaceStateBaseAddress_bits 52 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_BindlessSurfaceStateBaseAddress_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 52; case 120: return 52; case 110: return 52; case 90: return 52; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_STATE_BASE_ADDRESS_BindlessSurfaceStateBaseAddress_start 524 #define GFX12_STATE_BASE_ADDRESS_BindlessSurfaceStateBaseAddress_start 524 #define GFX11_STATE_BASE_ADDRESS_BindlessSurfaceStateBaseAddress_start 524 #define GFX9_STATE_BASE_ADDRESS_BindlessSurfaceStateBaseAddress_start 524 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_BindlessSurfaceStateBaseAddress_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 524; case 120: return 524; case 110: return 524; case 90: return 524; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* STATE_BASE_ADDRESS::Bindless Surface State Base Address Modify Enable */ #define GFX125_STATE_BASE_ADDRESS_BindlessSurfaceStateBaseAddressModifyEnable_bits 1 #define GFX12_STATE_BASE_ADDRESS_BindlessSurfaceStateBaseAddressModifyEnable_bits 1 #define GFX11_STATE_BASE_ADDRESS_BindlessSurfaceStateBaseAddressModifyEnable_bits 1 #define GFX9_STATE_BASE_ADDRESS_BindlessSurfaceStateBaseAddressModifyEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_BindlessSurfaceStateBaseAddressModifyEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_STATE_BASE_ADDRESS_BindlessSurfaceStateBaseAddressModifyEnable_start 512 #define GFX12_STATE_BASE_ADDRESS_BindlessSurfaceStateBaseAddressModifyEnable_start 512 #define GFX11_STATE_BASE_ADDRESS_BindlessSurfaceStateBaseAddressModifyEnable_start 512 #define GFX9_STATE_BASE_ADDRESS_BindlessSurfaceStateBaseAddressModifyEnable_start 512 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_BindlessSurfaceStateBaseAddressModifyEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 512; case 120: return 512; case 110: return 512; case 90: return 512; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* STATE_BASE_ADDRESS::Bindless Surface State MOCS */ #define GFX125_STATE_BASE_ADDRESS_BindlessSurfaceStateMOCS_bits 7 #define GFX12_STATE_BASE_ADDRESS_BindlessSurfaceStateMOCS_bits 7 #define GFX11_STATE_BASE_ADDRESS_BindlessSurfaceStateMOCS_bits 7 #define GFX9_STATE_BASE_ADDRESS_BindlessSurfaceStateMOCS_bits 7 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_BindlessSurfaceStateMOCS_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 7; case 120: return 7; case 110: return 7; case 90: return 7; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_STATE_BASE_ADDRESS_BindlessSurfaceStateMOCS_start 516 #define GFX12_STATE_BASE_ADDRESS_BindlessSurfaceStateMOCS_start 516 #define GFX11_STATE_BASE_ADDRESS_BindlessSurfaceStateMOCS_start 516 #define GFX9_STATE_BASE_ADDRESS_BindlessSurfaceStateMOCS_start 516 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_BindlessSurfaceStateMOCS_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 516; case 120: return 516; case 110: return 516; case 90: return 516; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* STATE_BASE_ADDRESS::Bindless Surface State Size */ #define GFX125_STATE_BASE_ADDRESS_BindlessSurfaceStateSize_bits 20 #define GFX12_STATE_BASE_ADDRESS_BindlessSurfaceStateSize_bits 20 #define GFX11_STATE_BASE_ADDRESS_BindlessSurfaceStateSize_bits 20 #define GFX9_STATE_BASE_ADDRESS_BindlessSurfaceStateSize_bits 20 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_BindlessSurfaceStateSize_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 20; case 120: return 20; case 110: return 20; case 90: return 20; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_STATE_BASE_ADDRESS_BindlessSurfaceStateSize_start 588 #define GFX12_STATE_BASE_ADDRESS_BindlessSurfaceStateSize_start 588 #define GFX11_STATE_BASE_ADDRESS_BindlessSurfaceStateSize_start 588 #define GFX9_STATE_BASE_ADDRESS_BindlessSurfaceStateSize_start 588 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_BindlessSurfaceStateSize_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 588; case 120: return 588; case 110: return 588; case 90: return 588; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* STATE_BASE_ADDRESS::Command SubType */ #define GFX125_STATE_BASE_ADDRESS_CommandSubType_bits 2 #define GFX12_STATE_BASE_ADDRESS_CommandSubType_bits 2 #define GFX11_STATE_BASE_ADDRESS_CommandSubType_bits 2 #define GFX9_STATE_BASE_ADDRESS_CommandSubType_bits 2 #define GFX8_STATE_BASE_ADDRESS_CommandSubType_bits 2 #define GFX75_STATE_BASE_ADDRESS_CommandSubType_bits 2 #define GFX7_STATE_BASE_ADDRESS_CommandSubType_bits 2 #define GFX6_STATE_BASE_ADDRESS_CommandSubType_bits 2 #define GFX5_STATE_BASE_ADDRESS_CommandSubType_bits 2 #define GFX45_STATE_BASE_ADDRESS_CommandSubType_bits 2 #define GFX4_STATE_BASE_ADDRESS_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 2; case 45: return 2; case 40: return 2; default: unreachable("Invalid hardware generation"); } } #define GFX125_STATE_BASE_ADDRESS_CommandSubType_start 27 #define GFX12_STATE_BASE_ADDRESS_CommandSubType_start 27 #define GFX11_STATE_BASE_ADDRESS_CommandSubType_start 27 #define GFX9_STATE_BASE_ADDRESS_CommandSubType_start 27 #define GFX8_STATE_BASE_ADDRESS_CommandSubType_start 27 #define GFX75_STATE_BASE_ADDRESS_CommandSubType_start 27 #define GFX7_STATE_BASE_ADDRESS_CommandSubType_start 27 #define GFX6_STATE_BASE_ADDRESS_CommandSubType_start 27 #define GFX5_STATE_BASE_ADDRESS_CommandSubType_start 27 #define GFX45_STATE_BASE_ADDRESS_CommandSubType_start 27 #define GFX4_STATE_BASE_ADDRESS_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 27; case 50: return 27; case 45: return 27; case 40: return 27; default: unreachable("Invalid hardware generation"); } } /* STATE_BASE_ADDRESS::Command Type */ #define GFX125_STATE_BASE_ADDRESS_CommandType_bits 3 #define GFX12_STATE_BASE_ADDRESS_CommandType_bits 3 #define GFX11_STATE_BASE_ADDRESS_CommandType_bits 3 #define GFX9_STATE_BASE_ADDRESS_CommandType_bits 3 #define GFX8_STATE_BASE_ADDRESS_CommandType_bits 3 #define GFX75_STATE_BASE_ADDRESS_CommandType_bits 3 #define GFX7_STATE_BASE_ADDRESS_CommandType_bits 3 #define GFX6_STATE_BASE_ADDRESS_CommandType_bits 3 #define GFX5_STATE_BASE_ADDRESS_CommandType_bits 3 #define GFX45_STATE_BASE_ADDRESS_CommandType_bits 3 #define GFX4_STATE_BASE_ADDRESS_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX125_STATE_BASE_ADDRESS_CommandType_start 29 #define GFX12_STATE_BASE_ADDRESS_CommandType_start 29 #define GFX11_STATE_BASE_ADDRESS_CommandType_start 29 #define GFX9_STATE_BASE_ADDRESS_CommandType_start 29 #define GFX8_STATE_BASE_ADDRESS_CommandType_start 29 #define GFX75_STATE_BASE_ADDRESS_CommandType_start 29 #define GFX7_STATE_BASE_ADDRESS_CommandType_start 29 #define GFX6_STATE_BASE_ADDRESS_CommandType_start 29 #define GFX5_STATE_BASE_ADDRESS_CommandType_start 29 #define GFX45_STATE_BASE_ADDRESS_CommandType_start 29 #define GFX4_STATE_BASE_ADDRESS_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 29; case 50: return 29; case 45: return 29; case 40: return 29; default: unreachable("Invalid hardware generation"); } } /* STATE_BASE_ADDRESS::DWord Length */ #define GFX125_STATE_BASE_ADDRESS_DWordLength_bits 8 #define GFX12_STATE_BASE_ADDRESS_DWordLength_bits 8 #define GFX11_STATE_BASE_ADDRESS_DWordLength_bits 8 #define GFX9_STATE_BASE_ADDRESS_DWordLength_bits 8 #define GFX8_STATE_BASE_ADDRESS_DWordLength_bits 8 #define GFX75_STATE_BASE_ADDRESS_DWordLength_bits 8 #define GFX7_STATE_BASE_ADDRESS_DWordLength_bits 8 #define GFX6_STATE_BASE_ADDRESS_DWordLength_bits 8 #define GFX5_STATE_BASE_ADDRESS_DWordLength_bits 8 #define GFX45_STATE_BASE_ADDRESS_DWordLength_bits 8 #define GFX4_STATE_BASE_ADDRESS_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 8; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } #define GFX125_STATE_BASE_ADDRESS_DWordLength_start 0 #define GFX12_STATE_BASE_ADDRESS_DWordLength_start 0 #define GFX11_STATE_BASE_ADDRESS_DWordLength_start 0 #define GFX9_STATE_BASE_ADDRESS_DWordLength_start 0 #define GFX8_STATE_BASE_ADDRESS_DWordLength_start 0 #define GFX75_STATE_BASE_ADDRESS_DWordLength_start 0 #define GFX7_STATE_BASE_ADDRESS_DWordLength_start 0 #define GFX6_STATE_BASE_ADDRESS_DWordLength_start 0 #define GFX5_STATE_BASE_ADDRESS_DWordLength_start 0 #define GFX45_STATE_BASE_ADDRESS_DWordLength_start 0 #define GFX4_STATE_BASE_ADDRESS_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* STATE_BASE_ADDRESS::Dynamic State Access Upper Bound */ #define GFX75_STATE_BASE_ADDRESS_DynamicStateAccessUpperBound_bits 20 #define GFX7_STATE_BASE_ADDRESS_DynamicStateAccessUpperBound_bits 20 #define GFX6_STATE_BASE_ADDRESS_DynamicStateAccessUpperBound_bits 20 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_DynamicStateAccessUpperBound_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 20; case 70: return 20; case 60: return 20; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_STATE_BASE_ADDRESS_DynamicStateAccessUpperBound_start 236 #define GFX7_STATE_BASE_ADDRESS_DynamicStateAccessUpperBound_start 236 #define GFX6_STATE_BASE_ADDRESS_DynamicStateAccessUpperBound_start 236 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_DynamicStateAccessUpperBound_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 236; case 70: return 236; case 60: return 236; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* STATE_BASE_ADDRESS::Dynamic State Access Upper Bound Modify Enable */ #define GFX75_STATE_BASE_ADDRESS_DynamicStateAccessUpperBoundModifyEnable_bits 1 #define GFX7_STATE_BASE_ADDRESS_DynamicStateAccessUpperBoundModifyEnable_bits 1 #define GFX6_STATE_BASE_ADDRESS_DynamicStateAccessUpperBoundModifyEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_DynamicStateAccessUpperBoundModifyEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_STATE_BASE_ADDRESS_DynamicStateAccessUpperBoundModifyEnable_start 224 #define GFX7_STATE_BASE_ADDRESS_DynamicStateAccessUpperBoundModifyEnable_start 224 #define GFX6_STATE_BASE_ADDRESS_DynamicStateAccessUpperBoundModifyEnable_start 224 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_DynamicStateAccessUpperBoundModifyEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 224; case 70: return 224; case 60: return 224; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* STATE_BASE_ADDRESS::Dynamic State Base Address */ #define GFX125_STATE_BASE_ADDRESS_DynamicStateBaseAddress_bits 52 #define GFX12_STATE_BASE_ADDRESS_DynamicStateBaseAddress_bits 52 #define GFX11_STATE_BASE_ADDRESS_DynamicStateBaseAddress_bits 52 #define GFX9_STATE_BASE_ADDRESS_DynamicStateBaseAddress_bits 52 #define GFX8_STATE_BASE_ADDRESS_DynamicStateBaseAddress_bits 52 #define GFX75_STATE_BASE_ADDRESS_DynamicStateBaseAddress_bits 20 #define GFX7_STATE_BASE_ADDRESS_DynamicStateBaseAddress_bits 20 #define GFX6_STATE_BASE_ADDRESS_DynamicStateBaseAddress_bits 20 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_DynamicStateBaseAddress_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 52; case 120: return 52; case 110: return 52; case 90: return 52; case 80: return 52; case 75: return 20; case 70: return 20; case 60: return 20; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_STATE_BASE_ADDRESS_DynamicStateBaseAddress_start 204 #define GFX12_STATE_BASE_ADDRESS_DynamicStateBaseAddress_start 204 #define GFX11_STATE_BASE_ADDRESS_DynamicStateBaseAddress_start 204 #define GFX9_STATE_BASE_ADDRESS_DynamicStateBaseAddress_start 204 #define GFX8_STATE_BASE_ADDRESS_DynamicStateBaseAddress_start 204 #define GFX75_STATE_BASE_ADDRESS_DynamicStateBaseAddress_start 108 #define GFX7_STATE_BASE_ADDRESS_DynamicStateBaseAddress_start 108 #define GFX6_STATE_BASE_ADDRESS_DynamicStateBaseAddress_start 108 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_DynamicStateBaseAddress_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 204; case 120: return 204; case 110: return 204; case 90: return 204; case 80: return 204; case 75: return 108; case 70: return 108; case 60: return 108; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* STATE_BASE_ADDRESS::Dynamic State Base Address Modify Enable */ #define GFX125_STATE_BASE_ADDRESS_DynamicStateBaseAddressModifyEnable_bits 1 #define GFX12_STATE_BASE_ADDRESS_DynamicStateBaseAddressModifyEnable_bits 1 #define GFX11_STATE_BASE_ADDRESS_DynamicStateBaseAddressModifyEnable_bits 1 #define GFX9_STATE_BASE_ADDRESS_DynamicStateBaseAddressModifyEnable_bits 1 #define GFX8_STATE_BASE_ADDRESS_DynamicStateBaseAddressModifyEnable_bits 1 #define GFX75_STATE_BASE_ADDRESS_DynamicStateBaseAddressModifyEnable_bits 1 #define GFX7_STATE_BASE_ADDRESS_DynamicStateBaseAddressModifyEnable_bits 1 #define GFX6_STATE_BASE_ADDRESS_DynamicStateBaseAddressModifyEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_DynamicStateBaseAddressModifyEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_STATE_BASE_ADDRESS_DynamicStateBaseAddressModifyEnable_start 192 #define GFX12_STATE_BASE_ADDRESS_DynamicStateBaseAddressModifyEnable_start 192 #define GFX11_STATE_BASE_ADDRESS_DynamicStateBaseAddressModifyEnable_start 192 #define GFX9_STATE_BASE_ADDRESS_DynamicStateBaseAddressModifyEnable_start 192 #define GFX8_STATE_BASE_ADDRESS_DynamicStateBaseAddressModifyEnable_start 192 #define GFX75_STATE_BASE_ADDRESS_DynamicStateBaseAddressModifyEnable_start 96 #define GFX7_STATE_BASE_ADDRESS_DynamicStateBaseAddressModifyEnable_start 96 #define GFX6_STATE_BASE_ADDRESS_DynamicStateBaseAddressModifyEnable_start 96 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_DynamicStateBaseAddressModifyEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 192; case 120: return 192; case 110: return 192; case 90: return 192; case 80: return 192; case 75: return 96; case 70: return 96; case 60: return 96; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* STATE_BASE_ADDRESS::Dynamic State Buffer Size */ #define GFX125_STATE_BASE_ADDRESS_DynamicStateBufferSize_bits 20 #define GFX12_STATE_BASE_ADDRESS_DynamicStateBufferSize_bits 20 #define GFX11_STATE_BASE_ADDRESS_DynamicStateBufferSize_bits 20 #define GFX9_STATE_BASE_ADDRESS_DynamicStateBufferSize_bits 20 #define GFX8_STATE_BASE_ADDRESS_DynamicStateBufferSize_bits 20 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_DynamicStateBufferSize_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 20; case 120: return 20; case 110: return 20; case 90: return 20; case 80: return 20; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_STATE_BASE_ADDRESS_DynamicStateBufferSize_start 428 #define GFX12_STATE_BASE_ADDRESS_DynamicStateBufferSize_start 428 #define GFX11_STATE_BASE_ADDRESS_DynamicStateBufferSize_start 428 #define GFX9_STATE_BASE_ADDRESS_DynamicStateBufferSize_start 428 #define GFX8_STATE_BASE_ADDRESS_DynamicStateBufferSize_start 428 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_DynamicStateBufferSize_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 428; case 120: return 428; case 110: return 428; case 90: return 428; case 80: return 428; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* STATE_BASE_ADDRESS::Dynamic State Buffer Size Modify Enable */ #define GFX125_STATE_BASE_ADDRESS_DynamicStateBufferSizeModifyEnable_bits 1 #define GFX12_STATE_BASE_ADDRESS_DynamicStateBufferSizeModifyEnable_bits 1 #define GFX11_STATE_BASE_ADDRESS_DynamicStateBufferSizeModifyEnable_bits 1 #define GFX9_STATE_BASE_ADDRESS_DynamicStateBufferSizeModifyEnable_bits 1 #define GFX8_STATE_BASE_ADDRESS_DynamicStateBufferSizeModifyEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_DynamicStateBufferSizeModifyEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_STATE_BASE_ADDRESS_DynamicStateBufferSizeModifyEnable_start 416 #define GFX12_STATE_BASE_ADDRESS_DynamicStateBufferSizeModifyEnable_start 416 #define GFX11_STATE_BASE_ADDRESS_DynamicStateBufferSizeModifyEnable_start 416 #define GFX9_STATE_BASE_ADDRESS_DynamicStateBufferSizeModifyEnable_start 416 #define GFX8_STATE_BASE_ADDRESS_DynamicStateBufferSizeModifyEnable_start 416 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_DynamicStateBufferSizeModifyEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 416; case 120: return 416; case 110: return 416; case 90: return 416; case 80: return 416; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* STATE_BASE_ADDRESS::Dynamic State MOCS */ #define GFX125_STATE_BASE_ADDRESS_DynamicStateMOCS_bits 7 #define GFX12_STATE_BASE_ADDRESS_DynamicStateMOCS_bits 7 #define GFX11_STATE_BASE_ADDRESS_DynamicStateMOCS_bits 7 #define GFX9_STATE_BASE_ADDRESS_DynamicStateMOCS_bits 7 #define GFX8_STATE_BASE_ADDRESS_DynamicStateMOCS_bits 7 #define GFX75_STATE_BASE_ADDRESS_DynamicStateMOCS_bits 4 #define GFX7_STATE_BASE_ADDRESS_DynamicStateMOCS_bits 4 #define GFX6_STATE_BASE_ADDRESS_DynamicStateMOCS_bits 4 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_DynamicStateMOCS_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 7; case 120: return 7; case 110: return 7; case 90: return 7; case 80: return 7; case 75: return 4; case 70: return 4; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_STATE_BASE_ADDRESS_DynamicStateMOCS_start 196 #define GFX12_STATE_BASE_ADDRESS_DynamicStateMOCS_start 196 #define GFX11_STATE_BASE_ADDRESS_DynamicStateMOCS_start 196 #define GFX9_STATE_BASE_ADDRESS_DynamicStateMOCS_start 196 #define GFX8_STATE_BASE_ADDRESS_DynamicStateMOCS_start 196 #define GFX75_STATE_BASE_ADDRESS_DynamicStateMOCS_start 104 #define GFX7_STATE_BASE_ADDRESS_DynamicStateMOCS_start 104 #define GFX6_STATE_BASE_ADDRESS_DynamicStateMOCS_start 104 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_DynamicStateMOCS_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 196; case 120: return 196; case 110: return 196; case 90: return 196; case 80: return 196; case 75: return 104; case 70: return 104; case 60: return 104; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* STATE_BASE_ADDRESS::General State Access Upper Bound */ #define GFX75_STATE_BASE_ADDRESS_GeneralStateAccessUpperBound_bits 20 #define GFX7_STATE_BASE_ADDRESS_GeneralStateAccessUpperBound_bits 20 #define GFX6_STATE_BASE_ADDRESS_GeneralStateAccessUpperBound_bits 20 #define GFX5_STATE_BASE_ADDRESS_GeneralStateAccessUpperBound_bits 20 #define GFX45_STATE_BASE_ADDRESS_GeneralStateAccessUpperBound_bits 20 #define GFX4_STATE_BASE_ADDRESS_GeneralStateAccessUpperBound_bits 20 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_GeneralStateAccessUpperBound_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 20; case 70: return 20; case 60: return 20; case 50: return 20; case 45: return 20; case 40: return 20; default: unreachable("Invalid hardware generation"); } } #define GFX75_STATE_BASE_ADDRESS_GeneralStateAccessUpperBound_start 204 #define GFX7_STATE_BASE_ADDRESS_GeneralStateAccessUpperBound_start 204 #define GFX6_STATE_BASE_ADDRESS_GeneralStateAccessUpperBound_start 204 #define GFX5_STATE_BASE_ADDRESS_GeneralStateAccessUpperBound_start 172 #define GFX45_STATE_BASE_ADDRESS_GeneralStateAccessUpperBound_start 140 #define GFX4_STATE_BASE_ADDRESS_GeneralStateAccessUpperBound_start 140 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_GeneralStateAccessUpperBound_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 204; case 70: return 204; case 60: return 204; case 50: return 172; case 45: return 140; case 40: return 140; default: unreachable("Invalid hardware generation"); } } /* STATE_BASE_ADDRESS::General State Access Upper Bound Modify Enable */ #define GFX75_STATE_BASE_ADDRESS_GeneralStateAccessUpperBoundModifyEnable_bits 1 #define GFX7_STATE_BASE_ADDRESS_GeneralStateAccessUpperBoundModifyEnable_bits 1 #define GFX6_STATE_BASE_ADDRESS_GeneralStateAccessUpperBoundModifyEnable_bits 1 #define GFX5_STATE_BASE_ADDRESS_GeneralStateAccessUpperBoundModifyEnable_bits 1 #define GFX45_STATE_BASE_ADDRESS_GeneralStateAccessUpperBoundModifyEnable_bits 1 #define GFX4_STATE_BASE_ADDRESS_GeneralStateAccessUpperBoundModifyEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_GeneralStateAccessUpperBoundModifyEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX75_STATE_BASE_ADDRESS_GeneralStateAccessUpperBoundModifyEnable_start 192 #define GFX7_STATE_BASE_ADDRESS_GeneralStateAccessUpperBoundModifyEnable_start 192 #define GFX6_STATE_BASE_ADDRESS_GeneralStateAccessUpperBoundModifyEnable_start 192 #define GFX5_STATE_BASE_ADDRESS_GeneralStateAccessUpperBoundModifyEnable_start 160 #define GFX45_STATE_BASE_ADDRESS_GeneralStateAccessUpperBoundModifyEnable_start 128 #define GFX4_STATE_BASE_ADDRESS_GeneralStateAccessUpperBoundModifyEnable_start 128 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_GeneralStateAccessUpperBoundModifyEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 192; case 70: return 192; case 60: return 192; case 50: return 160; case 45: return 128; case 40: return 128; default: unreachable("Invalid hardware generation"); } } /* STATE_BASE_ADDRESS::General State Base Address */ #define GFX125_STATE_BASE_ADDRESS_GeneralStateBaseAddress_bits 52 #define GFX12_STATE_BASE_ADDRESS_GeneralStateBaseAddress_bits 52 #define GFX11_STATE_BASE_ADDRESS_GeneralStateBaseAddress_bits 52 #define GFX9_STATE_BASE_ADDRESS_GeneralStateBaseAddress_bits 52 #define GFX8_STATE_BASE_ADDRESS_GeneralStateBaseAddress_bits 52 #define GFX75_STATE_BASE_ADDRESS_GeneralStateBaseAddress_bits 20 #define GFX7_STATE_BASE_ADDRESS_GeneralStateBaseAddress_bits 20 #define GFX6_STATE_BASE_ADDRESS_GeneralStateBaseAddress_bits 20 #define GFX5_STATE_BASE_ADDRESS_GeneralStateBaseAddress_bits 20 #define GFX45_STATE_BASE_ADDRESS_GeneralStateBaseAddress_bits 20 #define GFX4_STATE_BASE_ADDRESS_GeneralStateBaseAddress_bits 20 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_GeneralStateBaseAddress_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 52; case 120: return 52; case 110: return 52; case 90: return 52; case 80: return 52; case 75: return 20; case 70: return 20; case 60: return 20; case 50: return 20; case 45: return 20; case 40: return 20; default: unreachable("Invalid hardware generation"); } } #define GFX125_STATE_BASE_ADDRESS_GeneralStateBaseAddress_start 44 #define GFX12_STATE_BASE_ADDRESS_GeneralStateBaseAddress_start 44 #define GFX11_STATE_BASE_ADDRESS_GeneralStateBaseAddress_start 44 #define GFX9_STATE_BASE_ADDRESS_GeneralStateBaseAddress_start 44 #define GFX8_STATE_BASE_ADDRESS_GeneralStateBaseAddress_start 44 #define GFX75_STATE_BASE_ADDRESS_GeneralStateBaseAddress_start 44 #define GFX7_STATE_BASE_ADDRESS_GeneralStateBaseAddress_start 44 #define GFX6_STATE_BASE_ADDRESS_GeneralStateBaseAddress_start 44 #define GFX5_STATE_BASE_ADDRESS_GeneralStateBaseAddress_start 44 #define GFX45_STATE_BASE_ADDRESS_GeneralStateBaseAddress_start 44 #define GFX4_STATE_BASE_ADDRESS_GeneralStateBaseAddress_start 44 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_GeneralStateBaseAddress_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 44; case 120: return 44; case 110: return 44; case 90: return 44; case 80: return 44; case 75: return 44; case 70: return 44; case 60: return 44; case 50: return 44; case 45: return 44; case 40: return 44; default: unreachable("Invalid hardware generation"); } } /* STATE_BASE_ADDRESS::General State Base Address Modify Enable */ #define GFX125_STATE_BASE_ADDRESS_GeneralStateBaseAddressModifyEnable_bits 1 #define GFX12_STATE_BASE_ADDRESS_GeneralStateBaseAddressModifyEnable_bits 1 #define GFX11_STATE_BASE_ADDRESS_GeneralStateBaseAddressModifyEnable_bits 1 #define GFX9_STATE_BASE_ADDRESS_GeneralStateBaseAddressModifyEnable_bits 1 #define GFX8_STATE_BASE_ADDRESS_GeneralStateBaseAddressModifyEnable_bits 1 #define GFX75_STATE_BASE_ADDRESS_GeneralStateBaseAddressModifyEnable_bits 1 #define GFX7_STATE_BASE_ADDRESS_GeneralStateBaseAddressModifyEnable_bits 1 #define GFX6_STATE_BASE_ADDRESS_GeneralStateBaseAddressModifyEnable_bits 1 #define GFX5_STATE_BASE_ADDRESS_GeneralStateBaseAddressModifyEnable_bits 1 #define GFX45_STATE_BASE_ADDRESS_GeneralStateBaseAddressModifyEnable_bits 1 #define GFX4_STATE_BASE_ADDRESS_GeneralStateBaseAddressModifyEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_GeneralStateBaseAddressModifyEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX125_STATE_BASE_ADDRESS_GeneralStateBaseAddressModifyEnable_start 32 #define GFX12_STATE_BASE_ADDRESS_GeneralStateBaseAddressModifyEnable_start 32 #define GFX11_STATE_BASE_ADDRESS_GeneralStateBaseAddressModifyEnable_start 32 #define GFX9_STATE_BASE_ADDRESS_GeneralStateBaseAddressModifyEnable_start 32 #define GFX8_STATE_BASE_ADDRESS_GeneralStateBaseAddressModifyEnable_start 32 #define GFX75_STATE_BASE_ADDRESS_GeneralStateBaseAddressModifyEnable_start 32 #define GFX7_STATE_BASE_ADDRESS_GeneralStateBaseAddressModifyEnable_start 32 #define GFX6_STATE_BASE_ADDRESS_GeneralStateBaseAddressModifyEnable_start 32 #define GFX5_STATE_BASE_ADDRESS_GeneralStateBaseAddressModifyEnable_start 32 #define GFX45_STATE_BASE_ADDRESS_GeneralStateBaseAddressModifyEnable_start 32 #define GFX4_STATE_BASE_ADDRESS_GeneralStateBaseAddressModifyEnable_start 32 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_GeneralStateBaseAddressModifyEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 32; case 50: return 32; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } /* STATE_BASE_ADDRESS::General State Buffer Size */ #define GFX125_STATE_BASE_ADDRESS_GeneralStateBufferSize_bits 20 #define GFX12_STATE_BASE_ADDRESS_GeneralStateBufferSize_bits 20 #define GFX11_STATE_BASE_ADDRESS_GeneralStateBufferSize_bits 20 #define GFX9_STATE_BASE_ADDRESS_GeneralStateBufferSize_bits 20 #define GFX8_STATE_BASE_ADDRESS_GeneralStateBufferSize_bits 20 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_GeneralStateBufferSize_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 20; case 120: return 20; case 110: return 20; case 90: return 20; case 80: return 20; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_STATE_BASE_ADDRESS_GeneralStateBufferSize_start 396 #define GFX12_STATE_BASE_ADDRESS_GeneralStateBufferSize_start 396 #define GFX11_STATE_BASE_ADDRESS_GeneralStateBufferSize_start 396 #define GFX9_STATE_BASE_ADDRESS_GeneralStateBufferSize_start 396 #define GFX8_STATE_BASE_ADDRESS_GeneralStateBufferSize_start 396 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_GeneralStateBufferSize_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 396; case 120: return 396; case 110: return 396; case 90: return 396; case 80: return 396; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* STATE_BASE_ADDRESS::General State Buffer Size Modify Enable */ #define GFX125_STATE_BASE_ADDRESS_GeneralStateBufferSizeModifyEnable_bits 1 #define GFX12_STATE_BASE_ADDRESS_GeneralStateBufferSizeModifyEnable_bits 1 #define GFX11_STATE_BASE_ADDRESS_GeneralStateBufferSizeModifyEnable_bits 1 #define GFX9_STATE_BASE_ADDRESS_GeneralStateBufferSizeModifyEnable_bits 1 #define GFX8_STATE_BASE_ADDRESS_GeneralStateBufferSizeModifyEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_GeneralStateBufferSizeModifyEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_STATE_BASE_ADDRESS_GeneralStateBufferSizeModifyEnable_start 384 #define GFX12_STATE_BASE_ADDRESS_GeneralStateBufferSizeModifyEnable_start 384 #define GFX11_STATE_BASE_ADDRESS_GeneralStateBufferSizeModifyEnable_start 384 #define GFX9_STATE_BASE_ADDRESS_GeneralStateBufferSizeModifyEnable_start 384 #define GFX8_STATE_BASE_ADDRESS_GeneralStateBufferSizeModifyEnable_start 384 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_GeneralStateBufferSizeModifyEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 384; case 120: return 384; case 110: return 384; case 90: return 384; case 80: return 384; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* STATE_BASE_ADDRESS::General State MOCS */ #define GFX125_STATE_BASE_ADDRESS_GeneralStateMOCS_bits 7 #define GFX12_STATE_BASE_ADDRESS_GeneralStateMOCS_bits 7 #define GFX11_STATE_BASE_ADDRESS_GeneralStateMOCS_bits 7 #define GFX9_STATE_BASE_ADDRESS_GeneralStateMOCS_bits 7 #define GFX8_STATE_BASE_ADDRESS_GeneralStateMOCS_bits 7 #define GFX75_STATE_BASE_ADDRESS_GeneralStateMOCS_bits 4 #define GFX7_STATE_BASE_ADDRESS_GeneralStateMOCS_bits 4 #define GFX6_STATE_BASE_ADDRESS_GeneralStateMOCS_bits 4 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_GeneralStateMOCS_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 7; case 120: return 7; case 110: return 7; case 90: return 7; case 80: return 7; case 75: return 4; case 70: return 4; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_STATE_BASE_ADDRESS_GeneralStateMOCS_start 36 #define GFX12_STATE_BASE_ADDRESS_GeneralStateMOCS_start 36 #define GFX11_STATE_BASE_ADDRESS_GeneralStateMOCS_start 36 #define GFX9_STATE_BASE_ADDRESS_GeneralStateMOCS_start 36 #define GFX8_STATE_BASE_ADDRESS_GeneralStateMOCS_start 36 #define GFX75_STATE_BASE_ADDRESS_GeneralStateMOCS_start 40 #define GFX7_STATE_BASE_ADDRESS_GeneralStateMOCS_start 40 #define GFX6_STATE_BASE_ADDRESS_GeneralStateMOCS_start 40 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_GeneralStateMOCS_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 36; case 120: return 36; case 110: return 36; case 90: return 36; case 80: return 36; case 75: return 40; case 70: return 40; case 60: return 40; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* STATE_BASE_ADDRESS::Indirect Object Access Upper Bound */ #define GFX75_STATE_BASE_ADDRESS_IndirectObjectAccessUpperBound_bits 20 #define GFX7_STATE_BASE_ADDRESS_IndirectObjectAccessUpperBound_bits 20 #define GFX6_STATE_BASE_ADDRESS_IndirectObjectAccessUpperBound_bits 20 #define GFX5_STATE_BASE_ADDRESS_IndirectObjectAccessUpperBound_bits 20 #define GFX45_STATE_BASE_ADDRESS_IndirectObjectAccessUpperBound_bits 20 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_IndirectObjectAccessUpperBound_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 20; case 70: return 20; case 60: return 20; case 50: return 20; case 45: return 20; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_STATE_BASE_ADDRESS_IndirectObjectAccessUpperBound_start 268 #define GFX7_STATE_BASE_ADDRESS_IndirectObjectAccessUpperBound_start 268 #define GFX6_STATE_BASE_ADDRESS_IndirectObjectAccessUpperBound_start 268 #define GFX5_STATE_BASE_ADDRESS_IndirectObjectAccessUpperBound_start 204 #define GFX45_STATE_BASE_ADDRESS_IndirectObjectAccessUpperBound_start 172 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_IndirectObjectAccessUpperBound_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 268; case 70: return 268; case 60: return 268; case 50: return 204; case 45: return 172; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* STATE_BASE_ADDRESS::Indirect Object Access Upper Bound Modify Enable */ #define GFX75_STATE_BASE_ADDRESS_IndirectObjectAccessUpperBoundModifyEnable_bits 1 #define GFX7_STATE_BASE_ADDRESS_IndirectObjectAccessUpperBoundModifyEnable_bits 1 #define GFX6_STATE_BASE_ADDRESS_IndirectObjectAccessUpperBoundModifyEnable_bits 1 #define GFX5_STATE_BASE_ADDRESS_IndirectObjectAccessUpperBoundModifyEnable_bits 1 #define GFX45_STATE_BASE_ADDRESS_IndirectObjectAccessUpperBoundModifyEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_IndirectObjectAccessUpperBoundModifyEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 1; case 45: return 1; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_STATE_BASE_ADDRESS_IndirectObjectAccessUpperBoundModifyEnable_start 256 #define GFX7_STATE_BASE_ADDRESS_IndirectObjectAccessUpperBoundModifyEnable_start 256 #define GFX6_STATE_BASE_ADDRESS_IndirectObjectAccessUpperBoundModifyEnable_start 256 #define GFX5_STATE_BASE_ADDRESS_IndirectObjectAccessUpperBoundModifyEnable_start 192 #define GFX45_STATE_BASE_ADDRESS_IndirectObjectAccessUpperBoundModifyEnable_start 160 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_IndirectObjectAccessUpperBoundModifyEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 256; case 70: return 256; case 60: return 256; case 50: return 192; case 45: return 160; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* STATE_BASE_ADDRESS::Indirect Object Base Address */ #define GFX125_STATE_BASE_ADDRESS_IndirectObjectBaseAddress_bits 52 #define GFX12_STATE_BASE_ADDRESS_IndirectObjectBaseAddress_bits 52 #define GFX11_STATE_BASE_ADDRESS_IndirectObjectBaseAddress_bits 52 #define GFX9_STATE_BASE_ADDRESS_IndirectObjectBaseAddress_bits 52 #define GFX8_STATE_BASE_ADDRESS_IndirectObjectBaseAddress_bits 52 #define GFX75_STATE_BASE_ADDRESS_IndirectObjectBaseAddress_bits 20 #define GFX7_STATE_BASE_ADDRESS_IndirectObjectBaseAddress_bits 20 #define GFX6_STATE_BASE_ADDRESS_IndirectObjectBaseAddress_bits 20 #define GFX5_STATE_BASE_ADDRESS_IndirectObjectBaseAddress_bits 20 #define GFX45_STATE_BASE_ADDRESS_IndirectObjectBaseAddress_bits 20 #define GFX4_STATE_BASE_ADDRESS_IndirectObjectBaseAddress_bits 20 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_IndirectObjectBaseAddress_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 52; case 120: return 52; case 110: return 52; case 90: return 52; case 80: return 52; case 75: return 20; case 70: return 20; case 60: return 20; case 50: return 20; case 45: return 20; case 40: return 20; default: unreachable("Invalid hardware generation"); } } #define GFX125_STATE_BASE_ADDRESS_IndirectObjectBaseAddress_start 268 #define GFX12_STATE_BASE_ADDRESS_IndirectObjectBaseAddress_start 268 #define GFX11_STATE_BASE_ADDRESS_IndirectObjectBaseAddress_start 268 #define GFX9_STATE_BASE_ADDRESS_IndirectObjectBaseAddress_start 268 #define GFX8_STATE_BASE_ADDRESS_IndirectObjectBaseAddress_start 268 #define GFX75_STATE_BASE_ADDRESS_IndirectObjectBaseAddress_start 140 #define GFX7_STATE_BASE_ADDRESS_IndirectObjectBaseAddress_start 140 #define GFX6_STATE_BASE_ADDRESS_IndirectObjectBaseAddress_start 140 #define GFX5_STATE_BASE_ADDRESS_IndirectObjectBaseAddress_start 108 #define GFX45_STATE_BASE_ADDRESS_IndirectObjectBaseAddress_start 108 #define GFX4_STATE_BASE_ADDRESS_IndirectObjectBaseAddress_start 108 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_IndirectObjectBaseAddress_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 268; case 120: return 268; case 110: return 268; case 90: return 268; case 80: return 268; case 75: return 140; case 70: return 140; case 60: return 140; case 50: return 108; case 45: return 108; case 40: return 108; default: unreachable("Invalid hardware generation"); } } /* STATE_BASE_ADDRESS::Indirect Object Base Address Modify Enable */ #define GFX125_STATE_BASE_ADDRESS_IndirectObjectBaseAddressModifyEnable_bits 1 #define GFX12_STATE_BASE_ADDRESS_IndirectObjectBaseAddressModifyEnable_bits 1 #define GFX11_STATE_BASE_ADDRESS_IndirectObjectBaseAddressModifyEnable_bits 1 #define GFX9_STATE_BASE_ADDRESS_IndirectObjectBaseAddressModifyEnable_bits 1 #define GFX8_STATE_BASE_ADDRESS_IndirectObjectBaseAddressModifyEnable_bits 1 #define GFX75_STATE_BASE_ADDRESS_IndirectObjectBaseAddressModifyEnable_bits 1 #define GFX7_STATE_BASE_ADDRESS_IndirectObjectBaseAddressModifyEnable_bits 1 #define GFX6_STATE_BASE_ADDRESS_IndirectObjectBaseAddressModifyEnable_bits 1 #define GFX5_STATE_BASE_ADDRESS_IndirectObjectBaseAddressModifyEnable_bits 1 #define GFX45_STATE_BASE_ADDRESS_IndirectObjectBaseAddressModifyEnable_bits 1 #define GFX4_STATE_BASE_ADDRESS_IndirectObjectBaseAddressModifyEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_IndirectObjectBaseAddressModifyEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX125_STATE_BASE_ADDRESS_IndirectObjectBaseAddressModifyEnable_start 256 #define GFX12_STATE_BASE_ADDRESS_IndirectObjectBaseAddressModifyEnable_start 256 #define GFX11_STATE_BASE_ADDRESS_IndirectObjectBaseAddressModifyEnable_start 256 #define GFX9_STATE_BASE_ADDRESS_IndirectObjectBaseAddressModifyEnable_start 256 #define GFX8_STATE_BASE_ADDRESS_IndirectObjectBaseAddressModifyEnable_start 256 #define GFX75_STATE_BASE_ADDRESS_IndirectObjectBaseAddressModifyEnable_start 128 #define GFX7_STATE_BASE_ADDRESS_IndirectObjectBaseAddressModifyEnable_start 128 #define GFX6_STATE_BASE_ADDRESS_IndirectObjectBaseAddressModifyEnable_start 128 #define GFX5_STATE_BASE_ADDRESS_IndirectObjectBaseAddressModifyEnable_start 96 #define GFX45_STATE_BASE_ADDRESS_IndirectObjectBaseAddressModifyEnable_start 96 #define GFX4_STATE_BASE_ADDRESS_IndirectObjectBaseAddressModifyEnable_start 96 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_IndirectObjectBaseAddressModifyEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 256; case 120: return 256; case 110: return 256; case 90: return 256; case 80: return 256; case 75: return 128; case 70: return 128; case 60: return 128; case 50: return 96; case 45: return 96; case 40: return 96; default: unreachable("Invalid hardware generation"); } } /* STATE_BASE_ADDRESS::Indirect Object Buffer Size */ #define GFX125_STATE_BASE_ADDRESS_IndirectObjectBufferSize_bits 20 #define GFX12_STATE_BASE_ADDRESS_IndirectObjectBufferSize_bits 20 #define GFX11_STATE_BASE_ADDRESS_IndirectObjectBufferSize_bits 20 #define GFX9_STATE_BASE_ADDRESS_IndirectObjectBufferSize_bits 20 #define GFX8_STATE_BASE_ADDRESS_IndirectObjectBufferSize_bits 20 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_IndirectObjectBufferSize_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 20; case 120: return 20; case 110: return 20; case 90: return 20; case 80: return 20; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_STATE_BASE_ADDRESS_IndirectObjectBufferSize_start 460 #define GFX12_STATE_BASE_ADDRESS_IndirectObjectBufferSize_start 460 #define GFX11_STATE_BASE_ADDRESS_IndirectObjectBufferSize_start 460 #define GFX9_STATE_BASE_ADDRESS_IndirectObjectBufferSize_start 460 #define GFX8_STATE_BASE_ADDRESS_IndirectObjectBufferSize_start 460 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_IndirectObjectBufferSize_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 460; case 120: return 460; case 110: return 460; case 90: return 460; case 80: return 460; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* STATE_BASE_ADDRESS::Indirect Object Buffer Size Modify Enable */ #define GFX125_STATE_BASE_ADDRESS_IndirectObjectBufferSizeModifyEnable_bits 1 #define GFX12_STATE_BASE_ADDRESS_IndirectObjectBufferSizeModifyEnable_bits 1 #define GFX11_STATE_BASE_ADDRESS_IndirectObjectBufferSizeModifyEnable_bits 1 #define GFX9_STATE_BASE_ADDRESS_IndirectObjectBufferSizeModifyEnable_bits 1 #define GFX8_STATE_BASE_ADDRESS_IndirectObjectBufferSizeModifyEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_IndirectObjectBufferSizeModifyEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_STATE_BASE_ADDRESS_IndirectObjectBufferSizeModifyEnable_start 448 #define GFX12_STATE_BASE_ADDRESS_IndirectObjectBufferSizeModifyEnable_start 448 #define GFX11_STATE_BASE_ADDRESS_IndirectObjectBufferSizeModifyEnable_start 448 #define GFX9_STATE_BASE_ADDRESS_IndirectObjectBufferSizeModifyEnable_start 448 #define GFX8_STATE_BASE_ADDRESS_IndirectObjectBufferSizeModifyEnable_start 448 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_IndirectObjectBufferSizeModifyEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 448; case 120: return 448; case 110: return 448; case 90: return 448; case 80: return 448; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* STATE_BASE_ADDRESS::Indirect Object MOCS */ #define GFX125_STATE_BASE_ADDRESS_IndirectObjectMOCS_bits 7 #define GFX12_STATE_BASE_ADDRESS_IndirectObjectMOCS_bits 7 #define GFX11_STATE_BASE_ADDRESS_IndirectObjectMOCS_bits 7 #define GFX9_STATE_BASE_ADDRESS_IndirectObjectMOCS_bits 7 #define GFX8_STATE_BASE_ADDRESS_IndirectObjectMOCS_bits 7 #define GFX75_STATE_BASE_ADDRESS_IndirectObjectMOCS_bits 4 #define GFX7_STATE_BASE_ADDRESS_IndirectObjectMOCS_bits 4 #define GFX6_STATE_BASE_ADDRESS_IndirectObjectMOCS_bits 4 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_IndirectObjectMOCS_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 7; case 120: return 7; case 110: return 7; case 90: return 7; case 80: return 7; case 75: return 4; case 70: return 4; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_STATE_BASE_ADDRESS_IndirectObjectMOCS_start 260 #define GFX12_STATE_BASE_ADDRESS_IndirectObjectMOCS_start 260 #define GFX11_STATE_BASE_ADDRESS_IndirectObjectMOCS_start 260 #define GFX9_STATE_BASE_ADDRESS_IndirectObjectMOCS_start 260 #define GFX8_STATE_BASE_ADDRESS_IndirectObjectMOCS_start 260 #define GFX75_STATE_BASE_ADDRESS_IndirectObjectMOCS_start 136 #define GFX7_STATE_BASE_ADDRESS_IndirectObjectMOCS_start 136 #define GFX6_STATE_BASE_ADDRESS_IndirectObjectMOCS_start 136 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_IndirectObjectMOCS_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 260; case 120: return 260; case 110: return 260; case 90: return 260; case 80: return 260; case 75: return 136; case 70: return 136; case 60: return 136; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* STATE_BASE_ADDRESS::Instruction Access Upper Bound */ #define GFX75_STATE_BASE_ADDRESS_InstructionAccessUpperBound_bits 20 #define GFX7_STATE_BASE_ADDRESS_InstructionAccessUpperBound_bits 20 #define GFX6_STATE_BASE_ADDRESS_InstructionAccessUpperBound_bits 20 #define GFX5_STATE_BASE_ADDRESS_InstructionAccessUpperBound_bits 20 #define GFX4_STATE_BASE_ADDRESS_InstructionAccessUpperBound_bits 20 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_InstructionAccessUpperBound_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 20; case 70: return 20; case 60: return 20; case 50: return 20; case 45: return 0; case 40: return 20; default: unreachable("Invalid hardware generation"); } } #define GFX75_STATE_BASE_ADDRESS_InstructionAccessUpperBound_start 300 #define GFX7_STATE_BASE_ADDRESS_InstructionAccessUpperBound_start 300 #define GFX6_STATE_BASE_ADDRESS_InstructionAccessUpperBound_start 300 #define GFX5_STATE_BASE_ADDRESS_InstructionAccessUpperBound_start 236 #define GFX4_STATE_BASE_ADDRESS_InstructionAccessUpperBound_start 172 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_InstructionAccessUpperBound_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 300; case 70: return 300; case 60: return 300; case 50: return 236; case 45: return 0; case 40: return 172; default: unreachable("Invalid hardware generation"); } } /* STATE_BASE_ADDRESS::Instruction Access Upper Bound Modify Enable */ #define GFX75_STATE_BASE_ADDRESS_InstructionAccessUpperBoundModifyEnable_bits 1 #define GFX7_STATE_BASE_ADDRESS_InstructionAccessUpperBoundModifyEnable_bits 1 #define GFX6_STATE_BASE_ADDRESS_InstructionAccessUpperBoundModifyEnable_bits 1 #define GFX5_STATE_BASE_ADDRESS_InstructionAccessUpperBoundModifyEnable_bits 1 #define GFX4_STATE_BASE_ADDRESS_InstructionAccessUpperBoundModifyEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_InstructionAccessUpperBoundModifyEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 1; case 45: return 0; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX75_STATE_BASE_ADDRESS_InstructionAccessUpperBoundModifyEnable_start 288 #define GFX7_STATE_BASE_ADDRESS_InstructionAccessUpperBoundModifyEnable_start 288 #define GFX6_STATE_BASE_ADDRESS_InstructionAccessUpperBoundModifyEnable_start 288 #define GFX5_STATE_BASE_ADDRESS_InstructionAccessUpperBoundModifyEnable_start 224 #define GFX4_STATE_BASE_ADDRESS_InstructionAccessUpperBoundModifyEnable_start 160 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_InstructionAccessUpperBoundModifyEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 288; case 70: return 288; case 60: return 288; case 50: return 224; case 45: return 0; case 40: return 160; default: unreachable("Invalid hardware generation"); } } /* STATE_BASE_ADDRESS::Instruction Base Address */ #define GFX125_STATE_BASE_ADDRESS_InstructionBaseAddress_bits 52 #define GFX12_STATE_BASE_ADDRESS_InstructionBaseAddress_bits 52 #define GFX11_STATE_BASE_ADDRESS_InstructionBaseAddress_bits 52 #define GFX9_STATE_BASE_ADDRESS_InstructionBaseAddress_bits 52 #define GFX8_STATE_BASE_ADDRESS_InstructionBaseAddress_bits 52 #define GFX75_STATE_BASE_ADDRESS_InstructionBaseAddress_bits 20 #define GFX7_STATE_BASE_ADDRESS_InstructionBaseAddress_bits 20 #define GFX6_STATE_BASE_ADDRESS_InstructionBaseAddress_bits 20 #define GFX5_STATE_BASE_ADDRESS_InstructionBaseAddress_bits 20 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_InstructionBaseAddress_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 52; case 120: return 52; case 110: return 52; case 90: return 52; case 80: return 52; case 75: return 20; case 70: return 20; case 60: return 20; case 50: return 20; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_STATE_BASE_ADDRESS_InstructionBaseAddress_start 332 #define GFX12_STATE_BASE_ADDRESS_InstructionBaseAddress_start 332 #define GFX11_STATE_BASE_ADDRESS_InstructionBaseAddress_start 332 #define GFX9_STATE_BASE_ADDRESS_InstructionBaseAddress_start 332 #define GFX8_STATE_BASE_ADDRESS_InstructionBaseAddress_start 332 #define GFX75_STATE_BASE_ADDRESS_InstructionBaseAddress_start 172 #define GFX7_STATE_BASE_ADDRESS_InstructionBaseAddress_start 172 #define GFX6_STATE_BASE_ADDRESS_InstructionBaseAddress_start 172 #define GFX5_STATE_BASE_ADDRESS_InstructionBaseAddress_start 140 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_InstructionBaseAddress_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 332; case 120: return 332; case 110: return 332; case 90: return 332; case 80: return 332; case 75: return 172; case 70: return 172; case 60: return 172; case 50: return 140; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* STATE_BASE_ADDRESS::Instruction Base Address Modify Enable */ #define GFX125_STATE_BASE_ADDRESS_InstructionBaseAddressModifyEnable_bits 1 #define GFX12_STATE_BASE_ADDRESS_InstructionBaseAddressModifyEnable_bits 1 #define GFX11_STATE_BASE_ADDRESS_InstructionBaseAddressModifyEnable_bits 1 #define GFX9_STATE_BASE_ADDRESS_InstructionBaseAddressModifyEnable_bits 1 #define GFX8_STATE_BASE_ADDRESS_InstructionBaseAddressModifyEnable_bits 1 #define GFX75_STATE_BASE_ADDRESS_InstructionBaseAddressModifyEnable_bits 1 #define GFX7_STATE_BASE_ADDRESS_InstructionBaseAddressModifyEnable_bits 1 #define GFX6_STATE_BASE_ADDRESS_InstructionBaseAddressModifyEnable_bits 1 #define GFX5_STATE_BASE_ADDRESS_InstructionBaseAddressModifyEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_InstructionBaseAddressModifyEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 1; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_STATE_BASE_ADDRESS_InstructionBaseAddressModifyEnable_start 320 #define GFX12_STATE_BASE_ADDRESS_InstructionBaseAddressModifyEnable_start 320 #define GFX11_STATE_BASE_ADDRESS_InstructionBaseAddressModifyEnable_start 320 #define GFX9_STATE_BASE_ADDRESS_InstructionBaseAddressModifyEnable_start 320 #define GFX8_STATE_BASE_ADDRESS_InstructionBaseAddressModifyEnable_start 320 #define GFX75_STATE_BASE_ADDRESS_InstructionBaseAddressModifyEnable_start 160 #define GFX7_STATE_BASE_ADDRESS_InstructionBaseAddressModifyEnable_start 160 #define GFX6_STATE_BASE_ADDRESS_InstructionBaseAddressModifyEnable_start 160 #define GFX5_STATE_BASE_ADDRESS_InstructionBaseAddressModifyEnable_start 128 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_InstructionBaseAddressModifyEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 320; case 120: return 320; case 110: return 320; case 90: return 320; case 80: return 320; case 75: return 160; case 70: return 160; case 60: return 160; case 50: return 128; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* STATE_BASE_ADDRESS::Instruction Buffer Size */ #define GFX125_STATE_BASE_ADDRESS_InstructionBufferSize_bits 20 #define GFX12_STATE_BASE_ADDRESS_InstructionBufferSize_bits 20 #define GFX11_STATE_BASE_ADDRESS_InstructionBufferSize_bits 20 #define GFX9_STATE_BASE_ADDRESS_InstructionBufferSize_bits 20 #define GFX8_STATE_BASE_ADDRESS_InstructionBufferSize_bits 20 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_InstructionBufferSize_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 20; case 120: return 20; case 110: return 20; case 90: return 20; case 80: return 20; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_STATE_BASE_ADDRESS_InstructionBufferSize_start 492 #define GFX12_STATE_BASE_ADDRESS_InstructionBufferSize_start 492 #define GFX11_STATE_BASE_ADDRESS_InstructionBufferSize_start 492 #define GFX9_STATE_BASE_ADDRESS_InstructionBufferSize_start 492 #define GFX8_STATE_BASE_ADDRESS_InstructionBufferSize_start 492 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_InstructionBufferSize_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 492; case 120: return 492; case 110: return 492; case 90: return 492; case 80: return 492; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* STATE_BASE_ADDRESS::Instruction Buffer size Modify Enable */ #define GFX125_STATE_BASE_ADDRESS_InstructionBuffersizeModifyEnable_bits 1 #define GFX12_STATE_BASE_ADDRESS_InstructionBuffersizeModifyEnable_bits 1 #define GFX11_STATE_BASE_ADDRESS_InstructionBuffersizeModifyEnable_bits 1 #define GFX9_STATE_BASE_ADDRESS_InstructionBuffersizeModifyEnable_bits 1 #define GFX8_STATE_BASE_ADDRESS_InstructionBuffersizeModifyEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_InstructionBuffersizeModifyEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_STATE_BASE_ADDRESS_InstructionBuffersizeModifyEnable_start 480 #define GFX12_STATE_BASE_ADDRESS_InstructionBuffersizeModifyEnable_start 480 #define GFX11_STATE_BASE_ADDRESS_InstructionBuffersizeModifyEnable_start 480 #define GFX9_STATE_BASE_ADDRESS_InstructionBuffersizeModifyEnable_start 480 #define GFX8_STATE_BASE_ADDRESS_InstructionBuffersizeModifyEnable_start 480 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_InstructionBuffersizeModifyEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 480; case 120: return 480; case 110: return 480; case 90: return 480; case 80: return 480; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* STATE_BASE_ADDRESS::Instruction MOCS */ #define GFX125_STATE_BASE_ADDRESS_InstructionMOCS_bits 7 #define GFX12_STATE_BASE_ADDRESS_InstructionMOCS_bits 7 #define GFX11_STATE_BASE_ADDRESS_InstructionMOCS_bits 7 #define GFX9_STATE_BASE_ADDRESS_InstructionMOCS_bits 7 #define GFX8_STATE_BASE_ADDRESS_InstructionMOCS_bits 7 #define GFX75_STATE_BASE_ADDRESS_InstructionMOCS_bits 4 #define GFX7_STATE_BASE_ADDRESS_InstructionMOCS_bits 4 #define GFX6_STATE_BASE_ADDRESS_InstructionMOCS_bits 4 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_InstructionMOCS_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 7; case 120: return 7; case 110: return 7; case 90: return 7; case 80: return 7; case 75: return 4; case 70: return 4; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_STATE_BASE_ADDRESS_InstructionMOCS_start 324 #define GFX12_STATE_BASE_ADDRESS_InstructionMOCS_start 324 #define GFX11_STATE_BASE_ADDRESS_InstructionMOCS_start 324 #define GFX9_STATE_BASE_ADDRESS_InstructionMOCS_start 324 #define GFX8_STATE_BASE_ADDRESS_InstructionMOCS_start 324 #define GFX75_STATE_BASE_ADDRESS_InstructionMOCS_start 168 #define GFX7_STATE_BASE_ADDRESS_InstructionMOCS_start 168 #define GFX6_STATE_BASE_ADDRESS_InstructionMOCS_start 168 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_InstructionMOCS_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 324; case 120: return 324; case 110: return 324; case 90: return 324; case 80: return 324; case 75: return 168; case 70: return 168; case 60: return 168; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* STATE_BASE_ADDRESS::Stateless Data Port Access Force Write Thru */ #define GFX7_STATE_BASE_ADDRESS_StatelessDataPortAccessForceWriteThru_bits 1 #define GFX6_STATE_BASE_ADDRESS_StatelessDataPortAccessForceWriteThru_bits 1 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_StatelessDataPortAccessForceWriteThru_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX7_STATE_BASE_ADDRESS_StatelessDataPortAccessForceWriteThru_start 35 #define GFX6_STATE_BASE_ADDRESS_StatelessDataPortAccessForceWriteThru_start 35 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_StatelessDataPortAccessForceWriteThru_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 35; case 60: return 35; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* STATE_BASE_ADDRESS::Stateless Data Port Access MOCS */ #define GFX125_STATE_BASE_ADDRESS_StatelessDataPortAccessMOCS_bits 7 #define GFX12_STATE_BASE_ADDRESS_StatelessDataPortAccessMOCS_bits 7 #define GFX11_STATE_BASE_ADDRESS_StatelessDataPortAccessMOCS_bits 7 #define GFX9_STATE_BASE_ADDRESS_StatelessDataPortAccessMOCS_bits 7 #define GFX8_STATE_BASE_ADDRESS_StatelessDataPortAccessMOCS_bits 7 #define GFX75_STATE_BASE_ADDRESS_StatelessDataPortAccessMOCS_bits 4 #define GFX7_STATE_BASE_ADDRESS_StatelessDataPortAccessMOCS_bits 4 #define GFX6_STATE_BASE_ADDRESS_StatelessDataPortAccessMOCS_bits 4 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_StatelessDataPortAccessMOCS_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 7; case 120: return 7; case 110: return 7; case 90: return 7; case 80: return 7; case 75: return 4; case 70: return 4; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_STATE_BASE_ADDRESS_StatelessDataPortAccessMOCS_start 112 #define GFX12_STATE_BASE_ADDRESS_StatelessDataPortAccessMOCS_start 112 #define GFX11_STATE_BASE_ADDRESS_StatelessDataPortAccessMOCS_start 112 #define GFX9_STATE_BASE_ADDRESS_StatelessDataPortAccessMOCS_start 112 #define GFX8_STATE_BASE_ADDRESS_StatelessDataPortAccessMOCS_start 112 #define GFX75_STATE_BASE_ADDRESS_StatelessDataPortAccessMOCS_start 36 #define GFX7_STATE_BASE_ADDRESS_StatelessDataPortAccessMOCS_start 36 #define GFX6_STATE_BASE_ADDRESS_StatelessDataPortAccessMOCS_start 36 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_StatelessDataPortAccessMOCS_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 112; case 120: return 112; case 110: return 112; case 90: return 112; case 80: return 112; case 75: return 36; case 70: return 36; case 60: return 36; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* STATE_BASE_ADDRESS::Surface State Base Address */ #define GFX125_STATE_BASE_ADDRESS_SurfaceStateBaseAddress_bits 52 #define GFX12_STATE_BASE_ADDRESS_SurfaceStateBaseAddress_bits 52 #define GFX11_STATE_BASE_ADDRESS_SurfaceStateBaseAddress_bits 52 #define GFX9_STATE_BASE_ADDRESS_SurfaceStateBaseAddress_bits 52 #define GFX8_STATE_BASE_ADDRESS_SurfaceStateBaseAddress_bits 52 #define GFX75_STATE_BASE_ADDRESS_SurfaceStateBaseAddress_bits 20 #define GFX7_STATE_BASE_ADDRESS_SurfaceStateBaseAddress_bits 20 #define GFX6_STATE_BASE_ADDRESS_SurfaceStateBaseAddress_bits 20 #define GFX5_STATE_BASE_ADDRESS_SurfaceStateBaseAddress_bits 20 #define GFX45_STATE_BASE_ADDRESS_SurfaceStateBaseAddress_bits 20 #define GFX4_STATE_BASE_ADDRESS_SurfaceStateBaseAddress_bits 20 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_SurfaceStateBaseAddress_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 52; case 120: return 52; case 110: return 52; case 90: return 52; case 80: return 52; case 75: return 20; case 70: return 20; case 60: return 20; case 50: return 20; case 45: return 20; case 40: return 20; default: unreachable("Invalid hardware generation"); } } #define GFX125_STATE_BASE_ADDRESS_SurfaceStateBaseAddress_start 140 #define GFX12_STATE_BASE_ADDRESS_SurfaceStateBaseAddress_start 140 #define GFX11_STATE_BASE_ADDRESS_SurfaceStateBaseAddress_start 140 #define GFX9_STATE_BASE_ADDRESS_SurfaceStateBaseAddress_start 140 #define GFX8_STATE_BASE_ADDRESS_SurfaceStateBaseAddress_start 140 #define GFX75_STATE_BASE_ADDRESS_SurfaceStateBaseAddress_start 76 #define GFX7_STATE_BASE_ADDRESS_SurfaceStateBaseAddress_start 76 #define GFX6_STATE_BASE_ADDRESS_SurfaceStateBaseAddress_start 76 #define GFX5_STATE_BASE_ADDRESS_SurfaceStateBaseAddress_start 76 #define GFX45_STATE_BASE_ADDRESS_SurfaceStateBaseAddress_start 76 #define GFX4_STATE_BASE_ADDRESS_SurfaceStateBaseAddress_start 76 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_SurfaceStateBaseAddress_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 140; case 120: return 140; case 110: return 140; case 90: return 140; case 80: return 140; case 75: return 76; case 70: return 76; case 60: return 76; case 50: return 76; case 45: return 76; case 40: return 76; default: unreachable("Invalid hardware generation"); } } /* STATE_BASE_ADDRESS::Surface State Base Address Modify Enable */ #define GFX125_STATE_BASE_ADDRESS_SurfaceStateBaseAddressModifyEnable_bits 1 #define GFX12_STATE_BASE_ADDRESS_SurfaceStateBaseAddressModifyEnable_bits 1 #define GFX11_STATE_BASE_ADDRESS_SurfaceStateBaseAddressModifyEnable_bits 1 #define GFX9_STATE_BASE_ADDRESS_SurfaceStateBaseAddressModifyEnable_bits 1 #define GFX8_STATE_BASE_ADDRESS_SurfaceStateBaseAddressModifyEnable_bits 1 #define GFX75_STATE_BASE_ADDRESS_SurfaceStateBaseAddressModifyEnable_bits 1 #define GFX7_STATE_BASE_ADDRESS_SurfaceStateBaseAddressModifyEnable_bits 1 #define GFX6_STATE_BASE_ADDRESS_SurfaceStateBaseAddressModifyEnable_bits 1 #define GFX5_STATE_BASE_ADDRESS_SurfaceStateBaseAddressModifyEnable_bits 1 #define GFX45_STATE_BASE_ADDRESS_SurfaceStateBaseAddressModifyEnable_bits 1 #define GFX4_STATE_BASE_ADDRESS_SurfaceStateBaseAddressModifyEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_SurfaceStateBaseAddressModifyEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX125_STATE_BASE_ADDRESS_SurfaceStateBaseAddressModifyEnable_start 128 #define GFX12_STATE_BASE_ADDRESS_SurfaceStateBaseAddressModifyEnable_start 128 #define GFX11_STATE_BASE_ADDRESS_SurfaceStateBaseAddressModifyEnable_start 128 #define GFX9_STATE_BASE_ADDRESS_SurfaceStateBaseAddressModifyEnable_start 128 #define GFX8_STATE_BASE_ADDRESS_SurfaceStateBaseAddressModifyEnable_start 128 #define GFX75_STATE_BASE_ADDRESS_SurfaceStateBaseAddressModifyEnable_start 64 #define GFX7_STATE_BASE_ADDRESS_SurfaceStateBaseAddressModifyEnable_start 64 #define GFX6_STATE_BASE_ADDRESS_SurfaceStateBaseAddressModifyEnable_start 64 #define GFX5_STATE_BASE_ADDRESS_SurfaceStateBaseAddressModifyEnable_start 64 #define GFX45_STATE_BASE_ADDRESS_SurfaceStateBaseAddressModifyEnable_start 64 #define GFX4_STATE_BASE_ADDRESS_SurfaceStateBaseAddressModifyEnable_start 64 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_SurfaceStateBaseAddressModifyEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 128; case 120: return 128; case 110: return 128; case 90: return 128; case 80: return 128; case 75: return 64; case 70: return 64; case 60: return 64; case 50: return 64; case 45: return 64; case 40: return 64; default: unreachable("Invalid hardware generation"); } } /* STATE_BASE_ADDRESS::Surface State MOCS */ #define GFX125_STATE_BASE_ADDRESS_SurfaceStateMOCS_bits 7 #define GFX12_STATE_BASE_ADDRESS_SurfaceStateMOCS_bits 7 #define GFX11_STATE_BASE_ADDRESS_SurfaceStateMOCS_bits 7 #define GFX9_STATE_BASE_ADDRESS_SurfaceStateMOCS_bits 7 #define GFX8_STATE_BASE_ADDRESS_SurfaceStateMOCS_bits 7 #define GFX75_STATE_BASE_ADDRESS_SurfaceStateMOCS_bits 4 #define GFX7_STATE_BASE_ADDRESS_SurfaceStateMOCS_bits 4 #define GFX6_STATE_BASE_ADDRESS_SurfaceStateMOCS_bits 4 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_SurfaceStateMOCS_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 7; case 120: return 7; case 110: return 7; case 90: return 7; case 80: return 7; case 75: return 4; case 70: return 4; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_STATE_BASE_ADDRESS_SurfaceStateMOCS_start 132 #define GFX12_STATE_BASE_ADDRESS_SurfaceStateMOCS_start 132 #define GFX11_STATE_BASE_ADDRESS_SurfaceStateMOCS_start 132 #define GFX9_STATE_BASE_ADDRESS_SurfaceStateMOCS_start 132 #define GFX8_STATE_BASE_ADDRESS_SurfaceStateMOCS_start 132 #define GFX75_STATE_BASE_ADDRESS_SurfaceStateMOCS_start 72 #define GFX7_STATE_BASE_ADDRESS_SurfaceStateMOCS_start 72 #define GFX6_STATE_BASE_ADDRESS_SurfaceStateMOCS_start 72 static inline uint32_t ATTRIBUTE_PURE STATE_BASE_ADDRESS_SurfaceStateMOCS_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 132; case 120: return 132; case 110: return 132; case 90: return 132; case 80: return 132; case 75: return 72; case 70: return 72; case 60: return 72; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* STATE_PREFETCH */ #define GFX9_STATE_PREFETCH_length 2 #define GFX8_STATE_PREFETCH_length 2 #define GFX75_STATE_PREFETCH_length 2 #define GFX7_STATE_PREFETCH_length 2 #define GFX6_STATE_PREFETCH_length 2 static inline uint32_t ATTRIBUTE_PURE STATE_PREFETCH_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* STATE_PREFETCH::3D Command Opcode */ #define GFX9_STATE_PREFETCH_3DCommandOpcode_bits 3 #define GFX8_STATE_PREFETCH_3DCommandOpcode_bits 3 #define GFX75_STATE_PREFETCH_3DCommandOpcode_bits 3 #define GFX7_STATE_PREFETCH_3DCommandOpcode_bits 3 #define GFX6_STATE_PREFETCH_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE STATE_PREFETCH_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_STATE_PREFETCH_3DCommandOpcode_start 24 #define GFX8_STATE_PREFETCH_3DCommandOpcode_start 24 #define GFX75_STATE_PREFETCH_3DCommandOpcode_start 24 #define GFX7_STATE_PREFETCH_3DCommandOpcode_start 24 #define GFX6_STATE_PREFETCH_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE STATE_PREFETCH_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 24; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* STATE_PREFETCH::3D Command Sub Opcode */ #define GFX9_STATE_PREFETCH_3DCommandSubOpcode_bits 8 #define GFX8_STATE_PREFETCH_3DCommandSubOpcode_bits 8 #define GFX75_STATE_PREFETCH_3DCommandSubOpcode_bits 8 #define GFX7_STATE_PREFETCH_3DCommandSubOpcode_bits 8 #define GFX6_STATE_PREFETCH_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE STATE_PREFETCH_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_STATE_PREFETCH_3DCommandSubOpcode_start 16 #define GFX8_STATE_PREFETCH_3DCommandSubOpcode_start 16 #define GFX75_STATE_PREFETCH_3DCommandSubOpcode_start 16 #define GFX7_STATE_PREFETCH_3DCommandSubOpcode_start 16 #define GFX6_STATE_PREFETCH_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE STATE_PREFETCH_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 16; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* STATE_PREFETCH::Command SubType */ #define GFX9_STATE_PREFETCH_CommandSubType_bits 2 #define GFX8_STATE_PREFETCH_CommandSubType_bits 2 #define GFX75_STATE_PREFETCH_CommandSubType_bits 2 #define GFX7_STATE_PREFETCH_CommandSubType_bits 2 #define GFX6_STATE_PREFETCH_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE STATE_PREFETCH_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_STATE_PREFETCH_CommandSubType_start 27 #define GFX8_STATE_PREFETCH_CommandSubType_start 27 #define GFX75_STATE_PREFETCH_CommandSubType_start 27 #define GFX7_STATE_PREFETCH_CommandSubType_start 27 #define GFX6_STATE_PREFETCH_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE STATE_PREFETCH_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 27; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* STATE_PREFETCH::Command Type */ #define GFX9_STATE_PREFETCH_CommandType_bits 3 #define GFX8_STATE_PREFETCH_CommandType_bits 3 #define GFX75_STATE_PREFETCH_CommandType_bits 3 #define GFX7_STATE_PREFETCH_CommandType_bits 3 #define GFX6_STATE_PREFETCH_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE STATE_PREFETCH_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_STATE_PREFETCH_CommandType_start 29 #define GFX8_STATE_PREFETCH_CommandType_start 29 #define GFX75_STATE_PREFETCH_CommandType_start 29 #define GFX7_STATE_PREFETCH_CommandType_start 29 #define GFX6_STATE_PREFETCH_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE STATE_PREFETCH_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 29; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* STATE_PREFETCH::DWord Length */ #define GFX9_STATE_PREFETCH_DWordLength_bits 8 #define GFX8_STATE_PREFETCH_DWordLength_bits 8 #define GFX75_STATE_PREFETCH_DWordLength_bits 8 #define GFX7_STATE_PREFETCH_DWordLength_bits 8 #define GFX6_STATE_PREFETCH_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE STATE_PREFETCH_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_STATE_PREFETCH_DWordLength_start 0 #define GFX8_STATE_PREFETCH_DWordLength_start 0 #define GFX75_STATE_PREFETCH_DWordLength_start 0 #define GFX7_STATE_PREFETCH_DWordLength_start 0 #define GFX6_STATE_PREFETCH_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE STATE_PREFETCH_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* STATE_PREFETCH::Prefetch Count */ #define GFX9_STATE_PREFETCH_PrefetchCount_bits 3 #define GFX8_STATE_PREFETCH_PrefetchCount_bits 3 #define GFX75_STATE_PREFETCH_PrefetchCount_bits 3 #define GFX7_STATE_PREFETCH_PrefetchCount_bits 3 #define GFX6_STATE_PREFETCH_PrefetchCount_bits 3 static inline uint32_t ATTRIBUTE_PURE STATE_PREFETCH_PrefetchCount_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_STATE_PREFETCH_PrefetchCount_start 32 #define GFX8_STATE_PREFETCH_PrefetchCount_start 32 #define GFX75_STATE_PREFETCH_PrefetchCount_start 32 #define GFX7_STATE_PREFETCH_PrefetchCount_start 32 #define GFX6_STATE_PREFETCH_PrefetchCount_start 32 static inline uint32_t ATTRIBUTE_PURE STATE_PREFETCH_PrefetchCount_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 32; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* STATE_PREFETCH::Prefetch Pointer */ #define GFX9_STATE_PREFETCH_PrefetchPointer_bits 26 #define GFX8_STATE_PREFETCH_PrefetchPointer_bits 26 #define GFX75_STATE_PREFETCH_PrefetchPointer_bits 26 #define GFX7_STATE_PREFETCH_PrefetchPointer_bits 26 #define GFX6_STATE_PREFETCH_PrefetchPointer_bits 26 static inline uint32_t ATTRIBUTE_PURE STATE_PREFETCH_PrefetchPointer_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 26; case 80: return 26; case 75: return 26; case 70: return 26; case 60: return 26; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_STATE_PREFETCH_PrefetchPointer_start 38 #define GFX8_STATE_PREFETCH_PrefetchPointer_start 38 #define GFX75_STATE_PREFETCH_PrefetchPointer_start 38 #define GFX7_STATE_PREFETCH_PrefetchPointer_start 38 #define GFX6_STATE_PREFETCH_PrefetchPointer_start 38 static inline uint32_t ATTRIBUTE_PURE STATE_PREFETCH_PrefetchPointer_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 38; case 80: return 38; case 75: return 38; case 70: return 38; case 60: return 38; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* STATE_SIP */ #define GFX125_STATE_SIP_length 3 #define GFX12_STATE_SIP_length 3 #define GFX11_STATE_SIP_length 3 #define GFX9_STATE_SIP_length 3 #define GFX8_STATE_SIP_length 3 #define GFX75_STATE_SIP_length 2 #define GFX7_STATE_SIP_length 2 #define GFX6_STATE_SIP_length 2 #define GFX5_STATE_SIP_length 2 #define GFX45_STATE_SIP_length 2 #define GFX4_STATE_SIP_length 2 static inline uint32_t ATTRIBUTE_PURE STATE_SIP_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 2; case 45: return 2; case 40: return 2; default: unreachable("Invalid hardware generation"); } } /* STATE_SIP::3D Command Opcode */ #define GFX125_STATE_SIP_3DCommandOpcode_bits 3 #define GFX12_STATE_SIP_3DCommandOpcode_bits 3 #define GFX11_STATE_SIP_3DCommandOpcode_bits 3 #define GFX9_STATE_SIP_3DCommandOpcode_bits 3 #define GFX8_STATE_SIP_3DCommandOpcode_bits 3 #define GFX75_STATE_SIP_3DCommandOpcode_bits 3 #define GFX7_STATE_SIP_3DCommandOpcode_bits 3 #define GFX6_STATE_SIP_3DCommandOpcode_bits 3 #define GFX5_STATE_SIP_3DCommandOpcode_bits 3 #define GFX45_STATE_SIP_3DCommandOpcode_bits 3 #define GFX4_STATE_SIP_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE STATE_SIP_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX125_STATE_SIP_3DCommandOpcode_start 24 #define GFX12_STATE_SIP_3DCommandOpcode_start 24 #define GFX11_STATE_SIP_3DCommandOpcode_start 24 #define GFX9_STATE_SIP_3DCommandOpcode_start 24 #define GFX8_STATE_SIP_3DCommandOpcode_start 24 #define GFX75_STATE_SIP_3DCommandOpcode_start 24 #define GFX7_STATE_SIP_3DCommandOpcode_start 24 #define GFX6_STATE_SIP_3DCommandOpcode_start 24 #define GFX5_STATE_SIP_3DCommandOpcode_start 24 #define GFX45_STATE_SIP_3DCommandOpcode_start 24 #define GFX4_STATE_SIP_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE STATE_SIP_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 24; case 50: return 24; case 45: return 24; case 40: return 24; default: unreachable("Invalid hardware generation"); } } /* STATE_SIP::3D Command Sub Opcode */ #define GFX125_STATE_SIP_3DCommandSubOpcode_bits 8 #define GFX12_STATE_SIP_3DCommandSubOpcode_bits 8 #define GFX11_STATE_SIP_3DCommandSubOpcode_bits 8 #define GFX9_STATE_SIP_3DCommandSubOpcode_bits 8 #define GFX8_STATE_SIP_3DCommandSubOpcode_bits 8 #define GFX75_STATE_SIP_3DCommandSubOpcode_bits 8 #define GFX7_STATE_SIP_3DCommandSubOpcode_bits 8 #define GFX6_STATE_SIP_3DCommandSubOpcode_bits 8 #define GFX5_STATE_SIP_3DCommandSubOpcode_bits 8 #define GFX45_STATE_SIP_3DCommandSubOpcode_bits 8 #define GFX4_STATE_SIP_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE STATE_SIP_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 8; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } #define GFX125_STATE_SIP_3DCommandSubOpcode_start 16 #define GFX12_STATE_SIP_3DCommandSubOpcode_start 16 #define GFX11_STATE_SIP_3DCommandSubOpcode_start 16 #define GFX9_STATE_SIP_3DCommandSubOpcode_start 16 #define GFX8_STATE_SIP_3DCommandSubOpcode_start 16 #define GFX75_STATE_SIP_3DCommandSubOpcode_start 16 #define GFX7_STATE_SIP_3DCommandSubOpcode_start 16 #define GFX6_STATE_SIP_3DCommandSubOpcode_start 16 #define GFX5_STATE_SIP_3DCommandSubOpcode_start 16 #define GFX45_STATE_SIP_3DCommandSubOpcode_start 16 #define GFX4_STATE_SIP_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE STATE_SIP_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 16; case 50: return 16; case 45: return 16; case 40: return 16; default: unreachable("Invalid hardware generation"); } } /* STATE_SIP::Command SubType */ #define GFX125_STATE_SIP_CommandSubType_bits 2 #define GFX12_STATE_SIP_CommandSubType_bits 2 #define GFX11_STATE_SIP_CommandSubType_bits 2 #define GFX9_STATE_SIP_CommandSubType_bits 2 #define GFX8_STATE_SIP_CommandSubType_bits 2 #define GFX75_STATE_SIP_CommandSubType_bits 2 #define GFX7_STATE_SIP_CommandSubType_bits 2 #define GFX6_STATE_SIP_CommandSubType_bits 2 #define GFX5_STATE_SIP_CommandSubType_bits 2 #define GFX45_STATE_SIP_CommandSubType_bits 2 #define GFX4_STATE_SIP_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE STATE_SIP_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 2; case 45: return 2; case 40: return 2; default: unreachable("Invalid hardware generation"); } } #define GFX125_STATE_SIP_CommandSubType_start 27 #define GFX12_STATE_SIP_CommandSubType_start 27 #define GFX11_STATE_SIP_CommandSubType_start 27 #define GFX9_STATE_SIP_CommandSubType_start 27 #define GFX8_STATE_SIP_CommandSubType_start 27 #define GFX75_STATE_SIP_CommandSubType_start 27 #define GFX7_STATE_SIP_CommandSubType_start 27 #define GFX6_STATE_SIP_CommandSubType_start 27 #define GFX5_STATE_SIP_CommandSubType_start 27 #define GFX45_STATE_SIP_CommandSubType_start 27 #define GFX4_STATE_SIP_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE STATE_SIP_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 27; case 50: return 27; case 45: return 27; case 40: return 27; default: unreachable("Invalid hardware generation"); } } /* STATE_SIP::Command Type */ #define GFX125_STATE_SIP_CommandType_bits 3 #define GFX12_STATE_SIP_CommandType_bits 3 #define GFX11_STATE_SIP_CommandType_bits 3 #define GFX9_STATE_SIP_CommandType_bits 3 #define GFX8_STATE_SIP_CommandType_bits 3 #define GFX75_STATE_SIP_CommandType_bits 3 #define GFX7_STATE_SIP_CommandType_bits 3 #define GFX6_STATE_SIP_CommandType_bits 3 #define GFX5_STATE_SIP_CommandType_bits 3 #define GFX45_STATE_SIP_CommandType_bits 3 #define GFX4_STATE_SIP_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE STATE_SIP_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX125_STATE_SIP_CommandType_start 29 #define GFX12_STATE_SIP_CommandType_start 29 #define GFX11_STATE_SIP_CommandType_start 29 #define GFX9_STATE_SIP_CommandType_start 29 #define GFX8_STATE_SIP_CommandType_start 29 #define GFX75_STATE_SIP_CommandType_start 29 #define GFX7_STATE_SIP_CommandType_start 29 #define GFX6_STATE_SIP_CommandType_start 29 #define GFX5_STATE_SIP_CommandType_start 29 #define GFX45_STATE_SIP_CommandType_start 29 #define GFX4_STATE_SIP_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE STATE_SIP_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 29; case 50: return 29; case 45: return 29; case 40: return 29; default: unreachable("Invalid hardware generation"); } } /* STATE_SIP::DWord Length */ #define GFX125_STATE_SIP_DWordLength_bits 8 #define GFX12_STATE_SIP_DWordLength_bits 8 #define GFX11_STATE_SIP_DWordLength_bits 8 #define GFX9_STATE_SIP_DWordLength_bits 8 #define GFX8_STATE_SIP_DWordLength_bits 8 #define GFX75_STATE_SIP_DWordLength_bits 8 #define GFX7_STATE_SIP_DWordLength_bits 8 #define GFX6_STATE_SIP_DWordLength_bits 8 #define GFX5_STATE_SIP_DWordLength_bits 8 #define GFX45_STATE_SIP_DWordLength_bits 8 #define GFX4_STATE_SIP_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE STATE_SIP_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 8; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } #define GFX125_STATE_SIP_DWordLength_start 0 #define GFX12_STATE_SIP_DWordLength_start 0 #define GFX11_STATE_SIP_DWordLength_start 0 #define GFX9_STATE_SIP_DWordLength_start 0 #define GFX8_STATE_SIP_DWordLength_start 0 #define GFX75_STATE_SIP_DWordLength_start 0 #define GFX7_STATE_SIP_DWordLength_start 0 #define GFX6_STATE_SIP_DWordLength_start 0 #define GFX5_STATE_SIP_DWordLength_start 0 #define GFX45_STATE_SIP_DWordLength_start 0 #define GFX4_STATE_SIP_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE STATE_SIP_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* STATE_SIP::System Instruction Pointer */ #define GFX125_STATE_SIP_SystemInstructionPointer_bits 60 #define GFX12_STATE_SIP_SystemInstructionPointer_bits 60 #define GFX11_STATE_SIP_SystemInstructionPointer_bits 60 #define GFX9_STATE_SIP_SystemInstructionPointer_bits 60 #define GFX8_STATE_SIP_SystemInstructionPointer_bits 60 #define GFX75_STATE_SIP_SystemInstructionPointer_bits 28 #define GFX7_STATE_SIP_SystemInstructionPointer_bits 28 #define GFX6_STATE_SIP_SystemInstructionPointer_bits 28 #define GFX5_STATE_SIP_SystemInstructionPointer_bits 28 #define GFX45_STATE_SIP_SystemInstructionPointer_bits 28 #define GFX4_STATE_SIP_SystemInstructionPointer_bits 28 static inline uint32_t ATTRIBUTE_PURE STATE_SIP_SystemInstructionPointer_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 60; case 120: return 60; case 110: return 60; case 90: return 60; case 80: return 60; case 75: return 28; case 70: return 28; case 60: return 28; case 50: return 28; case 45: return 28; case 40: return 28; default: unreachable("Invalid hardware generation"); } } #define GFX125_STATE_SIP_SystemInstructionPointer_start 36 #define GFX12_STATE_SIP_SystemInstructionPointer_start 36 #define GFX11_STATE_SIP_SystemInstructionPointer_start 36 #define GFX9_STATE_SIP_SystemInstructionPointer_start 36 #define GFX8_STATE_SIP_SystemInstructionPointer_start 36 #define GFX75_STATE_SIP_SystemInstructionPointer_start 36 #define GFX7_STATE_SIP_SystemInstructionPointer_start 36 #define GFX6_STATE_SIP_SystemInstructionPointer_start 36 #define GFX5_STATE_SIP_SystemInstructionPointer_start 36 #define GFX45_STATE_SIP_SystemInstructionPointer_start 36 #define GFX4_STATE_SIP_SystemInstructionPointer_start 36 static inline uint32_t ATTRIBUTE_PURE STATE_SIP_SystemInstructionPointer_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 36; case 120: return 36; case 110: return 36; case 90: return 36; case 80: return 36; case 75: return 36; case 70: return 36; case 60: return 36; case 50: return 36; case 45: return 36; case 40: return 36; default: unreachable("Invalid hardware generation"); } } /* SWTESS_BASE_ADDRESS */ #define GFX8_SWTESS_BASE_ADDRESS_length 2 #define GFX75_SWTESS_BASE_ADDRESS_length 2 #define GFX7_SWTESS_BASE_ADDRESS_length 2 static inline uint32_t ATTRIBUTE_PURE SWTESS_BASE_ADDRESS_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SWTESS_BASE_ADDRESS::3D Command Opcode */ #define GFX8_SWTESS_BASE_ADDRESS_3DCommandOpcode_bits 3 #define GFX75_SWTESS_BASE_ADDRESS_3DCommandOpcode_bits 3 #define GFX7_SWTESS_BASE_ADDRESS_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE SWTESS_BASE_ADDRESS_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX8_SWTESS_BASE_ADDRESS_3DCommandOpcode_start 24 #define GFX75_SWTESS_BASE_ADDRESS_3DCommandOpcode_start 24 #define GFX7_SWTESS_BASE_ADDRESS_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE SWTESS_BASE_ADDRESS_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SWTESS_BASE_ADDRESS::3D Command Sub Opcode */ #define GFX8_SWTESS_BASE_ADDRESS_3DCommandSubOpcode_bits 8 #define GFX75_SWTESS_BASE_ADDRESS_3DCommandSubOpcode_bits 8 #define GFX7_SWTESS_BASE_ADDRESS_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE SWTESS_BASE_ADDRESS_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX8_SWTESS_BASE_ADDRESS_3DCommandSubOpcode_start 16 #define GFX75_SWTESS_BASE_ADDRESS_3DCommandSubOpcode_start 16 #define GFX7_SWTESS_BASE_ADDRESS_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE SWTESS_BASE_ADDRESS_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SWTESS_BASE_ADDRESS::Command SubType */ #define GFX8_SWTESS_BASE_ADDRESS_CommandSubType_bits 2 #define GFX75_SWTESS_BASE_ADDRESS_CommandSubType_bits 2 #define GFX7_SWTESS_BASE_ADDRESS_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE SWTESS_BASE_ADDRESS_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX8_SWTESS_BASE_ADDRESS_CommandSubType_start 27 #define GFX75_SWTESS_BASE_ADDRESS_CommandSubType_start 27 #define GFX7_SWTESS_BASE_ADDRESS_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE SWTESS_BASE_ADDRESS_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SWTESS_BASE_ADDRESS::Command Type */ #define GFX8_SWTESS_BASE_ADDRESS_CommandType_bits 3 #define GFX75_SWTESS_BASE_ADDRESS_CommandType_bits 3 #define GFX7_SWTESS_BASE_ADDRESS_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE SWTESS_BASE_ADDRESS_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX8_SWTESS_BASE_ADDRESS_CommandType_start 29 #define GFX75_SWTESS_BASE_ADDRESS_CommandType_start 29 #define GFX7_SWTESS_BASE_ADDRESS_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE SWTESS_BASE_ADDRESS_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 29; case 75: return 29; case 70: return 29; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SWTESS_BASE_ADDRESS::DWord Length */ #define GFX8_SWTESS_BASE_ADDRESS_DWordLength_bits 8 #define GFX75_SWTESS_BASE_ADDRESS_DWordLength_bits 8 #define GFX7_SWTESS_BASE_ADDRESS_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE SWTESS_BASE_ADDRESS_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX8_SWTESS_BASE_ADDRESS_DWordLength_start 0 #define GFX75_SWTESS_BASE_ADDRESS_DWordLength_start 0 #define GFX7_SWTESS_BASE_ADDRESS_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE SWTESS_BASE_ADDRESS_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SWTESS_BASE_ADDRESS::SW Tessellation Base Address */ #define GFX8_SWTESS_BASE_ADDRESS_SWTessellationBaseAddress_bits 36 #define GFX75_SWTESS_BASE_ADDRESS_SWTessellationBaseAddress_bits 20 #define GFX7_SWTESS_BASE_ADDRESS_SWTessellationBaseAddress_bits 20 static inline uint32_t ATTRIBUTE_PURE SWTESS_BASE_ADDRESS_SWTessellationBaseAddress_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 36; case 75: return 20; case 70: return 20; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX8_SWTESS_BASE_ADDRESS_SWTessellationBaseAddress_start 44 #define GFX75_SWTESS_BASE_ADDRESS_SWTessellationBaseAddress_start 44 #define GFX7_SWTESS_BASE_ADDRESS_SWTessellationBaseAddress_start 44 static inline uint32_t ATTRIBUTE_PURE SWTESS_BASE_ADDRESS_SWTessellationBaseAddress_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 44; case 75: return 44; case 70: return 44; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* SWTESS_BASE_ADDRESS::SW Tessellation MOCS */ #define GFX8_SWTESS_BASE_ADDRESS_SWTessellationMOCS_bits 4 #define GFX75_SWTESS_BASE_ADDRESS_SWTessellationMOCS_bits 4 #define GFX7_SWTESS_BASE_ADDRESS_SWTessellationMOCS_bits 4 static inline uint32_t ATTRIBUTE_PURE SWTESS_BASE_ADDRESS_SWTessellationMOCS_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 4; case 75: return 4; case 70: return 4; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX8_SWTESS_BASE_ADDRESS_SWTessellationMOCS_start 40 #define GFX75_SWTESS_BASE_ADDRESS_SWTessellationMOCS_start 40 #define GFX7_SWTESS_BASE_ADDRESS_SWTessellationMOCS_start 40 static inline uint32_t ATTRIBUTE_PURE SWTESS_BASE_ADDRESS_SWTessellationMOCS_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 40; case 75: return 40; case 70: return 40; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* TCCNTLREG */ #define GFX11_TCCNTLREG_length 1 static inline uint32_t ATTRIBUTE_PURE TCCNTLREG_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* TCCNTLREG::Color/Z Partial Write Merging Enable */ #define GFX11_TCCNTLREG_ColorZPartialWriteMergingEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE TCCNTLREG_ColorZPartialWriteMergingEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX11_TCCNTLREG_ColorZPartialWriteMergingEnable_start 1 static inline uint32_t ATTRIBUTE_PURE TCCNTLREG_ColorZPartialWriteMergingEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* TCCNTLREG::L3 Data Partial Write Merging Enable */ #define GFX11_TCCNTLREG_L3DataPartialWriteMergingEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE TCCNTLREG_L3DataPartialWriteMergingEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX11_TCCNTLREG_L3DataPartialWriteMergingEnable_start 2 static inline uint32_t ATTRIBUTE_PURE TCCNTLREG_L3DataPartialWriteMergingEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 2; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* TCCNTLREG::TC Disable */ #define GFX11_TCCNTLREG_TCDisable_bits 1 static inline uint32_t ATTRIBUTE_PURE TCCNTLREG_TCDisable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX11_TCCNTLREG_TCDisable_start 3 static inline uint32_t ATTRIBUTE_PURE TCCNTLREG_TCDisable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 3; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* TCCNTLREG::URB Partial Write Merging Enable */ #define GFX11_TCCNTLREG_URBPartialWriteMergingEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE TCCNTLREG_URBPartialWriteMergingEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 1; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX11_TCCNTLREG_URBPartialWriteMergingEnable_start 0 static inline uint32_t ATTRIBUTE_PURE TCCNTLREG_URBPartialWriteMergingEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* URB_FENCE */ #define GFX5_URB_FENCE_length 3 #define GFX45_URB_FENCE_length 3 #define GFX4_URB_FENCE_length 3 static inline uint32_t ATTRIBUTE_PURE URB_FENCE_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } /* URB_FENCE::3D Command Opcode */ #define GFX5_URB_FENCE_3DCommandOpcode_bits 3 #define GFX45_URB_FENCE_3DCommandOpcode_bits 3 #define GFX4_URB_FENCE_3DCommandOpcode_bits 3 static inline uint32_t ATTRIBUTE_PURE URB_FENCE_3DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX5_URB_FENCE_3DCommandOpcode_start 24 #define GFX45_URB_FENCE_3DCommandOpcode_start 24 #define GFX4_URB_FENCE_3DCommandOpcode_start 24 static inline uint32_t ATTRIBUTE_PURE URB_FENCE_3DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 24; case 45: return 24; case 40: return 24; default: unreachable("Invalid hardware generation"); } } /* URB_FENCE::3D Command Sub Opcode */ #define GFX5_URB_FENCE_3DCommandSubOpcode_bits 8 #define GFX45_URB_FENCE_3DCommandSubOpcode_bits 8 #define GFX4_URB_FENCE_3DCommandSubOpcode_bits 8 static inline uint32_t ATTRIBUTE_PURE URB_FENCE_3DCommandSubOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 8; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } #define GFX5_URB_FENCE_3DCommandSubOpcode_start 16 #define GFX45_URB_FENCE_3DCommandSubOpcode_start 16 #define GFX4_URB_FENCE_3DCommandSubOpcode_start 16 static inline uint32_t ATTRIBUTE_PURE URB_FENCE_3DCommandSubOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 16; case 45: return 16; case 40: return 16; default: unreachable("Invalid hardware generation"); } } /* URB_FENCE::CLIP Fence */ #define GFX5_URB_FENCE_CLIPFence_bits 10 #define GFX45_URB_FENCE_CLIPFence_bits 10 #define GFX4_URB_FENCE_CLIPFence_bits 10 static inline uint32_t ATTRIBUTE_PURE URB_FENCE_CLIPFence_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 10; case 45: return 10; case 40: return 10; default: unreachable("Invalid hardware generation"); } } #define GFX5_URB_FENCE_CLIPFence_start 52 #define GFX45_URB_FENCE_CLIPFence_start 52 #define GFX4_URB_FENCE_CLIPFence_start 52 static inline uint32_t ATTRIBUTE_PURE URB_FENCE_CLIPFence_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 52; case 45: return 52; case 40: return 52; default: unreachable("Invalid hardware generation"); } } /* URB_FENCE::CLIP Unit URB Reallocation Request */ #define GFX5_URB_FENCE_CLIPUnitURBReallocationRequest_bits 1 #define GFX45_URB_FENCE_CLIPUnitURBReallocationRequest_bits 1 #define GFX4_URB_FENCE_CLIPUnitURBReallocationRequest_bits 1 static inline uint32_t ATTRIBUTE_PURE URB_FENCE_CLIPUnitURBReallocationRequest_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_URB_FENCE_CLIPUnitURBReallocationRequest_start 10 #define GFX45_URB_FENCE_CLIPUnitURBReallocationRequest_start 10 #define GFX4_URB_FENCE_CLIPUnitURBReallocationRequest_start 10 static inline uint32_t ATTRIBUTE_PURE URB_FENCE_CLIPUnitURBReallocationRequest_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 10; case 45: return 10; case 40: return 10; default: unreachable("Invalid hardware generation"); } } /* URB_FENCE::CS Fence */ #define GFX5_URB_FENCE_CSFence_bits 11 #define GFX45_URB_FENCE_CSFence_bits 11 #define GFX4_URB_FENCE_CSFence_bits 11 static inline uint32_t ATTRIBUTE_PURE URB_FENCE_CSFence_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 11; case 45: return 11; case 40: return 11; default: unreachable("Invalid hardware generation"); } } #define GFX5_URB_FENCE_CSFence_start 84 #define GFX45_URB_FENCE_CSFence_start 84 #define GFX4_URB_FENCE_CSFence_start 84 static inline uint32_t ATTRIBUTE_PURE URB_FENCE_CSFence_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 84; case 45: return 84; case 40: return 84; default: unreachable("Invalid hardware generation"); } } /* URB_FENCE::CS Unit URB Reallocation Request */ #define GFX5_URB_FENCE_CSUnitURBReallocationRequest_bits 1 #define GFX45_URB_FENCE_CSUnitURBReallocationRequest_bits 1 #define GFX4_URB_FENCE_CSUnitURBReallocationRequest_bits 1 static inline uint32_t ATTRIBUTE_PURE URB_FENCE_CSUnitURBReallocationRequest_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_URB_FENCE_CSUnitURBReallocationRequest_start 13 #define GFX45_URB_FENCE_CSUnitURBReallocationRequest_start 13 #define GFX4_URB_FENCE_CSUnitURBReallocationRequest_start 13 static inline uint32_t ATTRIBUTE_PURE URB_FENCE_CSUnitURBReallocationRequest_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 13; case 45: return 13; case 40: return 13; default: unreachable("Invalid hardware generation"); } } /* URB_FENCE::Command SubType */ #define GFX5_URB_FENCE_CommandSubType_bits 2 #define GFX45_URB_FENCE_CommandSubType_bits 2 #define GFX4_URB_FENCE_CommandSubType_bits 2 static inline uint32_t ATTRIBUTE_PURE URB_FENCE_CommandSubType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 2; case 45: return 2; case 40: return 2; default: unreachable("Invalid hardware generation"); } } #define GFX5_URB_FENCE_CommandSubType_start 27 #define GFX45_URB_FENCE_CommandSubType_start 27 #define GFX4_URB_FENCE_CommandSubType_start 27 static inline uint32_t ATTRIBUTE_PURE URB_FENCE_CommandSubType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 27; case 45: return 27; case 40: return 27; default: unreachable("Invalid hardware generation"); } } /* URB_FENCE::Command Type */ #define GFX5_URB_FENCE_CommandType_bits 3 #define GFX45_URB_FENCE_CommandType_bits 3 #define GFX4_URB_FENCE_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE URB_FENCE_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX5_URB_FENCE_CommandType_start 29 #define GFX45_URB_FENCE_CommandType_start 29 #define GFX4_URB_FENCE_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE URB_FENCE_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 29; case 45: return 29; case 40: return 29; default: unreachable("Invalid hardware generation"); } } /* URB_FENCE::DWord Length */ #define GFX5_URB_FENCE_DWordLength_bits 8 #define GFX45_URB_FENCE_DWordLength_bits 8 #define GFX4_URB_FENCE_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE URB_FENCE_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 8; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } #define GFX5_URB_FENCE_DWordLength_start 0 #define GFX45_URB_FENCE_DWordLength_start 0 #define GFX4_URB_FENCE_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE URB_FENCE_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* URB_FENCE::GS Fence */ #define GFX5_URB_FENCE_GSFence_bits 10 #define GFX45_URB_FENCE_GSFence_bits 10 #define GFX4_URB_FENCE_GSFence_bits 10 static inline uint32_t ATTRIBUTE_PURE URB_FENCE_GSFence_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 10; case 45: return 10; case 40: return 10; default: unreachable("Invalid hardware generation"); } } #define GFX5_URB_FENCE_GSFence_start 42 #define GFX45_URB_FENCE_GSFence_start 42 #define GFX4_URB_FENCE_GSFence_start 42 static inline uint32_t ATTRIBUTE_PURE URB_FENCE_GSFence_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 42; case 45: return 42; case 40: return 42; default: unreachable("Invalid hardware generation"); } } /* URB_FENCE::GS Unit URB Reallocation Request */ #define GFX5_URB_FENCE_GSUnitURBReallocationRequest_bits 1 #define GFX45_URB_FENCE_GSUnitURBReallocationRequest_bits 1 #define GFX4_URB_FENCE_GSUnitURBReallocationRequest_bits 1 static inline uint32_t ATTRIBUTE_PURE URB_FENCE_GSUnitURBReallocationRequest_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_URB_FENCE_GSUnitURBReallocationRequest_start 9 #define GFX45_URB_FENCE_GSUnitURBReallocationRequest_start 9 #define GFX4_URB_FENCE_GSUnitURBReallocationRequest_start 9 static inline uint32_t ATTRIBUTE_PURE URB_FENCE_GSUnitURBReallocationRequest_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 9; case 45: return 9; case 40: return 9; default: unreachable("Invalid hardware generation"); } } /* URB_FENCE::SF Fence */ #define GFX5_URB_FENCE_SFFence_bits 10 #define GFX45_URB_FENCE_SFFence_bits 10 #define GFX4_URB_FENCE_SFFence_bits 10 static inline uint32_t ATTRIBUTE_PURE URB_FENCE_SFFence_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 10; case 45: return 10; case 40: return 10; default: unreachable("Invalid hardware generation"); } } #define GFX5_URB_FENCE_SFFence_start 64 #define GFX45_URB_FENCE_SFFence_start 64 #define GFX4_URB_FENCE_SFFence_start 64 static inline uint32_t ATTRIBUTE_PURE URB_FENCE_SFFence_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 64; case 45: return 64; case 40: return 64; default: unreachable("Invalid hardware generation"); } } /* URB_FENCE::SF Unit URB Reallocation Request */ #define GFX5_URB_FENCE_SFUnitURBReallocationRequest_bits 1 #define GFX45_URB_FENCE_SFUnitURBReallocationRequest_bits 1 #define GFX4_URB_FENCE_SFUnitURBReallocationRequest_bits 1 static inline uint32_t ATTRIBUTE_PURE URB_FENCE_SFUnitURBReallocationRequest_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_URB_FENCE_SFUnitURBReallocationRequest_start 11 #define GFX45_URB_FENCE_SFUnitURBReallocationRequest_start 11 #define GFX4_URB_FENCE_SFUnitURBReallocationRequest_start 11 static inline uint32_t ATTRIBUTE_PURE URB_FENCE_SFUnitURBReallocationRequest_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 11; case 45: return 11; case 40: return 11; default: unreachable("Invalid hardware generation"); } } /* URB_FENCE::VFE Fence */ #define GFX5_URB_FENCE_VFEFence_bits 10 #define GFX45_URB_FENCE_VFEFence_bits 10 #define GFX4_URB_FENCE_VFEFence_bits 10 static inline uint32_t ATTRIBUTE_PURE URB_FENCE_VFEFence_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 10; case 45: return 10; case 40: return 10; default: unreachable("Invalid hardware generation"); } } #define GFX5_URB_FENCE_VFEFence_start 74 #define GFX45_URB_FENCE_VFEFence_start 74 #define GFX4_URB_FENCE_VFEFence_start 74 static inline uint32_t ATTRIBUTE_PURE URB_FENCE_VFEFence_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 74; case 45: return 74; case 40: return 74; default: unreachable("Invalid hardware generation"); } } /* URB_FENCE::VFE Unit URB Reallocation Request */ #define GFX5_URB_FENCE_VFEUnitURBReallocationRequest_bits 1 #define GFX45_URB_FENCE_VFEUnitURBReallocationRequest_bits 1 #define GFX4_URB_FENCE_VFEUnitURBReallocationRequest_bits 1 static inline uint32_t ATTRIBUTE_PURE URB_FENCE_VFEUnitURBReallocationRequest_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_URB_FENCE_VFEUnitURBReallocationRequest_start 12 #define GFX45_URB_FENCE_VFEUnitURBReallocationRequest_start 12 #define GFX4_URB_FENCE_VFEUnitURBReallocationRequest_start 12 static inline uint32_t ATTRIBUTE_PURE URB_FENCE_VFEUnitURBReallocationRequest_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 12; case 45: return 12; case 40: return 12; default: unreachable("Invalid hardware generation"); } } /* URB_FENCE::VS Fence */ #define GFX5_URB_FENCE_VSFence_bits 10 #define GFX45_URB_FENCE_VSFence_bits 10 #define GFX4_URB_FENCE_VSFence_bits 10 static inline uint32_t ATTRIBUTE_PURE URB_FENCE_VSFence_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 10; case 45: return 10; case 40: return 10; default: unreachable("Invalid hardware generation"); } } #define GFX5_URB_FENCE_VSFence_start 32 #define GFX45_URB_FENCE_VSFence_start 32 #define GFX4_URB_FENCE_VSFence_start 32 static inline uint32_t ATTRIBUTE_PURE URB_FENCE_VSFence_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 32; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } /* URB_FENCE::VS Unit URB Reallocation Request */ #define GFX5_URB_FENCE_VSUnitURBReallocationRequest_bits 1 #define GFX45_URB_FENCE_VSUnitURBReallocationRequest_bits 1 #define GFX4_URB_FENCE_VSUnitURBReallocationRequest_bits 1 static inline uint32_t ATTRIBUTE_PURE URB_FENCE_VSUnitURBReallocationRequest_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_URB_FENCE_VSUnitURBReallocationRequest_start 8 #define GFX45_URB_FENCE_VSUnitURBReallocationRequest_start 8 #define GFX4_URB_FENCE_VSUnitURBReallocationRequest_start 8 static inline uint32_t ATTRIBUTE_PURE URB_FENCE_VSUnitURBReallocationRequest_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 8; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } /* VCS2_RING_BUFFER_CTL */ #define GFX9_VCS2_RING_BUFFER_CTL_length 1 #define GFX8_VCS2_RING_BUFFER_CTL_length 1 static inline uint32_t ATTRIBUTE_PURE VCS2_RING_BUFFER_CTL_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VCS2_RING_BUFFER_CTL::Automatic Report Head Pointer */ #define GFX9_VCS2_RING_BUFFER_CTL_AutomaticReportHeadPointer_bits 2 #define GFX8_VCS2_RING_BUFFER_CTL_AutomaticReportHeadPointer_bits 2 static inline uint32_t ATTRIBUTE_PURE VCS2_RING_BUFFER_CTL_AutomaticReportHeadPointer_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 2; case 80: return 2; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_VCS2_RING_BUFFER_CTL_AutomaticReportHeadPointer_start 1 #define GFX8_VCS2_RING_BUFFER_CTL_AutomaticReportHeadPointer_start 1 static inline uint32_t ATTRIBUTE_PURE VCS2_RING_BUFFER_CTL_AutomaticReportHeadPointer_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VCS2_RING_BUFFER_CTL::Buffer Length (in pages - 1) */ #define GFX9_VCS2_RING_BUFFER_CTL_BufferLengthinpages1_bits 9 #define GFX8_VCS2_RING_BUFFER_CTL_BufferLengthinpages1_bits 9 static inline uint32_t ATTRIBUTE_PURE VCS2_RING_BUFFER_CTL_BufferLengthinpages1_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 9; case 80: return 9; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_VCS2_RING_BUFFER_CTL_BufferLengthinpages1_start 12 #define GFX8_VCS2_RING_BUFFER_CTL_BufferLengthinpages1_start 12 static inline uint32_t ATTRIBUTE_PURE VCS2_RING_BUFFER_CTL_BufferLengthinpages1_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 12; case 80: return 12; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VCS2_RING_BUFFER_CTL::Disable Register Accesses */ #define GFX9_VCS2_RING_BUFFER_CTL_DisableRegisterAccesses_bits 1 #define GFX8_VCS2_RING_BUFFER_CTL_DisableRegisterAccesses_bits 1 static inline uint32_t ATTRIBUTE_PURE VCS2_RING_BUFFER_CTL_DisableRegisterAccesses_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_VCS2_RING_BUFFER_CTL_DisableRegisterAccesses_start 8 #define GFX8_VCS2_RING_BUFFER_CTL_DisableRegisterAccesses_start 8 static inline uint32_t ATTRIBUTE_PURE VCS2_RING_BUFFER_CTL_DisableRegisterAccesses_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 8; case 80: return 8; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VCS2_RING_BUFFER_CTL::RBWait */ #define GFX9_VCS2_RING_BUFFER_CTL_RBWait_bits 1 #define GFX8_VCS2_RING_BUFFER_CTL_RBWait_bits 1 static inline uint32_t ATTRIBUTE_PURE VCS2_RING_BUFFER_CTL_RBWait_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_VCS2_RING_BUFFER_CTL_RBWait_start 11 #define GFX8_VCS2_RING_BUFFER_CTL_RBWait_start 11 static inline uint32_t ATTRIBUTE_PURE VCS2_RING_BUFFER_CTL_RBWait_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 11; case 80: return 11; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VCS2_RING_BUFFER_CTL::Ring Buffer Enable */ #define GFX9_VCS2_RING_BUFFER_CTL_RingBufferEnable_bits 1 #define GFX8_VCS2_RING_BUFFER_CTL_RingBufferEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE VCS2_RING_BUFFER_CTL_RingBufferEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_VCS2_RING_BUFFER_CTL_RingBufferEnable_start 0 #define GFX8_VCS2_RING_BUFFER_CTL_RingBufferEnable_start 0 static inline uint32_t ATTRIBUTE_PURE VCS2_RING_BUFFER_CTL_RingBufferEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VCS2_RING_BUFFER_CTL::Semaphore Wait */ #define GFX9_VCS2_RING_BUFFER_CTL_SemaphoreWait_bits 1 #define GFX8_VCS2_RING_BUFFER_CTL_SemaphoreWait_bits 1 static inline uint32_t ATTRIBUTE_PURE VCS2_RING_BUFFER_CTL_SemaphoreWait_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_VCS2_RING_BUFFER_CTL_SemaphoreWait_start 10 #define GFX8_VCS2_RING_BUFFER_CTL_SemaphoreWait_start 10 static inline uint32_t ATTRIBUTE_PURE VCS2_RING_BUFFER_CTL_SemaphoreWait_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 10; case 80: return 10; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VCS_ACTHD_UDW */ #define GFX9_VCS_ACTHD_UDW_length 1 #define GFX8_VCS_ACTHD_UDW_length 1 static inline uint32_t ATTRIBUTE_PURE VCS_ACTHD_UDW_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VCS_ACTHD_UDW::Head Pointer Upper DWORD */ #define GFX9_VCS_ACTHD_UDW_HeadPointerUpperDWORD_bits 16 #define GFX8_VCS_ACTHD_UDW_HeadPointerUpperDWORD_bits 16 static inline uint32_t ATTRIBUTE_PURE VCS_ACTHD_UDW_HeadPointerUpperDWORD_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 16; case 80: return 16; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_VCS_ACTHD_UDW_HeadPointerUpperDWORD_start 0 #define GFX8_VCS_ACTHD_UDW_HeadPointerUpperDWORD_start 0 static inline uint32_t ATTRIBUTE_PURE VCS_ACTHD_UDW_HeadPointerUpperDWORD_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VCS_FAULT_REG */ #define GFX75_VCS_FAULT_REG_length 1 #define GFX7_VCS_FAULT_REG_length 1 #define GFX6_VCS_FAULT_REG_length 1 static inline uint32_t ATTRIBUTE_PURE VCS_FAULT_REG_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VCS_FAULT_REG::Fault Type */ #define GFX75_VCS_FAULT_REG_FaultType_bits 2 #define GFX7_VCS_FAULT_REG_FaultType_bits 2 #define GFX6_VCS_FAULT_REG_FaultType_bits 2 static inline uint32_t ATTRIBUTE_PURE VCS_FAULT_REG_FaultType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_VCS_FAULT_REG_FaultType_start 1 #define GFX7_VCS_FAULT_REG_FaultType_start 1 #define GFX6_VCS_FAULT_REG_FaultType_start 1 static inline uint32_t ATTRIBUTE_PURE VCS_FAULT_REG_FaultType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VCS_FAULT_REG::GTTSEL */ #define GFX75_VCS_FAULT_REG_GTTSEL_bits 1 #define GFX7_VCS_FAULT_REG_GTTSEL_bits 1 #define GFX6_VCS_FAULT_REG_GTTSEL_bits 1 static inline uint32_t ATTRIBUTE_PURE VCS_FAULT_REG_GTTSEL_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_VCS_FAULT_REG_GTTSEL_start 11 #define GFX7_VCS_FAULT_REG_GTTSEL_start 11 #define GFX6_VCS_FAULT_REG_GTTSEL_start 11 static inline uint32_t ATTRIBUTE_PURE VCS_FAULT_REG_GTTSEL_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 11; case 70: return 11; case 60: return 11; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VCS_FAULT_REG::SRCID of Fault */ #define GFX75_VCS_FAULT_REG_SRCIDofFault_bits 8 #define GFX7_VCS_FAULT_REG_SRCIDofFault_bits 8 #define GFX6_VCS_FAULT_REG_SRCIDofFault_bits 8 static inline uint32_t ATTRIBUTE_PURE VCS_FAULT_REG_SRCIDofFault_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_VCS_FAULT_REG_SRCIDofFault_start 3 #define GFX7_VCS_FAULT_REG_SRCIDofFault_start 3 #define GFX6_VCS_FAULT_REG_SRCIDofFault_start 3 static inline uint32_t ATTRIBUTE_PURE VCS_FAULT_REG_SRCIDofFault_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VCS_FAULT_REG::Valid Bit */ #define GFX75_VCS_FAULT_REG_ValidBit_bits 1 #define GFX7_VCS_FAULT_REG_ValidBit_bits 1 #define GFX6_VCS_FAULT_REG_ValidBit_bits 1 static inline uint32_t ATTRIBUTE_PURE VCS_FAULT_REG_ValidBit_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_VCS_FAULT_REG_ValidBit_start 0 #define GFX7_VCS_FAULT_REG_ValidBit_start 0 #define GFX6_VCS_FAULT_REG_ValidBit_start 0 static inline uint32_t ATTRIBUTE_PURE VCS_FAULT_REG_ValidBit_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VCS_FAULT_REG::Virtual Address of Fault */ #define GFX75_VCS_FAULT_REG_VirtualAddressofFault_bits 20 #define GFX7_VCS_FAULT_REG_VirtualAddressofFault_bits 20 #define GFX6_VCS_FAULT_REG_VirtualAddressofFault_bits 20 static inline uint32_t ATTRIBUTE_PURE VCS_FAULT_REG_VirtualAddressofFault_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 20; case 70: return 20; case 60: return 20; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_VCS_FAULT_REG_VirtualAddressofFault_start 12 #define GFX7_VCS_FAULT_REG_VirtualAddressofFault_start 12 #define GFX6_VCS_FAULT_REG_VirtualAddressofFault_start 12 static inline uint32_t ATTRIBUTE_PURE VCS_FAULT_REG_VirtualAddressofFault_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 12; case 70: return 12; case 60: return 12; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VCS_INSTDONE */ #define GFX125_VCS_INSTDONE_length 1 #define GFX12_VCS_INSTDONE_length 1 #define GFX11_VCS_INSTDONE_length 1 #define GFX9_VCS_INSTDONE_length 1 #define GFX8_VCS_INSTDONE_length 1 #define GFX75_VCS_INSTDONE_length 1 #define GFX7_VCS_INSTDONE_length 1 #define GFX6_VCS_INSTDONE_length 1 static inline uint32_t ATTRIBUTE_PURE VCS_INSTDONE_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VCS_INSTDONE::BSP Done */ #define GFX125_VCS_INSTDONE_BSPDone_bits 1 #define GFX12_VCS_INSTDONE_BSPDone_bits 1 #define GFX11_VCS_INSTDONE_BSPDone_bits 1 #define GFX9_VCS_INSTDONE_BSPDone_bits 1 #define GFX8_VCS_INSTDONE_BSPDone_bits 1 #define GFX75_VCS_INSTDONE_BSPDone_bits 1 #define GFX7_VCS_INSTDONE_BSPDone_bits 1 #define GFX6_VCS_INSTDONE_BSPDone_bits 1 static inline uint32_t ATTRIBUTE_PURE VCS_INSTDONE_BSPDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_VCS_INSTDONE_BSPDone_start 6 #define GFX12_VCS_INSTDONE_BSPDone_start 6 #define GFX11_VCS_INSTDONE_BSPDone_start 6 #define GFX9_VCS_INSTDONE_BSPDone_start 6 #define GFX8_VCS_INSTDONE_BSPDone_start 6 #define GFX75_VCS_INSTDONE_BSPDone_start 6 #define GFX7_VCS_INSTDONE_BSPDone_start 6 #define GFX6_VCS_INSTDONE_BSPDone_start 6 static inline uint32_t ATTRIBUTE_PURE VCS_INSTDONE_BSPDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 6; case 60: return 6; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VCS_INSTDONE::GAC Done */ #define GFX125_VCS_INSTDONE_GACDone_bits 1 #define GFX12_VCS_INSTDONE_GACDone_bits 1 #define GFX11_VCS_INSTDONE_GACDone_bits 1 #define GFX9_VCS_INSTDONE_GACDone_bits 1 #define GFX8_VCS_INSTDONE_GACDone_bits 1 #define GFX75_VCS_INSTDONE_GACDone_bits 1 #define GFX7_VCS_INSTDONE_GACDone_bits 1 #define GFX6_VCS_INSTDONE_GACDone_bits 1 static inline uint32_t ATTRIBUTE_PURE VCS_INSTDONE_GACDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_VCS_INSTDONE_GACDone_start 31 #define GFX12_VCS_INSTDONE_GACDone_start 31 #define GFX11_VCS_INSTDONE_GACDone_start 31 #define GFX9_VCS_INSTDONE_GACDone_start 31 #define GFX8_VCS_INSTDONE_GACDone_start 31 #define GFX75_VCS_INSTDONE_GACDone_start 31 #define GFX7_VCS_INSTDONE_GACDone_start 31 #define GFX6_VCS_INSTDONE_GACDone_start 31 static inline uint32_t ATTRIBUTE_PURE VCS_INSTDONE_GACDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 31; case 120: return 31; case 110: return 31; case 90: return 31; case 80: return 31; case 75: return 31; case 70: return 31; case 60: return 31; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VCS_INSTDONE::JPG Done */ #define GFX125_VCS_INSTDONE_JPGDone_bits 1 #define GFX12_VCS_INSTDONE_JPGDone_bits 1 #define GFX11_VCS_INSTDONE_JPGDone_bits 1 #define GFX9_VCS_INSTDONE_JPGDone_bits 1 #define GFX8_VCS_INSTDONE_JPGDone_bits 1 #define GFX75_VCS_INSTDONE_JPGDone_bits 1 #define GFX7_VCS_INSTDONE_JPGDone_bits 1 #define GFX6_VCS_INSTDONE_JPGDone_bits 1 static inline uint32_t ATTRIBUTE_PURE VCS_INSTDONE_JPGDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_VCS_INSTDONE_JPGDone_start 21 #define GFX12_VCS_INSTDONE_JPGDone_start 21 #define GFX11_VCS_INSTDONE_JPGDone_start 21 #define GFX9_VCS_INSTDONE_JPGDone_start 21 #define GFX8_VCS_INSTDONE_JPGDone_start 21 #define GFX75_VCS_INSTDONE_JPGDone_start 21 #define GFX7_VCS_INSTDONE_JPGDone_start 21 #define GFX6_VCS_INSTDONE_JPGDone_start 21 static inline uint32_t ATTRIBUTE_PURE VCS_INSTDONE_JPGDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 21; case 120: return 21; case 110: return 21; case 90: return 21; case 80: return 21; case 75: return 21; case 70: return 21; case 60: return 21; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VCS_INSTDONE::MPC Done */ #define GFX125_VCS_INSTDONE_MPCDone_bits 1 #define GFX12_VCS_INSTDONE_MPCDone_bits 1 #define GFX11_VCS_INSTDONE_MPCDone_bits 1 #define GFX9_VCS_INSTDONE_MPCDone_bits 1 #define GFX8_VCS_INSTDONE_MPCDone_bits 1 #define GFX75_VCS_INSTDONE_MPCDone_bits 1 #define GFX7_VCS_INSTDONE_MPCDone_bits 1 #define GFX6_VCS_INSTDONE_MPCDone_bits 1 static inline uint32_t ATTRIBUTE_PURE VCS_INSTDONE_MPCDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_VCS_INSTDONE_MPCDone_start 4 #define GFX12_VCS_INSTDONE_MPCDone_start 4 #define GFX11_VCS_INSTDONE_MPCDone_start 4 #define GFX9_VCS_INSTDONE_MPCDone_start 4 #define GFX8_VCS_INSTDONE_MPCDone_start 4 #define GFX75_VCS_INSTDONE_MPCDone_start 4 #define GFX7_VCS_INSTDONE_MPCDone_start 4 #define GFX6_VCS_INSTDONE_MPCDone_start 4 static inline uint32_t ATTRIBUTE_PURE VCS_INSTDONE_MPCDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 4; case 70: return 4; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VCS_INSTDONE::QRC Done */ #define GFX125_VCS_INSTDONE_QRCDone_bits 1 #define GFX12_VCS_INSTDONE_QRCDone_bits 1 #define GFX11_VCS_INSTDONE_QRCDone_bits 1 #define GFX9_VCS_INSTDONE_QRCDone_bits 1 #define GFX8_VCS_INSTDONE_QRCDone_bits 1 #define GFX75_VCS_INSTDONE_QRCDone_bits 1 #define GFX7_VCS_INSTDONE_QRCDone_bits 1 #define GFX6_VCS_INSTDONE_QRCDone_bits 1 static inline uint32_t ATTRIBUTE_PURE VCS_INSTDONE_QRCDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_VCS_INSTDONE_QRCDone_start 2 #define GFX12_VCS_INSTDONE_QRCDone_start 2 #define GFX11_VCS_INSTDONE_QRCDone_start 2 #define GFX9_VCS_INSTDONE_QRCDone_start 2 #define GFX8_VCS_INSTDONE_QRCDone_start 2 #define GFX75_VCS_INSTDONE_QRCDone_start 2 #define GFX7_VCS_INSTDONE_QRCDone_start 2 #define GFX6_VCS_INSTDONE_QRCDone_start 2 static inline uint32_t ATTRIBUTE_PURE VCS_INSTDONE_QRCDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VCS_INSTDONE::Reserved */ #define GFX125_VCS_INSTDONE_Reserved_bits 1 #define GFX12_VCS_INSTDONE_Reserved_bits 1 #define GFX11_VCS_INSTDONE_Reserved_bits 1 #define GFX9_VCS_INSTDONE_Reserved_bits 1 #define GFX8_VCS_INSTDONE_Reserved_bits 1 #define GFX75_VCS_INSTDONE_Reserved_bits 1 static inline uint32_t ATTRIBUTE_PURE VCS_INSTDONE_Reserved_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_VCS_INSTDONE_Reserved_start 29 #define GFX12_VCS_INSTDONE_Reserved_start 29 #define GFX11_VCS_INSTDONE_Reserved_start 29 #define GFX9_VCS_INSTDONE_Reserved_start 29 #define GFX8_VCS_INSTDONE_Reserved_start 29 #define GFX75_VCS_INSTDONE_Reserved_start 29 static inline uint32_t ATTRIBUTE_PURE VCS_INSTDONE_Reserved_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 29; case 120: return 29; case 110: return 29; case 90: return 29; case 80: return 29; case 75: return 29; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VCS_INSTDONE::Ring Enable */ #define GFX125_VCS_INSTDONE_RingEnable_bits 1 #define GFX12_VCS_INSTDONE_RingEnable_bits 1 #define GFX11_VCS_INSTDONE_RingEnable_bits 1 #define GFX9_VCS_INSTDONE_RingEnable_bits 1 #define GFX8_VCS_INSTDONE_RingEnable_bits 1 #define GFX75_VCS_INSTDONE_RingEnable_bits 1 #define GFX7_VCS_INSTDONE_RingEnable_bits 1 #define GFX6_VCS_INSTDONE_RingEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE VCS_INSTDONE_RingEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_VCS_INSTDONE_RingEnable_start 0 #define GFX12_VCS_INSTDONE_RingEnable_start 0 #define GFX11_VCS_INSTDONE_RingEnable_start 0 #define GFX9_VCS_INSTDONE_RingEnable_start 0 #define GFX8_VCS_INSTDONE_RingEnable_start 0 #define GFX75_VCS_INSTDONE_RingEnable_start 0 #define GFX7_VCS_INSTDONE_RingEnable_start 0 #define GFX6_VCS_INSTDONE_RingEnable_start 0 static inline uint32_t ATTRIBUTE_PURE VCS_INSTDONE_RingEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VCS_INSTDONE::SEC Done */ #define GFX125_VCS_INSTDONE_SECDone_bits 1 #define GFX12_VCS_INSTDONE_SECDone_bits 1 #define GFX11_VCS_INSTDONE_SECDone_bits 1 #define GFX9_VCS_INSTDONE_SECDone_bits 1 #define GFX8_VCS_INSTDONE_SECDone_bits 1 #define GFX75_VCS_INSTDONE_SECDone_bits 1 #define GFX7_VCS_INSTDONE_SECDone_bits 1 #define GFX6_VCS_INSTDONE_SECDone_bits 1 static inline uint32_t ATTRIBUTE_PURE VCS_INSTDONE_SECDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_VCS_INSTDONE_SECDone_start 3 #define GFX12_VCS_INSTDONE_SECDone_start 3 #define GFX11_VCS_INSTDONE_SECDone_start 3 #define GFX9_VCS_INSTDONE_SECDone_start 3 #define GFX8_VCS_INSTDONE_SECDone_start 3 #define GFX75_VCS_INSTDONE_SECDone_start 3 #define GFX7_VCS_INSTDONE_SECDone_start 3 #define GFX6_VCS_INSTDONE_SECDone_start 3 static inline uint32_t ATTRIBUTE_PURE VCS_INSTDONE_SECDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VCS_INSTDONE::USB Done */ #define GFX125_VCS_INSTDONE_USBDone_bits 1 #define GFX12_VCS_INSTDONE_USBDone_bits 1 #define GFX11_VCS_INSTDONE_USBDone_bits 1 #define GFX9_VCS_INSTDONE_USBDone_bits 1 #define GFX8_VCS_INSTDONE_USBDone_bits 1 #define GFX75_VCS_INSTDONE_USBDone_bits 1 #define GFX7_VCS_INSTDONE_USBDone_bits 1 #define GFX6_VCS_INSTDONE_USBDone_bits 1 static inline uint32_t ATTRIBUTE_PURE VCS_INSTDONE_USBDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_VCS_INSTDONE_USBDone_start 1 #define GFX12_VCS_INSTDONE_USBDone_start 1 #define GFX11_VCS_INSTDONE_USBDone_start 1 #define GFX9_VCS_INSTDONE_USBDone_start 1 #define GFX8_VCS_INSTDONE_USBDone_start 1 #define GFX75_VCS_INSTDONE_USBDone_start 1 #define GFX7_VCS_INSTDONE_USBDone_start 1 #define GFX6_VCS_INSTDONE_USBDone_start 1 static inline uint32_t ATTRIBUTE_PURE VCS_INSTDONE_USBDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VCS_INSTDONE::VAC Done */ #define GFX125_VCS_INSTDONE_VACDone_bits 1 #define GFX12_VCS_INSTDONE_VACDone_bits 1 #define GFX11_VCS_INSTDONE_VACDone_bits 1 #define GFX9_VCS_INSTDONE_VACDone_bits 1 #define GFX8_VCS_INSTDONE_VACDone_bits 1 #define GFX75_VCS_INSTDONE_VACDone_bits 1 #define GFX7_VCS_INSTDONE_VACDone_bits 1 #define GFX6_VCS_INSTDONE_VACDone_bits 1 static inline uint32_t ATTRIBUTE_PURE VCS_INSTDONE_VACDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_VCS_INSTDONE_VACDone_start 19 #define GFX12_VCS_INSTDONE_VACDone_start 19 #define GFX11_VCS_INSTDONE_VACDone_start 19 #define GFX9_VCS_INSTDONE_VACDone_start 19 #define GFX8_VCS_INSTDONE_VACDone_start 19 #define GFX75_VCS_INSTDONE_VACDone_start 19 #define GFX7_VCS_INSTDONE_VACDone_start 19 #define GFX6_VCS_INSTDONE_VACDone_start 19 static inline uint32_t ATTRIBUTE_PURE VCS_INSTDONE_VACDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 19; case 120: return 19; case 110: return 19; case 90: return 19; case 80: return 19; case 75: return 19; case 70: return 19; case 60: return 19; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VCS_INSTDONE::VAD Done */ #define GFX125_VCS_INSTDONE_VADDone_bits 1 #define GFX12_VCS_INSTDONE_VADDone_bits 1 #define GFX11_VCS_INSTDONE_VADDone_bits 1 #define GFX9_VCS_INSTDONE_VADDone_bits 1 #define GFX8_VCS_INSTDONE_VADDone_bits 1 #define GFX75_VCS_INSTDONE_VADDone_bits 1 #define GFX7_VCS_INSTDONE_VADDone_bits 1 #define GFX6_VCS_INSTDONE_VADDone_bits 1 static inline uint32_t ATTRIBUTE_PURE VCS_INSTDONE_VADDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_VCS_INSTDONE_VADDone_start 16 #define GFX12_VCS_INSTDONE_VADDone_start 16 #define GFX11_VCS_INSTDONE_VADDone_start 16 #define GFX9_VCS_INSTDONE_VADDone_start 16 #define GFX8_VCS_INSTDONE_VADDone_start 16 #define GFX75_VCS_INSTDONE_VADDone_start 16 #define GFX7_VCS_INSTDONE_VADDone_start 16 #define GFX6_VCS_INSTDONE_VADDone_start 16 static inline uint32_t ATTRIBUTE_PURE VCS_INSTDONE_VADDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 16; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VCS_INSTDONE::VAM Done */ #define GFX125_VCS_INSTDONE_VAMDone_bits 1 #define GFX12_VCS_INSTDONE_VAMDone_bits 1 #define GFX11_VCS_INSTDONE_VAMDone_bits 1 #define GFX9_VCS_INSTDONE_VAMDone_bits 1 #define GFX8_VCS_INSTDONE_VAMDone_bits 1 #define GFX75_VCS_INSTDONE_VAMDone_bits 1 #define GFX7_VCS_INSTDONE_VAMDone_bits 1 #define GFX6_VCS_INSTDONE_VAMDone_bits 1 static inline uint32_t ATTRIBUTE_PURE VCS_INSTDONE_VAMDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_VCS_INSTDONE_VAMDone_start 20 #define GFX12_VCS_INSTDONE_VAMDone_start 20 #define GFX11_VCS_INSTDONE_VAMDone_start 20 #define GFX9_VCS_INSTDONE_VAMDone_start 20 #define GFX8_VCS_INSTDONE_VAMDone_start 20 #define GFX75_VCS_INSTDONE_VAMDone_start 20 #define GFX7_VCS_INSTDONE_VAMDone_start 20 #define GFX6_VCS_INSTDONE_VAMDone_start 20 static inline uint32_t ATTRIBUTE_PURE VCS_INSTDONE_VAMDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 20; case 120: return 20; case 110: return 20; case 90: return 20; case 80: return 20; case 75: return 20; case 70: return 20; case 60: return 20; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VCS_INSTDONE::VBP Done */ #define GFX125_VCS_INSTDONE_VBPDone_bits 1 #define GFX12_VCS_INSTDONE_VBPDone_bits 1 #define GFX11_VCS_INSTDONE_VBPDone_bits 1 #define GFX9_VCS_INSTDONE_VBPDone_bits 1 #define GFX8_VCS_INSTDONE_VBPDone_bits 1 #define GFX75_VCS_INSTDONE_VBPDone_bits 1 #define GFX7_VCS_INSTDONE_VBPDone_bits 1 #define GFX6_VCS_INSTDONE_VBPDone_bits 1 static inline uint32_t ATTRIBUTE_PURE VCS_INSTDONE_VBPDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_VCS_INSTDONE_VBPDone_start 22 #define GFX12_VCS_INSTDONE_VBPDone_start 22 #define GFX11_VCS_INSTDONE_VBPDone_start 22 #define GFX9_VCS_INSTDONE_VBPDone_start 22 #define GFX8_VCS_INSTDONE_VBPDone_start 22 #define GFX75_VCS_INSTDONE_VBPDone_start 22 #define GFX7_VCS_INSTDONE_VBPDone_start 22 #define GFX6_VCS_INSTDONE_VBPDone_start 22 static inline uint32_t ATTRIBUTE_PURE VCS_INSTDONE_VBPDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 22; case 120: return 22; case 110: return 22; case 90: return 22; case 80: return 22; case 75: return 22; case 70: return 22; case 60: return 22; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VCS_INSTDONE::VCD Done */ #define GFX125_VCS_INSTDONE_VCDDone_bits 1 #define GFX12_VCS_INSTDONE_VCDDone_bits 1 #define GFX11_VCS_INSTDONE_VCDDone_bits 1 #define GFX9_VCS_INSTDONE_VCDDone_bits 1 #define GFX8_VCS_INSTDONE_VCDDone_bits 1 #define GFX75_VCS_INSTDONE_VCDDone_bits 1 #define GFX7_VCS_INSTDONE_VCDDone_bits 1 #define GFX6_VCS_INSTDONE_VCDDone_bits 1 static inline uint32_t ATTRIBUTE_PURE VCS_INSTDONE_VCDDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_VCS_INSTDONE_VCDDone_start 15 #define GFX12_VCS_INSTDONE_VCDDone_start 15 #define GFX11_VCS_INSTDONE_VCDDone_start 15 #define GFX9_VCS_INSTDONE_VCDDone_start 15 #define GFX8_VCS_INSTDONE_VCDDone_start 15 #define GFX75_VCS_INSTDONE_VCDDone_start 15 #define GFX7_VCS_INSTDONE_VCDDone_start 15 #define GFX6_VCS_INSTDONE_VCDDone_start 15 static inline uint32_t ATTRIBUTE_PURE VCS_INSTDONE_VCDDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 15; case 120: return 15; case 110: return 15; case 90: return 15; case 80: return 15; case 75: return 15; case 70: return 15; case 60: return 15; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VCS_INSTDONE::VCI Done */ #define GFX125_VCS_INSTDONE_VCIDone_bits 1 #define GFX12_VCS_INSTDONE_VCIDone_bits 1 #define GFX11_VCS_INSTDONE_VCIDone_bits 1 #define GFX9_VCS_INSTDONE_VCIDone_bits 1 #define GFX8_VCS_INSTDONE_VCIDone_bits 1 #define GFX75_VCS_INSTDONE_VCIDone_bits 1 #define GFX7_VCS_INSTDONE_VCIDone_bits 1 #define GFX6_VCS_INSTDONE_VCIDone_bits 1 static inline uint32_t ATTRIBUTE_PURE VCS_INSTDONE_VCIDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_VCS_INSTDONE_VCIDone_start 24 #define GFX12_VCS_INSTDONE_VCIDone_start 24 #define GFX11_VCS_INSTDONE_VCIDone_start 24 #define GFX9_VCS_INSTDONE_VCIDone_start 24 #define GFX8_VCS_INSTDONE_VCIDone_start 24 #define GFX75_VCS_INSTDONE_VCIDone_start 24 #define GFX7_VCS_INSTDONE_VCIDone_start 24 #define GFX6_VCS_INSTDONE_VCIDone_start 24 static inline uint32_t ATTRIBUTE_PURE VCS_INSTDONE_VCIDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 24; case 120: return 24; case 110: return 24; case 90: return 24; case 80: return 24; case 75: return 24; case 70: return 24; case 60: return 24; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VCS_INSTDONE::VCP Done */ #define GFX125_VCS_INSTDONE_VCPDone_bits 1 #define GFX12_VCS_INSTDONE_VCPDone_bits 1 #define GFX11_VCS_INSTDONE_VCPDone_bits 1 #define GFX9_VCS_INSTDONE_VCPDone_bits 1 #define GFX8_VCS_INSTDONE_VCPDone_bits 1 #define GFX75_VCS_INSTDONE_VCPDone_bits 1 #define GFX7_VCS_INSTDONE_VCPDone_bits 1 #define GFX6_VCS_INSTDONE_VCPDone_bits 1 static inline uint32_t ATTRIBUTE_PURE VCS_INSTDONE_VCPDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_VCS_INSTDONE_VCPDone_start 14 #define GFX12_VCS_INSTDONE_VCPDone_start 14 #define GFX11_VCS_INSTDONE_VCPDone_start 14 #define GFX9_VCS_INSTDONE_VCPDone_start 14 #define GFX8_VCS_INSTDONE_VCPDone_start 14 #define GFX75_VCS_INSTDONE_VCPDone_start 14 #define GFX7_VCS_INSTDONE_VCPDone_start 14 #define GFX6_VCS_INSTDONE_VCPDone_start 14 static inline uint32_t ATTRIBUTE_PURE VCS_INSTDONE_VCPDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 14; case 120: return 14; case 110: return 14; case 90: return 14; case 80: return 14; case 75: return 14; case 70: return 14; case 60: return 14; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VCS_INSTDONE::VCR Done */ #define GFX9_VCS_INSTDONE_VCRDone_bits 1 #define GFX8_VCS_INSTDONE_VCRDone_bits 1 #define GFX75_VCS_INSTDONE_VCRDone_bits 1 #define GFX7_VCS_INSTDONE_VCRDone_bits 1 #define GFX6_VCS_INSTDONE_VCRDone_bits 1 static inline uint32_t ATTRIBUTE_PURE VCS_INSTDONE_VCRDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_VCS_INSTDONE_VCRDone_start 25 #define GFX8_VCS_INSTDONE_VCRDone_start 25 #define GFX75_VCS_INSTDONE_VCRDone_start 25 #define GFX7_VCS_INSTDONE_VCRDone_start 25 #define GFX6_VCS_INSTDONE_VCRDone_start 25 static inline uint32_t ATTRIBUTE_PURE VCS_INSTDONE_VCRDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 25; case 80: return 25; case 75: return 25; case 70: return 25; case 60: return 25; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VCS_INSTDONE::VCS Done */ #define GFX125_VCS_INSTDONE_VCSDone_bits 1 #define GFX12_VCS_INSTDONE_VCSDone_bits 1 #define GFX11_VCS_INSTDONE_VCSDone_bits 1 #define GFX9_VCS_INSTDONE_VCSDone_bits 1 #define GFX8_VCS_INSTDONE_VCSDone_bits 1 #define GFX75_VCS_INSTDONE_VCSDone_bits 1 #define GFX7_VCS_INSTDONE_VCSDone_bits 1 #define GFX6_VCS_INSTDONE_VCSDone_bits 1 static inline uint32_t ATTRIBUTE_PURE VCS_INSTDONE_VCSDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_VCS_INSTDONE_VCSDone_start 30 #define GFX12_VCS_INSTDONE_VCSDone_start 30 #define GFX11_VCS_INSTDONE_VCSDone_start 30 #define GFX9_VCS_INSTDONE_VCSDone_start 30 #define GFX8_VCS_INSTDONE_VCSDone_start 30 #define GFX75_VCS_INSTDONE_VCSDone_start 30 #define GFX7_VCS_INSTDONE_VCSDone_start 30 #define GFX6_VCS_INSTDONE_VCSDone_start 30 static inline uint32_t ATTRIBUTE_PURE VCS_INSTDONE_VCSDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 30; case 120: return 30; case 110: return 30; case 90: return 30; case 80: return 30; case 75: return 30; case 70: return 30; case 60: return 30; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VCS_INSTDONE::VDS Done */ #define GFX125_VCS_INSTDONE_VDSDone_bits 1 #define GFX12_VCS_INSTDONE_VDSDone_bits 1 #define GFX11_VCS_INSTDONE_VDSDone_bits 1 #define GFX9_VCS_INSTDONE_VDSDone_bits 1 #define GFX8_VCS_INSTDONE_VDSDone_bits 1 #define GFX75_VCS_INSTDONE_VDSDone_bits 1 #define GFX7_VCS_INSTDONE_VDSDone_bits 1 #define GFX6_VCS_INSTDONE_VDSDone_bits 1 static inline uint32_t ATTRIBUTE_PURE VCS_INSTDONE_VDSDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_VCS_INSTDONE_VDSDone_start 12 #define GFX12_VCS_INSTDONE_VDSDone_start 12 #define GFX11_VCS_INSTDONE_VDSDone_start 12 #define GFX9_VCS_INSTDONE_VDSDone_start 12 #define GFX8_VCS_INSTDONE_VDSDone_start 12 #define GFX75_VCS_INSTDONE_VDSDone_start 12 #define GFX7_VCS_INSTDONE_VDSDone_start 12 #define GFX6_VCS_INSTDONE_VDSDone_start 12 static inline uint32_t ATTRIBUTE_PURE VCS_INSTDONE_VDSDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 12; case 120: return 12; case 110: return 12; case 90: return 12; case 80: return 12; case 75: return 12; case 70: return 12; case 60: return 12; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VCS_INSTDONE::VFT Done */ #define GFX125_VCS_INSTDONE_VFTDone_bits 1 #define GFX12_VCS_INSTDONE_VFTDone_bits 1 #define GFX11_VCS_INSTDONE_VFTDone_bits 1 #define GFX9_VCS_INSTDONE_VFTDone_bits 1 #define GFX8_VCS_INSTDONE_VFTDone_bits 1 #define GFX75_VCS_INSTDONE_VFTDone_bits 1 #define GFX7_VCS_INSTDONE_VFTDone_bits 1 #define GFX6_VCS_INSTDONE_VFTDone_bits 1 static inline uint32_t ATTRIBUTE_PURE VCS_INSTDONE_VFTDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_VCS_INSTDONE_VFTDone_start 5 #define GFX12_VCS_INSTDONE_VFTDone_start 5 #define GFX11_VCS_INSTDONE_VFTDone_start 5 #define GFX9_VCS_INSTDONE_VFTDone_start 5 #define GFX8_VCS_INSTDONE_VFTDone_start 5 #define GFX75_VCS_INSTDONE_VFTDone_start 5 #define GFX7_VCS_INSTDONE_VFTDone_start 5 #define GFX6_VCS_INSTDONE_VFTDone_start 5 static inline uint32_t ATTRIBUTE_PURE VCS_INSTDONE_VFTDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 5; case 110: return 5; case 90: return 5; case 80: return 5; case 75: return 5; case 70: return 5; case 60: return 5; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VCS_INSTDONE::VHR Done */ #define GFX125_VCS_INSTDONE_VHRDone_bits 1 #define GFX12_VCS_INSTDONE_VHRDone_bits 1 #define GFX11_VCS_INSTDONE_VHRDone_bits 1 #define GFX9_VCS_INSTDONE_VHRDone_bits 1 #define GFX8_VCS_INSTDONE_VHRDone_bits 1 #define GFX75_VCS_INSTDONE_VHRDone_bits 1 #define GFX7_VCS_INSTDONE_VHRDone_bits 1 #define GFX6_VCS_INSTDONE_VHRDone_bits 1 static inline uint32_t ATTRIBUTE_PURE VCS_INSTDONE_VHRDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_VCS_INSTDONE_VHRDone_start 23 #define GFX12_VCS_INSTDONE_VHRDone_start 23 #define GFX11_VCS_INSTDONE_VHRDone_start 23 #define GFX9_VCS_INSTDONE_VHRDone_start 23 #define GFX8_VCS_INSTDONE_VHRDone_start 23 #define GFX75_VCS_INSTDONE_VHRDone_start 23 #define GFX7_VCS_INSTDONE_VHRDone_start 23 #define GFX6_VCS_INSTDONE_VHRDone_start 23 static inline uint32_t ATTRIBUTE_PURE VCS_INSTDONE_VHRDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 23; case 120: return 23; case 110: return 23; case 90: return 23; case 80: return 23; case 75: return 23; case 70: return 23; case 60: return 23; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VCS_INSTDONE::VIN Done */ #define GFX125_VCS_INSTDONE_VINDone_bits 1 #define GFX12_VCS_INSTDONE_VINDone_bits 1 #define GFX11_VCS_INSTDONE_VINDone_bits 1 #define GFX9_VCS_INSTDONE_VINDone_bits 1 #define GFX8_VCS_INSTDONE_VINDone_bits 1 #define GFX75_VCS_INSTDONE_VINDone_bits 1 #define GFX7_VCS_INSTDONE_VINDone_bits 1 #define GFX6_VCS_INSTDONE_VINDone_bits 1 static inline uint32_t ATTRIBUTE_PURE VCS_INSTDONE_VINDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_VCS_INSTDONE_VINDone_start 26 #define GFX12_VCS_INSTDONE_VINDone_start 26 #define GFX11_VCS_INSTDONE_VINDone_start 26 #define GFX9_VCS_INSTDONE_VINDone_start 26 #define GFX8_VCS_INSTDONE_VINDone_start 26 #define GFX75_VCS_INSTDONE_VINDone_start 26 #define GFX7_VCS_INSTDONE_VINDone_start 26 #define GFX6_VCS_INSTDONE_VINDone_start 26 static inline uint32_t ATTRIBUTE_PURE VCS_INSTDONE_VINDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 26; case 120: return 26; case 110: return 26; case 90: return 26; case 80: return 26; case 75: return 26; case 70: return 26; case 60: return 26; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VCS_INSTDONE::VIP Done */ #define GFX125_VCS_INSTDONE_VIPDone_bits 1 #define GFX12_VCS_INSTDONE_VIPDone_bits 1 #define GFX11_VCS_INSTDONE_VIPDone_bits 1 #define GFX9_VCS_INSTDONE_VIPDone_bits 1 #define GFX8_VCS_INSTDONE_VIPDone_bits 1 #define GFX75_VCS_INSTDONE_VIPDone_bits 1 #define GFX7_VCS_INSTDONE_VIPDone_bits 1 #define GFX6_VCS_INSTDONE_VIPDone_bits 1 static inline uint32_t ATTRIBUTE_PURE VCS_INSTDONE_VIPDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_VCS_INSTDONE_VIPDone_start 10 #define GFX12_VCS_INSTDONE_VIPDone_start 10 #define GFX11_VCS_INSTDONE_VIPDone_start 10 #define GFX9_VCS_INSTDONE_VIPDone_start 10 #define GFX8_VCS_INSTDONE_VIPDone_start 10 #define GFX75_VCS_INSTDONE_VIPDone_start 10 #define GFX7_VCS_INSTDONE_VIPDone_start 10 #define GFX6_VCS_INSTDONE_VIPDone_start 10 static inline uint32_t ATTRIBUTE_PURE VCS_INSTDONE_VIPDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 10; case 120: return 10; case 110: return 10; case 90: return 10; case 80: return 10; case 75: return 10; case 70: return 10; case 60: return 10; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VCS_INSTDONE::VIS Done */ #define GFX125_VCS_INSTDONE_VISDone_bits 1 #define GFX12_VCS_INSTDONE_VISDone_bits 1 #define GFX11_VCS_INSTDONE_VISDone_bits 1 #define GFX9_VCS_INSTDONE_VISDone_bits 1 #define GFX8_VCS_INSTDONE_VISDone_bits 1 #define GFX75_VCS_INSTDONE_VISDone_bits 1 #define GFX7_VCS_INSTDONE_VISDone_bits 1 #define GFX6_VCS_INSTDONE_VISDone_bits 1 static inline uint32_t ATTRIBUTE_PURE VCS_INSTDONE_VISDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_VCS_INSTDONE_VISDone_start 18 #define GFX12_VCS_INSTDONE_VISDone_start 18 #define GFX11_VCS_INSTDONE_VISDone_start 18 #define GFX9_VCS_INSTDONE_VISDone_start 18 #define GFX8_VCS_INSTDONE_VISDone_start 18 #define GFX75_VCS_INSTDONE_VISDone_start 18 #define GFX7_VCS_INSTDONE_VISDone_start 18 #define GFX6_VCS_INSTDONE_VISDone_start 18 static inline uint32_t ATTRIBUTE_PURE VCS_INSTDONE_VISDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 18; case 120: return 18; case 110: return 18; case 90: return 18; case 80: return 18; case 75: return 18; case 70: return 18; case 60: return 18; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VCS_INSTDONE::VIT Done */ #define GFX125_VCS_INSTDONE_VITDone_bits 1 #define GFX12_VCS_INSTDONE_VITDone_bits 1 #define GFX11_VCS_INSTDONE_VITDone_bits 1 #define GFX9_VCS_INSTDONE_VITDone_bits 1 #define GFX8_VCS_INSTDONE_VITDone_bits 1 #define GFX75_VCS_INSTDONE_VITDone_bits 1 #define GFX7_VCS_INSTDONE_VITDone_bits 1 #define GFX6_VCS_INSTDONE_VITDone_bits 1 static inline uint32_t ATTRIBUTE_PURE VCS_INSTDONE_VITDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_VCS_INSTDONE_VITDone_start 11 #define GFX12_VCS_INSTDONE_VITDone_start 11 #define GFX11_VCS_INSTDONE_VITDone_start 11 #define GFX9_VCS_INSTDONE_VITDone_start 11 #define GFX8_VCS_INSTDONE_VITDone_start 11 #define GFX75_VCS_INSTDONE_VITDone_start 11 #define GFX7_VCS_INSTDONE_VITDone_start 11 #define GFX6_VCS_INSTDONE_VITDone_start 11 static inline uint32_t ATTRIBUTE_PURE VCS_INSTDONE_VITDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 11; case 120: return 11; case 110: return 11; case 90: return 11; case 80: return 11; case 75: return 11; case 70: return 11; case 60: return 11; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VCS_INSTDONE::VLF Done */ #define GFX125_VCS_INSTDONE_VLFDone_bits 1 #define GFX12_VCS_INSTDONE_VLFDone_bits 1 #define GFX11_VCS_INSTDONE_VLFDone_bits 1 #define GFX9_VCS_INSTDONE_VLFDone_bits 1 #define GFX8_VCS_INSTDONE_VLFDone_bits 1 #define GFX75_VCS_INSTDONE_VLFDone_bits 1 #define GFX7_VCS_INSTDONE_VLFDone_bits 1 #define GFX6_VCS_INSTDONE_VLFDone_bits 1 static inline uint32_t ATTRIBUTE_PURE VCS_INSTDONE_VLFDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_VCS_INSTDONE_VLFDone_start 7 #define GFX12_VCS_INSTDONE_VLFDone_start 7 #define GFX11_VCS_INSTDONE_VLFDone_start 7 #define GFX9_VCS_INSTDONE_VLFDone_start 7 #define GFX8_VCS_INSTDONE_VLFDone_start 7 #define GFX75_VCS_INSTDONE_VLFDone_start 7 #define GFX7_VCS_INSTDONE_VLFDone_start 7 #define GFX6_VCS_INSTDONE_VLFDone_start 7 static inline uint32_t ATTRIBUTE_PURE VCS_INSTDONE_VLFDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 7; case 120: return 7; case 110: return 7; case 90: return 7; case 80: return 7; case 75: return 7; case 70: return 7; case 60: return 7; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VCS_INSTDONE::VMC Done */ #define GFX125_VCS_INSTDONE_VMCDone_bits 1 #define GFX12_VCS_INSTDONE_VMCDone_bits 1 #define GFX11_VCS_INSTDONE_VMCDone_bits 1 #define GFX9_VCS_INSTDONE_VMCDone_bits 1 #define GFX8_VCS_INSTDONE_VMCDone_bits 1 #define GFX75_VCS_INSTDONE_VMCDone_bits 1 #define GFX7_VCS_INSTDONE_VMCDone_bits 1 #define GFX6_VCS_INSTDONE_VMCDone_bits 1 static inline uint32_t ATTRIBUTE_PURE VCS_INSTDONE_VMCDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_VCS_INSTDONE_VMCDone_start 9 #define GFX12_VCS_INSTDONE_VMCDone_start 9 #define GFX11_VCS_INSTDONE_VMCDone_start 9 #define GFX9_VCS_INSTDONE_VMCDone_start 9 #define GFX8_VCS_INSTDONE_VMCDone_start 9 #define GFX75_VCS_INSTDONE_VMCDone_start 9 #define GFX7_VCS_INSTDONE_VMCDone_start 9 #define GFX6_VCS_INSTDONE_VMCDone_start 9 static inline uint32_t ATTRIBUTE_PURE VCS_INSTDONE_VMCDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 9; case 120: return 9; case 110: return 9; case 90: return 9; case 80: return 9; case 75: return 9; case 70: return 9; case 60: return 9; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VCS_INSTDONE::VMD Done */ #define GFX125_VCS_INSTDONE_VMDDone_bits 1 #define GFX12_VCS_INSTDONE_VMDDone_bits 1 #define GFX11_VCS_INSTDONE_VMDDone_bits 1 #define GFX9_VCS_INSTDONE_VMDDone_bits 1 #define GFX8_VCS_INSTDONE_VMDDone_bits 1 #define GFX75_VCS_INSTDONE_VMDDone_bits 1 #define GFX7_VCS_INSTDONE_VMDDone_bits 1 #define GFX6_VCS_INSTDONE_VMDDone_bits 1 static inline uint32_t ATTRIBUTE_PURE VCS_INSTDONE_VMDDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_VCS_INSTDONE_VMDDone_start 17 #define GFX12_VCS_INSTDONE_VMDDone_start 17 #define GFX11_VCS_INSTDONE_VMDDone_start 17 #define GFX9_VCS_INSTDONE_VMDDone_start 17 #define GFX8_VCS_INSTDONE_VMDDone_start 17 #define GFX75_VCS_INSTDONE_VMDDone_start 17 #define GFX7_VCS_INSTDONE_VMDDone_start 17 #define GFX6_VCS_INSTDONE_VMDDone_start 17 static inline uint32_t ATTRIBUTE_PURE VCS_INSTDONE_VMDDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 17; case 120: return 17; case 110: return 17; case 90: return 17; case 80: return 17; case 75: return 17; case 70: return 17; case 60: return 17; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VCS_INSTDONE::VMX Done */ #define GFX125_VCS_INSTDONE_VMXDone_bits 1 #define GFX12_VCS_INSTDONE_VMXDone_bits 1 #define GFX11_VCS_INSTDONE_VMXDone_bits 1 #define GFX9_VCS_INSTDONE_VMXDone_bits 1 #define GFX8_VCS_INSTDONE_VMXDone_bits 1 #define GFX75_VCS_INSTDONE_VMXDone_bits 1 #define GFX7_VCS_INSTDONE_VMXDone_bits 1 #define GFX6_VCS_INSTDONE_VMXDone_bits 1 static inline uint32_t ATTRIBUTE_PURE VCS_INSTDONE_VMXDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_VCS_INSTDONE_VMXDone_start 13 #define GFX12_VCS_INSTDONE_VMXDone_start 13 #define GFX11_VCS_INSTDONE_VMXDone_start 13 #define GFX9_VCS_INSTDONE_VMXDone_start 13 #define GFX8_VCS_INSTDONE_VMXDone_start 13 #define GFX75_VCS_INSTDONE_VMXDone_start 13 #define GFX7_VCS_INSTDONE_VMXDone_start 13 #define GFX6_VCS_INSTDONE_VMXDone_start 13 static inline uint32_t ATTRIBUTE_PURE VCS_INSTDONE_VMXDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 13; case 120: return 13; case 110: return 13; case 90: return 13; case 80: return 13; case 75: return 13; case 70: return 13; case 60: return 13; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VCS_INSTDONE::VOP Done */ #define GFX125_VCS_INSTDONE_VOPDone_bits 1 #define GFX12_VCS_INSTDONE_VOPDone_bits 1 #define GFX11_VCS_INSTDONE_VOPDone_bits 1 #define GFX9_VCS_INSTDONE_VOPDone_bits 1 #define GFX8_VCS_INSTDONE_VOPDone_bits 1 #define GFX75_VCS_INSTDONE_VOPDone_bits 1 #define GFX7_VCS_INSTDONE_VOPDone_bits 1 #define GFX6_VCS_INSTDONE_VOPDone_bits 1 static inline uint32_t ATTRIBUTE_PURE VCS_INSTDONE_VOPDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_VCS_INSTDONE_VOPDone_start 8 #define GFX12_VCS_INSTDONE_VOPDone_start 8 #define GFX11_VCS_INSTDONE_VOPDone_start 8 #define GFX9_VCS_INSTDONE_VOPDone_start 8 #define GFX8_VCS_INSTDONE_VOPDone_start 8 #define GFX75_VCS_INSTDONE_VOPDone_start 8 #define GFX7_VCS_INSTDONE_VOPDone_start 8 #define GFX6_VCS_INSTDONE_VOPDone_start 8 static inline uint32_t ATTRIBUTE_PURE VCS_INSTDONE_VOPDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 8; case 120: return 8; case 110: return 8; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VCS_INSTDONE::VPR Done */ #define GFX125_VCS_INSTDONE_VPRDone_bits 1 #define GFX12_VCS_INSTDONE_VPRDone_bits 1 #define GFX11_VCS_INSTDONE_VPRDone_bits 1 #define GFX9_VCS_INSTDONE_VPRDone_bits 1 #define GFX8_VCS_INSTDONE_VPRDone_bits 1 #define GFX75_VCS_INSTDONE_VPRDone_bits 1 #define GFX7_VCS_INSTDONE_VPRDone_bits 1 #define GFX6_VCS_INSTDONE_VPRDone_bits 1 static inline uint32_t ATTRIBUTE_PURE VCS_INSTDONE_VPRDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_VCS_INSTDONE_VPRDone_start 27 #define GFX12_VCS_INSTDONE_VPRDone_start 27 #define GFX11_VCS_INSTDONE_VPRDone_start 27 #define GFX9_VCS_INSTDONE_VPRDone_start 27 #define GFX8_VCS_INSTDONE_VPRDone_start 27 #define GFX75_VCS_INSTDONE_VPRDone_start 27 #define GFX7_VCS_INSTDONE_VPRDone_start 27 #define GFX6_VCS_INSTDONE_VPRDone_start 27 static inline uint32_t ATTRIBUTE_PURE VCS_INSTDONE_VPRDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 27; case 120: return 27; case 110: return 27; case 90: return 27; case 80: return 27; case 75: return 27; case 70: return 27; case 60: return 27; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VCS_INSTDONE::VTQ Done */ #define GFX125_VCS_INSTDONE_VTQDone_bits 1 #define GFX12_VCS_INSTDONE_VTQDone_bits 1 #define GFX11_VCS_INSTDONE_VTQDone_bits 1 #define GFX9_VCS_INSTDONE_VTQDone_bits 1 #define GFX8_VCS_INSTDONE_VTQDone_bits 1 #define GFX75_VCS_INSTDONE_VTQDone_bits 1 #define GFX7_VCS_INSTDONE_VTQDone_bits 1 #define GFX6_VCS_INSTDONE_VTQDone_bits 1 static inline uint32_t ATTRIBUTE_PURE VCS_INSTDONE_VTQDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_VCS_INSTDONE_VTQDone_start 28 #define GFX12_VCS_INSTDONE_VTQDone_start 28 #define GFX11_VCS_INSTDONE_VTQDone_start 28 #define GFX9_VCS_INSTDONE_VTQDone_start 28 #define GFX8_VCS_INSTDONE_VTQDone_start 28 #define GFX75_VCS_INSTDONE_VTQDone_start 28 #define GFX7_VCS_INSTDONE_VTQDone_start 28 #define GFX6_VCS_INSTDONE_VTQDone_start 28 static inline uint32_t ATTRIBUTE_PURE VCS_INSTDONE_VTQDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 28; case 120: return 28; case 110: return 28; case 90: return 28; case 80: return 28; case 75: return 28; case 70: return 28; case 60: return 28; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VCS_RING_BUFFER_CTL */ #define GFX9_VCS_RING_BUFFER_CTL_length 1 #define GFX8_VCS_RING_BUFFER_CTL_length 1 #define GFX75_VCS_RING_BUFFER_CTL_length 1 #define GFX7_VCS_RING_BUFFER_CTL_length 1 #define GFX6_VCS_RING_BUFFER_CTL_length 1 static inline uint32_t ATTRIBUTE_PURE VCS_RING_BUFFER_CTL_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VCS_RING_BUFFER_CTL::Automatic Report Head Pointer */ #define GFX9_VCS_RING_BUFFER_CTL_AutomaticReportHeadPointer_bits 2 #define GFX8_VCS_RING_BUFFER_CTL_AutomaticReportHeadPointer_bits 2 #define GFX75_VCS_RING_BUFFER_CTL_AutomaticReportHeadPointer_bits 2 #define GFX7_VCS_RING_BUFFER_CTL_AutomaticReportHeadPointer_bits 2 #define GFX6_VCS_RING_BUFFER_CTL_AutomaticReportHeadPointer_bits 2 static inline uint32_t ATTRIBUTE_PURE VCS_RING_BUFFER_CTL_AutomaticReportHeadPointer_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_VCS_RING_BUFFER_CTL_AutomaticReportHeadPointer_start 1 #define GFX8_VCS_RING_BUFFER_CTL_AutomaticReportHeadPointer_start 1 #define GFX75_VCS_RING_BUFFER_CTL_AutomaticReportHeadPointer_start 1 #define GFX7_VCS_RING_BUFFER_CTL_AutomaticReportHeadPointer_start 1 #define GFX6_VCS_RING_BUFFER_CTL_AutomaticReportHeadPointer_start 1 static inline uint32_t ATTRIBUTE_PURE VCS_RING_BUFFER_CTL_AutomaticReportHeadPointer_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VCS_RING_BUFFER_CTL::Buffer Length (in pages - 1) */ #define GFX9_VCS_RING_BUFFER_CTL_BufferLengthinpages1_bits 9 #define GFX8_VCS_RING_BUFFER_CTL_BufferLengthinpages1_bits 9 #define GFX75_VCS_RING_BUFFER_CTL_BufferLengthinpages1_bits 9 #define GFX7_VCS_RING_BUFFER_CTL_BufferLengthinpages1_bits 9 #define GFX6_VCS_RING_BUFFER_CTL_BufferLengthinpages1_bits 9 static inline uint32_t ATTRIBUTE_PURE VCS_RING_BUFFER_CTL_BufferLengthinpages1_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 9; case 80: return 9; case 75: return 9; case 70: return 9; case 60: return 9; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_VCS_RING_BUFFER_CTL_BufferLengthinpages1_start 12 #define GFX8_VCS_RING_BUFFER_CTL_BufferLengthinpages1_start 12 #define GFX75_VCS_RING_BUFFER_CTL_BufferLengthinpages1_start 12 #define GFX7_VCS_RING_BUFFER_CTL_BufferLengthinpages1_start 12 #define GFX6_VCS_RING_BUFFER_CTL_BufferLengthinpages1_start 12 static inline uint32_t ATTRIBUTE_PURE VCS_RING_BUFFER_CTL_BufferLengthinpages1_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 12; case 80: return 12; case 75: return 12; case 70: return 12; case 60: return 12; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VCS_RING_BUFFER_CTL::Disable Register Accesses */ #define GFX9_VCS_RING_BUFFER_CTL_DisableRegisterAccesses_bits 1 #define GFX8_VCS_RING_BUFFER_CTL_DisableRegisterAccesses_bits 1 #define GFX75_VCS_RING_BUFFER_CTL_DisableRegisterAccesses_bits 1 #define GFX7_VCS_RING_BUFFER_CTL_DisableRegisterAccesses_bits 1 #define GFX6_VCS_RING_BUFFER_CTL_DisableRegisterAccesses_bits 1 static inline uint32_t ATTRIBUTE_PURE VCS_RING_BUFFER_CTL_DisableRegisterAccesses_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_VCS_RING_BUFFER_CTL_DisableRegisterAccesses_start 8 #define GFX8_VCS_RING_BUFFER_CTL_DisableRegisterAccesses_start 8 #define GFX75_VCS_RING_BUFFER_CTL_DisableRegisterAccesses_start 8 #define GFX7_VCS_RING_BUFFER_CTL_DisableRegisterAccesses_start 8 #define GFX6_VCS_RING_BUFFER_CTL_DisableRegisterAccesses_start 8 static inline uint32_t ATTRIBUTE_PURE VCS_RING_BUFFER_CTL_DisableRegisterAccesses_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 8; case 60: return 8; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VCS_RING_BUFFER_CTL::RBWait */ #define GFX9_VCS_RING_BUFFER_CTL_RBWait_bits 1 #define GFX8_VCS_RING_BUFFER_CTL_RBWait_bits 1 #define GFX75_VCS_RING_BUFFER_CTL_RBWait_bits 1 #define GFX7_VCS_RING_BUFFER_CTL_RBWait_bits 1 #define GFX6_VCS_RING_BUFFER_CTL_RBWait_bits 1 static inline uint32_t ATTRIBUTE_PURE VCS_RING_BUFFER_CTL_RBWait_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_VCS_RING_BUFFER_CTL_RBWait_start 11 #define GFX8_VCS_RING_BUFFER_CTL_RBWait_start 11 #define GFX75_VCS_RING_BUFFER_CTL_RBWait_start 11 #define GFX7_VCS_RING_BUFFER_CTL_RBWait_start 11 #define GFX6_VCS_RING_BUFFER_CTL_RBWait_start 11 static inline uint32_t ATTRIBUTE_PURE VCS_RING_BUFFER_CTL_RBWait_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 11; case 80: return 11; case 75: return 11; case 70: return 11; case 60: return 11; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VCS_RING_BUFFER_CTL::Ring Buffer Enable */ #define GFX9_VCS_RING_BUFFER_CTL_RingBufferEnable_bits 1 #define GFX8_VCS_RING_BUFFER_CTL_RingBufferEnable_bits 1 #define GFX75_VCS_RING_BUFFER_CTL_RingBufferEnable_bits 1 #define GFX7_VCS_RING_BUFFER_CTL_RingBufferEnable_bits 1 #define GFX6_VCS_RING_BUFFER_CTL_RingBufferEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE VCS_RING_BUFFER_CTL_RingBufferEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_VCS_RING_BUFFER_CTL_RingBufferEnable_start 0 #define GFX8_VCS_RING_BUFFER_CTL_RingBufferEnable_start 0 #define GFX75_VCS_RING_BUFFER_CTL_RingBufferEnable_start 0 #define GFX7_VCS_RING_BUFFER_CTL_RingBufferEnable_start 0 #define GFX6_VCS_RING_BUFFER_CTL_RingBufferEnable_start 0 static inline uint32_t ATTRIBUTE_PURE VCS_RING_BUFFER_CTL_RingBufferEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VCS_RING_BUFFER_CTL::Semaphore Wait */ #define GFX9_VCS_RING_BUFFER_CTL_SemaphoreWait_bits 1 #define GFX8_VCS_RING_BUFFER_CTL_SemaphoreWait_bits 1 #define GFX75_VCS_RING_BUFFER_CTL_SemaphoreWait_bits 1 #define GFX7_VCS_RING_BUFFER_CTL_SemaphoreWait_bits 1 #define GFX6_VCS_RING_BUFFER_CTL_SemaphoreWait_bits 1 static inline uint32_t ATTRIBUTE_PURE VCS_RING_BUFFER_CTL_SemaphoreWait_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_VCS_RING_BUFFER_CTL_SemaphoreWait_start 10 #define GFX8_VCS_RING_BUFFER_CTL_SemaphoreWait_start 10 #define GFX75_VCS_RING_BUFFER_CTL_SemaphoreWait_start 10 #define GFX7_VCS_RING_BUFFER_CTL_SemaphoreWait_start 10 #define GFX6_VCS_RING_BUFFER_CTL_SemaphoreWait_start 10 static inline uint32_t ATTRIBUTE_PURE VCS_RING_BUFFER_CTL_SemaphoreWait_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 10; case 80: return 10; case 75: return 10; case 70: return 10; case 60: return 10; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VDENC_PICTURE */ #define GFX125_VDENC_PICTURE_length 3 #define GFX12_VDENC_PICTURE_length 3 #define GFX11_VDENC_PICTURE_length 3 #define GFX9_VDENC_PICTURE_length 3 static inline uint32_t ATTRIBUTE_PURE VDENC_PICTURE_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VDENC_PICTURE::Address */ #define GFX125_VDENC_PICTURE_Address_bits 64 #define GFX12_VDENC_PICTURE_Address_bits 64 #define GFX11_VDENC_PICTURE_Address_bits 64 #define GFX9_VDENC_PICTURE_Address_bits 64 static inline uint32_t ATTRIBUTE_PURE VDENC_PICTURE_Address_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 64; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_VDENC_PICTURE_Address_start 0 #define GFX12_VDENC_PICTURE_Address_start 0 #define GFX11_VDENC_PICTURE_Address_start 0 #define GFX9_VDENC_PICTURE_Address_start 0 static inline uint32_t ATTRIBUTE_PURE VDENC_PICTURE_Address_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VDENC_PICTURE::Picture Fields */ #define GFX125_VDENC_PICTURE_PictureFields_bits 32 #define GFX12_VDENC_PICTURE_PictureFields_bits 32 #define GFX11_VDENC_PICTURE_PictureFields_bits 32 #define GFX9_VDENC_PICTURE_PictureFields_bits 32 static inline uint32_t ATTRIBUTE_PURE VDENC_PICTURE_PictureFields_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_VDENC_PICTURE_PictureFields_start 64 #define GFX12_VDENC_PICTURE_PictureFields_start 64 #define GFX11_VDENC_PICTURE_PictureFields_start 64 #define GFX9_VDENC_PICTURE_PictureFields_start 64 static inline uint32_t ATTRIBUTE_PURE VDENC_PICTURE_PictureFields_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 64; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VDENC_SURFACE_CONTROL_BITS */ #define GFX125_VDENC_SURFACE_CONTROL_BITS_length 1 #define GFX12_VDENC_SURFACE_CONTROL_BITS_length 1 #define GFX11_VDENC_SURFACE_CONTROL_BITS_length 1 #define GFX9_VDENC_SURFACE_CONTROL_BITS_length 1 static inline uint32_t ATTRIBUTE_PURE VDENC_SURFACE_CONTROL_BITS_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VDENC_SURFACE_CONTROL_BITS::Arbitration Priority Control */ #define GFX125_VDENC_SURFACE_CONTROL_BITS_ArbitrationPriorityControl_bits 2 #define GFX12_VDENC_SURFACE_CONTROL_BITS_ArbitrationPriorityControl_bits 2 #define GFX11_VDENC_SURFACE_CONTROL_BITS_ArbitrationPriorityControl_bits 2 #define GFX9_VDENC_SURFACE_CONTROL_BITS_ArbitrationPriorityControl_bits 2 static inline uint32_t ATTRIBUTE_PURE VDENC_SURFACE_CONTROL_BITS_ArbitrationPriorityControl_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_VDENC_SURFACE_CONTROL_BITS_ArbitrationPriorityControl_start 7 #define GFX12_VDENC_SURFACE_CONTROL_BITS_ArbitrationPriorityControl_start 7 #define GFX11_VDENC_SURFACE_CONTROL_BITS_ArbitrationPriorityControl_start 7 #define GFX9_VDENC_SURFACE_CONTROL_BITS_ArbitrationPriorityControl_start 7 static inline uint32_t ATTRIBUTE_PURE VDENC_SURFACE_CONTROL_BITS_ArbitrationPriorityControl_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 7; case 120: return 7; case 110: return 7; case 90: return 7; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VDENC_SURFACE_CONTROL_BITS::Cache Select */ #define GFX125_VDENC_SURFACE_CONTROL_BITS_CacheSelect_bits 1 #define GFX12_VDENC_SURFACE_CONTROL_BITS_CacheSelect_bits 1 #define GFX11_VDENC_SURFACE_CONTROL_BITS_CacheSelect_bits 1 #define GFX9_VDENC_SURFACE_CONTROL_BITS_CacheSelect_bits 1 static inline uint32_t ATTRIBUTE_PURE VDENC_SURFACE_CONTROL_BITS_CacheSelect_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_VDENC_SURFACE_CONTROL_BITS_CacheSelect_start 12 #define GFX12_VDENC_SURFACE_CONTROL_BITS_CacheSelect_start 12 #define GFX11_VDENC_SURFACE_CONTROL_BITS_CacheSelect_start 12 #define GFX9_VDENC_SURFACE_CONTROL_BITS_CacheSelect_start 12 static inline uint32_t ATTRIBUTE_PURE VDENC_SURFACE_CONTROL_BITS_CacheSelect_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 12; case 120: return 12; case 110: return 12; case 90: return 12; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VDENC_SURFACE_CONTROL_BITS::MOCS */ #define GFX125_VDENC_SURFACE_CONTROL_BITS_MOCS_bits 6 #define GFX12_VDENC_SURFACE_CONTROL_BITS_MOCS_bits 6 #define GFX11_VDENC_SURFACE_CONTROL_BITS_MOCS_bits 6 #define GFX9_VDENC_SURFACE_CONTROL_BITS_MOCS_bits 6 static inline uint32_t ATTRIBUTE_PURE VDENC_SURFACE_CONTROL_BITS_MOCS_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_VDENC_SURFACE_CONTROL_BITS_MOCS_start 1 #define GFX12_VDENC_SURFACE_CONTROL_BITS_MOCS_start 1 #define GFX11_VDENC_SURFACE_CONTROL_BITS_MOCS_start 1 #define GFX9_VDENC_SURFACE_CONTROL_BITS_MOCS_start 1 static inline uint32_t ATTRIBUTE_PURE VDENC_SURFACE_CONTROL_BITS_MOCS_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VDENC_SURFACE_CONTROL_BITS::Memory Compression Enable */ #define GFX125_VDENC_SURFACE_CONTROL_BITS_MemoryCompressionEnable_bits 1 #define GFX12_VDENC_SURFACE_CONTROL_BITS_MemoryCompressionEnable_bits 1 #define GFX11_VDENC_SURFACE_CONTROL_BITS_MemoryCompressionEnable_bits 1 #define GFX9_VDENC_SURFACE_CONTROL_BITS_MemoryCompressionEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE VDENC_SURFACE_CONTROL_BITS_MemoryCompressionEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_VDENC_SURFACE_CONTROL_BITS_MemoryCompressionEnable_start 9 #define GFX12_VDENC_SURFACE_CONTROL_BITS_MemoryCompressionEnable_start 9 #define GFX11_VDENC_SURFACE_CONTROL_BITS_MemoryCompressionEnable_start 9 #define GFX9_VDENC_SURFACE_CONTROL_BITS_MemoryCompressionEnable_start 9 static inline uint32_t ATTRIBUTE_PURE VDENC_SURFACE_CONTROL_BITS_MemoryCompressionEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 9; case 120: return 9; case 110: return 9; case 90: return 9; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VDENC_SURFACE_CONTROL_BITS::Memory Compression Mode */ #define GFX125_VDENC_SURFACE_CONTROL_BITS_MemoryCompressionMode_bits 1 #define GFX12_VDENC_SURFACE_CONTROL_BITS_MemoryCompressionMode_bits 1 #define GFX11_VDENC_SURFACE_CONTROL_BITS_MemoryCompressionMode_bits 1 #define GFX9_VDENC_SURFACE_CONTROL_BITS_MemoryCompressionMode_bits 1 static inline uint32_t ATTRIBUTE_PURE VDENC_SURFACE_CONTROL_BITS_MemoryCompressionMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_VDENC_SURFACE_CONTROL_BITS_MemoryCompressionMode_start 10 #define GFX12_VDENC_SURFACE_CONTROL_BITS_MemoryCompressionMode_start 10 #define GFX11_VDENC_SURFACE_CONTROL_BITS_MemoryCompressionMode_start 10 #define GFX9_VDENC_SURFACE_CONTROL_BITS_MemoryCompressionMode_start 10 static inline uint32_t ATTRIBUTE_PURE VDENC_SURFACE_CONTROL_BITS_MemoryCompressionMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 10; case 120: return 10; case 110: return 10; case 90: return 10; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VDENC_SURFACE_CONTROL_BITS::Tiled Resource Mode */ #define GFX125_VDENC_SURFACE_CONTROL_BITS_TiledResourceMode_bits 2 #define GFX12_VDENC_SURFACE_CONTROL_BITS_TiledResourceMode_bits 2 #define GFX11_VDENC_SURFACE_CONTROL_BITS_TiledResourceMode_bits 2 #define GFX9_VDENC_SURFACE_CONTROL_BITS_TiledResourceMode_bits 2 static inline uint32_t ATTRIBUTE_PURE VDENC_SURFACE_CONTROL_BITS_TiledResourceMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_VDENC_SURFACE_CONTROL_BITS_TiledResourceMode_start 13 #define GFX12_VDENC_SURFACE_CONTROL_BITS_TiledResourceMode_start 13 #define GFX11_VDENC_SURFACE_CONTROL_BITS_TiledResourceMode_start 13 #define GFX9_VDENC_SURFACE_CONTROL_BITS_TiledResourceMode_start 13 static inline uint32_t ATTRIBUTE_PURE VDENC_SURFACE_CONTROL_BITS_TiledResourceMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 13; case 120: return 13; case 110: return 13; case 90: return 13; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VDENC_SURFACE_STATE_FIELDS */ #define GFX125_VDENC_SURFACE_STATE_FIELDS_length 4 #define GFX12_VDENC_SURFACE_STATE_FIELDS_length 4 #define GFX11_VDENC_SURFACE_STATE_FIELDS_length 4 #define GFX9_VDENC_SURFACE_STATE_FIELDS_length 4 static inline uint32_t ATTRIBUTE_PURE VDENC_SURFACE_STATE_FIELDS_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VDENC_SURFACE_STATE_FIELDS::Chroma Downsample Filter Control */ #define GFX125_VDENC_SURFACE_STATE_FIELDS_ChromaDownsampleFilterControl_bits 3 #define GFX12_VDENC_SURFACE_STATE_FIELDS_ChromaDownsampleFilterControl_bits 3 #define GFX11_VDENC_SURFACE_STATE_FIELDS_ChromaDownsampleFilterControl_bits 3 static inline uint32_t ATTRIBUTE_PURE VDENC_SURFACE_STATE_FIELDS_ChromaDownsampleFilterControl_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_VDENC_SURFACE_STATE_FIELDS_ChromaDownsampleFilterControl_start 52 #define GFX12_VDENC_SURFACE_STATE_FIELDS_ChromaDownsampleFilterControl_start 52 #define GFX11_VDENC_SURFACE_STATE_FIELDS_ChromaDownsampleFilterControl_start 52 static inline uint32_t ATTRIBUTE_PURE VDENC_SURFACE_STATE_FIELDS_ChromaDownsampleFilterControl_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 52; case 120: return 52; case 110: return 52; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VDENC_SURFACE_STATE_FIELDS::Color space selection */ #define GFX125_VDENC_SURFACE_STATE_FIELDS_Colorspaceselection_bits 1 #define GFX12_VDENC_SURFACE_STATE_FIELDS_Colorspaceselection_bits 1 #define GFX11_VDENC_SURFACE_STATE_FIELDS_Colorspaceselection_bits 1 #define GFX9_VDENC_SURFACE_STATE_FIELDS_Colorspaceselection_bits 1 static inline uint32_t ATTRIBUTE_PURE VDENC_SURFACE_STATE_FIELDS_Colorspaceselection_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_VDENC_SURFACE_STATE_FIELDS_Colorspaceselection_start 3 #define GFX12_VDENC_SURFACE_STATE_FIELDS_Colorspaceselection_start 3 #define GFX11_VDENC_SURFACE_STATE_FIELDS_Colorspaceselection_start 3 #define GFX9_VDENC_SURFACE_STATE_FIELDS_Colorspaceselection_start 3 static inline uint32_t ATTRIBUTE_PURE VDENC_SURFACE_STATE_FIELDS_Colorspaceselection_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VDENC_SURFACE_STATE_FIELDS::Cr(V)/Cb(U) Pixel Offset V Direction */ #define GFX125_VDENC_SURFACE_STATE_FIELDS_CrVCbUPixelOffsetVDirection_bits 2 #define GFX12_VDENC_SURFACE_STATE_FIELDS_CrVCbUPixelOffsetVDirection_bits 2 #define GFX11_VDENC_SURFACE_STATE_FIELDS_CrVCbUPixelOffsetVDirection_bits 2 #define GFX9_VDENC_SURFACE_STATE_FIELDS_CrVCbUPixelOffsetVDirection_bits 2 static inline uint32_t ATTRIBUTE_PURE VDENC_SURFACE_STATE_FIELDS_CrVCbUPixelOffsetVDirection_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_VDENC_SURFACE_STATE_FIELDS_CrVCbUPixelOffsetVDirection_start 0 #define GFX12_VDENC_SURFACE_STATE_FIELDS_CrVCbUPixelOffsetVDirection_start 0 #define GFX11_VDENC_SURFACE_STATE_FIELDS_CrVCbUPixelOffsetVDirection_start 0 #define GFX9_VDENC_SURFACE_STATE_FIELDS_CrVCbUPixelOffsetVDirection_start 0 static inline uint32_t ATTRIBUTE_PURE VDENC_SURFACE_STATE_FIELDS_CrVCbUPixelOffsetVDirection_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VDENC_SURFACE_STATE_FIELDS::Format */ #define GFX125_VDENC_SURFACE_STATE_FIELDS_Format_bits 5 #define GFX12_VDENC_SURFACE_STATE_FIELDS_Format_bits 5 #define GFX11_VDENC_SURFACE_STATE_FIELDS_Format_bits 5 #define GFX9_VDENC_SURFACE_STATE_FIELDS_Format_bits 5 static inline uint32_t ATTRIBUTE_PURE VDENC_SURFACE_STATE_FIELDS_Format_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 5; case 120: return 5; case 110: return 5; case 90: return 5; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_VDENC_SURFACE_STATE_FIELDS_Format_start 59 #define GFX12_VDENC_SURFACE_STATE_FIELDS_Format_start 59 #define GFX11_VDENC_SURFACE_STATE_FIELDS_Format_start 59 #define GFX9_VDENC_SURFACE_STATE_FIELDS_Format_start 59 static inline uint32_t ATTRIBUTE_PURE VDENC_SURFACE_STATE_FIELDS_Format_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 59; case 120: return 59; case 110: return 59; case 90: return 59; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VDENC_SURFACE_STATE_FIELDS::Half Pitch for Chroma */ #define GFX125_VDENC_SURFACE_STATE_FIELDS_HalfPitchforChroma_bits 1 #define GFX12_VDENC_SURFACE_STATE_FIELDS_HalfPitchforChroma_bits 1 #define GFX11_VDENC_SURFACE_STATE_FIELDS_HalfPitchforChroma_bits 1 #define GFX9_VDENC_SURFACE_STATE_FIELDS_HalfPitchforChroma_bits 1 static inline uint32_t ATTRIBUTE_PURE VDENC_SURFACE_STATE_FIELDS_HalfPitchforChroma_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_VDENC_SURFACE_STATE_FIELDS_HalfPitchforChroma_start 34 #define GFX12_VDENC_SURFACE_STATE_FIELDS_HalfPitchforChroma_start 34 #define GFX11_VDENC_SURFACE_STATE_FIELDS_HalfPitchforChroma_start 34 #define GFX9_VDENC_SURFACE_STATE_FIELDS_HalfPitchforChroma_start 34 static inline uint32_t ATTRIBUTE_PURE VDENC_SURFACE_STATE_FIELDS_HalfPitchforChroma_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 34; case 120: return 34; case 110: return 34; case 90: return 34; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VDENC_SURFACE_STATE_FIELDS::Height */ #define GFX125_VDENC_SURFACE_STATE_FIELDS_Height_bits 14 #define GFX12_VDENC_SURFACE_STATE_FIELDS_Height_bits 14 #define GFX11_VDENC_SURFACE_STATE_FIELDS_Height_bits 14 #define GFX9_VDENC_SURFACE_STATE_FIELDS_Height_bits 14 static inline uint32_t ATTRIBUTE_PURE VDENC_SURFACE_STATE_FIELDS_Height_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 14; case 120: return 14; case 110: return 14; case 90: return 14; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_VDENC_SURFACE_STATE_FIELDS_Height_start 18 #define GFX12_VDENC_SURFACE_STATE_FIELDS_Height_start 18 #define GFX11_VDENC_SURFACE_STATE_FIELDS_Height_start 18 #define GFX9_VDENC_SURFACE_STATE_FIELDS_Height_start 18 static inline uint32_t ATTRIBUTE_PURE VDENC_SURFACE_STATE_FIELDS_Height_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 18; case 120: return 18; case 110: return 18; case 90: return 18; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VDENC_SURFACE_STATE_FIELDS::Surface Format */ #define GFX125_VDENC_SURFACE_STATE_FIELDS_SurfaceFormat_bits 4 #define GFX12_VDENC_SURFACE_STATE_FIELDS_SurfaceFormat_bits 4 #define GFX11_VDENC_SURFACE_STATE_FIELDS_SurfaceFormat_bits 4 #define GFX9_VDENC_SURFACE_STATE_FIELDS_SurfaceFormat_bits 4 static inline uint32_t ATTRIBUTE_PURE VDENC_SURFACE_STATE_FIELDS_SurfaceFormat_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_VDENC_SURFACE_STATE_FIELDS_SurfaceFormat_start 60 #define GFX12_VDENC_SURFACE_STATE_FIELDS_SurfaceFormat_start 60 #define GFX11_VDENC_SURFACE_STATE_FIELDS_SurfaceFormat_start 60 #define GFX9_VDENC_SURFACE_STATE_FIELDS_SurfaceFormat_start 60 static inline uint32_t ATTRIBUTE_PURE VDENC_SURFACE_STATE_FIELDS_SurfaceFormat_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 60; case 120: return 60; case 110: return 60; case 90: return 60; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VDENC_SURFACE_STATE_FIELDS::Surface Format Byte Swizzle */ #define GFX125_VDENC_SURFACE_STATE_FIELDS_SurfaceFormatByteSwizzle_bits 1 #define GFX12_VDENC_SURFACE_STATE_FIELDS_SurfaceFormatByteSwizzle_bits 1 #define GFX11_VDENC_SURFACE_STATE_FIELDS_SurfaceFormatByteSwizzle_bits 1 #define GFX9_VDENC_SURFACE_STATE_FIELDS_SurfaceFormatByteSwizzle_bits 1 static inline uint32_t ATTRIBUTE_PURE VDENC_SURFACE_STATE_FIELDS_SurfaceFormatByteSwizzle_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_VDENC_SURFACE_STATE_FIELDS_SurfaceFormatByteSwizzle_start 2 #define GFX12_VDENC_SURFACE_STATE_FIELDS_SurfaceFormatByteSwizzle_start 2 #define GFX11_VDENC_SURFACE_STATE_FIELDS_SurfaceFormatByteSwizzle_start 2 #define GFX9_VDENC_SURFACE_STATE_FIELDS_SurfaceFormatByteSwizzle_start 2 static inline uint32_t ATTRIBUTE_PURE VDENC_SURFACE_STATE_FIELDS_SurfaceFormatByteSwizzle_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VDENC_SURFACE_STATE_FIELDS::Surface Pitch */ #define GFX125_VDENC_SURFACE_STATE_FIELDS_SurfacePitch_bits 17 #define GFX12_VDENC_SURFACE_STATE_FIELDS_SurfacePitch_bits 17 #define GFX11_VDENC_SURFACE_STATE_FIELDS_SurfacePitch_bits 17 #define GFX9_VDENC_SURFACE_STATE_FIELDS_SurfacePitch_bits 17 static inline uint32_t ATTRIBUTE_PURE VDENC_SURFACE_STATE_FIELDS_SurfacePitch_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 17; case 120: return 17; case 110: return 17; case 90: return 17; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_VDENC_SURFACE_STATE_FIELDS_SurfacePitch_start 35 #define GFX12_VDENC_SURFACE_STATE_FIELDS_SurfacePitch_start 35 #define GFX11_VDENC_SURFACE_STATE_FIELDS_SurfacePitch_start 35 #define GFX9_VDENC_SURFACE_STATE_FIELDS_SurfacePitch_start 35 static inline uint32_t ATTRIBUTE_PURE VDENC_SURFACE_STATE_FIELDS_SurfacePitch_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 35; case 120: return 35; case 110: return 35; case 90: return 35; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VDENC_SURFACE_STATE_FIELDS::Tile Walk */ #define GFX125_VDENC_SURFACE_STATE_FIELDS_TileWalk_bits 1 #define GFX12_VDENC_SURFACE_STATE_FIELDS_TileWalk_bits 1 #define GFX11_VDENC_SURFACE_STATE_FIELDS_TileWalk_bits 1 #define GFX9_VDENC_SURFACE_STATE_FIELDS_TileWalk_bits 1 static inline uint32_t ATTRIBUTE_PURE VDENC_SURFACE_STATE_FIELDS_TileWalk_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_VDENC_SURFACE_STATE_FIELDS_TileWalk_start 32 #define GFX12_VDENC_SURFACE_STATE_FIELDS_TileWalk_start 32 #define GFX11_VDENC_SURFACE_STATE_FIELDS_TileWalk_start 32 #define GFX9_VDENC_SURFACE_STATE_FIELDS_TileWalk_start 32 static inline uint32_t ATTRIBUTE_PURE VDENC_SURFACE_STATE_FIELDS_TileWalk_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VDENC_SURFACE_STATE_FIELDS::Tiled Surface */ #define GFX125_VDENC_SURFACE_STATE_FIELDS_TiledSurface_bits 1 #define GFX12_VDENC_SURFACE_STATE_FIELDS_TiledSurface_bits 1 #define GFX11_VDENC_SURFACE_STATE_FIELDS_TiledSurface_bits 1 #define GFX9_VDENC_SURFACE_STATE_FIELDS_TiledSurface_bits 1 static inline uint32_t ATTRIBUTE_PURE VDENC_SURFACE_STATE_FIELDS_TiledSurface_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_VDENC_SURFACE_STATE_FIELDS_TiledSurface_start 33 #define GFX12_VDENC_SURFACE_STATE_FIELDS_TiledSurface_start 33 #define GFX11_VDENC_SURFACE_STATE_FIELDS_TiledSurface_start 33 #define GFX9_VDENC_SURFACE_STATE_FIELDS_TiledSurface_start 33 static inline uint32_t ATTRIBUTE_PURE VDENC_SURFACE_STATE_FIELDS_TiledSurface_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 33; case 120: return 33; case 110: return 33; case 90: return 33; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VDENC_SURFACE_STATE_FIELDS::Width */ #define GFX125_VDENC_SURFACE_STATE_FIELDS_Width_bits 14 #define GFX12_VDENC_SURFACE_STATE_FIELDS_Width_bits 14 #define GFX11_VDENC_SURFACE_STATE_FIELDS_Width_bits 14 #define GFX9_VDENC_SURFACE_STATE_FIELDS_Width_bits 14 static inline uint32_t ATTRIBUTE_PURE VDENC_SURFACE_STATE_FIELDS_Width_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 14; case 120: return 14; case 110: return 14; case 90: return 14; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_VDENC_SURFACE_STATE_FIELDS_Width_start 4 #define GFX12_VDENC_SURFACE_STATE_FIELDS_Width_start 4 #define GFX11_VDENC_SURFACE_STATE_FIELDS_Width_start 4 #define GFX9_VDENC_SURFACE_STATE_FIELDS_Width_start 4 static inline uint32_t ATTRIBUTE_PURE VDENC_SURFACE_STATE_FIELDS_Width_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VDENC_SURFACE_STATE_FIELDS::X Offset for U(Cb) */ #define GFX125_VDENC_SURFACE_STATE_FIELDS_XOffsetforUCb_bits 15 #define GFX12_VDENC_SURFACE_STATE_FIELDS_XOffsetforUCb_bits 15 #define GFX11_VDENC_SURFACE_STATE_FIELDS_XOffsetforUCb_bits 15 #define GFX9_VDENC_SURFACE_STATE_FIELDS_XOffsetforUCb_bits 15 static inline uint32_t ATTRIBUTE_PURE VDENC_SURFACE_STATE_FIELDS_XOffsetforUCb_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 15; case 120: return 15; case 110: return 15; case 90: return 15; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_VDENC_SURFACE_STATE_FIELDS_XOffsetforUCb_start 80 #define GFX12_VDENC_SURFACE_STATE_FIELDS_XOffsetforUCb_start 80 #define GFX11_VDENC_SURFACE_STATE_FIELDS_XOffsetforUCb_start 80 #define GFX9_VDENC_SURFACE_STATE_FIELDS_XOffsetforUCb_start 80 static inline uint32_t ATTRIBUTE_PURE VDENC_SURFACE_STATE_FIELDS_XOffsetforUCb_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 80; case 120: return 80; case 110: return 80; case 90: return 80; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VDENC_SURFACE_STATE_FIELDS::X Offset for V(Cr) */ #define GFX125_VDENC_SURFACE_STATE_FIELDS_XOffsetforVCr_bits 13 #define GFX12_VDENC_SURFACE_STATE_FIELDS_XOffsetforVCr_bits 13 #define GFX11_VDENC_SURFACE_STATE_FIELDS_XOffsetforVCr_bits 13 #define GFX9_VDENC_SURFACE_STATE_FIELDS_XOffsetforVCr_bits 13 static inline uint32_t ATTRIBUTE_PURE VDENC_SURFACE_STATE_FIELDS_XOffsetforVCr_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 13; case 120: return 13; case 110: return 13; case 90: return 13; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_VDENC_SURFACE_STATE_FIELDS_XOffsetforVCr_start 112 #define GFX12_VDENC_SURFACE_STATE_FIELDS_XOffsetforVCr_start 112 #define GFX11_VDENC_SURFACE_STATE_FIELDS_XOffsetforVCr_start 112 #define GFX9_VDENC_SURFACE_STATE_FIELDS_XOffsetforVCr_start 112 static inline uint32_t ATTRIBUTE_PURE VDENC_SURFACE_STATE_FIELDS_XOffsetforVCr_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 112; case 120: return 112; case 110: return 112; case 90: return 112; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VDENC_SURFACE_STATE_FIELDS::Y Offset for U(Cb) */ #define GFX125_VDENC_SURFACE_STATE_FIELDS_YOffsetforUCb_bits 15 #define GFX12_VDENC_SURFACE_STATE_FIELDS_YOffsetforUCb_bits 15 #define GFX11_VDENC_SURFACE_STATE_FIELDS_YOffsetforUCb_bits 15 #define GFX9_VDENC_SURFACE_STATE_FIELDS_YOffsetforUCb_bits 15 static inline uint32_t ATTRIBUTE_PURE VDENC_SURFACE_STATE_FIELDS_YOffsetforUCb_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 15; case 120: return 15; case 110: return 15; case 90: return 15; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_VDENC_SURFACE_STATE_FIELDS_YOffsetforUCb_start 64 #define GFX12_VDENC_SURFACE_STATE_FIELDS_YOffsetforUCb_start 64 #define GFX11_VDENC_SURFACE_STATE_FIELDS_YOffsetforUCb_start 64 #define GFX9_VDENC_SURFACE_STATE_FIELDS_YOffsetforUCb_start 64 static inline uint32_t ATTRIBUTE_PURE VDENC_SURFACE_STATE_FIELDS_YOffsetforUCb_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 64; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VDENC_SURFACE_STATE_FIELDS::Y Offset for V(Cr) */ #define GFX125_VDENC_SURFACE_STATE_FIELDS_YOffsetforVCr_bits 16 #define GFX12_VDENC_SURFACE_STATE_FIELDS_YOffsetforVCr_bits 16 #define GFX11_VDENC_SURFACE_STATE_FIELDS_YOffsetforVCr_bits 16 #define GFX9_VDENC_SURFACE_STATE_FIELDS_YOffsetforVCr_bits 16 static inline uint32_t ATTRIBUTE_PURE VDENC_SURFACE_STATE_FIELDS_YOffsetforVCr_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_VDENC_SURFACE_STATE_FIELDS_YOffsetforVCr_start 96 #define GFX12_VDENC_SURFACE_STATE_FIELDS_YOffsetforVCr_start 96 #define GFX11_VDENC_SURFACE_STATE_FIELDS_YOffsetforVCr_start 96 #define GFX9_VDENC_SURFACE_STATE_FIELDS_YOffsetforVCr_start 96 static inline uint32_t ATTRIBUTE_PURE VDENC_SURFACE_STATE_FIELDS_YOffsetforVCr_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 96; case 120: return 96; case 110: return 96; case 90: return 96; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VECS_ACTHD_UDW */ #define GFX9_VECS_ACTHD_UDW_length 1 #define GFX8_VECS_ACTHD_UDW_length 1 static inline uint32_t ATTRIBUTE_PURE VECS_ACTHD_UDW_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VECS_ACTHD_UDW::Head Pointer Upper DWORD */ #define GFX9_VECS_ACTHD_UDW_HeadPointerUpperDWORD_bits 16 #define GFX8_VECS_ACTHD_UDW_HeadPointerUpperDWORD_bits 16 static inline uint32_t ATTRIBUTE_PURE VECS_ACTHD_UDW_HeadPointerUpperDWORD_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 16; case 80: return 16; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_VECS_ACTHD_UDW_HeadPointerUpperDWORD_start 0 #define GFX8_VECS_ACTHD_UDW_HeadPointerUpperDWORD_start 0 static inline uint32_t ATTRIBUTE_PURE VECS_ACTHD_UDW_HeadPointerUpperDWORD_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VECS_FAULT_REG */ #define GFX75_VECS_FAULT_REG_length 1 static inline uint32_t ATTRIBUTE_PURE VECS_FAULT_REG_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VECS_FAULT_REG::Fault Type */ #define GFX75_VECS_FAULT_REG_FaultType_bits 2 static inline uint32_t ATTRIBUTE_PURE VECS_FAULT_REG_FaultType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 2; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_VECS_FAULT_REG_FaultType_start 1 static inline uint32_t ATTRIBUTE_PURE VECS_FAULT_REG_FaultType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VECS_FAULT_REG::GTTSEL */ #define GFX75_VECS_FAULT_REG_GTTSEL_bits 1 static inline uint32_t ATTRIBUTE_PURE VECS_FAULT_REG_GTTSEL_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_VECS_FAULT_REG_GTTSEL_start 11 static inline uint32_t ATTRIBUTE_PURE VECS_FAULT_REG_GTTSEL_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 11; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VECS_FAULT_REG::SRCID of Fault */ #define GFX75_VECS_FAULT_REG_SRCIDofFault_bits 8 static inline uint32_t ATTRIBUTE_PURE VECS_FAULT_REG_SRCIDofFault_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 8; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_VECS_FAULT_REG_SRCIDofFault_start 3 static inline uint32_t ATTRIBUTE_PURE VECS_FAULT_REG_SRCIDofFault_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 3; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VECS_FAULT_REG::Valid Bit */ #define GFX75_VECS_FAULT_REG_ValidBit_bits 1 static inline uint32_t ATTRIBUTE_PURE VECS_FAULT_REG_ValidBit_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_VECS_FAULT_REG_ValidBit_start 0 static inline uint32_t ATTRIBUTE_PURE VECS_FAULT_REG_ValidBit_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VECS_FAULT_REG::Virtual Address of Fault */ #define GFX75_VECS_FAULT_REG_VirtualAddressofFault_bits 20 static inline uint32_t ATTRIBUTE_PURE VECS_FAULT_REG_VirtualAddressofFault_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 20; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_VECS_FAULT_REG_VirtualAddressofFault_start 12 static inline uint32_t ATTRIBUTE_PURE VECS_FAULT_REG_VirtualAddressofFault_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 12; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VECS_INSTDONE */ #define GFX9_VECS_INSTDONE_length 1 #define GFX8_VECS_INSTDONE_length 1 #define GFX75_VECS_INSTDONE_length 1 static inline uint32_t ATTRIBUTE_PURE VECS_INSTDONE_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VECS_INSTDONE::GAM Done */ #define GFX9_VECS_INSTDONE_GAMDone_bits 1 #define GFX8_VECS_INSTDONE_GAMDone_bits 1 #define GFX75_VECS_INSTDONE_GAMDone_bits 1 static inline uint32_t ATTRIBUTE_PURE VECS_INSTDONE_GAMDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_VECS_INSTDONE_GAMDone_start 31 #define GFX8_VECS_INSTDONE_GAMDone_start 31 #define GFX75_VECS_INSTDONE_GAMDone_start 31 static inline uint32_t ATTRIBUTE_PURE VECS_INSTDONE_GAMDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 31; case 80: return 31; case 75: return 31; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VECS_INSTDONE::Ring Enable */ #define GFX9_VECS_INSTDONE_RingEnable_bits 1 #define GFX8_VECS_INSTDONE_RingEnable_bits 1 #define GFX75_VECS_INSTDONE_RingEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE VECS_INSTDONE_RingEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_VECS_INSTDONE_RingEnable_start 0 #define GFX8_VECS_INSTDONE_RingEnable_start 0 #define GFX75_VECS_INSTDONE_RingEnable_start 0 static inline uint32_t ATTRIBUTE_PURE VECS_INSTDONE_RingEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VECS_INSTDONE::VECS Done */ #define GFX9_VECS_INSTDONE_VECSDone_bits 1 #define GFX8_VECS_INSTDONE_VECSDone_bits 1 #define GFX75_VECS_INSTDONE_VECSDone_bits 1 static inline uint32_t ATTRIBUTE_PURE VECS_INSTDONE_VECSDone_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_VECS_INSTDONE_VECSDone_start 30 #define GFX8_VECS_INSTDONE_VECSDone_start 30 #define GFX75_VECS_INSTDONE_VECSDone_start 30 static inline uint32_t ATTRIBUTE_PURE VECS_INSTDONE_VECSDone_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 30; case 80: return 30; case 75: return 30; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VECS_RING_BUFFER_CTL */ #define GFX9_VECS_RING_BUFFER_CTL_length 1 #define GFX8_VECS_RING_BUFFER_CTL_length 1 #define GFX75_VECS_RING_BUFFER_CTL_length 1 static inline uint32_t ATTRIBUTE_PURE VECS_RING_BUFFER_CTL_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VECS_RING_BUFFER_CTL::Automatic Report Head Pointer */ #define GFX9_VECS_RING_BUFFER_CTL_AutomaticReportHeadPointer_bits 2 #define GFX8_VECS_RING_BUFFER_CTL_AutomaticReportHeadPointer_bits 2 #define GFX75_VECS_RING_BUFFER_CTL_AutomaticReportHeadPointer_bits 2 static inline uint32_t ATTRIBUTE_PURE VECS_RING_BUFFER_CTL_AutomaticReportHeadPointer_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_VECS_RING_BUFFER_CTL_AutomaticReportHeadPointer_start 1 #define GFX8_VECS_RING_BUFFER_CTL_AutomaticReportHeadPointer_start 1 #define GFX75_VECS_RING_BUFFER_CTL_AutomaticReportHeadPointer_start 1 static inline uint32_t ATTRIBUTE_PURE VECS_RING_BUFFER_CTL_AutomaticReportHeadPointer_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VECS_RING_BUFFER_CTL::Buffer Length (in pages - 1) */ #define GFX9_VECS_RING_BUFFER_CTL_BufferLengthinpages1_bits 9 #define GFX8_VECS_RING_BUFFER_CTL_BufferLengthinpages1_bits 9 #define GFX75_VECS_RING_BUFFER_CTL_BufferLengthinpages1_bits 9 static inline uint32_t ATTRIBUTE_PURE VECS_RING_BUFFER_CTL_BufferLengthinpages1_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 9; case 80: return 9; case 75: return 9; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_VECS_RING_BUFFER_CTL_BufferLengthinpages1_start 12 #define GFX8_VECS_RING_BUFFER_CTL_BufferLengthinpages1_start 12 #define GFX75_VECS_RING_BUFFER_CTL_BufferLengthinpages1_start 12 static inline uint32_t ATTRIBUTE_PURE VECS_RING_BUFFER_CTL_BufferLengthinpages1_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 12; case 80: return 12; case 75: return 12; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VECS_RING_BUFFER_CTL::Disable Register Accesses */ #define GFX9_VECS_RING_BUFFER_CTL_DisableRegisterAccesses_bits 1 #define GFX8_VECS_RING_BUFFER_CTL_DisableRegisterAccesses_bits 1 #define GFX75_VECS_RING_BUFFER_CTL_DisableRegisterAccesses_bits 1 static inline uint32_t ATTRIBUTE_PURE VECS_RING_BUFFER_CTL_DisableRegisterAccesses_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_VECS_RING_BUFFER_CTL_DisableRegisterAccesses_start 8 #define GFX8_VECS_RING_BUFFER_CTL_DisableRegisterAccesses_start 8 #define GFX75_VECS_RING_BUFFER_CTL_DisableRegisterAccesses_start 8 static inline uint32_t ATTRIBUTE_PURE VECS_RING_BUFFER_CTL_DisableRegisterAccesses_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 8; case 80: return 8; case 75: return 8; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VECS_RING_BUFFER_CTL::RBWait */ #define GFX9_VECS_RING_BUFFER_CTL_RBWait_bits 1 #define GFX8_VECS_RING_BUFFER_CTL_RBWait_bits 1 #define GFX75_VECS_RING_BUFFER_CTL_RBWait_bits 1 static inline uint32_t ATTRIBUTE_PURE VECS_RING_BUFFER_CTL_RBWait_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_VECS_RING_BUFFER_CTL_RBWait_start 11 #define GFX8_VECS_RING_BUFFER_CTL_RBWait_start 11 #define GFX75_VECS_RING_BUFFER_CTL_RBWait_start 11 static inline uint32_t ATTRIBUTE_PURE VECS_RING_BUFFER_CTL_RBWait_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 11; case 80: return 11; case 75: return 11; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VECS_RING_BUFFER_CTL::Ring Buffer Enable */ #define GFX9_VECS_RING_BUFFER_CTL_RingBufferEnable_bits 1 #define GFX8_VECS_RING_BUFFER_CTL_RingBufferEnable_bits 1 #define GFX75_VECS_RING_BUFFER_CTL_RingBufferEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE VECS_RING_BUFFER_CTL_RingBufferEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_VECS_RING_BUFFER_CTL_RingBufferEnable_start 0 #define GFX8_VECS_RING_BUFFER_CTL_RingBufferEnable_start 0 #define GFX75_VECS_RING_BUFFER_CTL_RingBufferEnable_start 0 static inline uint32_t ATTRIBUTE_PURE VECS_RING_BUFFER_CTL_RingBufferEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VECS_RING_BUFFER_CTL::Semaphore Wait */ #define GFX9_VECS_RING_BUFFER_CTL_SemaphoreWait_bits 1 #define GFX8_VECS_RING_BUFFER_CTL_SemaphoreWait_bits 1 #define GFX75_VECS_RING_BUFFER_CTL_SemaphoreWait_bits 1 static inline uint32_t ATTRIBUTE_PURE VECS_RING_BUFFER_CTL_SemaphoreWait_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX9_VECS_RING_BUFFER_CTL_SemaphoreWait_start 10 #define GFX8_VECS_RING_BUFFER_CTL_SemaphoreWait_start 10 #define GFX75_VECS_RING_BUFFER_CTL_SemaphoreWait_start 10 static inline uint32_t ATTRIBUTE_PURE VECS_RING_BUFFER_CTL_SemaphoreWait_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 10; case 80: return 10; case 75: return 10; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VERTEX_BUFFER_STATE */ #define GFX125_VERTEX_BUFFER_STATE_length 4 #define GFX12_VERTEX_BUFFER_STATE_length 4 #define GFX11_VERTEX_BUFFER_STATE_length 4 #define GFX9_VERTEX_BUFFER_STATE_length 4 #define GFX8_VERTEX_BUFFER_STATE_length 4 #define GFX75_VERTEX_BUFFER_STATE_length 4 #define GFX7_VERTEX_BUFFER_STATE_length 4 #define GFX6_VERTEX_BUFFER_STATE_length 4 #define GFX5_VERTEX_BUFFER_STATE_length 4 #define GFX45_VERTEX_BUFFER_STATE_length 4 #define GFX4_VERTEX_BUFFER_STATE_length 4 static inline uint32_t ATTRIBUTE_PURE VERTEX_BUFFER_STATE_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 4; case 120: return 4; case 110: return 4; case 90: return 4; case 80: return 4; case 75: return 4; case 70: return 4; case 60: return 4; case 50: return 4; case 45: return 4; case 40: return 4; default: unreachable("Invalid hardware generation"); } } /* VERTEX_BUFFER_STATE::Address Modify Enable */ #define GFX125_VERTEX_BUFFER_STATE_AddressModifyEnable_bits 1 #define GFX12_VERTEX_BUFFER_STATE_AddressModifyEnable_bits 1 #define GFX11_VERTEX_BUFFER_STATE_AddressModifyEnable_bits 1 #define GFX9_VERTEX_BUFFER_STATE_AddressModifyEnable_bits 1 #define GFX8_VERTEX_BUFFER_STATE_AddressModifyEnable_bits 1 #define GFX75_VERTEX_BUFFER_STATE_AddressModifyEnable_bits 1 #define GFX7_VERTEX_BUFFER_STATE_AddressModifyEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE VERTEX_BUFFER_STATE_AddressModifyEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_VERTEX_BUFFER_STATE_AddressModifyEnable_start 14 #define GFX12_VERTEX_BUFFER_STATE_AddressModifyEnable_start 14 #define GFX11_VERTEX_BUFFER_STATE_AddressModifyEnable_start 14 #define GFX9_VERTEX_BUFFER_STATE_AddressModifyEnable_start 14 #define GFX8_VERTEX_BUFFER_STATE_AddressModifyEnable_start 14 #define GFX75_VERTEX_BUFFER_STATE_AddressModifyEnable_start 14 #define GFX7_VERTEX_BUFFER_STATE_AddressModifyEnable_start 14 static inline uint32_t ATTRIBUTE_PURE VERTEX_BUFFER_STATE_AddressModifyEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 14; case 120: return 14; case 110: return 14; case 90: return 14; case 80: return 14; case 75: return 14; case 70: return 14; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VERTEX_BUFFER_STATE::Buffer Access Type */ #define GFX75_VERTEX_BUFFER_STATE_BufferAccessType_bits 1 #define GFX7_VERTEX_BUFFER_STATE_BufferAccessType_bits 1 #define GFX6_VERTEX_BUFFER_STATE_BufferAccessType_bits 1 #define GFX5_VERTEX_BUFFER_STATE_BufferAccessType_bits 1 #define GFX45_VERTEX_BUFFER_STATE_BufferAccessType_bits 1 #define GFX4_VERTEX_BUFFER_STATE_BufferAccessType_bits 1 static inline uint32_t ATTRIBUTE_PURE VERTEX_BUFFER_STATE_BufferAccessType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX75_VERTEX_BUFFER_STATE_BufferAccessType_start 20 #define GFX7_VERTEX_BUFFER_STATE_BufferAccessType_start 20 #define GFX6_VERTEX_BUFFER_STATE_BufferAccessType_start 20 #define GFX5_VERTEX_BUFFER_STATE_BufferAccessType_start 26 #define GFX45_VERTEX_BUFFER_STATE_BufferAccessType_start 26 #define GFX4_VERTEX_BUFFER_STATE_BufferAccessType_start 26 static inline uint32_t ATTRIBUTE_PURE VERTEX_BUFFER_STATE_BufferAccessType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 20; case 70: return 20; case 60: return 20; case 50: return 26; case 45: return 26; case 40: return 26; default: unreachable("Invalid hardware generation"); } } /* VERTEX_BUFFER_STATE::Buffer Pitch */ #define GFX125_VERTEX_BUFFER_STATE_BufferPitch_bits 12 #define GFX12_VERTEX_BUFFER_STATE_BufferPitch_bits 12 #define GFX11_VERTEX_BUFFER_STATE_BufferPitch_bits 12 #define GFX9_VERTEX_BUFFER_STATE_BufferPitch_bits 12 #define GFX8_VERTEX_BUFFER_STATE_BufferPitch_bits 12 #define GFX75_VERTEX_BUFFER_STATE_BufferPitch_bits 12 #define GFX7_VERTEX_BUFFER_STATE_BufferPitch_bits 12 #define GFX6_VERTEX_BUFFER_STATE_BufferPitch_bits 12 #define GFX5_VERTEX_BUFFER_STATE_BufferPitch_bits 12 #define GFX45_VERTEX_BUFFER_STATE_BufferPitch_bits 11 #define GFX4_VERTEX_BUFFER_STATE_BufferPitch_bits 11 static inline uint32_t ATTRIBUTE_PURE VERTEX_BUFFER_STATE_BufferPitch_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 12; case 120: return 12; case 110: return 12; case 90: return 12; case 80: return 12; case 75: return 12; case 70: return 12; case 60: return 12; case 50: return 12; case 45: return 11; case 40: return 11; default: unreachable("Invalid hardware generation"); } } #define GFX125_VERTEX_BUFFER_STATE_BufferPitch_start 0 #define GFX12_VERTEX_BUFFER_STATE_BufferPitch_start 0 #define GFX11_VERTEX_BUFFER_STATE_BufferPitch_start 0 #define GFX9_VERTEX_BUFFER_STATE_BufferPitch_start 0 #define GFX8_VERTEX_BUFFER_STATE_BufferPitch_start 0 #define GFX75_VERTEX_BUFFER_STATE_BufferPitch_start 0 #define GFX7_VERTEX_BUFFER_STATE_BufferPitch_start 0 #define GFX6_VERTEX_BUFFER_STATE_BufferPitch_start 0 #define GFX5_VERTEX_BUFFER_STATE_BufferPitch_start 0 #define GFX45_VERTEX_BUFFER_STATE_BufferPitch_start 0 #define GFX4_VERTEX_BUFFER_STATE_BufferPitch_start 0 static inline uint32_t ATTRIBUTE_PURE VERTEX_BUFFER_STATE_BufferPitch_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VERTEX_BUFFER_STATE::Buffer Size */ #define GFX125_VERTEX_BUFFER_STATE_BufferSize_bits 32 #define GFX12_VERTEX_BUFFER_STATE_BufferSize_bits 32 #define GFX11_VERTEX_BUFFER_STATE_BufferSize_bits 32 #define GFX9_VERTEX_BUFFER_STATE_BufferSize_bits 32 #define GFX8_VERTEX_BUFFER_STATE_BufferSize_bits 32 static inline uint32_t ATTRIBUTE_PURE VERTEX_BUFFER_STATE_BufferSize_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_VERTEX_BUFFER_STATE_BufferSize_start 96 #define GFX12_VERTEX_BUFFER_STATE_BufferSize_start 96 #define GFX11_VERTEX_BUFFER_STATE_BufferSize_start 96 #define GFX9_VERTEX_BUFFER_STATE_BufferSize_start 96 #define GFX8_VERTEX_BUFFER_STATE_BufferSize_start 96 static inline uint32_t ATTRIBUTE_PURE VERTEX_BUFFER_STATE_BufferSize_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 96; case 120: return 96; case 110: return 96; case 90: return 96; case 80: return 96; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VERTEX_BUFFER_STATE::Buffer Starting Address */ #define GFX125_VERTEX_BUFFER_STATE_BufferStartingAddress_bits 64 #define GFX12_VERTEX_BUFFER_STATE_BufferStartingAddress_bits 64 #define GFX11_VERTEX_BUFFER_STATE_BufferStartingAddress_bits 64 #define GFX9_VERTEX_BUFFER_STATE_BufferStartingAddress_bits 64 #define GFX8_VERTEX_BUFFER_STATE_BufferStartingAddress_bits 64 #define GFX75_VERTEX_BUFFER_STATE_BufferStartingAddress_bits 32 #define GFX7_VERTEX_BUFFER_STATE_BufferStartingAddress_bits 32 #define GFX6_VERTEX_BUFFER_STATE_BufferStartingAddress_bits 32 #define GFX5_VERTEX_BUFFER_STATE_BufferStartingAddress_bits 32 #define GFX45_VERTEX_BUFFER_STATE_BufferStartingAddress_bits 32 #define GFX4_VERTEX_BUFFER_STATE_BufferStartingAddress_bits 32 static inline uint32_t ATTRIBUTE_PURE VERTEX_BUFFER_STATE_BufferStartingAddress_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 64; case 80: return 64; case 75: return 32; case 70: return 32; case 60: return 32; case 50: return 32; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } #define GFX125_VERTEX_BUFFER_STATE_BufferStartingAddress_start 32 #define GFX12_VERTEX_BUFFER_STATE_BufferStartingAddress_start 32 #define GFX11_VERTEX_BUFFER_STATE_BufferStartingAddress_start 32 #define GFX9_VERTEX_BUFFER_STATE_BufferStartingAddress_start 32 #define GFX8_VERTEX_BUFFER_STATE_BufferStartingAddress_start 32 #define GFX75_VERTEX_BUFFER_STATE_BufferStartingAddress_start 32 #define GFX7_VERTEX_BUFFER_STATE_BufferStartingAddress_start 32 #define GFX6_VERTEX_BUFFER_STATE_BufferStartingAddress_start 32 #define GFX5_VERTEX_BUFFER_STATE_BufferStartingAddress_start 32 #define GFX45_VERTEX_BUFFER_STATE_BufferStartingAddress_start 32 #define GFX4_VERTEX_BUFFER_STATE_BufferStartingAddress_start 32 static inline uint32_t ATTRIBUTE_PURE VERTEX_BUFFER_STATE_BufferStartingAddress_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 32; case 120: return 32; case 110: return 32; case 90: return 32; case 80: return 32; case 75: return 32; case 70: return 32; case 60: return 32; case 50: return 32; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } /* VERTEX_BUFFER_STATE::End Address */ #define GFX75_VERTEX_BUFFER_STATE_EndAddress_bits 32 #define GFX7_VERTEX_BUFFER_STATE_EndAddress_bits 32 #define GFX6_VERTEX_BUFFER_STATE_EndAddress_bits 32 #define GFX5_VERTEX_BUFFER_STATE_EndAddress_bits 32 static inline uint32_t ATTRIBUTE_PURE VERTEX_BUFFER_STATE_EndAddress_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 32; case 70: return 32; case 60: return 32; case 50: return 32; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_VERTEX_BUFFER_STATE_EndAddress_start 64 #define GFX7_VERTEX_BUFFER_STATE_EndAddress_start 64 #define GFX6_VERTEX_BUFFER_STATE_EndAddress_start 64 #define GFX5_VERTEX_BUFFER_STATE_EndAddress_start 64 static inline uint32_t ATTRIBUTE_PURE VERTEX_BUFFER_STATE_EndAddress_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 64; case 70: return 64; case 60: return 64; case 50: return 64; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VERTEX_BUFFER_STATE::Instance Data Step Rate */ #define GFX75_VERTEX_BUFFER_STATE_InstanceDataStepRate_bits 32 #define GFX7_VERTEX_BUFFER_STATE_InstanceDataStepRate_bits 32 #define GFX6_VERTEX_BUFFER_STATE_InstanceDataStepRate_bits 32 #define GFX5_VERTEX_BUFFER_STATE_InstanceDataStepRate_bits 32 #define GFX45_VERTEX_BUFFER_STATE_InstanceDataStepRate_bits 32 #define GFX4_VERTEX_BUFFER_STATE_InstanceDataStepRate_bits 32 static inline uint32_t ATTRIBUTE_PURE VERTEX_BUFFER_STATE_InstanceDataStepRate_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 32; case 70: return 32; case 60: return 32; case 50: return 32; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } #define GFX75_VERTEX_BUFFER_STATE_InstanceDataStepRate_start 96 #define GFX7_VERTEX_BUFFER_STATE_InstanceDataStepRate_start 96 #define GFX6_VERTEX_BUFFER_STATE_InstanceDataStepRate_start 96 #define GFX5_VERTEX_BUFFER_STATE_InstanceDataStepRate_start 96 #define GFX45_VERTEX_BUFFER_STATE_InstanceDataStepRate_start 96 #define GFX4_VERTEX_BUFFER_STATE_InstanceDataStepRate_start 96 static inline uint32_t ATTRIBUTE_PURE VERTEX_BUFFER_STATE_InstanceDataStepRate_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 96; case 70: return 96; case 60: return 96; case 50: return 96; case 45: return 96; case 40: return 96; default: unreachable("Invalid hardware generation"); } } /* VERTEX_BUFFER_STATE::L3 Bypass Disable */ #define GFX125_VERTEX_BUFFER_STATE_L3BypassDisable_bits 1 #define GFX12_VERTEX_BUFFER_STATE_L3BypassDisable_bits 1 static inline uint32_t ATTRIBUTE_PURE VERTEX_BUFFER_STATE_L3BypassDisable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_VERTEX_BUFFER_STATE_L3BypassDisable_start 25 #define GFX12_VERTEX_BUFFER_STATE_L3BypassDisable_start 25 static inline uint32_t ATTRIBUTE_PURE VERTEX_BUFFER_STATE_L3BypassDisable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 25; case 120: return 25; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VERTEX_BUFFER_STATE::MOCS */ #define GFX125_VERTEX_BUFFER_STATE_MOCS_bits 7 #define GFX12_VERTEX_BUFFER_STATE_MOCS_bits 7 #define GFX11_VERTEX_BUFFER_STATE_MOCS_bits 7 #define GFX9_VERTEX_BUFFER_STATE_MOCS_bits 7 #define GFX8_VERTEX_BUFFER_STATE_MOCS_bits 7 #define GFX75_VERTEX_BUFFER_STATE_MOCS_bits 4 #define GFX7_VERTEX_BUFFER_STATE_MOCS_bits 4 #define GFX6_VERTEX_BUFFER_STATE_MOCS_bits 4 static inline uint32_t ATTRIBUTE_PURE VERTEX_BUFFER_STATE_MOCS_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 7; case 120: return 7; case 110: return 7; case 90: return 7; case 80: return 7; case 75: return 4; case 70: return 4; case 60: return 4; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_VERTEX_BUFFER_STATE_MOCS_start 16 #define GFX12_VERTEX_BUFFER_STATE_MOCS_start 16 #define GFX11_VERTEX_BUFFER_STATE_MOCS_start 16 #define GFX9_VERTEX_BUFFER_STATE_MOCS_start 16 #define GFX8_VERTEX_BUFFER_STATE_MOCS_start 16 #define GFX75_VERTEX_BUFFER_STATE_MOCS_start 16 #define GFX7_VERTEX_BUFFER_STATE_MOCS_start 16 #define GFX6_VERTEX_BUFFER_STATE_MOCS_start 16 static inline uint32_t ATTRIBUTE_PURE VERTEX_BUFFER_STATE_MOCS_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 16; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VERTEX_BUFFER_STATE::Max Index */ #define GFX45_VERTEX_BUFFER_STATE_MaxIndex_bits 32 #define GFX4_VERTEX_BUFFER_STATE_MaxIndex_bits 32 static inline uint32_t ATTRIBUTE_PURE VERTEX_BUFFER_STATE_MaxIndex_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } #define GFX45_VERTEX_BUFFER_STATE_MaxIndex_start 64 #define GFX4_VERTEX_BUFFER_STATE_MaxIndex_start 64 static inline uint32_t ATTRIBUTE_PURE VERTEX_BUFFER_STATE_MaxIndex_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 64; case 40: return 64; default: unreachable("Invalid hardware generation"); } } /* VERTEX_BUFFER_STATE::Null Vertex Buffer */ #define GFX125_VERTEX_BUFFER_STATE_NullVertexBuffer_bits 1 #define GFX12_VERTEX_BUFFER_STATE_NullVertexBuffer_bits 1 #define GFX11_VERTEX_BUFFER_STATE_NullVertexBuffer_bits 1 #define GFX9_VERTEX_BUFFER_STATE_NullVertexBuffer_bits 1 #define GFX8_VERTEX_BUFFER_STATE_NullVertexBuffer_bits 1 #define GFX75_VERTEX_BUFFER_STATE_NullVertexBuffer_bits 1 #define GFX7_VERTEX_BUFFER_STATE_NullVertexBuffer_bits 1 #define GFX6_VERTEX_BUFFER_STATE_NullVertexBuffer_bits 1 #define GFX5_VERTEX_BUFFER_STATE_NullVertexBuffer_bits 1 static inline uint32_t ATTRIBUTE_PURE VERTEX_BUFFER_STATE_NullVertexBuffer_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 1; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_VERTEX_BUFFER_STATE_NullVertexBuffer_start 13 #define GFX12_VERTEX_BUFFER_STATE_NullVertexBuffer_start 13 #define GFX11_VERTEX_BUFFER_STATE_NullVertexBuffer_start 13 #define GFX9_VERTEX_BUFFER_STATE_NullVertexBuffer_start 13 #define GFX8_VERTEX_BUFFER_STATE_NullVertexBuffer_start 13 #define GFX75_VERTEX_BUFFER_STATE_NullVertexBuffer_start 13 #define GFX7_VERTEX_BUFFER_STATE_NullVertexBuffer_start 13 #define GFX6_VERTEX_BUFFER_STATE_NullVertexBuffer_start 13 #define GFX5_VERTEX_BUFFER_STATE_NullVertexBuffer_start 13 static inline uint32_t ATTRIBUTE_PURE VERTEX_BUFFER_STATE_NullVertexBuffer_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 13; case 120: return 13; case 110: return 13; case 90: return 13; case 80: return 13; case 75: return 13; case 70: return 13; case 60: return 13; case 50: return 13; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VERTEX_BUFFER_STATE::Vertex Buffer Index */ #define GFX125_VERTEX_BUFFER_STATE_VertexBufferIndex_bits 6 #define GFX12_VERTEX_BUFFER_STATE_VertexBufferIndex_bits 6 #define GFX11_VERTEX_BUFFER_STATE_VertexBufferIndex_bits 6 #define GFX9_VERTEX_BUFFER_STATE_VertexBufferIndex_bits 6 #define GFX8_VERTEX_BUFFER_STATE_VertexBufferIndex_bits 6 #define GFX75_VERTEX_BUFFER_STATE_VertexBufferIndex_bits 6 #define GFX7_VERTEX_BUFFER_STATE_VertexBufferIndex_bits 6 #define GFX6_VERTEX_BUFFER_STATE_VertexBufferIndex_bits 6 #define GFX5_VERTEX_BUFFER_STATE_VertexBufferIndex_bits 5 #define GFX45_VERTEX_BUFFER_STATE_VertexBufferIndex_bits 5 #define GFX4_VERTEX_BUFFER_STATE_VertexBufferIndex_bits 5 static inline uint32_t ATTRIBUTE_PURE VERTEX_BUFFER_STATE_VertexBufferIndex_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 6; case 60: return 6; case 50: return 5; case 45: return 5; case 40: return 5; default: unreachable("Invalid hardware generation"); } } #define GFX125_VERTEX_BUFFER_STATE_VertexBufferIndex_start 26 #define GFX12_VERTEX_BUFFER_STATE_VertexBufferIndex_start 26 #define GFX11_VERTEX_BUFFER_STATE_VertexBufferIndex_start 26 #define GFX9_VERTEX_BUFFER_STATE_VertexBufferIndex_start 26 #define GFX8_VERTEX_BUFFER_STATE_VertexBufferIndex_start 26 #define GFX75_VERTEX_BUFFER_STATE_VertexBufferIndex_start 26 #define GFX7_VERTEX_BUFFER_STATE_VertexBufferIndex_start 26 #define GFX6_VERTEX_BUFFER_STATE_VertexBufferIndex_start 26 #define GFX5_VERTEX_BUFFER_STATE_VertexBufferIndex_start 27 #define GFX45_VERTEX_BUFFER_STATE_VertexBufferIndex_start 27 #define GFX4_VERTEX_BUFFER_STATE_VertexBufferIndex_start 27 static inline uint32_t ATTRIBUTE_PURE VERTEX_BUFFER_STATE_VertexBufferIndex_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 26; case 120: return 26; case 110: return 26; case 90: return 26; case 80: return 26; case 75: return 26; case 70: return 26; case 60: return 26; case 50: return 27; case 45: return 27; case 40: return 27; default: unreachable("Invalid hardware generation"); } } /* VERTEX_BUFFER_STATE::Vertex Fetch Invalidate */ #define GFX75_VERTEX_BUFFER_STATE_VertexFetchInvalidate_bits 1 #define GFX7_VERTEX_BUFFER_STATE_VertexFetchInvalidate_bits 1 #define GFX6_VERTEX_BUFFER_STATE_VertexFetchInvalidate_bits 1 static inline uint32_t ATTRIBUTE_PURE VERTEX_BUFFER_STATE_VertexFetchInvalidate_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX75_VERTEX_BUFFER_STATE_VertexFetchInvalidate_start 12 #define GFX7_VERTEX_BUFFER_STATE_VertexFetchInvalidate_start 12 #define GFX6_VERTEX_BUFFER_STATE_VertexFetchInvalidate_start 12 static inline uint32_t ATTRIBUTE_PURE VERTEX_BUFFER_STATE_VertexFetchInvalidate_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 12; case 70: return 12; case 60: return 12; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VERTEX_ELEMENT_STATE */ #define GFX125_VERTEX_ELEMENT_STATE_length 2 #define GFX12_VERTEX_ELEMENT_STATE_length 2 #define GFX11_VERTEX_ELEMENT_STATE_length 2 #define GFX9_VERTEX_ELEMENT_STATE_length 2 #define GFX8_VERTEX_ELEMENT_STATE_length 2 #define GFX75_VERTEX_ELEMENT_STATE_length 2 #define GFX7_VERTEX_ELEMENT_STATE_length 2 #define GFX6_VERTEX_ELEMENT_STATE_length 2 #define GFX5_VERTEX_ELEMENT_STATE_length 2 #define GFX45_VERTEX_ELEMENT_STATE_length 2 #define GFX4_VERTEX_ELEMENT_STATE_length 2 static inline uint32_t ATTRIBUTE_PURE VERTEX_ELEMENT_STATE_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 2; case 50: return 2; case 45: return 2; case 40: return 2; default: unreachable("Invalid hardware generation"); } } /* VERTEX_ELEMENT_STATE::Component 0 Control */ #define GFX125_VERTEX_ELEMENT_STATE_Component0Control_bits 3 #define GFX12_VERTEX_ELEMENT_STATE_Component0Control_bits 3 #define GFX11_VERTEX_ELEMENT_STATE_Component0Control_bits 3 #define GFX9_VERTEX_ELEMENT_STATE_Component0Control_bits 3 #define GFX8_VERTEX_ELEMENT_STATE_Component0Control_bits 3 #define GFX75_VERTEX_ELEMENT_STATE_Component0Control_bits 3 #define GFX7_VERTEX_ELEMENT_STATE_Component0Control_bits 3 #define GFX6_VERTEX_ELEMENT_STATE_Component0Control_bits 3 #define GFX5_VERTEX_ELEMENT_STATE_Component0Control_bits 3 #define GFX45_VERTEX_ELEMENT_STATE_Component0Control_bits 3 #define GFX4_VERTEX_ELEMENT_STATE_Component0Control_bits 3 static inline uint32_t ATTRIBUTE_PURE VERTEX_ELEMENT_STATE_Component0Control_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX125_VERTEX_ELEMENT_STATE_Component0Control_start 60 #define GFX12_VERTEX_ELEMENT_STATE_Component0Control_start 60 #define GFX11_VERTEX_ELEMENT_STATE_Component0Control_start 60 #define GFX9_VERTEX_ELEMENT_STATE_Component0Control_start 60 #define GFX8_VERTEX_ELEMENT_STATE_Component0Control_start 60 #define GFX75_VERTEX_ELEMENT_STATE_Component0Control_start 60 #define GFX7_VERTEX_ELEMENT_STATE_Component0Control_start 60 #define GFX6_VERTEX_ELEMENT_STATE_Component0Control_start 60 #define GFX5_VERTEX_ELEMENT_STATE_Component0Control_start 60 #define GFX45_VERTEX_ELEMENT_STATE_Component0Control_start 60 #define GFX4_VERTEX_ELEMENT_STATE_Component0Control_start 60 static inline uint32_t ATTRIBUTE_PURE VERTEX_ELEMENT_STATE_Component0Control_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 60; case 120: return 60; case 110: return 60; case 90: return 60; case 80: return 60; case 75: return 60; case 70: return 60; case 60: return 60; case 50: return 60; case 45: return 60; case 40: return 60; default: unreachable("Invalid hardware generation"); } } /* VERTEX_ELEMENT_STATE::Component 1 Control */ #define GFX125_VERTEX_ELEMENT_STATE_Component1Control_bits 3 #define GFX12_VERTEX_ELEMENT_STATE_Component1Control_bits 3 #define GFX11_VERTEX_ELEMENT_STATE_Component1Control_bits 3 #define GFX9_VERTEX_ELEMENT_STATE_Component1Control_bits 3 #define GFX8_VERTEX_ELEMENT_STATE_Component1Control_bits 3 #define GFX75_VERTEX_ELEMENT_STATE_Component1Control_bits 3 #define GFX7_VERTEX_ELEMENT_STATE_Component1Control_bits 3 #define GFX6_VERTEX_ELEMENT_STATE_Component1Control_bits 3 #define GFX5_VERTEX_ELEMENT_STATE_Component1Control_bits 3 #define GFX45_VERTEX_ELEMENT_STATE_Component1Control_bits 3 #define GFX4_VERTEX_ELEMENT_STATE_Component1Control_bits 3 static inline uint32_t ATTRIBUTE_PURE VERTEX_ELEMENT_STATE_Component1Control_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX125_VERTEX_ELEMENT_STATE_Component1Control_start 56 #define GFX12_VERTEX_ELEMENT_STATE_Component1Control_start 56 #define GFX11_VERTEX_ELEMENT_STATE_Component1Control_start 56 #define GFX9_VERTEX_ELEMENT_STATE_Component1Control_start 56 #define GFX8_VERTEX_ELEMENT_STATE_Component1Control_start 56 #define GFX75_VERTEX_ELEMENT_STATE_Component1Control_start 56 #define GFX7_VERTEX_ELEMENT_STATE_Component1Control_start 56 #define GFX6_VERTEX_ELEMENT_STATE_Component1Control_start 56 #define GFX5_VERTEX_ELEMENT_STATE_Component1Control_start 56 #define GFX45_VERTEX_ELEMENT_STATE_Component1Control_start 56 #define GFX4_VERTEX_ELEMENT_STATE_Component1Control_start 56 static inline uint32_t ATTRIBUTE_PURE VERTEX_ELEMENT_STATE_Component1Control_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 56; case 120: return 56; case 110: return 56; case 90: return 56; case 80: return 56; case 75: return 56; case 70: return 56; case 60: return 56; case 50: return 56; case 45: return 56; case 40: return 56; default: unreachable("Invalid hardware generation"); } } /* VERTEX_ELEMENT_STATE::Component 2 Control */ #define GFX125_VERTEX_ELEMENT_STATE_Component2Control_bits 3 #define GFX12_VERTEX_ELEMENT_STATE_Component2Control_bits 3 #define GFX11_VERTEX_ELEMENT_STATE_Component2Control_bits 3 #define GFX9_VERTEX_ELEMENT_STATE_Component2Control_bits 3 #define GFX8_VERTEX_ELEMENT_STATE_Component2Control_bits 3 #define GFX75_VERTEX_ELEMENT_STATE_Component2Control_bits 3 #define GFX7_VERTEX_ELEMENT_STATE_Component2Control_bits 3 #define GFX6_VERTEX_ELEMENT_STATE_Component2Control_bits 3 #define GFX5_VERTEX_ELEMENT_STATE_Component2Control_bits 3 #define GFX45_VERTEX_ELEMENT_STATE_Component2Control_bits 3 #define GFX4_VERTEX_ELEMENT_STATE_Component2Control_bits 3 static inline uint32_t ATTRIBUTE_PURE VERTEX_ELEMENT_STATE_Component2Control_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX125_VERTEX_ELEMENT_STATE_Component2Control_start 52 #define GFX12_VERTEX_ELEMENT_STATE_Component2Control_start 52 #define GFX11_VERTEX_ELEMENT_STATE_Component2Control_start 52 #define GFX9_VERTEX_ELEMENT_STATE_Component2Control_start 52 #define GFX8_VERTEX_ELEMENT_STATE_Component2Control_start 52 #define GFX75_VERTEX_ELEMENT_STATE_Component2Control_start 52 #define GFX7_VERTEX_ELEMENT_STATE_Component2Control_start 52 #define GFX6_VERTEX_ELEMENT_STATE_Component2Control_start 52 #define GFX5_VERTEX_ELEMENT_STATE_Component2Control_start 52 #define GFX45_VERTEX_ELEMENT_STATE_Component2Control_start 52 #define GFX4_VERTEX_ELEMENT_STATE_Component2Control_start 52 static inline uint32_t ATTRIBUTE_PURE VERTEX_ELEMENT_STATE_Component2Control_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 52; case 120: return 52; case 110: return 52; case 90: return 52; case 80: return 52; case 75: return 52; case 70: return 52; case 60: return 52; case 50: return 52; case 45: return 52; case 40: return 52; default: unreachable("Invalid hardware generation"); } } /* VERTEX_ELEMENT_STATE::Component 3 Control */ #define GFX125_VERTEX_ELEMENT_STATE_Component3Control_bits 3 #define GFX12_VERTEX_ELEMENT_STATE_Component3Control_bits 3 #define GFX11_VERTEX_ELEMENT_STATE_Component3Control_bits 3 #define GFX9_VERTEX_ELEMENT_STATE_Component3Control_bits 3 #define GFX8_VERTEX_ELEMENT_STATE_Component3Control_bits 3 #define GFX75_VERTEX_ELEMENT_STATE_Component3Control_bits 3 #define GFX7_VERTEX_ELEMENT_STATE_Component3Control_bits 3 #define GFX6_VERTEX_ELEMENT_STATE_Component3Control_bits 3 #define GFX5_VERTEX_ELEMENT_STATE_Component3Control_bits 3 #define GFX45_VERTEX_ELEMENT_STATE_Component3Control_bits 3 #define GFX4_VERTEX_ELEMENT_STATE_Component3Control_bits 3 static inline uint32_t ATTRIBUTE_PURE VERTEX_ELEMENT_STATE_Component3Control_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 3; case 120: return 3; case 110: return 3; case 90: return 3; case 80: return 3; case 75: return 3; case 70: return 3; case 60: return 3; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX125_VERTEX_ELEMENT_STATE_Component3Control_start 48 #define GFX12_VERTEX_ELEMENT_STATE_Component3Control_start 48 #define GFX11_VERTEX_ELEMENT_STATE_Component3Control_start 48 #define GFX9_VERTEX_ELEMENT_STATE_Component3Control_start 48 #define GFX8_VERTEX_ELEMENT_STATE_Component3Control_start 48 #define GFX75_VERTEX_ELEMENT_STATE_Component3Control_start 48 #define GFX7_VERTEX_ELEMENT_STATE_Component3Control_start 48 #define GFX6_VERTEX_ELEMENT_STATE_Component3Control_start 48 #define GFX5_VERTEX_ELEMENT_STATE_Component3Control_start 48 #define GFX45_VERTEX_ELEMENT_STATE_Component3Control_start 48 #define GFX4_VERTEX_ELEMENT_STATE_Component3Control_start 48 static inline uint32_t ATTRIBUTE_PURE VERTEX_ELEMENT_STATE_Component3Control_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 48; case 120: return 48; case 110: return 48; case 90: return 48; case 80: return 48; case 75: return 48; case 70: return 48; case 60: return 48; case 50: return 48; case 45: return 48; case 40: return 48; default: unreachable("Invalid hardware generation"); } } /* VERTEX_ELEMENT_STATE::Destination Element Offset */ #define GFX5_VERTEX_ELEMENT_STATE_DestinationElementOffset_bits 8 #define GFX45_VERTEX_ELEMENT_STATE_DestinationElementOffset_bits 8 #define GFX4_VERTEX_ELEMENT_STATE_DestinationElementOffset_bits 8 static inline uint32_t ATTRIBUTE_PURE VERTEX_ELEMENT_STATE_DestinationElementOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 8; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } #define GFX5_VERTEX_ELEMENT_STATE_DestinationElementOffset_start 32 #define GFX45_VERTEX_ELEMENT_STATE_DestinationElementOffset_start 32 #define GFX4_VERTEX_ELEMENT_STATE_DestinationElementOffset_start 32 static inline uint32_t ATTRIBUTE_PURE VERTEX_ELEMENT_STATE_DestinationElementOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 32; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } /* VERTEX_ELEMENT_STATE::Edge Flag Enable */ #define GFX125_VERTEX_ELEMENT_STATE_EdgeFlagEnable_bits 1 #define GFX12_VERTEX_ELEMENT_STATE_EdgeFlagEnable_bits 1 #define GFX11_VERTEX_ELEMENT_STATE_EdgeFlagEnable_bits 1 #define GFX9_VERTEX_ELEMENT_STATE_EdgeFlagEnable_bits 1 #define GFX8_VERTEX_ELEMENT_STATE_EdgeFlagEnable_bits 1 #define GFX75_VERTEX_ELEMENT_STATE_EdgeFlagEnable_bits 1 #define GFX7_VERTEX_ELEMENT_STATE_EdgeFlagEnable_bits 1 #define GFX6_VERTEX_ELEMENT_STATE_EdgeFlagEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE VERTEX_ELEMENT_STATE_EdgeFlagEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_VERTEX_ELEMENT_STATE_EdgeFlagEnable_start 15 #define GFX12_VERTEX_ELEMENT_STATE_EdgeFlagEnable_start 15 #define GFX11_VERTEX_ELEMENT_STATE_EdgeFlagEnable_start 15 #define GFX9_VERTEX_ELEMENT_STATE_EdgeFlagEnable_start 15 #define GFX8_VERTEX_ELEMENT_STATE_EdgeFlagEnable_start 15 #define GFX75_VERTEX_ELEMENT_STATE_EdgeFlagEnable_start 15 #define GFX7_VERTEX_ELEMENT_STATE_EdgeFlagEnable_start 15 #define GFX6_VERTEX_ELEMENT_STATE_EdgeFlagEnable_start 15 static inline uint32_t ATTRIBUTE_PURE VERTEX_ELEMENT_STATE_EdgeFlagEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 15; case 120: return 15; case 110: return 15; case 90: return 15; case 80: return 15; case 75: return 15; case 70: return 15; case 60: return 15; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VERTEX_ELEMENT_STATE::Source Element Format */ #define GFX125_VERTEX_ELEMENT_STATE_SourceElementFormat_bits 9 #define GFX12_VERTEX_ELEMENT_STATE_SourceElementFormat_bits 9 #define GFX11_VERTEX_ELEMENT_STATE_SourceElementFormat_bits 9 #define GFX9_VERTEX_ELEMENT_STATE_SourceElementFormat_bits 9 #define GFX8_VERTEX_ELEMENT_STATE_SourceElementFormat_bits 9 #define GFX75_VERTEX_ELEMENT_STATE_SourceElementFormat_bits 9 #define GFX7_VERTEX_ELEMENT_STATE_SourceElementFormat_bits 9 #define GFX6_VERTEX_ELEMENT_STATE_SourceElementFormat_bits 9 #define GFX5_VERTEX_ELEMENT_STATE_SourceElementFormat_bits 9 #define GFX45_VERTEX_ELEMENT_STATE_SourceElementFormat_bits 9 #define GFX4_VERTEX_ELEMENT_STATE_SourceElementFormat_bits 9 static inline uint32_t ATTRIBUTE_PURE VERTEX_ELEMENT_STATE_SourceElementFormat_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 9; case 120: return 9; case 110: return 9; case 90: return 9; case 80: return 9; case 75: return 9; case 70: return 9; case 60: return 9; case 50: return 9; case 45: return 9; case 40: return 9; default: unreachable("Invalid hardware generation"); } } #define GFX125_VERTEX_ELEMENT_STATE_SourceElementFormat_start 16 #define GFX12_VERTEX_ELEMENT_STATE_SourceElementFormat_start 16 #define GFX11_VERTEX_ELEMENT_STATE_SourceElementFormat_start 16 #define GFX9_VERTEX_ELEMENT_STATE_SourceElementFormat_start 16 #define GFX8_VERTEX_ELEMENT_STATE_SourceElementFormat_start 16 #define GFX75_VERTEX_ELEMENT_STATE_SourceElementFormat_start 16 #define GFX7_VERTEX_ELEMENT_STATE_SourceElementFormat_start 16 #define GFX6_VERTEX_ELEMENT_STATE_SourceElementFormat_start 16 #define GFX5_VERTEX_ELEMENT_STATE_SourceElementFormat_start 16 #define GFX45_VERTEX_ELEMENT_STATE_SourceElementFormat_start 16 #define GFX4_VERTEX_ELEMENT_STATE_SourceElementFormat_start 16 static inline uint32_t ATTRIBUTE_PURE VERTEX_ELEMENT_STATE_SourceElementFormat_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 16; case 120: return 16; case 110: return 16; case 90: return 16; case 80: return 16; case 75: return 16; case 70: return 16; case 60: return 16; case 50: return 16; case 45: return 16; case 40: return 16; default: unreachable("Invalid hardware generation"); } } /* VERTEX_ELEMENT_STATE::Source Element Offset */ #define GFX125_VERTEX_ELEMENT_STATE_SourceElementOffset_bits 12 #define GFX12_VERTEX_ELEMENT_STATE_SourceElementOffset_bits 12 #define GFX11_VERTEX_ELEMENT_STATE_SourceElementOffset_bits 12 #define GFX9_VERTEX_ELEMENT_STATE_SourceElementOffset_bits 12 #define GFX8_VERTEX_ELEMENT_STATE_SourceElementOffset_bits 12 #define GFX75_VERTEX_ELEMENT_STATE_SourceElementOffset_bits 12 #define GFX7_VERTEX_ELEMENT_STATE_SourceElementOffset_bits 12 #define GFX6_VERTEX_ELEMENT_STATE_SourceElementOffset_bits 12 #define GFX5_VERTEX_ELEMENT_STATE_SourceElementOffset_bits 11 #define GFX45_VERTEX_ELEMENT_STATE_SourceElementOffset_bits 11 #define GFX4_VERTEX_ELEMENT_STATE_SourceElementOffset_bits 11 static inline uint32_t ATTRIBUTE_PURE VERTEX_ELEMENT_STATE_SourceElementOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 12; case 120: return 12; case 110: return 12; case 90: return 12; case 80: return 12; case 75: return 12; case 70: return 12; case 60: return 12; case 50: return 11; case 45: return 11; case 40: return 11; default: unreachable("Invalid hardware generation"); } } #define GFX125_VERTEX_ELEMENT_STATE_SourceElementOffset_start 0 #define GFX12_VERTEX_ELEMENT_STATE_SourceElementOffset_start 0 #define GFX11_VERTEX_ELEMENT_STATE_SourceElementOffset_start 0 #define GFX9_VERTEX_ELEMENT_STATE_SourceElementOffset_start 0 #define GFX8_VERTEX_ELEMENT_STATE_SourceElementOffset_start 0 #define GFX75_VERTEX_ELEMENT_STATE_SourceElementOffset_start 0 #define GFX7_VERTEX_ELEMENT_STATE_SourceElementOffset_start 0 #define GFX6_VERTEX_ELEMENT_STATE_SourceElementOffset_start 0 #define GFX5_VERTEX_ELEMENT_STATE_SourceElementOffset_start 0 #define GFX45_VERTEX_ELEMENT_STATE_SourceElementOffset_start 0 #define GFX4_VERTEX_ELEMENT_STATE_SourceElementOffset_start 0 static inline uint32_t ATTRIBUTE_PURE VERTEX_ELEMENT_STATE_SourceElementOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VERTEX_ELEMENT_STATE::Valid */ #define GFX125_VERTEX_ELEMENT_STATE_Valid_bits 1 #define GFX12_VERTEX_ELEMENT_STATE_Valid_bits 1 #define GFX11_VERTEX_ELEMENT_STATE_Valid_bits 1 #define GFX9_VERTEX_ELEMENT_STATE_Valid_bits 1 #define GFX8_VERTEX_ELEMENT_STATE_Valid_bits 1 #define GFX75_VERTEX_ELEMENT_STATE_Valid_bits 1 #define GFX7_VERTEX_ELEMENT_STATE_Valid_bits 1 #define GFX6_VERTEX_ELEMENT_STATE_Valid_bits 1 #define GFX5_VERTEX_ELEMENT_STATE_Valid_bits 1 #define GFX45_VERTEX_ELEMENT_STATE_Valid_bits 1 #define GFX4_VERTEX_ELEMENT_STATE_Valid_bits 1 static inline uint32_t ATTRIBUTE_PURE VERTEX_ELEMENT_STATE_Valid_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 1; case 120: return 1; case 110: return 1; case 90: return 1; case 80: return 1; case 75: return 1; case 70: return 1; case 60: return 1; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX125_VERTEX_ELEMENT_STATE_Valid_start 25 #define GFX12_VERTEX_ELEMENT_STATE_Valid_start 25 #define GFX11_VERTEX_ELEMENT_STATE_Valid_start 25 #define GFX9_VERTEX_ELEMENT_STATE_Valid_start 25 #define GFX8_VERTEX_ELEMENT_STATE_Valid_start 25 #define GFX75_VERTEX_ELEMENT_STATE_Valid_start 25 #define GFX7_VERTEX_ELEMENT_STATE_Valid_start 25 #define GFX6_VERTEX_ELEMENT_STATE_Valid_start 25 #define GFX5_VERTEX_ELEMENT_STATE_Valid_start 26 #define GFX45_VERTEX_ELEMENT_STATE_Valid_start 26 #define GFX4_VERTEX_ELEMENT_STATE_Valid_start 26 static inline uint32_t ATTRIBUTE_PURE VERTEX_ELEMENT_STATE_Valid_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 25; case 120: return 25; case 110: return 25; case 90: return 25; case 80: return 25; case 75: return 25; case 70: return 25; case 60: return 25; case 50: return 26; case 45: return 26; case 40: return 26; default: unreachable("Invalid hardware generation"); } } /* VERTEX_ELEMENT_STATE::Vertex Buffer Index */ #define GFX125_VERTEX_ELEMENT_STATE_VertexBufferIndex_bits 6 #define GFX12_VERTEX_ELEMENT_STATE_VertexBufferIndex_bits 6 #define GFX11_VERTEX_ELEMENT_STATE_VertexBufferIndex_bits 6 #define GFX9_VERTEX_ELEMENT_STATE_VertexBufferIndex_bits 6 #define GFX8_VERTEX_ELEMENT_STATE_VertexBufferIndex_bits 6 #define GFX75_VERTEX_ELEMENT_STATE_VertexBufferIndex_bits 6 #define GFX7_VERTEX_ELEMENT_STATE_VertexBufferIndex_bits 6 #define GFX6_VERTEX_ELEMENT_STATE_VertexBufferIndex_bits 6 #define GFX5_VERTEX_ELEMENT_STATE_VertexBufferIndex_bits 5 #define GFX45_VERTEX_ELEMENT_STATE_VertexBufferIndex_bits 5 #define GFX4_VERTEX_ELEMENT_STATE_VertexBufferIndex_bits 5 static inline uint32_t ATTRIBUTE_PURE VERTEX_ELEMENT_STATE_VertexBufferIndex_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 6; case 120: return 6; case 110: return 6; case 90: return 6; case 80: return 6; case 75: return 6; case 70: return 6; case 60: return 6; case 50: return 5; case 45: return 5; case 40: return 5; default: unreachable("Invalid hardware generation"); } } #define GFX125_VERTEX_ELEMENT_STATE_VertexBufferIndex_start 26 #define GFX12_VERTEX_ELEMENT_STATE_VertexBufferIndex_start 26 #define GFX11_VERTEX_ELEMENT_STATE_VertexBufferIndex_start 26 #define GFX9_VERTEX_ELEMENT_STATE_VertexBufferIndex_start 26 #define GFX8_VERTEX_ELEMENT_STATE_VertexBufferIndex_start 26 #define GFX75_VERTEX_ELEMENT_STATE_VertexBufferIndex_start 26 #define GFX7_VERTEX_ELEMENT_STATE_VertexBufferIndex_start 26 #define GFX6_VERTEX_ELEMENT_STATE_VertexBufferIndex_start 26 #define GFX5_VERTEX_ELEMENT_STATE_VertexBufferIndex_start 27 #define GFX45_VERTEX_ELEMENT_STATE_VertexBufferIndex_start 27 #define GFX4_VERTEX_ELEMENT_STATE_VertexBufferIndex_start 27 static inline uint32_t ATTRIBUTE_PURE VERTEX_ELEMENT_STATE_VertexBufferIndex_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 26; case 120: return 26; case 110: return 26; case 90: return 26; case 80: return 26; case 75: return 26; case 70: return 26; case 60: return 26; case 50: return 27; case 45: return 27; case 40: return 27; default: unreachable("Invalid hardware generation"); } } /* VS_INVOCATION_COUNT */ #define GFX125_VS_INVOCATION_COUNT_length 2 #define GFX12_VS_INVOCATION_COUNT_length 2 #define GFX11_VS_INVOCATION_COUNT_length 2 #define GFX9_VS_INVOCATION_COUNT_length 2 #define GFX8_VS_INVOCATION_COUNT_length 2 #define GFX75_VS_INVOCATION_COUNT_length 2 #define GFX7_VS_INVOCATION_COUNT_length 2 static inline uint32_t ATTRIBUTE_PURE VS_INVOCATION_COUNT_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 2; case 120: return 2; case 110: return 2; case 90: return 2; case 80: return 2; case 75: return 2; case 70: return 2; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VS_INVOCATION_COUNT::VS Invocation Count Report */ #define GFX125_VS_INVOCATION_COUNT_VSInvocationCountReport_bits 64 #define GFX12_VS_INVOCATION_COUNT_VSInvocationCountReport_bits 64 #define GFX11_VS_INVOCATION_COUNT_VSInvocationCountReport_bits 64 #define GFX9_VS_INVOCATION_COUNT_VSInvocationCountReport_bits 64 #define GFX8_VS_INVOCATION_COUNT_VSInvocationCountReport_bits 64 #define GFX75_VS_INVOCATION_COUNT_VSInvocationCountReport_bits 64 #define GFX7_VS_INVOCATION_COUNT_VSInvocationCountReport_bits 64 static inline uint32_t ATTRIBUTE_PURE VS_INVOCATION_COUNT_VSInvocationCountReport_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 64; case 120: return 64; case 110: return 64; case 90: return 64; case 80: return 64; case 75: return 64; case 70: return 64; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX125_VS_INVOCATION_COUNT_VSInvocationCountReport_start 0 #define GFX12_VS_INVOCATION_COUNT_VSInvocationCountReport_start 0 #define GFX11_VS_INVOCATION_COUNT_VSInvocationCountReport_start 0 #define GFX9_VS_INVOCATION_COUNT_VSInvocationCountReport_start 0 #define GFX8_VS_INVOCATION_COUNT_VSInvocationCountReport_start 0 #define GFX75_VS_INVOCATION_COUNT_VSInvocationCountReport_start 0 #define GFX7_VS_INVOCATION_COUNT_VSInvocationCountReport_start 0 static inline uint32_t ATTRIBUTE_PURE VS_INVOCATION_COUNT_VSInvocationCountReport_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* VS_STATE */ #define GFX5_VS_STATE_length 7 #define GFX45_VS_STATE_length 7 #define GFX4_VS_STATE_length 7 static inline uint32_t ATTRIBUTE_PURE VS_STATE_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 7; case 45: return 7; case 40: return 7; default: unreachable("Invalid hardware generation"); } } /* VS_STATE::Binding Table Entry Count */ #define GFX5_VS_STATE_BindingTableEntryCount_bits 8 #define GFX45_VS_STATE_BindingTableEntryCount_bits 8 #define GFX4_VS_STATE_BindingTableEntryCount_bits 8 static inline uint32_t ATTRIBUTE_PURE VS_STATE_BindingTableEntryCount_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 8; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } #define GFX5_VS_STATE_BindingTableEntryCount_start 50 #define GFX45_VS_STATE_BindingTableEntryCount_start 50 #define GFX4_VS_STATE_BindingTableEntryCount_start 50 static inline uint32_t ATTRIBUTE_PURE VS_STATE_BindingTableEntryCount_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 50; case 45: return 50; case 40: return 50; default: unreachable("Invalid hardware generation"); } } /* VS_STATE::Constant URB Entry Read Length */ #define GFX5_VS_STATE_ConstantURBEntryReadLength_bits 6 #define GFX45_VS_STATE_ConstantURBEntryReadLength_bits 6 #define GFX4_VS_STATE_ConstantURBEntryReadLength_bits 6 static inline uint32_t ATTRIBUTE_PURE VS_STATE_ConstantURBEntryReadLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 6; case 45: return 6; case 40: return 6; default: unreachable("Invalid hardware generation"); } } #define GFX5_VS_STATE_ConstantURBEntryReadLength_start 121 #define GFX45_VS_STATE_ConstantURBEntryReadLength_start 121 #define GFX4_VS_STATE_ConstantURBEntryReadLength_start 121 static inline uint32_t ATTRIBUTE_PURE VS_STATE_ConstantURBEntryReadLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 121; case 45: return 121; case 40: return 121; default: unreachable("Invalid hardware generation"); } } /* VS_STATE::Constant URB Entry Read Offset */ #define GFX5_VS_STATE_ConstantURBEntryReadOffset_bits 6 #define GFX45_VS_STATE_ConstantURBEntryReadOffset_bits 6 #define GFX4_VS_STATE_ConstantURBEntryReadOffset_bits 6 static inline uint32_t ATTRIBUTE_PURE VS_STATE_ConstantURBEntryReadOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 6; case 45: return 6; case 40: return 6; default: unreachable("Invalid hardware generation"); } } #define GFX5_VS_STATE_ConstantURBEntryReadOffset_start 114 #define GFX45_VS_STATE_ConstantURBEntryReadOffset_start 114 #define GFX4_VS_STATE_ConstantURBEntryReadOffset_start 114 static inline uint32_t ATTRIBUTE_PURE VS_STATE_ConstantURBEntryReadOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 114; case 45: return 114; case 40: return 114; default: unreachable("Invalid hardware generation"); } } /* VS_STATE::Dispatch GRF Start Register For URB Data */ #define GFX5_VS_STATE_DispatchGRFStartRegisterForURBData_bits 4 #define GFX45_VS_STATE_DispatchGRFStartRegisterForURBData_bits 4 #define GFX4_VS_STATE_DispatchGRFStartRegisterForURBData_bits 4 static inline uint32_t ATTRIBUTE_PURE VS_STATE_DispatchGRFStartRegisterForURBData_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 4; case 45: return 4; case 40: return 4; default: unreachable("Invalid hardware generation"); } } #define GFX5_VS_STATE_DispatchGRFStartRegisterForURBData_start 96 #define GFX45_VS_STATE_DispatchGRFStartRegisterForURBData_start 96 #define GFX4_VS_STATE_DispatchGRFStartRegisterForURBData_start 96 static inline uint32_t ATTRIBUTE_PURE VS_STATE_DispatchGRFStartRegisterForURBData_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 96; case 45: return 96; case 40: return 96; default: unreachable("Invalid hardware generation"); } } /* VS_STATE::Enable */ #define GFX5_VS_STATE_Enable_bits 1 #define GFX45_VS_STATE_Enable_bits 1 #define GFX4_VS_STATE_Enable_bits 1 static inline uint32_t ATTRIBUTE_PURE VS_STATE_Enable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_VS_STATE_Enable_start 192 #define GFX45_VS_STATE_Enable_start 192 #define GFX4_VS_STATE_Enable_start 192 static inline uint32_t ATTRIBUTE_PURE VS_STATE_Enable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 192; case 45: return 192; case 40: return 192; default: unreachable("Invalid hardware generation"); } } /* VS_STATE::Floating Point Mode */ #define GFX5_VS_STATE_FloatingPointMode_bits 1 #define GFX45_VS_STATE_FloatingPointMode_bits 1 #define GFX4_VS_STATE_FloatingPointMode_bits 1 static inline uint32_t ATTRIBUTE_PURE VS_STATE_FloatingPointMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_VS_STATE_FloatingPointMode_start 48 #define GFX45_VS_STATE_FloatingPointMode_start 48 #define GFX4_VS_STATE_FloatingPointMode_start 48 static inline uint32_t ATTRIBUTE_PURE VS_STATE_FloatingPointMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 48; case 45: return 48; case 40: return 48; default: unreachable("Invalid hardware generation"); } } /* VS_STATE::GRF Register Count */ #define GFX5_VS_STATE_GRFRegisterCount_bits 3 #define GFX45_VS_STATE_GRFRegisterCount_bits 3 #define GFX4_VS_STATE_GRFRegisterCount_bits 3 static inline uint32_t ATTRIBUTE_PURE VS_STATE_GRFRegisterCount_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX5_VS_STATE_GRFRegisterCount_start 1 #define GFX45_VS_STATE_GRFRegisterCount_start 1 #define GFX4_VS_STATE_GRFRegisterCount_start 1 static inline uint32_t ATTRIBUTE_PURE VS_STATE_GRFRegisterCount_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } /* VS_STATE::Illegal Opcode Exception Enable */ #define GFX5_VS_STATE_IllegalOpcodeExceptionEnable_bits 1 #define GFX45_VS_STATE_IllegalOpcodeExceptionEnable_bits 1 #define GFX4_VS_STATE_IllegalOpcodeExceptionEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE VS_STATE_IllegalOpcodeExceptionEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_VS_STATE_IllegalOpcodeExceptionEnable_start 45 #define GFX45_VS_STATE_IllegalOpcodeExceptionEnable_start 45 #define GFX4_VS_STATE_IllegalOpcodeExceptionEnable_start 45 static inline uint32_t ATTRIBUTE_PURE VS_STATE_IllegalOpcodeExceptionEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 45; case 45: return 45; case 40: return 45; default: unreachable("Invalid hardware generation"); } } /* VS_STATE::Kernel Start Pointer */ #define GFX5_VS_STATE_KernelStartPointer_bits 26 #define GFX45_VS_STATE_KernelStartPointer_bits 26 #define GFX4_VS_STATE_KernelStartPointer_bits 26 static inline uint32_t ATTRIBUTE_PURE VS_STATE_KernelStartPointer_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 26; case 45: return 26; case 40: return 26; default: unreachable("Invalid hardware generation"); } } #define GFX5_VS_STATE_KernelStartPointer_start 6 #define GFX45_VS_STATE_KernelStartPointer_start 6 #define GFX4_VS_STATE_KernelStartPointer_start 6 static inline uint32_t ATTRIBUTE_PURE VS_STATE_KernelStartPointer_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 6; case 45: return 6; case 40: return 6; default: unreachable("Invalid hardware generation"); } } /* VS_STATE::Mask Stack Exception Enable */ #define GFX5_VS_STATE_MaskStackExceptionEnable_bits 1 #define GFX45_VS_STATE_MaskStackExceptionEnable_bits 1 #define GFX4_VS_STATE_MaskStackExceptionEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE VS_STATE_MaskStackExceptionEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_VS_STATE_MaskStackExceptionEnable_start 43 #define GFX45_VS_STATE_MaskStackExceptionEnable_start 43 #define GFX4_VS_STATE_MaskStackExceptionEnable_start 43 static inline uint32_t ATTRIBUTE_PURE VS_STATE_MaskStackExceptionEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 43; case 45: return 43; case 40: return 43; default: unreachable("Invalid hardware generation"); } } /* VS_STATE::Maximum Number of Threads */ #define GFX5_VS_STATE_MaximumNumberofThreads_bits 6 #define GFX45_VS_STATE_MaximumNumberofThreads_bits 6 #define GFX4_VS_STATE_MaximumNumberofThreads_bits 6 static inline uint32_t ATTRIBUTE_PURE VS_STATE_MaximumNumberofThreads_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 6; case 45: return 6; case 40: return 6; default: unreachable("Invalid hardware generation"); } } #define GFX5_VS_STATE_MaximumNumberofThreads_start 153 #define GFX45_VS_STATE_MaximumNumberofThreads_start 153 #define GFX4_VS_STATE_MaximumNumberofThreads_start 153 static inline uint32_t ATTRIBUTE_PURE VS_STATE_MaximumNumberofThreads_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 153; case 45: return 153; case 40: return 153; default: unreachable("Invalid hardware generation"); } } /* VS_STATE::Number of URB Entries */ #define GFX5_VS_STATE_NumberofURBEntries_bits 8 #define GFX45_VS_STATE_NumberofURBEntries_bits 8 #define GFX4_VS_STATE_NumberofURBEntries_bits 8 static inline uint32_t ATTRIBUTE_PURE VS_STATE_NumberofURBEntries_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 8; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } #define GFX5_VS_STATE_NumberofURBEntries_start 139 #define GFX45_VS_STATE_NumberofURBEntries_start 139 #define GFX4_VS_STATE_NumberofURBEntries_start 139 static inline uint32_t ATTRIBUTE_PURE VS_STATE_NumberofURBEntries_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 139; case 45: return 139; case 40: return 139; default: unreachable("Invalid hardware generation"); } } /* VS_STATE::Per-Thread Scratch Space */ #define GFX5_VS_STATE_PerThreadScratchSpace_bits 4 #define GFX45_VS_STATE_PerThreadScratchSpace_bits 4 #define GFX4_VS_STATE_PerThreadScratchSpace_bits 4 static inline uint32_t ATTRIBUTE_PURE VS_STATE_PerThreadScratchSpace_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 4; case 45: return 4; case 40: return 4; default: unreachable("Invalid hardware generation"); } } #define GFX5_VS_STATE_PerThreadScratchSpace_start 64 #define GFX45_VS_STATE_PerThreadScratchSpace_start 64 #define GFX4_VS_STATE_PerThreadScratchSpace_start 64 static inline uint32_t ATTRIBUTE_PURE VS_STATE_PerThreadScratchSpace_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 64; case 45: return 64; case 40: return 64; default: unreachable("Invalid hardware generation"); } } /* VS_STATE::Sampler Count */ #define GFX5_VS_STATE_SamplerCount_bits 3 #define GFX45_VS_STATE_SamplerCount_bits 3 #define GFX4_VS_STATE_SamplerCount_bits 3 static inline uint32_t ATTRIBUTE_PURE VS_STATE_SamplerCount_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX5_VS_STATE_SamplerCount_start 160 #define GFX45_VS_STATE_SamplerCount_start 160 #define GFX4_VS_STATE_SamplerCount_start 160 static inline uint32_t ATTRIBUTE_PURE VS_STATE_SamplerCount_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 160; case 45: return 160; case 40: return 160; default: unreachable("Invalid hardware generation"); } } /* VS_STATE::Sampler State Pointer */ #define GFX5_VS_STATE_SamplerStatePointer_bits 27 #define GFX45_VS_STATE_SamplerStatePointer_bits 27 #define GFX4_VS_STATE_SamplerStatePointer_bits 27 static inline uint32_t ATTRIBUTE_PURE VS_STATE_SamplerStatePointer_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 27; case 45: return 27; case 40: return 27; default: unreachable("Invalid hardware generation"); } } #define GFX5_VS_STATE_SamplerStatePointer_start 165 #define GFX45_VS_STATE_SamplerStatePointer_start 165 #define GFX4_VS_STATE_SamplerStatePointer_start 165 static inline uint32_t ATTRIBUTE_PURE VS_STATE_SamplerStatePointer_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 165; case 45: return 165; case 40: return 165; default: unreachable("Invalid hardware generation"); } } /* VS_STATE::Scratch Space Base Pointer */ #define GFX5_VS_STATE_ScratchSpaceBasePointer_bits 22 #define GFX45_VS_STATE_ScratchSpaceBasePointer_bits 22 #define GFX4_VS_STATE_ScratchSpaceBasePointer_bits 22 static inline uint32_t ATTRIBUTE_PURE VS_STATE_ScratchSpaceBasePointer_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 22; case 45: return 22; case 40: return 22; default: unreachable("Invalid hardware generation"); } } #define GFX5_VS_STATE_ScratchSpaceBasePointer_start 74 #define GFX45_VS_STATE_ScratchSpaceBasePointer_start 74 #define GFX4_VS_STATE_ScratchSpaceBasePointer_start 74 static inline uint32_t ATTRIBUTE_PURE VS_STATE_ScratchSpaceBasePointer_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 74; case 45: return 74; case 40: return 74; default: unreachable("Invalid hardware generation"); } } /* VS_STATE::Single Program Flow */ #define GFX5_VS_STATE_SingleProgramFlow_bits 1 #define GFX45_VS_STATE_SingleProgramFlow_bits 1 #define GFX4_VS_STATE_SingleProgramFlow_bits 1 static inline uint32_t ATTRIBUTE_PURE VS_STATE_SingleProgramFlow_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_VS_STATE_SingleProgramFlow_start 63 #define GFX45_VS_STATE_SingleProgramFlow_start 63 #define GFX4_VS_STATE_SingleProgramFlow_start 63 static inline uint32_t ATTRIBUTE_PURE VS_STATE_SingleProgramFlow_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 63; case 45: return 63; case 40: return 63; default: unreachable("Invalid hardware generation"); } } /* VS_STATE::Software Exception Enable */ #define GFX5_VS_STATE_SoftwareExceptionEnable_bits 1 #define GFX45_VS_STATE_SoftwareExceptionEnable_bits 1 #define GFX4_VS_STATE_SoftwareExceptionEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE VS_STATE_SoftwareExceptionEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_VS_STATE_SoftwareExceptionEnable_start 39 #define GFX45_VS_STATE_SoftwareExceptionEnable_start 39 #define GFX4_VS_STATE_SoftwareExceptionEnable_start 39 static inline uint32_t ATTRIBUTE_PURE VS_STATE_SoftwareExceptionEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 39; case 45: return 39; case 40: return 39; default: unreachable("Invalid hardware generation"); } } /* VS_STATE::Statistics Enable */ #define GFX5_VS_STATE_StatisticsEnable_bits 1 #define GFX45_VS_STATE_StatisticsEnable_bits 1 #define GFX4_VS_STATE_StatisticsEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE VS_STATE_StatisticsEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_VS_STATE_StatisticsEnable_start 138 #define GFX45_VS_STATE_StatisticsEnable_start 138 #define GFX4_VS_STATE_StatisticsEnable_start 138 static inline uint32_t ATTRIBUTE_PURE VS_STATE_StatisticsEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 138; case 45: return 138; case 40: return 138; default: unreachable("Invalid hardware generation"); } } /* VS_STATE::Thread Priority */ #define GFX5_VS_STATE_ThreadPriority_bits 1 #define GFX45_VS_STATE_ThreadPriority_bits 1 #define GFX4_VS_STATE_ThreadPriority_bits 1 static inline uint32_t ATTRIBUTE_PURE VS_STATE_ThreadPriority_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_VS_STATE_ThreadPriority_start 49 #define GFX45_VS_STATE_ThreadPriority_start 49 #define GFX4_VS_STATE_ThreadPriority_start 49 static inline uint32_t ATTRIBUTE_PURE VS_STATE_ThreadPriority_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 49; case 45: return 49; case 40: return 49; default: unreachable("Invalid hardware generation"); } } /* VS_STATE::URB Entry Allocation Size */ #define GFX5_VS_STATE_URBEntryAllocationSize_bits 5 #define GFX45_VS_STATE_URBEntryAllocationSize_bits 5 #define GFX4_VS_STATE_URBEntryAllocationSize_bits 5 static inline uint32_t ATTRIBUTE_PURE VS_STATE_URBEntryAllocationSize_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 5; case 45: return 5; case 40: return 5; default: unreachable("Invalid hardware generation"); } } #define GFX5_VS_STATE_URBEntryAllocationSize_start 147 #define GFX45_VS_STATE_URBEntryAllocationSize_start 147 #define GFX4_VS_STATE_URBEntryAllocationSize_start 147 static inline uint32_t ATTRIBUTE_PURE VS_STATE_URBEntryAllocationSize_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 147; case 45: return 147; case 40: return 147; default: unreachable("Invalid hardware generation"); } } /* VS_STATE::Vertex Cache Disable */ #define GFX5_VS_STATE_VertexCacheDisable_bits 1 #define GFX45_VS_STATE_VertexCacheDisable_bits 1 #define GFX4_VS_STATE_VertexCacheDisable_bits 1 static inline uint32_t ATTRIBUTE_PURE VS_STATE_VertexCacheDisable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_VS_STATE_VertexCacheDisable_start 193 #define GFX45_VS_STATE_VertexCacheDisable_start 193 #define GFX4_VS_STATE_VertexCacheDisable_start 193 static inline uint32_t ATTRIBUTE_PURE VS_STATE_VertexCacheDisable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 193; case 45: return 193; case 40: return 193; default: unreachable("Invalid hardware generation"); } } /* VS_STATE::Vertex URB Entry Read Length */ #define GFX5_VS_STATE_VertexURBEntryReadLength_bits 6 #define GFX45_VS_STATE_VertexURBEntryReadLength_bits 6 #define GFX4_VS_STATE_VertexURBEntryReadLength_bits 6 static inline uint32_t ATTRIBUTE_PURE VS_STATE_VertexURBEntryReadLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 6; case 45: return 6; case 40: return 6; default: unreachable("Invalid hardware generation"); } } #define GFX5_VS_STATE_VertexURBEntryReadLength_start 107 #define GFX45_VS_STATE_VertexURBEntryReadLength_start 107 #define GFX4_VS_STATE_VertexURBEntryReadLength_start 107 static inline uint32_t ATTRIBUTE_PURE VS_STATE_VertexURBEntryReadLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 107; case 45: return 107; case 40: return 107; default: unreachable("Invalid hardware generation"); } } /* VS_STATE::Vertex URB Entry Read Offset */ #define GFX5_VS_STATE_VertexURBEntryReadOffset_bits 6 #define GFX45_VS_STATE_VertexURBEntryReadOffset_bits 6 #define GFX4_VS_STATE_VertexURBEntryReadOffset_bits 6 static inline uint32_t ATTRIBUTE_PURE VS_STATE_VertexURBEntryReadOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 6; case 45: return 6; case 40: return 6; default: unreachable("Invalid hardware generation"); } } #define GFX5_VS_STATE_VertexURBEntryReadOffset_start 100 #define GFX45_VS_STATE_VertexURBEntryReadOffset_start 100 #define GFX4_VS_STATE_VertexURBEntryReadOffset_start 100 static inline uint32_t ATTRIBUTE_PURE VS_STATE_VertexURBEntryReadOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 100; case 45: return 100; case 40: return 100; default: unreachable("Invalid hardware generation"); } } /* WM_STATE */ #define GFX5_WM_STATE_length 11 #define GFX45_WM_STATE_length 8 #define GFX4_WM_STATE_length 8 static inline uint32_t ATTRIBUTE_PURE WM_STATE_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 11; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } /* WM_STATE::16 Pixel Dispatch Enable */ #define GFX5_WM_STATE_16PixelDispatchEnable_bits 1 #define GFX45_WM_STATE_16PixelDispatchEnable_bits 1 #define GFX4_WM_STATE_16PixelDispatchEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE WM_STATE_16PixelDispatchEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_WM_STATE_16PixelDispatchEnable_start 161 #define GFX45_WM_STATE_16PixelDispatchEnable_start 161 #define GFX4_WM_STATE_16PixelDispatchEnable_start 161 static inline uint32_t ATTRIBUTE_PURE WM_STATE_16PixelDispatchEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 161; case 45: return 161; case 40: return 161; default: unreachable("Invalid hardware generation"); } } /* WM_STATE::32 Pixel Dispatch Enable */ #define GFX5_WM_STATE_32PixelDispatchEnable_bits 1 #define GFX45_WM_STATE_32PixelDispatchEnable_bits 1 #define GFX4_WM_STATE_32PixelDispatchEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE WM_STATE_32PixelDispatchEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_WM_STATE_32PixelDispatchEnable_start 162 #define GFX45_WM_STATE_32PixelDispatchEnable_start 162 #define GFX4_WM_STATE_32PixelDispatchEnable_start 162 static inline uint32_t ATTRIBUTE_PURE WM_STATE_32PixelDispatchEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 162; case 45: return 162; case 40: return 162; default: unreachable("Invalid hardware generation"); } } /* WM_STATE::8 Pixel Dispatch Enable */ #define GFX5_WM_STATE_8PixelDispatchEnable_bits 1 #define GFX45_WM_STATE_8PixelDispatchEnable_bits 1 #define GFX4_WM_STATE_8PixelDispatchEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE WM_STATE_8PixelDispatchEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_WM_STATE_8PixelDispatchEnable_start 160 #define GFX45_WM_STATE_8PixelDispatchEnable_start 160 #define GFX4_WM_STATE_8PixelDispatchEnable_start 160 static inline uint32_t ATTRIBUTE_PURE WM_STATE_8PixelDispatchEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 160; case 45: return 160; case 40: return 160; default: unreachable("Invalid hardware generation"); } } /* WM_STATE::Binding Table Entry Count */ #define GFX5_WM_STATE_BindingTableEntryCount_bits 8 #define GFX45_WM_STATE_BindingTableEntryCount_bits 8 #define GFX4_WM_STATE_BindingTableEntryCount_bits 8 static inline uint32_t ATTRIBUTE_PURE WM_STATE_BindingTableEntryCount_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 8; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } #define GFX5_WM_STATE_BindingTableEntryCount_start 50 #define GFX45_WM_STATE_BindingTableEntryCount_start 50 #define GFX4_WM_STATE_BindingTableEntryCount_start 50 static inline uint32_t ATTRIBUTE_PURE WM_STATE_BindingTableEntryCount_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 50; case 45: return 50; case 40: return 50; default: unreachable("Invalid hardware generation"); } } /* WM_STATE::Constant URB Entry Read Length */ #define GFX5_WM_STATE_ConstantURBEntryReadLength_bits 6 #define GFX45_WM_STATE_ConstantURBEntryReadLength_bits 6 #define GFX4_WM_STATE_ConstantURBEntryReadLength_bits 6 static inline uint32_t ATTRIBUTE_PURE WM_STATE_ConstantURBEntryReadLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 6; case 45: return 6; case 40: return 6; default: unreachable("Invalid hardware generation"); } } #define GFX5_WM_STATE_ConstantURBEntryReadLength_start 121 #define GFX45_WM_STATE_ConstantURBEntryReadLength_start 121 #define GFX4_WM_STATE_ConstantURBEntryReadLength_start 121 static inline uint32_t ATTRIBUTE_PURE WM_STATE_ConstantURBEntryReadLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 121; case 45: return 121; case 40: return 121; default: unreachable("Invalid hardware generation"); } } /* WM_STATE::Constant URB Entry Read Offset */ #define GFX5_WM_STATE_ConstantURBEntryReadOffset_bits 6 #define GFX45_WM_STATE_ConstantURBEntryReadOffset_bits 6 #define GFX4_WM_STATE_ConstantURBEntryReadOffset_bits 6 static inline uint32_t ATTRIBUTE_PURE WM_STATE_ConstantURBEntryReadOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 6; case 45: return 6; case 40: return 6; default: unreachable("Invalid hardware generation"); } } #define GFX5_WM_STATE_ConstantURBEntryReadOffset_start 114 #define GFX45_WM_STATE_ConstantURBEntryReadOffset_start 114 #define GFX4_WM_STATE_ConstantURBEntryReadOffset_start 114 static inline uint32_t ATTRIBUTE_PURE WM_STATE_ConstantURBEntryReadOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 114; case 45: return 114; case 40: return 114; default: unreachable("Invalid hardware generation"); } } /* WM_STATE::Contiguous 32 Pixel Dispatch Enable */ #define GFX5_WM_STATE_Contiguous32PixelDispatchEnable_bits 1 #define GFX45_WM_STATE_Contiguous32PixelDispatchEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE WM_STATE_Contiguous32PixelDispatchEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX5_WM_STATE_Contiguous32PixelDispatchEnable_start 163 #define GFX45_WM_STATE_Contiguous32PixelDispatchEnable_start 163 static inline uint32_t ATTRIBUTE_PURE WM_STATE_Contiguous32PixelDispatchEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 163; case 45: return 163; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* WM_STATE::Contiguous 64 Pixel Dispatch Enable */ #define GFX5_WM_STATE_Contiguous64PixelDispatchEnable_bits 1 #define GFX45_WM_STATE_Contiguous64PixelDispatchEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE WM_STATE_Contiguous64PixelDispatchEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX5_WM_STATE_Contiguous64PixelDispatchEnable_start 164 #define GFX45_WM_STATE_Contiguous64PixelDispatchEnable_start 164 static inline uint32_t ATTRIBUTE_PURE WM_STATE_Contiguous64PixelDispatchEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 164; case 45: return 164; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* WM_STATE::Depth Buffer Clear */ #define GFX5_WM_STATE_DepthBufferClear_bits 1 static inline uint32_t ATTRIBUTE_PURE WM_STATE_DepthBufferClear_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX5_WM_STATE_DepthBufferClear_start 167 static inline uint32_t ATTRIBUTE_PURE WM_STATE_DepthBufferClear_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 167; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* WM_STATE::Depth Buffer Resolve Enable */ #define GFX5_WM_STATE_DepthBufferResolveEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE WM_STATE_DepthBufferResolveEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX5_WM_STATE_DepthBufferResolveEnable_start 168 static inline uint32_t ATTRIBUTE_PURE WM_STATE_DepthBufferResolveEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 168; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* WM_STATE::Depth Coefficient URB Read Offset */ #define GFX5_WM_STATE_DepthCoefficientURBReadOffset_bits 6 #define GFX45_WM_STATE_DepthCoefficientURBReadOffset_bits 6 #define GFX4_WM_STATE_DepthCoefficientURBReadOffset_bits 6 static inline uint32_t ATTRIBUTE_PURE WM_STATE_DepthCoefficientURBReadOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 6; case 45: return 6; case 40: return 6; default: unreachable("Invalid hardware generation"); } } #define GFX5_WM_STATE_DepthCoefficientURBReadOffset_start 40 #define GFX45_WM_STATE_DepthCoefficientURBReadOffset_start 40 #define GFX4_WM_STATE_DepthCoefficientURBReadOffset_start 40 static inline uint32_t ATTRIBUTE_PURE WM_STATE_DepthCoefficientURBReadOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 40; case 45: return 40; case 40: return 40; default: unreachable("Invalid hardware generation"); } } /* WM_STATE::Dispatch GRF Start Register For Constant/Setup Data 0 */ #define GFX5_WM_STATE_DispatchGRFStartRegisterForConstantSetupData0_bits 4 #define GFX45_WM_STATE_DispatchGRFStartRegisterForConstantSetupData0_bits 4 #define GFX4_WM_STATE_DispatchGRFStartRegisterForConstantSetupData0_bits 4 static inline uint32_t ATTRIBUTE_PURE WM_STATE_DispatchGRFStartRegisterForConstantSetupData0_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 4; case 45: return 4; case 40: return 4; default: unreachable("Invalid hardware generation"); } } #define GFX5_WM_STATE_DispatchGRFStartRegisterForConstantSetupData0_start 96 #define GFX45_WM_STATE_DispatchGRFStartRegisterForConstantSetupData0_start 96 #define GFX4_WM_STATE_DispatchGRFStartRegisterForConstantSetupData0_start 96 static inline uint32_t ATTRIBUTE_PURE WM_STATE_DispatchGRFStartRegisterForConstantSetupData0_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 96; case 45: return 96; case 40: return 96; default: unreachable("Invalid hardware generation"); } } /* WM_STATE::Early Depth Test Enable */ #define GFX5_WM_STATE_EarlyDepthTestEnable_bits 1 #define GFX45_WM_STATE_EarlyDepthTestEnable_bits 1 #define GFX4_WM_STATE_EarlyDepthTestEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE WM_STATE_EarlyDepthTestEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_WM_STATE_EarlyDepthTestEnable_start 178 #define GFX45_WM_STATE_EarlyDepthTestEnable_start 178 #define GFX4_WM_STATE_EarlyDepthTestEnable_start 178 static inline uint32_t ATTRIBUTE_PURE WM_STATE_EarlyDepthTestEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 178; case 45: return 178; case 40: return 178; default: unreachable("Invalid hardware generation"); } } /* WM_STATE::Fast Span Coverage Enable */ #define GFX5_WM_STATE_FastSpanCoverageEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE WM_STATE_FastSpanCoverageEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX5_WM_STATE_FastSpanCoverageEnable_start 166 static inline uint32_t ATTRIBUTE_PURE WM_STATE_FastSpanCoverageEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 166; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* WM_STATE::Floating Point Mode */ #define GFX5_WM_STATE_FloatingPointMode_bits 1 #define GFX45_WM_STATE_FloatingPointMode_bits 1 #define GFX4_WM_STATE_FloatingPointMode_bits 1 static inline uint32_t ATTRIBUTE_PURE WM_STATE_FloatingPointMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_WM_STATE_FloatingPointMode_start 48 #define GFX45_WM_STATE_FloatingPointMode_start 48 #define GFX4_WM_STATE_FloatingPointMode_start 48 static inline uint32_t ATTRIBUTE_PURE WM_STATE_FloatingPointMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 48; case 45: return 48; case 40: return 48; default: unreachable("Invalid hardware generation"); } } /* WM_STATE::GRF Register Count 0 */ #define GFX5_WM_STATE_GRFRegisterCount0_bits 3 #define GFX45_WM_STATE_GRFRegisterCount0_bits 3 #define GFX4_WM_STATE_GRFRegisterCount0_bits 3 static inline uint32_t ATTRIBUTE_PURE WM_STATE_GRFRegisterCount0_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX5_WM_STATE_GRFRegisterCount0_start 1 #define GFX45_WM_STATE_GRFRegisterCount0_start 1 #define GFX4_WM_STATE_GRFRegisterCount0_start 1 static inline uint32_t ATTRIBUTE_PURE WM_STATE_GRFRegisterCount0_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } /* WM_STATE::GRF Register Count 1 */ #define GFX5_WM_STATE_GRFRegisterCount1_bits 3 static inline uint32_t ATTRIBUTE_PURE WM_STATE_GRFRegisterCount1_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 3; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX5_WM_STATE_GRFRegisterCount1_start 257 static inline uint32_t ATTRIBUTE_PURE WM_STATE_GRFRegisterCount1_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 257; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* WM_STATE::GRF Register Count 2 */ #define GFX5_WM_STATE_GRFRegisterCount2_bits 3 static inline uint32_t ATTRIBUTE_PURE WM_STATE_GRFRegisterCount2_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 3; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX5_WM_STATE_GRFRegisterCount2_start 289 static inline uint32_t ATTRIBUTE_PURE WM_STATE_GRFRegisterCount2_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 289; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* WM_STATE::GRF Register Count 3 */ #define GFX5_WM_STATE_GRFRegisterCount3_bits 3 static inline uint32_t ATTRIBUTE_PURE WM_STATE_GRFRegisterCount3_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 3; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX5_WM_STATE_GRFRegisterCount3_start 321 static inline uint32_t ATTRIBUTE_PURE WM_STATE_GRFRegisterCount3_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 321; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* WM_STATE::Global Depth Offset Constant */ #define GFX5_WM_STATE_GlobalDepthOffsetConstant_bits 32 #define GFX45_WM_STATE_GlobalDepthOffsetConstant_bits 32 #define GFX4_WM_STATE_GlobalDepthOffsetConstant_bits 32 static inline uint32_t ATTRIBUTE_PURE WM_STATE_GlobalDepthOffsetConstant_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 32; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } #define GFX5_WM_STATE_GlobalDepthOffsetConstant_start 192 #define GFX45_WM_STATE_GlobalDepthOffsetConstant_start 192 #define GFX4_WM_STATE_GlobalDepthOffsetConstant_start 192 static inline uint32_t ATTRIBUTE_PURE WM_STATE_GlobalDepthOffsetConstant_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 192; case 45: return 192; case 40: return 192; default: unreachable("Invalid hardware generation"); } } /* WM_STATE::Global Depth Offset Enable */ #define GFX5_WM_STATE_GlobalDepthOffsetEnable_bits 1 #define GFX45_WM_STATE_GlobalDepthOffsetEnable_bits 1 #define GFX4_WM_STATE_GlobalDepthOffsetEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE WM_STATE_GlobalDepthOffsetEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_WM_STATE_GlobalDepthOffsetEnable_start 172 #define GFX45_WM_STATE_GlobalDepthOffsetEnable_start 172 #define GFX4_WM_STATE_GlobalDepthOffsetEnable_start 172 static inline uint32_t ATTRIBUTE_PURE WM_STATE_GlobalDepthOffsetEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 172; case 45: return 172; case 40: return 172; default: unreachable("Invalid hardware generation"); } } /* WM_STATE::Global Depth Offset Scale */ #define GFX5_WM_STATE_GlobalDepthOffsetScale_bits 32 #define GFX45_WM_STATE_GlobalDepthOffsetScale_bits 32 #define GFX4_WM_STATE_GlobalDepthOffsetScale_bits 32 static inline uint32_t ATTRIBUTE_PURE WM_STATE_GlobalDepthOffsetScale_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 32; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } #define GFX5_WM_STATE_GlobalDepthOffsetScale_start 224 #define GFX45_WM_STATE_GlobalDepthOffsetScale_start 224 #define GFX4_WM_STATE_GlobalDepthOffsetScale_start 224 static inline uint32_t ATTRIBUTE_PURE WM_STATE_GlobalDepthOffsetScale_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 224; case 45: return 224; case 40: return 224; default: unreachable("Invalid hardware generation"); } } /* WM_STATE::Hierarchical Depth Buffer Resolve Enable */ #define GFX5_WM_STATE_HierarchicalDepthBufferResolveEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE WM_STATE_HierarchicalDepthBufferResolveEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX5_WM_STATE_HierarchicalDepthBufferResolveEnable_start 169 static inline uint32_t ATTRIBUTE_PURE WM_STATE_HierarchicalDepthBufferResolveEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 169; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* WM_STATE::Illegal Opcode Exception Enable */ #define GFX5_WM_STATE_IllegalOpcodeExceptionEnable_bits 1 #define GFX45_WM_STATE_IllegalOpcodeExceptionEnable_bits 1 #define GFX4_WM_STATE_IllegalOpcodeExceptionEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE WM_STATE_IllegalOpcodeExceptionEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_WM_STATE_IllegalOpcodeExceptionEnable_start 36 #define GFX45_WM_STATE_IllegalOpcodeExceptionEnable_start 36 #define GFX4_WM_STATE_IllegalOpcodeExceptionEnable_start 36 static inline uint32_t ATTRIBUTE_PURE WM_STATE_IllegalOpcodeExceptionEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 36; case 45: return 36; case 40: return 36; default: unreachable("Invalid hardware generation"); } } /* WM_STATE::Kernel Start Pointer 0 */ #define GFX5_WM_STATE_KernelStartPointer0_bits 26 #define GFX45_WM_STATE_KernelStartPointer0_bits 26 #define GFX4_WM_STATE_KernelStartPointer0_bits 26 static inline uint32_t ATTRIBUTE_PURE WM_STATE_KernelStartPointer0_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 26; case 45: return 26; case 40: return 26; default: unreachable("Invalid hardware generation"); } } #define GFX5_WM_STATE_KernelStartPointer0_start 6 #define GFX45_WM_STATE_KernelStartPointer0_start 6 #define GFX4_WM_STATE_KernelStartPointer0_start 6 static inline uint32_t ATTRIBUTE_PURE WM_STATE_KernelStartPointer0_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 6; case 45: return 6; case 40: return 6; default: unreachable("Invalid hardware generation"); } } /* WM_STATE::Kernel Start Pointer 1 */ #define GFX5_WM_STATE_KernelStartPointer1_bits 26 static inline uint32_t ATTRIBUTE_PURE WM_STATE_KernelStartPointer1_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 26; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX5_WM_STATE_KernelStartPointer1_start 262 static inline uint32_t ATTRIBUTE_PURE WM_STATE_KernelStartPointer1_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 262; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* WM_STATE::Kernel Start Pointer 2 */ #define GFX5_WM_STATE_KernelStartPointer2_bits 26 static inline uint32_t ATTRIBUTE_PURE WM_STATE_KernelStartPointer2_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 26; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX5_WM_STATE_KernelStartPointer2_start 294 static inline uint32_t ATTRIBUTE_PURE WM_STATE_KernelStartPointer2_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 294; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* WM_STATE::Kernel Start Pointer 3 */ #define GFX5_WM_STATE_KernelStartPointer3_bits 26 static inline uint32_t ATTRIBUTE_PURE WM_STATE_KernelStartPointer3_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 26; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } #define GFX5_WM_STATE_KernelStartPointer3_start 326 static inline uint32_t ATTRIBUTE_PURE WM_STATE_KernelStartPointer3_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 326; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* WM_STATE::Legacy Diamond Line Rasterization */ #define GFX5_WM_STATE_LegacyDiamondLineRasterization_bits 1 #define GFX45_WM_STATE_LegacyDiamondLineRasterization_bits 1 #define GFX4_WM_STATE_LegacyDiamondLineRasterization_bits 1 static inline uint32_t ATTRIBUTE_PURE WM_STATE_LegacyDiamondLineRasterization_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_WM_STATE_LegacyDiamondLineRasterization_start 183 #define GFX45_WM_STATE_LegacyDiamondLineRasterization_start 183 #define GFX4_WM_STATE_LegacyDiamondLineRasterization_start 183 static inline uint32_t ATTRIBUTE_PURE WM_STATE_LegacyDiamondLineRasterization_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 183; case 45: return 183; case 40: return 183; default: unreachable("Invalid hardware generation"); } } /* WM_STATE::Legacy Global Depth Bias Enable */ #define GFX5_WM_STATE_LegacyGlobalDepthBiasEnable_bits 1 #define GFX45_WM_STATE_LegacyGlobalDepthBiasEnable_bits 1 #define GFX4_WM_STATE_LegacyGlobalDepthBiasEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE WM_STATE_LegacyGlobalDepthBiasEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_WM_STATE_LegacyGlobalDepthBiasEnable_start 170 #define GFX45_WM_STATE_LegacyGlobalDepthBiasEnable_start 170 #define GFX4_WM_STATE_LegacyGlobalDepthBiasEnable_start 170 static inline uint32_t ATTRIBUTE_PURE WM_STATE_LegacyGlobalDepthBiasEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 170; case 45: return 170; case 40: return 170; default: unreachable("Invalid hardware generation"); } } /* WM_STATE::Line Antialiasing Region Width */ #define GFX5_WM_STATE_LineAntialiasingRegionWidth_bits 2 #define GFX45_WM_STATE_LineAntialiasingRegionWidth_bits 2 #define GFX4_WM_STATE_LineAntialiasingRegionWidth_bits 2 static inline uint32_t ATTRIBUTE_PURE WM_STATE_LineAntialiasingRegionWidth_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 2; case 45: return 2; case 40: return 2; default: unreachable("Invalid hardware generation"); } } #define GFX5_WM_STATE_LineAntialiasingRegionWidth_start 174 #define GFX45_WM_STATE_LineAntialiasingRegionWidth_start 174 #define GFX4_WM_STATE_LineAntialiasingRegionWidth_start 174 static inline uint32_t ATTRIBUTE_PURE WM_STATE_LineAntialiasingRegionWidth_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 174; case 45: return 174; case 40: return 174; default: unreachable("Invalid hardware generation"); } } /* WM_STATE::Line End Cap Antialiasing Region Width */ #define GFX5_WM_STATE_LineEndCapAntialiasingRegionWidth_bits 2 #define GFX45_WM_STATE_LineEndCapAntialiasingRegionWidth_bits 2 #define GFX4_WM_STATE_LineEndCapAntialiasingRegionWidth_bits 2 static inline uint32_t ATTRIBUTE_PURE WM_STATE_LineEndCapAntialiasingRegionWidth_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 2; case 45: return 2; case 40: return 2; default: unreachable("Invalid hardware generation"); } } #define GFX5_WM_STATE_LineEndCapAntialiasingRegionWidth_start 176 #define GFX45_WM_STATE_LineEndCapAntialiasingRegionWidth_start 176 #define GFX4_WM_STATE_LineEndCapAntialiasingRegionWidth_start 176 static inline uint32_t ATTRIBUTE_PURE WM_STATE_LineEndCapAntialiasingRegionWidth_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 176; case 45: return 176; case 40: return 176; default: unreachable("Invalid hardware generation"); } } /* WM_STATE::Line Stipple Enable */ #define GFX5_WM_STATE_LineStippleEnable_bits 1 #define GFX45_WM_STATE_LineStippleEnable_bits 1 #define GFX4_WM_STATE_LineStippleEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE WM_STATE_LineStippleEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_WM_STATE_LineStippleEnable_start 171 #define GFX45_WM_STATE_LineStippleEnable_start 171 #define GFX4_WM_STATE_LineStippleEnable_start 171 static inline uint32_t ATTRIBUTE_PURE WM_STATE_LineStippleEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 171; case 45: return 171; case 40: return 171; default: unreachable("Invalid hardware generation"); } } /* WM_STATE::Mask Stack Exception Enable */ #define GFX5_WM_STATE_MaskStackExceptionEnable_bits 1 #define GFX45_WM_STATE_MaskStackExceptionEnable_bits 1 #define GFX4_WM_STATE_MaskStackExceptionEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE WM_STATE_MaskStackExceptionEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_WM_STATE_MaskStackExceptionEnable_start 34 #define GFX45_WM_STATE_MaskStackExceptionEnable_start 34 #define GFX4_WM_STATE_MaskStackExceptionEnable_start 34 static inline uint32_t ATTRIBUTE_PURE WM_STATE_MaskStackExceptionEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 34; case 45: return 34; case 40: return 34; default: unreachable("Invalid hardware generation"); } } /* WM_STATE::Maximum Number of Threads */ #define GFX5_WM_STATE_MaximumNumberofThreads_bits 7 #define GFX45_WM_STATE_MaximumNumberofThreads_bits 7 #define GFX4_WM_STATE_MaximumNumberofThreads_bits 7 static inline uint32_t ATTRIBUTE_PURE WM_STATE_MaximumNumberofThreads_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 7; case 45: return 7; case 40: return 7; default: unreachable("Invalid hardware generation"); } } #define GFX5_WM_STATE_MaximumNumberofThreads_start 185 #define GFX45_WM_STATE_MaximumNumberofThreads_start 185 #define GFX4_WM_STATE_MaximumNumberofThreads_start 185 static inline uint32_t ATTRIBUTE_PURE WM_STATE_MaximumNumberofThreads_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 185; case 45: return 185; case 40: return 185; default: unreachable("Invalid hardware generation"); } } /* WM_STATE::Per-Thread Scratch Space */ #define GFX5_WM_STATE_PerThreadScratchSpace_bits 4 #define GFX45_WM_STATE_PerThreadScratchSpace_bits 4 #define GFX4_WM_STATE_PerThreadScratchSpace_bits 4 static inline uint32_t ATTRIBUTE_PURE WM_STATE_PerThreadScratchSpace_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 4; case 45: return 4; case 40: return 4; default: unreachable("Invalid hardware generation"); } } #define GFX5_WM_STATE_PerThreadScratchSpace_start 64 #define GFX45_WM_STATE_PerThreadScratchSpace_start 64 #define GFX4_WM_STATE_PerThreadScratchSpace_start 64 static inline uint32_t ATTRIBUTE_PURE WM_STATE_PerThreadScratchSpace_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 64; case 45: return 64; case 40: return 64; default: unreachable("Invalid hardware generation"); } } /* WM_STATE::Pixel Shader Computed Depth */ #define GFX5_WM_STATE_PixelShaderComputedDepth_bits 1 #define GFX45_WM_STATE_PixelShaderComputedDepth_bits 1 #define GFX4_WM_STATE_PixelShaderComputedDepth_bits 1 static inline uint32_t ATTRIBUTE_PURE WM_STATE_PixelShaderComputedDepth_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_WM_STATE_PixelShaderComputedDepth_start 181 #define GFX45_WM_STATE_PixelShaderComputedDepth_start 181 #define GFX4_WM_STATE_PixelShaderComputedDepth_start 181 static inline uint32_t ATTRIBUTE_PURE WM_STATE_PixelShaderComputedDepth_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 181; case 45: return 181; case 40: return 181; default: unreachable("Invalid hardware generation"); } } /* WM_STATE::Pixel Shader Kills Pixel */ #define GFX5_WM_STATE_PixelShaderKillsPixel_bits 1 #define GFX45_WM_STATE_PixelShaderKillsPixel_bits 1 #define GFX4_WM_STATE_PixelShaderKillsPixel_bits 1 static inline uint32_t ATTRIBUTE_PURE WM_STATE_PixelShaderKillsPixel_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_WM_STATE_PixelShaderKillsPixel_start 182 #define GFX45_WM_STATE_PixelShaderKillsPixel_start 182 #define GFX4_WM_STATE_PixelShaderKillsPixel_start 182 static inline uint32_t ATTRIBUTE_PURE WM_STATE_PixelShaderKillsPixel_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 182; case 45: return 182; case 40: return 182; default: unreachable("Invalid hardware generation"); } } /* WM_STATE::Pixel Shader Uses Source Depth */ #define GFX5_WM_STATE_PixelShaderUsesSourceDepth_bits 1 #define GFX45_WM_STATE_PixelShaderUsesSourceDepth_bits 1 #define GFX4_WM_STATE_PixelShaderUsesSourceDepth_bits 1 static inline uint32_t ATTRIBUTE_PURE WM_STATE_PixelShaderUsesSourceDepth_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_WM_STATE_PixelShaderUsesSourceDepth_start 180 #define GFX45_WM_STATE_PixelShaderUsesSourceDepth_start 180 #define GFX4_WM_STATE_PixelShaderUsesSourceDepth_start 180 static inline uint32_t ATTRIBUTE_PURE WM_STATE_PixelShaderUsesSourceDepth_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 180; case 45: return 180; case 40: return 180; default: unreachable("Invalid hardware generation"); } } /* WM_STATE::Polygon Stipple Enable */ #define GFX5_WM_STATE_PolygonStippleEnable_bits 1 #define GFX45_WM_STATE_PolygonStippleEnable_bits 1 #define GFX4_WM_STATE_PolygonStippleEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE WM_STATE_PolygonStippleEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_WM_STATE_PolygonStippleEnable_start 173 #define GFX45_WM_STATE_PolygonStippleEnable_start 173 #define GFX4_WM_STATE_PolygonStippleEnable_start 173 static inline uint32_t ATTRIBUTE_PURE WM_STATE_PolygonStippleEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 173; case 45: return 173; case 40: return 173; default: unreachable("Invalid hardware generation"); } } /* WM_STATE::Sampler Count */ #define GFX5_WM_STATE_SamplerCount_bits 3 #define GFX45_WM_STATE_SamplerCount_bits 3 #define GFX4_WM_STATE_SamplerCount_bits 3 static inline uint32_t ATTRIBUTE_PURE WM_STATE_SamplerCount_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX5_WM_STATE_SamplerCount_start 130 #define GFX45_WM_STATE_SamplerCount_start 130 #define GFX4_WM_STATE_SamplerCount_start 130 static inline uint32_t ATTRIBUTE_PURE WM_STATE_SamplerCount_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 130; case 45: return 130; case 40: return 130; default: unreachable("Invalid hardware generation"); } } /* WM_STATE::Sampler State Pointer */ #define GFX5_WM_STATE_SamplerStatePointer_bits 27 #define GFX45_WM_STATE_SamplerStatePointer_bits 27 #define GFX4_WM_STATE_SamplerStatePointer_bits 27 static inline uint32_t ATTRIBUTE_PURE WM_STATE_SamplerStatePointer_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 27; case 45: return 27; case 40: return 27; default: unreachable("Invalid hardware generation"); } } #define GFX5_WM_STATE_SamplerStatePointer_start 133 #define GFX45_WM_STATE_SamplerStatePointer_start 133 #define GFX4_WM_STATE_SamplerStatePointer_start 133 static inline uint32_t ATTRIBUTE_PURE WM_STATE_SamplerStatePointer_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 133; case 45: return 133; case 40: return 133; default: unreachable("Invalid hardware generation"); } } /* WM_STATE::Scratch Space Base Pointer */ #define GFX5_WM_STATE_ScratchSpaceBasePointer_bits 22 #define GFX45_WM_STATE_ScratchSpaceBasePointer_bits 22 #define GFX4_WM_STATE_ScratchSpaceBasePointer_bits 22 static inline uint32_t ATTRIBUTE_PURE WM_STATE_ScratchSpaceBasePointer_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 22; case 45: return 22; case 40: return 22; default: unreachable("Invalid hardware generation"); } } #define GFX5_WM_STATE_ScratchSpaceBasePointer_start 74 #define GFX45_WM_STATE_ScratchSpaceBasePointer_start 74 #define GFX4_WM_STATE_ScratchSpaceBasePointer_start 74 static inline uint32_t ATTRIBUTE_PURE WM_STATE_ScratchSpaceBasePointer_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 74; case 45: return 74; case 40: return 74; default: unreachable("Invalid hardware generation"); } } /* WM_STATE::Setup URB Entry Read Length */ #define GFX5_WM_STATE_SetupURBEntryReadLength_bits 6 #define GFX45_WM_STATE_SetupURBEntryReadLength_bits 6 #define GFX4_WM_STATE_SetupURBEntryReadLength_bits 6 static inline uint32_t ATTRIBUTE_PURE WM_STATE_SetupURBEntryReadLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 6; case 45: return 6; case 40: return 6; default: unreachable("Invalid hardware generation"); } } #define GFX5_WM_STATE_SetupURBEntryReadLength_start 107 #define GFX45_WM_STATE_SetupURBEntryReadLength_start 107 #define GFX4_WM_STATE_SetupURBEntryReadLength_start 107 static inline uint32_t ATTRIBUTE_PURE WM_STATE_SetupURBEntryReadLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 107; case 45: return 107; case 40: return 107; default: unreachable("Invalid hardware generation"); } } /* WM_STATE::Setup URB Entry Read Offset */ #define GFX5_WM_STATE_SetupURBEntryReadOffset_bits 6 #define GFX45_WM_STATE_SetupURBEntryReadOffset_bits 6 #define GFX4_WM_STATE_SetupURBEntryReadOffset_bits 6 static inline uint32_t ATTRIBUTE_PURE WM_STATE_SetupURBEntryReadOffset_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 6; case 45: return 6; case 40: return 6; default: unreachable("Invalid hardware generation"); } } #define GFX5_WM_STATE_SetupURBEntryReadOffset_start 100 #define GFX45_WM_STATE_SetupURBEntryReadOffset_start 100 #define GFX4_WM_STATE_SetupURBEntryReadOffset_start 100 static inline uint32_t ATTRIBUTE_PURE WM_STATE_SetupURBEntryReadOffset_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 100; case 45: return 100; case 40: return 100; default: unreachable("Invalid hardware generation"); } } /* WM_STATE::Single Program Flow */ #define GFX5_WM_STATE_SingleProgramFlow_bits 1 #define GFX45_WM_STATE_SingleProgramFlow_bits 1 #define GFX4_WM_STATE_SingleProgramFlow_bits 1 static inline uint32_t ATTRIBUTE_PURE WM_STATE_SingleProgramFlow_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_WM_STATE_SingleProgramFlow_start 63 #define GFX45_WM_STATE_SingleProgramFlow_start 63 #define GFX4_WM_STATE_SingleProgramFlow_start 63 static inline uint32_t ATTRIBUTE_PURE WM_STATE_SingleProgramFlow_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 63; case 45: return 63; case 40: return 63; default: unreachable("Invalid hardware generation"); } } /* WM_STATE::Software Exception Enable */ #define GFX5_WM_STATE_SoftwareExceptionEnable_bits 1 #define GFX45_WM_STATE_SoftwareExceptionEnable_bits 1 #define GFX4_WM_STATE_SoftwareExceptionEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE WM_STATE_SoftwareExceptionEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_WM_STATE_SoftwareExceptionEnable_start 33 #define GFX45_WM_STATE_SoftwareExceptionEnable_start 33 #define GFX4_WM_STATE_SoftwareExceptionEnable_start 33 static inline uint32_t ATTRIBUTE_PURE WM_STATE_SoftwareExceptionEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 33; case 45: return 33; case 40: return 33; default: unreachable("Invalid hardware generation"); } } /* WM_STATE::Statistics Enable */ #define GFX5_WM_STATE_StatisticsEnable_bits 1 #define GFX45_WM_STATE_StatisticsEnable_bits 1 #define GFX4_WM_STATE_StatisticsEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE WM_STATE_StatisticsEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_WM_STATE_StatisticsEnable_start 128 #define GFX45_WM_STATE_StatisticsEnable_start 128 #define GFX4_WM_STATE_StatisticsEnable_start 128 static inline uint32_t ATTRIBUTE_PURE WM_STATE_StatisticsEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 128; case 45: return 128; case 40: return 128; default: unreachable("Invalid hardware generation"); } } /* WM_STATE::Thread Dispatch Enable */ #define GFX5_WM_STATE_ThreadDispatchEnable_bits 1 #define GFX45_WM_STATE_ThreadDispatchEnable_bits 1 #define GFX4_WM_STATE_ThreadDispatchEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE WM_STATE_ThreadDispatchEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_WM_STATE_ThreadDispatchEnable_start 179 #define GFX45_WM_STATE_ThreadDispatchEnable_start 179 #define GFX4_WM_STATE_ThreadDispatchEnable_start 179 static inline uint32_t ATTRIBUTE_PURE WM_STATE_ThreadDispatchEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 179; case 45: return 179; case 40: return 179; default: unreachable("Invalid hardware generation"); } } /* WM_STATE::Thread Priority */ #define GFX5_WM_STATE_ThreadPriority_bits 1 #define GFX45_WM_STATE_ThreadPriority_bits 1 #define GFX4_WM_STATE_ThreadPriority_bits 1 static inline uint32_t ATTRIBUTE_PURE WM_STATE_ThreadPriority_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_WM_STATE_ThreadPriority_start 49 #define GFX45_WM_STATE_ThreadPriority_start 49 #define GFX4_WM_STATE_ThreadPriority_start 49 static inline uint32_t ATTRIBUTE_PURE WM_STATE_ThreadPriority_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 49; case 45: return 49; case 40: return 49; default: unreachable("Invalid hardware generation"); } } /* XY_COLOR_BLT */ #define GFX5_XY_COLOR_BLT_length 6 #define GFX45_XY_COLOR_BLT_length 6 #define GFX4_XY_COLOR_BLT_length 6 static inline uint32_t ATTRIBUTE_PURE XY_COLOR_BLT_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 6; case 45: return 6; case 40: return 6; default: unreachable("Invalid hardware generation"); } } /* XY_COLOR_BLT::2D Command Opcode */ #define GFX5_XY_COLOR_BLT_2DCommandOpcode_bits 7 #define GFX45_XY_COLOR_BLT_2DCommandOpcode_bits 7 #define GFX4_XY_COLOR_BLT_2DCommandOpcode_bits 7 static inline uint32_t ATTRIBUTE_PURE XY_COLOR_BLT_2DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 7; case 45: return 7; case 40: return 7; default: unreachable("Invalid hardware generation"); } } #define GFX5_XY_COLOR_BLT_2DCommandOpcode_start 22 #define GFX45_XY_COLOR_BLT_2DCommandOpcode_start 22 #define GFX4_XY_COLOR_BLT_2DCommandOpcode_start 22 static inline uint32_t ATTRIBUTE_PURE XY_COLOR_BLT_2DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 22; case 45: return 22; case 40: return 22; default: unreachable("Invalid hardware generation"); } } /* XY_COLOR_BLT::32bpp Byte Mask */ #define GFX5_XY_COLOR_BLT_32bppByteMask_bits 2 #define GFX45_XY_COLOR_BLT_32bppByteMask_bits 2 #define GFX4_XY_COLOR_BLT_32bppByteMask_bits 2 static inline uint32_t ATTRIBUTE_PURE XY_COLOR_BLT_32bppByteMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 2; case 45: return 2; case 40: return 2; default: unreachable("Invalid hardware generation"); } } #define GFX5_XY_COLOR_BLT_32bppByteMask_start 20 #define GFX45_XY_COLOR_BLT_32bppByteMask_start 20 #define GFX4_XY_COLOR_BLT_32bppByteMask_start 20 static inline uint32_t ATTRIBUTE_PURE XY_COLOR_BLT_32bppByteMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 20; case 45: return 20; case 40: return 20; default: unreachable("Invalid hardware generation"); } } /* XY_COLOR_BLT::Clipping Enabled */ #define GFX5_XY_COLOR_BLT_ClippingEnabled_bits 1 #define GFX45_XY_COLOR_BLT_ClippingEnabled_bits 1 #define GFX4_XY_COLOR_BLT_ClippingEnabled_bits 1 static inline uint32_t ATTRIBUTE_PURE XY_COLOR_BLT_ClippingEnabled_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_XY_COLOR_BLT_ClippingEnabled_start 62 #define GFX45_XY_COLOR_BLT_ClippingEnabled_start 62 #define GFX4_XY_COLOR_BLT_ClippingEnabled_start 62 static inline uint32_t ATTRIBUTE_PURE XY_COLOR_BLT_ClippingEnabled_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 62; case 45: return 62; case 40: return 62; default: unreachable("Invalid hardware generation"); } } /* XY_COLOR_BLT::Color Depth */ #define GFX5_XY_COLOR_BLT_ColorDepth_bits 3 #define GFX45_XY_COLOR_BLT_ColorDepth_bits 2 #define GFX4_XY_COLOR_BLT_ColorDepth_bits 2 static inline uint32_t ATTRIBUTE_PURE XY_COLOR_BLT_ColorDepth_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 3; case 45: return 2; case 40: return 2; default: unreachable("Invalid hardware generation"); } } #define GFX5_XY_COLOR_BLT_ColorDepth_start 56 #define GFX45_XY_COLOR_BLT_ColorDepth_start 56 #define GFX4_XY_COLOR_BLT_ColorDepth_start 56 static inline uint32_t ATTRIBUTE_PURE XY_COLOR_BLT_ColorDepth_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 56; case 45: return 56; case 40: return 56; default: unreachable("Invalid hardware generation"); } } /* XY_COLOR_BLT::Command Type */ #define GFX5_XY_COLOR_BLT_CommandType_bits 3 #define GFX45_XY_COLOR_BLT_CommandType_bits 3 #define GFX4_XY_COLOR_BLT_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE XY_COLOR_BLT_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX5_XY_COLOR_BLT_CommandType_start 29 #define GFX45_XY_COLOR_BLT_CommandType_start 29 #define GFX4_XY_COLOR_BLT_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE XY_COLOR_BLT_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 29; case 45: return 29; case 40: return 29; default: unreachable("Invalid hardware generation"); } } /* XY_COLOR_BLT::DWord Length */ #define GFX5_XY_COLOR_BLT_DWordLength_bits 8 #define GFX45_XY_COLOR_BLT_DWordLength_bits 8 #define GFX4_XY_COLOR_BLT_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE XY_COLOR_BLT_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 8; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } #define GFX5_XY_COLOR_BLT_DWordLength_start 0 #define GFX45_XY_COLOR_BLT_DWordLength_start 0 #define GFX4_XY_COLOR_BLT_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE XY_COLOR_BLT_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* XY_COLOR_BLT::Destination Base Address */ #define GFX5_XY_COLOR_BLT_DestinationBaseAddress_bits 32 #define GFX45_XY_COLOR_BLT_DestinationBaseAddress_bits 32 #define GFX4_XY_COLOR_BLT_DestinationBaseAddress_bits 32 static inline uint32_t ATTRIBUTE_PURE XY_COLOR_BLT_DestinationBaseAddress_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 32; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } #define GFX5_XY_COLOR_BLT_DestinationBaseAddress_start 128 #define GFX45_XY_COLOR_BLT_DestinationBaseAddress_start 128 #define GFX4_XY_COLOR_BLT_DestinationBaseAddress_start 128 static inline uint32_t ATTRIBUTE_PURE XY_COLOR_BLT_DestinationBaseAddress_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 128; case 45: return 128; case 40: return 128; default: unreachable("Invalid hardware generation"); } } /* XY_COLOR_BLT::Destination Pitch */ #define GFX5_XY_COLOR_BLT_DestinationPitch_bits 16 #define GFX45_XY_COLOR_BLT_DestinationPitch_bits 16 #define GFX4_XY_COLOR_BLT_DestinationPitch_bits 16 static inline uint32_t ATTRIBUTE_PURE XY_COLOR_BLT_DestinationPitch_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 16; case 45: return 16; case 40: return 16; default: unreachable("Invalid hardware generation"); } } #define GFX5_XY_COLOR_BLT_DestinationPitch_start 32 #define GFX45_XY_COLOR_BLT_DestinationPitch_start 32 #define GFX4_XY_COLOR_BLT_DestinationPitch_start 32 static inline uint32_t ATTRIBUTE_PURE XY_COLOR_BLT_DestinationPitch_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 32; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } /* XY_COLOR_BLT::Destination X1 Coordinate */ #define GFX5_XY_COLOR_BLT_DestinationX1Coordinate_bits 16 #define GFX45_XY_COLOR_BLT_DestinationX1Coordinate_bits 16 #define GFX4_XY_COLOR_BLT_DestinationX1Coordinate_bits 16 static inline uint32_t ATTRIBUTE_PURE XY_COLOR_BLT_DestinationX1Coordinate_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 16; case 45: return 16; case 40: return 16; default: unreachable("Invalid hardware generation"); } } #define GFX5_XY_COLOR_BLT_DestinationX1Coordinate_start 64 #define GFX45_XY_COLOR_BLT_DestinationX1Coordinate_start 64 #define GFX4_XY_COLOR_BLT_DestinationX1Coordinate_start 64 static inline uint32_t ATTRIBUTE_PURE XY_COLOR_BLT_DestinationX1Coordinate_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 64; case 45: return 64; case 40: return 64; default: unreachable("Invalid hardware generation"); } } /* XY_COLOR_BLT::Destination X2 Coordinate */ #define GFX5_XY_COLOR_BLT_DestinationX2Coordinate_bits 16 #define GFX45_XY_COLOR_BLT_DestinationX2Coordinate_bits 16 #define GFX4_XY_COLOR_BLT_DestinationX2Coordinate_bits 16 static inline uint32_t ATTRIBUTE_PURE XY_COLOR_BLT_DestinationX2Coordinate_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 16; case 45: return 16; case 40: return 16; default: unreachable("Invalid hardware generation"); } } #define GFX5_XY_COLOR_BLT_DestinationX2Coordinate_start 96 #define GFX45_XY_COLOR_BLT_DestinationX2Coordinate_start 96 #define GFX4_XY_COLOR_BLT_DestinationX2Coordinate_start 96 static inline uint32_t ATTRIBUTE_PURE XY_COLOR_BLT_DestinationX2Coordinate_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 96; case 45: return 96; case 40: return 96; default: unreachable("Invalid hardware generation"); } } /* XY_COLOR_BLT::Destination Y1 Coordinate */ #define GFX5_XY_COLOR_BLT_DestinationY1Coordinate_bits 16 #define GFX45_XY_COLOR_BLT_DestinationY1Coordinate_bits 16 #define GFX4_XY_COLOR_BLT_DestinationY1Coordinate_bits 16 static inline uint32_t ATTRIBUTE_PURE XY_COLOR_BLT_DestinationY1Coordinate_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 16; case 45: return 16; case 40: return 16; default: unreachable("Invalid hardware generation"); } } #define GFX5_XY_COLOR_BLT_DestinationY1Coordinate_start 80 #define GFX45_XY_COLOR_BLT_DestinationY1Coordinate_start 80 #define GFX4_XY_COLOR_BLT_DestinationY1Coordinate_start 80 static inline uint32_t ATTRIBUTE_PURE XY_COLOR_BLT_DestinationY1Coordinate_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 80; case 45: return 80; case 40: return 80; default: unreachable("Invalid hardware generation"); } } /* XY_COLOR_BLT::Destination Y2 Coordinate */ #define GFX5_XY_COLOR_BLT_DestinationY2Coordinate_bits 16 #define GFX45_XY_COLOR_BLT_DestinationY2Coordinate_bits 16 #define GFX4_XY_COLOR_BLT_DestinationY2Coordinate_bits 16 static inline uint32_t ATTRIBUTE_PURE XY_COLOR_BLT_DestinationY2Coordinate_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 16; case 45: return 16; case 40: return 16; default: unreachable("Invalid hardware generation"); } } #define GFX5_XY_COLOR_BLT_DestinationY2Coordinate_start 112 #define GFX45_XY_COLOR_BLT_DestinationY2Coordinate_start 112 #define GFX4_XY_COLOR_BLT_DestinationY2Coordinate_start 112 static inline uint32_t ATTRIBUTE_PURE XY_COLOR_BLT_DestinationY2Coordinate_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 112; case 45: return 112; case 40: return 112; default: unreachable("Invalid hardware generation"); } } /* XY_COLOR_BLT::Raster Operation */ #define GFX5_XY_COLOR_BLT_RasterOperation_bits 8 #define GFX45_XY_COLOR_BLT_RasterOperation_bits 8 #define GFX4_XY_COLOR_BLT_RasterOperation_bits 8 static inline uint32_t ATTRIBUTE_PURE XY_COLOR_BLT_RasterOperation_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 8; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } #define GFX5_XY_COLOR_BLT_RasterOperation_start 48 #define GFX45_XY_COLOR_BLT_RasterOperation_start 48 #define GFX4_XY_COLOR_BLT_RasterOperation_start 48 static inline uint32_t ATTRIBUTE_PURE XY_COLOR_BLT_RasterOperation_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 48; case 45: return 48; case 40: return 48; default: unreachable("Invalid hardware generation"); } } /* XY_COLOR_BLT::Solid Pattern Color */ #define GFX5_XY_COLOR_BLT_SolidPatternColor_bits 32 #define GFX45_XY_COLOR_BLT_SolidPatternColor_bits 32 #define GFX4_XY_COLOR_BLT_SolidPatternColor_bits 32 static inline uint32_t ATTRIBUTE_PURE XY_COLOR_BLT_SolidPatternColor_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 32; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } #define GFX5_XY_COLOR_BLT_SolidPatternColor_start 160 #define GFX45_XY_COLOR_BLT_SolidPatternColor_start 160 #define GFX4_XY_COLOR_BLT_SolidPatternColor_start 160 static inline uint32_t ATTRIBUTE_PURE XY_COLOR_BLT_SolidPatternColor_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 160; case 45: return 160; case 40: return 160; default: unreachable("Invalid hardware generation"); } } /* XY_COLOR_BLT::Tiling Enable */ #define GFX5_XY_COLOR_BLT_TilingEnable_bits 1 #define GFX45_XY_COLOR_BLT_TilingEnable_bits 1 #define GFX4_XY_COLOR_BLT_TilingEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE XY_COLOR_BLT_TilingEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_XY_COLOR_BLT_TilingEnable_start 11 #define GFX45_XY_COLOR_BLT_TilingEnable_start 11 #define GFX4_XY_COLOR_BLT_TilingEnable_start 11 static inline uint32_t ATTRIBUTE_PURE XY_COLOR_BLT_TilingEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 11; case 45: return 11; case 40: return 11; default: unreachable("Invalid hardware generation"); } } /* XY_SETUP_BLT */ #define GFX45_XY_SETUP_BLT_length 8 #define GFX4_XY_SETUP_BLT_length 8 static inline uint32_t ATTRIBUTE_PURE XY_SETUP_BLT_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } /* XY_SETUP_BLT::2D Command Opcode */ #define GFX45_XY_SETUP_BLT_2DCommandOpcode_bits 7 #define GFX4_XY_SETUP_BLT_2DCommandOpcode_bits 7 static inline uint32_t ATTRIBUTE_PURE XY_SETUP_BLT_2DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 7; case 40: return 7; default: unreachable("Invalid hardware generation"); } } #define GFX45_XY_SETUP_BLT_2DCommandOpcode_start 22 #define GFX4_XY_SETUP_BLT_2DCommandOpcode_start 22 static inline uint32_t ATTRIBUTE_PURE XY_SETUP_BLT_2DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 22; case 40: return 22; default: unreachable("Invalid hardware generation"); } } /* XY_SETUP_BLT::32bpp Byte Mask */ #define GFX45_XY_SETUP_BLT_32bppByteMask_bits 2 #define GFX4_XY_SETUP_BLT_32bppByteMask_bits 2 static inline uint32_t ATTRIBUTE_PURE XY_SETUP_BLT_32bppByteMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 2; case 40: return 2; default: unreachable("Invalid hardware generation"); } } #define GFX45_XY_SETUP_BLT_32bppByteMask_start 20 #define GFX4_XY_SETUP_BLT_32bppByteMask_start 20 static inline uint32_t ATTRIBUTE_PURE XY_SETUP_BLT_32bppByteMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 20; case 40: return 20; default: unreachable("Invalid hardware generation"); } } /* XY_SETUP_BLT::Background Color */ #define GFX45_XY_SETUP_BLT_BackgroundColor_bits 32 #define GFX4_XY_SETUP_BLT_BackgroundColor_bits 32 static inline uint32_t ATTRIBUTE_PURE XY_SETUP_BLT_BackgroundColor_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } #define GFX45_XY_SETUP_BLT_BackgroundColor_start 160 #define GFX4_XY_SETUP_BLT_BackgroundColor_start 160 static inline uint32_t ATTRIBUTE_PURE XY_SETUP_BLT_BackgroundColor_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 160; case 40: return 160; default: unreachable("Invalid hardware generation"); } } /* XY_SETUP_BLT::ClipRect X1 Coordinate */ #define GFX45_XY_SETUP_BLT_ClipRectX1Coordinate_bits 16 #define GFX4_XY_SETUP_BLT_ClipRectX1Coordinate_bits 16 static inline uint32_t ATTRIBUTE_PURE XY_SETUP_BLT_ClipRectX1Coordinate_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 16; case 40: return 16; default: unreachable("Invalid hardware generation"); } } #define GFX45_XY_SETUP_BLT_ClipRectX1Coordinate_start 64 #define GFX4_XY_SETUP_BLT_ClipRectX1Coordinate_start 64 static inline uint32_t ATTRIBUTE_PURE XY_SETUP_BLT_ClipRectX1Coordinate_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 64; case 40: return 64; default: unreachable("Invalid hardware generation"); } } /* XY_SETUP_BLT::ClipRect X2 Coordinate */ #define GFX45_XY_SETUP_BLT_ClipRectX2Coordinate_bits 16 #define GFX4_XY_SETUP_BLT_ClipRectX2Coordinate_bits 16 static inline uint32_t ATTRIBUTE_PURE XY_SETUP_BLT_ClipRectX2Coordinate_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 16; case 40: return 16; default: unreachable("Invalid hardware generation"); } } #define GFX45_XY_SETUP_BLT_ClipRectX2Coordinate_start 96 #define GFX4_XY_SETUP_BLT_ClipRectX2Coordinate_start 96 static inline uint32_t ATTRIBUTE_PURE XY_SETUP_BLT_ClipRectX2Coordinate_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 96; case 40: return 96; default: unreachable("Invalid hardware generation"); } } /* XY_SETUP_BLT::ClipRect Y1 Coordinate */ #define GFX45_XY_SETUP_BLT_ClipRectY1Coordinate_bits 16 #define GFX4_XY_SETUP_BLT_ClipRectY1Coordinate_bits 16 static inline uint32_t ATTRIBUTE_PURE XY_SETUP_BLT_ClipRectY1Coordinate_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 16; case 40: return 16; default: unreachable("Invalid hardware generation"); } } #define GFX45_XY_SETUP_BLT_ClipRectY1Coordinate_start 80 #define GFX4_XY_SETUP_BLT_ClipRectY1Coordinate_start 80 static inline uint32_t ATTRIBUTE_PURE XY_SETUP_BLT_ClipRectY1Coordinate_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 80; case 40: return 80; default: unreachable("Invalid hardware generation"); } } /* XY_SETUP_BLT::ClipRect Y2 Coordinate */ #define GFX45_XY_SETUP_BLT_ClipRectY2Coordinate_bits 16 #define GFX4_XY_SETUP_BLT_ClipRectY2Coordinate_bits 16 static inline uint32_t ATTRIBUTE_PURE XY_SETUP_BLT_ClipRectY2Coordinate_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 16; case 40: return 16; default: unreachable("Invalid hardware generation"); } } #define GFX45_XY_SETUP_BLT_ClipRectY2Coordinate_start 112 #define GFX4_XY_SETUP_BLT_ClipRectY2Coordinate_start 112 static inline uint32_t ATTRIBUTE_PURE XY_SETUP_BLT_ClipRectY2Coordinate_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 112; case 40: return 112; default: unreachable("Invalid hardware generation"); } } /* XY_SETUP_BLT::Clipping Enabled */ #define GFX45_XY_SETUP_BLT_ClippingEnabled_bits 1 #define GFX4_XY_SETUP_BLT_ClippingEnabled_bits 1 static inline uint32_t ATTRIBUTE_PURE XY_SETUP_BLT_ClippingEnabled_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX45_XY_SETUP_BLT_ClippingEnabled_start 62 #define GFX4_XY_SETUP_BLT_ClippingEnabled_start 62 static inline uint32_t ATTRIBUTE_PURE XY_SETUP_BLT_ClippingEnabled_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 62; case 40: return 62; default: unreachable("Invalid hardware generation"); } } /* XY_SETUP_BLT::Color Depth */ #define GFX45_XY_SETUP_BLT_ColorDepth_bits 2 #define GFX4_XY_SETUP_BLT_ColorDepth_bits 2 static inline uint32_t ATTRIBUTE_PURE XY_SETUP_BLT_ColorDepth_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 2; case 40: return 2; default: unreachable("Invalid hardware generation"); } } #define GFX45_XY_SETUP_BLT_ColorDepth_start 56 #define GFX4_XY_SETUP_BLT_ColorDepth_start 56 static inline uint32_t ATTRIBUTE_PURE XY_SETUP_BLT_ColorDepth_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 56; case 40: return 56; default: unreachable("Invalid hardware generation"); } } /* XY_SETUP_BLT::Command Type */ #define GFX45_XY_SETUP_BLT_CommandType_bits 3 #define GFX4_XY_SETUP_BLT_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE XY_SETUP_BLT_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX45_XY_SETUP_BLT_CommandType_start 29 #define GFX4_XY_SETUP_BLT_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE XY_SETUP_BLT_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 29; case 40: return 29; default: unreachable("Invalid hardware generation"); } } /* XY_SETUP_BLT::DWord Length */ #define GFX45_XY_SETUP_BLT_DWordLength_bits 8 #define GFX4_XY_SETUP_BLT_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE XY_SETUP_BLT_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } #define GFX45_XY_SETUP_BLT_DWordLength_start 0 #define GFX4_XY_SETUP_BLT_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE XY_SETUP_BLT_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* XY_SETUP_BLT::Destination Base Address */ #define GFX45_XY_SETUP_BLT_DestinationBaseAddress_bits 32 #define GFX4_XY_SETUP_BLT_DestinationBaseAddress_bits 32 static inline uint32_t ATTRIBUTE_PURE XY_SETUP_BLT_DestinationBaseAddress_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } #define GFX45_XY_SETUP_BLT_DestinationBaseAddress_start 128 #define GFX4_XY_SETUP_BLT_DestinationBaseAddress_start 128 static inline uint32_t ATTRIBUTE_PURE XY_SETUP_BLT_DestinationBaseAddress_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 128; case 40: return 128; default: unreachable("Invalid hardware generation"); } } /* XY_SETUP_BLT::Destination Pitch */ #define GFX45_XY_SETUP_BLT_DestinationPitch_bits 16 #define GFX4_XY_SETUP_BLT_DestinationPitch_bits 16 static inline uint32_t ATTRIBUTE_PURE XY_SETUP_BLT_DestinationPitch_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 16; case 40: return 16; default: unreachable("Invalid hardware generation"); } } #define GFX45_XY_SETUP_BLT_DestinationPitch_start 32 #define GFX4_XY_SETUP_BLT_DestinationPitch_start 32 static inline uint32_t ATTRIBUTE_PURE XY_SETUP_BLT_DestinationPitch_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } /* XY_SETUP_BLT::Foreground Color */ #define GFX45_XY_SETUP_BLT_ForegroundColor_bits 32 #define GFX4_XY_SETUP_BLT_ForegroundColor_bits 32 static inline uint32_t ATTRIBUTE_PURE XY_SETUP_BLT_ForegroundColor_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } #define GFX45_XY_SETUP_BLT_ForegroundColor_start 192 #define GFX4_XY_SETUP_BLT_ForegroundColor_start 192 static inline uint32_t ATTRIBUTE_PURE XY_SETUP_BLT_ForegroundColor_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 192; case 40: return 192; default: unreachable("Invalid hardware generation"); } } /* XY_SETUP_BLT::Mono Source Transparency Mode */ #define GFX45_XY_SETUP_BLT_MonoSourceTransparencyMode_bits 1 #define GFX4_XY_SETUP_BLT_MonoSourceTransparencyMode_bits 1 static inline uint32_t ATTRIBUTE_PURE XY_SETUP_BLT_MonoSourceTransparencyMode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX45_XY_SETUP_BLT_MonoSourceTransparencyMode_start 61 #define GFX4_XY_SETUP_BLT_MonoSourceTransparencyMode_start 61 static inline uint32_t ATTRIBUTE_PURE XY_SETUP_BLT_MonoSourceTransparencyMode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 61; case 40: return 61; default: unreachable("Invalid hardware generation"); } } /* XY_SETUP_BLT::Pattern Base Address */ #define GFX45_XY_SETUP_BLT_PatternBaseAddress_bits 32 #define GFX4_XY_SETUP_BLT_PatternBaseAddress_bits 32 static inline uint32_t ATTRIBUTE_PURE XY_SETUP_BLT_PatternBaseAddress_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } #define GFX45_XY_SETUP_BLT_PatternBaseAddress_start 224 #define GFX4_XY_SETUP_BLT_PatternBaseAddress_start 224 static inline uint32_t ATTRIBUTE_PURE XY_SETUP_BLT_PatternBaseAddress_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 224; case 40: return 224; default: unreachable("Invalid hardware generation"); } } /* XY_SETUP_BLT::Raster Operation */ #define GFX45_XY_SETUP_BLT_RasterOperation_bits 8 #define GFX4_XY_SETUP_BLT_RasterOperation_bits 8 static inline uint32_t ATTRIBUTE_PURE XY_SETUP_BLT_RasterOperation_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } #define GFX45_XY_SETUP_BLT_RasterOperation_start 48 #define GFX4_XY_SETUP_BLT_RasterOperation_start 48 static inline uint32_t ATTRIBUTE_PURE XY_SETUP_BLT_RasterOperation_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 48; case 40: return 48; default: unreachable("Invalid hardware generation"); } } /* XY_SETUP_BLT::Tiling Enable */ #define GFX45_XY_SETUP_BLT_TilingEnable_bits 1 #define GFX4_XY_SETUP_BLT_TilingEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE XY_SETUP_BLT_TilingEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX45_XY_SETUP_BLT_TilingEnable_start 11 #define GFX4_XY_SETUP_BLT_TilingEnable_start 11 static inline uint32_t ATTRIBUTE_PURE XY_SETUP_BLT_TilingEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 11; case 40: return 11; default: unreachable("Invalid hardware generation"); } } /* XY_SRC_COPY_BLT */ #define GFX5_XY_SRC_COPY_BLT_length 8 #define GFX45_XY_SRC_COPY_BLT_length 8 #define GFX4_XY_SRC_COPY_BLT_length 8 static inline uint32_t ATTRIBUTE_PURE XY_SRC_COPY_BLT_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 8; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } /* XY_SRC_COPY_BLT::2D Command Opcode */ #define GFX5_XY_SRC_COPY_BLT_2DCommandOpcode_bits 7 #define GFX45_XY_SRC_COPY_BLT_2DCommandOpcode_bits 7 #define GFX4_XY_SRC_COPY_BLT_2DCommandOpcode_bits 7 static inline uint32_t ATTRIBUTE_PURE XY_SRC_COPY_BLT_2DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 7; case 45: return 7; case 40: return 7; default: unreachable("Invalid hardware generation"); } } #define GFX5_XY_SRC_COPY_BLT_2DCommandOpcode_start 22 #define GFX45_XY_SRC_COPY_BLT_2DCommandOpcode_start 22 #define GFX4_XY_SRC_COPY_BLT_2DCommandOpcode_start 22 static inline uint32_t ATTRIBUTE_PURE XY_SRC_COPY_BLT_2DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 22; case 45: return 22; case 40: return 22; default: unreachable("Invalid hardware generation"); } } /* XY_SRC_COPY_BLT::32bpp Byte Mask */ #define GFX5_XY_SRC_COPY_BLT_32bppByteMask_bits 2 #define GFX45_XY_SRC_COPY_BLT_32bppByteMask_bits 2 #define GFX4_XY_SRC_COPY_BLT_32bppByteMask_bits 2 static inline uint32_t ATTRIBUTE_PURE XY_SRC_COPY_BLT_32bppByteMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 2; case 45: return 2; case 40: return 2; default: unreachable("Invalid hardware generation"); } } #define GFX5_XY_SRC_COPY_BLT_32bppByteMask_start 20 #define GFX45_XY_SRC_COPY_BLT_32bppByteMask_start 20 #define GFX4_XY_SRC_COPY_BLT_32bppByteMask_start 20 static inline uint32_t ATTRIBUTE_PURE XY_SRC_COPY_BLT_32bppByteMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 20; case 45: return 20; case 40: return 20; default: unreachable("Invalid hardware generation"); } } /* XY_SRC_COPY_BLT::Clipping Enabled */ #define GFX5_XY_SRC_COPY_BLT_ClippingEnabled_bits 1 #define GFX45_XY_SRC_COPY_BLT_ClippingEnabled_bits 1 #define GFX4_XY_SRC_COPY_BLT_ClippingEnabled_bits 1 static inline uint32_t ATTRIBUTE_PURE XY_SRC_COPY_BLT_ClippingEnabled_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_XY_SRC_COPY_BLT_ClippingEnabled_start 62 #define GFX45_XY_SRC_COPY_BLT_ClippingEnabled_start 62 #define GFX4_XY_SRC_COPY_BLT_ClippingEnabled_start 62 static inline uint32_t ATTRIBUTE_PURE XY_SRC_COPY_BLT_ClippingEnabled_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 62; case 45: return 62; case 40: return 62; default: unreachable("Invalid hardware generation"); } } /* XY_SRC_COPY_BLT::Color Depth */ #define GFX5_XY_SRC_COPY_BLT_ColorDepth_bits 3 #define GFX45_XY_SRC_COPY_BLT_ColorDepth_bits 2 #define GFX4_XY_SRC_COPY_BLT_ColorDepth_bits 2 static inline uint32_t ATTRIBUTE_PURE XY_SRC_COPY_BLT_ColorDepth_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 3; case 45: return 2; case 40: return 2; default: unreachable("Invalid hardware generation"); } } #define GFX5_XY_SRC_COPY_BLT_ColorDepth_start 56 #define GFX45_XY_SRC_COPY_BLT_ColorDepth_start 56 #define GFX4_XY_SRC_COPY_BLT_ColorDepth_start 56 static inline uint32_t ATTRIBUTE_PURE XY_SRC_COPY_BLT_ColorDepth_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 56; case 45: return 56; case 40: return 56; default: unreachable("Invalid hardware generation"); } } /* XY_SRC_COPY_BLT::Command Type */ #define GFX5_XY_SRC_COPY_BLT_CommandType_bits 3 #define GFX45_XY_SRC_COPY_BLT_CommandType_bits 3 #define GFX4_XY_SRC_COPY_BLT_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE XY_SRC_COPY_BLT_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX5_XY_SRC_COPY_BLT_CommandType_start 29 #define GFX45_XY_SRC_COPY_BLT_CommandType_start 29 #define GFX4_XY_SRC_COPY_BLT_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE XY_SRC_COPY_BLT_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 29; case 45: return 29; case 40: return 29; default: unreachable("Invalid hardware generation"); } } /* XY_SRC_COPY_BLT::DWord Length */ #define GFX5_XY_SRC_COPY_BLT_DWordLength_bits 8 #define GFX45_XY_SRC_COPY_BLT_DWordLength_bits 8 #define GFX4_XY_SRC_COPY_BLT_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE XY_SRC_COPY_BLT_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 8; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } #define GFX5_XY_SRC_COPY_BLT_DWordLength_start 0 #define GFX45_XY_SRC_COPY_BLT_DWordLength_start 0 #define GFX4_XY_SRC_COPY_BLT_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE XY_SRC_COPY_BLT_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* XY_SRC_COPY_BLT::Destination Base Address */ #define GFX5_XY_SRC_COPY_BLT_DestinationBaseAddress_bits 32 #define GFX45_XY_SRC_COPY_BLT_DestinationBaseAddress_bits 32 #define GFX4_XY_SRC_COPY_BLT_DestinationBaseAddress_bits 32 static inline uint32_t ATTRIBUTE_PURE XY_SRC_COPY_BLT_DestinationBaseAddress_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 32; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } #define GFX5_XY_SRC_COPY_BLT_DestinationBaseAddress_start 128 #define GFX45_XY_SRC_COPY_BLT_DestinationBaseAddress_start 128 #define GFX4_XY_SRC_COPY_BLT_DestinationBaseAddress_start 128 static inline uint32_t ATTRIBUTE_PURE XY_SRC_COPY_BLT_DestinationBaseAddress_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 128; case 45: return 128; case 40: return 128; default: unreachable("Invalid hardware generation"); } } /* XY_SRC_COPY_BLT::Destination Pitch */ #define GFX5_XY_SRC_COPY_BLT_DestinationPitch_bits 16 #define GFX45_XY_SRC_COPY_BLT_DestinationPitch_bits 16 #define GFX4_XY_SRC_COPY_BLT_DestinationPitch_bits 16 static inline uint32_t ATTRIBUTE_PURE XY_SRC_COPY_BLT_DestinationPitch_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 16; case 45: return 16; case 40: return 16; default: unreachable("Invalid hardware generation"); } } #define GFX5_XY_SRC_COPY_BLT_DestinationPitch_start 32 #define GFX45_XY_SRC_COPY_BLT_DestinationPitch_start 32 #define GFX4_XY_SRC_COPY_BLT_DestinationPitch_start 32 static inline uint32_t ATTRIBUTE_PURE XY_SRC_COPY_BLT_DestinationPitch_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 32; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } /* XY_SRC_COPY_BLT::Destination Tiling Enable */ #define GFX5_XY_SRC_COPY_BLT_DestinationTilingEnable_bits 1 #define GFX45_XY_SRC_COPY_BLT_DestinationTilingEnable_bits 1 #define GFX4_XY_SRC_COPY_BLT_DestinationTilingEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE XY_SRC_COPY_BLT_DestinationTilingEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_XY_SRC_COPY_BLT_DestinationTilingEnable_start 11 #define GFX45_XY_SRC_COPY_BLT_DestinationTilingEnable_start 11 #define GFX4_XY_SRC_COPY_BLT_DestinationTilingEnable_start 11 static inline uint32_t ATTRIBUTE_PURE XY_SRC_COPY_BLT_DestinationTilingEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 11; case 45: return 11; case 40: return 11; default: unreachable("Invalid hardware generation"); } } /* XY_SRC_COPY_BLT::Destination X1 Coordinate */ #define GFX5_XY_SRC_COPY_BLT_DestinationX1Coordinate_bits 16 #define GFX45_XY_SRC_COPY_BLT_DestinationX1Coordinate_bits 16 #define GFX4_XY_SRC_COPY_BLT_DestinationX1Coordinate_bits 16 static inline uint32_t ATTRIBUTE_PURE XY_SRC_COPY_BLT_DestinationX1Coordinate_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 16; case 45: return 16; case 40: return 16; default: unreachable("Invalid hardware generation"); } } #define GFX5_XY_SRC_COPY_BLT_DestinationX1Coordinate_start 64 #define GFX45_XY_SRC_COPY_BLT_DestinationX1Coordinate_start 64 #define GFX4_XY_SRC_COPY_BLT_DestinationX1Coordinate_start 64 static inline uint32_t ATTRIBUTE_PURE XY_SRC_COPY_BLT_DestinationX1Coordinate_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 64; case 45: return 64; case 40: return 64; default: unreachable("Invalid hardware generation"); } } /* XY_SRC_COPY_BLT::Destination X2 Coordinate */ #define GFX5_XY_SRC_COPY_BLT_DestinationX2Coordinate_bits 16 #define GFX45_XY_SRC_COPY_BLT_DestinationX2Coordinate_bits 16 #define GFX4_XY_SRC_COPY_BLT_DestinationX2Coordinate_bits 16 static inline uint32_t ATTRIBUTE_PURE XY_SRC_COPY_BLT_DestinationX2Coordinate_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 16; case 45: return 16; case 40: return 16; default: unreachable("Invalid hardware generation"); } } #define GFX5_XY_SRC_COPY_BLT_DestinationX2Coordinate_start 96 #define GFX45_XY_SRC_COPY_BLT_DestinationX2Coordinate_start 96 #define GFX4_XY_SRC_COPY_BLT_DestinationX2Coordinate_start 96 static inline uint32_t ATTRIBUTE_PURE XY_SRC_COPY_BLT_DestinationX2Coordinate_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 96; case 45: return 96; case 40: return 96; default: unreachable("Invalid hardware generation"); } } /* XY_SRC_COPY_BLT::Destination Y1 Coordinate */ #define GFX5_XY_SRC_COPY_BLT_DestinationY1Coordinate_bits 16 #define GFX45_XY_SRC_COPY_BLT_DestinationY1Coordinate_bits 16 #define GFX4_XY_SRC_COPY_BLT_DestinationY1Coordinate_bits 16 static inline uint32_t ATTRIBUTE_PURE XY_SRC_COPY_BLT_DestinationY1Coordinate_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 16; case 45: return 16; case 40: return 16; default: unreachable("Invalid hardware generation"); } } #define GFX5_XY_SRC_COPY_BLT_DestinationY1Coordinate_start 80 #define GFX45_XY_SRC_COPY_BLT_DestinationY1Coordinate_start 80 #define GFX4_XY_SRC_COPY_BLT_DestinationY1Coordinate_start 80 static inline uint32_t ATTRIBUTE_PURE XY_SRC_COPY_BLT_DestinationY1Coordinate_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 80; case 45: return 80; case 40: return 80; default: unreachable("Invalid hardware generation"); } } /* XY_SRC_COPY_BLT::Destination Y2 Coordinate */ #define GFX5_XY_SRC_COPY_BLT_DestinationY2Coordinate_bits 16 #define GFX45_XY_SRC_COPY_BLT_DestinationY2Coordinate_bits 16 #define GFX4_XY_SRC_COPY_BLT_DestinationY2Coordinate_bits 16 static inline uint32_t ATTRIBUTE_PURE XY_SRC_COPY_BLT_DestinationY2Coordinate_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 16; case 45: return 16; case 40: return 16; default: unreachable("Invalid hardware generation"); } } #define GFX5_XY_SRC_COPY_BLT_DestinationY2Coordinate_start 112 #define GFX45_XY_SRC_COPY_BLT_DestinationY2Coordinate_start 112 #define GFX4_XY_SRC_COPY_BLT_DestinationY2Coordinate_start 112 static inline uint32_t ATTRIBUTE_PURE XY_SRC_COPY_BLT_DestinationY2Coordinate_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 112; case 45: return 112; case 40: return 112; default: unreachable("Invalid hardware generation"); } } /* XY_SRC_COPY_BLT::Raster Operation */ #define GFX5_XY_SRC_COPY_BLT_RasterOperation_bits 8 #define GFX45_XY_SRC_COPY_BLT_RasterOperation_bits 8 #define GFX4_XY_SRC_COPY_BLT_RasterOperation_bits 8 static inline uint32_t ATTRIBUTE_PURE XY_SRC_COPY_BLT_RasterOperation_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 8; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } #define GFX5_XY_SRC_COPY_BLT_RasterOperation_start 48 #define GFX45_XY_SRC_COPY_BLT_RasterOperation_start 48 #define GFX4_XY_SRC_COPY_BLT_RasterOperation_start 48 static inline uint32_t ATTRIBUTE_PURE XY_SRC_COPY_BLT_RasterOperation_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 48; case 45: return 48; case 40: return 48; default: unreachable("Invalid hardware generation"); } } /* XY_SRC_COPY_BLT::Source Base Address */ #define GFX5_XY_SRC_COPY_BLT_SourceBaseAddress_bits 32 #define GFX45_XY_SRC_COPY_BLT_SourceBaseAddress_bits 32 #define GFX4_XY_SRC_COPY_BLT_SourceBaseAddress_bits 32 static inline uint32_t ATTRIBUTE_PURE XY_SRC_COPY_BLT_SourceBaseAddress_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 32; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } #define GFX5_XY_SRC_COPY_BLT_SourceBaseAddress_start 224 #define GFX45_XY_SRC_COPY_BLT_SourceBaseAddress_start 224 #define GFX4_XY_SRC_COPY_BLT_SourceBaseAddress_start 224 static inline uint32_t ATTRIBUTE_PURE XY_SRC_COPY_BLT_SourceBaseAddress_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 224; case 45: return 224; case 40: return 224; default: unreachable("Invalid hardware generation"); } } /* XY_SRC_COPY_BLT::Source Pitch */ #define GFX5_XY_SRC_COPY_BLT_SourcePitch_bits 16 #define GFX45_XY_SRC_COPY_BLT_SourcePitch_bits 16 #define GFX4_XY_SRC_COPY_BLT_SourcePitch_bits 16 static inline uint32_t ATTRIBUTE_PURE XY_SRC_COPY_BLT_SourcePitch_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 16; case 45: return 16; case 40: return 16; default: unreachable("Invalid hardware generation"); } } #define GFX5_XY_SRC_COPY_BLT_SourcePitch_start 192 #define GFX45_XY_SRC_COPY_BLT_SourcePitch_start 192 #define GFX4_XY_SRC_COPY_BLT_SourcePitch_start 192 static inline uint32_t ATTRIBUTE_PURE XY_SRC_COPY_BLT_SourcePitch_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 192; case 45: return 192; case 40: return 192; default: unreachable("Invalid hardware generation"); } } /* XY_SRC_COPY_BLT::Source Tiling Enable */ #define GFX5_XY_SRC_COPY_BLT_SourceTilingEnable_bits 1 #define GFX45_XY_SRC_COPY_BLT_SourceTilingEnable_bits 1 #define GFX4_XY_SRC_COPY_BLT_SourceTilingEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE XY_SRC_COPY_BLT_SourceTilingEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_XY_SRC_COPY_BLT_SourceTilingEnable_start 15 #define GFX45_XY_SRC_COPY_BLT_SourceTilingEnable_start 15 #define GFX4_XY_SRC_COPY_BLT_SourceTilingEnable_start 15 static inline uint32_t ATTRIBUTE_PURE XY_SRC_COPY_BLT_SourceTilingEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 15; case 45: return 15; case 40: return 15; default: unreachable("Invalid hardware generation"); } } /* XY_SRC_COPY_BLT::Source X1 Coordinate */ #define GFX5_XY_SRC_COPY_BLT_SourceX1Coordinate_bits 16 #define GFX45_XY_SRC_COPY_BLT_SourceX1Coordinate_bits 16 #define GFX4_XY_SRC_COPY_BLT_SourceX1Coordinate_bits 16 static inline uint32_t ATTRIBUTE_PURE XY_SRC_COPY_BLT_SourceX1Coordinate_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 16; case 45: return 16; case 40: return 16; default: unreachable("Invalid hardware generation"); } } #define GFX5_XY_SRC_COPY_BLT_SourceX1Coordinate_start 160 #define GFX45_XY_SRC_COPY_BLT_SourceX1Coordinate_start 160 #define GFX4_XY_SRC_COPY_BLT_SourceX1Coordinate_start 160 static inline uint32_t ATTRIBUTE_PURE XY_SRC_COPY_BLT_SourceX1Coordinate_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 160; case 45: return 160; case 40: return 160; default: unreachable("Invalid hardware generation"); } } /* XY_SRC_COPY_BLT::Source Y1 Coordinate */ #define GFX5_XY_SRC_COPY_BLT_SourceY1Coordinate_bits 16 #define GFX45_XY_SRC_COPY_BLT_SourceY1Coordinate_bits 16 #define GFX4_XY_SRC_COPY_BLT_SourceY1Coordinate_bits 16 static inline uint32_t ATTRIBUTE_PURE XY_SRC_COPY_BLT_SourceY1Coordinate_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 16; case 45: return 16; case 40: return 16; default: unreachable("Invalid hardware generation"); } } #define GFX5_XY_SRC_COPY_BLT_SourceY1Coordinate_start 176 #define GFX45_XY_SRC_COPY_BLT_SourceY1Coordinate_start 176 #define GFX4_XY_SRC_COPY_BLT_SourceY1Coordinate_start 176 static inline uint32_t ATTRIBUTE_PURE XY_SRC_COPY_BLT_SourceY1Coordinate_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 176; case 45: return 176; case 40: return 176; default: unreachable("Invalid hardware generation"); } } /* XY_TEXT_IMMEDIATE_BLT */ #define GFX5_XY_TEXT_IMMEDIATE_BLT_length 3 #define GFX45_XY_TEXT_IMMEDIATE_BLT_length 3 #define GFX4_XY_TEXT_IMMEDIATE_BLT_length 3 static inline uint32_t ATTRIBUTE_PURE XY_TEXT_IMMEDIATE_BLT_length(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } /* XY_TEXT_IMMEDIATE_BLT::2D Command Opcode */ #define GFX5_XY_TEXT_IMMEDIATE_BLT_2DCommandOpcode_bits 7 #define GFX45_XY_TEXT_IMMEDIATE_BLT_2DCommandOpcode_bits 7 #define GFX4_XY_TEXT_IMMEDIATE_BLT_2DCommandOpcode_bits 7 static inline uint32_t ATTRIBUTE_PURE XY_TEXT_IMMEDIATE_BLT_2DCommandOpcode_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 7; case 45: return 7; case 40: return 7; default: unreachable("Invalid hardware generation"); } } #define GFX5_XY_TEXT_IMMEDIATE_BLT_2DCommandOpcode_start 22 #define GFX45_XY_TEXT_IMMEDIATE_BLT_2DCommandOpcode_start 22 #define GFX4_XY_TEXT_IMMEDIATE_BLT_2DCommandOpcode_start 22 static inline uint32_t ATTRIBUTE_PURE XY_TEXT_IMMEDIATE_BLT_2DCommandOpcode_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 22; case 45: return 22; case 40: return 22; default: unreachable("Invalid hardware generation"); } } /* XY_TEXT_IMMEDIATE_BLT::32bpp Byte Mask */ #define GFX5_XY_TEXT_IMMEDIATE_BLT_32bppByteMask_bits 2 #define GFX45_XY_TEXT_IMMEDIATE_BLT_32bppByteMask_bits 2 #define GFX4_XY_TEXT_IMMEDIATE_BLT_32bppByteMask_bits 2 static inline uint32_t ATTRIBUTE_PURE XY_TEXT_IMMEDIATE_BLT_32bppByteMask_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 2; case 45: return 2; case 40: return 2; default: unreachable("Invalid hardware generation"); } } #define GFX5_XY_TEXT_IMMEDIATE_BLT_32bppByteMask_start 20 #define GFX45_XY_TEXT_IMMEDIATE_BLT_32bppByteMask_start 20 #define GFX4_XY_TEXT_IMMEDIATE_BLT_32bppByteMask_start 20 static inline uint32_t ATTRIBUTE_PURE XY_TEXT_IMMEDIATE_BLT_32bppByteMask_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 20; case 45: return 20; case 40: return 20; default: unreachable("Invalid hardware generation"); } } /* XY_TEXT_IMMEDIATE_BLT::Command Type */ #define GFX5_XY_TEXT_IMMEDIATE_BLT_CommandType_bits 3 #define GFX45_XY_TEXT_IMMEDIATE_BLT_CommandType_bits 3 #define GFX4_XY_TEXT_IMMEDIATE_BLT_CommandType_bits 3 static inline uint32_t ATTRIBUTE_PURE XY_TEXT_IMMEDIATE_BLT_CommandType_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 3; case 45: return 3; case 40: return 3; default: unreachable("Invalid hardware generation"); } } #define GFX5_XY_TEXT_IMMEDIATE_BLT_CommandType_start 29 #define GFX45_XY_TEXT_IMMEDIATE_BLT_CommandType_start 29 #define GFX4_XY_TEXT_IMMEDIATE_BLT_CommandType_start 29 static inline uint32_t ATTRIBUTE_PURE XY_TEXT_IMMEDIATE_BLT_CommandType_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 29; case 45: return 29; case 40: return 29; default: unreachable("Invalid hardware generation"); } } /* XY_TEXT_IMMEDIATE_BLT::DWord Length */ #define GFX5_XY_TEXT_IMMEDIATE_BLT_DWordLength_bits 8 #define GFX45_XY_TEXT_IMMEDIATE_BLT_DWordLength_bits 8 #define GFX4_XY_TEXT_IMMEDIATE_BLT_DWordLength_bits 8 static inline uint32_t ATTRIBUTE_PURE XY_TEXT_IMMEDIATE_BLT_DWordLength_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 8; case 45: return 8; case 40: return 8; default: unreachable("Invalid hardware generation"); } } #define GFX5_XY_TEXT_IMMEDIATE_BLT_DWordLength_start 0 #define GFX45_XY_TEXT_IMMEDIATE_BLT_DWordLength_start 0 #define GFX4_XY_TEXT_IMMEDIATE_BLT_DWordLength_start 0 static inline uint32_t ATTRIBUTE_PURE XY_TEXT_IMMEDIATE_BLT_DWordLength_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 0; case 45: return 0; case 40: return 0; default: unreachable("Invalid hardware generation"); } } /* XY_TEXT_IMMEDIATE_BLT::Destination Pitch */ #define GFX5_XY_TEXT_IMMEDIATE_BLT_DestinationPitch_bits 16 #define GFX45_XY_TEXT_IMMEDIATE_BLT_DestinationPitch_bits 16 #define GFX4_XY_TEXT_IMMEDIATE_BLT_DestinationPitch_bits 16 static inline uint32_t ATTRIBUTE_PURE XY_TEXT_IMMEDIATE_BLT_DestinationPitch_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 16; case 45: return 16; case 40: return 16; default: unreachable("Invalid hardware generation"); } } #define GFX5_XY_TEXT_IMMEDIATE_BLT_DestinationPitch_start 32 #define GFX45_XY_TEXT_IMMEDIATE_BLT_DestinationPitch_start 32 #define GFX4_XY_TEXT_IMMEDIATE_BLT_DestinationPitch_start 32 static inline uint32_t ATTRIBUTE_PURE XY_TEXT_IMMEDIATE_BLT_DestinationPitch_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 32; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } /* XY_TEXT_IMMEDIATE_BLT::Destination X1 Coordinate */ #define GFX5_XY_TEXT_IMMEDIATE_BLT_DestinationX1Coordinate_bits 16 #define GFX45_XY_TEXT_IMMEDIATE_BLT_DestinationX1Coordinate_bits 16 #define GFX4_XY_TEXT_IMMEDIATE_BLT_DestinationX1Coordinate_bits 16 static inline uint32_t ATTRIBUTE_PURE XY_TEXT_IMMEDIATE_BLT_DestinationX1Coordinate_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 16; case 45: return 16; case 40: return 16; default: unreachable("Invalid hardware generation"); } } #define GFX5_XY_TEXT_IMMEDIATE_BLT_DestinationX1Coordinate_start 32 #define GFX45_XY_TEXT_IMMEDIATE_BLT_DestinationX1Coordinate_start 32 #define GFX4_XY_TEXT_IMMEDIATE_BLT_DestinationX1Coordinate_start 32 static inline uint32_t ATTRIBUTE_PURE XY_TEXT_IMMEDIATE_BLT_DestinationX1Coordinate_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 32; case 45: return 32; case 40: return 32; default: unreachable("Invalid hardware generation"); } } /* XY_TEXT_IMMEDIATE_BLT::Destination X2 Coordinate */ #define GFX5_XY_TEXT_IMMEDIATE_BLT_DestinationX2Coordinate_bits 16 #define GFX45_XY_TEXT_IMMEDIATE_BLT_DestinationX2Coordinate_bits 16 #define GFX4_XY_TEXT_IMMEDIATE_BLT_DestinationX2Coordinate_bits 16 static inline uint32_t ATTRIBUTE_PURE XY_TEXT_IMMEDIATE_BLT_DestinationX2Coordinate_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 16; case 45: return 16; case 40: return 16; default: unreachable("Invalid hardware generation"); } } #define GFX5_XY_TEXT_IMMEDIATE_BLT_DestinationX2Coordinate_start 64 #define GFX45_XY_TEXT_IMMEDIATE_BLT_DestinationX2Coordinate_start 64 #define GFX4_XY_TEXT_IMMEDIATE_BLT_DestinationX2Coordinate_start 64 static inline uint32_t ATTRIBUTE_PURE XY_TEXT_IMMEDIATE_BLT_DestinationX2Coordinate_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 64; case 45: return 64; case 40: return 64; default: unreachable("Invalid hardware generation"); } } /* XY_TEXT_IMMEDIATE_BLT::Destination Y1 Coordinate */ #define GFX5_XY_TEXT_IMMEDIATE_BLT_DestinationY1Coordinate_bits 16 #define GFX45_XY_TEXT_IMMEDIATE_BLT_DestinationY1Coordinate_bits 16 #define GFX4_XY_TEXT_IMMEDIATE_BLT_DestinationY1Coordinate_bits 16 static inline uint32_t ATTRIBUTE_PURE XY_TEXT_IMMEDIATE_BLT_DestinationY1Coordinate_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 16; case 45: return 16; case 40: return 16; default: unreachable("Invalid hardware generation"); } } #define GFX5_XY_TEXT_IMMEDIATE_BLT_DestinationY1Coordinate_start 48 #define GFX45_XY_TEXT_IMMEDIATE_BLT_DestinationY1Coordinate_start 48 #define GFX4_XY_TEXT_IMMEDIATE_BLT_DestinationY1Coordinate_start 48 static inline uint32_t ATTRIBUTE_PURE XY_TEXT_IMMEDIATE_BLT_DestinationY1Coordinate_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 48; case 45: return 48; case 40: return 48; default: unreachable("Invalid hardware generation"); } } /* XY_TEXT_IMMEDIATE_BLT::Destination Y2 Coordinate */ #define GFX5_XY_TEXT_IMMEDIATE_BLT_DestinationY2Coordinate_bits 16 #define GFX45_XY_TEXT_IMMEDIATE_BLT_DestinationY2Coordinate_bits 16 #define GFX4_XY_TEXT_IMMEDIATE_BLT_DestinationY2Coordinate_bits 16 static inline uint32_t ATTRIBUTE_PURE XY_TEXT_IMMEDIATE_BLT_DestinationY2Coordinate_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 16; case 45: return 16; case 40: return 16; default: unreachable("Invalid hardware generation"); } } #define GFX5_XY_TEXT_IMMEDIATE_BLT_DestinationY2Coordinate_start 80 #define GFX45_XY_TEXT_IMMEDIATE_BLT_DestinationY2Coordinate_start 80 #define GFX4_XY_TEXT_IMMEDIATE_BLT_DestinationY2Coordinate_start 80 static inline uint32_t ATTRIBUTE_PURE XY_TEXT_IMMEDIATE_BLT_DestinationY2Coordinate_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 80; case 45: return 80; case 40: return 80; default: unreachable("Invalid hardware generation"); } } /* XY_TEXT_IMMEDIATE_BLT::Packing */ #define GFX5_XY_TEXT_IMMEDIATE_BLT_Packing_bits 1 #define GFX45_XY_TEXT_IMMEDIATE_BLT_Packing_bits 1 #define GFX4_XY_TEXT_IMMEDIATE_BLT_Packing_bits 1 static inline uint32_t ATTRIBUTE_PURE XY_TEXT_IMMEDIATE_BLT_Packing_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_XY_TEXT_IMMEDIATE_BLT_Packing_start 16 #define GFX45_XY_TEXT_IMMEDIATE_BLT_Packing_start 16 #define GFX4_XY_TEXT_IMMEDIATE_BLT_Packing_start 16 static inline uint32_t ATTRIBUTE_PURE XY_TEXT_IMMEDIATE_BLT_Packing_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 16; case 45: return 16; case 40: return 16; default: unreachable("Invalid hardware generation"); } } /* XY_TEXT_IMMEDIATE_BLT::Tiling Enable */ #define GFX5_XY_TEXT_IMMEDIATE_BLT_TilingEnable_bits 1 #define GFX45_XY_TEXT_IMMEDIATE_BLT_TilingEnable_bits 1 #define GFX4_XY_TEXT_IMMEDIATE_BLT_TilingEnable_bits 1 static inline uint32_t ATTRIBUTE_PURE XY_TEXT_IMMEDIATE_BLT_TilingEnable_bits(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 1; case 45: return 1; case 40: return 1; default: unreachable("Invalid hardware generation"); } } #define GFX5_XY_TEXT_IMMEDIATE_BLT_TilingEnable_start 11 #define GFX45_XY_TEXT_IMMEDIATE_BLT_TilingEnable_start 11 #define GFX4_XY_TEXT_IMMEDIATE_BLT_TilingEnable_start 11 static inline uint32_t ATTRIBUTE_PURE XY_TEXT_IMMEDIATE_BLT_TilingEnable_start(const struct intel_device_info *devinfo) { switch (devinfo->verx10) { case 125: return 0; case 120: return 0; case 110: return 0; case 90: return 0; case 80: return 0; case 75: return 0; case 70: return 0; case 60: return 0; case 50: return 11; case 45: return 11; case 40: return 11; default: unreachable("Invalid hardware generation"); } } #ifdef __cplusplus } #endif #endif /* GENX_BITS_H */